diff -r 44b5c183c3cd -r 8e7da5c45d78 src/mem/cache/cache.cc --- a/src/mem/cache/cache.cc Mon Oct 12 04:08:01 2015 -0400 +++ b/src/mem/cache/cache.cc Tue Oct 13 17:49:05 2015 +0100 @@ -1190,7 +1190,6 @@ // Initial target is used just for stats MSHR::Target *initial_tgt = mshr->getTarget(); - CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure()); int stats_cmd_idx = initial_tgt->pkt->cmdToIndex(); Tick miss_latency = curTick() - initial_tgt->recvTime; PacketList writebacks; @@ -1212,16 +1211,18 @@ miss_latency; } + // upgrade deferred targets if possible + mshr->promoteIfExclusive(pkt); + bool is_fill = !mshr->isForward && (pkt->isRead() || pkt->cmd == MemCmd::UpgradeResp); + CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure()); + if (is_fill && !is_error) { DPRINTF(Cache, "Block for addr %#llx being updated in Cache\n", pkt->getAddr()); - // give mshr a chance to do some dirty work - mshr->handleFill(pkt, blk); - blk = handleFill(pkt, blk, writebacks); assert(blk != NULL); } @@ -1264,7 +1265,7 @@ assert(!is_error); // NB: we use the original packet here and not the response! - mshr->handleFill(tgt_pkt, blk); + mshr->promoteIfExclusive(tgt_pkt); blk = handleFill(tgt_pkt, blk, writebacks); assert(blk != NULL); diff -r 44b5c183c3cd -r 8e7da5c45d78 src/mem/cache/mshr.hh --- a/src/mem/cache/mshr.hh Mon Oct 12 04:08:01 2015 -0400 +++ b/src/mem/cache/mshr.hh Tue Oct 13 17:49:05 2015 +0100 @@ -282,7 +282,7 @@ bool promoteDeferredTargets(); - void handleFill(PacketPtr pkt, CacheBlk *blk); + void promoteIfExclusive(const PacketPtr pkt); bool checkFunctional(PacketPtr pkt); diff -r 44b5c183c3cd -r 8e7da5c45d78 src/mem/cache/mshr.cc --- a/src/mem/cache/mshr.cc Mon Oct 12 04:08:01 2015 -0400 +++ b/src/mem/cache/mshr.cc Tue Oct 13 17:49:05 2015 +0100 @@ -430,7 +430,7 @@ void -MSHR::handleFill(PacketPtr pkt, CacheBlk *blk) +MSHR::promoteIfExclusive(const PacketPtr pkt) { if (!pkt->sharedAsserted() && !(hasPostInvalidate() || hasPostDowngrade())