diff -r dd9708ed6940 -r 7efa6f630cd8 src/mem/cache/cache.cc --- a/src/mem/cache/cache.cc Mon Oct 19 15:18:48 2015 +0100 +++ b/src/mem/cache/cache.cc Mon Oct 19 15:20:40 2015 +0100 @@ -676,7 +676,7 @@ // lat, neglecting responseLatency, modelling hit latency // just as lookupLatency or or the value of lat overriden // by access(), that calls accessBlock() function. - cpuSidePort->schedTimingResp(pkt, request_time); + cpuSidePort->schedTimingResp(pkt, request_time, true); } else { /// @todo nominally we should just delete the packet here, /// however, until 4-phase stuff we can't because sending cache is @@ -734,7 +734,7 @@ std::memset(pkt->getPtr(), 0xFF, pkt->getSize()); // request_time is used here, taking into account lat and the delay // charged if the packet comes from the xbar. - cpuSidePort->schedTimingResp(pkt, request_time); + cpuSidePort->schedTimingResp(pkt, request_time, true); // If an outstanding request is in progress (we found an // MSHR) this is set to null @@ -1341,7 +1341,7 @@ } // Reset the bus additional time as it is now accounted for tgt_pkt->headerDelay = tgt_pkt->payloadDelay = 0; - cpuSidePort->schedTimingResp(tgt_pkt, completion_time); + cpuSidePort->schedTimingResp(tgt_pkt, completion_time, true); break; case MSHR::Target::FromPrefetcher: diff -r dd9708ed6940 -r 7efa6f630cd8 src/mem/qport.hh --- a/src/mem/qport.hh Mon Oct 19 15:18:48 2015 +0100 +++ b/src/mem/qport.hh Mon Oct 19 15:20:40 2015 +0100 @@ -88,8 +88,8 @@ * @param pkt Packet to send * @param when Absolute time (in ticks) to send packet */ - void schedTimingResp(PacketPtr pkt, Tick when) - { respQueue.schedSendTiming(pkt, when); } + void schedTimingResp(PacketPtr pkt, Tick when, bool force_order = false) + { respQueue.schedSendTiming(pkt, when, force_order); } /** Check the list of buffered packets against the supplied * functional request. */