diff --git a/src/mem/ruby/system/RubySystem.hh b/src/mem/ruby/system/RubySystem.hh --- a/src/mem/ruby/system/RubySystem.hh +++ b/src/mem/ruby/system/RubySystem.hh @@ -99,8 +99,8 @@ void drainResume() override; void process(); void startup() override; - bool functionalRead(Packet *ptr); - bool functionalWrite(Packet *ptr); + bool functionalRead(PacketPtr ptr); + bool functionalWrite(PacketPtr ptr); void registerNetwork(Network*); void registerAbstractController(AbstractController*); diff --git a/src/mem/ruby/network/simple/Switch.cc b/src/mem/ruby/network/simple/Switch.cc --- a/src/mem/ruby/network/simple/Switch.cc +++ b/src/mem/ruby/network/simple/Switch.cc @@ -169,13 +169,13 @@ } bool -Switch::functionalRead(Packet *pkt) +Switch::functionalRead(PacketPtr pkt) { return false; } uint32_t -Switch::functionalWrite(Packet *pkt) +Switch::functionalWrite(PacketPtr pkt) { // Access the buffers in the switch for performing a functional write uint32_t num_functional_writes = 0; diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh b/src/mem/ruby/slicc_interface/AbstractController.hh --- a/src/mem/ruby/slicc_interface/AbstractController.hh +++ b/src/mem/ruby/slicc_interface/AbstractController.hh @@ -88,12 +88,12 @@ //! These functions are used by ruby system to read/write the data blocks //! that exist with in the controller. - virtual void functionalRead(const Addr &addr, PacketPtr) = 0; + virtual void functionalRead(const Addr &addr, const PacketPtr &pkt) = 0; void functionalMemoryRead(PacketPtr); //! The return value indicates the number of messages written with the //! data from the packet. virtual int functionalWriteBuffers(PacketPtr&) = 0; - virtual int functionalWrite(const Addr &addr, PacketPtr) = 0; + virtual int functionalWrite(const Addr &addr, const PacketPtr &pkt) = 0; int functionalMemoryWrite(PacketPtr); //! Function for enqueuing a prefetch request diff --git a/src/mem/ruby/slicc_interface/Message.hh b/src/mem/ruby/slicc_interface/Message.hh --- a/src/mem/ruby/slicc_interface/Message.hh +++ b/src/mem/ruby/slicc_interface/Message.hh @@ -73,8 +73,8 @@ * class that can be potentially searched for the address needs to * implement these methods. */ - virtual bool functionalRead(Packet *pkt) = 0; - virtual bool functionalWrite(Packet *pkt) = 0; + virtual bool functionalRead(PacketPtr const& pkt) = 0; + virtual bool functionalWrite(PacketPtr const& pkt) = 0; //! Update the delay this message has experienced so far. void updateDelayedTicks(Tick curTime) diff --git a/src/mem/ruby/slicc_interface/RubyRequest.hh b/src/mem/ruby/slicc_interface/RubyRequest.hh --- a/src/mem/ruby/slicc_interface/RubyRequest.hh +++ b/src/mem/ruby/slicc_interface/RubyRequest.hh @@ -82,8 +82,8 @@ const PrefetchBit& getPrefetch() const { return m_Prefetch; } void print(std::ostream& out) const; - bool functionalRead(Packet *pkt); - bool functionalWrite(Packet *pkt); + bool functionalRead(PacketPtr const& pkt); + bool functionalWrite(PacketPtr const& pkt); }; inline std::ostream& diff --git a/src/mem/ruby/slicc_interface/RubyRequest.cc b/src/mem/ruby/slicc_interface/RubyRequest.cc --- a/src/mem/ruby/slicc_interface/RubyRequest.cc +++ b/src/mem/ruby/slicc_interface/RubyRequest.cc @@ -48,7 +48,7 @@ } bool -RubyRequest::functionalRead(Packet *pkt) +RubyRequest::functionalRead(PacketPtr const& pkt) { // This needs a little explanation. Initially I thought that this // message should be read. But the way the memtester works for now, @@ -58,7 +58,7 @@ } bool -RubyRequest::functionalWrite(Packet *pkt) +RubyRequest::functionalWrite(PacketPtr const& pkt) { // This needs a little explanation. I am not sure if this message // should be written. Essentially the question is how are writes diff --git a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh --- a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh +++ b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh @@ -75,54 +75,4 @@ return 1024; } -/** - * This function accepts an address, a data block and a packet. If the address - * range for the data block contains the address which the packet needs to - * read, then the data from the data block is written to the packet. True is - * returned if the data block was read, otherwise false is returned. - */ -inline bool -testAndRead(Addr addr, DataBlock& blk, Packet *pkt) -{ - Addr pktLineAddr = makeLineAddress(pkt->getAddr()); - Addr lineAddr = makeLineAddress(addr); - - if (pktLineAddr == lineAddr) { - uint8_t *data = pkt->getPtr(); - unsigned int size_in_bytes = pkt->getSize(); - unsigned startByte = pkt->getAddr() - lineAddr; - - for (unsigned i = 0; i < size_in_bytes; ++i) { - data[i] = blk.getByte(i + startByte); - } - return true; - } - return false; -} - -/** - * This function accepts an address, a data block and a packet. If the address - * range for the data block contains the address which the packet needs to - * write, then the data from the packet is written to the data block. True is - * returned if the data block was written, otherwise false is returned. - */ -inline bool -testAndWrite(Addr addr, DataBlock& blk, Packet *pkt) -{ - Addr pktLineAddr = makeLineAddress(pkt->getAddr()); - Addr lineAddr = makeLineAddress(addr); - - if (pktLineAddr == lineAddr) { - const uint8_t *data = pkt->getConstPtr(); - unsigned int size_in_bytes = pkt->getSize(); - unsigned startByte = pkt->getAddr() - lineAddr; - - for (unsigned i = 0; i < size_in_bytes; ++i) { - blk.setByte(i + startByte, data[i]); - } - return true; - } - return false; -} - #endif // __MEM_RUBY_SLICC_INTERFACE_RUBYSLICCUTIL_HH__ diff --git a/src/mem/ruby/structures/RubyMemoryControl.hh b/src/mem/ruby/structures/RubyMemoryControl.hh --- a/src/mem/ruby/structures/RubyMemoryControl.hh +++ b/src/mem/ruby/structures/RubyMemoryControl.hh @@ -87,8 +87,8 @@ int getRanksPerDimm() { return m_ranks_per_dimm; }; int getDimmsPerChannel() { return m_dimms_per_channel; } - bool functionalRead(Packet *pkt); - uint32_t functionalWrite(Packet *pkt); + bool functionalRead(PacketPtr pkt); + uint32_t functionalWrite(PacketPtr pkt); private: void enqueueToDirectory(MemoryNode *req, Cycles latency); diff --git a/src/mem/ruby/structures/RubyMemoryControl.cc b/src/mem/ruby/structures/RubyMemoryControl.cc --- a/src/mem/ruby/structures/RubyMemoryControl.cc +++ b/src/mem/ruby/structures/RubyMemoryControl.cc @@ -670,7 +670,7 @@ * being lists. */ bool -RubyMemoryControl::functionalRead(Packet *pkt) +RubyMemoryControl::functionalRead(PacketPtr pkt) { for (std::list::iterator it = m_input_queue.begin(); it != m_input_queue.end(); ++it) { @@ -711,7 +711,7 @@ * for debugging purposes. */ uint32_t -RubyMemoryControl::functionalWrite(Packet *pkt) +RubyMemoryControl::functionalWrite(PacketPtr pkt) { uint32_t num_functional_writes = 0; diff --git a/src/mem/ruby/system/CacheRecorder.cc b/src/mem/ruby/system/CacheRecorder.cc --- a/src/mem/ruby/system/CacheRecorder.cc +++ b/src/mem/ruby/system/CacheRecorder.cc @@ -88,7 +88,7 @@ m_block_size_bytes, 0, Request::funcMasterId); MemCmd::Command requestType = MemCmd::FlushReq; - Packet *pkt = new Packet(req, requestType); + PacketPtr pkt = new Packet(req, requestType); Sequencer* m_sequencer_ptr = m_seq_map[rec->m_cntrl_id]; assert(m_sequencer_ptr != NULL); @@ -129,7 +129,7 @@ RubySystem::getBlockSizeBytes(), 0, Request::funcMasterId); } - Packet *pkt = new Packet(req, requestType); + PacketPtr pkt = new Packet(req, requestType); pkt->dataStatic(traceRecord->m_data + rec_bytes_read); Sequencer* m_sequencer_ptr = m_seq_map[traceRecord->m_cntrl_id]; diff --git a/src/mem/ruby/network/simple/SimpleNetwork.cc b/src/mem/ruby/network/simple/SimpleNetwork.cc --- a/src/mem/ruby/network/simple/SimpleNetwork.cc +++ b/src/mem/ruby/network/simple/SimpleNetwork.cc @@ -181,7 +181,7 @@ * between different switches have buffers that need to be accessed. */ bool -SimpleNetwork::functionalRead(Packet *pkt) +SimpleNetwork::functionalRead(PacketPtr pkt) { for (unsigned int i = 0; i < m_switches.size(); i++) { if (m_switches[i]->functionalRead(pkt)) { @@ -193,7 +193,7 @@ } uint32_t -SimpleNetwork::functionalWrite(Packet *pkt) +SimpleNetwork::functionalWrite(PacketPtr pkt) { uint32_t num_functional_writes = 0; diff --git a/src/mem/ruby/network/simple/Switch.hh b/src/mem/ruby/network/simple/Switch.hh --- a/src/mem/ruby/network/simple/Switch.hh +++ b/src/mem/ruby/network/simple/Switch.hh @@ -78,8 +78,8 @@ void print(std::ostream& out) const; void init_net_ptr(SimpleNetwork* net_ptr) { m_network_ptr = net_ptr; } - bool functionalRead(Packet *); - uint32_t functionalWrite(Packet *); + bool functionalRead(PacketPtr); + uint32_t functionalWrite(PacketPtr); private: // Private copy constructor and assignment operator diff --git a/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc b/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc --- a/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc +++ b/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc @@ -342,7 +342,7 @@ } bool -NetworkInterface::functionalRead(Packet *pkt) +NetworkInterface::functionalRead(PacketPtr pkt) { // Go through the internal buffers for (unsigned int i = 0; i < m_ni_buffers.size(); ++i) { @@ -360,7 +360,7 @@ } uint32_t -NetworkInterface::functionalWrite(Packet *pkt) +NetworkInterface::functionalWrite(PacketPtr pkt) { uint32_t num_functional_writes = 0; for (unsigned int i = 0; i < m_ni_buffers.size(); ++i) { diff --git a/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.hh b/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.hh --- a/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.hh +++ b/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.hh @@ -74,8 +74,8 @@ unsigned int getLinkUtilization() const { return m_link_utilized; } const std::vector & getVcLoad() const { return m_vc_load; } - bool functionalRead(Packet *); - uint32_t functionalWrite(Packet *); + bool functionalRead(PacketPtr); + uint32_t functionalWrite(PacketPtr); private: int m_id; diff --git a/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.cc b/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.cc --- a/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.cc +++ b/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.cc @@ -133,13 +133,13 @@ } bool -NetworkLink::functionalRead(Packet *pkt) +NetworkLink::functionalRead(PacketPtr pkt) { return linkBuffer->functionalRead(pkt); } uint32_t -NetworkLink::functionalWrite(Packet *pkt) +NetworkLink::functionalWrite(PacketPtr pkt) { return linkBuffer->functionalWrite(pkt); } diff --git a/src/mem/ruby/network/garnet/flexible-pipeline/Router.hh b/src/mem/ruby/network/garnet/flexible-pipeline/Router.hh --- a/src/mem/ruby/network/garnet/flexible-pipeline/Router.hh +++ b/src/mem/ruby/network/garnet/flexible-pipeline/Router.hh @@ -73,8 +73,8 @@ m_net_ptr = net_ptr; } - bool functionalRead(Packet *); - uint32_t functionalWrite(Packet *); + bool functionalRead(PacketPtr); + uint32_t functionalWrite(PacketPtr); private: int m_virtual_networks, m_num_vcs, m_vc_per_vnet; diff --git a/src/mem/ruby/network/garnet/flexible-pipeline/Router.cc b/src/mem/ruby/network/garnet/flexible-pipeline/Router.cc --- a/src/mem/ruby/network/garnet/flexible-pipeline/Router.cc +++ b/src/mem/ruby/network/garnet/flexible-pipeline/Router.cc @@ -394,7 +394,7 @@ } bool -Router::functionalRead(Packet *pkt) +Router::functionalRead(PacketPtr pkt) { // Access the buffers in the router for performing a functional read for (unsigned int i = 0; i < m_router_buffers.size(); i++) { @@ -415,7 +415,7 @@ } uint32_t -Router::functionalWrite(Packet *pkt) +Router::functionalWrite(PacketPtr pkt) { uint32_t num_functional_writes = 0; diff --git a/src/mem/ruby/network/garnet/flexible-pipeline/flit.hh b/src/mem/ruby/network/garnet/flexible-pipeline/flit.hh --- a/src/mem/ruby/network/garnet/flexible-pipeline/flit.hh +++ b/src/mem/ruby/network/garnet/flexible-pipeline/flit.hh @@ -67,8 +67,8 @@ return (n1->get_time() > n2->get_time()); } - bool functionalRead(Packet *pkt); - bool functionalWrite(Packet *pkt); + bool functionalRead(PacketPtr pkt); + bool functionalWrite(PacketPtr pkt); private: const int m_id; diff --git a/src/mem/ruby/network/garnet/flexible-pipeline/flit.cc b/src/mem/ruby/network/garnet/flexible-pipeline/flit.cc --- a/src/mem/ruby/network/garnet/flexible-pipeline/flit.cc +++ b/src/mem/ruby/network/garnet/flexible-pipeline/flit.cc @@ -61,14 +61,14 @@ } bool -flit::functionalRead(Packet *pkt) +flit::functionalRead(PacketPtr pkt) { Message *msg = m_msg_ptr.get(); return msg->functionalRead(pkt); } bool -flit::functionalWrite(Packet *pkt) +flit::functionalWrite(PacketPtr pkt) { Message *msg = m_msg_ptr.get(); return msg->functionalWrite(pkt); diff --git a/src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.hh b/src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.hh --- a/src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.hh +++ b/src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.hh @@ -52,8 +52,8 @@ void insert(flit *flt); void print(std::ostream& out) const; - bool functionalRead(Packet *); - uint32_t functionalWrite(Packet *); + bool functionalRead(PacketPtr); + uint32_t functionalWrite(PacketPtr); private: std::vector m_buffer; diff --git a/src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.cc b/src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.cc --- a/src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.cc +++ b/src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.cc @@ -103,7 +103,7 @@ } bool -flitBuffer::functionalRead(Packet *pkt) +flitBuffer::functionalRead(PacketPtr pkt) { for (unsigned int i = 0; i < m_buffer.size(); ++i) { if (m_buffer[i]->functionalRead(pkt)) { @@ -114,7 +114,7 @@ } uint32_t -flitBuffer::functionalWrite(Packet *pkt) +flitBuffer::functionalWrite(PacketPtr pkt) { uint32_t num_functional_writes = 0; diff --git a/src/mem/ruby/network/simple/SimpleNetwork.hh b/src/mem/ruby/network/simple/SimpleNetwork.hh --- a/src/mem/ruby/network/simple/SimpleNetwork.hh +++ b/src/mem/ruby/network/simple/SimpleNetwork.hh @@ -71,8 +71,8 @@ void print(std::ostream& out) const; - bool functionalRead(Packet *pkt); - uint32_t functionalWrite(Packet *pkt); + bool functionalRead(PacketPtr pkt); + uint32_t functionalWrite(PacketPtr pkt); private: void addLink(SwitchID src, SwitchID dest, int link_latency); diff --git a/src/mem/protocol/MOESI_hammer-dir.sm b/src/mem/protocol/MOESI_hammer-dir.sm --- a/src/mem/protocol/MOESI_hammer-dir.sm +++ b/src/mem/protocol/MOESI_hammer-dir.sm @@ -270,22 +270,22 @@ getDirectoryEntry(addr).changePermission(Directory_State_to_permission(state)); } - void functionalRead(Addr addr, Packet *pkt) { + void functionalRead(Addr addr, PacketPtr pkt) { TBE tbe := TBEs[addr]; if(is_valid(tbe)) { - testAndRead(addr, tbe.DataBlk, pkt); + tbe.DataBlk.testAndRead(addr, pkt); } else { functionalMemoryRead(pkt); } } - int functionalWrite(Addr addr, Packet *pkt) { + int functionalWrite(Addr addr, PacketPtr pkt) { int num_functional_writes := 0; TBE tbe := TBEs[addr]; if(is_valid(tbe)) { num_functional_writes := num_functional_writes + - testAndWrite(addr, tbe.DataBlk, pkt); + tbe.DataBlk.testAndWrite(addr, pkt); } num_functional_writes := num_functional_writes + functionalMemoryWrite(pkt); diff --git a/src/mem/protocol/MOESI_hammer-dma.sm b/src/mem/protocol/MOESI_hammer-dma.sm --- a/src/mem/protocol/MOESI_hammer-dma.sm +++ b/src/mem/protocol/MOESI_hammer-dma.sm @@ -68,11 +68,11 @@ void setAccessPermission(Addr addr, State state) { } - void functionalRead(Addr addr, Packet *pkt) { + void functionalRead(Addr addr, PacketPtr pkt) { error("DMA does not support functional read."); } - int functionalWrite(Addr addr, Packet *pkt) { + int functionalWrite(Addr addr, PacketPtr pkt) { error("DMA does not support functional write."); } diff --git a/src/mem/protocol/MOESI_hammer-msg.sm b/src/mem/protocol/MOESI_hammer-msg.sm --- a/src/mem/protocol/MOESI_hammer-msg.sm +++ b/src/mem/protocol/MOESI_hammer-msg.sm @@ -74,12 +74,12 @@ Addr addr, desc="Physical address for this request"; TriggerType Type, desc="Type of trigger"; - bool functionalRead(Packet *pkt) { + bool functionalRead(PacketPtr pkt) { // Trigger messages do not hold any data! return false; } - bool functionalWrite(Packet *pkt) { + bool functionalWrite(PacketPtr pkt) { // Trigger messages do not hold any data! return false; } @@ -101,12 +101,12 @@ desc="time the dir forwarded the request"; int SilentAcks, default="0", desc="silent acks from the full-bit directory"; - bool functionalRead(Packet *pkt) { + bool functionalRead(PacketPtr pkt) { // Request messages do not hold any data return false; } - bool functionalWrite(Packet *pkt) { + bool functionalWrite(PacketPtr pkt) { // Request messages do not hold any data return false; } @@ -130,7 +130,7 @@ desc="time the dir forwarded the request"; int SilentAcks, default="0", desc="silent acks from the full-bit directory"; - bool functionalRead(Packet *pkt) { + bool functionalRead(PacketPtr pkt) { // The check below ensures that data is read only from messages that // actually hold data. if (Type == CoherenceResponseType:DATA || @@ -138,17 +138,17 @@ Type == CoherenceResponseType:DATA_EXCLUSIVE || Type == CoherenceResponseType:WB_DIRTY || Type == CoherenceResponseType:WB_EXCLUSIVE_DIRTY) { - return testAndRead(addr, DataBlk, pkt); + return DataBlk.testAndRead(addr, pkt); } return false; } - bool functionalWrite(Packet *pkt) { + bool functionalWrite(PacketPtr pkt) { // Message type does not matter since all messages are written. // If a protocol reads data from a packet that is not supposed // to hold the data, then the fault lies with the protocol. - return testAndWrite(addr, DataBlk, pkt); + return DataBlk.testAndWrite(addr, pkt); } } @@ -174,12 +174,12 @@ int Len, desc="The length of the request"; MessageSizeType MessageSize, desc="size category of the message"; - bool functionalRead(Packet *pkt) { - return testAndRead(LineAddress, DataBlk, pkt); + bool functionalRead(PacketPtr pkt) { + return DataBlk.testAndRead(LineAddress, pkt); } - bool functionalWrite(Packet *pkt) { - return testAndWrite(LineAddress, DataBlk, pkt); + bool functionalWrite(PacketPtr pkt) { + return DataBlk.testAndWrite(LineAddress, pkt); } } @@ -191,11 +191,11 @@ DataBlock DataBlk, desc="DataBlk attached to this request"; MessageSizeType MessageSize, desc="size category of the message"; - bool functionalRead(Packet *pkt) { - return testAndRead(LineAddress, DataBlk, pkt); + bool functionalRead(PacketPtr pkt) { + return DataBlk.testAndRead(LineAddress, pkt); } - bool functionalWrite(Packet *pkt) { - return testAndWrite(LineAddress, DataBlk, pkt); + bool functionalWrite(PacketPtr pkt) { + return DataBlk.testAndWrite(LineAddress, pkt); } } diff --git a/src/mem/protocol/Network_test-cache.sm b/src/mem/protocol/Network_test-cache.sm --- a/src/mem/protocol/Network_test-cache.sm +++ b/src/mem/protocol/Network_test-cache.sm @@ -114,11 +114,11 @@ return OOD; } - void functionalRead(Addr addr, Packet *pkt) { + void functionalRead(Addr addr, PacketPtr pkt) { error("Network test does not support functional read."); } - int functionalWrite(Addr addr, Packet *pkt) { + int functionalWrite(Addr addr, PacketPtr pkt) { error("Network test does not support functional write."); } diff --git a/src/mem/protocol/Network_test-dir.sm b/src/mem/protocol/Network_test-dir.sm --- a/src/mem/protocol/Network_test-dir.sm +++ b/src/mem/protocol/Network_test-dir.sm @@ -78,11 +78,11 @@ void setAccessPermission(Addr addr, State state) { } - void functionalRead(Addr addr, Packet *pkt) { + void functionalRead(Addr addr, PacketPtr pkt) { error("Network test does not support functional read."); } - int functionalWrite(Addr addr, Packet *pkt) { + int functionalWrite(Addr addr, PacketPtr pkt) { error("Network test does not support functional write."); } diff --git a/src/mem/protocol/Network_test-msg.sm b/src/mem/protocol/Network_test-msg.sm --- a/src/mem/protocol/Network_test-msg.sm +++ b/src/mem/protocol/Network_test-msg.sm @@ -41,11 +41,11 @@ DataBlock DataBlk, desc="data for the cache line"; MessageSizeType MessageSize, desc="size category of the message"; - bool functionalRead(Packet *pkt) { + bool functionalRead(PacketPtr pkt) { error("Network test does not support functional accesses!"); } - bool functionalWrite(Packet *pkt) { + bool functionalWrite(PacketPtr pkt) { error("Network test does not support functional accesses!"); } } diff --git a/src/mem/protocol/RubySlicc_Defines.sm b/src/mem/protocol/RubySlicc_Defines.sm --- a/src/mem/protocol/RubySlicc_Defines.sm +++ b/src/mem/protocol/RubySlicc_Defines.sm @@ -44,5 +44,5 @@ // Functions implemented in the AbstractController class for // making functional access to the memory maintained by the // memory controllers. -void functionalMemoryRead(Packet *pkt); -bool functionalMemoryWrite(Packet *pkt); +void functionalMemoryRead(PacketPtr pkt); +bool functionalMemoryWrite(PacketPtr pkt); diff --git a/src/mem/protocol/RubySlicc_Exports.sm b/src/mem/protocol/RubySlicc_Exports.sm --- a/src/mem/protocol/RubySlicc_Exports.sm +++ b/src/mem/protocol/RubySlicc_Exports.sm @@ -42,11 +42,10 @@ structure(DataBlock, external = "yes", desc="..."){ void clear(); void copyPartial(DataBlock, int, int); + bool testAndRead(Addr, PacketPtr); + bool testAndWrite(Addr, PacketPtr); } -bool testAndRead(Addr addr, DataBlock datablk, Packet *pkt); -bool testAndWrite(Addr addr, DataBlock datablk, Packet *pkt); - // AccessPermission // The following five states define the access permission of all memory blocks. // These permissions have multiple uses. They coordinate locking and @@ -226,12 +225,12 @@ PrefetchBit Prefetch, desc="Is this a prefetch request"; MessageSizeType MessageSize; - bool functionalRead(Packet *pkt) { - return testAndRead(PhysicalAddress, DataBlk, pkt); + bool functionalRead(PacketPtr pkt) { + return DataBlk.testAndRead(PhysicalAddress, pkt); } - bool functionalWrite(Packet *pkt) { - return testAndWrite(PhysicalAddress, DataBlk, pkt); + bool functionalWrite(PacketPtr pkt) { + return DataBlk.testAndWrite(PhysicalAddress, pkt); } } diff --git a/src/mem/protocol/RubySlicc_MemControl.sm b/src/mem/protocol/RubySlicc_MemControl.sm --- a/src/mem/protocol/RubySlicc_MemControl.sm +++ b/src/mem/protocol/RubySlicc_MemControl.sm @@ -62,11 +62,11 @@ bool ReadX, desc="Exclusive"; int Acks, desc="How many acks to expect"; - bool functionalRead(Packet *pkt) { - return testAndRead(addr, DataBlk, pkt); + bool functionalRead(PacketPtr pkt) { + return DataBlk.testAndRead(addr, pkt); } - bool functionalWrite(Packet *pkt) { - return testAndWrite(addr, DataBlk, pkt); + bool functionalWrite(PacketPtr pkt) { + return DataBlk.testAndWrite(addr, pkt); } } diff --git a/src/mem/ruby/common/DataBlock.hh b/src/mem/ruby/common/DataBlock.hh --- a/src/mem/ruby/common/DataBlock.hh +++ b/src/mem/ruby/common/DataBlock.hh @@ -35,6 +35,8 @@ #include #include +#include "mem/packet.hh" + class DataBlock { public: @@ -63,6 +65,8 @@ void copyPartial(const DataBlock & dblk, int offset, int len); bool equal(const DataBlock& obj) const; void print(std::ostream& out) const; + bool testAndRead(Addr addr, PacketPtr pkt); + bool testAndWrite(Addr addr, PacketPtr pkt); private: void alloc(); diff --git a/src/mem/ruby/common/DataBlock.cc b/src/mem/ruby/common/DataBlock.cc --- a/src/mem/ruby/common/DataBlock.cc +++ b/src/mem/ruby/common/DataBlock.cc @@ -27,6 +27,8 @@ */ #include "mem/ruby/common/DataBlock.hh" + +#include "mem/packet.hh" #include "mem/ruby/system/RubySystem.hh" DataBlock::DataBlock(const DataBlock &cp) @@ -90,3 +92,42 @@ memcpy(m_data, obj.m_data, RubySystem::getBlockSizeBytes()); return *this; } + +bool +DataBlock::testAndRead(Addr addr, PacketPtr pkt) +{ + Addr pktLineAddr = makeLineAddress(pkt->getAddr()); + Addr lineAddr = makeLineAddress(addr); + + if (pktLineAddr == lineAddr) { + uint8_t *data = pkt->getPtr(); + unsigned size_in_bytes = pkt->getSize(); + unsigned startByte = pkt->getAddr() - lineAddr; + + for (unsigned i = 0; i < size_in_bytes; ++i) { + data[i] = getByte(i + startByte); + } + return true; + } + return false; +} + +bool +DataBlock::testAndWrite(Addr addr, PacketPtr pkt) +{ + Addr pktLineAddr = makeLineAddress(pkt->getAddr()); + Addr lineAddr = makeLineAddress(addr); + + if (pktLineAddr == lineAddr) { + const uint8_t *data = pkt->getConstPtr(); + unsigned size_in_bytes = pkt->getSize(); + unsigned startByte = pkt->getAddr() - lineAddr; + + for (unsigned i = 0; i < size_in_bytes; ++i) { + setByte(i + startByte, data[i]); + } + return true; + } + return false; +} + diff --git a/src/mem/ruby/network/MessageBuffer.hh b/src/mem/ruby/network/MessageBuffer.hh --- a/src/mem/ruby/network/MessageBuffer.hh +++ b/src/mem/ruby/network/MessageBuffer.hh @@ -120,7 +120,7 @@ // to be updated with the data from the packet. // Return value indicates the number of messages that were updated. // This required for debugging the code. - uint32_t functionalWrite(Packet *pkt); + uint32_t functionalWrite(PacketPtr pkt); private: void reanalyzeList(std::list &, Tick); diff --git a/src/mem/ruby/network/MessageBuffer.cc b/src/mem/ruby/network/MessageBuffer.cc --- a/src/mem/ruby/network/MessageBuffer.cc +++ b/src/mem/ruby/network/MessageBuffer.cc @@ -351,7 +351,7 @@ } uint32_t -MessageBuffer::functionalWrite(Packet *pkt) +MessageBuffer::functionalWrite(PacketPtr pkt) { uint32_t num_functional_writes = 0; diff --git a/src/mem/ruby/network/Network.hh b/src/mem/ruby/network/Network.hh --- a/src/mem/ruby/network/Network.hh +++ b/src/mem/ruby/network/Network.hh @@ -98,9 +98,9 @@ * the network. Each network needs to implement these for functional * accesses to work correctly. */ - virtual bool functionalRead(Packet *pkt) + virtual bool functionalRead(PacketPtr pkt) { fatal("Functional read not implemented.\n"); } - virtual uint32_t functionalWrite(Packet *pkt) + virtual uint32_t functionalWrite(PacketPtr pkt) { fatal("Functional write not implemented.\n"); } protected: diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.hh b/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.hh --- a/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.hh +++ b/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.hh @@ -81,7 +81,7 @@ //! Function for performing a functional write. The return value //! indicates the number of messages that were written. - uint32_t functionalWrite(Packet *pkt); + uint32_t functionalWrite(PacketPtr pkt); private: GarnetNetwork_d(const GarnetNetwork_d& obj); diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc b/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc --- a/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc +++ b/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc @@ -241,7 +241,7 @@ } uint32_t -GarnetNetwork_d::functionalWrite(Packet *pkt) +GarnetNetwork_d::functionalWrite(PacketPtr pkt) { uint32_t num_functional_writes = 0; diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.hh b/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.hh --- a/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.hh +++ b/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.hh @@ -158,7 +158,7 @@ double get_buf_write_count(unsigned int vnet) const { return m_num_buffer_writes[vnet]; } - uint32_t functionalWrite(Packet *pkt); + uint32_t functionalWrite(PacketPtr pkt); void resetStats(); private: diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.cc b/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.cc --- a/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.cc +++ b/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.cc @@ -102,7 +102,7 @@ } uint32_t -InputUnit_d::functionalWrite(Packet *pkt) +InputUnit_d::functionalWrite(PacketPtr pkt) { uint32_t num_functional_writes = 0; for (int i=0; i < m_num_vcs; i++) { diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.hh b/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.hh --- a/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.hh +++ b/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.hh @@ -66,7 +66,7 @@ int get_vnet(int vc); void init_net_ptr(GarnetNetwork_d *net_ptr) { m_net_ptr = net_ptr; } - uint32_t functionalWrite(Packet *); + uint32_t functionalWrite(PacketPtr); private: GarnetNetwork_d *m_net_ptr; diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc b/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc --- a/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc +++ b/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc @@ -375,7 +375,7 @@ } uint32_t -NetworkInterface_d::functionalWrite(Packet *pkt) +NetworkInterface_d::functionalWrite(PacketPtr pkt) { uint32_t num_functional_writes = 0; for (unsigned int i = 0; i < m_num_vcs; ++i) { diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.hh b/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.hh --- a/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.hh +++ b/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.hh @@ -64,7 +64,7 @@ inline flit_d* peekLink() { return linkBuffer->peekTopFlit(); } inline flit_d* consumeLink() { return linkBuffer->getTopFlit(); } - uint32_t functionalWrite(Packet *); + uint32_t functionalWrite(PacketPtr); private: const int m_id; diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.cc b/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.cc --- a/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.cc +++ b/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.cc @@ -83,7 +83,7 @@ } uint32_t -NetworkLink_d::functionalWrite(Packet *pkt) +NetworkLink_d::functionalWrite(PacketPtr pkt) { return linkBuffer->functionalWrite(pkt); } diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.hh b/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.hh --- a/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.hh +++ b/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.hh @@ -86,7 +86,7 @@ m_out_link->scheduleEventAbsolute(m_router->clockEdge(Cycles(1))); } - uint32_t functionalWrite(Packet *pkt); + uint32_t functionalWrite(PacketPtr pkt); private: int m_id; diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.cc b/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.cc --- a/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.cc +++ b/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.cc @@ -110,7 +110,7 @@ } uint32_t -OutputUnit_d::functionalWrite(Packet *pkt) +OutputUnit_d::functionalWrite(PacketPtr pkt) { return m_out_buffer->functionalWrite(pkt); } diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.hh b/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.hh --- a/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.hh +++ b/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.hh @@ -105,7 +105,7 @@ aggregate_fault_prob); } - uint32_t functionalWrite(Packet *); + uint32_t functionalWrite(PacketPtr); private: int m_virtual_networks, m_num_vcs, m_vc_per_vnet; diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc b/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc --- a/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc +++ b/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc @@ -252,7 +252,7 @@ } uint32_t -Router_d::functionalWrite(Packet *pkt) +Router_d::functionalWrite(PacketPtr pkt) { uint32_t num_functional_writes = 0; num_functional_writes += m_switch->functionalWrite(pkt); diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.hh b/src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.hh --- a/src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.hh +++ b/src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.hh @@ -56,7 +56,7 @@ inline double get_crossbar_count() { return m_crossbar_activity; } - uint32_t functionalWrite(Packet *pkt); + uint32_t functionalWrite(PacketPtr pkt); private: int m_num_vcs; diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.cc b/src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.cc --- a/src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.cc +++ b/src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.cc @@ -99,7 +99,7 @@ } uint32_t -Switch_d::functionalWrite(Packet *pkt) +Switch_d::functionalWrite(PacketPtr pkt) { uint32_t num_functional_writes = 0; diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/VirtualChannel_d.hh b/src/mem/ruby/network/garnet/fixed-pipeline/VirtualChannel_d.hh --- a/src/mem/ruby/network/garnet/fixed-pipeline/VirtualChannel_d.hh +++ b/src/mem/ruby/network/garnet/fixed-pipeline/VirtualChannel_d.hh @@ -85,7 +85,7 @@ return m_input_buffer->getTopFlit(); } - uint32_t functionalWrite(Packet *pkt); + uint32_t functionalWrite(PacketPtr pkt); private: int m_id; diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/VirtualChannel_d.cc b/src/mem/ruby/network/garnet/fixed-pipeline/VirtualChannel_d.cc --- a/src/mem/ruby/network/garnet/fixed-pipeline/VirtualChannel_d.cc +++ b/src/mem/ruby/network/garnet/fixed-pipeline/VirtualChannel_d.cc @@ -74,7 +74,7 @@ } uint32_t -VirtualChannel_d::functionalWrite(Packet *pkt) +VirtualChannel_d::functionalWrite(PacketPtr pkt) { return m_input_buffer->functionalWrite(pkt); } diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/flitBuffer_d.hh b/src/mem/ruby/network/garnet/fixed-pipeline/flitBuffer_d.hh --- a/src/mem/ruby/network/garnet/fixed-pipeline/flitBuffer_d.hh +++ b/src/mem/ruby/network/garnet/fixed-pipeline/flitBuffer_d.hh @@ -72,7 +72,7 @@ std::push_heap(m_buffer.begin(), m_buffer.end(), flit_d::greater); } - uint32_t functionalWrite(Packet *pkt); + uint32_t functionalWrite(PacketPtr pkt); private: std::vector m_buffer; diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/flitBuffer_d.cc b/src/mem/ruby/network/garnet/fixed-pipeline/flitBuffer_d.cc --- a/src/mem/ruby/network/garnet/fixed-pipeline/flitBuffer_d.cc +++ b/src/mem/ruby/network/garnet/fixed-pipeline/flitBuffer_d.cc @@ -76,7 +76,7 @@ } uint32_t -flitBuffer_d::functionalWrite(Packet *pkt) +flitBuffer_d::functionalWrite(PacketPtr pkt) { uint32_t num_functional_writes = 0; diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/flit_d.hh b/src/mem/ruby/network/garnet/fixed-pipeline/flit_d.hh --- a/src/mem/ruby/network/garnet/fixed-pipeline/flit_d.hh +++ b/src/mem/ruby/network/garnet/fixed-pipeline/flit_d.hh @@ -88,7 +88,7 @@ } } - bool functionalWrite(Packet *pkt); + bool functionalWrite(PacketPtr pkt); private: int m_id; diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/flit_d.cc b/src/mem/ruby/network/garnet/fixed-pipeline/flit_d.cc --- a/src/mem/ruby/network/garnet/fixed-pipeline/flit_d.cc +++ b/src/mem/ruby/network/garnet/fixed-pipeline/flit_d.cc @@ -76,7 +76,7 @@ } bool -flit_d::functionalWrite(Packet *pkt) +flit_d::functionalWrite(PacketPtr pkt) { Message *msg = m_msg_ptr.get(); return msg->functionalWrite(pkt); diff --git a/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.hh b/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.hh --- a/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.hh +++ b/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.hh @@ -72,11 +72,11 @@ //! Function for performing a functional read. The return value //! indicates if a message was found that had the required address. - bool functionalRead(Packet *pkt); + bool functionalRead(PacketPtr pkt); //! Function for performing a functional write. The return value //! indicates the number of messages that were written. - uint32_t functionalWrite(Packet *pkt); + uint32_t functionalWrite(PacketPtr pkt); private: GarnetNetwork(const GarnetNetwork& obj); diff --git a/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc b/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc --- a/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc +++ b/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc @@ -148,7 +148,7 @@ * links for reading/writing all the messages. */ bool -GarnetNetwork::functionalRead(Packet *pkt) +GarnetNetwork::functionalRead(PacketPtr pkt) { for (unsigned int i = 0; i < m_routers.size(); i++) { if (m_routers[i]->functionalRead(pkt)) { @@ -172,7 +172,7 @@ } uint32_t -GarnetNetwork::functionalWrite(Packet *pkt) +GarnetNetwork::functionalWrite(PacketPtr pkt) { uint32_t num_functional_writes = 0; diff --git a/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.hh b/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.hh --- a/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.hh +++ b/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.hh @@ -68,8 +68,8 @@ void print(std::ostream& out) const; - bool functionalRead(Packet *); - uint32_t functionalWrite(Packet *); + bool functionalRead(PacketPtr); + uint32_t functionalWrite(PacketPtr); void init_net_ptr(GarnetNetwork* net_ptr) { m_net_ptr = net_ptr; } # Node ID 7910391ba27673b8203458979f3eb9061533dd45 # Parent 325e2b732bd00ee216cabbf7c87ff7f59044125d diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc --- a/src/mem/cache/cache.cc +++ b/src/mem/cache/cache.cc @@ -579,7 +579,7 @@ // create a downstream express snoop with cleared packet // flags, there is no need to allocate any data as the // packet is merely used to co-ordinate state transitions - Packet *snoop_pkt = new Packet(pkt, true, false); + PacketPtr snoop_pkt = new Packet(pkt, true, false); // also reset the bus time that the original packet has // not yet paid for @@ -1235,7 +1235,7 @@ while (mshr->hasTargets()) { MSHR::Target *target = mshr->getTarget(); - Packet *tgt_pkt = target->pkt; + PacketPtr tgt_pkt = target->pkt; switch (target->source) { case MSHR::Target::FromCPU: diff --git a/src/mem/packet.hh b/src/mem/packet.hh --- a/src/mem/packet.hh +++ b/src/mem/packet.hh @@ -529,7 +529,7 @@ cmd = MemCmd::BadAddressError; } - void copyError(Packet *pkt) { assert(pkt->isError()); cmd = pkt->cmd; } + void copyError(PacketPtr pkt) { assert(pkt->isError()); cmd = pkt->cmd; } Addr getAddr() const { assert(flags.isSet(VALID_ADDR)); return addr; } /** diff --git a/src/mem/protocol/MESI_Three_Level-L0cache.sm b/src/mem/protocol/MESI_Three_Level-L0cache.sm --- a/src/mem/protocol/MESI_Three_Level-L0cache.sm +++ b/src/mem/protocol/MESI_Three_Level-L0cache.sm @@ -207,27 +207,27 @@ return AccessPermission:NotPresent; } - void functionalRead(Addr addr, Packet *pkt) { + void functionalRead(Addr addr, PacketPtr pkt) { TBE tbe := TBEs[addr]; if(is_valid(tbe)) { - testAndRead(addr, tbe.DataBlk, pkt); + tbe.DataBlk.testAndRead(addr, pkt); } else { - testAndRead(addr, getCacheEntry(addr).DataBlk, pkt); + getCacheEntry(addr).DataBlk.testAndRead(addr, pkt); } } - int functionalWrite(Addr addr, Packet *pkt) { + int functionalWrite(Addr addr, PacketPtr pkt) { int num_functional_writes := 0; TBE tbe := TBEs[addr]; if(is_valid(tbe)) { num_functional_writes := num_functional_writes + - testAndWrite(addr, tbe.DataBlk, pkt); + tbe.DataBlk.testAndWrite(addr, pkt); return num_functional_writes; } num_functional_writes := num_functional_writes + - testAndWrite(addr, getCacheEntry(addr).DataBlk, pkt); + getCacheEntry(addr).DataBlk.testAndWrite(addr, pkt); return num_functional_writes; } diff --git a/src/mem/protocol/MESI_Three_Level-L1cache.sm b/src/mem/protocol/MESI_Three_Level-L1cache.sm --- a/src/mem/protocol/MESI_Three_Level-L1cache.sm +++ b/src/mem/protocol/MESI_Three_Level-L1cache.sm @@ -204,27 +204,27 @@ return AccessPermission:NotPresent; } - void functionalRead(Addr addr, Packet *pkt) { + void functionalRead(Addr addr, PacketPtr pkt) { TBE tbe := TBEs[addr]; if(is_valid(tbe)) { - testAndRead(addr, tbe.DataBlk, pkt); + tbe.DataBlk.testAndRead(addr, pkt); } else { - testAndRead(addr, getCacheEntry(addr).DataBlk, pkt); + getCacheEntry(addr).DataBlk.testAndRead(addr, pkt); } } - int functionalWrite(Addr addr, Packet *pkt) { + int functionalWrite(Addr addr, PacketPtr pkt) { int num_functional_writes := 0; TBE tbe := TBEs[addr]; if(is_valid(tbe)) { num_functional_writes := num_functional_writes + - testAndWrite(addr, tbe.DataBlk, pkt); + tbe.DataBlk.testAndWrite(addr, pkt); return num_functional_writes; } num_functional_writes := num_functional_writes + - testAndWrite(addr, getCacheEntry(addr).DataBlk, pkt); + getCacheEntry(addr).DataBlk.testAndWrite(addr, pkt); return num_functional_writes; } diff --git a/src/mem/protocol/MESI_Three_Level-msg.sm b/src/mem/protocol/MESI_Three_Level-msg.sm --- a/src/mem/protocol/MESI_Three_Level-msg.sm +++ b/src/mem/protocol/MESI_Three_Level-msg.sm @@ -59,18 +59,18 @@ DataBlock DataBlk, desc="Data for the cache line (if PUTX)"; bool Dirty, default="false", desc="Dirty bit"; - bool functionalRead(Packet *pkt) { + bool functionalRead(PacketPtr pkt) { // Only PUTX messages contains the data block if (Class == CoherenceClass:PUTX) { - return testAndRead(addr, DataBlk, pkt); + return DataBlk.testAndRead(addr, pkt); } return false; } - bool functionalWrite(Packet *pkt) { + bool functionalWrite(PacketPtr pkt) { // No check on message type required since the protocol should // read data from those messages that contain the block - return testAndWrite(addr, DataBlk, pkt); + return DataBlk.testAndWrite(addr, pkt); } } diff --git a/src/mem/protocol/MESI_Two_Level-L1cache.sm b/src/mem/protocol/MESI_Two_Level-L1cache.sm --- a/src/mem/protocol/MESI_Two_Level-L1cache.sm +++ b/src/mem/protocol/MESI_Two_Level-L1cache.sm @@ -227,27 +227,27 @@ return AccessPermission:NotPresent; } - void functionalRead(Addr addr, Packet *pkt) { + void functionalRead(Addr addr, PacketPtr pkt) { TBE tbe := TBEs[addr]; if(is_valid(tbe)) { - testAndRead(addr, tbe.DataBlk, pkt); + tbe.DataBlk.testAndRead(addr, pkt); } else { - testAndRead(addr, getCacheEntry(addr).DataBlk, pkt); + getCacheEntry(addr).DataBlk.testAndRead(addr, pkt); } } - int functionalWrite(Addr addr, Packet *pkt) { + int functionalWrite(Addr addr, PacketPtr pkt) { int num_functional_writes := 0; TBE tbe := TBEs[addr]; if(is_valid(tbe)) { num_functional_writes := num_functional_writes + - testAndWrite(addr, tbe.DataBlk, pkt); + tbe.DataBlk.testAndWrite(addr, pkt); return num_functional_writes; } num_functional_writes := num_functional_writes + - testAndWrite(addr, getCacheEntry(addr).DataBlk, pkt); + getCacheEntry(addr).DataBlk.testAndWrite(addr, pkt); return num_functional_writes; } diff --git a/src/mem/protocol/MESI_Two_Level-L2cache.sm b/src/mem/protocol/MESI_Two_Level-L2cache.sm --- a/src/mem/protocol/MESI_Two_Level-L2cache.sm +++ b/src/mem/protocol/MESI_Two_Level-L2cache.sm @@ -216,27 +216,27 @@ return AccessPermission:NotPresent; } - void functionalRead(Addr addr, Packet *pkt) { + void functionalRead(Addr addr, PacketPtr pkt) { TBE tbe := TBEs[addr]; if(is_valid(tbe)) { - testAndRead(addr, tbe.DataBlk, pkt); + tbe.DataBlk.testAndRead(addr, pkt); } else { - testAndRead(addr, getCacheEntry(addr).DataBlk, pkt); + getCacheEntry(addr).DataBlk.testAndRead(addr, pkt); } } - int functionalWrite(Addr addr, Packet *pkt) { + int functionalWrite(Addr addr, PacketPtr pkt) { int num_functional_writes := 0; TBE tbe := TBEs[addr]; if(is_valid(tbe)) { num_functional_writes := num_functional_writes + - testAndWrite(addr, tbe.DataBlk, pkt); + tbe.DataBlk.testAndWrite(addr, pkt); return num_functional_writes; } num_functional_writes := num_functional_writes + - testAndWrite(addr, getCacheEntry(addr).DataBlk, pkt); + getCacheEntry(addr).DataBlk.testAndWrite(addr, pkt); return num_functional_writes; } diff --git a/src/mem/protocol/MESI_Two_Level-dir.sm b/src/mem/protocol/MESI_Two_Level-dir.sm --- a/src/mem/protocol/MESI_Two_Level-dir.sm +++ b/src/mem/protocol/MESI_Two_Level-dir.sm @@ -90,8 +90,8 @@ void allocate(Addr); void deallocate(Addr); bool isPresent(Addr); - bool functionalRead(Packet *pkt); - int functionalWrite(Packet *pkt); + bool functionalRead(PacketPtr pkt); + int functionalWrite(PacketPtr pkt); } @@ -152,22 +152,22 @@ return AccessPermission:NotPresent; } - void functionalRead(Addr addr, Packet *pkt) { + void functionalRead(Addr addr, PacketPtr pkt) { TBE tbe := TBEs[addr]; if(is_valid(tbe)) { - testAndRead(addr, tbe.DataBlk, pkt); + tbe.DataBlk.testAndRead(addr, pkt); } else { functionalMemoryRead(pkt); } } - int functionalWrite(Addr addr, Packet *pkt) { + int functionalWrite(Addr addr, PacketPtr pkt) { int num_functional_writes := 0; TBE tbe := TBEs[addr]; if(is_valid(tbe)) { num_functional_writes := num_functional_writes + - testAndWrite(addr, tbe.DataBlk, pkt); + tbe.DataBlk.testAndWrite(addr, pkt); } num_functional_writes := num_functional_writes + functionalMemoryWrite(pkt); diff --git a/src/mem/protocol/MESI_Two_Level-dma.sm b/src/mem/protocol/MESI_Two_Level-dma.sm --- a/src/mem/protocol/MESI_Two_Level-dma.sm +++ b/src/mem/protocol/MESI_Two_Level-dma.sm @@ -68,11 +68,11 @@ void setAccessPermission(Addr addr, State state) { } - void functionalRead(Addr addr, Packet *pkt) { + void functionalRead(Addr addr, PacketPtr pkt) { error("DMA does not support functional read."); } - int functionalWrite(Addr addr, Packet *pkt) { + int functionalWrite(Addr addr, PacketPtr pkt) { error("DMA does not support functional write."); } diff --git a/src/mem/protocol/MESI_Two_Level-msg.sm b/src/mem/protocol/MESI_Two_Level-msg.sm --- a/src/mem/protocol/MESI_Two_Level-msg.sm +++ b/src/mem/protocol/MESI_Two_Level-msg.sm @@ -69,19 +69,19 @@ bool Dirty, default="false", desc="Dirty bit"; PrefetchBit Prefetch, desc="Is this a prefetch request"; - bool functionalRead(Packet *pkt) { + bool functionalRead(PacketPtr pkt) { // Only PUTX messages contains the data block if (Type == CoherenceRequestType:PUTX) { - return testAndRead(addr, DataBlk, pkt); + return DataBlk.testAndRead(addr, pkt); } return false; } - bool functionalWrite(Packet *pkt) { + bool functionalWrite(PacketPtr pkt) { // No check on message type required since the protocol should // read data from those messages that contain the block - return testAndWrite(addr, DataBlk, pkt); + return DataBlk.testAndWrite(addr, pkt); } } @@ -96,21 +96,21 @@ int AckCount, default="0", desc="number of acks in this message"; MessageSizeType MessageSize, desc="size category of the message"; - bool functionalRead(Packet *pkt) { + bool functionalRead(PacketPtr pkt) { // Valid data block is only present in message with following types if (Type == CoherenceResponseType:DATA || Type == CoherenceResponseType:DATA_EXCLUSIVE || Type == CoherenceResponseType:MEMORY_DATA) { - return testAndRead(addr, DataBlk, pkt); + return DataBlk.testAndRead(addr, pkt); } return false; } - bool functionalWrite(Packet *pkt) { + bool functionalWrite(PacketPtr pkt) { // No check on message type required since the protocol should // read data from those messages that contain the block - return testAndWrite(addr, DataBlk, pkt); + return DataBlk.testAndWrite(addr, pkt); } } diff --git a/src/mem/protocol/MI_example-cache.sm b/src/mem/protocol/MI_example-cache.sm --- a/src/mem/protocol/MI_example-cache.sm +++ b/src/mem/protocol/MI_example-cache.sm @@ -172,27 +172,27 @@ } } - void functionalRead(Addr addr, Packet *pkt) { + void functionalRead(Addr addr, PacketPtr pkt) { TBE tbe := TBEs[addr]; if(is_valid(tbe)) { - testAndRead(addr, tbe.DataBlk, pkt); + tbe.DataBlk.testAndRead(addr, pkt); } else { - testAndRead(addr, getCacheEntry(addr).DataBlk, pkt); + getCacheEntry(addr).DataBlk.testAndRead(addr, pkt); } } - int functionalWrite(Addr addr, Packet *pkt) { + int functionalWrite(Addr addr, PacketPtr pkt) { int num_functional_writes := 0; TBE tbe := TBEs[addr]; if(is_valid(tbe)) { num_functional_writes := num_functional_writes + - testAndWrite(addr, tbe.DataBlk, pkt); + tbe.DataBlk.testAndWrite(addr, pkt); return num_functional_writes; } num_functional_writes := num_functional_writes + - testAndWrite(addr, getCacheEntry(addr).DataBlk, pkt); + getCacheEntry(addr).DataBlk.testAndWrite(addr, pkt); return num_functional_writes; } diff --git a/src/mem/protocol/MI_example-dir.sm b/src/mem/protocol/MI_example-dir.sm --- a/src/mem/protocol/MI_example-dir.sm +++ b/src/mem/protocol/MI_example-dir.sm @@ -177,22 +177,22 @@ } } - void functionalRead(Addr addr, Packet *pkt) { + void functionalRead(Addr addr, PacketPtr pkt) { TBE tbe := TBEs[addr]; if(is_valid(tbe)) { - testAndRead(addr, tbe.DataBlk, pkt); + tbe.DataBlk.testAndRead(addr, pkt); } else { functionalMemoryRead(pkt); } } - int functionalWrite(Addr addr, Packet *pkt) { + int functionalWrite(Addr addr, PacketPtr pkt) { int num_functional_writes := 0; TBE tbe := TBEs[addr]; if(is_valid(tbe)) { num_functional_writes := num_functional_writes + - testAndWrite(addr, tbe.DataBlk, pkt); + tbe.DataBlk.testAndWrite(addr, pkt); } num_functional_writes := num_functional_writes + functionalMemoryWrite(pkt); diff --git a/src/mem/protocol/MI_example-dma.sm b/src/mem/protocol/MI_example-dma.sm --- a/src/mem/protocol/MI_example-dma.sm +++ b/src/mem/protocol/MI_example-dma.sm @@ -70,11 +70,11 @@ void setAccessPermission(Addr addr, State state) { } - void functionalRead(Addr addr, Packet *pkt) { + void functionalRead(Addr addr, PacketPtr pkt) { error("DMA does not support functional read."); } - int functionalWrite(Addr addr, Packet *pkt) { + int functionalWrite(Addr addr, PacketPtr pkt) { error("DMA does not support functional write."); } diff --git a/src/mem/protocol/MI_example-msg.sm b/src/mem/protocol/MI_example-msg.sm --- a/src/mem/protocol/MI_example-msg.sm +++ b/src/mem/protocol/MI_example-msg.sm @@ -58,18 +58,18 @@ DataBlock DataBlk, desc="data for the cache line"; MessageSizeType MessageSize, desc="size category of the message"; - bool functionalRead(Packet *pkt) { + bool functionalRead(PacketPtr pkt) { // Valid data block is only present in PUTX messages if (Type == CoherenceRequestType:PUTX) { - return testAndRead(addr, DataBlk, pkt); + return DataBlk.testAndRead(addr, pkt); } return false; } - bool functionalWrite(Packet *pkt) { + bool functionalWrite(PacketPtr pkt) { // No check on message type required since the protocol should read // data block from only those messages that contain valid data - return testAndWrite(addr, DataBlk, pkt); + return DataBlk.testAndWrite(addr, pkt); } } @@ -83,16 +83,16 @@ bool Dirty, desc="Is the data dirty (different than memory)?"; MessageSizeType MessageSize, desc="size category of the message"; - bool functionalRead(Packet *pkt) { + bool functionalRead(PacketPtr pkt) { // A check on message type should appear here so that only those // messages that contain data - return testAndRead(addr, DataBlk, pkt); + return DataBlk.testAndRead(addr, pkt); } - bool functionalWrite(Packet *pkt) { + bool functionalWrite(PacketPtr pkt) { // No check on message type required since the protocol should read // data block from only those messages that contain valid data - return testAndWrite(addr, DataBlk, pkt); + return DataBlk.testAndWrite(addr, pkt); } } @@ -118,12 +118,12 @@ int Len, desc="The length of the request"; MessageSizeType MessageSize, desc="size category of the message"; - bool functionalRead(Packet *pkt) { - return testAndRead(LineAddress, DataBlk, pkt); + bool functionalRead(PacketPtr pkt) { + return DataBlk.testAndRead(LineAddress, pkt); } - bool functionalWrite(Packet *pkt) { - return testAndWrite(LineAddress, DataBlk, pkt); + bool functionalWrite(PacketPtr pkt) { + return DataBlk.testAndWrite(LineAddress, pkt); } } @@ -135,11 +135,11 @@ DataBlock DataBlk, desc="DataBlk attached to this request"; MessageSizeType MessageSize, desc="size category of the message"; - bool functionalRead(Packet *pkt) { - return testAndRead(LineAddress, DataBlk, pkt); + bool functionalRead(PacketPtr pkt) { + return DataBlk.testAndRead(LineAddress, pkt); } - bool functionalWrite(Packet *pkt) { - return testAndWrite(LineAddress, DataBlk, pkt); + bool functionalWrite(PacketPtr pkt) { + return DataBlk.testAndWrite(LineAddress, pkt); } } diff --git a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm --- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm +++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm @@ -216,33 +216,33 @@ } } - void functionalRead(Addr addr, Packet *pkt) { + void functionalRead(Addr addr, PacketPtr pkt) { Entry cache_entry := getCacheEntry(addr); if(is_valid(cache_entry)) { - testAndRead(addr, cache_entry.DataBlk, pkt); + cache_entry.DataBlk.testAndRead(addr, pkt); } else { TBE tbe := TBEs[addr]; if(is_valid(tbe)) { - testAndRead(addr, tbe.DataBlk, pkt); + tbe.DataBlk.testAndRead(addr, pkt); } else { error("Data block missing!"); } } } - int functionalWrite(Addr addr, Packet *pkt) { + int functionalWrite(Addr addr, PacketPtr pkt) { int num_functional_writes := 0; Entry cache_entry := getCacheEntry(addr); if(is_valid(cache_entry)) { num_functional_writes := num_functional_writes + - testAndWrite(addr, cache_entry.DataBlk, pkt); + cache_entry.DataBlk.testAndWrite(addr, pkt); return num_functional_writes; } TBE tbe := TBEs[addr]; num_functional_writes := num_functional_writes + - testAndWrite(addr, tbe.DataBlk, pkt); + tbe.DataBlk.testAndWrite(addr, pkt); return num_functional_writes; } diff --git a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm --- a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm +++ b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm @@ -544,27 +544,27 @@ } } - void functionalRead(Addr addr, Packet *pkt) { + void functionalRead(Addr addr, PacketPtr pkt) { TBE tbe := TBEs[addr]; if(is_valid(tbe)) { - testAndRead(addr, tbe.DataBlk, pkt); + tbe.DataBlk.testAndRead(addr, pkt); } else { - testAndRead(addr, getCacheEntry(addr).DataBlk, pkt); + getCacheEntry(addr).DataBlk.testAndRead(addr, pkt); } } - int functionalWrite(Addr addr, Packet *pkt) { + int functionalWrite(Addr addr, PacketPtr pkt) { int num_functional_writes := 0; TBE tbe := TBEs[addr]; if(is_valid(tbe)) { num_functional_writes := num_functional_writes + - testAndWrite(addr, tbe.DataBlk, pkt); + tbe.DataBlk.testAndWrite(addr, pkt); return num_functional_writes; } num_functional_writes := num_functional_writes + - testAndWrite(addr, getCacheEntry(addr).DataBlk, pkt); + getCacheEntry(addr).DataBlk.testAndWrite(addr, pkt); return num_functional_writes; } diff --git a/src/mem/protocol/MOESI_CMP_directory-dir.sm b/src/mem/protocol/MOESI_CMP_directory-dir.sm --- a/src/mem/protocol/MOESI_CMP_directory-dir.sm +++ b/src/mem/protocol/MOESI_CMP_directory-dir.sm @@ -193,11 +193,11 @@ } } - void functionalRead(Addr addr, Packet *pkt) { + void functionalRead(Addr addr, PacketPtr pkt) { functionalMemoryRead(pkt); } - int functionalWrite(Addr addr, Packet *pkt) { + int functionalWrite(Addr addr, PacketPtr pkt) { int num_functional_writes := 0; num_functional_writes := num_functional_writes + functionalMemoryWrite(pkt); return num_functional_writes; diff --git a/src/mem/protocol/MOESI_CMP_directory-dma.sm b/src/mem/protocol/MOESI_CMP_directory-dma.sm --- a/src/mem/protocol/MOESI_CMP_directory-dma.sm +++ b/src/mem/protocol/MOESI_CMP_directory-dma.sm @@ -92,11 +92,11 @@ void setAccessPermission(Addr addr, State state) { } - void functionalRead(Addr addr, Packet *pkt) { + void functionalRead(Addr addr, PacketPtr pkt) { error("DMA does not support functional read."); } - int functionalWrite(Addr addr, Packet *pkt) { + int functionalWrite(Addr addr, PacketPtr pkt) { error("DMA does not support functional write."); } diff --git a/src/mem/protocol/MOESI_CMP_directory-msg.sm b/src/mem/protocol/MOESI_CMP_directory-msg.sm --- a/src/mem/protocol/MOESI_CMP_directory-msg.sm +++ b/src/mem/protocol/MOESI_CMP_directory-msg.sm @@ -72,12 +72,12 @@ Addr addr, desc="Physical address for this request"; TriggerType Type, desc="Type of trigger"; - bool functionalRead(Packet *pkt) { + bool functionalRead(PacketPtr pkt) { // Trigger message does not hold data return false; } - bool functionalWrite(Packet *pkt) { + bool functionalWrite(PacketPtr pkt) { // Trigger message does not hold data return false; } @@ -97,18 +97,18 @@ RubyAccessMode AccessMode, desc="user/supervisor access type"; PrefetchBit Prefetch, desc="Is this a prefetch request"; - bool functionalRead(Packet *pkt) { + bool functionalRead(PacketPtr pkt) { // Read only those messages that contain the data if (Type == CoherenceRequestType:DMA_READ || Type == CoherenceRequestType:DMA_WRITE) { - return testAndRead(addr, DataBlk, pkt); + return DataBlk.testAndRead(addr, pkt); } return false; } - bool functionalWrite(Packet *pkt) { + bool functionalWrite(PacketPtr pkt) { // No check required since all messages are written - return testAndWrite(addr, DataBlk, pkt); + return DataBlk.testAndWrite(addr, pkt); } } @@ -124,19 +124,19 @@ int Acks, desc="How many acks to expect"; MessageSizeType MessageSize, desc="size category of the message"; - bool functionalRead(Packet *pkt) { + bool functionalRead(PacketPtr pkt) { // Read only those messages that contain the data if (Type == CoherenceResponseType:DATA || Type == CoherenceResponseType:DATA_EXCLUSIVE || Type == CoherenceResponseType:WRITEBACK_CLEAN_DATA || Type == CoherenceResponseType:WRITEBACK_DIRTY_DATA) { - return testAndRead(addr, DataBlk, pkt); + return DataBlk.testAndRead(addr, pkt); } return false; } - bool functionalWrite(Packet *pkt) { + bool functionalWrite(PacketPtr pkt) { // No check required since all messages are written - return testAndWrite(addr, DataBlk, pkt); + return DataBlk.testAndWrite(addr, pkt); } } diff --git a/src/mem/protocol/MOESI_CMP_token-L1cache.sm b/src/mem/protocol/MOESI_CMP_token-L1cache.sm --- a/src/mem/protocol/MOESI_CMP_token-L1cache.sm +++ b/src/mem/protocol/MOESI_CMP_token-L1cache.sm @@ -240,14 +240,14 @@ return L1Icache_entry; } - void functionalRead(Addr addr, Packet *pkt) { - testAndRead(addr, getCacheEntry(addr).DataBlk, pkt); + void functionalRead(Addr addr, PacketPtr pkt) { + getCacheEntry(addr).DataBlk.testAndRead(addr, pkt); } - int functionalWrite(Addr addr, Packet *pkt) { + int functionalWrite(Addr addr, PacketPtr pkt) { int num_functional_writes := 0; num_functional_writes := num_functional_writes + - testAndWrite(addr, getCacheEntry(addr).DataBlk, pkt); + getCacheEntry(addr).DataBlk.testAndWrite(addr, pkt); return num_functional_writes; } diff --git a/src/mem/protocol/MOESI_CMP_token-L2cache.sm b/src/mem/protocol/MOESI_CMP_token-L2cache.sm --- a/src/mem/protocol/MOESI_CMP_token-L2cache.sm +++ b/src/mem/protocol/MOESI_CMP_token-L2cache.sm @@ -162,14 +162,14 @@ return localDirectory.lookup(address); } - void functionalRead(Addr addr, Packet *pkt) { - testAndRead(addr, getCacheEntry(addr).DataBlk, pkt); + void functionalRead(Addr addr, PacketPtr pkt) { + getCacheEntry(addr).DataBlk.testAndRead(addr, pkt); } - int functionalWrite(Addr addr, Packet *pkt) { + int functionalWrite(Addr addr, PacketPtr pkt) { int num_functional_writes := 0; num_functional_writes := num_functional_writes + - testAndWrite(addr, getCacheEntry(addr).DataBlk, pkt); + getCacheEntry(addr).DataBlk.testAndWrite(addr, pkt); return num_functional_writes; } diff --git a/src/mem/protocol/MOESI_CMP_token-dir.sm b/src/mem/protocol/MOESI_CMP_token-dir.sm --- a/src/mem/protocol/MOESI_CMP_token-dir.sm +++ b/src/mem/protocol/MOESI_CMP_token-dir.sm @@ -247,22 +247,22 @@ persistentTable.markEntries(addr); } - void functionalRead(Addr addr, Packet *pkt) { + void functionalRead(Addr addr, PacketPtr pkt) { TBE tbe := TBEs[addr]; if(is_valid(tbe)) { - testAndRead(addr, tbe.DataBlk, pkt); + tbe.DataBlk.testAndRead(addr, pkt); } else { functionalMemoryRead(pkt); } } - int functionalWrite(Addr addr, Packet *pkt) { + int functionalWrite(Addr addr, PacketPtr pkt) { int num_functional_writes := 0; TBE tbe := TBEs[addr]; if(is_valid(tbe)) { num_functional_writes := num_functional_writes + - testAndWrite(addr, tbe.DataBlk, pkt); + tbe.DataBlk.testAndWrite(addr, pkt); } num_functional_writes := num_functional_writes + functionalMemoryWrite(pkt); diff --git a/src/mem/protocol/MOESI_CMP_token-dma.sm b/src/mem/protocol/MOESI_CMP_token-dma.sm --- a/src/mem/protocol/MOESI_CMP_token-dma.sm +++ b/src/mem/protocol/MOESI_CMP_token-dma.sm @@ -71,11 +71,11 @@ void setAccessPermission(Addr addr, State state) { } - void functionalRead(Addr addr, Packet *pkt) { + void functionalRead(Addr addr, PacketPtr pkt) { error("DMA does not support functional read."); } - int functionalWrite(Addr addr, Packet *pkt) { + int functionalWrite(Addr addr, PacketPtr pkt) { error("DMA does not support functional write."); } diff --git a/src/mem/protocol/MOESI_CMP_token-msg.sm b/src/mem/protocol/MOESI_CMP_token-msg.sm --- a/src/mem/protocol/MOESI_CMP_token-msg.sm +++ b/src/mem/protocol/MOESI_CMP_token-msg.sm @@ -66,12 +66,12 @@ RubyAccessMode AccessMode, desc="user/supervisor access type"; PrefetchBit Prefetch, desc="Is this a prefetch request"; - bool functionalRead(Packet *pkt) { + bool functionalRead(PacketPtr pkt) { // No data in persistent messages return false; } - bool functionalWrite(Packet *pkt) { + bool functionalWrite(PacketPtr pkt) { // No data in persistent messages return false; } @@ -89,12 +89,12 @@ RubyAccessMode AccessMode, desc="user/supervisor access type"; PrefetchBit Prefetch, desc="Is this a prefetch request"; - bool functionalRead(Packet *pkt) { + bool functionalRead(PacketPtr pkt) { // No data in request messages return false; } - bool functionalWrite(Packet *pkt) { + bool functionalWrite(PacketPtr pkt) { // No data in request messages return false; } @@ -111,14 +111,14 @@ bool Dirty, desc="Is the data dirty (different than memory)?"; MessageSizeType MessageSize, desc="size category of the message"; - bool functionalRead(Packet *pkt) { + bool functionalRead(PacketPtr pkt) { // No check being carried out on the message type. Would be added later. - return testAndRead(addr, DataBlk, pkt); + return DataBlk.testAndRead(addr, pkt); } - bool functionalWrite(Packet *pkt) { + bool functionalWrite(PacketPtr pkt) { // No check required since all messages are written. - return testAndWrite(addr, DataBlk, pkt); + return DataBlk.testAndWrite(addr, pkt); } } @@ -144,12 +144,12 @@ int Len, desc="The length of the request"; MessageSizeType MessageSize, desc="size category of the message"; - bool functionalRead(Packet *pkt) { + bool functionalRead(PacketPtr pkt) { return false; } - bool functionalWrite(Packet *pkt) { - return testAndWrite(LineAddress, DataBlk, pkt); + bool functionalWrite(PacketPtr pkt) { + return DataBlk.testAndWrite(LineAddress, pkt); } } @@ -161,11 +161,11 @@ DataBlock DataBlk, desc="DataBlk attached to this request"; MessageSizeType MessageSize, desc="size category of the message"; - bool functionalRead(Packet *pkt) { + bool functionalRead(PacketPtr pkt) { return false; } - bool functionalWrite(Packet *pkt) { - return testAndWrite(LineAddress, DataBlk, pkt); + bool functionalWrite(PacketPtr pkt) { + return DataBlk.testAndWrite(LineAddress, pkt); } } diff --git a/src/mem/protocol/MOESI_hammer-cache.sm b/src/mem/protocol/MOESI_hammer-cache.sm --- a/src/mem/protocol/MOESI_hammer-cache.sm +++ b/src/mem/protocol/MOESI_hammer-cache.sm @@ -204,33 +204,33 @@ return L1Icache_entry; } - void functionalRead(Addr addr, Packet *pkt) { + void functionalRead(Addr addr, PacketPtr pkt) { Entry cache_entry := getCacheEntry(addr); if(is_valid(cache_entry)) { - testAndRead(addr, cache_entry.DataBlk, pkt); + cache_entry.DataBlk.testAndRead(addr, pkt); } else { TBE tbe := TBEs[addr]; if(is_valid(tbe)) { - testAndRead(addr, tbe.DataBlk, pkt); + tbe.DataBlk.testAndRead(addr, pkt); } else { error("Missing data block"); } } } - int functionalWrite(Addr addr, Packet *pkt) { + int functionalWrite(Addr addr, PacketPtr pkt) { int num_functional_writes := 0; Entry cache_entry := getCacheEntry(addr); if(is_valid(cache_entry)) { num_functional_writes := num_functional_writes + - testAndWrite(addr, cache_entry.DataBlk, pkt); + cache_entry.DataBlk.testAndWrite(addr, pkt); return num_functional_writes; } TBE tbe := TBEs[addr]; num_functional_writes := num_functional_writes + - testAndWrite(addr, tbe.DataBlk, pkt); + tbe.DataBlk.testAndWrite(addr, pkt); return num_functional_writes; }