diff -r 2d1d51615e0e src/arch/x86/bios/IntelMP.py --- a/src/arch/x86/bios/IntelMP.py Tue Nov 03 12:17:58 2015 -0600 +++ b/src/arch/x86/bios/IntelMP.py Wed Nov 04 14:50:24 2015 +0000 @@ -108,25 +108,25 @@ class X86IntelMPProcessor(X86IntelMPBase feature_flags = Param.UInt32(0, 'flags returned by the CPUID instruction') class X86IntelMPBus(X86IntelMPBaseConfigEntry): type = 'X86IntelMPBus' cxx_class = 'X86ISA::IntelMP::Bus' cxx_header = 'arch/x86/bios/intelmp.hh' bus_id = Param.UInt8(0, 'bus id assigned by the bios') bus_type = Param.String("", 'string that identify the bus type') - # Legal values for bus_type are: + # Legal values for bus_type are [space padded to 6 bytes]: # - # "CBUS", "CBUSII", "EISA", "FUTURE", "INTERN", "ISA", "MBI", "MBII", - # "MCA", "MPI", "MPSA", "NUBUS", "PCI", "PCMCIA", "TC", "VL", "VME", - # "XPRESS" + # "CBUS ", "CBUSII", "EISA ", "FUTURE", "INTERN", "ISA ", "MBI ", + # "MBII ", "MCA ", "MPI ", "MPSA ", "NUBUS ", "PCI ", "PCMCIA", + # "TC ", "VL ", "VME ", "XPRESS" class X86IntelMPIOAPIC(X86IntelMPBaseConfigEntry): type = 'X86IntelMPIOAPIC' cxx_class = 'X86ISA::IntelMP::IOAPIC' cxx_header = 'arch/x86/bios/intelmp.hh' id = Param.UInt8(0, 'id of this APIC') version = Param.UInt8(0, 'bits 0-7 of the version register') enable = Param.Bool(True, 'if this APIC is usable') diff -r 2d1d51615e0e configs/common/FSConfig.py --- a/configs/common/FSConfig.py Tue Nov 03 12:17:58 2015 -0600 +++ b/configs/common/FSConfig.py Wed Nov 04 14:02:06 2015 +0000 @@ -503,63 +503,63 @@ def makeX86System(mem_mode, numCPUs=1, m disk0 = CowIdeDisk(driveID='master') disk2 = CowIdeDisk(driveID='master') disk0.childImage(mdesc.disk()) disk2.childImage(disk('linux-bigswap2.img')) self.pc.south_bridge.ide.disks = [disk0, disk2] # Add in a Bios information structure. structures = [X86SMBiosBiosInformation()] self.smbios_table.structures = structures # Set up the Intel MP table base_entries = [] ext_entries = [] for i in xrange(numCPUs): bp = X86IntelMPProcessor( local_apic_id = i, local_apic_version = 0x14, enable = True, bootstrap = (i == 0)) base_entries.append(bp) io_apic = X86IntelMPIOAPIC( id = numCPUs, version = 0x11, enable = True, address = 0xfec00000) self.pc.south_bridge.io_apic.apic_id = io_apic.id base_entries.append(io_apic) # In gem5 Pc::calcPciConfigAddr(), it required "assert(bus==0)", # but linux kernel cannot config PCI device if it was not connected to PCI bus, # so we fix PCI bus id to 0, and ISA bus id to 1. - pci_bus = X86IntelMPBus(bus_id = 0, bus_type='PCI') + pci_bus = X86IntelMPBus(bus_id = 0, bus_type='PCI ') base_entries.append(pci_bus) - isa_bus = X86IntelMPBus(bus_id = 1, bus_type='ISA') + isa_bus = X86IntelMPBus(bus_id = 1, bus_type='ISA ') base_entries.append(isa_bus) connect_busses = X86IntelMPBusHierarchy(bus_id=1, subtractive_decode=True, parent_bus=0) ext_entries.append(connect_busses) pci_dev4_inta = X86IntelMPIOIntAssignment( interrupt_type = 'INT', polarity = 'ConformPolarity', trigger = 'ConformTrigger', source_bus_id = 0, source_bus_irq = 0 + (4 << 2), dest_io_apic_id = io_apic.id, dest_io_apic_intin = 16) base_entries.append(pci_dev4_inta) def assignISAInt(irq, apicPin): assign_8259_to_apic = X86IntelMPIOIntAssignment( interrupt_type = 'ExtInt', polarity = 'ConformPolarity', trigger = 'ConformTrigger', source_bus_id = 1, source_bus_irq = irq, dest_io_apic_id = io_apic.id, dest_io_apic_intin = 0) base_entries.append(assign_8259_to_apic) assign_to_apic = X86IntelMPIOIntAssignment( interrupt_type = 'INT', polarity = 'ConformPolarity', trigger = 'ConformTrigger', source_bus_id = 1, source_bus_irq = irq, dest_io_apic_id = io_apic.id,