diff -r ef6a27d53bd8 -r 0aafcce44a46 src/arch/sparc/isa/decoder.isa
--- a/src/arch/sparc/isa/decoder.isa	Fri Nov 19 18:06:44 2010 -0600
+++ b/src/arch/sparc/isa/decoder.isa	Fri Nov 19 18:08:29 2010 -0600
@@ -490,7 +490,7 @@
                 0x00: NoPriv::wry({{Y = (Rs1 ^ Rs2_or_imm13)<31:0>;}});
                 // 0x01 should cause an illegal instruction exception
                 0x02: NoPriv::wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}});
-                0x03: NoPriv::wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}});
+                0x03: NoPriv::wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}}, false, IsSquashAfter);
                 // 0x04-0x05 should cause an illegal instruction exception
                 0x06: NoPriv::wrfprs({{Fprs = Rs1 ^ Rs2_or_imm13;}});
                 // 0x07-0x0E should cause an illegal instruction exception
diff -r ef6a27d53bd8 -r 0aafcce44a46 src/cpu/base_dyn_inst.hh
--- a/src/cpu/base_dyn_inst.hh	Fri Nov 19 18:06:44 2010 -0600
+++ b/src/cpu/base_dyn_inst.hh	Fri Nov 19 18:08:29 2010 -0600
@@ -478,6 +478,7 @@
     { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
     bool isSerializeAfter() const
     { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
+    bool isSquashAfter() const { return staticInst->isSquashAfter(); }
     bool isMemBarrier()   const { return staticInst->isMemBarrier(); }
     bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
     bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
diff -r ef6a27d53bd8 -r 0aafcce44a46 src/cpu/o3/commit_impl.hh
--- a/src/cpu/o3/commit_impl.hh	Fri Nov 19 18:06:44 2010 -0600
+++ b/src/cpu/o3/commit_impl.hh	Fri Nov 19 18:08:29 2010 -0600
@@ -915,8 +915,38 @@
                 // Updates misc. registers.
                 head_inst->updateMiscRegs();
 
+                bool squash_after = head_inst->isSquashAfter();
+
                 TheISA::advancePC(pc[tid], head_inst->staticInst);
 
+                // If this is an instruction that doesn't play nicely with
+                // others squash everything and restart fetch
+                if (squash_after) {
+                    int squash_after_inst = head_inst->seqNum;
+                    youngestSeqNum[tid] = squash_after_inst;
+
+                    rob->squash(squash_after, tid);
+                    changedROBNumEntries[tid] = true;
+
+                    // Send back the sequence number of the squashed instruction.
+                    toIEW->commitInfo[tid].doneSeqNum = squash_after_inst;
+
+                    // Send back the squash signal to tell stages that they should
+                    // squash.
+                    toIEW->commitInfo[tid].squash = true;
+
+                    // Send back the rob squashing signal so other stages know that
+                    // the ROB is in the process of squashing.
+                    toIEW->commitInfo[tid].robSquashing = true;
+
+                    toIEW->commitInfo[tid].branchMispredict = false;
+
+                    toIEW->commitInfo[tid].pc = pc[tid];
+                    DPRINTF(Commit, "Executing squash after for [tid:%i] inst"
+                            " [sn:%lli]\n", tid, squash_after_inst);
+                    commitStatus[tid] = ROBSquashing;
+                }
+
                 int count = 0;
                 Addr oldpc;
                 // Debug statement.  Checks to make sure we're not
diff -r ef6a27d53bd8 -r 0aafcce44a46 src/cpu/static_inst.hh
--- a/src/cpu/static_inst.hh	Fri Nov 19 18:06:44 2010 -0600
+++ b/src/cpu/static_inst.hh	Fri Nov 19 18:08:29 2010 -0600
@@ -158,7 +158,7 @@
         //This flag doesn't do anything yet
         IsMicroBranch,  ///< This microop branches within the microcode for a macroop
         IsDspOp,
-
+        IsSquashAfter, ///< Squash all uncommitted state after executed
         NumFlags
     };
 
@@ -248,6 +248,7 @@
                                       flags[IsSerializeAfter]; }
     bool isSerializeBefore() const { return flags[IsSerializeBefore]; }
     bool isSerializeAfter() const { return flags[IsSerializeAfter]; }
+    bool isSquashAfter() const { return flags[IsSquashAfter]; }
     bool isMemBarrier()   const { return flags[IsMemBarrier]; }
     bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
     bool isNonSpeculative() const { return flags[IsNonSpeculative]; }