diff -r 83e890c83564 -r 5b9e9bac916d src/arch/arm/remote_gdb.hh
--- a/src/arch/arm/remote_gdb.hh	Tue Nov 10 04:49:02 2015 -0500
+++ b/src/arch/arm/remote_gdb.hh	Thu Nov 12 08:03:58 2015 -0500
@@ -60,13 +60,13 @@
 // For now, assume gdb's default.
 
 // AArch32 registers (--target=arm-linux-gnueabihf)
-// 32bit-word offsets are used instead of enum of register numbers
-// because widths are different and not always powers of 2, but
-// at least all aligned on 4-byte boundary
-const int GDB32_R0_OFFSET = 0;
-const int GDB32_F0_OFFSET = 16;
-const int GDB32_FPSCR_OFFSET = GDB32_F0_OFFSET + 3*8;
-const int GDB32_CPSR_OFFSET = GDB32_FPSCR_OFFSET + 1;
+enum {
+    GDB32_R0 = 0,
+    GDB32_F0 = 16,
+    GDB32_FPSCR = GDB32_F0 + 3*8,
+    GDB32_CPSR = GDB32_FPSCR + 1,
+    GDB32_NUMREGS = 42
+};
 
 // AArch64 registers
 enum {
@@ -80,10 +80,7 @@
 };
 
 const int GDB64_REG_BYTES M5_VAR_USED = GDB64_NUMREGS * sizeof(uint64_t);
-const int GDB32_REG_BYTES M5_VAR_USED = 16 * sizeof(uint32_t) /* R0-R15 */ +
-                          8 * 12 /* F0-F7, Extended precision (96 bits) */ +
-                          sizeof(uint32_t) /* FPSCR */ +
-                          sizeof(uint32_t) /* CPSR */ ;
+const int GDB32_REG_BYTES M5_VAR_USED = GDB32_NUMREGS * sizeof(uint32_t);
 
 class RemoteGDB : public BaseRemoteGDB
 {
diff -r 83e890c83564 -r 5b9e9bac916d src/arch/arm/remote_gdb.cc
--- a/src/arch/arm/remote_gdb.cc	Tue Nov 10 04:49:02 2015 -0500
+++ b/src/arch/arm/remote_gdb.cc	Thu Nov 12 08:03:58 2015 -0500
@@ -227,22 +227,22 @@
         memset(gdbregs.regs, 0, gdbregs.bytes());
 
         // R0-R15 supervisor mode
-        gdbregs.regs32[GDB32_R0_OFFSET + 0] = context->readIntReg(INTREG_R0);
-        gdbregs.regs32[GDB32_R0_OFFSET + 1] = context->readIntReg(INTREG_R1);
-        gdbregs.regs32[GDB32_R0_OFFSET + 2] = context->readIntReg(INTREG_R2);
-        gdbregs.regs32[GDB32_R0_OFFSET + 3] = context->readIntReg(INTREG_R3);
-        gdbregs.regs32[GDB32_R0_OFFSET + 4] = context->readIntReg(INTREG_R4);
-        gdbregs.regs32[GDB32_R0_OFFSET + 5] = context->readIntReg(INTREG_R5);
-        gdbregs.regs32[GDB32_R0_OFFSET + 6] = context->readIntReg(INTREG_R6);
-        gdbregs.regs32[GDB32_R0_OFFSET + 7] = context->readIntReg(INTREG_R7);
-        gdbregs.regs32[GDB32_R0_OFFSET + 8] = context->readIntReg(INTREG_R8);
-        gdbregs.regs32[GDB32_R0_OFFSET + 9] = context->readIntReg(INTREG_R9);
-        gdbregs.regs32[GDB32_R0_OFFSET + 10] = context->readIntReg(INTREG_R10);
-        gdbregs.regs32[GDB32_R0_OFFSET + 11] = context->readIntReg(INTREG_R11);
-        gdbregs.regs32[GDB32_R0_OFFSET + 12] = context->readIntReg(INTREG_R12);
-        gdbregs.regs32[GDB32_R0_OFFSET + 13] = context->readIntReg(INTREG_SP);
-        gdbregs.regs32[GDB32_R0_OFFSET + 14] = context->readIntReg(INTREG_LR);
-        gdbregs.regs32[GDB32_R0_OFFSET + 15] = context->pcState().pc();
+        gdbregs.regs32[GDB32_R0 + 0] = context->readIntReg(INTREG_R0);
+        gdbregs.regs32[GDB32_R0 + 1] = context->readIntReg(INTREG_R1);
+        gdbregs.regs32[GDB32_R0 + 2] = context->readIntReg(INTREG_R2);
+        gdbregs.regs32[GDB32_R0 + 3] = context->readIntReg(INTREG_R3);
+        gdbregs.regs32[GDB32_R0 + 4] = context->readIntReg(INTREG_R4);
+        gdbregs.regs32[GDB32_R0 + 5] = context->readIntReg(INTREG_R5);
+        gdbregs.regs32[GDB32_R0 + 6] = context->readIntReg(INTREG_R6);
+        gdbregs.regs32[GDB32_R0 + 7] = context->readIntReg(INTREG_R7);
+        gdbregs.regs32[GDB32_R0 + 8] = context->readIntReg(INTREG_R8);
+        gdbregs.regs32[GDB32_R0 + 9] = context->readIntReg(INTREG_R9);
+        gdbregs.regs32[GDB32_R0 + 10] = context->readIntReg(INTREG_R10);
+        gdbregs.regs32[GDB32_R0 + 11] = context->readIntReg(INTREG_R11);
+        gdbregs.regs32[GDB32_R0 + 12] = context->readIntReg(INTREG_R12);
+        gdbregs.regs32[GDB32_R0 + 13] = context->readIntReg(INTREG_SP);
+        gdbregs.regs32[GDB32_R0 + 14] = context->readIntReg(INTREG_LR);
+        gdbregs.regs32[GDB32_R0 + 15] = context->pcState().pc();
 
         // By default, gdb configured for arm-linux-gnueabihf will
         // expect f0-f7 of IEEE Extended precision (96 bits) each.
@@ -251,11 +251,11 @@
         // day somebody will implement transfer of FPRs correctly.
 
         // FPSCR
-        gdbregs.regs32[GDB32_FPSCR_OFFSET] =
+        gdbregs.regs32[GDB32_FPSCR] =
             context->readMiscRegNoEffect(MISCREG_FPSCR);
 
         // CPSR
-        gdbregs.regs32[GDB32_CPSR_OFFSET] =
+        gdbregs.regs32[GDB32_CPSR] =
             context->readMiscRegNoEffect(MISCREG_CPSR);
     }
 }
@@ -293,28 +293,28 @@
         // R0-R15 supervisor mode
         // arm registers are 32 bits wide, gdb registers are 64 bits wide
         // two arm registers are packed into one gdb register (little endian)
-        context->setIntReg(INTREG_R0, gdbregs.regs32[GDB32_R0_OFFSET + 0]);
-        context->setIntReg(INTREG_R1, gdbregs.regs32[GDB32_R0_OFFSET + 1]);
-        context->setIntReg(INTREG_R2, gdbregs.regs32[GDB32_R0_OFFSET + 2]);
-        context->setIntReg(INTREG_R3, gdbregs.regs32[GDB32_R0_OFFSET + 3]);
-        context->setIntReg(INTREG_R4, gdbregs.regs32[GDB32_R0_OFFSET + 4]);
-        context->setIntReg(INTREG_R5, gdbregs.regs32[GDB32_R0_OFFSET + 5]);
-        context->setIntReg(INTREG_R6, gdbregs.regs32[GDB32_R0_OFFSET + 6]);
-        context->setIntReg(INTREG_R7, gdbregs.regs32[GDB32_R0_OFFSET + 7]);
-        context->setIntReg(INTREG_R8, gdbregs.regs32[GDB32_R0_OFFSET + 8]);
-        context->setIntReg(INTREG_R9, gdbregs.regs32[GDB32_R0_OFFSET + 9]);
-        context->setIntReg(INTREG_R10, gdbregs.regs32[GDB32_R0_OFFSET + 10]);
-        context->setIntReg(INTREG_R11, gdbregs.regs32[GDB32_R0_OFFSET + 11]);
-        context->setIntReg(INTREG_R12, gdbregs.regs32[GDB32_R0_OFFSET + 12]);
-        context->setIntReg(INTREG_SP, gdbregs.regs32[GDB32_R0_OFFSET + 13]);
-        context->setIntReg(INTREG_LR, gdbregs.regs32[GDB32_R0_OFFSET + 14]);
-        context->pcState(gdbregs.regs32[GDB32_R0_OFFSET + 15]);
+        context->setIntReg(INTREG_R0, gdbregs.regs32[GDB32_R0 + 0]);
+        context->setIntReg(INTREG_R1, gdbregs.regs32[GDB32_R0 + 1]);
+        context->setIntReg(INTREG_R2, gdbregs.regs32[GDB32_R0 + 2]);
+        context->setIntReg(INTREG_R3, gdbregs.regs32[GDB32_R0 + 3]);
+        context->setIntReg(INTREG_R4, gdbregs.regs32[GDB32_R0 + 4]);
+        context->setIntReg(INTREG_R5, gdbregs.regs32[GDB32_R0 + 5]);
+        context->setIntReg(INTREG_R6, gdbregs.regs32[GDB32_R0 + 6]);
+        context->setIntReg(INTREG_R7, gdbregs.regs32[GDB32_R0 + 7]);
+        context->setIntReg(INTREG_R8, gdbregs.regs32[GDB32_R0 + 8]);
+        context->setIntReg(INTREG_R9, gdbregs.regs32[GDB32_R0 + 9]);
+        context->setIntReg(INTREG_R10, gdbregs.regs32[GDB32_R0 + 10]);
+        context->setIntReg(INTREG_R11, gdbregs.regs32[GDB32_R0 + 11]);
+        context->setIntReg(INTREG_R12, gdbregs.regs32[GDB32_R0 + 12]);
+        context->setIntReg(INTREG_SP, gdbregs.regs32[GDB32_R0 + 13]);
+        context->setIntReg(INTREG_LR, gdbregs.regs32[GDB32_R0 + 14]);
+        context->pcState(gdbregs.regs32[GDB32_R0 + 15]);
 
         //FPSCR
-        context->setMiscReg(MISCREG_FPSCR, gdbregs.regs32[GDB32_FPSCR_OFFSET]);
+        context->setMiscReg(MISCREG_FPSCR, gdbregs.regs32[GDB32_FPSCR]);
 
         //CPSR
-        context->setMiscRegNoEffect(MISCREG_CPSR, gdbregs.regs32[GDB32_CPSR_OFFSET]);
+        context->setMiscRegNoEffect(MISCREG_CPSR, gdbregs.regs32[GDB32_CPSR]);
     }
 }
 
diff -r 83e890c83564 -r 5b9e9bac916d src/sim/system.cc
--- a/src/sim/system.cc	Tue Nov 10 04:49:02 2015 -0500
+++ b/src/sim/system.cc	Thu Nov 12 08:03:58 2015 -0500
@@ -208,7 +208,7 @@
  * connect to that context ID before continuing.  This should really
    be a parameter on the CPU object or something...
  */
-int rgdb_wait = -1;
+int rgdb_wait = 0;
 
 ContextID
 System::registerThreadContext(ThreadContext *tc, ContextID assigned)