diff --git a/src/dev/CopyEngine.py b/src/dev/pci/CopyEngine.py
rename from src/dev/CopyEngine.py
rename to src/dev/pci/CopyEngine.py
--- a/src/dev/CopyEngine.py
+++ b/src/dev/pci/CopyEngine.py
@@ -33,7 +33,7 @@
 
 class CopyEngine(PciDevice):
     type = 'CopyEngine'
-    cxx_header = "dev/copy_engine.hh"
+    cxx_header = "dev/pci/copy_engine.hh"
     dma = VectorMasterPort("Copy engine DMA port")
     VendorID = 0x8086
     DeviceID = 0x1a38
# Node ID 3a6f434a199e554606787bd3af29d321000c284c
# Parent  2af9f017205f164db54c23c0c09b5481d96b1977
diff --git a/src/dev/SConscript b/src/dev/SConscript
--- a/src/dev/SConscript
+++ b/src/dev/SConscript
@@ -40,7 +40,6 @@
     Return()
 
 SimObject('BadDevice.py')
-SimObject('CopyEngine.py')
 SimObject('DiskImage.py')
 SimObject('Ethernet.py')
 SimObject('I2C.py')
@@ -51,7 +50,6 @@
 SimObject('Uart.py')
 
 Source('baddev.cc')
-Source('copy_engine.cc')
 Source('disk_image.cc')
 Source('dma_device.cc')
 Source('etherbus.cc')
@@ -85,7 +83,6 @@
 DebugFlag('DiskImageRead')
 DebugFlag('DiskImageWrite')
 DebugFlag('DMA')
-DebugFlag('DMACopyEngine')
 DebugFlag('Ethernet')
 DebugFlag('MultiEthernet')
 DebugFlag('MultiEthernetPkt')
diff --git a/src/dev/copy_engine.hh b/src/dev/pci/copy_engine.hh
rename from src/dev/copy_engine.hh
rename to src/dev/pci/copy_engine.hh
--- a/src/dev/copy_engine.hh
+++ b/src/dev/pci/copy_engine.hh
@@ -45,14 +45,14 @@
  * A DMA asyncronous copy engine
  */
 
-#ifndef __DEV_COPY_ENGINE_HH__
-#define __DEV_COPY_ENGINE_HH__
+#ifndef __DEV_PCI_COPY_ENGINE_HH__
+#define __DEV_PCI_COPY_ENGINE_HH__
 
 #include <vector>
 
 #include "base/cp_annotate.hh"
 #include "base/statistics.hh"
-#include "dev/copy_engine_defs.hh"
+#include "dev/pci/copy_engine_defs.hh"
 #include "dev/pci/device.hh"
 #include "params/CopyEngine.hh"
 #include "sim/drain.hh"
@@ -208,5 +208,5 @@
     void unserialize(CheckpointIn &cp) override;
 };
 
-#endif //__DEV_COPY_ENGINE_HH__
+#endif //__DEV_PCI_COPY_ENGINE_HH__
 
diff --git a/src/dev/copy_engine.cc b/src/dev/pci/copy_engine.cc
rename from src/dev/copy_engine.cc
rename to src/dev/pci/copy_engine.cc
--- a/src/dev/copy_engine.cc
+++ b/src/dev/pci/copy_engine.cc
@@ -44,13 +44,14 @@
  * Device model for Intel's I/O AT DMA copy engine.
  */
 
+#include "dev/pci/copy_engine.hh"
+
 #include <algorithm>
 
 #include "base/cp_annotate.hh"
 #include "base/trace.hh"
 #include "debug/DMACopyEngine.hh"
 #include "debug/Drain.hh"
-#include "dev/copy_engine.hh"
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
 #include "params/CopyEngine.hh"
diff --git a/src/dev/copy_engine_defs.hh b/src/dev/pci/copy_engine_defs.hh
rename from src/dev/copy_engine_defs.hh
rename to src/dev/pci/copy_engine_defs.hh
diff --git a/src/dev/pci/SConscript b/src/dev/pci/SConscript
--- a/src/dev/pci/SConscript
+++ b/src/dev/pci/SConscript
@@ -55,3 +55,6 @@
 Source('host.cc')
 DebugFlag('PciHost')
 
+SimObject('CopyEngine.py')
+Source('copy_engine.cc')
+DebugFlag('DMACopyEngine')