diff -r cf2a46c01102 -r 374d79447577 src/arch/null/cpu_dummy.hh --- a/src/arch/null/cpu_dummy.hh Tue Dec 29 15:12:40 2015 -0600 +++ b/src/arch/null/cpu_dummy.hh Wed Jan 06 16:01:20 2016 -0600 @@ -47,6 +47,8 @@ public: static int numSimulatedInsts() { return 0; } static int numSimulatedOps() { return 0; } + static int numSimulatorInsts() { return 0; } + static int numSimulatorOps() { return 0; } static void wakeup(ThreadID tid) { ; } }; diff -r cf2a46c01102 -r 374d79447577 src/cpu/BaseCPU.py --- a/src/cpu/BaseCPU.py Tue Dec 29 15:12:40 2015 -0600 +++ b/src/cpu/BaseCPU.py Wed Jan 06 16:01:20 2016 -0600 @@ -99,6 +99,7 @@ bool switchedOut(); void flushTLBs(); Counter totalInsts(); + Counter totalSimulatorInsts(); void scheduleInstStop(ThreadID tid, Counter insts, const char *cause); void scheduleLoadStop(ThreadID tid, Counter loads, const char *cause); ''') diff -r cf2a46c01102 -r 374d79447577 src/cpu/base.hh --- a/src/cpu/base.hh Tue Dec 29 15:12:40 2015 -0600 +++ b/src/cpu/base.hh Wed Jan 06 16:01:20 2016 -0600 @@ -435,6 +435,10 @@ virtual Counter totalOps() const = 0; + virtual Counter totalSimulatorInsts() const = 0; + + virtual Counter totalSimulatorOps() const = 0; + /** * Schedule an event that exits the simulation loops after a * predefined number of instructions. @@ -534,6 +538,7 @@ } static int numSimulatedCPUs() { return cpuList.size(); } + static Counter numSimulatedInsts() { Counter total = 0; @@ -556,6 +561,29 @@ return total; } + static Counter numSimulatorInsts() + { + Counter total = 0; + + int size = cpuList.size(); + for (int i = 0; i < size; ++i) + total += cpuList[i]->totalSimulatorInsts(); + + return total; + } + + static Counter numSimulatorOps() + { + Counter total = 0; + + int size = cpuList.size(); + for (int i = 0; i < size; ++i) + total += cpuList[i]->totalSimulatorOps(); + + return total; + } + + public: // Number of CPU cycles simulated Stats::Scalar numCycles; diff -r cf2a46c01102 -r 374d79447577 src/cpu/checker/cpu.hh --- a/src/cpu/checker/cpu.hh Tue Dec 29 15:12:40 2015 -0600 +++ b/src/cpu/checker/cpu.hh Wed Jan 06 16:01:20 2016 -0600 @@ -185,6 +185,16 @@ return 0; } + virtual Counter totalSimulatorInsts() const override + { + return 0; + } + + virtual Counter totalSimulatorOps() const override + { + return 0; + } + // number of simulated loads Counter numLoad; Counter startNumLoad; diff -r cf2a46c01102 -r 374d79447577 src/cpu/kvm/base.hh --- a/src/cpu/kvm/base.hh Tue Dec 29 15:12:40 2015 -0600 +++ b/src/cpu/kvm/base.hh Wed Jan 06 16:01:20 2016 -0600 @@ -109,6 +109,9 @@ Counter totalInsts() const; Counter totalOps() const; + Counter totalSimulatorInsts() const; + Counter totalSimulatorOps() const; + /** Dump the internal state to the terminal. */ virtual void dump() const; diff -r cf2a46c01102 -r 374d79447577 src/cpu/kvm/base.cc --- a/src/cpu/kvm/base.cc Tue Dec 29 15:12:40 2015 -0600 +++ b/src/cpu/kvm/base.cc Wed Jan 06 16:01:20 2016 -0600 @@ -492,11 +492,24 @@ Counter BaseKvmCPU::totalInsts() const { + return numInsts.value(); +} + +Counter +BaseKvmCPU::totalOps() const +{ + hack_once("Pretending totalOps is equivalent to totalInsts()\n"); + return numInsts.value(); +} + +Counter +BaseKvmCPU::totalSimulatorInsts() const +{ return ctrInsts; } Counter -BaseKvmCPU::totalOps() const +BaseKvmCPU::totalSimulatorOps() const { hack_once("Pretending totalOps is equivalent to totalInsts()\n"); return ctrInsts; diff -r cf2a46c01102 -r 374d79447577 src/cpu/minor/cpu.cc --- a/src/cpu/minor/cpu.cc Tue Dec 29 15:12:40 2015 -0600 +++ b/src/cpu/minor/cpu.cc Wed Jan 06 16:01:20 2016 -0600 @@ -332,7 +332,7 @@ Counter ret = 0; for (auto i = threads.begin(); i != threads.end(); i ++) - ret += (*i)->numInst; + ret += (*i)->numInsts.value(); return ret; } @@ -343,6 +343,28 @@ Counter ret = 0; for (auto i = threads.begin(); i != threads.end(); i ++) + ret += (*i)->numOps.value(); + + return ret; +} + +Counter +MinorCPU::totalSimulatorInsts() const +{ + Counter ret = 0; + + for (auto i = threads.begin(); i != threads.end(); i ++) + ret += (*i)->numInst; + + return ret; +} + +Counter +MinorCPU::totalSimulatorOps() const +{ + Counter ret = 0; + + for (auto i = threads.begin(); i != threads.end(); i ++) ret += (*i)->numOp; return ret; diff -r cf2a46c01102 -r 374d79447577 src/cpu/o3/cpu.hh --- a/src/cpu/o3/cpu.hh Tue Dec 29 15:12:40 2015 -0600 +++ b/src/cpu/o3/cpu.hh Wed Jan 06 16:01:20 2016 -0600 @@ -321,6 +321,14 @@ /** Count the Total Ops (including micro ops) committed in the CPU. */ Counter totalOps() const override; + /** Count the Total Instructions Committed in the CPU, during this + * execution of the simulator. */ + Counter totalSimulatorInsts() const override; + + /** Count the Total Ops (including micro ops) committed in the CPU, during + * this execution of the simulator. */ + Counter totalSimulatorOps() const override; + /** Add Thread to Active Threads List. */ void activateContext(ThreadID tid) override; diff -r cf2a46c01102 -r 374d79447577 src/cpu/o3/cpu.cc --- a/src/cpu/o3/cpu.cc Tue Dec 29 15:12:40 2015 -0600 +++ b/src/cpu/o3/cpu.cc Wed Jan 06 16:01:20 2016 -0600 @@ -682,6 +682,32 @@ ThreadID size = thread.size(); for (ThreadID i = 0; i < size; i++) + total += thread[i]->numInsts.value(); + + return total; +} + +template +Counter +FullO3CPU::totalOps() const +{ + Counter total(0); + + ThreadID size = thread.size(); + for (ThreadID i = 0; i < size; i++) + total += thread[i]->numOps.value(); + + return total; +} + +template +Counter +FullO3CPU::totalSimulatorInsts() const +{ + Counter total(0); + + ThreadID size = thread.size(); + for (ThreadID i = 0; i < size; i++) total += thread[i]->numInst; return total; @@ -689,7 +715,7 @@ template Counter -FullO3CPU::totalOps() const +FullO3CPU::totalSimulatorOps() const { Counter total(0); diff -r cf2a46c01102 -r 374d79447577 src/cpu/simple/base.hh --- a/src/cpu/simple/base.hh Tue Dec 29 15:12:40 2015 -0600 +++ b/src/cpu/simple/base.hh Wed Jan 06 16:01:20 2016 -0600 @@ -151,6 +151,8 @@ void countInst(); Counter totalInsts() const override; Counter totalOps() const override; + Counter totalSimulatorInsts() const override; + Counter totalSimulatorOps() const override; void serializeThread(CheckpointOut &cp, ThreadID tid) const override; void unserializeThread(CheckpointIn &cp, ThreadID tid) override; diff -r cf2a46c01102 -r 374d79447577 src/cpu/simple/base.cc --- a/src/cpu/simple/base.cc Tue Dec 29 15:12:40 2015 -0600 +++ b/src/cpu/simple/base.cc Wed Jan 06 16:01:20 2016 -0600 @@ -188,6 +188,17 @@ { Counter total_inst = 0; for (auto& t_info : threadInfo) { + total_inst += t_info->numInsts.value(); + } + + return total_inst; +} + +Counter +BaseSimpleCPU::totalSimulatorInsts() const +{ + Counter total_inst = 0; + for (auto& t_info : threadInfo) { total_inst += t_info->numInst; } @@ -199,6 +210,17 @@ { Counter total_op = 0; for (auto& t_info : threadInfo) { + total_op += t_info->numOps.value(); + } + + return total_op; +} + +Counter +BaseSimpleCPU::totalSimulatorOps() const +{ + Counter total_op = 0; + for (auto& t_info : threadInfo) { total_op += t_info->numOp; } diff -r cf2a46c01102 -r 374d79447577 src/sim/stat_control.hh --- a/src/sim/stat_control.hh Tue Dec 29 15:12:40 2015 -0600 +++ b/src/sim/stat_control.hh Wed Jan 06 16:01:20 2016 -0600 @@ -47,8 +47,10 @@ namespace Stats { double statElapsedTime(); +double simulatorElapsedTime(); Tick statElapsedTicks(); +Tick simulatorElapsedTicks(); Tick statFinalTick(); diff -r cf2a46c01102 -r 374d79447577 src/sim/stat_control.cc --- a/src/sim/stat_control.cc Tue Dec 29 15:12:40 2015 -0600 +++ b/src/sim/stat_control.cc Wed Jan 06 16:01:20 2016 -0600 @@ -62,13 +62,13 @@ Stats::Formula simSeconds; Stats::Value simTicks; -Stats::Value finalTick; -Stats::Value simFreq; namespace Stats { Time statTime(true); +Time simulatorStartTime(true); Tick startTick; +Tick simulatorStartTick; GlobalEvent *dumpEvent; @@ -91,6 +91,15 @@ return elapsed; } +double +simulatorElapsedTime() +{ + Time now; + now.setTimer(); + Time elapsed = now - simulatorStartTime; + return elapsed; +} + Tick statElapsedTicks() { @@ -98,6 +107,12 @@ } Tick +simulatorElapsedTicks() +{ + return curTick() - simulatorStartTick; +} + +Tick statFinalTick() { return curTick(); @@ -107,14 +122,25 @@ struct Global { + Stats::Value simInsts; + Stats::Value simOps; Stats::Formula hostInstRate; Stats::Formula hostOpRate; Stats::Formula hostTickRate; - Stats::Value hostMemory; Stats::Value hostSeconds; - Stats::Value simInsts; - Stats::Value simOps; + Stats::Formula simulatorSeconds; + Stats::Value simulatorTicks; + Stats::Value simulatorInsts; + Stats::Value simulatorOps; + Stats::Formula simulatorHostInstRate; + Stats::Formula simulatorHostOpRate; + Stats::Formula simulatorHostTickRate; + Stats::Value simulatorHostSeconds; + + Stats::Value finalTick; + Stats::Value hostMemory; + Stats::Value simFreq; Global(); }; @@ -129,6 +155,14 @@ .prereq(simInsts) ; + simulatorInsts + .functor(BaseCPU::numSimulatorInsts) + .name("simulator_insts") + .desc("Number of instructions simulated (not reset)") + .precision(0) + .prereq(simulatorInsts) + ; + simOps .functor(BaseCPU::numSimulatedOps) .name("sim_ops") @@ -137,6 +171,19 @@ .prereq(simOps) ; + simulatorOps + .functor(BaseCPU::numSimulatorOps) + .name("simulator_ops") + .desc("Number of ops (including micro ops) simulated (not reset)") + .precision(0) + .prereq(simulatorOps) + ; + + simulatorSeconds + .name("simulator_seconds") + .desc("Number of seconds simulated (not reset)") + ; + simSeconds .name("sim_seconds") .desc("Number of seconds simulated") @@ -148,6 +195,12 @@ .desc("Frequency of simulated ticks") ; + simulatorTicks + .functor(simulatorElapsedTicks) + .name("simulator_ticks") + .desc("Number of ticks simulated (not reset)") + ; + simTicks .functor(statElapsedTicks) .name("sim_ticks") @@ -163,18 +216,33 @@ hostInstRate .name("host_inst_rate") - .desc("Simulator instruction rate (inst/s)") + .desc("Simulator instruction rate (inst/s) since last stat reset") .precision(0) .prereq(simInsts) ; hostOpRate .name("host_op_rate") - .desc("Simulator op (including micro ops) rate (op/s)") + .desc("Simulator op (including micro ops) rate (op/s) since last stat " + "reset") .precision(0) .prereq(simOps) ; + simulatorHostInstRate + .name("simulator_host_inst_rate") + .desc("Simulator instruction rate (inst/s) (not reset)") + .precision(0) + .prereq(simulatorInsts) + ; + + simulatorHostOpRate + .name("simulator_host_op_rate") + .desc("Simulator op (including micro ops) rate (op/s) (not reset)") + .precision(0) + .prereq(simulatorOps) + ; + hostMemory .functor(memUsage) .name("host_mem_usage") @@ -185,20 +253,37 @@ hostSeconds .functor(statElapsedTime) .name("host_seconds") - .desc("Real time elapsed on the host") + .desc("Real time elapsed on the host since last stat reset") + .precision(2) + ; + + simulatorHostSeconds + .functor(simulatorElapsedTime) + .name("simulator_host_seconds") + .desc("Real time elapsed on the host (not reset)") .precision(2) ; hostTickRate .name("host_tick_rate") - .desc("Simulator tick rate (ticks/s)") + .desc("Simulator tick rate (ticks/s) since last stat reset") + .precision(0) + ; + + simulatorHostTickRate + .name("simulator_host_tick_rate") + .desc("Simulator tick rate (ticks/s) (not reset)") .precision(0) ; simSeconds = simTicks / simFreq; + simulatorSeconds = simulatorTicks / simFreq; hostInstRate = simInsts / hostSeconds; hostOpRate = simOps / hostSeconds; hostTickRate = simTicks / hostSeconds; + simulatorHostInstRate = simulatorInsts / simulatorHostSeconds; + simulatorHostOpRate = simulatorOps / simulatorHostSeconds; + simulatorHostTickRate = simulatorTicks / simulatorHostSeconds; registerResetCallback(&simTicksReset); } @@ -207,6 +292,8 @@ initSimStats() { static Global global; + simulatorStartTick = curTick(); + simulatorStartTime.setTimer(); } /**