diff -r b82ef73f63c1 -r d416c44fe086 src/mem/ruby/system/RubySystem.hh --- a/src/mem/ruby/system/RubySystem.hh Thu Jan 07 16:31:49 2016 +0000 +++ b/src/mem/ruby/system/RubySystem.hh Thu Jan 07 16:31:55 2016 +0000 @@ -79,7 +79,7 @@ SimpleMemory *getPhysMem() { return m_phys_mem; } Cycles getStartCycle() { return m_start_cycle; } - const bool getAccessBackingStore() { return m_access_backing_store; } + bool getAccessBackingStore() { return m_access_backing_store; } // Public Methods Profiler* diff -r b82ef73f63c1 -r d416c44fe086 src/sim/process.cc --- a/src/sim/process.cc Thu Jan 07 16:31:49 2016 +0000 +++ b/src/sim/process.cc Thu Jan 07 16:31:55 2016 +0000 @@ -290,7 +290,8 @@ { int npages = divCeil(size, (int64_t)PageBytes); Addr paddr = system->allocPhysPages(npages); - pTable->map(vaddr, paddr, size, clobber ? PageTableBase::Clobber : 0); + pTable->map(vaddr, paddr, size, + clobber ? PageTableBase::Clobber : PageTableBase::Zero); } bool @@ -454,7 +455,7 @@ Process::map(Addr vaddr, Addr paddr, int size, bool cacheable) { pTable->map(vaddr, paddr, size, - cacheable ? 0 : PageTableBase::Uncacheable); + cacheable ? PageTableBase::Zero : PageTableBase::Uncacheable); return true; } diff -r b82ef73f63c1 -r d416c44fe086 src/sim/sim_events.hh --- a/src/sim/sim_events.hh Thu Jan 07 16:31:49 2016 +0000 +++ b/src/sim/sim_events.hh Thu Jan 07 16:31:55 2016 +0000 @@ -66,7 +66,7 @@ Tick repeat = 0); const std::string getCause() const { return cause; } - const int getCode() const { return code; } + int getCode() const { return code; } void process(); // process event @@ -86,7 +86,7 @@ LocalSimLoopExitEvent(const std::string &_cause, int c, Tick repeat = 0); const std::string getCause() const { return cause; } - const int getCode() const { return code; } + int getCode() const { return code; } void process() override; // process event @@ -111,7 +111,7 @@ void setCount(int _count) { count = _count; } - const int getCount() const { return count; } + int getCount() const { return count; } }; // diff -r b82ef73f63c1 -r d416c44fe086 src/dev/sparc/iob.cc --- a/src/dev/sparc/iob.cc Thu Jan 07 16:31:49 2016 +0000 +++ b/src/dev/sparc/iob.cc Thu Jan 07 16:31:55 2016 +0000 @@ -91,7 +91,8 @@ { Addr accessAddr = pkt->getAddr() - iobManAddr; - if (accessAddr >= IntManAddr && accessAddr < IntManAddr + IntManSize) { + assert(IntManAddr == 0); + if (accessAddr < IntManAddr + IntManSize) { int index = (accessAddr - IntManAddr) >> 3; uint64_t data = intMan[index].cpu << 8 | intMan[index].vector << 0; pkt->set(data); @@ -186,7 +187,8 @@ int index; uint64_t data; - if (accessAddr >= IntManAddr && accessAddr < IntManAddr + IntManSize) { + assert(IntManAddr == 0); + if (accessAddr < IntManAddr + IntManSize) { index = (accessAddr - IntManAddr) >> 3; data = pkt->get(); intMan[index].cpu = bits(data,12,8); diff -r b82ef73f63c1 -r d416c44fe086 src/dev/terminal.cc --- a/src/dev/terminal.cc Thu Jan 07 16:31:49 2016 +0000 +++ b/src/dev/terminal.cc Thu Jan 07 16:31:55 2016 +0000 @@ -249,7 +249,7 @@ if (data_fd < 0) panic("Terminal not properly attached.\n"); - size_t ret; + ssize_t ret; do { ret = ::read(data_fd, buf, len); } while (ret == -1 && errno == EINTR); diff -r b82ef73f63c1 -r d416c44fe086 src/mem/packet.hh --- a/src/mem/packet.hh Thu Jan 07 16:31:49 2016 +0000 +++ b/src/mem/packet.hh Thu Jan 07 16:31:55 2016 +0000 @@ -215,7 +215,7 @@ bool isPrint() const { return testCmdAttrib(IsPrint); } bool isFlush() const { return testCmdAttrib(IsFlush); } - const Command + Command responseCommand() const { return commandInfo[cmd].response; diff -r b82ef73f63c1 -r d416c44fe086 src/mem/page_table.hh --- a/src/mem/page_table.hh Thu Jan 07 16:31:49 2016 +0000 +++ b/src/mem/page_table.hh Thu Jan 07 16:31:55 2016 +0000 @@ -93,6 +93,7 @@ * bit 3 - read-write | read-only */ enum MappingFlags : uint32_t { + Zero = 0, Clobber = 1, NotPresent = 2, Uncacheable = 4, diff -r b82ef73f63c1 -r d416c44fe086 src/mem/request.hh --- a/src/mem/request.hh Thu Jan 07 16:31:49 2016 +0000 +++ b/src/mem/request.hh Thu Jan 07 16:31:55 2016 +0000 @@ -234,7 +234,6 @@ void setPhys(Addr paddr, unsigned size, Flags flags, MasterID mid, Tick time) { - assert(size >= 0); _paddr = paddr; _size = size; _time = time; diff -r b82ef73f63c1 -r d416c44fe086 src/mem/ruby/slicc_interface/AbstractController.hh --- a/src/mem/ruby/slicc_interface/AbstractController.hh Thu Jan 07 16:31:49 2016 +0000 +++ b/src/mem/ruby/slicc_interface/AbstractController.hh Thu Jan 07 16:31:55 2016 +0000 @@ -65,8 +65,8 @@ void init(); const Params *params() const { return (const Params *)_params; } - const NodeID getVersion() const { return m_machineID.getNum(); } - const MachineType getType() const { return m_machineID.getType(); } + NodeID getVersion() const { return m_machineID.getNum(); } + MachineType getType() const { return m_machineID.getType(); } void initNetworkPtr(Network* net_ptr) { m_net_ptr = net_ptr; } diff -r b82ef73f63c1 -r d416c44fe086 src/mem/ruby/slicc_interface/Message.hh --- a/src/mem/ruby/slicc_interface/Message.hh Thu Jan 07 16:31:49 2016 +0000 +++ b/src/mem/ruby/slicc_interface/Message.hh Thu Jan 07 16:31:55 2016 +0000 @@ -83,12 +83,12 @@ Tick delta = curTime - m_LastEnqueueTime; m_DelayedTicks += delta; } - const Tick getDelayedTicks() const {return m_DelayedTicks;} + Tick getDelayedTicks() const {return m_DelayedTicks;} void setLastEnqueueTime(const Tick& time) { m_LastEnqueueTime = time; } - const Tick getLastEnqueueTime() const {return m_LastEnqueueTime;} + Tick getLastEnqueueTime() const {return m_LastEnqueueTime;} - const Tick& getTime() const { return m_time; } + Tick getTime() const { return m_time; } void setMsgCounter(uint64_t c) { m_msg_counter = c; } uint64_t getMsgCounter() const { return m_msg_counter; } diff -r b82ef73f63c1 -r d416c44fe086 src/mem/ruby/structures/RubyMemoryControl.hh --- a/src/mem/ruby/structures/RubyMemoryControl.hh Thu Jan 07 16:31:49 2016 +0000 +++ b/src/mem/ruby/structures/RubyMemoryControl.hh Thu Jan 07 16:31:55 2016 +0000 @@ -75,12 +75,12 @@ void print(std::ostream& out) const override; void regStats() override; - const int getBank(const Addr addr) const; - const int getRank(const Addr addr) const; + int getBank(const Addr addr) const; + int getRank(const Addr addr) const; // not used in Ruby memory controller - const int getChannel(const Addr addr) const; - const int getRow(const Addr addr) const; + int getChannel(const Addr addr) const; + int getRow(const Addr addr) const; //added by SS int getBanksPerRank() { return m_banks_per_rank; }; @@ -92,7 +92,7 @@ private: void enqueueToDirectory(MemoryNode *req, Cycles latency); - const int getRank(int bank) const; + int getRank(int bank) const; bool queueReady(int bank); void issueRequest(int bank); bool issueRefresh(int bank); diff -r b82ef73f63c1 -r d416c44fe086 src/mem/ruby/structures/RubyMemoryControl.cc --- a/src/mem/ruby/structures/RubyMemoryControl.cc Thu Jan 07 16:31:49 2016 +0000 +++ b/src/mem/ruby/structures/RubyMemoryControl.cc Thu Jan 07 16:31:55 2016 +0000 @@ -342,7 +342,7 @@ // getBank returns an integer that is unique for each // bank across this memory controller. -const int +int RubyMemoryControl::getBank(const Addr addr) const { int dimm = (addr >> m_dimm_bit_0) & (m_dimms_per_channel - 1); @@ -353,7 +353,7 @@ + bank; } -const int +int RubyMemoryControl::getRank(const Addr addr) const { int bank = getBank(addr); @@ -364,7 +364,7 @@ // getRank returns an integer that is unique for each rank // and independent of individual bank. -const int +int RubyMemoryControl::getRank(int bank) const { int rank = (bank / m_banks_per_rank); @@ -373,7 +373,7 @@ } // Not used! -const int +int RubyMemoryControl::getChannel(const Addr addr) const { assert(false); @@ -381,7 +381,7 @@ } // Not used! -const int +int RubyMemoryControl::getRow(const Addr addr) const { assert(false); diff -r b82ef73f63c1 -r d416c44fe086 SConstruct --- a/SConstruct Thu Jan 07 16:31:49 2016 +0000 +++ b/SConstruct Thu Jan 07 16:31:55 2016 +0000 @@ -554,14 +554,12 @@ # As gcc and clang share many flags, do the common parts here main.Append(CCFLAGS=['-pipe']) main.Append(CCFLAGS=['-fno-strict-aliasing']) - # Enable -Wall and then disable the few warnings that we - # consistently violate - main.Append(CCFLAGS=['-Wall', '-Wno-sign-compare', '-Wundef']) + # Enable -Wall and -Wextra and then disable the few warnings that + # we consistently violate + main.Append(CCFLAGS=['-Wall', '-Wundef', '-Wextra', + '-Wno-sign-compare', '-Wno-unused-parameter']) # We always compile using C++11 main.Append(CXXFLAGS=['-std=c++11']) - # Add selected sanity checks from -Wextra - main.Append(CXXFLAGS=['-Wmissing-field-initializers', - '-Woverloaded-virtual']) else: print termcap.Yellow + termcap.Bold + 'Error' + termcap.Normal, print "Don't know what compiler options to use for your compiler." @@ -656,14 +654,11 @@ print 'Error: Unable to determine clang version.' Exit(1) - # clang has a few additional warnings that we disable, - # tautological comparisons are allowed due to unsigned integers - # being compared to constants that happen to be 0, and extraneous + # clang has a few additional warnings that we disable, extraneous # parantheses are allowed due to Ruby's printing of the AST, # finally self assignments are allowed as the generated CPU code # is relying on this - main.Append(CCFLAGS=['-Wno-tautological-compare', - '-Wno-parentheses', + main.Append(CCFLAGS=['-Wno-parentheses', '-Wno-self-assign', # Some versions of libstdc++ (4.8?) seem to # use struct hash and class hash diff -r b82ef73f63c1 -r d416c44fe086 ext/dramsim2/SConscript --- a/ext/dramsim2/SConscript Thu Jan 07 16:31:49 2016 +0000 +++ b/ext/dramsim2/SConscript Thu Jan 07 16:31:55 2016 +0000 @@ -77,7 +77,8 @@ # If we are using clang, there are more flags to disable if main['CLANG']: - dramenv.Append(CCFLAGS=['-Wno-unused-private-field']) + dramenv.Append(CCFLAGS=['-Wno-unused-private-field', + '-Wno-tautological-undefined-compare']) # Tell DRAMSim2 to not store any data as this is already covered by # the wrapper diff -r b82ef73f63c1 -r d416c44fe086 ext/libelf/SConscript --- a/ext/libelf/SConscript Thu Jan 07 16:31:49 2016 +0000 +++ b/ext/libelf/SConscript Thu Jan 07 16:31:55 2016 +0000 @@ -93,10 +93,10 @@ m4env = main.Clone() if m4env['GCC']: - m4env.Append(CCFLAGS=['-Wno-pointer-sign']) - if compareVersions(m4env['GCC_VERSION'], '4.6') >= 0: - m4env.Append(CCFLAGS=['-Wno-unused-but-set-variable', - '-Wno-implicit-function-declaration']) + m4env.Append(CCFLAGS=['-Wno-pointer-sign', + '-Wno-unused-but-set-variable', + '-Wno-implicit-function-declaration', + '-Wno-override-init']) if m4env['CLANG']: m4env.Append(CCFLAGS=['-Wno-initializer-overrides', '-Wno-pointer-sign']) # clang defaults to c99 (while gcc defaults to gnu89) and there is a diff -r b82ef73f63c1 -r d416c44fe086 ext/nomali/SConscript --- a/ext/nomali/SConscript Thu Jan 07 16:31:49 2016 +0000 +++ b/ext/nomali/SConscript Thu Jan 07 16:31:55 2016 +0000 @@ -42,6 +42,7 @@ main.Prepend(CPPPATH=Dir('./include')) nomali = main.Clone() +nomali.Append(CCFLAGS=['-Wno-ignored-qualifiers']) nomali_sources = [ "lib/gpu.cc", diff -r b82ef73f63c1 -r d416c44fe086 src/SConscript --- a/src/SConscript Thu Jan 07 16:31:49 2016 +0000 +++ b/src/SConscript Thu Jan 07 16:31:55 2016 +0000 @@ -1016,12 +1016,8 @@ # Both gcc and clang have issues with unused labels and values in # the SWIG generated code - swig_env.Append(CCFLAGS=['-Wno-unused-label', '-Wno-unused-value']) - - # Add additional warnings here that should not be applied to - # the SWIG generated code - new_env.Append(CXXFLAGS=['-Wmissing-declarations', - '-Wdelete-non-virtual-dtor']) + swig_env.Append(CCFLAGS=['-Wno-unused-label', '-Wno-unused-value', + '-Wno-tautological-compare']) if env['GCC']: # Depending on the SWIG version, we also need to supress diff -r b82ef73f63c1 -r d416c44fe086 src/arch/alpha/faults.hh --- a/src/arch/alpha/faults.hh Thu Jan 07 16:31:49 2016 +0000 +++ b/src/arch/alpha/faults.hh Thu Jan 07 16:31:55 2016 +0000 @@ -40,7 +40,7 @@ namespace AlphaISA { -typedef const Addr FaultVect; +typedef Addr FaultVect; class AlphaFault : public FaultBase { diff -r b82ef73f63c1 -r d416c44fe086 src/arch/alpha/utility.hh --- a/src/arch/alpha/utility.hh Thu Jan 07 16:31:49 2016 +0000 +++ b/src/arch/alpha/utility.hh Thu Jan 07 16:31:55 2016 +0000 @@ -78,7 +78,7 @@ inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; } // User Virtual -inline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; } +inline bool IsUSeg(Addr a) { assert(USegBase == 0); return a <= USegEnd; } // Kernel Direct Mapped inline bool IsK0Seg(Addr a) { return K0SegBase <= a && a <= K0SegEnd; } diff -r b82ef73f63c1 -r d416c44fe086 src/arch/arm/faults.hh --- a/src/arch/arm/faults.hh Thu Jan 07 16:31:49 2016 +0000 +++ b/src/arch/arm/faults.hh Thu Jan 07 16:31:55 2016 +0000 @@ -58,7 +58,7 @@ namespace ArmISA { -typedef const Addr FaultOffset; +typedef Addr FaultOffset; class ArmFault : public FaultBase { diff -r b82ef73f63c1 -r d416c44fe086 src/arch/arm/utility.cc --- a/src/arch/arm/utility.cc Thu Jan 07 16:31:49 2016 +0000 +++ b/src/arch/arm/utility.cc Thu Jan 07 16:31:55 2016 +0000 @@ -209,7 +209,7 @@ // We deliberately extend both the Cluster ID and CPU ID fields to allow // for simulation of larger systems assert((0 <= tc->cpuId()) && (tc->cpuId() < 256)); - assert((0 <= tc->socketId()) && (tc->socketId() < 65536)); + assert(tc->socketId() < 65536); if (arm_sys->multiThread) { return 0x80000000 | // multiprocessor extensions available tc->contextId(); diff -r b82ef73f63c1 -r d416c44fe086 src/arch/mips/faults.hh --- a/src/arch/mips/faults.hh Thu Jan 07 16:31:49 2016 +0000 +++ b/src/arch/mips/faults.hh Thu Jan 07 16:31:55 2016 +0000 @@ -45,7 +45,7 @@ namespace MipsISA { -typedef const Addr FaultVect; +typedef Addr FaultVect; enum ExcCode { // A dummy value to use when the code isn't defined or doesn't matter. diff -r b82ef73f63c1 -r d416c44fe086 src/arch/mips/isa/decoder.isa --- a/src/arch/mips/isa/decoder.isa Thu Jan 07 16:31:49 2016 +0000 +++ b/src/arch/mips/isa/decoder.isa Thu Jan 07 16:31:55 2016 +0000 @@ -2404,7 +2404,7 @@ 0x3: decode OP_LO { format DspHiLoOp { 0x2: shilo({{ - if (sext<6>(HILOSA) < 0) { + if ((int64_t)sext<6>(HILOSA) < 0) { dspac = (uint64_t)dspac << -sext<6>(HILOSA); } else { @@ -2413,7 +2413,7 @@ } }}); 0x3: shilov({{ - if (sext<6>(Rs_sw<5:0>) < 0) { + if ((int64_t)sext<6>(Rs_sw<5:0>) < 0) { dspac = (uint64_t)dspac << -sext<6>(Rs_sw<5:0>); } else { diff -r b82ef73f63c1 -r d416c44fe086 src/arch/sparc/isa/decoder.isa --- a/src/arch/sparc/isa/decoder.isa Thu Jan 07 16:31:49 2016 +0000 +++ b/src/arch/sparc/isa/decoder.isa Thu Jan 07 16:31:55 2016 +0000 @@ -669,13 +669,13 @@ }}); 0x43: FpUnimpl::fmovq_fcc1(); 0x45: fmovrslez({{ - if (Rs1 <= 0) + if ((int64_t)Rs1 <= 0) Frds = Frs2s; else Frds = Frds; }}); 0x46: fmovrdlez({{ - if (Rs1 <= 0) + if ((int64_t)Rs1 <= 0) Frd = Frs2; else Frd = Frd; @@ -740,13 +740,13 @@ }}); 0x57: FpUnimpl::fcmpeq(); 0x65: fmovrslz({{ - if (Rs1 < 0) + if ((int64_t)Rs1 < 0) Frds = Frs2s; else Frds = Frds; }}); 0x66: fmovrdlz({{ - if (Rs1 < 0) + if ((int64_t)Rs1 < 0) Frd = Frs2; else Frd = Frd; @@ -792,26 +792,26 @@ }}); 0xC3: FpUnimpl::fmovq_fcc3(); 0xC5: fmovrsgz({{ - if (Rs1 > 0) + if ((int64_t)Rs1 > 0) Frds = Frs2s; else Frds = Frds; }}); 0xC6: fmovrdgz({{ - if (Rs1 > 0) + if ((int64_t)Rs1 > 0) Frd = Frs2; else Frd = Frd; }}); 0xC7: FpUnimpl::fmovrqgz(); 0xE5: fmovrsgez({{ - if (Rs1 >= 0) + if ((int64_t)Rs1 >= 0) Frds = Frs2s; else Frds = Frds; }}); 0xE6: fmovrdgez({{ - if (Rs1 >= 0) + if ((int64_t)Rs1 >= 0) Frd = Frs2; else Frd = Frd; diff -r b82ef73f63c1 -r d416c44fe086 src/base/bitunion.hh --- a/src/base/bitunion.hh Thu Jan 07 16:31:49 2016 +0000 +++ b/src/base/bitunion.hh Thu Jan 07 16:31:55 2016 +0000 @@ -89,7 +89,7 @@ "Bitfield ranges must be specified as "); public: - operator const uint64_t () const + operator uint64_t () const { return this->getBits(first, last); } @@ -129,7 +129,7 @@ class BitfieldWO : public Bitfield { private: - operator const uint64_t () const; + operator uint64_t () const; public: using Bitfield::operator=; @@ -148,7 +148,7 @@ class SignedBitfield : public BitfieldBase { public: - operator const int64_t () const + operator int64_t () const { return sext(this->getBits(first, last)); } @@ -188,7 +188,7 @@ class SignedBitfieldWO : public SignedBitfield { private: - operator const int64_t () const; + operator int64_t () const; public: using SignedBitfield::operator=; @@ -304,10 +304,10 @@ //do so. #define EndSubBitUnion(name) \ }; \ - inline operator const __DataType () const \ + inline operator __DataType () const \ { return __data; } \ \ - inline const __DataType operator = (const __DataType & _data) \ + inline __DataType operator = (const __DataType & _data) \ { return __data = _data;} \ } name; diff -r b82ef73f63c1 -r d416c44fe086 src/cpu/base_dyn_inst.hh --- a/src/cpu/base_dyn_inst.hh Thu Jan 07 16:31:49 2016 +0000 +++ b/src/cpu/base_dyn_inst.hh Thu Jan 07 16:31:55 2016 +0000 @@ -793,13 +793,13 @@ void pcState(const TheISA::PCState &val) { pc = val; } /** Read the PC of this instruction. */ - const Addr instAddr() const { return pc.instAddr(); } + Addr instAddr() const { return pc.instAddr(); } /** Read the PC of the next instruction. */ - const Addr nextInstAddr() const { return pc.nextInstAddr(); } + Addr nextInstAddr() const { return pc.nextInstAddr(); } /**Read the micro PC of this instruction. */ - const Addr microPC() const { return pc.microPC(); } + Addr microPC() const { return pc.microPC(); } bool readPredicate() { diff -r b82ef73f63c1 -r d416c44fe086 src/cpu/pred/sat_counter.hh --- a/src/cpu/pred/sat_counter.hh Thu Jan 07 16:31:49 2016 +0000 +++ b/src/cpu/pred/sat_counter.hh Thu Jan 07 16:31:55 2016 +0000 @@ -105,7 +105,7 @@ /** * Read the counter's value. */ - const uint8_t read() const + uint8_t read() const { return counter; } private: diff -r b82ef73f63c1 -r d416c44fe086 src/cpu/trace/trace_cpu.cc --- a/src/cpu/trace/trace_cpu.cc Thu Jan 07 16:31:49 2016 +0000 +++ b/src/cpu/trace/trace_cpu.cc Thu Jan 07 16:31:55 2016 +0000 @@ -1337,8 +1337,8 @@ if (own_reg_dep == reg_dep) { // If register dependency is found, make it zero and return true own_reg_dep = 0; + assert(numRegDep > 0); --numRegDep; - assert(numRegDep >= 0); DPRINTFR(TraceCPUData, "\tFor %lli: Marking register dependency %lli " "done.\n", seqNum, reg_dep); return true; @@ -1356,8 +1356,8 @@ if (own_rob_dep == rob_dep) { // If the rob dependency is found, make it zero and return true own_rob_dep = 0; + assert(numRobDep > 0); --numRobDep; - assert(numRobDep >= 0); DPRINTFR(TraceCPUData, "\tFor %lli: Marking ROB dependency %lli " "done.\n", seqNum, rob_dep); return true; diff -r b82ef73f63c1 -r d416c44fe086 src/dev/arm/hdlcd.hh --- a/src/dev/arm/hdlcd.hh Thu Jan 07 16:31:49 2016 +0000 +++ b/src/dev/arm/hdlcd.hh Thu Jan 07 16:31:55 2016 +0000 @@ -316,7 +316,7 @@ } /** Masked interrupt status register */ - const uint32_t intStatus() const { return int_rawstat & int_mask; } + uint32_t intStatus() const { return int_rawstat & int_mask; } protected: // Pixel output class PixelPump : public BasePixelPump diff -r b82ef73f63c1 -r d416c44fe086 src/dev/arm/pl011.hh --- a/src/dev/arm/pl011.hh Thu Jan 07 16:31:49 2016 +0000 +++ b/src/dev/arm/pl011.hh Thu Jan 07 16:31:55 2016 +0000 @@ -110,7 +110,7 @@ void clearInterrupts(uint16_t ints) { setInterrupts(rawInt & ~ints, imsc); } /** Masked interrupt status register */ - const inline uint16_t maskInt() const { return rawInt & imsc; } + inline uint16_t maskInt() const { return rawInt & imsc; } /** Wrapper to create an event out of the thing */ EventWrapper intEvent; diff -r b82ef73f63c1 -r d416c44fe086 src/dev/net/ethertap.cc --- a/src/dev/net/ethertap.cc Thu Jan 07 16:31:49 2016 +0000 +++ b/src/dev/net/ethertap.cc Thu Jan 07 16:31:55 2016 +0000 @@ -241,8 +241,8 @@ packet->length = data_len; memcpy(packet->data, data, data_len); + assert(buffer_offset >= data_len + sizeof(uint32_t)); buffer_offset -= data_len + sizeof(uint32_t); - assert(buffer_offset >= 0); if (buffer_offset > 0) { memmove(buffer, data + data_len, buffer_offset); data_len = ntohl(*(uint32_t *)buffer); diff -r b82ef73f63c1 -r d416c44fe086 src/dev/net/ns_gige_reg.h --- a/src/dev/net/ns_gige_reg.h Thu Jan 07 16:31:49 2016 +0000 +++ b/src/dev/net/ns_gige_reg.h Thu Jan 07 16:31:55 2016 +0000 @@ -93,6 +93,7 @@ /* configuration register */ enum ConfigurationRegisters { + CFGR_ZERO = 0x00000000, CFGR_LNKSTS = 0x80000000, CFGR_SPDSTS = 0x60000000, CFGR_SPDSTS1 = 0x40000000, @@ -395,7 +396,7 @@ SPDSTS_POLARITY(int lnksts) { return (CFGR_SPDSTS1 | CFGR_SPDSTS0 | CFGR_DUPSTS | - (lnksts ? CFGR_LNKSTS : 0)); + (lnksts ? CFGR_LNKSTS : CFGR_ZERO)); } #endif /* __DEV_NS_GIGE_REG_H__ */ diff -r b82ef73f63c1 -r d416c44fe086 src/dev/net/pktfifo.hh --- a/src/dev/net/pktfifo.hh Thu Jan 07 16:31:49 2016 +0000 +++ b/src/dev/net/pktfifo.hh Thu Jan 07 16:31:55 2016 +0000 @@ -106,8 +106,8 @@ unsigned reserve(unsigned len = 0) { + assert(avail() >= len); _reserved += len; - assert(avail() >= 0); return _reserved; }