# Node ID 13844da643aa68a8840a9f974674db54348bcd22
# Parent  4cc8b312f026321a81cb0b043e8e3a5c20b5f5db
diff --git a/src/arch/alpha/types.hh b/src/arch/alpha/types.hh
--- a/src/arch/alpha/types.hh
+++ b/src/arch/alpha/types.hh
@@ -42,8 +42,6 @@
 
 typedef GenericISA::SimplePCState<MachInst> PCState;
 
-typedef uint64_t LargestRead;
-
 enum annotes
 {
     ANNOTE_NONE = 0,
diff --git a/src/arch/arm/types.hh b/src/arch/arm/types.hh
--- a/src/arch/arm/types.hh
+++ b/src/arch/arm/types.hh
@@ -524,9 +524,6 @@
         SXTX = 7
     };
 
-    typedef uint64_t LargestRead;
-    // Need to use 64 bits to make sure that read requests get handled properly
-
     typedef int RegContextParam;
     typedef int RegContextVal;
 
diff --git a/src/arch/mips/types.hh b/src/arch/mips/types.hh
--- a/src/arch/mips/types.hh
+++ b/src/arch/mips/types.hh
@@ -42,8 +42,6 @@
 
 typedef GenericISA::DelaySlotPCState<MachInst> PCState;
 
-typedef uint64_t LargestRead;
-
 //used in FP convert & round function
 enum ConvertType{
     SINGLE_TO_DOUBLE,
diff --git a/src/arch/sparc/types.hh b/src/arch/sparc/types.hh
--- a/src/arch/sparc/types.hh
+++ b/src/arch/sparc/types.hh
@@ -43,8 +43,6 @@
 
 typedef GenericISA::DelaySlotUPCState<MachInst> PCState;
 
-typedef Twin64_t LargestRead;
-
 }
 
 #endif
diff --git a/src/arch/x86/registers.hh b/src/arch/x86/registers.hh
--- a/src/arch/x86/registers.hh
+++ b/src/arch/x86/registers.hh
@@ -91,8 +91,6 @@
 
 typedef uint64_t IntReg;
 typedef uint64_t CCReg;
-//XXX Should this be a 128 bit structure for XMM memory ops?
-typedef uint64_t LargestRead;
 typedef uint64_t MiscReg;
 
 //These floating point types are correct for mmx, but not