diff -r 31a04e5ac4be -r 68374d55ea98 src/cpu/testers/rubytest/RubyTester.hh --- a/src/cpu/testers/rubytest/RubyTester.hh Sat Jan 22 21:48:06 2011 -0800 +++ b/src/cpu/testers/rubytest/RubyTester.hh Mon Jan 24 22:28:54 2011 -0600 @@ -37,7 +37,6 @@ #include "cpu/testers/rubytest/CheckTable.hh" #include "mem/mem_object.hh" #include "mem/packet.hh" -#include "mem/ruby/common/DataBlock.hh" #include "mem/ruby/common/Global.hh" #include "mem/ruby/common/SubBlock.hh" #include "mem/ruby/system/RubyPort.hh" diff -r 31a04e5ac4be -r 68374d55ea98 src/mem/protocol/MESI_CMP_directory-L1cache.sm --- a/src/mem/protocol/MESI_CMP_directory-L1cache.sm Sat Jan 22 21:48:06 2011 -0800 +++ b/src/mem/protocol/MESI_CMP_directory-L1cache.sm Mon Jan 24 22:28:54 2011 -0600 @@ -199,7 +199,9 @@ return Event:Load; } else if (type == CacheRequestType:IFETCH) { return Event:Ifetch; - } else if ((type == CacheRequestType:ST) || (type == CacheRequestType:ATOMIC)) { + } else if ((type == CacheRequestType:ST) || + (type == CacheRequestType:Locked_Read) || + (type == CacheRequestType:Locked_Write)) { return Event:Store; } else { error("Invalid CacheRequestType"); @@ -278,9 +280,9 @@ } // Mandatory Queue betweens Node's CPU and it's L1 caches - in_port(mandatoryQueue_in, CacheMsg, mandatoryQueue, desc="...") { + in_port(mandatoryQueue_in, RubyRequest, mandatoryQueue, desc="...") { if (mandatoryQueue_in.isReady()) { - peek(mandatoryQueue_in, CacheMsg, block_on="LineAddress") { + peek(mandatoryQueue_in, RubyRequest, block_on="LineAddress") { // Check for data access to blocks in I-cache and ifetchs to blocks in D-cache @@ -346,7 +348,7 @@ // ACTIONS action(a_issueGETS, "a", desc="Issue GETS") { - peek(mandatoryQueue_in, CacheMsg) { + peek(mandatoryQueue_in, RubyRequest) { enqueue(requestIntraChipL1Network_out, RequestMsg, latency=l1_request_latency) { out_msg.Address := address; out_msg.Type := CoherenceRequestType:GETS; @@ -363,7 +365,7 @@ } action(ai_issueGETINSTR, "ai", desc="Issue GETINSTR") { - peek(mandatoryQueue_in, CacheMsg) { + peek(mandatoryQueue_in, RubyRequest) { enqueue(requestIntraChipL1Network_out, RequestMsg, latency=l1_request_latency) { out_msg.Address := address; out_msg.Type := CoherenceRequestType:GET_INSTR; @@ -381,7 +383,7 @@ action(b_issueGETX, "b", desc="Issue GETX") { - peek(mandatoryQueue_in, CacheMsg) { + peek(mandatoryQueue_in, RubyRequest) { enqueue(requestIntraChipL1Network_out, RequestMsg, latency=l1_request_latency) { out_msg.Address := address; out_msg.Type := CoherenceRequestType:GETX; @@ -399,7 +401,7 @@ } action(c_issueUPGRADE, "c", desc="Issue GETX") { - peek(mandatoryQueue_in, CacheMsg) { + peek(mandatoryQueue_in, RubyRequest) { enqueue(requestIntraChipL1Network_out, RequestMsg, latency= l1_request_latency) { out_msg.Address := address; out_msg.Type := CoherenceRequestType:UPGRADE; diff -r 31a04e5ac4be -r 68374d55ea98 src/mem/protocol/MI_example-cache.sm --- a/src/mem/protocol/MI_example-cache.sm Sat Jan 22 21:48:06 2011 -0800 +++ b/src/mem/protocol/MI_example-cache.sm Mon Jan 24 22:28:54 2011 -0600 @@ -89,7 +89,9 @@ return Event:Load; } else if (type == CacheRequestType:IFETCH) { return Event:Ifetch; - } else if ((type == CacheRequestType:ST) || (type == CacheRequestType:ATOMIC)) { + } else if ((type == CacheRequestType:ST) || + (type == CacheRequestType:Locked_Read) || + (type == CacheRequestType:Locked_Write)) { return Event:Store; } else { error("Invalid CacheRequestType"); @@ -186,9 +188,9 @@ } // Mandatory Queue - in_port(mandatoryQueue_in, CacheMsg, mandatoryQueue, desc="...") { + in_port(mandatoryQueue_in, RubyRequest, mandatoryQueue, desc="...") { if (mandatoryQueue_in.isReady()) { - peek(mandatoryQueue_in, CacheMsg, block_on="LineAddress") { + peek(mandatoryQueue_in, RubyRequest, block_on="LineAddress") { Entry cache_entry := getCacheEntry(in_msg.LineAddress); if (is_invalid(cache_entry) && @@ -286,7 +288,7 @@ } action(p_profileMiss, "p", desc="Profile cache miss") { - peek(mandatoryQueue_in, CacheMsg) { + peek(mandatoryQueue_in, RubyRequest) { cacheMemory.profileMiss(in_msg); } } diff -r 31a04e5ac4be -r 68374d55ea98 src/mem/protocol/MOESI_CMP_directory-L1cache.sm --- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm Sat Jan 22 21:48:06 2011 -0800 +++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm Mon Jan 24 22:28:54 2011 -0600 @@ -215,7 +215,9 @@ return Event:Load; } else if (type == CacheRequestType:IFETCH) { return Event:Ifetch; - } else if ((type == CacheRequestType:ST) || (type == CacheRequestType:ATOMIC)) { + } else if ((type == CacheRequestType:ST) || + (type == CacheRequestType:Locked_Read) || + (type == CacheRequestType:Locked_Write)) { return Event:Store; } else { error("Invalid CacheRequestType"); @@ -329,9 +331,9 @@ // Nothing from the unblock network // Mandatory Queue betweens Node's CPU and it's L1 caches - in_port(mandatoryQueue_in, CacheMsg, mandatoryQueue, desc="...") { + in_port(mandatoryQueue_in, RubyRequest, mandatoryQueue, desc="...") { if (mandatoryQueue_in.isReady()) { - peek(mandatoryQueue_in, CacheMsg, block_on="LineAddress") { + peek(mandatoryQueue_in, RubyRequest, block_on="LineAddress") { // Check for data access to blocks in I-cache and ifetchs to blocks in D-cache @@ -406,7 +408,7 @@ // ACTIONS action(a_issueGETS, "a", desc="Issue GETS") { - peek(mandatoryQueue_in, CacheMsg) { + peek(mandatoryQueue_in, RubyRequest) { enqueue(requestNetwork_out, RequestMsg, latency= request_latency) { out_msg.Address := address; out_msg.Type := CoherenceRequestType:GETS; @@ -421,7 +423,7 @@ } action(b_issueGETX, "b", desc="Issue GETX") { - peek(mandatoryQueue_in, CacheMsg) { + peek(mandatoryQueue_in, RubyRequest) { enqueue(requestNetwork_out, RequestMsg, latency=request_latency) { out_msg.Address := address; out_msg.Type := CoherenceRequestType:GETX; @@ -818,7 +820,7 @@ action(uu_profileMiss, "\u", desc="Profile the demand miss") { - peek(mandatoryQueue_in, CacheMsg) { + peek(mandatoryQueue_in, RubyRequest) { // profile_miss(in_msg); } } diff -r 31a04e5ac4be -r 68374d55ea98 src/mem/protocol/MOESI_CMP_token-L1cache.sm --- a/src/mem/protocol/MOESI_CMP_token-L1cache.sm Sat Jan 22 21:48:06 2011 -0800 +++ b/src/mem/protocol/MOESI_CMP_token-L1cache.sm Mon Jan 24 22:28:54 2011 -0600 @@ -363,7 +363,8 @@ return Event:Ifetch; } else if (type == CacheRequestType:ST) { return Event:Store; - } else if (type == CacheRequestType:ATOMIC) { + } else if (type == CacheRequestType:Locked_Read || + type == CacheRequestType:Locked_Write) { if (no_mig_atomic) { return Event:Atomic; } else { @@ -377,7 +378,9 @@ AccessType cache_request_type_to_access_type(CacheRequestType type) { if ((type == CacheRequestType:LD) || (type == CacheRequestType:IFETCH)) { return AccessType:Read; - } else if ((type == CacheRequestType:ST) || (type == CacheRequestType:ATOMIC)) { + } else if ((type == CacheRequestType:ST) || + (type == CacheRequestType:Locked_Read) || + (type == CacheRequestType:Locked_Write)) { return AccessType:Write; } else { error("Invalid CacheRequestType"); @@ -640,9 +643,9 @@ } // Mandatory Queue - in_port(mandatoryQueue_in, CacheMsg, mandatoryQueue, desc="...") { + in_port(mandatoryQueue_in, RubyRequest, mandatoryQueue, desc="...") { if (mandatoryQueue_in.isReady()) { - peek(mandatoryQueue_in, CacheMsg, block_on="LineAddress") { + peek(mandatoryQueue_in, RubyRequest, block_on="LineAddress") { // Check for data access to blocks in I-cache and ifetchs to blocks in D-cache TBE tbe := L1_TBEs[in_msg.LineAddress]; @@ -1327,10 +1330,11 @@ L1_TBEs.allocate(address); set_tbe(L1_TBEs[address]); tbe.IssueCount := 0; - peek(mandatoryQueue_in, CacheMsg) { + peek(mandatoryQueue_in, RubyRequest) { tbe.PC := in_msg.ProgramCounter; tbe.AccessType := cache_request_type_to_access_type(in_msg.Type); - if (in_msg.Type == CacheRequestType:ATOMIC) { + if ((in_msg.Type == CacheRequestType:Locked_Read) || + (in_msg.Type == CacheRequestType:Locked_Write)) { tbe.IsAtomic := true; } tbe.Prefetch := in_msg.Prefetch; @@ -1511,7 +1515,7 @@ } action(uu_profileMiss, "\u", desc="Profile the demand miss") { - peek(mandatoryQueue_in, CacheMsg) { + peek(mandatoryQueue_in, RubyRequest) { if (L1DcacheMemory.isTagPresent(address)) { L1DcacheMemory.profileMiss(in_msg); } else { diff -r 31a04e5ac4be -r 68374d55ea98 src/mem/protocol/MOESI_CMP_token-dir.sm --- a/src/mem/protocol/MOESI_CMP_token-dir.sm Sat Jan 22 21:48:06 2011 -0800 +++ b/src/mem/protocol/MOESI_CMP_token-dir.sm Mon Jan 24 22:28:54 2011 -0600 @@ -424,7 +424,7 @@ out_msg.Destination.add(map_Address_to_Directory(address)); out_msg.MessageSize := MessageSizeType:Persistent_Control; out_msg.Prefetch := PrefetchBit:No; - out_msg.AccessMode := AccessModeType:SupervisorMode; + out_msg.AccessMode := AccessModeType:Supervisor; } markPersistentEntries(address); starving := true; @@ -466,7 +466,7 @@ out_msg.RetryNum := 0; out_msg.MessageSize := MessageSizeType:Broadcast_Control; out_msg.Prefetch := PrefetchBit:No; - out_msg.AccessMode := AccessModeType:SupervisorMode; + out_msg.AccessMode := AccessModeType:Supervisor; } } } @@ -494,7 +494,7 @@ out_msg.Destination.add(map_Address_to_Directory(address)); out_msg.MessageSize := MessageSizeType:Persistent_Control; out_msg.Prefetch := PrefetchBit:No; - out_msg.AccessMode := AccessModeType:SupervisorMode; + out_msg.AccessMode := AccessModeType:Supervisor; } markPersistentEntries(address); starving := true; @@ -532,7 +532,7 @@ out_msg.RetryNum := 0; out_msg.MessageSize := MessageSizeType:Broadcast_Control; out_msg.Prefetch := PrefetchBit:No; - out_msg.AccessMode := AccessModeType:SupervisorMode; + out_msg.AccessMode := AccessModeType:Supervisor; } } } diff -r 31a04e5ac4be -r 68374d55ea98 src/mem/protocol/MOESI_hammer-cache.sm --- a/src/mem/protocol/MOESI_hammer-cache.sm Sat Jan 22 21:48:06 2011 -0800 +++ b/src/mem/protocol/MOESI_hammer-cache.sm Mon Jan 24 22:28:54 2011 -0600 @@ -233,7 +233,9 @@ return Event:Load; } else if (type == CacheRequestType:IFETCH) { return Event:Ifetch; - } else if ((type == CacheRequestType:ST) || (type == CacheRequestType:ATOMIC)) { + } else if ((type == CacheRequestType:ST) || + (type == CacheRequestType:Locked_Read) || + (type == CacheRequestType:Locked_Write)) { return Event:Store; } else { error("Invalid CacheRequestType"); @@ -366,9 +368,9 @@ // Nothing from the unblock network // Mandatory Queue - in_port(mandatoryQueue_in, CacheMsg, mandatoryQueue, desc="...") { + in_port(mandatoryQueue_in, RubyRequest, mandatoryQueue, desc="...") { if (mandatoryQueue_in.isReady()) { - peek(mandatoryQueue_in, CacheMsg, block_on="LineAddress") { + peek(mandatoryQueue_in, RubyRequest, block_on="LineAddress") { // Check for data access to blocks in I-cache and ifetchs to blocks in D-cache TBE tbe := TBEs[in_msg.LineAddress]; @@ -696,12 +698,13 @@ action(hh_store_hit, "\h", desc="Notify sequencer that store completed.") { assert(is_valid(cache_entry)); DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk); - peek(mandatoryQueue_in, CacheMsg) { + peek(mandatoryQueue_in, RubyRequest) { sequencer.writeCallback(address, testAndClearLocalHit(cache_entry), cache_entry.DataBlk); cache_entry.Dirty := true; - if (in_msg.Type == CacheRequestType:ATOMIC) { + if (in_msg.Type == CacheRequestType:Locked_Read || + in_msg.Type == CacheRequestType:Locked_Write) { cache_entry.AtomicAccessed := true; } } @@ -987,7 +990,7 @@ } action(uu_profileMiss, "\u", desc="Profile the demand miss") { - peek(mandatoryQueue_in, CacheMsg) { + peek(mandatoryQueue_in, RubyRequest) { if (L1IcacheMemory.isTagPresent(address)) { L1IcacheMemory.profileMiss(in_msg); } else if (L1DcacheMemory.isTagPresent(address)) { diff -r 31a04e5ac4be -r 68374d55ea98 src/mem/protocol/RubySlicc_Exports.sm --- a/src/mem/protocol/RubySlicc_Exports.sm Sat Jan 22 21:48:06 2011 -0800 +++ b/src/mem/protocol/RubySlicc_Exports.sm Mon Jan 24 22:28:54 2011 -0600 @@ -99,14 +99,17 @@ // CacheRequestType enumeration(CacheRequestType, desc="...", default="CacheRequestType_NULL") { - LD, desc="Load"; - ST, desc="Store"; - ATOMIC, desc="Atomic Load/Store"; - IFETCH, desc="Instruction fetch"; - IO, desc="I/O"; - REPLACEMENT, desc="Replacement"; - COMMIT, desc="Commit version"; - NULL, desc="Invalid request type"; + LD, desc="Load"; + ST, desc="Store"; + IFETCH, desc="Instruction fetch"; + IO, desc="I/O"; + Locked_Read, desc=""; + Locked_Write, desc=""; + REPLACEMENT, desc="Replacement"; + RMW_Read, desc=""; + RMW_Write, desc=""; + COMMIT, desc="Commit version"; + NULL, desc="Invalid request type"; } enumeration(SequencerRequestType, desc="...", default="SequencerRequestType_NULL") { @@ -187,9 +190,10 @@ } // AccessModeType -enumeration(AccessModeType, default="AccessModeType_UserMode", desc="...") { - SupervisorMode, desc="Supervisor mode"; - UserMode, desc="User mode"; +enumeration(AccessModeType, default="AccessModeType_User", desc="...") { + Supervisor, desc="Supervisor mode"; + User, desc="User mode"; + Device, desc="Device mode"; } enumeration(PrefetchBit, default="PrefetchBit_No", desc="...") { @@ -200,17 +204,6 @@ } // CacheMsg -structure(CacheMsg, desc="...", interface="Message") { - Address LineAddress, desc="Line address for this request"; - Address PhysicalAddress, desc="Physical address for this request"; - CacheRequestType Type, desc="Type of request (LD, ST, etc)"; - Address ProgramCounter, desc="Program counter of the instruction that caused the miss"; - AccessModeType AccessMode, desc="user/supervisor access type"; - int Size, desc="size in bytes of access"; - PrefetchBit Prefetch, desc="Is this a prefetch request"; -} - -// CacheMsg structure(SequencerMsg, desc="...", interface="Message") { Address LineAddress, desc="Line address for this request"; Address PhysicalAddress, desc="Physical address for this request"; diff -r 31a04e5ac4be -r 68374d55ea98 src/mem/protocol/RubySlicc_Profiler.sm --- a/src/mem/protocol/RubySlicc_Profiler.sm Sat Jan 22 21:48:06 2011 -0800 +++ b/src/mem/protocol/RubySlicc_Profiler.sm Mon Jan 24 22:28:54 2011 -0600 @@ -34,10 +34,10 @@ void profileMemoryCLBsize(int size, int numStaleI); // used by 2level exclusive cache protocols -void profile_miss(CacheMsg msg); +void profile_miss(RubyRequest msg); // used by non-fast path protocols -void profile_L1Cache_miss(CacheMsg msg, NodeID l1cacheID); +void profile_L1Cache_miss(RubyRequest msg, NodeID l1cacheID); // used by CMP protocols void profile_request(std::string L1CacheStateStr, std::string L2CacheStateStr, diff -r 31a04e5ac4be -r 68374d55ea98 src/mem/protocol/RubySlicc_Types.sm --- a/src/mem/protocol/RubySlicc_Types.sm Sat Jan 22 21:48:06 2011 -0800 +++ b/src/mem/protocol/RubySlicc_Types.sm Mon Jan 24 22:28:54 2011 -0600 @@ -98,6 +98,16 @@ MachineID smallestElement(MachineType); } +external_type(RubyRequest, desc="...", interface="Message") { + Address LineAddress; + Address PhysicalAddress; + CacheRequestType Type; + Address ProgramCounter; + AccessModeType AccessMode; + int Size; + PrefetchBit Prefetch; +} + external_type(Sequencer) { void readCallback(Address, DataBlock); void readCallback(Address, GenericMachineType, DataBlock); @@ -128,7 +138,7 @@ void deallocate(Address); AbstractCacheEntry lookup(Address); bool isTagPresent(Address); - void profileMiss(CacheMsg); + void profileMiss(RubyRequest); void profileGenericRequest(GenericRequestType, AccessModeType, @@ -165,7 +175,3 @@ bool isSet(Address, int); int getCount(Address, int); } - - - - diff -r 31a04e5ac4be -r 68374d55ea98 src/mem/ruby/SConscript --- a/src/mem/ruby/SConscript Sat Jan 22 21:48:06 2011 -0800 +++ b/src/mem/ruby/SConscript Mon Jan 24 22:28:54 2011 -0600 @@ -43,8 +43,6 @@ if not env['RUBY']: Return() -Source('libruby.cc') - def do_embed_text(target, source, env): """convert a text file into a file that can be embedded in C using an #include statement, that defines a \"const char *\" pointing @@ -95,6 +93,7 @@ MakeInclude('slicc_interface/AbstractProtocol.hh') MakeInclude('slicc_interface/Message.hh') MakeInclude('slicc_interface/NetworkMessage.hh') +MakeInclude('slicc_interface/RubyRequest.hh') # External types MakeInclude('buffers/MessageBuffer.hh') diff -r 31a04e5ac4be -r 68374d55ea98 src/mem/ruby/common/Address.hh --- a/src/mem/ruby/common/Address.hh Sat Jan 22 21:48:06 2011 -0800 +++ b/src/mem/ruby/common/Address.hh Mon Jan 24 22:28:54 2011 -0600 @@ -29,13 +29,13 @@ #ifndef __MEM_RUBY_COMMON_ADDRESS_HH__ #define __MEM_RUBY_COMMON_ADDRESS_HH__ +#include #include #include "base/hashmap.hh" #include "mem/ruby/common/Global.hh" #include "mem/ruby/system/MachineID.hh" #include "mem/ruby/system/NodeID.hh" -#include "mem/ruby/system/System.hh" const int ADDRESS_WIDTH = 64; // address width in bytes @@ -67,31 +67,10 @@ physical_address_t maskHighOrderBits(int number) const; physical_address_t shiftLowOrderBits(int number) const; - physical_address_t - getLineAddress() const - { - return bitSelect(RubySystem::getBlockSizeBits(), ADDRESS_WIDTH); - } - - physical_address_t - getOffset() const - { - return bitSelect(0, RubySystem::getBlockSizeBits() - 1); - } - - void - makeLineAddress() - { - m_address = maskLowOrderBits(RubySystem::getBlockSizeBits()); - } - - // returns the next stride address based on line address - void - makeNextStrideAddress(int stride) - { - m_address = maskLowOrderBits(RubySystem::getBlockSizeBits()) - + RubySystem::getBlockSizeBytes()*stride; - } + physical_address_t getLineAddress() const; + physical_address_t getOffset() const; + void makeLineAddress(); + void makeNextStrideAddress(int stride); int getBankSetNum() const; int getBankSetDist() const; @@ -224,49 +203,6 @@ return (m_address >> number); } -inline integer_t -Address::memoryModuleIndex() const -{ - integer_t index = - bitSelect(RubySystem::getBlockSizeBits() + - RubySystem::getMemorySizeBits(), ADDRESS_WIDTH); - assert (index >= 0); - return index; - - // Index indexHighPortion = - // address.bitSelect(MEMORY_SIZE_BITS - 1, - // PAGE_SIZE_BITS + NUMBER_OF_MEMORY_MODULE_BITS); - // Index indexLowPortion = - // address.bitSelect(DATA_BLOCK_BITS, PAGE_SIZE_BITS - 1); - // - // Index index = indexLowPortion | - // (indexHighPortion << (PAGE_SIZE_BITS - DATA_BLOCK_BITS)); - - /* - Round-robin mapping of addresses, at page size granularity - -ADDRESS_WIDTH MEMORY_SIZE_BITS PAGE_SIZE_BITS DATA_BLOCK_BITS - | | | | - \ / \ / \ / \ / 0 - ----------------------------------------------------------------------- - | unused |xxxxxxxxxxxxxxx| |xxxxxxxxxxxxxxx| | - | |xxxxxxxxxxxxxxx| |xxxxxxxxxxxxxxx| | - ----------------------------------------------------------------------- - indexHighPortion indexLowPortion - <-------> - NUMBER_OF_MEMORY_MODULE_BITS - */ -} - -inline void -Address::print(std::ostream& out) const -{ - using namespace std; - out << "[" << hex << "0x" << m_address << "," << " line 0x" - << maskLowOrderBits(RubySystem::getBlockSizeBits()) << dec << "]" - << flush; -} - class Address; namespace __hash_namespace { template <> struct hash
diff -r 31a04e5ac4be -r 68374d55ea98 src/mem/ruby/common/Address.cc --- a/src/mem/ruby/common/Address.cc Sat Jan 22 21:48:06 2011 -0800 +++ b/src/mem/ruby/common/Address.cc Mon Jan 24 22:28:54 2011 -0600 @@ -27,6 +27,7 @@ */ #include "mem/ruby/common/Address.hh" +#include "mem/ruby/system/System.hh" void Address::output(std::ostream& out) const @@ -64,3 +65,71 @@ return *this; } +physical_address_t +Address::getLineAddress() const +{ + return bitSelect(RubySystem::getBlockSizeBits(), ADDRESS_WIDTH); +} + +physical_address_t +Address::getOffset() const +{ + return bitSelect(0, RubySystem::getBlockSizeBits() - 1); +} + +void +Address::makeLineAddress() +{ + m_address = maskLowOrderBits(RubySystem::getBlockSizeBits()); +} + +// returns the next stride address based on line address +void +Address::makeNextStrideAddress(int stride) +{ + m_address = maskLowOrderBits(RubySystem::getBlockSizeBits()) + + RubySystem::getBlockSizeBytes()*stride; +} + +integer_t +Address::memoryModuleIndex() const +{ + integer_t index = + bitSelect(RubySystem::getBlockSizeBits() + + RubySystem::getMemorySizeBits(), ADDRESS_WIDTH); + assert (index >= 0); + return index; + + // Index indexHighPortion = + // address.bitSelect(MEMORY_SIZE_BITS - 1, + // PAGE_SIZE_BITS + NUMBER_OF_MEMORY_MODULE_BITS); + // Index indexLowPortion = + // address.bitSelect(DATA_BLOCK_BITS, PAGE_SIZE_BITS - 1); + // + // Index index = indexLowPortion | + // (indexHighPortion << (PAGE_SIZE_BITS - DATA_BLOCK_BITS)); + + /* + Round-robin mapping of addresses, at page size granularity + +ADDRESS_WIDTH MEMORY_SIZE_BITS PAGE_SIZE_BITS DATA_BLOCK_BITS + | | | | + \ / \ / \ / \ / 0 + ----------------------------------------------------------------------- + | unused |xxxxxxxxxxxxxxx| |xxxxxxxxxxxxxxx| | + | |xxxxxxxxxxxxxxx| |xxxxxxxxxxxxxxx| | + ----------------------------------------------------------------------- + indexHighPortion indexLowPortion + <-------> + NUMBER_OF_MEMORY_MODULE_BITS + */ +} + +void +Address::print(std::ostream& out) const +{ + using namespace std; + out << "[" << hex << "0x" << m_address << "," << " line 0x" + << maskLowOrderBits(RubySystem::getBlockSizeBits()) << dec << "]" + << flush; +} diff -r 31a04e5ac4be -r 68374d55ea98 src/mem/ruby/common/DataBlock.hh --- a/src/mem/ruby/common/DataBlock.hh Sat Jan 22 21:48:06 2011 -0800 +++ b/src/mem/ruby/common/DataBlock.hh Mon Jan 24 22:28:54 2011 -0600 @@ -33,7 +33,6 @@ #include #include "mem/ruby/common/Global.hh" -#include "mem/ruby/system/System.hh" class DataBlock { @@ -43,12 +42,7 @@ alloc(); } - DataBlock(const DataBlock &cp) - { - m_data = new uint8[RubySystem::getBlockSizeBytes()]; - memcpy(m_data, cp.m_data, RubySystem::getBlockSizeBytes()); - m_alloc = true; - } + DataBlock(const DataBlock &cp); ~DataBlock() { @@ -85,53 +79,12 @@ m_alloc = false; } -inline void -DataBlock::alloc() -{ - m_data = new uint8[RubySystem::getBlockSizeBytes()]; - m_alloc = true; - clear(); -} - -inline void -DataBlock::clear() -{ - memset(m_data, 0, RubySystem::getBlockSizeBytes()); -} - -inline bool -DataBlock::equal(const DataBlock& obj) const -{ - return !memcmp(m_data, obj.m_data, RubySystem::getBlockSizeBytes()); -} - -inline void -DataBlock::print(std::ostream& out) const -{ - using namespace std; - - int size = RubySystem::getBlockSizeBytes(); - out << "[ "; - for (int i = 0; i < size; i++) { - out << setw(2) << setfill('0') << hex << "0x" << (int)m_data[i] << " "; - out << setfill(' '); - } - out << dec << "]" << flush; -} - inline uint8 DataBlock::getByte(int whichByte) const { return m_data[whichByte]; } -inline const uint8* -DataBlock::getData(int offset, int len) const -{ - assert(offset + len <= RubySystem::getBlockSizeBytes()); - return &m_data[offset]; -} - inline void DataBlock::setByte(int whichByte, uint8 data) { @@ -139,13 +92,6 @@ } inline void -DataBlock::setData(uint8* data, int offset, int len) -{ - assert(offset + len <= RubySystem::getBlockSizeBytes()); - memcpy(&m_data[offset], data, len); -} - -inline void DataBlock::copyPartial(const DataBlock & dblk, int offset, int len) { setData(&dblk.m_data[offset], offset, len); diff -r 31a04e5ac4be -r 68374d55ea98 src/mem/ruby/common/DataBlock.cc --- a/src/mem/ruby/common/DataBlock.cc Sat Jan 22 21:48:06 2011 -0800 +++ b/src/mem/ruby/common/DataBlock.cc Mon Jan 24 22:28:54 2011 -0600 @@ -27,6 +27,62 @@ */ #include "mem/ruby/common/DataBlock.hh" +#include "mem/ruby/system/System.hh" + +DataBlock::DataBlock(const DataBlock &cp) +{ + m_data = new uint8[RubySystem::getBlockSizeBytes()]; + memcpy(m_data, cp.m_data, RubySystem::getBlockSizeBytes()); + m_alloc = true; +} + +void +DataBlock::alloc() +{ + m_data = new uint8[RubySystem::getBlockSizeBytes()]; + m_alloc = true; + clear(); +} + +void +DataBlock::clear() +{ + memset(m_data, 0, RubySystem::getBlockSizeBytes()); +} + +bool +DataBlock::equal(const DataBlock& obj) const +{ + return !memcmp(m_data, obj.m_data, RubySystem::getBlockSizeBytes()); +} + +void +DataBlock::print(std::ostream& out) const +{ + using namespace std; + + int size = RubySystem::getBlockSizeBytes(); + out << "[ "; + for (int i = 0; i < size; i++) { + out << setw(2) << setfill('0') << hex << "0x" << (int)m_data[i] << " "; + out << setfill(' '); + } + out << dec << "]" << flush; +} + +const uint8* +DataBlock::getData(int offset, int len) const +{ + assert(offset + len <= RubySystem::getBlockSizeBytes()); + return &m_data[offset]; +} + +void +DataBlock::setData(uint8* data, int offset, int len) +{ + assert(offset + len <= RubySystem::getBlockSizeBytes()); + memcpy(&m_data[offset], data, len); +} DataBlock & DataBlock::operator=(const DataBlock & obj) diff -r 31a04e5ac4be -r 68374d55ea98 src/mem/ruby/filters/BlockBloomFilter.cc --- a/src/mem/ruby/filters/BlockBloomFilter.cc Sat Jan 22 21:48:06 2011 -0800 +++ b/src/mem/ruby/filters/BlockBloomFilter.cc Mon Jan 24 22:28:54 2011 -0600 @@ -29,6 +29,7 @@ #include "base/intmath.hh" #include "base/str.hh" #include "mem/ruby/filters/BlockBloomFilter.hh" +#include "mem/ruby/system/System.hh" using namespace std; diff -r 31a04e5ac4be -r 68374d55ea98 src/mem/ruby/filters/BulkBloomFilter.cc --- a/src/mem/ruby/filters/BulkBloomFilter.cc Sat Jan 22 21:48:06 2011 -0800 +++ b/src/mem/ruby/filters/BulkBloomFilter.cc Mon Jan 24 22:28:54 2011 -0600 @@ -31,6 +31,7 @@ #include "base/intmath.hh" #include "base/str.hh" #include "mem/ruby/filters/BulkBloomFilter.hh" +#include "mem/ruby/system/System.hh" using namespace std; diff -r 31a04e5ac4be -r 68374d55ea98 src/mem/ruby/filters/LSB_CountingBloomFilter.cc --- a/src/mem/ruby/filters/LSB_CountingBloomFilter.cc Sat Jan 22 21:48:06 2011 -0800 +++ b/src/mem/ruby/filters/LSB_CountingBloomFilter.cc Mon Jan 24 22:28:54 2011 -0600 @@ -29,6 +29,7 @@ #include "base/intmath.hh" #include "base/str.hh" #include "mem/ruby/filters/LSB_CountingBloomFilter.hh" +#include "mem/ruby/system/System.hh" using namespace std; diff -r 31a04e5ac4be -r 68374d55ea98 src/mem/ruby/filters/MultiGrainBloomFilter.cc --- a/src/mem/ruby/filters/MultiGrainBloomFilter.cc Sat Jan 22 21:48:06 2011 -0800 +++ b/src/mem/ruby/filters/MultiGrainBloomFilter.cc Mon Jan 24 22:28:54 2011 -0600 @@ -29,6 +29,7 @@ #include "base/intmath.hh" #include "base/str.hh" #include "mem/ruby/filters/MultiGrainBloomFilter.hh" +#include "mem/ruby/system/System.hh" using namespace std; diff -r 31a04e5ac4be -r 68374d55ea98 src/mem/ruby/filters/NonCountingBloomFilter.cc --- a/src/mem/ruby/filters/NonCountingBloomFilter.cc Sat Jan 22 21:48:06 2011 -0800 +++ b/src/mem/ruby/filters/NonCountingBloomFilter.cc Mon Jan 24 22:28:54 2011 -0600 @@ -29,6 +29,7 @@ #include "base/intmath.hh" #include "base/str.hh" #include "mem/ruby/filters/NonCountingBloomFilter.hh" +#include "mem/ruby/system/System.hh" using namespace std; diff -r 31a04e5ac4be -r 68374d55ea98 src/mem/ruby/libruby.hh --- a/src/mem/ruby/libruby.hh Sat Jan 22 21:48:06 2011 -0800 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,178 +0,0 @@ -/* - * Copyright (c) 2009 Mark D. Hill and David A. Wood - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __MEM_RUBY_LIBRUBY_HH__ -#define __MEM_RUBY_LIBRUBY_HH__ - -#include - -#include "base/types.hh" -#include "mem/packet.hh" - -typedef void* RubyPortHandle; -enum RubyRequestType { - RubyRequestType_NULL, - RubyRequestType_IFETCH, - RubyRequestType_LD, - RubyRequestType_ST, - RubyRequestType_Locked_Read, - RubyRequestType_Locked_Write, - RubyRequestType_RMW_Read, - RubyRequestType_RMW_Write, - RubyRequestType_NUM -}; - -enum RubyAccessMode { - RubyAccessMode_User, - RubyAccessMode_Supervisor, - RubyAccessMode_Device -}; - -struct RubyRequest -{ - uint64_t paddr; - uint8_t* data; - int len; - uint64_t pc; - RubyRequestType type; - RubyAccessMode access_mode; - PacketPtr pkt; - unsigned proc_id; - - RubyRequest() {} - RubyRequest(uint64_t _paddr, - uint8_t* _data, - int _len, - uint64_t _pc, - RubyRequestType _type, - RubyAccessMode _access_mode, - PacketPtr _pkt, - unsigned _proc_id = 100) - : paddr(_paddr), - data(_data), - len(_len), - pc(_pc), - type(_type), - access_mode(_access_mode), - pkt(_pkt), - proc_id(_proc_id) - {} -}; - -std::ostream& operator<<(std::ostream& out, const RubyRequest& obj); -std::ostream& operator<<(std::ostream& out, const RubyRequestType& obj); - -/** - * Initialize the system. cfg_file is a Ruby-lang configuration script - */ -void libruby_init(const char* cfg_file); - -/** - * Tear down a configured system. Must be invoked after a call to - * libruby_init. - */ -void libruby_destroy(); - -/** - * Print the last error encountered by ruby. Currently unimplemented. - */ -const char* libruby_last_error(); - -/** - * Retrieve a handle to a RubyPort object, identified by name in the - * configuration. You also pass in the callback function you want - * this port to use when a request completes. Only one handle to a - * port is allowed at a time. - */ -RubyPortHandle libruby_get_port(const char* name, - void (*hit_callback)(int64_t access_id)); - -/** - * Retrieve a handle to a RubyPort object, identified by name in the - * configuration. - */ -RubyPortHandle libruby_get_port_by_name(const char* name); - -/** - * issue_request returns a unique access_id to identify the ruby - * transaction. This access_id is later returned to the caller via - * hit_callback (passed to libruby_get_port) - */ -int64_t libruby_issue_request(RubyPortHandle p, struct RubyRequest request); - -/** - * writes data directly into Ruby's data array. Note that this - * ignores caches, and should be considered incoherent after - * simulation starts. - */ -void libruby_write_ram(uint64_t paddr, uint8_t *data, int len); - -/** - * reads data directory from Ruby's data array. Note that this - * ignores caches, and should be considered incoherent after - * simulation starts - */ -void libruby_read_ram(uint64_t paddr, uint8_t *data, int len); - -/** - * tick the system n cycles. Eventually, will return the number of - * cycles until the next event, but for now it always returns 0 - */ -int libruby_tick(int n); - -/** - * self explainitory - */ -void libruby_print_config(std::ostream &out); - -/** - * self explainitory - */ -void libruby_print_stats(std::ostream &out); - -/** - * does not return until done - */ -void libruby_playback_trace(char *trace_filename); - -/* - * enables the tracer and opens the trace file - */ -void libruby_start_tracing(char *record_filename); - -/* - * closes the trace file - */ -void libruby_stop_tracing(); - -/** - * get time - */ -uint64_t libruby_get_time(); - -#endif // __MEM_RUBY_LIBRUBY_HH__ diff -r 31a04e5ac4be -r 68374d55ea98 src/mem/ruby/libruby.cc --- a/src/mem/ruby/libruby.cc Sat Jan 22 21:48:06 2011 -0800 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,263 +0,0 @@ -/* - * Copyright (c) 2009 Mark D. Hill and David A. Wood - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include - -#include "config/gems_root.hh" -#include "mem/ruby/common/Address.hh" -#include "mem/ruby/eventqueue/RubyEventQueue.hh" -#include "mem/ruby/libruby_internal.hh" -#include "mem/ruby/recorder/Tracer.hh" -#include "mem/ruby/system/MemoryVector.hh" -#include "mem/ruby/system/RubyPort.hh" -#include "mem/ruby/system/System.hh" - -using namespace std; - -string -RubyRequestType_to_string(const RubyRequestType& obj) -{ - switch(obj) { - case RubyRequestType_IFETCH: - return "IFETCH"; - case RubyRequestType_LD: - return "LD"; - case RubyRequestType_ST: - return "ST"; - case RubyRequestType_Locked_Read: - return "Locked_Read"; - case RubyRequestType_Locked_Write: - return "Locked_Write"; - case RubyRequestType_RMW_Read: - return "RMW_Read"; - case RubyRequestType_RMW_Write: - return "RMW_Write"; - case RubyRequestType_NULL: - default: - assert(0); - return ""; - } -} - -RubyRequestType -string_to_RubyRequestType(string str) -{ - if (str == "IFETCH") - return RubyRequestType_IFETCH; - else if (str == "LD") - return RubyRequestType_LD; - else if (str == "ST") - return RubyRequestType_ST; - else if (str == "Locked_Read") - return RubyRequestType_Locked_Read; - else if (str == "Locked_Write") - return RubyRequestType_Locked_Write; - else if (str == "RMW_Read") - return RubyRequestType_RMW_Read; - else if (str == "RMW_Write") - return RubyRequestType_RMW_Write; - else - assert(0); - return RubyRequestType_NULL; -} - -ostream& -operator<<(ostream& out, const RubyRequestType& obj) -{ - out << RubyRequestType_to_string(obj); - out << flush; - return out; -} - -ostream& -operator<<(ostream& out, const RubyRequest& obj) -{ - out << hex << "0x" << obj.paddr << " data: 0x" << flush; - for (int i = 0; i < obj.len; i++) { - out << (int)obj.data[i]; - } - out << dec << " type: " << RubyRequestType_to_string(obj.type) << endl; - return out; -} - -vector -tokenizeString(string str, string delims) -{ - vector tokens; - char* pch; - char* tmp; - const char* c_delims = delims.c_str(); - tmp = new char[str.length()+1]; - strcpy(tmp, str.c_str()); - pch = strtok(tmp, c_delims); - while (pch != NULL) { - string tmp_str(pch); - if (tmp_str == "null") tmp_str = ""; - tokens.push_back(tmp_str); - - pch = strtok(NULL, c_delims); - } - delete [] tmp; - return tokens; -} - -/* - * The current state of M5/Ruby integration breaks the libruby - * interface. This code is ifdef'd out for now so that we can move - * forward with the integration process for non-libruby uses. We'll - * have to go back and resolve the libruby compatibility issue at a - * later date. - */ -#if 0 -void -libruby_init(const char* cfg_filename) -{ - ifstream cfg_output(cfg_filename); - - vector * sys_conf = new vector; - - string line; - getline(cfg_output, line) ; - while ( !cfg_output.eof() ) { - vector tokens = tokenizeString(line, " "); - assert(tokens.size() >= 2); - vector argv; - for (size_t i=2; ipush_back(RubyObjConf(tokens[0], tokens[1], argv)); - tokens.clear(); - argv.clear(); - getline(cfg_output, line); - } - - RubySystem::create(*sys_conf); - delete sys_conf; -} -#endif - -RubyPortHandle -libruby_get_port(const char* port_name, - void (*hit_callback)(int64_t access_id)) -{ - // - // Fix me: Hit callback is now a non-static member function pointer of - // RubyPort and cannot be set to an arbitrary global function - // - return NULL;//static_cast(RubySystem::getPort(port_name, hit_callback)); -} - -RubyPortHandle libruby_get_port_by_name(const char* port_name) -{ - // - // Fix me: Ports should now be initialized using the python configuration - // system - // - return NULL;//static_cast(RubySystem::getPortOnly(port_name)); -} - -void -libruby_write_ram(uint64_t paddr, uint8_t* data, int len) -{ - RubySystem::getMemoryVector()->write(Address(paddr), data, len); -} - -void -libruby_read_ram(uint64_t paddr, uint8_t* data, int len) -{ - RubySystem::getMemoryVector()->read(Address(paddr), data, len); -} - -int64_t -libruby_issue_request(RubyPortHandle p, struct RubyRequest request) -{ - // - // Fix me: Ports should now be accessed using the python configuration - // system - // - return 0;//return static_cast(p)->makeRequest(request); -} - -int -libruby_tick(int n) -{ - RubyEventQueue *eventq = RubySystem::getEventQueue(); - eventq->triggerEvents(eventq->getTime() + n); - return 0; -} - -void -libruby_destroy() -{ -} - -const char* -libruby_last_error() -{ - return ""; -} - -void -libruby_print_config(ostream & out) -{ - RubySystem::printConfig(out); -} - -void -libruby_print_stats(ostream & out) -{ - RubySystem::printStats(out); -} -void -libruby_playback_trace(char * trace_filename) -{ - RubySystem::getTracer()->playbackTrace(trace_filename); -} - -void -libruby_start_tracing(char * record_filename) -{ - // start the trace - RubySystem::getTracer()->startTrace(record_filename); -} - -void -libruby_stop_tracing() -{ - // start the trace - RubySystem::getTracer()->stopTrace(); -} - -uint64_t -libruby_get_time() -{ - return RubySystem::getCycleCount(0); -} diff -r 31a04e5ac4be -r 68374d55ea98 src/mem/ruby/libruby_internal.hh --- a/src/mem/ruby/libruby_internal.hh Sat Jan 22 21:48:06 2011 -0800 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,41 +0,0 @@ -/* - * Copyright (c) 2009 Mark D. Hill and David A. Wood - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __MEM_RUBY_LIBRUBY_INTERNAL_HH__ -#define __MEM_RUBY_LIBRUBY_INTERNAL_HH__ - -#include -#include - -#include "mem/ruby/libruby.hh" - -std::string RubyRequestType_to_string(const RubyRequestType& obj); -RubyRequestType string_to_RubyRequestType(std::string); -std::ostream& operator<<(std::ostream& out, const RubyRequestType& obj); - -#endif // __MEM_RUBY_LIBRUBY_INTERNAL_HH__ diff -r 31a04e5ac4be -r 68374d55ea98 src/mem/ruby/profiler/AccessTraceForAddress.cc --- a/src/mem/ruby/profiler/AccessTraceForAddress.cc Sat Jan 22 21:48:06 2011 -0800 +++ b/src/mem/ruby/profiler/AccessTraceForAddress.cc Mon Jan 24 22:28:54 2011 -0600 @@ -64,7 +64,8 @@ { m_touched_by.add(cpu); m_total++; - if(type == CacheRequestType_ATOMIC) { + if(type == CacheRequestType_Locked_Read || + type == CacheRequestType_Locked_Write) { m_atomics++; } else if(type == CacheRequestType_LD){ m_loads++; @@ -74,7 +75,7 @@ // ERROR_MSG("Trying to add invalid access to trace"); } - if (access_mode == AccessModeType_UserMode) { + if (access_mode == AccessModeType_User) { m_user++; } diff -r 31a04e5ac4be -r 68374d55ea98 src/mem/ruby/profiler/AddressProfiler.hh --- a/src/mem/ruby/profiler/AddressProfiler.hh Sat Jan 22 21:48:06 2011 -0800 +++ b/src/mem/ruby/profiler/AddressProfiler.hh Mon Jan 24 22:28:54 2011 -0600 @@ -33,7 +33,6 @@ #include "base/hashmap.hh" #include "mem/protocol/AccessType.hh" -#include "mem/protocol/CacheMsg.hh" #include "mem/ruby/common/Address.hh" #include "mem/ruby/common/Global.hh" #include "mem/ruby/common/Histogram.hh" diff -r 31a04e5ac4be -r 68374d55ea98 src/mem/ruby/profiler/AddressProfiler.cc --- a/src/mem/ruby/profiler/AddressProfiler.cc Sat Jan 22 21:48:06 2011 -0800 +++ b/src/mem/ruby/profiler/AddressProfiler.cc Mon Jan 24 22:28:54 2011 -0600 @@ -29,7 +29,6 @@ #include #include "base/stl_helpers.hh" -#include "mem/protocol/CacheMsg.hh" #include "mem/ruby/profiler/AddressProfiler.hh" #include "mem/ruby/profiler/Profiler.hh" #include "mem/ruby/system/System.hh" diff -r 31a04e5ac4be -r 68374d55ea98 src/mem/ruby/profiler/Profiler.hh --- a/src/mem/ruby/profiler/Profiler.hh Sat Jan 22 21:48:06 2011 -0800 +++ b/src/mem/ruby/profiler/Profiler.hh Mon Jan 24 22:28:54 2011 -0600 @@ -62,14 +62,12 @@ #include "mem/ruby/common/Global.hh" #include "mem/ruby/common/Histogram.hh" #include "mem/ruby/common/Set.hh" -#include "mem/ruby/libruby.hh" #include "mem/ruby/system/MachineID.hh" #include "mem/ruby/system/MemoryControl.hh" #include "mem/ruby/system/NodeID.hh" #include "params/RubyProfiler.hh" #include "sim/sim_object.hh" -class CacheMsg; class AddressProfiler; class Profiler : public SimObject, public Consumer @@ -94,7 +92,7 @@ AddressProfiler* getAddressProfiler() { return m_address_profiler_ptr; } AddressProfiler* getInstructionProfiler() { return m_inst_profiler_ptr; } - void addAddressTraceSample(const CacheMsg& msg, NodeID id); + void addAddressTraceSample(const RubyRequest& msg, NodeID id); void profileRequest(const std::string& requestStr); void profileSharing(const Address& addr, AccessType type, @@ -135,7 +133,7 @@ void bankBusy(); void missLatency(Time t, - RubyRequestType type, + CacheRequestType type, const GenericMachineType respondingMach); void missLatencyWcc(Time issuedTime, diff -r 31a04e5ac4be -r 68374d55ea98 src/mem/ruby/profiler/Profiler.cc --- a/src/mem/ruby/profiler/Profiler.cc Sat Jan 22 21:48:06 2011 -0800 +++ b/src/mem/ruby/profiler/Profiler.cc Mon Jan 24 22:28:54 2011 -0600 @@ -51,12 +51,12 @@ #include "base/stl_helpers.hh" #include "base/str.hh" -#include "mem/protocol/CacheMsg.hh" #include "mem/protocol/MachineType.hh" #include "mem/protocol/Protocol.hh" #include "mem/ruby/network/Network.hh" #include "mem/ruby/profiler/AddressProfiler.hh" #include "mem/ruby/profiler/Profiler.hh" +#include "mem/ruby/slicc_interface/RubyRequest.hh" #include "mem/ruby/system/System.hh" #include "mem/ruby/system/System.hh" @@ -273,7 +273,7 @@ out << "miss_latency: " << m_allMissLatencyHistogram << endl; for (int i = 0; i < m_missLatencyHistograms.size(); i++) { if (m_missLatencyHistograms[i].size() > 0) { - out << "miss_latency_" << RubyRequestType(i) << ": " + out << "miss_latency_" << CacheRequestType(i) << ": " << m_missLatencyHistograms[i] << endl; } } @@ -306,7 +306,7 @@ for (int i = 0; i < m_missMachLatencyHistograms.size(); i++) { for (int j = 0; j < m_missMachLatencyHistograms[i].size(); j++) { if (m_missMachLatencyHistograms[i][j].size() > 0) { - out << "miss_latency_" << RubyRequestType(i) + out << "miss_latency_" << CacheRequestType(i) << "_" << GenericMachineType(j) << ": " << m_missMachLatencyHistograms[i][j] << endl; } @@ -473,7 +473,7 @@ m_delayedCyclesVCHistograms[i].clear(); } - m_missLatencyHistograms.resize(RubyRequestType_NUM); + m_missLatencyHistograms.resize(CacheRequestType_NUM); for (int i = 0; i < m_missLatencyHistograms.size(); i++) { m_missLatencyHistograms[i].clear(200); } @@ -481,7 +481,7 @@ for (int i = 0; i < m_machLatencyHistograms.size(); i++) { m_machLatencyHistograms[i].clear(200); } - m_missMachLatencyHistograms.resize(RubyRequestType_NUM); + m_missMachLatencyHistograms.resize(CacheRequestType_NUM); for (int i = 0; i < m_missLatencyHistograms.size(); i++) { m_missMachLatencyHistograms[i].resize(GenericMachineType_NUM+1); for (int j = 0; j < m_missMachLatencyHistograms[i].size(); j++) { @@ -535,7 +535,7 @@ } void -Profiler::addAddressTraceSample(const CacheMsg& msg, NodeID id) +Profiler::addAddressTraceSample(const RubyRequest& msg, NodeID id) { if (msg.getType() != CacheRequestType_IFETCH) { // Note: The following line should be commented out if you @@ -619,7 +619,7 @@ // non-zero cycle demand request void Profiler::missLatency(Time cycles, - RubyRequestType type, + CacheRequestType type, const GenericMachineType respondingMach) { m_allMissLatencyHistogram.add(cycles); diff -r 31a04e5ac4be -r 68374d55ea98 src/mem/ruby/recorder/CacheRecorder.hh --- a/src/mem/ruby/recorder/CacheRecorder.hh Sat Jan 22 21:48:06 2011 -0800 +++ b/src/mem/ruby/recorder/CacheRecorder.hh Mon Jan 24 22:28:54 2011 -0600 @@ -40,7 +40,6 @@ #include "mem/protocol/CacheRequestType.hh" #include "mem/ruby/common/Global.hh" -#include "mem/ruby/libruby_internal.hh" #include "mem/ruby/system/NodeID.hh" #include "mem/ruby/recorder/TraceRecord.hh" @@ -52,7 +51,7 @@ { public: void addRecord(Sequencer* sequencer, const Address& data_addr, - const Address& pc_addr, RubyRequestType type, Time time); + const Address& pc_addr, CacheRequestType type, Time time); int dumpRecords(std::string filename); void print(std::ostream& out) const; diff -r 31a04e5ac4be -r 68374d55ea98 src/mem/ruby/recorder/CacheRecorder.cc --- a/src/mem/ruby/recorder/CacheRecorder.cc Sat Jan 22 21:48:06 2011 -0800 +++ b/src/mem/ruby/recorder/CacheRecorder.cc Mon Jan 24 22:28:54 2011 -0600 @@ -37,7 +37,7 @@ void CacheRecorder::addRecord(Sequencer* sequencer, const Address& data_addr, - const Address& pc_addr, RubyRequestType type, Time time) + const Address& pc_addr, CacheRequestType type, Time time) { TraceRecord rec(sequencer, data_addr, pc_addr, type, time); m_records.push_back(rec); diff -r 31a04e5ac4be -r 68374d55ea98 src/mem/ruby/recorder/TraceRecord.hh --- a/src/mem/ruby/recorder/TraceRecord.hh Sat Jan 22 21:48:06 2011 -0800 +++ b/src/mem/ruby/recorder/TraceRecord.hh Mon Jan 24 22:28:54 2011 -0600 @@ -38,23 +38,20 @@ #include "mem/ruby/common/Address.hh" #include "mem/ruby/common/Global.hh" -#include "mem/ruby/libruby_internal.hh" #include "mem/ruby/system/NodeID.hh" #include "mem/ruby/system/Sequencer.hh" -class CacheMsg; - class TraceRecord { public: TraceRecord(Sequencer* _sequencer, const Address& data_addr, - const Address& pc_addr, RubyRequestType type, Time time); + const Address& pc_addr, CacheRequestType type, Time time); TraceRecord() { m_sequencer_ptr = NULL; m_time = 0; - m_type = RubyRequestType_NULL; + m_type = CacheRequestType_NULL; } TraceRecord(const TraceRecord& obj); @@ -73,7 +70,7 @@ Time m_time; Address m_data_address; Address m_pc_address; - RubyRequestType m_type; + CacheRequestType m_type; }; inline bool diff -r 31a04e5ac4be -r 68374d55ea98 src/mem/ruby/recorder/TraceRecord.cc --- a/src/mem/ruby/recorder/TraceRecord.cc Sat Jan 22 21:48:06 2011 -0800 +++ b/src/mem/ruby/recorder/TraceRecord.cc Mon Jan 24 22:28:54 2011 -0600 @@ -26,7 +26,6 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#include "mem/protocol/CacheMsg.hh" #include "mem/ruby/recorder/TraceRecord.hh" #include "mem/ruby/system/Sequencer.hh" #include "mem/ruby/system/System.hh" @@ -35,7 +34,7 @@ using namespace std; TraceRecord::TraceRecord(Sequencer* _sequencer, const Address& data_addr, - const Address& pc_addr, RubyRequestType type, Time time) + const Address& pc_addr, CacheRequestType type, Time time) { m_sequencer_ptr = _sequencer; m_data_address = data_addr; @@ -45,10 +44,10 @@ // Don't differentiate between store misses and atomic requests in // the trace - if (m_type == RubyRequestType_Locked_Read) { - m_type = RubyRequestType_ST; - } else if (m_type == RubyRequestType_Locked_Write) { - m_type = RubyRequestType_ST; + if (m_type == CacheRequestType_Locked_Read) { + m_type = CacheRequestType_ST; + } else if (m_type == CacheRequestType_Locked_Write) { + m_type = CacheRequestType_ST; } } @@ -74,9 +73,9 @@ { assert(m_sequencer_ptr != NULL); - RubyRequest request(m_data_address.getAddress(), NULL, + RubyRequest* request = new RubyRequest(m_data_address.getAddress(), NULL, RubySystem::getBlockSizeBytes(), m_pc_address.getAddress(), - m_type, RubyAccessMode_User, NULL); + m_type, AccessModeType_User, PrefetchBit_No, NULL); // Clear out the sequencer while (!m_sequencer_ptr->empty()) { @@ -129,7 +128,7 @@ string type; in >> type; - m_type = string_to_RubyRequestType(type); + m_type = string_to_CacheRequestType(type); // Ignore the rest of the line char c = '\0'; diff -r 31a04e5ac4be -r 68374d55ea98 src/mem/ruby/recorder/Tracer.hh --- a/src/mem/ruby/recorder/Tracer.hh Sat Jan 22 21:48:06 2011 -0800 +++ b/src/mem/ruby/recorder/Tracer.hh Mon Jan 24 22:28:54 2011 -0600 @@ -41,7 +41,6 @@ #include "mem/protocol/CacheRequestType.hh" #include "mem/ruby/common/Global.hh" -#include "mem/ruby/libruby_internal.hh" #include "mem/ruby/system/NodeID.hh" #include "params/RubyTracer.hh" #include "sim/sim_object.hh" @@ -60,7 +59,7 @@ void stopTrace(); bool traceEnabled() { return m_enabled; } void traceRequest(Sequencer* sequencer, const Address& data_addr, - const Address& pc_addr, RubyRequestType type, Time time); + const Address& pc_addr, CacheRequestType type, Time time); void print(std::ostream& out) const; diff -r 31a04e5ac4be -r 68374d55ea98 src/mem/ruby/recorder/Tracer.cc --- a/src/mem/ruby/recorder/Tracer.cc Sat Jan 22 21:48:06 2011 -0800 +++ b/src/mem/ruby/recorder/Tracer.cc Mon Jan 24 22:28:54 2011 -0600 @@ -73,7 +73,7 @@ void Tracer::traceRequest(Sequencer* sequencer, const Address& data_addr, - const Address& pc_addr, RubyRequestType type, Time time) + const Address& pc_addr, CacheRequestType type, Time time) { assert(m_enabled); TraceRecord tr(sequencer, data_addr, pc_addr, type, time); diff -r 31a04e5ac4be -r 68374d55ea98 src/mem/ruby/slicc_interface/RubyRequest.hh --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/mem/ruby/slicc_interface/RubyRequest.hh Mon Jan 24 22:28:54 2011 -0600 @@ -0,0 +1,138 @@ +/* + * Copyright (c) 2009 Mark D. Hill and David A. Wood + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __MEM_RUBY_SLICC_INTERFACE_RUBY_REQUEST_HH__ +#define __MEM_RUBY_SLICC_INTERFACE_RUBY_REQUEST_HH__ + +#include + +#include "mem/packet.hh" +#include "mem/protocol/AccessModeType.hh" +#include "mem/protocol/CacheRequestType.hh" +#include "mem/protocol/Message.hh" +#include "mem/protocol/PrefetchBit.hh" +#include "mem/ruby/common/Address.hh" + +class RubyRequest : public Message +{ + public: + Address m_LineAddress; + Address m_PhysicalAddress; + CacheRequestType m_Type; + uint8_t* data; + Address m_ProgramCounter; + AccessModeType m_AccessMode; + int m_Size; + PrefetchBit m_Prefetch; + PacketPtr pkt; + unsigned proc_id; + + RubyRequest() {} + RubyRequest(uint64_t _paddr, uint8_t* _data, int _len, uint64_t _pc, + CacheRequestType _type, AccessModeType _access_mode, + PrefetchBit _pb, PacketPtr _pkt, unsigned _proc_id = 100) + : m_PhysicalAddress(_paddr), + m_Type(_type), + data(_data), + m_ProgramCounter(_pc), + m_AccessMode(_access_mode), + m_Size(_len), + m_Prefetch(_pb), + pkt(_pkt), + proc_id(_proc_id) + { + m_LineAddress = m_PhysicalAddress; + m_LineAddress.makeLineAddress(); + } + + static RubyRequest* + create() + { + return new RubyRequest(); + } + + RubyRequest* + clone() const + { + return new RubyRequest(*this); + } + + const Address& + getLineAddress() const + { + return m_LineAddress; + } + + const Address& + getPhysicalAddress() const + { + return m_PhysicalAddress; + } + + const CacheRequestType& + getType() const + { + return m_Type; + } + + const Address& + getProgramCounter() const + { + return m_ProgramCounter; + } + + const AccessModeType& + getAccessMode() const + { + return m_AccessMode; + } + + const int& + getSize() const + { + return m_Size; + } + + const PrefetchBit& + getPrefetch() const + { + return m_Prefetch; + } + + void print(std::ostream& out) const; +}; + +inline std::ostream& +operator<<(std::ostream& out, const RubyRequest& obj) +{ + obj.print(out); + out << std::flush; + return out; +} + +#endif diff -r 31a04e5ac4be -r 68374d55ea98 src/mem/ruby/slicc_interface/RubyRequest.cc --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/mem/ruby/slicc_interface/RubyRequest.cc Mon Jan 24 22:28:54 2011 -0600 @@ -0,0 +1,20 @@ +#include + +#include "mem/ruby/slicc_interface/RubyRequest.hh" + +using namespace std; + +void +RubyRequest::print(ostream& out) const +{ + out << "[RubyRequest: "; + out << "LineAddress = " << m_LineAddress << " "; + out << "PhysicalAddress = " << m_PhysicalAddress << " "; + out << "Type = " << m_Type << " "; + out << "ProgramCounter = " << m_ProgramCounter << " "; + out << "AccessMode = " << m_AccessMode << " "; + out << "Size = " << m_Size << " "; + out << "Prefetch = " << m_Prefetch << " "; + out << "Time = " << getTime() << " "; + out << "]"; +} diff -r 31a04e5ac4be -r 68374d55ea98 src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.hh --- a/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.hh Sat Jan 22 21:48:06 2011 -0800 +++ b/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.hh Mon Jan 24 22:28:54 2011 -0600 @@ -56,8 +56,8 @@ const std::string& L2CacheStateStr, const std::string& directoryStateStr, const std::string& requestTypeStr); -void profile_miss(const CacheMsg& msg, NodeID id); -void profile_L1Cache_miss(const CacheMsg& msg, NodeID id); +void profile_miss(const RubyRequest& msg, NodeID id); +void profile_L1Cache_miss(const RubyRequest& msg, NodeID id); void profile_token_retry(const Address& addr, AccessType type, int count); void profile_filter_action(int action); void profile_persistent_prediction(const Address& addr, AccessType type); diff -r 31a04e5ac4be -r 68374d55ea98 src/mem/ruby/slicc_interface/RubySlicc_Util.hh --- a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh Sat Jan 22 21:48:06 2011 -0800 +++ b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh Mon Jan 24 22:28:54 2011 -0600 @@ -36,7 +36,6 @@ #include #include "mem/protocol/AccessType.hh" -#include "mem/protocol/CacheMsg.hh" #include "mem/protocol/CacheRequestType.hh" #include "mem/protocol/Directory_State.hh" #include "mem/protocol/GenericRequestType.hh" diff -r 31a04e5ac4be -r 68374d55ea98 src/mem/ruby/slicc_interface/SConscript --- a/src/mem/ruby/slicc_interface/SConscript Sat Jan 22 21:48:06 2011 -0800 +++ b/src/mem/ruby/slicc_interface/SConscript Mon Jan 24 22:28:54 2011 -0600 @@ -37,5 +37,6 @@ Source('AbstractEntry.cc') Source('AbstractCacheEntry.cc') +Source('RubyRequest.cc') Source('RubySlicc_Profiler_interface.cc') Source('RubySlicc_ComponentMapping.cc') diff -r 31a04e5ac4be -r 68374d55ea98 src/mem/ruby/storebuffer/stb_interface.cc --- a/src/mem/ruby/storebuffer/stb_interface.cc Sat Jan 22 21:48:06 2011 -0800 +++ b/src/mem/ruby/storebuffer/stb_interface.cc Mon Jan 24 22:28:54 2011 -0600 @@ -40,7 +40,7 @@ storebuffer_status_t handleStore(StoreBuffer *storebuffer, const RubyRequest &request) { - assert(request.type == RubyRequestType_ST); + assert(request.m_Type == CacheRequestType_ST); if (storebuffer->storeBufferFull()){ return WB_FULL; } else if (storebuffer->storeBufferFlushing()) { @@ -54,7 +54,7 @@ uint64_t handleLoad(StoreBuffer *storebuffer, const RubyRequest &request) { - assert(request.type == RubyRequestType_LD); + assert(request.m_Type == CacheRequestType_LD); return storebuffer->handleLoad(request); } diff -r 31a04e5ac4be -r 68374d55ea98 src/mem/ruby/storebuffer/storebuffer.hh --- a/src/mem/ruby/storebuffer/storebuffer.hh Sat Jan 22 21:48:06 2011 -0800 +++ b/src/mem/ruby/storebuffer/storebuffer.hh Mon Jan 24 22:28:54 2011 -0600 @@ -33,7 +33,7 @@ #include #include "mem/ruby/common/TypeDefines.hh" -#include "mem/ruby/libruby.hh" +#include "mem/ruby/slicc_interface/RubyRequest.hh" /** * Status for write buffer accesses. The Write buffer can hit in @@ -132,9 +132,6 @@ /// to be added should issue itself bool m_stalled_issue; - /// RubyPort to make requests to - RubyPortHandle m_port; - /// HitCallback to CPU void (*m_hit_callback)(int64_t); diff -r 31a04e5ac4be -r 68374d55ea98 src/mem/ruby/storebuffer/storebuffer.cc --- a/src/mem/ruby/storebuffer/storebuffer.cc Sat Jan 22 21:48:06 2011 -0800 +++ b/src/mem/ruby/storebuffer/storebuffer.cc Mon Jan 24 22:28:54 2011 -0600 @@ -59,7 +59,6 @@ char name [] = "Sequencer_"; char port_name [13]; sprintf(port_name, "%s%d", name, id); - m_port = libruby_get_port(port_name, hit); m_hit_callback = NULL; assert(storebuffer_size >= 0); m_storebuffer_size = storebuffer_size; @@ -92,8 +91,7 @@ StoreBuffer::addToStoreBuffer(RubyRequest request) { if (!m_use_storebuffer) { - // make request to libruby - uint64_t id = libruby_issue_request(m_port, request); + uint64_t id = 0; if (request_map.find(id) != request_map.end()) { panic("Request ID: %d is already in the map\n", id); } else { @@ -130,7 +128,7 @@ { if (!m_use_storebuffer) { // make a request to ruby - return libruby_issue_request(m_port, request); + return 0; } load_match match = checkForLoadHit(request); @@ -140,8 +138,7 @@ iseq++; return -2; } else if (match == NO_MATCH) { - // make request to libruby and return the id - uint64_t id = libruby_issue_request(m_port, request); + uint64_t id = 0; if (request_map.find(id) != request_map.end()) { panic("Request ID: %d is already in the map\n", id); } else { @@ -165,8 +162,8 @@ panic("checkForLoadHit called while write buffer is not in use\n"); } - physical_address_t physical_address = request.paddr; - int len = request.len; + physical_address_t physical_address = request.m_PhysicalAddress.getAddress(); + int len = request.m_Size; uint8_t * data = new uint8_t[64]; memset(data, 0, 64); @@ -180,11 +177,11 @@ deque::iterator it = buffer.begin(); for (; it != buffer.end(); it++) { RubyRequest &req = it->m_request; - if ((req.paddr & m_block_mask) != lineaddr) + if ((req.m_PhysicalAddress.getAddress() & m_block_mask) != lineaddr) continue; found = true; - for (int i = req.paddr % 64; i < req.len; i++) + for (int i = req.m_PhysicalAddress.getAddress() % 64; i < req.m_Size; i++) data[i] = 0; } @@ -221,8 +218,8 @@ uint8_t * written = new uint8_t[64]; memset(written, 0, 64); - physical_address_t physical_address = request.paddr; - int len = request.len; + physical_address_t physical_address = request.m_PhysicalAddress.getAddress(); + int len = request.m_Size; assert(checkForLoadHit(request) != NO_MATCH); physical_address_t lineaddr = physical_address & m_block_mask; @@ -230,13 +227,13 @@ deque::iterator satisfying_store; deque::iterator it = buffer.begin(); for (; it != buffer.end(); it++) { - if ((it->m_request.paddr & m_block_mask) == lineaddr) { + if ((it->m_request.m_PhysicalAddress.getAddress() & m_block_mask) == lineaddr) { if (!found) { found = true; } uint8_t * dataPtr = it->m_request.data; - int offset = it->m_request.paddr%64; - for (int i = offset; i < it->m_request.len; i++) { + int offset = it->m_request.m_PhysicalAddress.getAddress() % 64; + for (int i = offset; i < it->m_request.m_Size; i++) { if (!written[i]) { // don't overwrite data with earlier data data[i] = dataPtr[i-offset]; written[i] = 1; @@ -271,7 +268,7 @@ StoreBuffer::issueNextStore() { SBEntry request = buffer.back(); - uint64_t id = libruby_issue_request(m_port, request.m_request); + uint64_t id = 0; if (request_map.find(id) != request_map.end()) { assert(0); } else { @@ -290,10 +287,10 @@ assert(outstanding_requests.find(id) != outstanding_requests.end()); physical_address_t physical_address = - outstanding_requests.find(id)->second.paddr; - RubyRequestType type = outstanding_requests.find(id)->second.type; + outstanding_requests.find(id)->second.m_PhysicalAddress.getAddress(); + CacheRequestType type = outstanding_requests.find(id)->second.m_Type; - if (type == RubyRequestType_ST) { + if (type == CacheRequestType_ST) { physical_address_t lineaddr = physical_address & m_block_mask; // Note fastpath hits are handled like regular requests - they @@ -305,8 +302,8 @@ } SBEntry from_buffer = buffer.back(); - if ((from_buffer.m_request.paddr & m_block_mask) == lineaddr && - from_buffer.m_request.type == type) { + if ((from_buffer.m_request.m_PhysicalAddress.getAddress() & m_block_mask) == lineaddr && + from_buffer.m_request.m_Type == type) { buffer.pop_back(); m_buffer_size--; assert(m_buffer_size >= 0); @@ -327,7 +324,7 @@ m_id, lineaddr); } - } else if (type == RubyRequestType_LD) { + } else if (type == CacheRequestType_LD) { m_hit_callback(id); } diff -r 31a04e5ac4be -r 68374d55ea98 src/mem/ruby/system/CacheMemory.hh --- a/src/mem/ruby/system/CacheMemory.hh Sat Jan 22 21:48:06 2011 -0800 +++ b/src/mem/ruby/system/CacheMemory.hh Mon Jan 24 22:28:54 2011 -0600 @@ -35,7 +35,6 @@ #include "base/hashmap.hh" #include "mem/protocol/AccessPermission.hh" -#include "mem/protocol/CacheMsg.hh" #include "mem/protocol/CacheRequestType.hh" #include "mem/protocol/GenericRequestType.hh" #include "mem/protocol/MachineType.hh" @@ -46,6 +45,7 @@ #include "mem/ruby/recorder/CacheRecorder.hh" #include "mem/ruby/slicc_interface/AbstractCacheEntry.hh" #include "mem/ruby/slicc_interface/AbstractController.hh" +#include "mem/ruby/slicc_interface/RubyRequest.hh" #include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh" #include "mem/ruby/system/LRUPolicy.hh" #include "mem/ruby/system/PseudoLRUPolicy.hh" @@ -107,7 +107,7 @@ // Set this address to most recently used void setMRU(const Address& address); - void profileMiss(const CacheMsg & msg); + void profileMiss(const RubyRequest& msg); void profileGenericRequest(GenericRequestType requestType, AccessModeType accessType, diff -r 31a04e5ac4be -r 68374d55ea98 src/mem/ruby/system/CacheMemory.cc --- a/src/mem/ruby/system/CacheMemory.cc Sat Jan 22 21:48:06 2011 -0800 +++ b/src/mem/ruby/system/CacheMemory.cc Mon Jan 24 22:28:54 2011 -0600 @@ -344,7 +344,7 @@ } void -CacheMemory::profileMiss(const CacheMsg& msg) +CacheMemory::profileMiss(const RubyRequest& msg) { m_profiler_ptr->addCacheStatSample(msg.getType(), msg.getAccessMode(), diff -r 31a04e5ac4be -r 68374d55ea98 src/mem/ruby/system/DMASequencer.hh --- a/src/mem/ruby/system/DMASequencer.hh Sat Jan 22 21:48:06 2011 -0800 +++ b/src/mem/ruby/system/DMASequencer.hh Mon Jan 24 22:28:54 2011 -0600 @@ -53,7 +53,7 @@ DMASequencer(const Params *); void init(); /* external interface */ - RequestStatus makeRequest(const RubyRequest & request); + RequestStatus makeRequest(MsgPtr request); bool busy() { return m_is_busy;} /* SLICC callback */ diff -r 31a04e5ac4be -r 68374d55ea98 src/mem/ruby/system/DMASequencer.cc --- a/src/mem/ruby/system/DMASequencer.cc Sat Jan 22 21:48:06 2011 -0800 +++ b/src/mem/ruby/system/DMASequencer.cc Mon Jan 24 22:28:54 2011 -0600 @@ -47,31 +47,35 @@ } RequestStatus -DMASequencer::makeRequest(const RubyRequest &request) +DMASequencer::makeRequest(MsgPtr msg_ptr) { if (m_is_busy) { return RequestStatus_BufferFull; } - uint64_t paddr = request.paddr; - uint8_t* data = request.data; - int len = request.len; + RubyRequest* request = safe_cast(msg_ptr.get()); + uint64_t paddr = request->m_PhysicalAddress.getAddress(); + uint8_t* data = request->data; + int len = request->m_Size; bool write = false; - switch(request.type) { - case RubyRequestType_LD: + switch(request->m_Type) { + case CacheRequestType_LD: write = false; break; - case RubyRequestType_ST: + case CacheRequestType_ST: write = true; break; - case RubyRequestType_NULL: - case RubyRequestType_IFETCH: - case RubyRequestType_Locked_Read: - case RubyRequestType_Locked_Write: - case RubyRequestType_RMW_Read: - case RubyRequestType_RMW_Write: - case RubyRequestType_NUM: - panic("DMASequencer::makeRequest does not support RubyRequestType"); + case CacheRequestType_NULL: + case CacheRequestType_IFETCH: + case CacheRequestType_IO: + case CacheRequestType_Locked_Read: + case CacheRequestType_Locked_Write: + case CacheRequestType_REPLACEMENT: + case CacheRequestType_RMW_Read: + case CacheRequestType_RMW_Write: + case CacheRequestType_COMMIT: + case CacheRequestType_NUM: + panic("DMASequencer::makeRequest does not support CacheRequestType"); return RequestStatus_NULL; } @@ -84,7 +88,7 @@ active_request.len = len; active_request.bytes_completed = 0; active_request.bytes_issued = 0; - active_request.pkt = request.pkt; + active_request.pkt = request->pkt; SequencerMsg *msg = new SequencerMsg; msg->getPhysicalAddress() = Address(paddr); diff -r 31a04e5ac4be -r 68374d55ea98 src/mem/ruby/system/PerfectCacheMemory.hh --- a/src/mem/ruby/system/PerfectCacheMemory.hh Sat Jan 22 21:48:06 2011 -0800 +++ b/src/mem/ruby/system/PerfectCacheMemory.hh Mon Jan 24 22:28:54 2011 -0600 @@ -59,7 +59,7 @@ // perform a cache access and see if we hit or not. Return true // on a hit. - bool tryCacheAccess(const CacheMsg& msg, bool& block_stc, ENTRY*& entry); + bool tryCacheAccess(const RubyRequest& msg, bool& block_stc, ENTRY*& entry); // tests to see if an address is present in the cache bool isTagPresent(const Address& address) const; @@ -120,7 +120,7 @@ template inline bool -PerfectCacheMemory::tryCacheAccess(const CacheMsg& msg, +PerfectCacheMemory::tryCacheAccess(const RubyRequest& msg, bool& block_stc, ENTRY*& entry) { panic("not implemented"); diff -r 31a04e5ac4be -r 68374d55ea98 src/mem/ruby/system/RubyPort.hh --- a/src/mem/ruby/system/RubyPort.hh Sat Jan 22 21:48:06 2011 -0800 +++ b/src/mem/ruby/system/RubyPort.hh Mon Jan 24 22:28:54 2011 -0600 @@ -35,7 +35,7 @@ #include "mem/mem_object.hh" #include "mem/physical.hh" #include "mem/protocol/RequestStatus.hh" -#include "mem/ruby/libruby.hh" +#include "mem/ruby/slicc_interface/RubyRequest.hh" #include "mem/tport.hh" #include "params/RubyPort.hh" @@ -99,7 +99,7 @@ Port *getPort(const std::string &if_name, int idx); - virtual RequestStatus makeRequest(const RubyRequest & request) = 0; + virtual RequestStatus makeRequest(MsgPtr request) = 0; // // Called by the controller to give the sequencer a pointer. diff -r 31a04e5ac4be -r 68374d55ea98 src/mem/ruby/system/RubyPort.cc --- a/src/mem/ruby/system/RubyPort.cc Sat Jan 22 21:48:06 2011 -0800 +++ b/src/mem/ruby/system/RubyPort.cc Mon Jan 24 22:28:54 2011 -0600 @@ -184,7 +184,7 @@ // For DMA and CPU requests, translate them to ruby requests before // sending them to our assigned ruby port. - RubyRequestType type = RubyRequestType_NULL; + CacheRequestType type = CacheRequestType_NULL; // If valid, copy the pc to the ruby request Addr pc = 0; @@ -195,36 +195,36 @@ if (pkt->isLLSC()) { if (pkt->isWrite()) { DPRINTF(MemoryAccess, "Issuing SC\n"); - type = RubyRequestType_Locked_Write; + type = CacheRequestType_Locked_Write; } else { DPRINTF(MemoryAccess, "Issuing LL\n"); assert(pkt->isRead()); - type = RubyRequestType_Locked_Read; + type = CacheRequestType_Locked_Read; } } else { if (pkt->isRead()) { if (pkt->req->isInstFetch()) { - type = RubyRequestType_IFETCH; + type = CacheRequestType_IFETCH; } else { - type = RubyRequestType_LD; + type = CacheRequestType_LD; } } else if (pkt->isWrite()) { - type = RubyRequestType_ST; + type = CacheRequestType_ST; } else if (pkt->isReadWrite()) { // Fix me. This conditional will never be executed // because isReadWrite() is just an OR of isRead() and // isWrite(). Furthermore, just because the packet is a // read/write request does not necessary mean it is a // read-modify-write atomic operation. - type = RubyRequestType_RMW_Write; + type = CacheRequestType_RMW_Write; } else { panic("Unsupported ruby packet type\n"); } } - RubyRequest ruby_request(pkt->getAddr(), pkt->getPtr(), + MsgPtr ruby_request = new RubyRequest(pkt->getAddr(), pkt->getPtr(), pkt->getSize(), pc, type, - RubyAccessMode_Supervisor, pkt); + AccessModeType_Supervisor, PrefetchBit_No, pkt); // Submit the ruby request RequestStatus requestStatus = ruby_port->makeRequest(ruby_request); diff -r 31a04e5ac4be -r 68374d55ea98 src/mem/ruby/system/Sequencer.hh --- a/src/mem/ruby/system/Sequencer.hh Sat Jan 22 21:48:06 2011 -0800 +++ b/src/mem/ruby/system/Sequencer.hh Mon Jan 24 22:28:54 2011 -0600 @@ -42,7 +42,6 @@ #include "mem/ruby/system/RubyPort.hh" class DataBlock; -class CacheMsg; class MachineID; class CacheMemory; @@ -50,10 +49,10 @@ struct SequencerRequest { - RubyRequest ruby_request; + MsgPtr ruby_request; Time issue_time; - SequencerRequest(const RubyRequest & _ruby_request, Time _issue_time) + SequencerRequest(RubyRequest* _ruby_request, Time _issue_time) : ruby_request(_ruby_request), issue_time(_issue_time) {} }; @@ -100,8 +99,8 @@ Time forwardRequestTime, Time firstResponseTime); - RequestStatus makeRequest(const RubyRequest & request); - RequestStatus getRequestStatus(const RubyRequest& request); + RequestStatus makeRequest(MsgPtr request); + RequestStatus getRequestStatus(const RubyRequest* request); bool empty() const; void print(std::ostream& out) const; @@ -115,7 +114,7 @@ bool tryCacheAccess(const Address& addr, CacheRequestType type, const Address& pc, AccessModeType access_mode, int size, DataBlock*& data_ptr); - void issueRequest(const RubyRequest& request); + void issueRequest(MsgPtr request); void hitCallback(SequencerRequest* request, GenericMachineType mach, diff -r 31a04e5ac4be -r 68374d55ea98 src/mem/ruby/system/Sequencer.cc --- a/src/mem/ruby/system/Sequencer.cc Sat Jan 22 21:48:06 2011 -0800 +++ b/src/mem/ruby/system/Sequencer.cc Mon Jan 24 22:28:54 2011 -0600 @@ -29,13 +29,11 @@ #include "base/str.hh" #include "base/misc.hh" #include "cpu/testers/rubytest/RubyTester.hh" -#include "mem/protocol/CacheMsg.hh" #include "mem/protocol/Protocol.hh" #include "mem/protocol/Protocol.hh" #include "mem/ruby/buffers/MessageBuffer.hh" #include "mem/ruby/common/Global.hh" #include "mem/ruby/common/SubBlock.hh" -#include "mem/ruby/libruby.hh" #include "mem/ruby/profiler/Profiler.hh" #include "mem/ruby/recorder/Tracer.hh" #include "mem/ruby/slicc_interface/AbstractController.hh" @@ -97,13 +95,14 @@ RequestTable::iterator read_end = m_readRequestTable.end(); for (; read != read_end; ++read) { SequencerRequest* request = read->second; + RubyRequest* ruby_request = safe_cast(request->ruby_request.get()); if (current_time - request->issue_time < m_deadlock_threshold) continue; panic("Possible Deadlock detected. Aborting!\n" "version: %d request.paddr: %d m_readRequestTable: %d " "current time: %u issue_time: %d difference: %d\n", m_version, - request->ruby_request.paddr, m_readRequestTable.size(), + ruby_request->m_PhysicalAddress, m_readRequestTable.size(), current_time, request->issue_time, current_time - request->issue_time); } @@ -112,13 +111,14 @@ RequestTable::iterator write_end = m_writeRequestTable.end(); for (; write != write_end; ++write) { SequencerRequest* request = write->second; + RubyRequest* ruby_request = safe_cast(request->ruby_request.get()); if (current_time - request->issue_time < m_deadlock_threshold) continue; panic("Possible Deadlock detected. Aborting!\n" "version: %d request.paddr: %d m_writeRequestTable: %d " "current time: %u issue_time: %d difference: %d\n", m_version, - request->ruby_request.paddr, m_writeRequestTable.size(), + ruby_request->m_PhysicalAddress, m_writeRequestTable.size(), current_time, request->issue_time, current_time - request->issue_time); } @@ -226,13 +226,13 @@ schedule(deadlockCheckEvent, m_deadlock_threshold + curTick()); } - Address line_addr(request->ruby_request.paddr); - line_addr.makeLineAddress(); - if ((request->ruby_request.type == RubyRequestType_ST) || - (request->ruby_request.type == RubyRequestType_RMW_Read) || - (request->ruby_request.type == RubyRequestType_RMW_Write) || - (request->ruby_request.type == RubyRequestType_Locked_Read) || - (request->ruby_request.type == RubyRequestType_Locked_Write)) { + RubyRequest* ruby_request = safe_cast(request->ruby_request.get()); + Address line_addr(ruby_request->m_LineAddress); + if ((ruby_request->m_Type == CacheRequestType_ST) || + (ruby_request->m_Type == CacheRequestType_RMW_Read) || + (ruby_request->m_Type == CacheRequestType_RMW_Write) || + (ruby_request->m_Type == CacheRequestType_Locked_Read) || + (ruby_request->m_Type == CacheRequestType_Locked_Write)) { pair r = m_writeRequestTable.insert(RequestTable::value_type(line_addr, 0)); bool success = r.second; @@ -284,14 +284,13 @@ assert(m_outstanding_count == m_writeRequestTable.size() + m_readRequestTable.size()); - const RubyRequest & ruby_request = srequest->ruby_request; - Address line_addr(ruby_request.paddr); - line_addr.makeLineAddress(); - if ((ruby_request.type == RubyRequestType_ST) || - (ruby_request.type == RubyRequestType_RMW_Read) || - (ruby_request.type == RubyRequestType_RMW_Write) || - (ruby_request.type == RubyRequestType_Locked_Read) || - (ruby_request.type == RubyRequestType_Locked_Write)) { + const RubyRequest* ruby_request = safe_cast(srequest->ruby_request.get()); + Address line_addr(ruby_request->m_LineAddress); + if ((ruby_request->m_Type == CacheRequestType_ST) || + (ruby_request->m_Type == CacheRequestType_RMW_Read) || + (ruby_request->m_Type == CacheRequestType_RMW_Write) || + (ruby_request->m_Type == CacheRequestType_Locked_Read) || + (ruby_request->m_Type == CacheRequestType_Locked_Write)) { m_writeRequestTable.erase(line_addr); } else { m_readRequestTable.erase(line_addr); @@ -301,7 +300,7 @@ } bool -Sequencer::handleLlsc(const Address& address, SequencerRequest* request) +Sequencer::handleLlsc(const Address& address, SequencerRequest* srequest) { // // The success flag indicates whether the LLSC operation was successful. @@ -309,26 +308,27 @@ // longer locked. // bool success = true; - if (request->ruby_request.type == RubyRequestType_Locked_Write) { + RubyRequest* ruby_request = safe_cast(srequest->ruby_request.get()); + if (ruby_request->m_Type == CacheRequestType_Locked_Write) { if (!m_dataCache_ptr->isLocked(address, m_version)) { // // For failed SC requests, indicate the failure to the cpu by // setting the extra data to zero. // - request->ruby_request.pkt->req->setExtraData(0); + ruby_request->pkt->req->setExtraData(0); success = false; } else { // // For successful SC requests, indicate the success to the cpu by // setting the extra data to one. // - request->ruby_request.pkt->req->setExtraData(1); + ruby_request->pkt->req->setExtraData(1); } // // Independent of success, all SC operations must clear the lock // m_dataCache_ptr->clearLocked(address); - } else if (request->ruby_request.type == RubyRequestType_Locked_Read) { + } else if (ruby_request->m_Type == CacheRequestType_Locked_Read) { // // Note: To fully follow Alpha LLSC semantics, should the LL clear any // previously locked cache lines? @@ -371,15 +371,15 @@ RequestTable::iterator i = m_writeRequestTable.find(address); assert(i != m_writeRequestTable.end()); SequencerRequest* request = i->second; - + RubyRequest* ruby_request = safe_cast(request->ruby_request.get()); m_writeRequestTable.erase(i); markRemoved(); - assert((request->ruby_request.type == RubyRequestType_ST) || - (request->ruby_request.type == RubyRequestType_RMW_Read) || - (request->ruby_request.type == RubyRequestType_RMW_Write) || - (request->ruby_request.type == RubyRequestType_Locked_Read) || - (request->ruby_request.type == RubyRequestType_Locked_Write)); + assert((ruby_request->m_Type == CacheRequestType_ST) || + (ruby_request->m_Type == CacheRequestType_RMW_Read) || + (ruby_request->m_Type == CacheRequestType_RMW_Write) || + (ruby_request->m_Type == CacheRequestType_Locked_Read) || + (ruby_request->m_Type == CacheRequestType_Locked_Write)); // // For Alpha, properly handle LL, SC, and write requests with respect to @@ -387,9 +387,9 @@ // bool success = handleLlsc(address, request); - if (request->ruby_request.type == RubyRequestType_RMW_Read) { + if (ruby_request->m_Type == CacheRequestType_RMW_Read) { m_controller->blockOnQueue(address, m_mandatory_q_ptr); - } else if (request->ruby_request.type == RubyRequestType_RMW_Write) { + } else if (ruby_request->m_Type == CacheRequestType_RMW_Write) { m_controller->unblock(address); } @@ -429,9 +429,9 @@ m_readRequestTable.erase(i); markRemoved(); - assert((request->ruby_request.type == RubyRequestType_LD) || - (request->ruby_request.type == RubyRequestType_RMW_Read) || - (request->ruby_request.type == RubyRequestType_IFETCH)); + assert((request->ruby_request->m_Type == CacheRequestType_LD) || + (request->ruby_request->m_Type == CacheRequestType_RMW_Read) || + (request->ruby_request->m_Type == CacheRequestType_IFETCH)); hitCallback(request, mach, data, true, initialRequestTime, forwardRequestTime, firstResponseTime); @@ -446,15 +446,15 @@ Time forwardRequestTime, Time firstResponseTime) { - const RubyRequest & ruby_request = srequest->ruby_request; - Address request_address(ruby_request.paddr); - Address request_line_address(ruby_request.paddr); + RubyRequest* ruby_request = safe_cast(srequest->ruby_request.get()); + Address request_address(ruby_request->m_PhysicalAddress); + Address request_line_address(ruby_request->m_PhysicalAddress); request_line_address.makeLineAddress(); - RubyRequestType type = ruby_request.type; + CacheRequestType type = ruby_request->m_Type; Time issued_time = srequest->issue_time; // Set this cache entry to the most recently used - if (type == RubyRequestType_IFETCH) { + if (type == CacheRequestType_IFETCH) { if (m_instCache_ptr->isTagPresent(request_line_address)) m_instCache_ptr->setMRU(request_line_address); } else { @@ -488,7 +488,7 @@ DPRINTFR(ProtocolTrace, "%7s %3s %10s%20s %6s>%-6s %s %d cycles\n", g_eventQueue_ptr->getTime(), m_version, "Seq", success ? "Done" : "SC_Failed", "", "", - Address(ruby_request.paddr), miss_latency); + Address(ruby_request->m_PhysicalAddress), miss_latency); } #if 0 if (request.getPrefetch() == PrefetchBit_Yes) { @@ -497,23 +497,23 @@ #endif // update the data - if (ruby_request.data != NULL) { - if ((type == RubyRequestType_LD) || - (type == RubyRequestType_IFETCH) || - (type == RubyRequestType_RMW_Read) || - (type == RubyRequestType_Locked_Read)) { + if (ruby_request->data != NULL) { + if ((type == CacheRequestType_LD) || + (type == CacheRequestType_IFETCH) || + (type == CacheRequestType_RMW_Read) || + (type == CacheRequestType_Locked_Read)) { - memcpy(ruby_request.data, - data.getData(request_address.getOffset(), ruby_request.len), - ruby_request.len); + memcpy(ruby_request->data, + data.getData(request_address.getOffset(), ruby_request->m_Size), + ruby_request->m_Size); } else { - data.setData(ruby_request.data, request_address.getOffset(), - ruby_request.len); + data.setData(ruby_request->data, request_address.getOffset(), + ruby_request->m_Size); } } else { DPRINTF(MemoryAccess, "WARNING. Data not transfered from Ruby to M5 for type %s\n", - RubyRequestType_to_string(type)); + CacheRequestType_to_string(type)); } // If using the RubyTester, update the RubyTester sender state's @@ -523,36 +523,36 @@ // RubyTester. if (m_usingRubyTester) { RubyPort::SenderState *requestSenderState = - safe_cast(ruby_request.pkt->senderState); + safe_cast(ruby_request->pkt->senderState); RubyTester::SenderState* testerSenderState = safe_cast(requestSenderState->saved); testerSenderState->subBlock->mergeFrom(data); } - ruby_hit_callback(ruby_request.pkt); + ruby_hit_callback(ruby_request->pkt); delete srequest; } // Returns true if the sequencer already has a load or store outstanding RequestStatus -Sequencer::getRequestStatus(const RubyRequest& request) +Sequencer::getRequestStatus(const RubyRequest* request) { bool is_outstanding_store = - !!m_writeRequestTable.count(line_address(Address(request.paddr))); + !!m_writeRequestTable.count(line_address(request->m_PhysicalAddress)); bool is_outstanding_load = - !!m_readRequestTable.count(line_address(Address(request.paddr))); + !!m_readRequestTable.count(line_address(request->m_PhysicalAddress)); if (is_outstanding_store) { - if ((request.type == RubyRequestType_LD) || - (request.type == RubyRequestType_IFETCH) || - (request.type == RubyRequestType_RMW_Read)) { + if ((request->m_Type == CacheRequestType_LD) || + (request->m_Type == CacheRequestType_IFETCH) || + (request->m_Type == CacheRequestType_RMW_Read)) { m_store_waiting_on_load_cycles++; } else { m_store_waiting_on_store_cycles++; } return RequestStatus_Aliased; } else if (is_outstanding_load) { - if ((request.type == RubyRequestType_ST) || - (request.type == RubyRequestType_RMW_Write)) { + if ((request->m_Type == CacheRequestType_ST) || + (request->m_Type == CacheRequestType_RMW_Write)) { m_load_waiting_on_store_cycles++; } else { m_load_waiting_on_load_cycles++; @@ -574,9 +574,10 @@ } RequestStatus -Sequencer::makeRequest(const RubyRequest &request) +Sequencer::makeRequest(MsgPtr msg_ptr) { - assert(Address(request.paddr).getOffset() + request.len <= + RubyRequest* request = safe_cast(msg_ptr.get()); + assert(request->m_PhysicalAddress.getOffset() + request->m_Size <= RubySystem::getBlockSizeBytes()); RequestStatus status = getRequestStatus(request); if (status != RequestStatus_Ready) @@ -591,71 +592,23 @@ return RequestStatus_NULL; } - issueRequest(request); + issueRequest(msg_ptr); // TODO: issue hardware prefetches here return RequestStatus_Issued; } void -Sequencer::issueRequest(const RubyRequest& request) +Sequencer::issueRequest(MsgPtr msg_ptr) { - // TODO: get rid of CacheMsg, CacheRequestType, and - // AccessModeTYpe, & have SLICC use RubyRequest and subtypes - // natively - CacheRequestType ctype; - switch(request.type) { - case RubyRequestType_IFETCH: - ctype = CacheRequestType_IFETCH; - break; - case RubyRequestType_LD: - ctype = CacheRequestType_LD; - break; - case RubyRequestType_ST: - ctype = CacheRequestType_ST; - break; - case RubyRequestType_Locked_Read: - case RubyRequestType_Locked_Write: - ctype = CacheRequestType_ATOMIC; - break; - case RubyRequestType_RMW_Read: - ctype = CacheRequestType_ATOMIC; - break; - case RubyRequestType_RMW_Write: - ctype = CacheRequestType_ATOMIC; - break; - default: - assert(0); - } - - AccessModeType amtype; - switch(request.access_mode){ - case RubyAccessMode_User: - amtype = AccessModeType_UserMode; - break; - case RubyAccessMode_Supervisor: - amtype = AccessModeType_SupervisorMode; - break; - case RubyAccessMode_Device: - amtype = AccessModeType_UserMode; - break; - default: - assert(0); - } - - Address line_addr(request.paddr); - line_addr.makeLineAddress(); - CacheMsg *msg = new CacheMsg(line_addr, Address(request.paddr), ctype, - Address(request.pc), amtype, request.len, PrefetchBit_No, - request.proc_id); - + RubyRequest* request = safe_cast(msg_ptr.get()); DPRINTFR(ProtocolTrace, "%7s %3s %10s%20s %6s>%-6s %s %s\n", g_eventQueue_ptr->getTime(), m_version, "Seq", "Begin", "", "", - Address(request.paddr), RubyRequestType_to_string(request.type)); + request->m_PhysicalAddress, CacheRequestType_to_string(request->m_Type)); Time latency = 0; // initialzed to an null value - if (request.type == RubyRequestType_IFETCH) + if (request->m_Type == CacheRequestType_IFETCH) latency = m_instCache_ptr->getLatency(); else latency = m_dataCache_ptr->getLatency(); @@ -664,7 +617,7 @@ assert(latency > 0); assert(m_mandatory_q_ptr != NULL); - m_mandatory_q_ptr->enqueue(msg, latency); + m_mandatory_q_ptr->enqueue(msg_ptr, latency); } #if 0 diff -r 31a04e5ac4be -r 68374d55ea98 src/mem/ruby/system/SparseMemory.cc --- a/src/mem/ruby/system/SparseMemory.cc Sat Jan 22 21:48:06 2011 -0800 +++ b/src/mem/ruby/system/SparseMemory.cc Mon Jan 24 22:28:54 2011 -0600 @@ -27,6 +27,7 @@ */ #include "mem/ruby/system/SparseMemory.hh" +#include "mem/ruby/system/System.hh" using namespace std; diff -r 31a04e5ac4be -r 68374d55ea98 src/mem/slicc/parser.py --- a/src/mem/slicc/parser.py Sat Jan 22 21:48:06 2011 -0800 +++ b/src/mem/slicc/parser.py Mon Jan 24 22:28:54 2011 -0600 @@ -369,10 +369,14 @@ "type_methods : empty" p[0] = [] - def p_type_method(self, p): + def p_type_method__0(self, p): "type_method : type_or_void ident '(' types ')' pairs SEMI" p[0] = ast.TypeFieldMethodAST(self, p[1], p[2], p[4], p[6]) + def p_type_method__1(self, p): + "type_method : type_or_void ident SEMI" + p[0] = ast.TypeFieldMemberAST(self, p[1], p[2], None, None) + # Enum fields def p_type_enums__list(self, p): "type_enums : type_enum type_enums"