# HG changeset patch
# Parent 3d7a85d71bd1aad69c07781d50779b7d1f83dd96

diff -r 3d7a85d71bd1 src/arch/arm/insts/macromem.cc
--- a/src/arch/arm/insts/macromem.cc	Fri Jan 22 10:42:13 2016 -0500
+++ b/src/arch/arm/insts/macromem.cc	Tue Jan 26 12:44:20 2016 +0100
@@ -249,11 +249,11 @@
     bool post = (mode == AddrMd_PostIndex);
     bool writeback = (mode != AddrMd_Offset);
 
-    if (load) {
-        // Use integer rounding to round up loads of size 4
+    //@TODO FP store-pair are still cracked and they should not.
+    if(!load && fp) {
+        numMicroops = (post ? 0 : 1) + (size / 4) + (writeback ? 1 : 0);
+    } else {
         numMicroops = (post ? 0 : 1) + ((size + 4) / 8) + (writeback ? 1 : 0);
-    } else {
-        numMicroops = (post ? 0 : 1) + (size / 4) + (writeback ? 1 : 0);
     }
     microOps = new StaticInstPtr[numMicroops];
 
@@ -308,10 +308,8 @@
                 *uop++ = new MicroLdPairUop(machInst, rt, rt2,
                         post ? rn : INTREG_UREG0, 0, noAlloc, exclusive, acrel);
             } else {
-                *uop++ = new MicroStrXImmUop(machInst, rt, post ? rn : INTREG_UREG0,
-                        0, noAlloc, exclusive, acrel);
-                *uop++ = new MicroStrXImmUop(machInst, rt2, post ? rn : INTREG_UREG0,
-                        size, noAlloc, exclusive, acrel);
+                *uop++ = new MicroStPairUop(machInst, rt, rt2,
+                        post ? rn : INTREG_UREG0, 0, noAlloc, exclusive, acrel);
             }
         } else if (size == 4) {
             if (load) {
diff -r 3d7a85d71bd1 src/arch/arm/isa/insts/ldr64.isa
--- a/src/arch/arm/isa/insts/ldr64.isa	Fri Jan 22 10:42:13 2016 -0500
+++ b/src/arch/arm/isa/insts/ldr64.isa	Tue Jan 26 12:44:20 2016 +0100
@@ -427,6 +427,7 @@
 
     LoadImmDU64("ldp_uop", "MicroLdPairUop", 8).emit()
     LoadImmDU64("ldp_fp8_uop", "MicroLdPairFp8Uop", 8, flavor="fp").emit()
+
     LoadImmU64("ldfp16_uop", "MicroLdFp16Uop", 16, flavor="fp").emit()
     LoadReg64("ldfp16reg_uop", "MicroLdFp16RegUop", 16, flavor="fp").emit()
 
diff -r 3d7a85d71bd1 src/arch/arm/isa/insts/str64.isa
--- a/src/arch/arm/isa/insts/str64.isa	Fri Jan 22 10:42:13 2016 -0500
+++ b/src/arch/arm/isa/insts/str64.isa	Tue Jan 26 12:44:20 2016 +0100
@@ -349,6 +349,8 @@
         decConstBase = 'LoadStoreRegU64'
         micro = True
 
+    StoreImmDU64("stp_uop", "MicroStPairUop", 8).emit()
+
     StoreImmDEx64("stlxp", "STLXPW64", 4, flavor="relexp").emit()
     StoreImmDEx64("stlxp", "STLXPX64", 8, flavor="relexp").emit()
     StoreImmDEx64("stxp", "STXPW64", 4, flavor="exp").emit()