diff -r 1b834b01d375 -r 307cefea4123 configs/ruby/MOESI_hammer.py
--- a/configs/ruby/MOESI_hammer.py	Thu Feb 11 16:21:52 2016 -0600
+++ b/configs/ruby/MOESI_hammer.py	Thu Feb 11 16:22:10 2016 -0600
@@ -217,6 +217,7 @@
         dir_cntrl.requestToDir.slave = ruby_system.network.master
         dir_cntrl.dmaRequestToDir = MessageBuffer(ordered = True)
         dir_cntrl.dmaRequestToDir.slave = ruby_system.network.master
+        dir_cntrl.requestToMemory = MessageBuffer()
         dir_cntrl.responseFromMemory = MessageBuffer()
 
 
diff -r 1b834b01d375 -r 307cefea4123 src/mem/protocol/MOESI_hammer-dir.sm
--- a/src/mem/protocol/MOESI_hammer-dir.sm	Thu Feb 11 16:21:52 2016 -0600
+++ b/src/mem/protocol/MOESI_hammer-dir.sm	Thu Feb 11 16:22:10 2016 -0600
@@ -66,6 +66,7 @@
             vnet_type="request";
 
       MessageBuffer * triggerQueue;
+      MessageBuffer * requestToMemory;
       MessageBuffer * responseFromMemory;
 {
   // STATES
@@ -307,6 +308,7 @@
   // ** OUT_PORTS **
   out_port(requestQueue_out, ResponseMsg, requestToDir); // For recycling requests
   out_port(forwardNetwork_out, RequestMsg, forwardFromDir);
+  out_port(memQueue_out, MemoryMsg, requestToMemory);
   out_port(responseNetwork_out, ResponseMsg, responseFromDir);
   out_port(dmaResponseNetwork_out, DMAResponseMsg, dmaResponseFromDir);
   out_port(triggerQueue_out, TriggerMsg, triggerQueue);
@@ -848,13 +850,25 @@
 
   action(qf_queueMemoryFetchRequest, "qf", desc="Queue off-chip fetch request") {
     peek(requestQueue_in, RequestMsg) {
-      queueMemoryRead(in_msg.Requestor, address, to_memory_controller_latency);
+      enqueue(memQueue_out, MemoryMsg, to_memory_controller_latency) {
+        out_msg.addr := address;
+        out_msg.Type := MemoryRequestType:MEMORY_READ;
+        out_msg.Sender := in_msg.Requestor;
+        out_msg.MessageSize := MessageSizeType:Request_Control;
+        out_msg.Len := 0;
+      }
     }
   }
 
   action(qd_queueMemoryRequestFromDmaRead, "qd", desc="Queue off-chip fetch request") {
     peek(dmaRequestQueue_in, DMARequestMsg) {
-      queueMemoryRead(in_msg.Requestor, address, to_memory_controller_latency);
+      enqueue(memQueue_out, MemoryMsg, to_memory_controller_latency) {
+        out_msg.addr := address;
+        out_msg.Type := MemoryRequestType:MEMORY_READ;
+        out_msg.Sender := in_msg.Requestor;
+        out_msg.MessageSize := MessageSizeType:Request_Control;
+        out_msg.Len := 0;
+      }
     }
   }
 
@@ -1132,6 +1146,7 @@
 
   action(l_popMemQueue, "q", desc="Pop off-chip request queue") {
     memQueue_in.dequeue(clockEdge());
+    sendRetryRespIfBlocked();
   }
 
   action(g_popTriggerQueue, "g", desc="Pop trigger queue") {
@@ -1208,21 +1223,38 @@
 
   action(l_queueMemoryWBRequest, "lq", desc="Write PUTX data to memory") {
     peek(unblockNetwork_in, ResponseMsg) {
-      queueMemoryWrite(in_msg.Sender, address, to_memory_controller_latency,
-                       in_msg.DataBlk);
+      enqueue(memQueue_out, MemoryMsg, to_memory_controller_latency) {
+        out_msg.addr := address;
+        out_msg.Type := MemoryRequestType:MEMORY_WB;
+        out_msg.Sender := in_msg.Sender;
+        out_msg.MessageSize := MessageSizeType:Writeback_Data;
+        out_msg.DataBlk := in_msg.DataBlk;
+        out_msg.Len := 0;
+      }
     }
   }
 
   action(ld_queueMemoryDmaWrite, "ld", desc="Write DMA data to memory") {
     assert(is_valid(tbe));
-    queueMemoryWritePartial(tbe.DmaRequestor, tbe.PhysicalAddress,
-                            to_memory_controller_latency, tbe.DmaDataBlk,
-                            tbe.Len);
+    enqueue(memQueue_out, MemoryMsg, to_memory_controller_latency) {
+      out_msg.addr := tbe.PhysicalAddress;
+      out_msg.Type := MemoryRequestType:MEMORY_WB;
+      out_msg.Sender := tbe.DmaRequestor;
+      out_msg.MessageSize := MessageSizeType:Writeback_Data;
+      out_msg.DataBlk := tbe.DmaDataBlk;
+      out_msg.Len := tbe.Len;
+    }
   }
 
   action(ly_queueMemoryWriteFromTBE, "ly", desc="Write data to memory from TBE") {
-    queueMemoryWrite(machineID, address, to_memory_controller_latency,
-                     tbe.DataBlk);
+    enqueue(memQueue_out, MemoryMsg, to_memory_controller_latency) {
+      out_msg.addr := address;
+      out_msg.Type := MemoryRequestType:MEMORY_WB;
+      out_msg.Sender := tbe.DmaRequestor;
+      out_msg.MessageSize := MessageSizeType:Writeback_Data;
+      out_msg.DataBlk := tbe.DataBlk;
+      out_msg.Len := 0;
+    }
   }
 
   action(ll_checkIncomingWriteback, "\l", desc="Check PUTX/PUTO response message") {