diff --git a/src/sim/clock_domain.hh b/src/sim/clock_domain.hh
--- a/src/sim/clock_domain.hh
+++ b/src/sim/clock_domain.hh
@@ -244,6 +244,11 @@
 
   private:
     /**
+     * Inform other components about the changed performance level
+     */
+    void signalPerLevelUpdate();
+
+    /**
       * List of possible frequency operational points, should be in
       * descending order
       * An empty list corresponds to default frequency specified for its
# Node ID 7e1163aab210bbe9fd37fa2e69970c308d380aaa
# Parent  31c5786945b447b372c3b7d346aea8fa6208577c
diff --git a/src/sim/clock_domain.cc b/src/sim/clock_domain.cc
--- a/src/sim/clock_domain.cc
+++ b/src/sim/clock_domain.cc
@@ -147,6 +147,11 @@
 
     _perfLevel = perf_level;
 
+    signalPerLevelUpdate();
+}
+
+void SrcClockDomain::signalPerLevelUpdate()
+{
     // Signal the voltage domain that we have changed our perf level so that the
     // voltage domain can recompute its performance level
     voltageDomain()->sanitiseVoltages();
@@ -174,7 +179,7 @@
 {
     // Perform proper clock update when all related components have been
     // created (i.e. after unserialization / object creation)
-    perfLevel(_perfLevel);
+    signalPerLevelUpdate();
 }
 
 SrcClockDomain *