# Node ID 02756e2f20530d3de726d8b9ed7a40ee17e1ae8c # Parent 81cb93c4a16caf4b421a1acf8ebb913ba6df9c96 diff --git a/configs/ruby/GPU_RfO.py b/configs/ruby/GPU_RfO.py --- a/configs/ruby/GPU_RfO.py +++ b/configs/ruby/GPU_RfO.py @@ -492,6 +492,7 @@ dir_cntrl.triggerQueue = MessageBuffer(ordered = True) dir_cntrl.L3triggerQueue = MessageBuffer(ordered = True) + dir_cntrl.requestToMemory = MessageBuffer() dir_cntrl.responseFromMemory = MessageBuffer() exec("system.dir_cntrl%d = dir_cntrl" % i) diff --git a/configs/ruby/GPU_VIPER.py b/configs/ruby/GPU_VIPER.py --- a/configs/ruby/GPU_VIPER.py +++ b/configs/ruby/GPU_VIPER.py @@ -453,6 +453,7 @@ dir_cntrl.triggerQueue = MessageBuffer(ordered = True) dir_cntrl.L3triggerQueue = MessageBuffer(ordered = True) + dir_cntrl.requestToMemory = MessageBuffer() dir_cntrl.responseFromMemory = MessageBuffer() exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) diff --git a/configs/ruby/GPU_VIPER_Baseline.py b/configs/ruby/GPU_VIPER_Baseline.py --- a/configs/ruby/GPU_VIPER_Baseline.py +++ b/configs/ruby/GPU_VIPER_Baseline.py @@ -431,6 +431,7 @@ dir_cntrl.triggerQueue = MessageBuffer(ordered = True) dir_cntrl.L3triggerQueue = MessageBuffer(ordered = True) + dir_cntrl.requestToMemory = MessageBuffer() dir_cntrl.responseFromMemory = MessageBuffer() exec("system.dir_cntrl%d = dir_cntrl" % i) diff --git a/configs/ruby/GPU_VIPER_Region.py b/configs/ruby/GPU_VIPER_Region.py --- a/configs/ruby/GPU_VIPER_Region.py +++ b/configs/ruby/GPU_VIPER_Region.py @@ -711,6 +711,7 @@ dir_cntrl.triggerQueue = MessageBuffer(ordered = True) dir_cntrl.L3triggerQueue = MessageBuffer(ordered = True) + dir_cntrl.requestToMemory = MessageBuffer() dir_cntrl.responseFromMemory = MessageBuffer() exec("system.dir_cntrl%d = dir_cntrl" % i) diff --git a/src/mem/protocol/MOESI_AMD_Base-Region-dir.sm b/src/mem/protocol/MOESI_AMD_Base-Region-dir.sm --- a/src/mem/protocol/MOESI_AMD_Base-Region-dir.sm +++ b/src/mem/protocol/MOESI_AMD_Base-Region-dir.sm @@ -61,6 +61,8 @@ MessageBuffer * triggerQueue; MessageBuffer * L3triggerQueue; + + MessageBuffer * requestToMemory; MessageBuffer * responseFromMemory; { // STATES @@ -319,6 +321,8 @@ out_port(triggerQueue_out, TriggerMsg, triggerQueue); out_port(L3TriggerQueue_out, TriggerMsg, L3triggerQueue); + out_port(memQueue_out, MemoryMsg, requestToMemory); + // ** IN_PORTS ** // Trigger Queue @@ -841,7 +845,12 @@ DPRINTF(RubySlicc, "L3 data is %s\n", entry.DataBlk); L3CacheMemory.deallocate(address); } else { - queueMemoryRead(machineID, address, to_memory_controller_latency); + enqueue(memQueue_out, MemoryMsg, to_memory_controller_latency) { + out_msg.addr := address; + out_msg.Type := MemoryRequestType:MEMORY_READ; + out_msg.Sender := machineID; + out_msg.MessageSize := MessageSizeType:Request_Control; + } } } } @@ -862,7 +871,12 @@ DPRINTF(RubySlicc, "L3 data is %s\n", entry.DataBlk); L3CacheMemory.deallocate(address); } else { - queueMemoryRead(machineID, address, to_memory_controller_latency); + enqueue(memQueue_out, MemoryMsg, to_memory_controller_latency) { + out_msg.addr := address; + out_msg.Type := MemoryRequestType:MEMORY_READ; + out_msg.Sender := machineID; + out_msg.MessageSize := MessageSizeType:Request_Control; + } } } } @@ -1254,8 +1268,13 @@ Addr victim := L3CacheMemory.cacheProbe(address); CacheEntry victim_entry := static_cast(CacheEntry, "pointer", L3CacheMemory.lookup(victim)); - queueMemoryWrite(machineID, victim, to_memory_controller_latency, - victim_entry.DataBlk); + enqueue(memQueue_out, MemoryMsg, to_memory_controller_latency) { + out_msg.addr := victim; + out_msg.Type := MemoryRequestType:MEMORY_WB; + out_msg.Sender := machineID; + out_msg.MessageSize := MessageSizeType:Writeback_Data; + out_msg.DataBlk := victim_entry.DataBlk; + } L3CacheMemory.deallocate(victim); } assert(L3CacheMemory.cacheAvail(address)); @@ -1279,8 +1298,13 @@ Addr victim := L3CacheMemory.cacheProbe(address); CacheEntry victim_entry := static_cast(CacheEntry, "pointer", L3CacheMemory.lookup(victim)); - queueMemoryWrite(machineID, victim, to_memory_controller_latency, - victim_entry.DataBlk); + enqueue(memQueue_out, MemoryMsg, to_memory_controller_latency) { + out_msg.addr := victim; + out_msg.Type := MemoryRequestType:MEMORY_WB; + out_msg.Sender := machineID; + out_msg.MessageSize := MessageSizeType:Writeback_Data; + out_msg.DataBlk := victim_entry.DataBlk; + } L3CacheMemory.deallocate(victim); } assert(L3CacheMemory.cacheAvail(address)); @@ -1304,8 +1328,13 @@ Addr victim := L3CacheMemory.cacheProbe(address); CacheEntry victim_entry := static_cast(CacheEntry, "pointer", L3CacheMemory.lookup(victim)); - queueMemoryWrite(machineID, victim, to_memory_controller_latency, - victim_entry.DataBlk); + enqueue(memQueue_out, MemoryMsg, to_memory_controller_latency) { + out_msg.addr := victim; + out_msg.Type := MemoryRequestType:MEMORY_WB; + out_msg.Sender := machineID; + out_msg.MessageSize := MessageSizeType:Writeback_Data; + out_msg.DataBlk := victim_entry.DataBlk; + } L3CacheMemory.deallocate(victim); } assert(L3CacheMemory.cacheAvail(address)); @@ -1330,8 +1359,13 @@ Addr victim := L3CacheMemory.cacheProbe(address); CacheEntry victim_entry := static_cast(CacheEntry, "pointer", L3CacheMemory.lookup(victim)); - queueMemoryWrite(machineID, victim, to_memory_controller_latency, - victim_entry.DataBlk); + enqueue(memQueue_out, MemoryMsg, to_memory_controller_latency) { + out_msg.addr := victim; + out_msg.Type := MemoryRequestType:MEMORY_WB; + out_msg.Sender := machineID; + out_msg.MessageSize := MessageSizeType:Writeback_Data; + out_msg.DataBlk := victim_entry.DataBlk; + } L3CacheMemory.deallocate(victim); } assert(L3CacheMemory.cacheAvail(address)); diff --git a/src/mem/protocol/MOESI_AMD_Base-dir.sm b/src/mem/protocol/MOESI_AMD_Base-dir.sm --- a/src/mem/protocol/MOESI_AMD_Base-dir.sm +++ b/src/mem/protocol/MOESI_AMD_Base-dir.sm @@ -54,6 +54,8 @@ MessageBuffer * triggerQueue; MessageBuffer * L3triggerQueue; + + MessageBuffer * requestToMemory; MessageBuffer * responseFromMemory; { // STATES @@ -272,6 +274,8 @@ out_port(triggerQueue_out, TriggerMsg, triggerQueue); out_port(L3TriggerQueue_out, TriggerMsg, L3triggerQueue); + out_port(memQueue_out, MemoryMsg, requestToMemory); + // ** IN_PORTS ** // Trigger Queue @@ -518,8 +522,13 @@ action(l_queueMemWBReq, "lq", desc="Write WB data to memory") { peek(responseNetwork_in, ResponseMsg) { - queueMemoryWrite(machineID, address, to_memory_controller_latency, - in_msg.DataBlk); + enqueue(memQueue_out, MemoryMsg, to_memory_controller_latency) { + out_msg.addr := address; + out_msg.Type := MemoryRequestType:MEMORY_WB; + out_msg.Sender := machineID; + out_msg.MessageSize := MessageSizeType:Writeback_Data; + out_msg.DataBlk := in_msg.DataBlk; + } } } @@ -540,7 +549,12 @@ tbe.MemData := true; L3CacheMemory.deallocate(address); } else { - queueMemoryRead(machineID, address, to_memory_controller_latency); + enqueue(memQueue_out, MemoryMsg, to_memory_controller_latency) { + out_msg.addr := address; + out_msg.Type := MemoryRequestType:MEMORY_READ; + out_msg.Sender := machineID; + out_msg.MessageSize := MessageSizeType:Request_Control; + } } } } @@ -797,8 +811,13 @@ Addr victim := L3CacheMemory.cacheProbe(address); CacheEntry victim_entry := static_cast(CacheEntry, "pointer", L3CacheMemory.lookup(victim)); - queueMemoryWrite(machineID, victim, to_memory_controller_latency, - victim_entry.DataBlk); + enqueue(memQueue_out, MemoryMsg, to_memory_controller_latency) { + out_msg.addr := victim; + out_msg.Type := MemoryRequestType:MEMORY_WB; + out_msg.Sender := machineID; + out_msg.MessageSize := MessageSizeType:Writeback_Data; + out_msg.DataBlk := victim_entry.DataBlk; + } L3CacheMemory.deallocate(victim); } assert(L3CacheMemory.cacheAvail(address)); @@ -823,8 +842,13 @@ Addr victim := L3CacheMemory.cacheProbe(address); CacheEntry victim_entry := static_cast(CacheEntry, "pointer", L3CacheMemory.lookup(victim)); - queueMemoryWrite(machineID, victim, to_memory_controller_latency, - victim_entry.DataBlk); + enqueue(memQueue_out, MemoryMsg, to_memory_controller_latency) { + out_msg.addr := victim; + out_msg.Type := MemoryRequestType:MEMORY_WB; + out_msg.Sender := machineID; + out_msg.MessageSize := MessageSizeType:Writeback_Data; + out_msg.DataBlk := victim_entry.DataBlk; + } L3CacheMemory.deallocate(victim); } assert(L3CacheMemory.cacheAvail(address)); diff --git a/src/mem/protocol/MOESI_AMD_Base-probeFilter.sm b/src/mem/protocol/MOESI_AMD_Base-probeFilter.sm --- a/src/mem/protocol/MOESI_AMD_Base-probeFilter.sm +++ b/src/mem/protocol/MOESI_AMD_Base-probeFilter.sm @@ -66,6 +66,8 @@ MessageBuffer * triggerQueue, ordered="true"; MessageBuffer * L3triggerQueue, ordered="true"; + + MessageBuffer * requestToMemory; MessageBuffer * responseFromMemory; { // STATES @@ -350,6 +352,8 @@ out_port(triggerQueue_out, TriggerMsg, triggerQueue); out_port(L3TriggerQueue_out, TriggerMsg, L3triggerQueue); + out_port(memQueue_out, MemoryMsg, requestToMemory); + // ** IN_PORTS ** // Trigger Queue @@ -606,8 +610,13 @@ action(l_queueMemWBReq, "lq", desc="Write WB data to memory") { peek(responseNetwork_in, ResponseMsg) { - queueMemoryWrite(machineID, address, to_memory_controller_latency, - in_msg.DataBlk); + enqueue(memQueue_out, MemoryMsg, to_memory_controller_latency) { + out_msg.addr := address; + out_msg.Type := MemoryRequestType:MEMORY_WB; + out_msg.Sender := machineID; + out_msg.MessageSize := MessageSizeType:Writeback_Data; + out_msg.DataBlk := in_msg.DataBlk; + } } } @@ -626,7 +635,12 @@ tbe.MemData := true; L3CacheMemory.deallocate(address); } else { - queueMemoryRead(machineID, address, to_memory_controller_latency); + enqueue(memQueue_out, MemoryMsg, to_memory_controller_latency) { + out_msg.addr := address; + out_msg.Type := MemoryRequestType:MEMORY_READ; + out_msg.Sender := machineID; + out_msg.MessageSize := MessageSizeType:Request_Control; + } } } } @@ -943,8 +957,13 @@ Addr victim := L3CacheMemory.cacheProbe(address); CacheEntry victim_entry := static_cast(CacheEntry, "pointer", L3CacheMemory.lookup(victim)); - queueMemoryWrite(machineID, victim, to_memory_controller_latency, - victim_entry.DataBlk); + enqueue(memQueue_out, MemoryMsg, to_memory_controller_latency) { + out_msg.addr := victim; + out_msg.Type := MemoryRequestType:MEMORY_WB; + out_msg.Sender := machineID; + out_msg.MessageSize := MessageSizeType:Writeback_Data; + out_msg.DataBlk := victim_entry.DataBlk; + } L3CacheMemory.deallocate(victim); } assert(L3CacheMemory.cacheAvail(address)); @@ -969,8 +988,13 @@ Addr victim := L3CacheMemory.cacheProbe(address); CacheEntry victim_entry := static_cast(CacheEntry, "pointer", L3CacheMemory.lookup(victim)); - queueMemoryWrite(machineID, victim, to_memory_controller_latency, - victim_entry.DataBlk); + enqueue(memQueue_out, MemoryMsg, to_memory_controller_latency) { + out_msg.addr := victim; + out_msg.Type := MemoryRequestType:MEMORY_WB; + out_msg.Sender := machineID; + out_msg.MessageSize := MessageSizeType:Writeback_Data; + out_msg.DataBlk := victim_entry.DataBlk; + } L3CacheMemory.deallocate(victim); } assert(L3CacheMemory.cacheAvail(address)); diff --git a/src/mem/protocol/RubySlicc_MemControl.sm b/src/mem/protocol/RubySlicc_MemControl.sm --- a/src/mem/protocol/RubySlicc_MemControl.sm +++ b/src/mem/protocol/RubySlicc_MemControl.sm @@ -57,6 +57,7 @@ MachineID OriginalRequestorMachId, desc="What component originally requested"; DataBlock DataBlk, desc="Data to writeback"; MessageSizeType MessageSize, desc="size category of the message"; + int Len, default="0", desc="Size of the memory request"; // Not all fields used by all protocols: PrefetchBit Prefetch, desc="Is this a prefetch request"; bool ReadX, desc="Exclusive";