diff -r 0edcf757b6a2 -r 338a5d23f371 src/mem/cache/cache.cc
--- a/src/mem/cache/cache.cc	Sat Apr 09 12:13:40 2016 -0400
+++ b/src/mem/cache/cache.cc	Sat Apr 09 17:19:41 2016 +0100
@@ -1226,32 +1226,24 @@
 Cache::handleUncacheableWriteResp(PacketPtr pkt)
 {
     WriteQueueEntry *wq_entry =
-        dynamic_cast<WriteQueueEntry*>(pkt->senderState);
+        dynamic_cast<WriteQueueEntry*>(pkt->popSenderState());
     assert(wq_entry);
 
     WriteQueueEntry::Target *target = wq_entry->getTarget();
-    Packet *tgt_pkt = target->pkt;
 
-    // we send out invalidation reqs and get invalidation
-    // responses for write-line requests
-    assert(tgt_pkt->cmd != MemCmd::WriteLineReq);
-
-    int stats_cmd_idx = tgt_pkt->cmdToIndex();
+    int stats_cmd_idx = target->cmd.toInt();
     Tick miss_latency = curTick() - target->recvTime;
     assert(pkt->req->masterId() < system->maxMasters());
     mshr_uncacheable_lat[stats_cmd_idx][pkt->req->masterId()] +=
         miss_latency;
 
-    tgt_pkt->makeTimingResponse();
-    // if this packet is an error copy that to the new packet
-    if (pkt->isError())
-        tgt_pkt->copyError(pkt);
-    // Reset the bus additional time as it is now accounted for
-    tgt_pkt->headerDelay = tgt_pkt->payloadDelay = 0;
     Tick completion_time = clockEdge(responseLatency) +
         pkt->headerDelay + pkt->payloadDelay;
 
-    cpuSidePort->schedTimingResp(tgt_pkt, completion_time, true);
+    // Reset the bus additional time as it is now accounted for
+    pkt->headerDelay = pkt->payloadDelay = 0;
+
+    cpuSidePort->schedTimingResp(pkt, completion_time, true);
 
     wq_entry->popTarget();
     assert(!wq_entry->hasTargets());
@@ -1262,8 +1254,6 @@
     if (wasFull && !writeBuffer.isFull()) {
         clearBlocked(Blocked_NoWBBuffers);
     }
-
-    delete pkt;
 }
 
 void
@@ -1298,7 +1288,7 @@
 
     // we have dealt with any (uncacheable) writes above, from here on
     // we know we are dealing with an MSHR due to a miss or a prefetch
-    MSHR *mshr = dynamic_cast<MSHR*>(pkt->senderState);
+    MSHR *mshr = dynamic_cast<MSHR*>(pkt->popSenderState());
     assert(mshr);
 
     if (mshr == noTargetMSHR) {
@@ -2500,34 +2490,13 @@
             tgt_pkt->cmdString(), tgt_pkt->getAddr(),
             tgt_pkt->getSize());
 
-    PacketPtr pkt = nullptr;
-    bool delete_pkt = false;
+    // forward as is, both for evictions and uncacheable writes
+    tgt_pkt->pushSenderState(wq_entry);
 
-    if (tgt_pkt->isEviction()) {
-        assert(!wq_entry->isUncacheable());
-        // no response expected, just forward packet as it is
-        pkt = tgt_pkt;
-    } else {
-        // the only thing we deal with besides eviction commands
-        // are uncacheable writes
-        assert(tgt_pkt->req->isUncacheable() && tgt_pkt->isWrite());
-        // not a cache block request, but a response is expected
-        // make copy of current packet to forward, keep current
-        // copy for response handling
-        pkt = new Packet(tgt_pkt, false, true);
-        pkt->setData(tgt_pkt->getConstPtr<uint8_t>());
-        delete_pkt = true;
-    }
+    if (!memSidePort->sendTimingReq(tgt_pkt)) {
+        // undo the addition of the sender state
+        tgt_pkt->popSenderState();
 
-    pkt->pushSenderState(wq_entry);
-
-    if (!memSidePort->sendTimingReq(pkt)) {
-        if (delete_pkt) {
-            // we are awaiting a retry, but we
-            // delete the packet and will be creating a new packet
-            // when we get the opportunity
-            delete pkt;
-        }
         // note that we have now masked any requestBus and
         // schedSendEvent (we will wait for a retry before
         // doing anything), and this is so even if we do not
diff -r 0edcf757b6a2 -r 338a5d23f371 src/mem/cache/write_queue_entry.hh
--- a/src/mem/cache/write_queue_entry.hh	Sat Apr 09 12:13:40 2016 -0400
+++ b/src/mem/cache/write_queue_entry.hh	Sat Apr 09 17:19:41 2016 +0100
@@ -78,10 +78,11 @@
         const Tick readyTime; //!< Time when request is ready to be serviced
         const Counter order;  //!< Global order (for memory consistency mgmt)
         const PacketPtr pkt;  //!< Pending request packet.
+        const MemCmd cmd;     //!< Command as first seen by the cache
 
         Target(PacketPtr _pkt, Tick _readyTime, Counter _order)
             : recvTime(curTick()), readyTime(_readyTime), order(_order),
-              pkt(_pkt)
+              pkt(_pkt), cmd(pkt->cmd)
         {}
     };