# Node ID b188f1f37f106f1b4bbbcfb5005f7097644ecc67
# Parent  214335b48cb4e4d737a39ff3fda53067c8011161
diff --git a/src/mem/protocol/MESI_Three_Level-L0cache.sm b/src/mem/protocol/MESI_Three_Level-L0cache.sm
--- a/src/mem/protocol/MESI_Three_Level-L0cache.sm
+++ b/src/mem/protocol/MESI_Three_Level-L0cache.sm
@@ -510,6 +510,9 @@
     assert(is_valid(cache_entry));
     TBEs.allocate(address);
     set_tbe(TBEs[address]);
+  }
+
+  action(h_holdDataInTBE, desc="hold the data in the TBE in case required") {
     tbe.Dirty := cache_entry.Dirty;
     tbe.DataBlk := cache_entry.DataBlk;
   }
@@ -654,6 +657,7 @@
 
   transition(S, Store, SM) {
     i_allocateTBE;
+    h_holdDataInTBE;
     c_issueUPGRADE;
     uu_profileDataMiss;
     k_popMandatoryQueue;
diff --git a/src/mem/protocol/MESI_Three_Level-L1cache.sm b/src/mem/protocol/MESI_Three_Level-L1cache.sm
--- a/src/mem/protocol/MESI_Three_Level-L1cache.sm
+++ b/src/mem/protocol/MESI_Three_Level-L1cache.sm
@@ -631,6 +631,9 @@
     assert(is_valid(cache_entry));
     TBEs.allocate(address);
     set_tbe(TBEs[address]);
+  }
+
+  action(h_holdDataInTBE, desc="hold the data in the TBE in case required") {
     tbe.Dirty := cache_entry.Dirty;
     tbe.DataBlk := cache_entry.DataBlk;
   }
@@ -780,6 +783,7 @@
 
   transition({S,SS}, Store, SM) {
     i_allocateTBE;
+    h_holdDataInTBE;
     c_issueUPGRADE;
     uu_profileMiss;
     k_popL0RequestQueue;
@@ -810,7 +814,9 @@
   transition(EE, L1_Replacement, M_I) {
     // silent E replacement??
     i_allocateTBE;
-    g_issuePUTX;   // send data, but hold in case forwarded request
+    // send data, but hold in case forwarded request
+    h_holdDataInTBE;
+    g_issuePUTX;
     ff_deallocateCacheBlock;
   }
 
@@ -840,7 +846,9 @@
   // Transitions from Modified
   transition(MM, L1_Replacement, M_I) {
     i_allocateTBE;
-    g_issuePUTX;   // send data, but hold in case forwarded request
+    // send data, but hold in case forwarded request
+    h_holdDataInTBE;
+    g_issuePUTX;
     ff_deallocateCacheBlock;
   }
 
diff --git a/src/mem/protocol/MESI_Two_Level-L1cache.sm b/src/mem/protocol/MESI_Two_Level-L1cache.sm
--- a/src/mem/protocol/MESI_Two_Level-L1cache.sm
+++ b/src/mem/protocol/MESI_Two_Level-L1cache.sm
@@ -862,6 +862,9 @@
     assert(is_valid(cache_entry));
     TBEs.allocate(address);
     set_tbe(TBEs[address]);
+  }
+
+  action(h_holdDataInTBE, desc="hold the data in the TBE in case required") {
     tbe.isPrefetch := false;
     tbe.Dirty := cache_entry.Dirty;
     tbe.DataBlk := cache_entry.DataBlk;
@@ -1103,6 +1106,7 @@
 
   transition(S, Store, SM) {
     i_allocateTBE;
+    h_holdDataInTBE;
     c_issueUPGRADE;
     uu_profileDataMiss;
     k_popMandatoryQueue;
@@ -1131,7 +1135,9 @@
     // silent E replacement??
     forward_eviction_to_cpu;
     i_allocateTBE;
-    g_issuePUTX;   // send data, but hold in case forwarded request
+    // send data, but hold in case forwarded request
+    h_holdDataInTBE;
+    g_issuePUTX;
     ff_deallocateL1CacheBlock;
   }
 
@@ -1159,7 +1165,9 @@
   transition(M, L1_Replacement, M_I) {
     forward_eviction_to_cpu;
     i_allocateTBE;
-    g_issuePUTX;   // send data, but hold in case forwarded request
+    // send data, but hold in case forwarded request
+    h_holdDataInTBE;
+    g_issuePUTX;
     ff_deallocateL1CacheBlock;
   }
 
diff --git a/src/mem/protocol/MESI_Two_Level-L2cache.sm b/src/mem/protocol/MESI_Two_Level-L2cache.sm
--- a/src/mem/protocol/MESI_Two_Level-L2cache.sm
+++ b/src/mem/protocol/MESI_Two_Level-L2cache.sm
@@ -597,6 +597,9 @@
     TBEs.allocate(address);
     set_tbe(TBEs[address]);
     tbe.L1_GetS_IDs.clear();
+  }
+
+  action(h_holdDataInTBE, "", desc="hold the data in TBE in case required") {
     tbe.DataBlk := cache_entry.DataBlk;
     tbe.Dirty := cache_entry.Dirty;
     tbe.pendingAcks := cache_entry.Sharers.count();
@@ -922,12 +925,14 @@
 
   transition(SS, L2_Replacement_clean, I_I) {
     i_allocateTBE;
+    h_holdDataInTBE;
     f_sendInvToSharers;
     rr_deallocateL2CacheBlock;
   }
 
   transition(SS, {L2_Replacement, MEM_Inv}, S_I) {
     i_allocateTBE;
+    h_holdDataInTBE;
     f_sendInvToSharers;
     rr_deallocateL2CacheBlock;
   }
@@ -957,12 +962,14 @@
 
   transition(M, {L2_Replacement, MEM_Inv}, M_I) {
     i_allocateTBE;
+    h_holdDataInTBE;
     c_exclusiveReplacement;
     rr_deallocateL2CacheBlock;
   }
 
   transition(M, L2_Replacement_clean, M_I) {
     i_allocateTBE;
+    h_holdDataInTBE;
     c_exclusiveCleanReplacement;
     rr_deallocateL2CacheBlock;
   }
@@ -987,12 +994,14 @@
 
   transition(MT, {L2_Replacement, MEM_Inv}, MT_I) {
     i_allocateTBE;
+    h_holdDataInTBE;
     f_sendInvToSharers;
     rr_deallocateL2CacheBlock;
   }
 
   transition(MT, L2_Replacement_clean, MCT_I) {
     i_allocateTBE;
+    h_holdDataInTBE;
     f_sendInvToSharers;
     rr_deallocateL2CacheBlock;
   }
diff --git a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
--- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
@@ -680,8 +680,12 @@
     check_allocate(TBEs);
     TBEs.allocate(address);
     set_tbe(TBEs[address]);
+  }
+
+  action(h_holdDataInTBE, desc="hold the data in the TBE in case required") {
     assert(is_valid(cache_entry));
-    tbe.DataBlk := cache_entry.DataBlk; // Data only used for writebacks
+    // Data only used for writebacks
+    tbe.DataBlk := cache_entry.DataBlk;
     tbe.Dirty := cache_entry.Dirty;
   }
 
@@ -988,6 +992,7 @@
   // Transitions from Shared
   transition(S, Store, SM) {
     i_allocateTBE;
+    h_holdDataInTBE;
     b_issueGETX;
     uu_profileDataMiss;
     k_popMandatoryQueue;
@@ -995,6 +1000,7 @@
 
   transition(S, L1_Replacement, SI) {
     i_allocateTBE;
+    h_holdDataInTBE;
     dd_issuePUTS;
     forward_eviction_to_cpu;
     kk_deallocateL1CacheBlock;
@@ -1020,6 +1026,7 @@
   // Transitions from Owned
   transition(O, Store, OM) {
     i_allocateTBE;
+    h_holdDataInTBE;
     b_issueGETX;
     uu_profileDataMiss;
     k_popMandatoryQueue;
@@ -1027,6 +1034,7 @@
 
   transition(O, L1_Replacement, OI) {
     i_allocateTBE;
+    h_holdDataInTBE;
     dd_issuePUTO;
     forward_eviction_to_cpu;
     kk_deallocateL1CacheBlock;
@@ -1058,6 +1066,7 @@
 
   transition(MM, L1_Replacement, MI) {
     i_allocateTBE;
+    h_holdDataInTBE;
     d_issuePUTX;
     forward_eviction_to_cpu;
     kk_deallocateL1CacheBlock;
@@ -1096,6 +1105,7 @@
 
   transition(M, L1_Replacement, MI) {
     i_allocateTBE;
+    h_holdDataInTBE;
     d_issuePUTX;
     forward_eviction_to_cpu;
     kk_deallocateL1CacheBlock;
diff --git a/src/mem/protocol/MOESI_hammer-cache.sm b/src/mem/protocol/MOESI_hammer-cache.sm
--- a/src/mem/protocol/MOESI_hammer-cache.sm
+++ b/src/mem/protocol/MOESI_hammer-cache.sm
@@ -933,10 +933,14 @@
 
   action(i_allocateTBE, "i", desc="Allocate TBE") {
     check_allocate(TBEs);
-    assert(is_valid(cache_entry));
     TBEs.allocate(address);
     set_tbe(TBEs[address]);
-    tbe.DataBlk := cache_entry.DataBlk; // Data only used for writebacks
+  }
+
+  action(h_holdDataInTBE, desc="hold the data in the TBE in case required") {
+    assert(is_valid(cache_entry));
+    // Data only used for writebacks
+    tbe.DataBlk := cache_entry.DataBlk;
     tbe.Dirty := cache_entry.Dirty;
     tbe.Sharers := false;
   }
@@ -1348,6 +1352,7 @@
   // Transitions moving data between the L1 and L2 caches
   transition({S, O, M, MM}, L1_to_L2) {
     i_allocateTBE;
+    h_holdDataInTBE;
     gg_deallocateL1CacheBlock;
     vv_allocateL2CacheBlock;
     hp_copyFromTBEToL2;
@@ -1356,6 +1361,7 @@
 
   transition(S, Trigger_L2_to_L1D, ST) {
     i_allocateTBE;
+    h_holdDataInTBE;
     rr_deallocateL2CacheBlock;
     ii_allocateL1DCacheBlock;
     nb_copyFromTBEToL1;
@@ -1366,6 +1372,7 @@
 
   transition(O, Trigger_L2_to_L1D, OT) {
     i_allocateTBE;
+    h_holdDataInTBE;
     rr_deallocateL2CacheBlock;
     ii_allocateL1DCacheBlock;
     nb_copyFromTBEToL1;
@@ -1376,6 +1383,7 @@
 
   transition(M, Trigger_L2_to_L1D, MT) {
     i_allocateTBE;
+    h_holdDataInTBE;
     rr_deallocateL2CacheBlock;
     ii_allocateL1DCacheBlock;
     nb_copyFromTBEToL1;
@@ -1386,6 +1394,7 @@
 
   transition(MM, Trigger_L2_to_L1D, MMT) {
     i_allocateTBE;
+    h_holdDataInTBE;
     rr_deallocateL2CacheBlock;
     ii_allocateL1DCacheBlock;
     nb_copyFromTBEToL1;
@@ -1396,6 +1405,7 @@
 
   transition(S, Trigger_L2_to_L1I, ST) {
     i_allocateTBE;
+    h_holdDataInTBE;
     rr_deallocateL2CacheBlock;
     jj_allocateL1ICacheBlock;
     nb_copyFromTBEToL1;
@@ -1406,6 +1416,7 @@
 
   transition(O, Trigger_L2_to_L1I, OT) {
     i_allocateTBE;
+    h_holdDataInTBE;
     rr_deallocateL2CacheBlock;
     jj_allocateL1ICacheBlock;
     nb_copyFromTBEToL1;
@@ -1416,6 +1427,7 @@
 
   transition(M, Trigger_L2_to_L1I, MT) {
     i_allocateTBE;
+    h_holdDataInTBE;
     rr_deallocateL2CacheBlock;
     jj_allocateL1ICacheBlock;
     nb_copyFromTBEToL1;
@@ -1426,6 +1438,7 @@
 
   transition(MM, Trigger_L2_to_L1I, MMT) {
     i_allocateTBE;
+    h_holdDataInTBE;
     rr_deallocateL2CacheBlock;
     jj_allocateL1ICacheBlock;
     nb_copyFromTBEToL1;
@@ -1524,6 +1537,7 @@
 
   transition({S,SR}, Store, SM) {
     i_allocateTBE;
+    h_holdDataInTBE;
     b_issueGETX;
     uu_profileL1DataMiss;
     uu_profileL2Miss;
@@ -1532,6 +1546,7 @@
 
   transition({S, SR}, Flush_line, SM_F) {
     i_allocateTBE;
+    h_holdDataInTBE;
     bf_issueGETF;
     forward_eviction_to_cpu;
     gg_deallocateL1CacheBlock;
@@ -1587,6 +1602,7 @@
 
   transition({O,OR}, Store, OM) {
     i_allocateTBE;
+    h_holdDataInTBE;
     b_issueGETX;
     p_decrementNumberOfMessagesByOne;
     uu_profileL1DataMiss;
@@ -1596,6 +1612,7 @@
 
   transition({O, OR}, Flush_line, OM_F) {
     i_allocateTBE;
+    h_holdDataInTBE;
     bf_issueGETF;
     p_decrementNumberOfMessagesByOne;
     forward_eviction_to_cpu;
@@ -1605,6 +1622,7 @@
 
   transition(O, L2_Replacement, OI) {
     i_allocateTBE;
+    h_holdDataInTBE;
     d_issuePUT;
     forward_eviction_to_cpu;
     rr_deallocateL2CacheBlock;
@@ -1673,6 +1691,7 @@
 
   transition({MM, M, MMR, MR}, Flush_line, MM_F) {
     i_allocateTBE;
+    h_holdDataInTBE;
     bf_issueGETF;
     p_decrementNumberOfMessagesByOne;
     forward_eviction_to_cpu;
@@ -1688,6 +1707,7 @@
 
   transition(MM, L2_Replacement, MI) {
     i_allocateTBE;
+    h_holdDataInTBE;
     d_issuePUT;
     forward_eviction_to_cpu;
     rr_deallocateL2CacheBlock;
@@ -1756,6 +1776,7 @@
 
   transition(M, L2_Replacement, MI) {
     i_allocateTBE;
+    h_holdDataInTBE;
     d_issuePUT;
     forward_eviction_to_cpu;
     rr_deallocateL2CacheBlock;