# Node ID 4330a5015ddb79e0f50e01180942afce810d45e4
# Parent  9f0dee0a066985a9bd942478486931bc47014b56
diff --git a/src/mem/protocol/GPU_RfO-SQC.sm b/src/mem/protocol/GPU_RfO-SQC.sm
--- a/src/mem/protocol/GPU_RfO-SQC.sm
+++ b/src/mem/protocol/GPU_RfO-SQC.sm
@@ -106,7 +106,7 @@
     bool isPresent(Addr);
   }
 
-  TBETable TBEs, template="<SQC_TBE>", constructor="m_number_of_TBEs";
+  TBETable * TBEs, template="<SQC_TBE>", constructor="m_number_of_TBEs";
   int TCC_select_low_bit, default="RubySystem::getBlockSizeBits()";
 
   Tick clockEdge();
diff --git a/src/mem/protocol/GPU_RfO-TCC.sm b/src/mem/protocol/GPU_RfO-TCC.sm
--- a/src/mem/protocol/GPU_RfO-TCC.sm
+++ b/src/mem/protocol/GPU_RfO-TCC.sm
@@ -146,7 +146,7 @@
     bool isPresent(Addr);
   }
 
-  TBETable TBEs, template="<TCC_TBE>", constructor="m_number_of_TBEs";
+  TBETable * TBEs, template="<TCC_TBE>", constructor="m_number_of_TBEs";
   int TCC_select_low_bit, default="RubySystem::getBlockSizeBits()";
 
   void set_cache_entry(AbstractCacheEntry b);
diff --git a/src/mem/protocol/GPU_RfO-TCCdir.sm b/src/mem/protocol/GPU_RfO-TCCdir.sm
--- a/src/mem/protocol/GPU_RfO-TCCdir.sm
+++ b/src/mem/protocol/GPU_RfO-TCCdir.sm
@@ -236,7 +236,7 @@
   }
 
   // ** OBJECTS **
-  TBETable TBEs, template="<TCCdir_TBE>", constructor="m_number_of_TBEs";
+  TBETable * TBEs, template="<TCCdir_TBE>", constructor="m_number_of_TBEs";
   int TCC_select_low_bit, default="RubySystem::getBlockSizeBits()";
   NetDest TCC_dir_subtree;
   NetDest temp;
diff --git a/src/mem/protocol/GPU_RfO-TCP.sm b/src/mem/protocol/GPU_RfO-TCP.sm
--- a/src/mem/protocol/GPU_RfO-TCP.sm
+++ b/src/mem/protocol/GPU_RfO-TCP.sm
@@ -124,7 +124,7 @@
     bool isPresent(Addr);
   }
 
-  TBETable TBEs, template="<TCP_TBE>", constructor="m_number_of_TBEs";
+  TBETable * TBEs, template="<TCP_TBE>", constructor="m_number_of_TBEs";
   int TCC_select_low_bit, default="RubySystem::getBlockSizeBits()";
 
   Tick clockEdge();
diff --git a/src/mem/protocol/GPU_VIPER-SQC.sm b/src/mem/protocol/GPU_VIPER-SQC.sm
--- a/src/mem/protocol/GPU_VIPER-SQC.sm
+++ b/src/mem/protocol/GPU_VIPER-SQC.sm
@@ -90,7 +90,7 @@
     bool isPresent(Addr);
   }
 
-  TBETable TBEs, template="<SQC_TBE>", constructor="m_number_of_TBEs";
+  TBETable * TBEs, template="<SQC_TBE>", constructor="m_number_of_TBEs";
   int TCC_select_low_bit, default="RubySystem::getBlockSizeBits()";
 
   void set_cache_entry(AbstractCacheEntry b);
diff --git a/src/mem/protocol/GPU_VIPER-TCC.sm b/src/mem/protocol/GPU_VIPER-TCC.sm
--- a/src/mem/protocol/GPU_VIPER-TCC.sm
+++ b/src/mem/protocol/GPU_VIPER-TCC.sm
@@ -117,7 +117,7 @@
     bool isPresent(Addr);
   }
 
-  TBETable TBEs, template="<TCC_TBE>", constructor="m_number_of_TBEs";
+  TBETable * TBEs, template="<TCC_TBE>", constructor="m_number_of_TBEs";
 
   void set_cache_entry(AbstractCacheEntry b);
   void unset_cache_entry();
diff --git a/src/mem/protocol/GPU_VIPER-TCP.sm b/src/mem/protocol/GPU_VIPER-TCP.sm
--- a/src/mem/protocol/GPU_VIPER-TCP.sm
+++ b/src/mem/protocol/GPU_VIPER-TCP.sm
@@ -114,7 +114,7 @@
     bool isPresent(Addr);
   }
 
-  TBETable TBEs, template="<TCP_TBE>", constructor="m_number_of_TBEs";
+  TBETable * TBEs, template="<TCP_TBE>", constructor="m_number_of_TBEs";
   int TCC_select_low_bit, default="RubySystem::getBlockSizeBits()";
   int WTcnt, default="0";
   int Fcnt, default="0";
diff --git a/src/mem/protocol/GPU_VIPER_Region-TCC.sm b/src/mem/protocol/GPU_VIPER_Region-TCC.sm
--- a/src/mem/protocol/GPU_VIPER_Region-TCC.sm
+++ b/src/mem/protocol/GPU_VIPER_Region-TCC.sm
@@ -122,7 +122,7 @@
     bool isPresent(Addr);
   }
 
-  TBETable TBEs, template="<TCC_TBE>", constructor="m_number_of_TBEs";
+  TBETable * TBEs, template="<TCC_TBE>", constructor="m_number_of_TBEs";
 
   void set_cache_entry(AbstractCacheEntry b);
   void unset_cache_entry();
diff --git a/src/mem/protocol/MESI_Three_Level-L0cache.sm b/src/mem/protocol/MESI_Three_Level-L0cache.sm
--- a/src/mem/protocol/MESI_Three_Level-L0cache.sm
+++ b/src/mem/protocol/MESI_Three_Level-L0cache.sm
@@ -133,7 +133,7 @@
     bool isPresent(Addr);
   }
 
-  TBETable TBEs, template="<L0Cache_TBE>", constructor="m_number_of_TBEs";
+  TBETable * TBEs, template="<L0Cache_TBE>", constructor="m_number_of_TBEs";
 
   Tick clockEdge();
   Cycles ticksToCycles(Tick t);
diff --git a/src/mem/protocol/MESI_Three_Level-L1cache.sm b/src/mem/protocol/MESI_Three_Level-L1cache.sm
--- a/src/mem/protocol/MESI_Three_Level-L1cache.sm
+++ b/src/mem/protocol/MESI_Three_Level-L1cache.sm
@@ -147,7 +147,7 @@
     bool isPresent(Addr);
   }
 
-  TBETable TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs";
+  TBETable * TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs";
 
   int l2_select_low_bit, default="RubySystem::getBlockSizeBits()";
 
diff --git a/src/mem/protocol/MESI_Two_Level-L1cache.sm b/src/mem/protocol/MESI_Two_Level-L1cache.sm
--- a/src/mem/protocol/MESI_Two_Level-L1cache.sm
+++ b/src/mem/protocol/MESI_Two_Level-L1cache.sm
@@ -152,7 +152,7 @@
     bool isPresent(Addr);
   }
 
-  TBETable TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs";
+  TBETable * TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs";
 
   int l2_select_low_bit, default="RubySystem::getBlockSizeBits()";
 
diff --git a/src/mem/protocol/MESI_Two_Level-L2cache.sm b/src/mem/protocol/MESI_Two_Level-L2cache.sm
--- a/src/mem/protocol/MESI_Two_Level-L2cache.sm
+++ b/src/mem/protocol/MESI_Two_Level-L2cache.sm
@@ -146,7 +146,7 @@
     bool isPresent(Addr);
   }
 
-  TBETable TBEs, template="<L2Cache_TBE>", constructor="m_number_of_TBEs";
+  TBETable * TBEs, template="<L2Cache_TBE>", constructor="m_number_of_TBEs";
 
   Tick clockEdge();
   Tick cyclesToTicks(Cycles c);
diff --git a/src/mem/protocol/MESI_Two_Level-dir.sm b/src/mem/protocol/MESI_Two_Level-dir.sm
--- a/src/mem/protocol/MESI_Two_Level-dir.sm
+++ b/src/mem/protocol/MESI_Two_Level-dir.sm
@@ -96,7 +96,7 @@
 
 
   // ** OBJECTS **
-  TBETable TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs";
+  TBETable * TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs";
 
   Tick clockEdge();
   Tick cyclesToTicks(Cycles c);
diff --git a/src/mem/protocol/MI_example-cache.sm b/src/mem/protocol/MI_example-cache.sm
--- a/src/mem/protocol/MI_example-cache.sm
+++ b/src/mem/protocol/MI_example-cache.sm
@@ -100,7 +100,7 @@
 
 
   // STRUCTURES
-  TBETable TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs";
+  TBETable * TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs";
 
   // PROTOTYPES
   Tick clockEdge();
diff --git a/src/mem/protocol/MI_example-dir.sm b/src/mem/protocol/MI_example-dir.sm
--- a/src/mem/protocol/MI_example-dir.sm
+++ b/src/mem/protocol/MI_example-dir.sm
@@ -106,7 +106,7 @@
   }
 
   // ** OBJECTS **
-  TBETable TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs";
+  TBETable * TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs";
 
   Tick clockEdge();
   Cycles ticksToCycles(Tick t);
diff --git a/src/mem/protocol/MOESI_AMD_Base-CorePair.sm b/src/mem/protocol/MOESI_AMD_Base-CorePair.sm
--- a/src/mem/protocol/MOESI_AMD_Base-CorePair.sm
+++ b/src/mem/protocol/MOESI_AMD_Base-CorePair.sm
@@ -221,7 +221,7 @@
     bool isPresent(Addr);
   }
 
-  TBETable TBEs, template="<CorePair_TBE>", constructor="m_number_of_TBEs";
+  TBETable * TBEs, template="<CorePair_TBE>", constructor="m_number_of_TBEs";
 
   void set_cache_entry(AbstractCacheEntry b);
   void unset_cache_entry();
diff --git a/src/mem/protocol/MOESI_AMD_Base-L3cache.sm b/src/mem/protocol/MOESI_AMD_Base-L3cache.sm
--- a/src/mem/protocol/MOESI_AMD_Base-L3cache.sm
+++ b/src/mem/protocol/MOESI_AMD_Base-L3cache.sm
@@ -147,7 +147,7 @@
     bool isPresent(Addr);
   }
 
-  TBETable TBEs, template="<L3Cache_TBE>", constructor="m_number_of_TBEs";
+  TBETable * TBEs, template="<L3Cache_TBE>", constructor="m_number_of_TBEs";
 
   void set_cache_entry(AbstractCacheEntry b);
   void unset_cache_entry();
diff --git a/src/mem/protocol/MOESI_AMD_Base-Region-CorePair.sm b/src/mem/protocol/MOESI_AMD_Base-Region-CorePair.sm
--- a/src/mem/protocol/MOESI_AMD_Base-Region-CorePair.sm
+++ b/src/mem/protocol/MOESI_AMD_Base-Region-CorePair.sm
@@ -225,7 +225,7 @@
     bool isPresent(Addr);
   }
 
-  TBETable TBEs, template="<CorePair_TBE>", constructor="m_number_of_TBEs";
+  TBETable * TBEs, template="<CorePair_TBE>", constructor="m_number_of_TBEs";
 
   Tick clockEdge();
   Tick cyclesToTicks(Cycles c);
diff --git a/src/mem/protocol/MOESI_AMD_Base-Region-dir.sm b/src/mem/protocol/MOESI_AMD_Base-Region-dir.sm
--- a/src/mem/protocol/MOESI_AMD_Base-Region-dir.sm
+++ b/src/mem/protocol/MOESI_AMD_Base-Region-dir.sm
@@ -199,7 +199,7 @@
     bool isPresent(Addr);
   }
 
-  TBETable TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs";
+  TBETable * TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs";
 
   Tick clockEdge();
   Tick cyclesToTicks(Cycles c);
diff --git a/src/mem/protocol/MOESI_AMD_Base-RegionBuffer.sm b/src/mem/protocol/MOESI_AMD_Base-RegionBuffer.sm
--- a/src/mem/protocol/MOESI_AMD_Base-RegionBuffer.sm
+++ b/src/mem/protocol/MOESI_AMD_Base-RegionBuffer.sm
@@ -184,7 +184,7 @@
   }
 
   // Stores only region addresses
-  TBETable TBEs, template="<RegionBuffer_TBE>", constructor="m_number_of_TBEs";
+  TBETable * TBEs, template="<RegionBuffer_TBE>", constructor="m_number_of_TBEs";
   int TCC_select_low_bit, default="RubySystem::getBlockSizeBits()";
 
   Tick clockEdge();
diff --git a/src/mem/protocol/MOESI_AMD_Base-RegionDir.sm b/src/mem/protocol/MOESI_AMD_Base-RegionDir.sm
--- a/src/mem/protocol/MOESI_AMD_Base-RegionDir.sm
+++ b/src/mem/protocol/MOESI_AMD_Base-RegionDir.sm
@@ -158,7 +158,7 @@
   }
 
   // Stores only region addresses
-  TBETable TBEs, template="<RegionDir_TBE>", constructor="m_number_of_TBEs";
+  TBETable * TBEs, template="<RegionDir_TBE>", constructor="m_number_of_TBEs";
   int TCC_select_low_bit, default="RubySystem::getBlockSizeBits()";
 
   Tick clockEdge();
diff --git a/src/mem/protocol/MOESI_AMD_Base-dir.sm b/src/mem/protocol/MOESI_AMD_Base-dir.sm
--- a/src/mem/protocol/MOESI_AMD_Base-dir.sm
+++ b/src/mem/protocol/MOESI_AMD_Base-dir.sm
@@ -157,7 +157,7 @@
     bool isPresent(Addr);
   }
 
-  TBETable TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs";
+  TBETable * TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs";
 
   int TCC_select_low_bit, default="RubySystem::getBlockSizeBits()";
 
diff --git a/src/mem/protocol/MOESI_AMD_Base-probeFilter.sm b/src/mem/protocol/MOESI_AMD_Base-probeFilter.sm
--- a/src/mem/protocol/MOESI_AMD_Base-probeFilter.sm
+++ b/src/mem/protocol/MOESI_AMD_Base-probeFilter.sm
@@ -189,7 +189,7 @@
     bool isPresent(Addr);
   }
 
-  TBETable TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs";
+  TBETable * TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs";
 
   int TCC_select_low_bit, default="RubySystem::getBlockSizeBits()";
 
diff --git a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
--- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
@@ -140,8 +140,8 @@
   void set_tbe(TBE b);
   void unset_tbe();
 
-  TBETable TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs";
-  TimerTable useTimerTable;
+  TBETable * TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs";
+  TimerTable * useTimerTable;
   int l2_select_low_bit, default="RubySystem::getBlockSizeBits()";
 
   Entry getCacheEntry(Addr addr), return_by_pointer="yes" {
diff --git a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
--- a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
@@ -224,8 +224,8 @@
     bool isTagPresent(Addr);
   }
 
-  TBETable TBEs, template="<L2Cache_TBE>", constructor="m_number_of_TBEs";
-  PerfectCacheMemory localDirectory, template="<L2Cache_DirEntry>";
+  TBETable * TBEs, template="<L2Cache_TBE>", constructor="m_number_of_TBEs";
+  PerfectCacheMemory * localDirectory, template="<L2Cache_DirEntry>";
 
   Tick clockEdge();
   Tick cyclesToTicks(Cycles c);
diff --git a/src/mem/protocol/MOESI_CMP_directory-dir.sm b/src/mem/protocol/MOESI_CMP_directory-dir.sm
--- a/src/mem/protocol/MOESI_CMP_directory-dir.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-dir.sm
@@ -117,7 +117,7 @@
   }
 
   // ** OBJECTS **
-  TBETable TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs";
+  TBETable * TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs";
 
   Tick clockEdge();
   Tick cyclesToTicks(Cycles c);
diff --git a/src/mem/protocol/MOESI_CMP_directory-dma.sm b/src/mem/protocol/MOESI_CMP_directory-dma.sm
--- a/src/mem/protocol/MOESI_CMP_directory-dma.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-dma.sm
@@ -71,7 +71,7 @@
     bool isPresent(Addr);
   }
 
-  TBETable TBEs, template="<DMA_TBE>", constructor="m_number_of_TBEs";
+  TBETable * TBEs, template="<DMA_TBE>", constructor="m_number_of_TBEs";
   State cur_state;
 
   Tick clockEdge();
diff --git a/src/mem/protocol/MOESI_CMP_token-L1cache.sm b/src/mem/protocol/MOESI_CMP_token-L1cache.sm
--- a/src/mem/protocol/MOESI_CMP_token-L1cache.sm
+++ b/src/mem/protocol/MOESI_CMP_token-L1cache.sm
@@ -194,14 +194,14 @@
   void wakeUpBuffers(Addr a);
   Cycles curCycle();
 
-  TBETable L1_TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs";
+  TBETable * L1_TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs";
 
   bool starving, default="false";
   int l2_select_low_bit, default="RubySystem::getBlockSizeBits()";
 
-  PersistentTable persistentTable;
-  TimerTable useTimerTable;
-  TimerTable reissueTimerTable;
+  PersistentTable * persistentTable;
+  TimerTable * useTimerTable;
+  TimerTable * reissueTimerTable;
 
   int outstandingRequests, default="0";
   int outstandingPersistentRequests, default="0";
@@ -209,7 +209,7 @@
   // Constant that provides hysteresis for calculated the estimated average
   int averageLatencyHysteresis, default="(8)";
   Cycles averageLatencyCounter,
-        default="(Cycles(500) << (*m_averageLatencyHysteresis_ptr))";
+        default="(Cycles(500) << m_averageLatencyHysteresis)";
 
   Cycles averageLatencyEstimate() {
     DPRINTF(RubySlicc, "%d\n",
diff --git a/src/mem/protocol/MOESI_CMP_token-L2cache.sm b/src/mem/protocol/MOESI_CMP_token-L2cache.sm
--- a/src/mem/protocol/MOESI_CMP_token-L2cache.sm
+++ b/src/mem/protocol/MOESI_CMP_token-L2cache.sm
@@ -146,8 +146,8 @@
     int countReadStarvingForAddress(Addr);
   }
 
-  PersistentTable persistentTable;
-  PerfectCacheMemory localDirectory, template="<L2Cache_DirEntry>";
+  PersistentTable * persistentTable;
+  PerfectCacheMemory * localDirectory, template="<L2Cache_DirEntry>";
 
   Tick clockEdge();
   void set_cache_entry(AbstractCacheEntry b);
diff --git a/src/mem/protocol/MOESI_CMP_token-dir.sm b/src/mem/protocol/MOESI_CMP_token-dir.sm
--- a/src/mem/protocol/MOESI_CMP_token-dir.sm
+++ b/src/mem/protocol/MOESI_CMP_token-dir.sm
@@ -164,10 +164,10 @@
 
   // ** OBJECTS **
 
-  PersistentTable persistentTable;
-  TimerTable reissueTimerTable;
+  PersistentTable * persistentTable;
+  TimerTable * reissueTimerTable;
 
-  TBETable TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs";
+  TBETable * TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs";
 
   bool starving, default="false";
   int l2_select_low_bit, default="RubySystem::getBlockSizeBits()";
diff --git a/src/mem/protocol/MOESI_hammer-cache.sm b/src/mem/protocol/MOESI_hammer-cache.sm
--- a/src/mem/protocol/MOESI_hammer-cache.sm
+++ b/src/mem/protocol/MOESI_hammer-cache.sm
@@ -178,7 +178,7 @@
     bool isPresent(Addr);
   }
 
-  TBETable TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs";
+  TBETable * TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs";
 
   Tick clockEdge();
   void set_cache_entry(AbstractCacheEntry b);
diff --git a/src/mem/protocol/MOESI_hammer-dir.sm b/src/mem/protocol/MOESI_hammer-dir.sm
--- a/src/mem/protocol/MOESI_hammer-dir.sm
+++ b/src/mem/protocol/MOESI_hammer-dir.sm
@@ -196,7 +196,7 @@
 
   Set fwd_set;
 
-  TBETable TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs";
+  TBETable * TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs";
 
   Entry getDirectoryEntry(Addr addr), return_by_pointer="yes" {
     Entry dir_entry := static_cast(Entry, "pointer", directory[addr]);
diff --git a/src/mem/slicc/ast/ActionDeclAST.py b/src/mem/slicc/ast/ActionDeclAST.py
--- a/src/mem/slicc/ast/ActionDeclAST.py
+++ b/src/mem/slicc/ast/ActionDeclAST.py
@@ -54,17 +54,18 @@
                 self.error("Type 'Addr' not declared.")
 
             var = Var(self.symtab, "address", self.location, addr_type,
-                      "addr", self.pairs)
+                      False, "addr", self.pairs)
             self.symtab.newSymbol(var)
 
             if machine.TBEType != None:
                 var = Var(self.symtab, "tbe", self.location, machine.TBEType,
-                      "m_tbe_ptr", self.pairs)
+                          True, "m_tbe_ptr", self.pairs)
                 self.symtab.newSymbol(var)
 
             if machine.EntryType != None:
                 var = Var(self.symtab, "cache_entry", self.location,
-                          machine.EntryType, "m_cache_entry_ptr", self.pairs)
+                          machine.EntryType, True, "m_cache_entry_ptr",
+                          self.pairs)
                 self.symtab.newSymbol(var)
 
             # Do not allows returns in actions
diff --git a/src/mem/slicc/ast/EnqueueStatementAST.py b/src/mem/slicc/ast/EnqueueStatementAST.py
--- a/src/mem/slicc/ast/EnqueueStatementAST.py
+++ b/src/mem/slicc/ast/EnqueueStatementAST.py
@@ -50,8 +50,8 @@
         msg_type = self.type_ast.type
 
         # Add new local var to symbol table
-        v = Var(self.symtab, "out_msg", self.location, msg_type, "*out_msg",
-                self.pairs)
+        v = Var(self.symtab, "out_msg", self.location, msg_type, True,
+                "*out_msg", self.pairs)
         self.symtab.newSymbol(v)
 
         # Declare message
diff --git a/src/mem/slicc/ast/FormalParamAST.py b/src/mem/slicc/ast/FormalParamAST.py
--- a/src/mem/slicc/ast/FormalParamAST.py
+++ b/src/mem/slicc/ast/FormalParamAST.py
@@ -48,8 +48,8 @@
         param = "param_%s" % self.ident
 
         # Add to symbol table
-        v = Var(self.symtab, self.ident, self.location, type, param,
-                self.pairs)
+        v = Var(self.symtab, self.ident, self.location, type,
+                self.pointer, param, self.pairs)
         self.symtab.newSymbol(v)
 
         if self.pointer or str(type) == "TBE" or (
diff --git a/src/mem/slicc/ast/InPortDeclAST.py b/src/mem/slicc/ast/InPortDeclAST.py
--- a/src/mem/slicc/ast/InPortDeclAST.py
+++ b/src/mem/slicc/ast/InPortDeclAST.py
@@ -59,8 +59,8 @@
 
         type = self.queue_type.type
         self.pairs["buffer_expr"] = self.var_expr
-        in_port = Var(self.symtab, self.ident, self.location, type, str(code),
-                      self.pairs, machine)
+        in_port = Var(self.symtab, self.ident, self.location, type, False,
+                      str(code), self.pairs, machine)
         symtab.newSymbol(in_port)
 
         symtab.pushFrame()
diff --git a/src/mem/slicc/ast/LocalVariableAST.py b/src/mem/slicc/ast/LocalVariableAST.py
--- a/src/mem/slicc/ast/LocalVariableAST.py
+++ b/src/mem/slicc/ast/LocalVariableAST.py
@@ -57,8 +57,8 @@
         ident = "%s" % self.ident;
 
         # Add to symbol table
-        v = Var(self.symtab, self.ident, self.location, type, ident,
-                self.pairs)
+        v = Var(self.symtab, self.ident, self.location, type, self.pointer,
+                ident, self.pairs)
         self.symtab.newSymbol(v)
         if self.pointer or str(type) == "TBE" or (
            "interface" in type and (
diff --git a/src/mem/slicc/ast/ObjDeclAST.py b/src/mem/slicc/ast/ObjDeclAST.py
--- a/src/mem/slicc/ast/ObjDeclAST.py
+++ b/src/mem/slicc/ast/ObjDeclAST.py
@@ -41,24 +41,16 @@
         return "[ObjDecl: %r]" % self.ident
 
     def generate(self, parent = None):
-        if "network" in self and not ("virtual_network" in self or
-                                      "physical_network" in self) :
+        if "network" in self and not ("virtual_network" in self):
             self.error("Network queues require a 'virtual_network' attribute")
 
         type = self.type_ast.type
 
-        # FIXME : should all use accessors here to avoid public member
-        # variables
-        if self.ident == "version":
-            c_code = "m_version"
-        elif self.ident == "machineID":
-            c_code = "m_machineID"
-        elif self.ident == "clusterID":
-            c_code = "m_clusterID"
-        elif self.ident == "recycle_latency":
-            c_code = "m_recycle_latency"
+        c_code = ""
+        if self.pointer:
+            c_code = "(*m_%s)" % (self.ident)
         else:
-            c_code = "(*m_%s_ptr)" % (self.ident)
+            c_code = "m_%s" % (self.ident)
 
         # check type if this is a initialization
         init_code = ""
@@ -70,12 +62,13 @@
 
         machine = self.symtab.state_machine
 
-        v = Var(self.symtab, self.ident, self.location, type, c_code,
-                self.pairs, machine)
+        v = Var(self.symtab, self.ident, self.location, type, self.pointer,
+                c_code, self.pairs, machine)
 
         # Add data member to the parent type
         if parent:
-            if not parent.addDataMember(self.ident, type, self.pairs, init_code):
+            if not parent.addDataMember(self.ident, type, self.pointer,
+                                        self.pairs, init_code):
                 self.error("Duplicate data member: %s:%s" % (parent, self.ident))
 
         elif machine:
diff --git a/src/mem/slicc/ast/OutPortDeclAST.py b/src/mem/slicc/ast/OutPortDeclAST.py
--- a/src/mem/slicc/ast/OutPortDeclAST.py
+++ b/src/mem/slicc/ast/OutPortDeclAST.py
@@ -44,8 +44,8 @@
 
     def generate(self):
         code = self.slicc.codeFormatter(newlines=False)
+        queue_type = self.var_expr.generate(code)
 
-        queue_type = self.var_expr.generate(code)
         if not queue_type.isOutPort:
             self.error("The outport queue's type must have the 'outport' " +
                        "attribute.  Type '%s' does not have this attribute.",
@@ -56,5 +56,5 @@
                        self.msg_type.ident)
 
         var = Var(self.symtab, self.ident, self.location, self.queue_type.type,
-                  str(code), self.pairs)
+                  False, str(code), self.pairs)
         self.symtab.newSymbol(var)
diff --git a/src/mem/slicc/ast/PeekStatementAST.py b/src/mem/slicc/ast/PeekStatementAST.py
--- a/src/mem/slicc/ast/PeekStatementAST.py
+++ b/src/mem/slicc/ast/PeekStatementAST.py
@@ -48,22 +48,22 @@
         msg_type = self.type_ast.type
 
         # Add new local var to symbol table
-        var = Var(self.symtab, "in_msg", self.location, msg_type, "(*in_msg_ptr)",
-                  self.pairs)
+        var = Var(self.symtab, "in_msg", self.location, msg_type, True,
+                  "(*in_msg)", self.pairs)
         self.symtab.newSymbol(var)
 
         # Check the queue type
         self.queue_name.assertType("InPort")
 
-        # Declare the new "in_msg_ptr" variable
+        # Declare the new "in_msg" variable
         mtid = msg_type.c_ident
         qcode = self.queue_name.var.code
         code('''
 {
     // Declare message
-    const $mtid* in_msg_ptr M5_VAR_USED;
-    in_msg_ptr = dynamic_cast<const $mtid *>(($qcode).${{self.method}}());
-    if (in_msg_ptr == NULL) {
+    const $mtid* in_msg M5_VAR_USED;
+    in_msg = dynamic_cast<const $mtid *>(($qcode).${{self.method}}());
+    if (in_msg == NULL) {
         // If the cast fails, this is the wrong inport (wrong message type).
         // Throw an exception, and the caller will decide to either try a
         // different inport or punt.
@@ -75,8 +75,8 @@
             address_field = self.pairs['block_on']
             code('''
     if (m_is_blocking &&
-        (m_block_map.count(in_msg_ptr->m_$address_field) == 1) &&
-        (m_block_map[in_msg_ptr->m_$address_field] != &$qcode)) {
+        (m_block_map.count(in_msg->m_$address_field) == 1) &&
+        (m_block_map[in_msg->m_$address_field] != &$qcode)) {
             $qcode.delayHead(clockEdge(), cyclesToTicks(Cycles(1)));
             continue;
     }
@@ -85,8 +85,8 @@
         if self.pairs.has_key("wake_up"):
             address_field = self.pairs['wake_up']
             code('''
-    if (m_waiting_buffers.count(in_msg_ptr->m_$address_field) > 0) {
-        wakeUpBuffers(in_msg_ptr->m_$address_field);
+    if (m_waiting_buffers.count(in_msg->m_$address_field) > 0) {
+        wakeUpBuffers(in_msg->m_$address_field);
     }
             ''')
 
diff --git a/src/mem/slicc/symbols/StateMachine.py b/src/mem/slicc/symbols/StateMachine.py
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -68,10 +68,10 @@
         for param in config_parameters:
             if param.pointer:
                 var = Var(symtab, param.ident, location, param.type_ast.type,
-                          "(*m_%s_ptr)" % param.ident, {}, self)
+                          True, "(*m_%s)" % param.ident, {}, self)
             else:
                 var = Var(symtab, param.ident, location, param.type_ast.type,
-                          "m_%s" % param.ident, {}, self)
+                          False, "m_%s" % param.ident, {}, self)
 
             self.symtab.registerSym(param.ident, var)
 
@@ -327,7 +327,7 @@
         # added by SS
         for param in self.config_parameters:
             if param.pointer:
-                code('${{param.type_ast.type}}* m_${{param.ident}}_ptr;')
+                code('${{param.type_ast.type}} *m_${{param.ident}};')
             else:
                 code('${{param.type_ast.type}} m_${{param.ident}};')
 
@@ -429,7 +429,10 @@
 ''')
         for var in self.objects:
             th = var.get("template", "")
-            code('${{var.type.c_ident}}$th* m_${{var.ident}}_ptr;')
+            if var.pointer:
+                code('${{var.type.c_ident}}$th *m_${{var.ident}};')
+            else:
+                code('${{var.type.c_ident}}$th m_${{var.ident}};')
 
         code.dedent()
         code('};')
@@ -527,17 +530,14 @@
         # include a sequencer, connect the it to the controller.
         #
         for param in self.config_parameters:
-            if param.pointer:
-                code('m_${{param.ident}}_ptr = p->${{param.ident}};')
-            else:
-                code('m_${{param.ident}} = p->${{param.ident}};')
+            code('m_${{param.ident}} = p->${{param.ident}};')
 
             if re.compile("sequencer").search(param.ident) or \
                    param.type_ast.type.c_ident == "GPUCoalescer" or \
                    param.type_ast.type.c_ident == "VIPERCoalescer":
                 code('''
-if (m_${{param.ident}}_ptr != NULL) {
-    m_${{param.ident}}_ptr->setController(this);
+if (m_${{param.ident}} != NULL) {
+    m_${{param.ident}}->setController(this);
 }
 ''')
 
@@ -572,7 +572,7 @@
         vnet_dir_set = set()
 
         for var in self.config_parameters:
-            vid = "m_%s_ptr" % var.ident
+            vid = "m_%s" % var.ident
             if "network" in var:
                 vtype = var.type_ast.type
                 code('assert($vid != NULL);')
@@ -609,29 +609,25 @@
 
         for var in self.objects:
             vtype = var.type
-            vid = "m_%s_ptr" % var.ident
-            if "network" not in var:
-                # Not a network port object
-                if "primitive" in vtype:
-                    code('$vid = new ${{vtype.c_ident}};')
-                    if "default" in var:
-                        code('(*$vid) = ${{var["default"]}};')
-                else:
-                    # Normal Object
-                    th = var.get("template", "")
-                    expr = "%s  = new %s%s" % (vid, vtype.c_ident, th)
-                    args = ""
-                    if "non_obj" not in vtype and not vtype.isEnumeration:
-                        args = var.get("constructor", "")
+            vid = "m_%s" % var.ident
 
-                    code('$expr($args);')
-                    code('assert($vid != NULL);')
+            if var.pointer:
+                th = var.get("template", "")
+                expr = "%s  = new %s%s" % (vid, vtype.c_ident, th)
+                args = ""
+                if "non_obj" not in vtype and not vtype.isEnumeration:
+                    args = var.get("constructor", "")
 
-                    if "default" in var:
-                        code('*$vid = ${{var["default"]}}; // Object default')
-                    elif "default" in vtype:
-                        comment = "Type %s default" % vtype.ident
-                        code('*$vid = ${{vtype["default"]}}; // $comment')
+                code('$expr($args);')
+                code('assert($vid != NULL);')
+
+            else:
+                # Normal Object
+                if "default" in var:
+                    code('$vid = ${{var["default"]}}; // Object default')
+                elif "default" in vtype:
+                    comment = "Type %s default" % vtype.ident
+                    code('$vid = ${{vtype["default"]}}; // $comment')
 
         # Set the prefetchers
         code()
@@ -667,25 +663,25 @@
 
         mq_ident = "NULL"
         for port in self.in_ports:
-            if port.code.find("mandatoryQueue_ptr") >= 0:
-                mq_ident = "m_mandatoryQueue_ptr"
+            if port.code.find("mandatoryQueue") >= 0:
+                mq_ident = "m_mandatoryQueue"
 
         memq_ident = "NULL"
         for port in self.in_ports:
-            if port.code.find("responseFromMemory_ptr") >= 0:
-                memq_ident = "m_responseFromMemory_ptr"
+            if port.code.find("responseFromMemory") >= 0:
+                memq_ident = "m_responseFromMemory"
 
         seq_ident = "NULL"
         for param in self.config_parameters:
             if param.ident == "sequencer":
                 assert(param.pointer)
-                seq_ident = "m_%s_ptr" % param.ident
+                seq_ident = "m_%s" % param.ident
 
         coal_ident = "NULL"
         for param in self.config_parameters:
             if param.ident == "coalescer":
                 assert(param.pointer)
-                coal_ident = "m_%s_ptr" % param.ident
+                coal_ident = "m_%s" % param.ident
 
         if seq_ident != "NULL":
             code('''
@@ -926,7 +922,7 @@
         for param in self.config_parameters:
             if param.type_ast.type.ident == "CacheMemory":
                 assert(param.pointer)
-                code('m_${{param.ident}}_ptr->recordCacheContents(cntrl, tr);')
+                code('m_${{param.ident}}->recordCacheContents(cntrl, tr);')
 
         code.dedent()
         code('''
@@ -1013,13 +1009,13 @@
         for var in self.objects:
             vtype = var.type
             if vtype.isBuffer:
-                vid = "m_%s_ptr" % var.ident
+                vid = "m_%s" % var.ident
                 code('num_functional_writes += $vid->functionalWrite(pkt);')
 
         for var in self.config_parameters:
             vtype = var.type_ast.type
             if vtype.isBuffer:
-                vid = "m_%s_ptr" % var.ident
+                vid = "m_%s" % var.ident
                 code('num_functional_writes += $vid->functionalWrite(pkt);')
 
         code('''
diff --git a/src/mem/slicc/symbols/Type.py b/src/mem/slicc/symbols/Type.py
--- a/src/mem/slicc/symbols/Type.py
+++ b/src/mem/slicc/symbols/Type.py
@@ -32,10 +32,10 @@
 from slicc.symbols.Var import Var
 
 class DataMember(Var):
-    def __init__(self, symtab, ident, location, type, code, pairs,
+    def __init__(self, symtab, ident, location, type, pointer, code, pairs,
                  machine, init_code):
         super(DataMember, self).__init__(symtab, ident, location, type,
-                                         code, pairs, machine)
+                                         pointer, code, pairs, machine)
         self.init_code = init_code
 
 class Enumeration(PairContainer):
@@ -123,11 +123,11 @@
         return "interface" in self
 
     # Return false on error
-    def addDataMember(self, ident, type, pairs, init_code):
+    def addDataMember(self, ident, type, pointer, pairs, init_code):
         if ident in self.data_members:
             return False
 
-        member = DataMember(self.symtab, ident, self.location, type,
+        member = DataMember(self.symtab, ident, self.location, type, pointer,
                             "m_%s" % ident, pairs, None, init_code)
 
         self.data_members[ident] = member
diff --git a/src/mem/slicc/symbols/Var.py b/src/mem/slicc/symbols/Var.py
--- a/src/mem/slicc/symbols/Var.py
+++ b/src/mem/slicc/symbols/Var.py
@@ -28,12 +28,13 @@
 from slicc.symbols.Symbol import Symbol
 
 class Var(Symbol):
-    def __init__(self, symtab, ident, location, type, code, pairs,
+    def __init__(self, symtab, ident, location, type, pointer, code, pairs,
                  machine=None):
         super(Var, self).__init__(symtab, ident, location, pairs)
 
         self.machine = machine
         self.type = type
+        self.pointer = pointer
         self.code = code
 
     def __repr__(self):