diff --git a/src/mem/protocol/GPU_RfO-TCCdir.sm b/src/mem/protocol/GPU_RfO-TCCdir.sm
--- a/src/mem/protocol/GPU_RfO-TCCdir.sm
+++ b/src/mem/protocol/GPU_RfO-TCCdir.sm
@@ -300,7 +300,7 @@
   void functionalRead(Addr addr, Packet *pkt) {
     TBE tbe := TBEs.lookup(addr);
     if(is_valid(tbe)) {
-      testAndRead(addr, tbe.DataBlk, pkt);
+      testAndRead(addr, tbe.DataBlk, pkt, block_size_bits);
     } else {
       functionalMemoryRead(pkt);
     }
@@ -312,7 +312,7 @@
     TBE tbe := TBEs.lookup(addr);
     if(is_valid(tbe)) {
       num_functional_writes := num_functional_writes +
-            testAndWrite(addr, tbe.DataBlk, pkt);
+            testAndWrite(addr, tbe.DataBlk, pkt, block_size_bits);
     }
 
     num_functional_writes := num_functional_writes + functionalMemoryWrite(pkt);
diff --git a/src/mem/protocol/GPU_RfO-TCP.sm b/src/mem/protocol/GPU_RfO-TCP.sm
--- a/src/mem/protocol/GPU_RfO-TCP.sm
+++ b/src/mem/protocol/GPU_RfO-TCP.sm
@@ -206,7 +206,7 @@
   void functionalRead(Addr addr, Packet *pkt) {
     TBE tbe := TBEs.lookup(addr);
     if(is_valid(tbe)) {
-      testAndRead(addr, tbe.DataBlk, pkt);
+      testAndRead(addr, tbe.DataBlk, pkt, block_size_bits);
     } else {
       functionalMemoryRead(pkt);
     }
@@ -218,7 +218,7 @@
     TBE tbe := TBEs.lookup(addr);
     if(is_valid(tbe)) {
       num_functional_writes := num_functional_writes +
-            testAndWrite(addr, tbe.DataBlk, pkt);
+            testAndWrite(addr, tbe.DataBlk, pkt, block_size_bits);
     }
 
     num_functional_writes := num_functional_writes + functionalMemoryWrite(pkt);
diff --git a/src/mem/protocol/GPU_VIPER-SQC.sm b/src/mem/protocol/GPU_VIPER-SQC.sm
--- a/src/mem/protocol/GPU_VIPER-SQC.sm
+++ b/src/mem/protocol/GPU_VIPER-SQC.sm
@@ -140,7 +140,7 @@
   void functionalRead(Addr addr, Packet *pkt) {
     TBE tbe := TBEs.lookup(addr);
     if(is_valid(tbe)) {
-      testAndRead(addr, tbe.DataBlk, pkt);
+      testAndRead(addr, tbe.DataBlk, pkt, block_size_bits);
     } else {
       functionalMemoryRead(pkt);
     }
@@ -152,7 +152,7 @@
     TBE tbe := TBEs.lookup(addr);
     if(is_valid(tbe)) {
       num_functional_writes := num_functional_writes +
-            testAndWrite(addr, tbe.DataBlk, pkt);
+            testAndWrite(addr, tbe.DataBlk, pkt, block_size_bits);
     }
 
     num_functional_writes := num_functional_writes +
diff --git a/src/mem/protocol/GPU_VIPER-TCC.sm b/src/mem/protocol/GPU_VIPER-TCC.sm
--- a/src/mem/protocol/GPU_VIPER-TCC.sm
+++ b/src/mem/protocol/GPU_VIPER-TCC.sm
@@ -164,7 +164,7 @@
   void functionalRead(Addr addr, Packet *pkt) {
     TBE tbe := TBEs.lookup(addr);
     if(is_valid(tbe)) {
-      testAndRead(addr, tbe.DataBlk, pkt);
+      testAndRead(addr, tbe.DataBlk, pkt, block_size_bits);
     } else {
       functionalMemoryRead(pkt);
     }
@@ -176,7 +176,7 @@
     TBE tbe := TBEs.lookup(addr);
     if(is_valid(tbe)) {
       num_functional_writes := num_functional_writes +
-            testAndWrite(addr, tbe.DataBlk, pkt);
+            testAndWrite(addr, tbe.DataBlk, pkt, block_size_bits);
     }
 
     num_functional_writes := num_functional_writes +
diff --git a/src/mem/protocol/GPU_VIPER-TCP.sm b/src/mem/protocol/GPU_VIPER-TCP.sm
--- a/src/mem/protocol/GPU_VIPER-TCP.sm
+++ b/src/mem/protocol/GPU_VIPER-TCP.sm
@@ -167,7 +167,7 @@
   void functionalRead(Addr addr, Packet *pkt) {
     TBE tbe := TBEs.lookup(addr);
     if(is_valid(tbe)) {
-      testAndRead(addr, tbe.DataBlk, pkt);
+      testAndRead(addr, tbe.DataBlk, pkt, block_size_bits);
     } else {
       functionalMemoryRead(pkt);
     }
@@ -179,7 +179,7 @@
     TBE tbe := TBEs.lookup(addr);
     if(is_valid(tbe)) {
       num_functional_writes := num_functional_writes +
-            testAndWrite(addr, tbe.DataBlk, pkt);
+            testAndWrite(addr, tbe.DataBlk, pkt, block_size_bits);
     }
 
     num_functional_writes := num_functional_writes +
diff --git a/src/mem/protocol/GPU_VIPER_Region-TCC.sm b/src/mem/protocol/GPU_VIPER_Region-TCC.sm
--- a/src/mem/protocol/GPU_VIPER_Region-TCC.sm
+++ b/src/mem/protocol/GPU_VIPER_Region-TCC.sm
@@ -175,7 +175,7 @@
   void functionalRead(Addr addr, Packet *pkt) {
     TBE tbe := TBEs.lookup(addr);
     if(is_valid(tbe)) {
-      testAndRead(addr, tbe.DataBlk, pkt);
+      testAndRead(addr, tbe.DataBlk, pkt, block_size_bits);
     } else {
       functionalMemoryRead(pkt);
     }
@@ -187,7 +187,7 @@
     TBE tbe := TBEs.lookup(addr);
     if(is_valid(tbe)) {
       num_functional_writes := num_functional_writes +
-            testAndWrite(addr, tbe.DataBlk, pkt);
+            testAndWrite(addr, tbe.DataBlk, pkt, block_size_bits);
     }
 
     num_functional_writes := num_functional_writes +
# Node ID dd80771f73b0825429217414ea8205aada9419d3
# Parent  6901103f7f04d788302cc64e62667c080420858c
diff --git a/src/mem/protocol/GPU_RfO-SQC.sm b/src/mem/protocol/GPU_RfO-SQC.sm
--- a/src/mem/protocol/GPU_RfO-SQC.sm
+++ b/src/mem/protocol/GPU_RfO-SQC.sm
@@ -177,7 +177,7 @@
   void functionalRead(Addr addr, Packet *pkt) {
     TBE tbe := TBEs.lookup(addr);
     if(is_valid(tbe)) {
-      testAndRead(addr, tbe.DataBlk, pkt);
+      testAndRead(addr, tbe.DataBlk, pkt, block_size_bits);
     } else {
       functionalMemoryRead(pkt);
     }
@@ -189,7 +189,7 @@
     TBE tbe := TBEs.lookup(addr);
     if(is_valid(tbe)) {
       num_functional_writes := num_functional_writes +
-            testAndWrite(addr, tbe.DataBlk, pkt);
+            testAndWrite(addr, tbe.DataBlk, pkt, block_size_bits);
     }
 
     num_functional_writes := num_functional_writes + functionalMemoryWrite(pkt);
diff --git a/src/mem/protocol/GPU_RfO-TCC.sm b/src/mem/protocol/GPU_RfO-TCC.sm
--- a/src/mem/protocol/GPU_RfO-TCC.sm
+++ b/src/mem/protocol/GPU_RfO-TCC.sm
@@ -215,7 +215,7 @@
   void functionalRead(Addr addr, Packet *pkt) {
     TBE tbe := TBEs.lookup(addr);
     if(is_valid(tbe)) {
-      testAndRead(addr, tbe.DataBlk, pkt);
+      testAndRead(addr, tbe.DataBlk, pkt, block_size_bits);
     } else {
       functionalMemoryRead(pkt);
     }
@@ -227,7 +227,7 @@
     TBE tbe := TBEs.lookup(addr);
     if(is_valid(tbe)) {
       num_functional_writes := num_functional_writes +
-            testAndWrite(addr, tbe.DataBlk, pkt);
+            testAndWrite(addr, tbe.DataBlk, pkt, block_size_bits);
     }
 
     num_functional_writes := num_functional_writes + functionalMemoryWrite(pkt);
diff --git a/src/mem/protocol/MESI_Three_Level-L0cache.sm b/src/mem/protocol/MESI_Three_Level-L0cache.sm
--- a/src/mem/protocol/MESI_Three_Level-L0cache.sm
+++ b/src/mem/protocol/MESI_Three_Level-L0cache.sm
@@ -210,9 +210,9 @@
   void functionalRead(Addr addr, Packet *pkt) {
     TBE tbe := TBEs[addr];
     if(is_valid(tbe)) {
-      testAndRead(addr, tbe.DataBlk, pkt);
+      testAndRead(addr, tbe.DataBlk, pkt, block_size_bits);
     } else {
-      testAndRead(addr, getCacheEntry(addr).DataBlk, pkt);
+      testAndRead(addr, getCacheEntry(addr).DataBlk, pkt, block_size_bits);
     }
   }
 
@@ -222,12 +222,12 @@
     TBE tbe := TBEs[addr];
     if(is_valid(tbe)) {
       num_functional_writes := num_functional_writes +
-        testAndWrite(addr, tbe.DataBlk, pkt);
+        testAndWrite(addr, tbe.DataBlk, pkt, block_size_bits);
       return num_functional_writes;
     }
 
     num_functional_writes := num_functional_writes +
-        testAndWrite(addr, getCacheEntry(addr).DataBlk, pkt);
+        testAndWrite(addr, getCacheEntry(addr).DataBlk, pkt, block_size_bits);
     return num_functional_writes;
   }
 
diff --git a/src/mem/protocol/MESI_Three_Level-L1cache.sm b/src/mem/protocol/MESI_Three_Level-L1cache.sm
--- a/src/mem/protocol/MESI_Three_Level-L1cache.sm
+++ b/src/mem/protocol/MESI_Three_Level-L1cache.sm
@@ -207,9 +207,9 @@
   void functionalRead(Addr addr, Packet *pkt) {
     TBE tbe := TBEs[addr];
     if(is_valid(tbe)) {
-      testAndRead(addr, tbe.DataBlk, pkt);
+      testAndRead(addr, tbe.DataBlk, pkt, block_size_bits);
     } else {
-      testAndRead(addr, getCacheEntry(addr).DataBlk, pkt);
+      testAndRead(addr, getCacheEntry(addr).DataBlk, pkt, block_size_bits);
     }
   }
 
@@ -219,12 +219,12 @@
     TBE tbe := TBEs[addr];
     if(is_valid(tbe)) {
       num_functional_writes := num_functional_writes +
-        testAndWrite(addr, tbe.DataBlk, pkt);
+        testAndWrite(addr, tbe.DataBlk, pkt, block_size_bits);
       return num_functional_writes;
     }
 
     num_functional_writes := num_functional_writes +
-        testAndWrite(addr, getCacheEntry(addr).DataBlk, pkt);
+        testAndWrite(addr, getCacheEntry(addr).DataBlk, pkt, block_size_bits);
     return num_functional_writes;
   }
 
diff --git a/src/mem/protocol/MESI_Three_Level-msg.sm b/src/mem/protocol/MESI_Three_Level-msg.sm
--- a/src/mem/protocol/MESI_Three_Level-msg.sm
+++ b/src/mem/protocol/MESI_Three_Level-msg.sm
@@ -62,7 +62,7 @@
   bool functionalRead(Packet *pkt, uint32_t block_size_bits) {
     // Only PUTX messages contains the data block
     if (Class == CoherenceClass:PUTX) {
-        return testAndRead(addr, DataBlk, pkt);
+        return testAndRead(addr, DataBlk, pkt, block_size_bits);
     }
 
     return false;
@@ -71,6 +71,6 @@
   bool functionalWrite(Packet *pkt, uint32_t block_size_bits) {
     // No check on message type required since the protocol should
     // read data from those messages that contain the block
-    return testAndWrite(addr, DataBlk, pkt);
+    return testAndWrite(addr, DataBlk, pkt, block_size_bits);
   }
 }
diff --git a/src/mem/protocol/MESI_Two_Level-L1cache.sm b/src/mem/protocol/MESI_Two_Level-L1cache.sm
--- a/src/mem/protocol/MESI_Two_Level-L1cache.sm
+++ b/src/mem/protocol/MESI_Two_Level-L1cache.sm
@@ -230,9 +230,9 @@
   void functionalRead(Addr addr, Packet *pkt) {
     TBE tbe := TBEs[addr];
     if(is_valid(tbe)) {
-      testAndRead(addr, tbe.DataBlk, pkt);
+      testAndRead(addr, tbe.DataBlk, pkt, block_size_bits);
     } else {
-      testAndRead(addr, getCacheEntry(addr).DataBlk, pkt);
+      testAndRead(addr, getCacheEntry(addr).DataBlk, pkt, block_size_bits);
     }
   }
 
@@ -242,12 +242,12 @@
     TBE tbe := TBEs[addr];
     if(is_valid(tbe)) {
       num_functional_writes := num_functional_writes +
-        testAndWrite(addr, tbe.DataBlk, pkt);
+        testAndWrite(addr, tbe.DataBlk, pkt, block_size_bits);
       return num_functional_writes;
     }
 
     num_functional_writes := num_functional_writes +
-        testAndWrite(addr, getCacheEntry(addr).DataBlk, pkt);
+        testAndWrite(addr, getCacheEntry(addr).DataBlk, pkt, block_size_bits);
     return num_functional_writes;
   }
 
diff --git a/src/mem/protocol/MESI_Two_Level-L2cache.sm b/src/mem/protocol/MESI_Two_Level-L2cache.sm
--- a/src/mem/protocol/MESI_Two_Level-L2cache.sm
+++ b/src/mem/protocol/MESI_Two_Level-L2cache.sm
@@ -219,9 +219,9 @@
   void functionalRead(Addr addr, Packet *pkt) {
     TBE tbe := TBEs[addr];
     if(is_valid(tbe)) {
-      testAndRead(addr, tbe.DataBlk, pkt);
+      testAndRead(addr, tbe.DataBlk, pkt, block_size_bits);
     } else {
-      testAndRead(addr, getCacheEntry(addr).DataBlk, pkt);
+      testAndRead(addr, getCacheEntry(addr).DataBlk, pkt, block_size_bits);
     }
   }
 
@@ -231,12 +231,12 @@
     TBE tbe := TBEs[addr];
     if(is_valid(tbe)) {
       num_functional_writes := num_functional_writes +
-        testAndWrite(addr, tbe.DataBlk, pkt);
+        testAndWrite(addr, tbe.DataBlk, pkt, block_size_bits);
       return num_functional_writes;
     }
 
     num_functional_writes := num_functional_writes +
-        testAndWrite(addr, getCacheEntry(addr).DataBlk, pkt);
+        testAndWrite(addr, getCacheEntry(addr).DataBlk, pkt, block_size_bits);
     return num_functional_writes;
   }
 
diff --git a/src/mem/protocol/MOESI_CMP_token-L1cache.sm b/src/mem/protocol/MOESI_CMP_token-L1cache.sm
--- a/src/mem/protocol/MOESI_CMP_token-L1cache.sm
+++ b/src/mem/protocol/MOESI_CMP_token-L1cache.sm
@@ -241,13 +241,13 @@
   }
 
   void functionalRead(Addr addr, Packet *pkt) {
-    testAndRead(addr, getCacheEntry(addr).DataBlk, pkt);
+    testAndRead(addr, getCacheEntry(addr).DataBlk, pkt, block_size_bits);
   }
 
   int functionalWrite(Addr addr, Packet *pkt) {
     int num_functional_writes := 0;
     num_functional_writes := num_functional_writes +
-        testAndWrite(addr, getCacheEntry(addr).DataBlk, pkt);
+        testAndWrite(addr, getCacheEntry(addr).DataBlk, pkt, block_size_bits);
     return num_functional_writes;
   }
 
diff --git a/src/mem/protocol/MOESI_CMP_token-L2cache.sm b/src/mem/protocol/MOESI_CMP_token-L2cache.sm
--- a/src/mem/protocol/MOESI_CMP_token-L2cache.sm
+++ b/src/mem/protocol/MOESI_CMP_token-L2cache.sm
@@ -164,13 +164,13 @@
   }
 
   void functionalRead(Addr addr, Packet *pkt) {
-    testAndRead(addr, getCacheEntry(addr).DataBlk, pkt);
+    testAndRead(addr, getCacheEntry(addr).DataBlk, pkt, block_size_bits);
   }
 
   int functionalWrite(Addr addr, Packet *pkt) {
     int num_functional_writes := 0;
     num_functional_writes := num_functional_writes +
-        testAndWrite(addr, getCacheEntry(addr).DataBlk, pkt);
+        testAndWrite(addr, getCacheEntry(addr).DataBlk, pkt, block_size_bits);
     return num_functional_writes;
   }
 
diff --git a/src/mem/protocol/MOESI_CMP_token-dir.sm b/src/mem/protocol/MOESI_CMP_token-dir.sm
--- a/src/mem/protocol/MOESI_CMP_token-dir.sm
+++ b/src/mem/protocol/MOESI_CMP_token-dir.sm
@@ -250,7 +250,7 @@
   void functionalRead(Addr addr, Packet *pkt) {
     TBE tbe := TBEs[addr];
     if(is_valid(tbe)) {
-      testAndRead(addr, tbe.DataBlk, pkt);
+      testAndRead(addr, tbe.DataBlk, pkt, block_size_bits);
     } else {
       functionalMemoryRead(pkt);
     }
@@ -262,7 +262,7 @@
     TBE tbe := TBEs[addr];
     if(is_valid(tbe)) {
       num_functional_writes := num_functional_writes +
-            testAndWrite(addr, tbe.DataBlk, pkt);
+            testAndWrite(addr, tbe.DataBlk, pkt, block_size_bits);
     }
 
     num_functional_writes := num_functional_writes + functionalMemoryWrite(pkt);
diff --git a/src/mem/protocol/MOESI_CMP_token-msg.sm b/src/mem/protocol/MOESI_CMP_token-msg.sm
--- a/src/mem/protocol/MOESI_CMP_token-msg.sm
+++ b/src/mem/protocol/MOESI_CMP_token-msg.sm
@@ -113,12 +113,12 @@
 
   bool functionalRead(Packet *pkt, uint32_t block_size_bits) {
     // No check being carried out on the message type. Would be added later.
-    return testAndRead(addr, DataBlk, pkt);
+    return testAndRead(addr, DataBlk, pkt, block_size_bits);
   }
 
   bool functionalWrite(Packet *pkt, uint32_t block_size_bits) {
     // No check required since all messages are written.
-    return testAndWrite(addr, DataBlk, pkt);
+    return testAndWrite(addr, DataBlk, pkt, block_size_bits);
   }
 }
 
@@ -149,7 +149,7 @@
   }
 
   bool functionalWrite(Packet *pkt, uint32_t block_size_bits) {
-    return testAndWrite(LineAddress, DataBlk, pkt);
+    return testAndWrite(LineAddress, DataBlk, pkt, block_size_bits);
   }
 }
 
@@ -166,6 +166,6 @@
   }
 
   bool functionalWrite(Packet *pkt, uint32_t block_size_bits) {
-    return testAndWrite(LineAddress, DataBlk, pkt);
+    return testAndWrite(LineAddress, DataBlk, pkt, block_size_bits);
   }
 }
diff --git a/src/mem/protocol/MOESI_hammer-cache.sm b/src/mem/protocol/MOESI_hammer-cache.sm
--- a/src/mem/protocol/MOESI_hammer-cache.sm
+++ b/src/mem/protocol/MOESI_hammer-cache.sm
@@ -207,11 +207,11 @@
   void functionalRead(Addr addr, Packet *pkt) {
     Entry cache_entry := getCacheEntry(addr);
     if(is_valid(cache_entry)) {
-      testAndRead(addr, cache_entry.DataBlk, pkt);
+      testAndRead(addr, cache_entry.DataBlk, pkt, block_size_bits);
     } else {
       TBE tbe := TBEs[addr];
       if(is_valid(tbe)) {
-        testAndRead(addr, tbe.DataBlk, pkt);
+        testAndRead(addr, tbe.DataBlk, pkt, block_size_bits);
       } else {
         error("Missing data block");
       }
@@ -224,13 +224,13 @@
     Entry cache_entry := getCacheEntry(addr);
     if(is_valid(cache_entry)) {
       num_functional_writes := num_functional_writes +
-        testAndWrite(addr, cache_entry.DataBlk, pkt);
+        testAndWrite(addr, cache_entry.DataBlk, pkt, block_size_bits);
       return num_functional_writes;
     }
 
     TBE tbe := TBEs[addr];
     num_functional_writes := num_functional_writes +
-      testAndWrite(addr, tbe.DataBlk, pkt);
+      testAndWrite(addr, tbe.DataBlk, pkt, block_size_bits);
     return num_functional_writes;
   }
 
diff --git a/src/mem/protocol/MOESI_hammer-dir.sm b/src/mem/protocol/MOESI_hammer-dir.sm
--- a/src/mem/protocol/MOESI_hammer-dir.sm
+++ b/src/mem/protocol/MOESI_hammer-dir.sm
@@ -273,7 +273,7 @@
   void functionalRead(Addr addr, Packet *pkt) {
     TBE tbe := TBEs[addr];
     if(is_valid(tbe)) {
-      testAndRead(addr, tbe.DataBlk, pkt);
+      testAndRead(addr, tbe.DataBlk, pkt, block_size_bits);
     } else {
       functionalMemoryRead(pkt);
     }
@@ -285,7 +285,7 @@
     TBE tbe := TBEs[addr];
     if(is_valid(tbe)) {
       num_functional_writes := num_functional_writes +
-        testAndWrite(addr, tbe.DataBlk, pkt);
+        testAndWrite(addr, tbe.DataBlk, pkt, block_size_bits);
     }
 
     num_functional_writes := num_functional_writes + functionalMemoryWrite(pkt);
diff --git a/src/mem/protocol/MOESI_hammer-msg.sm b/src/mem/protocol/MOESI_hammer-msg.sm
--- a/src/mem/protocol/MOESI_hammer-msg.sm
+++ b/src/mem/protocol/MOESI_hammer-msg.sm
@@ -138,7 +138,7 @@
         Type == CoherenceResponseType:DATA_EXCLUSIVE ||
         Type == CoherenceResponseType:WB_DIRTY ||
         Type == CoherenceResponseType:WB_EXCLUSIVE_DIRTY) {
-        return testAndRead(addr, DataBlk, pkt);
+        return testAndRead(addr, DataBlk, pkt, block_size_bits);
     }
 
     return false;
@@ -148,7 +148,7 @@
     // Message type does not matter since all messages are written.
     // If a protocol reads data from a packet that is not supposed
     // to hold the data, then the fault lies with the protocol.
-    return testAndWrite(addr, DataBlk, pkt);
+    return testAndWrite(addr, DataBlk, pkt, block_size_bits);
   }
 }
 
@@ -175,11 +175,11 @@
   MessageSizeType MessageSize, desc="size category of the message";
 
   bool functionalRead(Packet *pkt, uint32_t block_size_bits) {
-    return testAndRead(LineAddress, DataBlk, pkt);
+    return testAndRead(LineAddress, DataBlk, pkt, block_size_bits);
   }
 
   bool functionalWrite(Packet *pkt, uint32_t block_size_bits) {
-    return testAndWrite(LineAddress, DataBlk, pkt);
+    return testAndWrite(LineAddress, DataBlk, pkt, block_size_bits);
   }
 }
 
@@ -192,10 +192,10 @@
   MessageSizeType MessageSize, desc="size category of the message";
 
   bool functionalRead(Packet *pkt, uint32_t block_size_bits) {
-    return testAndRead(LineAddress, DataBlk, pkt);
+    return testAndRead(LineAddress, DataBlk, pkt, block_size_bits);
   }
 
   bool functionalWrite(Packet *pkt, uint32_t block_size_bits) {
-    return testAndWrite(LineAddress, DataBlk, pkt);
+    return testAndWrite(LineAddress, DataBlk, pkt, block_size_bits);
   }
 }
diff --git a/src/mem/protocol/RubySlicc_Exports.sm b/src/mem/protocol/RubySlicc_Exports.sm
--- a/src/mem/protocol/RubySlicc_Exports.sm
+++ b/src/mem/protocol/RubySlicc_Exports.sm
@@ -56,9 +56,12 @@
   void atomicPartial(DataBlock, WriteMask);
 }
 
-bool testAndRead(Addr addr, DataBlock datablk, Packet *pkt);
-bool testAndReadMask(Addr addr, DataBlock datablk, WriteMask mask, Packet *pkt);
-bool testAndWrite(Addr addr, DataBlock datablk, Packet *pkt);
+bool testAndRead(Addr addr, DataBlock datablk, Packet *pkt,
+                 uint32_t block_size_bits);
+bool testAndReadMask(Addr addr, DataBlock datablk, WriteMask mask, Packet *pkt,
+                     uint32_t block_size_bits);
+bool testAndWrite(Addr addr, DataBlock datablk, Packet *pkt,
+                  uint32_t block_size_bits);
 
 // AccessPermission
 // The following five states define the access permission of all memory blocks.
@@ -290,11 +293,11 @@
   MessageSizeType MessageSize;
 
   bool functionalRead(Packet *pkt, uint32_t block_size_bits) {
-    return testAndRead(PhysicalAddress, DataBlk, pkt);
+    return testAndRead(PhysicalAddress, DataBlk, pkt, block_size_bits);
   }
 
   bool functionalWrite(Packet *pkt, uint32_t block_size_bits) {
-    return testAndWrite(PhysicalAddress, DataBlk, pkt);
+    return testAndWrite(PhysicalAddress, DataBlk, pkt, block_size_bits);
   }
 }
 
diff --git a/src/mem/protocol/RubySlicc_MemControl.sm b/src/mem/protocol/RubySlicc_MemControl.sm
--- a/src/mem/protocol/RubySlicc_MemControl.sm
+++ b/src/mem/protocol/RubySlicc_MemControl.sm
@@ -63,10 +63,10 @@
   int Acks,                     desc="How many acks to expect";
 
   bool functionalRead(Packet *pkt, uint32_t block_size_bits) {
-    return testAndRead(addr, DataBlk, pkt);
+    return testAndRead(addr, DataBlk, pkt, block_size_bits);
   }
 
   bool functionalWrite(Packet *pkt, uint32_t block_size_bits) {
-    return testAndWrite(addr, DataBlk, pkt);
+    return testAndWrite(addr, DataBlk, pkt, block_size_bits);
   }
 }
diff --git a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
--- a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
+++ b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
@@ -98,7 +98,7 @@
  * state, including empty.
  */
 inline bool
-testAndRead(Addr addr, DataBlock& blk, Packet *pkt)
+testAndRead(Addr addr, DataBlock& blk, Packet *pkt, uint32_t block_size_bits)
 {
     Addr pktLineAddr = makeLineAddress(pkt->getAddr());
     Addr lineAddr = makeLineAddress(addr);
@@ -124,7 +124,8 @@
  * otherwise false is returned.
  */
 inline bool
-testAndReadMask(Addr addr, DataBlock& blk, WriteMask& mask, Packet *pkt)
+testAndReadMask(Addr addr, DataBlock& blk, WriteMask& mask, Packet *pkt,
+                uint32_t block_size_bits)
 {
     Addr pktLineAddr = makeLineAddress(pkt->getAddr());
     Addr lineAddr = makeLineAddress(addr);
@@ -153,7 +154,8 @@
  * returned if the data block was written, otherwise false is returned.
  */
 inline bool
-testAndWrite(Addr addr, DataBlock& blk, Packet *pkt)
+testAndWrite(Addr addr, DataBlock& blk, Packet *pkt,
+             uint32_t block_size_bits)
 {
     Addr pktLineAddr = makeLineAddress(pkt->getAddr());
     Addr lineAddr = makeLineAddress(addr);
diff --git a/src/mem/protocol/MOESI_AMD_Base-dir.sm b/src/mem/protocol/MOESI_AMD_Base-dir.sm
--- a/src/mem/protocol/MOESI_AMD_Base-dir.sm
+++ b/src/mem/protocol/MOESI_AMD_Base-dir.sm
@@ -203,7 +203,7 @@
   void functionalRead(Addr addr, Packet *pkt) {
     TBE tbe := TBEs.lookup(addr);
     if(is_valid(tbe)) {
-      testAndRead(addr, tbe.DataBlk, pkt);
+      testAndRead(addr, tbe.DataBlk, pkt, block_size_bits);
     } else {
       functionalMemoryRead(pkt);
     }
@@ -215,7 +215,7 @@
     TBE tbe := TBEs.lookup(addr);
     if(is_valid(tbe)) {
       num_functional_writes := num_functional_writes +
-            testAndWrite(addr, tbe.DataBlk, pkt);
+            testAndWrite(addr, tbe.DataBlk, pkt, block_size_bits);
     }
 
     num_functional_writes := num_functional_writes
diff --git a/src/mem/protocol/MOESI_AMD_Base-msg.sm b/src/mem/protocol/MOESI_AMD_Base-msg.sm
--- a/src/mem/protocol/MOESI_AMD_Base-msg.sm
+++ b/src/mem/protocol/MOESI_AMD_Base-msg.sm
@@ -145,7 +145,7 @@
   bool functionalRead(Packet *pkt, uint32_t block_size_bits) {
     // Only PUTX messages contains the data block
     if (Type == CoherenceRequestType:VicDirty) {
-        return testAndRead(addr, DataBlk, pkt);
+        return testAndRead(addr, DataBlk, pkt, block_size_bits);
     }
 
     return false;
@@ -154,7 +154,7 @@
   bool functionalWrite(Packet *pkt, uint32_t block_size_bits) {
     // No check on message type required since the protocol should
     // read data from those messages that contain the block
-    return testAndWrite(addr, DataBlk, pkt);
+    return testAndWrite(addr, DataBlk, pkt, block_size_bits);
   }
 }
 
@@ -255,7 +255,7 @@
     // Only PUTX messages contains the data block
     if (Type == CoherenceResponseType:CPUData ||
         Type == CoherenceResponseType:MemData) {
-        return testAndRead(addr, DataBlk, pkt);
+        return testAndRead(addr, DataBlk, pkt, block_size_bits);
     }
 
     return false;
@@ -264,7 +264,7 @@
   bool functionalWrite(Packet *pkt, uint32_t block_size_bits) {
     // No check on message type required since the protocol should
     // read data from those messages that contain the block
-    return testAndWrite(addr, DataBlk, pkt);
+    return testAndWrite(addr, DataBlk, pkt, block_size_bits);
   }
 }
 
diff --git a/src/mem/protocol/MOESI_AMD_Base-probeFilter.sm b/src/mem/protocol/MOESI_AMD_Base-probeFilter.sm
--- a/src/mem/protocol/MOESI_AMD_Base-probeFilter.sm
+++ b/src/mem/protocol/MOESI_AMD_Base-probeFilter.sm
@@ -242,7 +242,7 @@
   void functionalRead(Addr addr, Packet *pkt) {
     TBE tbe := TBEs.lookup(addr);
     if(is_valid(tbe)) {
-      testAndRead(addr, tbe.DataBlk, pkt);
+      testAndRead(addr, tbe.DataBlk, pkt, block_size_bits);
     } else {
       functionalMemoryRead(pkt);
     }
@@ -254,7 +254,7 @@
     TBE tbe := TBEs.lookup(addr);
     if(is_valid(tbe)) {
       num_functional_writes := num_functional_writes +
-            testAndWrite(addr, tbe.DataBlk, pkt);
+            testAndWrite(addr, tbe.DataBlk, pkt, block_size_bits);
     }
 
     num_functional_writes := num_functional_writes +
diff --git a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
--- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
@@ -219,11 +219,11 @@
   void functionalRead(Addr addr, Packet *pkt) {
     Entry cache_entry := getCacheEntry(addr);
     if(is_valid(cache_entry)) {
-      testAndRead(addr, cache_entry.DataBlk, pkt);
+      testAndRead(addr, cache_entry.DataBlk, pkt, block_size_bits);
     } else {
       TBE tbe := TBEs[addr];
       if(is_valid(tbe)) {
-        testAndRead(addr, tbe.DataBlk, pkt);
+        testAndRead(addr, tbe.DataBlk, pkt, block_size_bits);
       } else {
         error("Data block missing!");
       }
@@ -236,13 +236,13 @@
     Entry cache_entry := getCacheEntry(addr);
     if(is_valid(cache_entry)) {
       num_functional_writes := num_functional_writes +
-        testAndWrite(addr, cache_entry.DataBlk, pkt);
+        testAndWrite(addr, cache_entry.DataBlk, pkt, block_size_bits);
       return num_functional_writes;
     }
 
     TBE tbe := TBEs[addr];
     num_functional_writes := num_functional_writes +
-        testAndWrite(addr, tbe.DataBlk, pkt);
+        testAndWrite(addr, tbe.DataBlk, pkt, block_size_bits);
     return num_functional_writes;
   }
 
diff --git a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
--- a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
@@ -548,9 +548,9 @@
   void functionalRead(Addr addr, Packet *pkt) {
     TBE tbe := TBEs[addr];
     if(is_valid(tbe)) {
-      testAndRead(addr, tbe.DataBlk, pkt);
+      testAndRead(addr, tbe.DataBlk, pkt, block_size_bits);
     } else {
-      testAndRead(addr, getCacheEntry(addr).DataBlk, pkt);
+      testAndRead(addr, getCacheEntry(addr).DataBlk, pkt, block_size_bits);
     }
   }
 
@@ -560,12 +560,12 @@
     TBE tbe := TBEs[addr];
     if(is_valid(tbe)) {
       num_functional_writes := num_functional_writes +
-        testAndWrite(addr, tbe.DataBlk, pkt);
+        testAndWrite(addr, tbe.DataBlk, pkt, block_size_bits);
       return num_functional_writes;
     }
 
     num_functional_writes := num_functional_writes +
-        testAndWrite(addr, getCacheEntry(addr).DataBlk, pkt);
+        testAndWrite(addr, getCacheEntry(addr).DataBlk, pkt, block_size_bits);
     return num_functional_writes;
   }
 
diff --git a/src/mem/protocol/MOESI_CMP_directory-msg.sm b/src/mem/protocol/MOESI_CMP_directory-msg.sm
--- a/src/mem/protocol/MOESI_CMP_directory-msg.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-msg.sm
@@ -101,14 +101,14 @@
     // Read only those messages that contain the data
     if (Type == CoherenceRequestType:DMA_READ ||
         Type == CoherenceRequestType:DMA_WRITE) {
-        return testAndRead(addr, DataBlk, pkt);
+        return testAndRead(addr, DataBlk, pkt, block_size_bits);
     }
     return false;
   }
 
   bool functionalWrite(Packet *pkt, uint32_t block_size_bits) {
     // No check required since all messages are written
-    return testAndWrite(addr, DataBlk, pkt);
+    return testAndWrite(addr, DataBlk, pkt, block_size_bits);
   }
 }
 
@@ -130,13 +130,13 @@
         Type == CoherenceResponseType:DATA_EXCLUSIVE ||
         Type == CoherenceResponseType:WRITEBACK_CLEAN_DATA ||
         Type == CoherenceResponseType:WRITEBACK_DIRTY_DATA) {
-        return testAndRead(addr, DataBlk, pkt);
+        return testAndRead(addr, DataBlk, pkt, block_size_bits);
     }
     return false;
   }
 
   bool functionalWrite(Packet *pkt, uint32_t block_size_bits) {
     // No check required since all messages are written
-    return testAndWrite(addr, DataBlk, pkt);
+    return testAndWrite(addr, DataBlk, pkt, block_size_bits);
   }
 }
diff --git a/src/mem/protocol/MESI_Two_Level-dir.sm b/src/mem/protocol/MESI_Two_Level-dir.sm
--- a/src/mem/protocol/MESI_Two_Level-dir.sm
+++ b/src/mem/protocol/MESI_Two_Level-dir.sm
@@ -155,7 +155,7 @@
   void functionalRead(Addr addr, Packet *pkt) {
     TBE tbe := TBEs[addr];
     if(is_valid(tbe)) {
-      testAndRead(addr, tbe.DataBlk, pkt);
+      testAndRead(addr, tbe.DataBlk, pkt, block_size_bits);
     } else {
       functionalMemoryRead(pkt);
     }
@@ -167,7 +167,7 @@
     TBE tbe := TBEs[addr];
     if(is_valid(tbe)) {
       num_functional_writes := num_functional_writes +
-        testAndWrite(addr, tbe.DataBlk, pkt);
+        testAndWrite(addr, tbe.DataBlk, pkt, block_size_bits);
     }
 
     num_functional_writes := num_functional_writes + functionalMemoryWrite(pkt);
diff --git a/src/mem/protocol/MESI_Two_Level-msg.sm b/src/mem/protocol/MESI_Two_Level-msg.sm
--- a/src/mem/protocol/MESI_Two_Level-msg.sm
+++ b/src/mem/protocol/MESI_Two_Level-msg.sm
@@ -72,7 +72,7 @@
   bool functionalRead(Packet *pkt, uint32_t block_size_bits) {
     // Only PUTX messages contains the data block
     if (Type == CoherenceRequestType:PUTX) {
-        return testAndRead(addr, DataBlk, pkt);
+        return testAndRead(addr, DataBlk, pkt, block_size_bits);
     }
 
     return false;
@@ -81,7 +81,7 @@
   bool functionalWrite(Packet *pkt, uint32_t block_size_bits) {
     // No check on message type required since the protocol should
     // read data from those messages that contain the block
-    return testAndWrite(addr, DataBlk, pkt);
+    return testAndWrite(addr, DataBlk, pkt, block_size_bits);
   }
 }
 
@@ -102,7 +102,7 @@
         Type == CoherenceResponseType:DATA_EXCLUSIVE ||
         Type == CoherenceResponseType:MEMORY_DATA) {
 
-        return testAndRead(addr, DataBlk, pkt);
+        return testAndRead(addr, DataBlk, pkt, block_size_bits);
     }
 
     return false;
@@ -111,6 +111,6 @@
   bool functionalWrite(Packet *pkt, uint32_t block_size_bits) {
     // No check on message type required since the protocol should
     // read data from those messages that contain the block
-    return testAndWrite(addr, DataBlk, pkt);
+    return testAndWrite(addr, DataBlk, pkt, block_size_bits);
   }
 }
diff --git a/src/mem/protocol/MI_example-cache.sm b/src/mem/protocol/MI_example-cache.sm
--- a/src/mem/protocol/MI_example-cache.sm
+++ b/src/mem/protocol/MI_example-cache.sm
@@ -175,9 +175,9 @@
   void functionalRead(Addr addr, Packet *pkt) {
     TBE tbe := TBEs[addr];
     if(is_valid(tbe)) {
-      testAndRead(addr, tbe.DataBlk, pkt);
+      testAndRead(addr, tbe.DataBlk, pkt, block_size_bits);
     } else {
-      testAndRead(addr, getCacheEntry(addr).DataBlk, pkt);
+      testAndRead(addr, getCacheEntry(addr).DataBlk, pkt, block_size_bits);
     }
   }
 
@@ -187,12 +187,12 @@
     TBE tbe := TBEs[addr];
     if(is_valid(tbe)) {
       num_functional_writes := num_functional_writes +
-        testAndWrite(addr, tbe.DataBlk, pkt);
+        testAndWrite(addr, tbe.DataBlk, pkt, block_size_bits);
       return num_functional_writes;
     }
 
     num_functional_writes := num_functional_writes +
-        testAndWrite(addr, getCacheEntry(addr).DataBlk, pkt);
+        testAndWrite(addr, getCacheEntry(addr).DataBlk, pkt, block_size_bits);
     return num_functional_writes;
   }
 
diff --git a/src/mem/protocol/MI_example-dir.sm b/src/mem/protocol/MI_example-dir.sm
--- a/src/mem/protocol/MI_example-dir.sm
+++ b/src/mem/protocol/MI_example-dir.sm
@@ -180,7 +180,7 @@
   void functionalRead(Addr addr, Packet *pkt) {
     TBE tbe := TBEs[addr];
     if(is_valid(tbe)) {
-      testAndRead(addr, tbe.DataBlk, pkt);
+      testAndRead(addr, tbe.DataBlk, pkt, block_size_bits);
     } else {
       functionalMemoryRead(pkt);
     }
@@ -192,7 +192,7 @@
     TBE tbe := TBEs[addr];
     if(is_valid(tbe)) {
       num_functional_writes := num_functional_writes +
-            testAndWrite(addr, tbe.DataBlk, pkt);
+            testAndWrite(addr, tbe.DataBlk, pkt, block_size_bits);
     }
 
     num_functional_writes := num_functional_writes + functionalMemoryWrite(pkt);
diff --git a/src/mem/protocol/MI_example-msg.sm b/src/mem/protocol/MI_example-msg.sm
--- a/src/mem/protocol/MI_example-msg.sm
+++ b/src/mem/protocol/MI_example-msg.sm
@@ -61,7 +61,7 @@
   bool functionalRead(Packet *pkt, uint32_t block_size_bits) {
     // Valid data block is only present in PUTX messages
     if (Type == CoherenceRequestType:PUTX) {
-        return testAndRead(addr, DataBlk, pkt);
+        return testAndRead(addr, DataBlk, pkt, block_size_bits);
     }
     return false;
   }
@@ -69,7 +69,7 @@
   bool functionalWrite(Packet *pkt, uint32_t block_size_bits) {
     // No check on message type required since the protocol should read
     // data block from only those messages that contain valid data
-    return testAndWrite(addr, DataBlk, pkt);
+    return testAndWrite(addr, DataBlk, pkt, block_size_bits);
   }
 }
 
@@ -86,13 +86,13 @@
   bool functionalRead(Packet *pkt, uint32_t block_size_bits) {
     // A check on message type should appear here so that only those
     // messages that contain data
-    return testAndRead(addr, DataBlk, pkt);
+    return testAndRead(addr, DataBlk, pkt, block_size_bits);
   }
 
   bool functionalWrite(Packet *pkt, uint32_t block_size_bits) {
     // No check on message type required since the protocol should read
     // data block from only those messages that contain valid data
-    return testAndWrite(addr, DataBlk, pkt);
+    return testAndWrite(addr, DataBlk, pkt, block_size_bits);
   }
 }
 
@@ -119,11 +119,11 @@
   MessageSizeType MessageSize, desc="size category of the message";
 
   bool functionalRead(Packet *pkt, uint32_t block_size_bits) {
-    return testAndRead(LineAddress, DataBlk, pkt);
+    return testAndRead(LineAddress, DataBlk, pkt, block_size_bits);
   }
 
   bool functionalWrite(Packet *pkt, uint32_t block_size_bits) {
-    return testAndWrite(LineAddress, DataBlk, pkt);
+    return testAndWrite(LineAddress, DataBlk, pkt, block_size_bits);
   }
 }
 
@@ -136,10 +136,10 @@
   MessageSizeType MessageSize, desc="size category of the message";
 
   bool functionalRead(Packet *pkt, uint32_t block_size_bits) {
-    return testAndRead(LineAddress, DataBlk, pkt);
+    return testAndRead(LineAddress, DataBlk, pkt, block_size_bits);
   }
 
   bool functionalWrite(Packet *pkt, uint32_t block_size_bits) {
-    return testAndWrite(LineAddress, DataBlk, pkt);
+    return testAndWrite(LineAddress, DataBlk, pkt, block_size_bits);
   }
 }
diff --git a/src/mem/protocol/MOESI_AMD_Base-CorePair.sm b/src/mem/protocol/MOESI_AMD_Base-CorePair.sm
--- a/src/mem/protocol/MOESI_AMD_Base-CorePair.sm
+++ b/src/mem/protocol/MOESI_AMD_Base-CorePair.sm
@@ -323,7 +323,7 @@
   void functionalRead(Addr addr, Packet *pkt) {
     TBE tbe := TBEs.lookup(addr);
     if(is_valid(tbe)) {
-      testAndRead(addr, tbe.DataBlk, pkt);
+      testAndRead(addr, tbe.DataBlk, pkt, block_size_bits);
     } else {
       functionalMemoryRead(pkt);
     }
@@ -335,7 +335,7 @@
     TBE tbe := TBEs.lookup(addr);
     if(is_valid(tbe)) {
       num_functional_writes := num_functional_writes +
-            testAndWrite(addr, tbe.DataBlk, pkt);
+            testAndWrite(addr, tbe.DataBlk, pkt, block_size_bits);
     }
 
     num_functional_writes := num_functional_writes + functionalMemoryWrite(pkt);
diff --git a/src/mem/protocol/MOESI_AMD_Base-L3cache.sm b/src/mem/protocol/MOESI_AMD_Base-L3cache.sm
--- a/src/mem/protocol/MOESI_AMD_Base-L3cache.sm
+++ b/src/mem/protocol/MOESI_AMD_Base-L3cache.sm
@@ -195,7 +195,7 @@
   void functionalRead(Addr addr, Packet *pkt) {
     TBE tbe := TBEs.lookup(addr);
     if(is_valid(tbe)) {
-      testAndRead(addr, tbe.DataBlk, pkt);
+      testAndRead(addr, tbe.DataBlk, pkt, block_size_bits);
     } else {
       functionalMemoryRead(pkt);
     }
@@ -207,7 +207,7 @@
     TBE tbe := TBEs.lookup(addr);
     if(is_valid(tbe)) {
       num_functional_writes := num_functional_writes +
-            testAndWrite(addr, tbe.DataBlk, pkt);
+            testAndWrite(addr, tbe.DataBlk, pkt, block_size_bits);
     }
 
     num_functional_writes := num_functional_writes +
diff --git a/src/mem/protocol/MOESI_AMD_Base-Region-CorePair.sm b/src/mem/protocol/MOESI_AMD_Base-Region-CorePair.sm
--- a/src/mem/protocol/MOESI_AMD_Base-Region-CorePair.sm
+++ b/src/mem/protocol/MOESI_AMD_Base-Region-CorePair.sm
@@ -331,7 +331,7 @@
   void functionalRead(Addr addr, Packet *pkt) {
     TBE tbe := TBEs.lookup(addr);
     if(is_valid(tbe)) {
-      testAndRead(addr, tbe.DataBlk, pkt);
+      testAndRead(addr, tbe.DataBlk, pkt, block_size_bits);
     } else {
       functionalMemoryRead(pkt);
     }
@@ -343,7 +343,7 @@
     TBE tbe := TBEs.lookup(addr);
     if(is_valid(tbe)) {
       num_functional_writes := num_functional_writes +
-            testAndWrite(addr, tbe.DataBlk, pkt);
+            testAndWrite(addr, tbe.DataBlk, pkt, block_size_bits);
     }
 
     num_functional_writes := num_functional_writes + functionalMemoryWrite(pkt);
diff --git a/src/mem/protocol/MOESI_AMD_Base-Region-dir.sm b/src/mem/protocol/MOESI_AMD_Base-Region-dir.sm
--- a/src/mem/protocol/MOESI_AMD_Base-Region-dir.sm
+++ b/src/mem/protocol/MOESI_AMD_Base-Region-dir.sm
@@ -259,7 +259,7 @@
   void functionalRead(Addr addr, Packet *pkt) {
     TBE tbe := TBEs.lookup(addr);
     if(is_valid(tbe)) {
-      testAndRead(addr, tbe.DataBlk, pkt);
+      testAndRead(addr, tbe.DataBlk, pkt, block_size_bits);
     } else {
       functionalMemoryRead(pkt);
     }
@@ -271,7 +271,7 @@
     TBE tbe := TBEs.lookup(addr);
     if(is_valid(tbe)) {
       num_functional_writes := num_functional_writes +
-            testAndWrite(addr, tbe.DataBlk, pkt);
+            testAndWrite(addr, tbe.DataBlk, pkt, block_size_bits);
     }
 
     num_functional_writes := num_functional_writes + functionalMemoryWrite(pkt);
diff --git a/src/mem/protocol/MOESI_AMD_Base-Region-msg.sm b/src/mem/protocol/MOESI_AMD_Base-Region-msg.sm
--- a/src/mem/protocol/MOESI_AMD_Base-Region-msg.sm
+++ b/src/mem/protocol/MOESI_AMD_Base-Region-msg.sm
@@ -130,7 +130,7 @@
   bool functionalRead(Packet *pkt, uint32_t block_size_bits) {
     // Only PUTX messages contains the data block
     if (Type == CoherenceRequestType:VicDirty) {
-        return testAndRead(addr, DataBlk, pkt);
+        return testAndRead(addr, DataBlk, pkt, block_size_bits);
     }
 
     return false;
@@ -139,7 +139,7 @@
   bool functionalWrite(Packet *pkt, uint32_t block_size_bits) {
     // No check on message type required since the protocol should
     // read data from those messages that contain the block
-    return testAndWrite(addr, DataBlk, pkt);
+    return testAndWrite(addr, DataBlk, pkt, block_size_bits);
   }
 }
 
@@ -232,7 +232,7 @@
     // Only PUTX messages contains the data block
     if (Type == CoherenceResponseType:CPUData ||
         Type == CoherenceResponseType:MemData) {
-        return testAndRead(addr, DataBlk, pkt);
+        return testAndRead(addr, DataBlk, pkt, block_size_bits);
     }
 
     return false;
@@ -241,7 +241,7 @@
   bool functionalWrite(Packet *pkt, uint32_t block_size_bits) {
     // No check on message type required since the protocol should
     // read data from those messages that contain the block
-    return testAndWrite(addr, DataBlk, pkt);
+    return testAndWrite(addr, DataBlk, pkt, block_size_bits);
   }
 }