diff --git a/src/mem/protocol/MOESI_CMP_token-L2cache.sm b/src/mem/protocol/MOESI_CMP_token-L2cache.sm
--- a/src/mem/protocol/MOESI_CMP_token-L2cache.sm
+++ b/src/mem/protocol/MOESI_CMP_token-L2cache.sm
@@ -979,7 +979,7 @@
   }
 
   action(vv_allocateL2CacheBlock, "\v", desc="Set L2 cache tag equal to tag of block B.") {
-    set_cache_entry(L2cache.allocate(address, new Entry));
+    set_cache_entry(L2cache.allocate(address, new Entry(block_size_bytes)));
   }
 
   action(rr_deallocateL2CacheBlock, "\r", desc="Deallocate L2 cache block.  Sets the cache to not present, allowing a replacement in parallel with a fetch.") {
diff --git a/src/mem/protocol/MOESI_CMP_token-dir.sm b/src/mem/protocol/MOESI_CMP_token-dir.sm
--- a/src/mem/protocol/MOESI_CMP_token-dir.sm
+++ b/src/mem/protocol/MOESI_CMP_token-dir.sm
@@ -167,7 +167,7 @@
   PersistentTable * persistentTable, constructor="m_block_size_bits";
   TimerTable * reissueTimerTable;
 
-  TBETable * TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs";
+  TBETable * TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs, m_block_size_bytes";
 
   bool starving, default="false";
   int l2_select_low_bit, default="RubySystem::getBlockSizeBits()";
@@ -185,7 +185,7 @@
     }
 
     dir_entry :=  static_cast(Entry, "pointer",
-                              directory.allocate(addr, new Entry));
+                              directory.allocate(addr, new Entry(block_size_bytes)));
     return dir_entry;
   }
 
diff --git a/src/mem/protocol/MOESI_hammer-cache.sm b/src/mem/protocol/MOESI_hammer-cache.sm
--- a/src/mem/protocol/MOESI_hammer-cache.sm
+++ b/src/mem/protocol/MOESI_hammer-cache.sm
@@ -178,7 +178,7 @@
     bool isPresent(Addr);
   }
 
-  TBETable * TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs";
+  TBETable * TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs, m_block_size_bytes";
 
   Tick clockEdge();
   void set_cache_entry(AbstractCacheEntry b);
@@ -1232,18 +1232,18 @@
 
   action(ii_allocateL1DCacheBlock, "\i", desc="Set L1 D-cache tag equal to tag of block B.") {
     if (is_invalid(cache_entry)) {
-      set_cache_entry(L1Dcache.allocate(address, new Entry));
+      set_cache_entry(L1Dcache.allocate(address, new Entry(block_size_bytes)));
     }
   }
 
   action(jj_allocateL1ICacheBlock, "\j", desc="Set L1 I-cache tag equal to tag of block B.") {
     if (is_invalid(cache_entry)) {
-      set_cache_entry(L1Icache.allocate(address, new Entry));
+      set_cache_entry(L1Icache.allocate(address, new Entry(block_size_bytes)));
     }
   }
 
   action(vv_allocateL2CacheBlock, "\v", desc="Set L2 cache tag equal to tag of block B.") {
-    set_cache_entry(L2cache.allocate(address, new Entry));
+    set_cache_entry(L2cache.allocate(address, new Entry(block_size_bytes)));
   }
 
   action(rr_deallocateL2CacheBlock, "\r", desc="Deallocate L2 cache block.  Sets the cache to not present, allowing a replacement in parallel with a fetch.") {
diff --git a/src/mem/protocol/MOESI_hammer-dir.sm b/src/mem/protocol/MOESI_hammer-dir.sm
--- a/src/mem/protocol/MOESI_hammer-dir.sm
+++ b/src/mem/protocol/MOESI_hammer-dir.sm
@@ -196,7 +196,7 @@
 
   Set fwd_set;
 
-  TBETable * TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs";
+  TBETable * TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs, m_block_size_bytes";
 
   Entry getDirectoryEntry(Addr addr), return_by_pointer="yes" {
     Entry dir_entry := static_cast(Entry, "pointer", directory[addr]);
@@ -206,7 +206,7 @@
     }
 
     dir_entry :=  static_cast(Entry, "pointer",
-                              directory.allocate(addr, new Entry));
+                              directory.allocate(addr, new Entry(block_size_bytes)));
     return dir_entry;
   }
 
@@ -543,7 +543,7 @@
   action(pfa_probeFilterAllocate, "pfa", desc="Allocate ProbeFilterEntry") {
     if (probe_filter_enabled || full_bit_dir_enabled) {
       peek(requestQueue_in, RequestMsg) {
-        set_cache_entry(probeFilter.allocate(address, new PfEntry));
+        set_cache_entry(probeFilter.allocate(address, new PfEntry(block_size_bytes)));
         cache_entry.Owner := in_msg.Requestor;
         cache_entry.Sharers.setSize(machineCount(MachineType:L1Cache));
       }
diff --git a/src/mem/ruby/structures/TBETable.hh b/src/mem/ruby/structures/TBETable.hh
--- a/src/mem/ruby/structures/TBETable.hh
+++ b/src/mem/ruby/structures/TBETable.hh
@@ -38,8 +38,9 @@
 class TBETable
 {
   public:
-    TBETable(int number_of_TBEs)
-        : m_number_of_TBEs(number_of_TBEs)
+    TBETable(int number_of_TBEs, uint32_t block_size_bytes)
+        : m_number_of_TBEs(number_of_TBEs),
+          m_block_size_bytes(block_size_bytes)
     {
     }
 
@@ -65,8 +66,8 @@
     // Data Members (m_prefix)
     std::unordered_map<Addr, ENTRY*> m_map;
 
-  private:
     const int m_number_of_TBEs;
+    const uint32_t m_block_size_bytes;
 };
 
 template<class ENTRY>
@@ -92,7 +93,7 @@
 {
     assert(!isPresent(address));
     assert(m_map.size() < m_number_of_TBEs);
-    m_map[address] = new ENTRY();
+    m_map[address] = new ENTRY(m_block_size_bytes);
 }
 
 template<class ENTRY>
diff --git a/src/mem/slicc/symbols/Type.py b/src/mem/slicc/symbols/Type.py
--- a/src/mem/slicc/symbols/Type.py
+++ b/src/mem/slicc/symbols/Type.py
@@ -84,6 +84,13 @@
         if self.ident == "Prefetcher":
             self["prefetcher"] = "yes"
 
+        if self.ident == "Entry" or \
+           self.ident == "DirEntry" or \
+           self.ident == "CacheEntry" or \
+           self.ident == "PfEntry" or \
+           self.ident == "TBE":
+            self["entry"] = "yes"
+
         self.isMachineType = (ident == "MachineType")
 
         self.isStateDecl = ("state_decl" in self)
@@ -101,6 +108,9 @@
     def isMessage(self):
         return "message" in self
     @property
+    def isEntry(self):
+        return "entry" in self
+    @property
     def isBuffer(self):
         return "buffer" in self
     @property
@@ -220,10 +230,31 @@
 ''', klass="class")
 
         if self.isMessage:
-            code('(Tick curTime) : %s(curTime) {' % self["interface"])
+                code('(Tick curTime) : %s(curTime)' % self["interface"])
+        elif self.isEntry:
+            code('(uint32_t block_size_bytes)')
+
+            data_block = False
+            for dm in self.data_members.values():
+                if "DataBlk" in dm.ident:
+                    data_block = True
+
+            dma_data_block = False
+            for dm in self.data_members.values():
+                if "DmaDataBlk" in dm.ident:
+                    dma_data_block = True
+
+            if data_block and dma_data_block:
+                code(' : m_DmaDataBlk(block_size_bytes), '
+                     ' m_DataBlk(block_size_bytes)')
+            elif data_block:
+                code(' : m_DataBlk(block_size_bytes)')
+            elif dma_data_block:
+                code(' : m_DmaDataBlk(block_size_bytes)')
         else:
-            code('()\n\t\t{')
+            code('()')
 
+        code(' {')
         code.indent()
         if not self.isGlobal:
             code.indent()
diff --git a/src/mem/protocol/MOESI_AMD_Base-L3cache.sm b/src/mem/protocol/MOESI_AMD_Base-L3cache.sm
--- a/src/mem/protocol/MOESI_AMD_Base-L3cache.sm
+++ b/src/mem/protocol/MOESI_AMD_Base-L3cache.sm
@@ -147,7 +147,7 @@
     bool isPresent(Addr);
   }
 
-  TBETable * TBEs, template="<L3Cache_TBE>", constructor="m_number_of_TBEs";
+  TBETable * TBEs, template="<L3Cache_TBE>", constructor="m_number_of_TBEs, m_block_size_bytes";
 
   void set_cache_entry(AbstractCacheEntry b);
   void unset_cache_entry();
@@ -551,7 +551,7 @@
 
   action(a_allocateBlock, "a", desc="allocate L3 block") {
     if (is_invalid(cache_entry)) {
-      set_cache_entry(L3cache.allocate(address, new Entry));
+      set_cache_entry(L3cache.allocate(address, new Entry(block_size_bytes)));
     }
   }
 
diff --git a/src/mem/protocol/MOESI_AMD_Base-Region-CorePair.sm b/src/mem/protocol/MOESI_AMD_Base-Region-CorePair.sm
--- a/src/mem/protocol/MOESI_AMD_Base-Region-CorePair.sm
+++ b/src/mem/protocol/MOESI_AMD_Base-Region-CorePair.sm
@@ -225,7 +225,7 @@
     bool isPresent(Addr);
   }
 
-  TBETable * TBEs, template="<CorePair_TBE>", constructor="m_number_of_TBEs";
+  TBETable * TBEs, template="<CorePair_TBE>", constructor="m_number_of_TBEs, m_block_size_bytes";
 
   Tick clockEdge();
   Tick cyclesToTicks(Cycles c);
@@ -870,25 +870,25 @@
 
   action(a0_allocateL1D, "a0", desc="Allocate L1D0 Block") {
     if (L1D0cache.isTagPresent(address) == false) {
-      L1D0cache.allocateVoid(address, new Entry);
+      L1D0cache.allocateVoid(address, new Entry(block_size_bytes));
     }
   }
 
   action(a1_allocateL1D, "a1", desc="Allocate L1D1 Block") {
     if (L1D1cache.isTagPresent(address) == false) {
-      L1D1cache.allocateVoid(address, new Entry);
+      L1D1cache.allocateVoid(address, new Entry(block_size_bytes));
     }
   }
 
   action(ai_allocateL1I, "ai", desc="Allocate L1I Block") {
     if (L1Icache.isTagPresent(address) == false) {
-      L1Icache.allocateVoid(address, new Entry);
+      L1Icache.allocateVoid(address, new Entry(block_size_bytes));
     }
   }
 
   action(a2_allocateL2, "a2", desc="Allocate L2 Block") {
     if (is_invalid(cache_entry)) {
-      set_cache_entry(L2cache.allocate(address, new Entry));
+      set_cache_entry(L2cache.allocate(address, new Entry(block_size_bytes)));
     }
   }
 
diff --git a/src/mem/protocol/MOESI_AMD_Base-Region-dir.sm b/src/mem/protocol/MOESI_AMD_Base-Region-dir.sm
--- a/src/mem/protocol/MOESI_AMD_Base-Region-dir.sm
+++ b/src/mem/protocol/MOESI_AMD_Base-Region-dir.sm
@@ -199,7 +199,7 @@
     bool isPresent(Addr);
   }
 
-  TBETable * TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs";
+  TBETable * TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs, m_block_size_bytes";
 
   Tick clockEdge();
   Tick cyclesToTicks(Cycles c);
@@ -219,7 +219,7 @@
     }
 
     dir_entry :=  static_cast(Entry, "pointer",
-                              directory.allocate(addr, new Entry));
+                              directory.allocate(addr, new Entry(block_size_bytes)));
     return dir_entry;
   }
 
@@ -1273,7 +1273,7 @@
           L3CacheMemory.deallocate(victim);
         }
         assert(L3CacheMemory.cacheAvail(address));
-        CacheEntry entry := static_cast(CacheEntry, "pointer", L3CacheMemory.allocate(address, new CacheEntry));
+        CacheEntry entry := static_cast(CacheEntry, "pointer", L3CacheMemory.allocate(address, new CacheEntry(block_size_bytes)));
         APPEND_TRANSITION_COMMENT(" al wrote data to L3 ");
         entry.DataBlk := in_msg.DataBlk;
         entry.LastSender := in_msg.Sender;
@@ -1298,7 +1298,7 @@
           L3CacheMemory.deallocate(victim);
         }
         assert(L3CacheMemory.cacheAvail(address));
-        CacheEntry entry := static_cast(CacheEntry, "pointer", L3CacheMemory.allocate(address, new CacheEntry));
+        CacheEntry entry := static_cast(CacheEntry, "pointer", L3CacheMemory.allocate(address, new CacheEntry(block_size_bytes)));
         APPEND_TRANSITION_COMMENT(" al wrote data to L3 ");
         entry.DataBlk := tbe.DataBlk;
         entry.LastSender := tbe.LastSender;
@@ -1323,7 +1323,7 @@
           L3CacheMemory.deallocate(victim);
         }
         assert(L3CacheMemory.cacheAvail(address));
-        CacheEntry entry := static_cast(CacheEntry, "pointer", L3CacheMemory.allocate(address, new CacheEntry));
+        CacheEntry entry := static_cast(CacheEntry, "pointer", L3CacheMemory.allocate(address, new CacheEntry(block_size_bytes)));
         APPEND_TRANSITION_COMMENT(" al wrote data to L3 ");
         entry.DataBlk := tbe.DataBlk;
         entry.LastSender := tbe.LastSender;
@@ -1349,7 +1349,7 @@
             L3CacheMemory.deallocate(victim);
           }
           assert(L3CacheMemory.cacheAvail(address));
-          CacheEntry entry := static_cast(CacheEntry, "pointer", L3CacheMemory.allocate(address, new CacheEntry));
+          CacheEntry entry := static_cast(CacheEntry, "pointer", L3CacheMemory.allocate(address, new CacheEntry(block_size_bytes)));
           APPEND_TRANSITION_COMMENT(" ali wrote data to L3 ");
           entry.DataBlk := in_msg.DataBlk;
           entry.LastSender := in_msg.Sender;
diff --git a/src/mem/protocol/MOESI_AMD_Base-RegionBuffer.sm b/src/mem/protocol/MOESI_AMD_Base-RegionBuffer.sm
--- a/src/mem/protocol/MOESI_AMD_Base-RegionBuffer.sm
+++ b/src/mem/protocol/MOESI_AMD_Base-RegionBuffer.sm
@@ -184,7 +184,7 @@
   }
 
   // Stores only region addresses
-  TBETable * TBEs, template="<RegionBuffer_TBE>", constructor="m_number_of_TBEs";
+  TBETable * TBEs, template="<RegionBuffer_TBE>", constructor="m_number_of_TBEs, m_block_size_bytes";
   int TCC_select_low_bit, default="RubySystem::getBlockSizeBits()";
 
   Tick clockEdge();
@@ -963,7 +963,7 @@
   }
 
   action(a_allocateRegionEntry, "a", desc="Allocate a new entry") {
-    set_cache_entry(cacheMemory.allocate(getRegionBase(address), new Entry));
+    set_cache_entry(cacheMemory.allocate(getRegionBase(address), new Entry(block_size_bytes)));
     cache_entry.ValidBlocks.clear();
     cache_entry.ValidBlocks.resize(blocksPerRegion);
     cache_entry.UsedBlocks.clear();
diff --git a/src/mem/protocol/MOESI_AMD_Base-RegionDir.sm b/src/mem/protocol/MOESI_AMD_Base-RegionDir.sm
--- a/src/mem/protocol/MOESI_AMD_Base-RegionDir.sm
+++ b/src/mem/protocol/MOESI_AMD_Base-RegionDir.sm
@@ -158,7 +158,7 @@
   }
 
   // Stores only region addresses
-  TBETable * TBEs, template="<RegionDir_TBE>", constructor="m_number_of_TBEs";
+  TBETable * TBEs, template="<RegionDir_TBE>", constructor="m_number_of_TBEs, m_block_size_bytes";
   int TCC_select_low_bit, default="RubySystem::getBlockSizeBits()";
 
   Tick clockEdge();
@@ -597,7 +597,7 @@
   }
 
   action(a_allocateRegionEntry, "a", desc="Allocate a new entry") {
-    set_cache_entry(cacheMemory.allocate(getRegionBase(address), new Entry));
+    set_cache_entry(cacheMemory.allocate(getRegionBase(address), new Entry(block_size_bytes)));
     peek(requestNetwork_in, CPURequestMsg) {
       APPEND_TRANSITION_COMMENT(in_msg.Requestor);
     }
diff --git a/src/mem/protocol/MOESI_AMD_Base-dir.sm b/src/mem/protocol/MOESI_AMD_Base-dir.sm
--- a/src/mem/protocol/MOESI_AMD_Base-dir.sm
+++ b/src/mem/protocol/MOESI_AMD_Base-dir.sm
@@ -157,7 +157,7 @@
     bool isPresent(Addr);
   }
 
-  TBETable * TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs";
+  TBETable * TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs, m_block_size_bytes";
 
   int TCC_select_low_bit, default="RubySystem::getBlockSizeBits()";
 
@@ -178,7 +178,7 @@
     }
 
     dir_entry :=  static_cast(Entry, "pointer",
-                              directory.allocate(addr, new Entry));
+                              directory.allocate(addr, new Entry(block_size_bytes)));
     return dir_entry;
   }
 
@@ -805,7 +805,7 @@
           L3CacheMemory.deallocate(victim);
         }
         assert(L3CacheMemory.cacheAvail(address));
-        CacheEntry entry := static_cast(CacheEntry, "pointer", L3CacheMemory.allocate(address, new CacheEntry));
+        CacheEntry entry := static_cast(CacheEntry, "pointer", L3CacheMemory.allocate(address, new CacheEntry(block_size_bytes)));
         APPEND_TRANSITION_COMMENT(" al wrote data to L3 ");
         entry.DataBlk := in_msg.DataBlk;
 
@@ -831,7 +831,7 @@
           L3CacheMemory.deallocate(victim);
         }
         assert(L3CacheMemory.cacheAvail(address));
-        CacheEntry entry := static_cast(CacheEntry, "pointer", L3CacheMemory.allocate(address, new CacheEntry));
+        CacheEntry entry := static_cast(CacheEntry, "pointer", L3CacheMemory.allocate(address, new CacheEntry(block_size_bytes)));
         APPEND_TRANSITION_COMMENT(" al wrote data to L3 ");
         entry.DataBlk := tbe.DataBlk;
         entry.LastSender := tbe.LastSender;
diff --git a/src/mem/protocol/MOESI_AMD_Base-probeFilter.sm b/src/mem/protocol/MOESI_AMD_Base-probeFilter.sm
--- a/src/mem/protocol/MOESI_AMD_Base-probeFilter.sm
+++ b/src/mem/protocol/MOESI_AMD_Base-probeFilter.sm
@@ -189,7 +189,7 @@
     bool isPresent(Addr);
   }
 
-  TBETable * TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs";
+  TBETable * TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs, m_block_size_bytes";
 
   int TCC_select_low_bit, default="RubySystem::getBlockSizeBits()";
 
@@ -211,7 +211,7 @@
     }
 
     dir_entry :=  static_cast(Entry, "pointer",
-                              directory.allocate(addr, new Entry));
+                              directory.allocate(addr, new Entry(block_size_bytes)));
     return dir_entry;
   }
 
@@ -950,7 +950,7 @@
           L3CacheMemory.deallocate(victim);
         }
         assert(L3CacheMemory.cacheAvail(address));
-        CacheEntry entry := static_cast(CacheEntry, "pointer", L3CacheMemory.allocate(address, new CacheEntry));
+        CacheEntry entry := static_cast(CacheEntry, "pointer", L3CacheMemory.allocate(address, new CacheEntry(block_size_bytes)));
         APPEND_TRANSITION_COMMENT(" al wrote data to L3 ");
         entry.DataBlk := in_msg.DataBlk;
 
@@ -976,7 +976,7 @@
           L3CacheMemory.deallocate(victim);
         }
         assert(L3CacheMemory.cacheAvail(address));
-        CacheEntry entry := static_cast(CacheEntry, "pointer", L3CacheMemory.allocate(address, new CacheEntry));
+        CacheEntry entry := static_cast(CacheEntry, "pointer", L3CacheMemory.allocate(address, new CacheEntry(block_size_bytes)));
         APPEND_TRANSITION_COMMENT(" al wrote data to L3 ");
         entry.DataBlk := tbe.DataBlk;
         entry.LastSender := tbe.LastSender;
@@ -993,7 +993,7 @@
           ProbeFilterMemory.deallocate(victim);
         }
         assert(ProbeFilterMemory.cacheAvail(address));
-        CacheEntry entry := static_cast(CacheEntry, "pointer", ProbeFilterMemory.allocate(address, new CacheEntry));
+        CacheEntry entry := static_cast(CacheEntry, "pointer", ProbeFilterMemory.allocate(address, new CacheEntry(block_size_bytes)));
         APPEND_TRANSITION_COMMENT(" allocating a new probe filter entry");
         entry.pfState := ProbeFilterState:NT;
         if (inclusiveDir) {
diff --git a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
--- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
@@ -140,7 +140,7 @@
   void set_tbe(TBE b);
   void unset_tbe();
 
-  TBETable * TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs";
+  TBETable * TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs, m_block_size_bytes";
   TimerTable * useTimerTable;
   int l2_select_low_bit, default="RubySystem::getBlockSizeBits()";
 
@@ -891,13 +891,13 @@
 
   action(ii_allocateL1DCacheBlock, "\i", desc="Set L1 D-cache tag equal to tag of block B.") {
     if ((is_invalid(cache_entry))) {
-      set_cache_entry(L1Dcache.allocate(address, new Entry));
+      set_cache_entry(L1Dcache.allocate(address, new Entry(block_size_bytes)));
     }
   }
 
   action(jj_allocateL1ICacheBlock, "\j", desc="Set L1 I-cache tag equal to tag of block B.") {
     if ((is_invalid(cache_entry))) {
-      set_cache_entry(L1Icache.allocate(address, new Entry));
+      set_cache_entry(L1Icache.allocate(address, new Entry(block_size_bytes)));
     }
   }
 
diff --git a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
--- a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
@@ -224,7 +224,7 @@
     bool isTagPresent(Addr);
   }
 
-  TBETable * TBEs, template="<L2Cache_TBE>", constructor="m_number_of_TBEs";
+  TBETable * TBEs, template="<L2Cache_TBE>", constructor="m_number_of_TBEs, m_block_size_bytes";
   PerfectCacheMemory * localDirectory, template="<L2Cache_DirEntry>",
                      constructor="m_block_size_bits";
 
@@ -1527,7 +1527,7 @@
   }
 
   action(vv_allocateL2CacheBlock, "\v", desc="Set L2 cache tag equal to tag of block B.") {
-    set_cache_entry(L2cache.allocate(address, new Entry));
+    set_cache_entry(L2cache.allocate(address, new Entry(block_size_bytes)));
   }
 
   action(rr_deallocateL2CacheBlock, "\r", desc="Deallocate L2 cache block.  Sets the cache to not present, allowing a replacement in parallel with a fetch.") {
diff --git a/src/mem/protocol/MOESI_CMP_directory-dir.sm b/src/mem/protocol/MOESI_CMP_directory-dir.sm
--- a/src/mem/protocol/MOESI_CMP_directory-dir.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-dir.sm
@@ -117,7 +117,7 @@
   }
 
   // ** OBJECTS **
-  TBETable * TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs";
+  TBETable * TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs, m_block_size_bytes";
 
   Tick clockEdge();
   Tick cyclesToTicks(Cycles c);
@@ -132,7 +132,7 @@
     }
 
     dir_entry :=  static_cast(Entry, "pointer",
-                              directory.allocate(addr, new Entry));
+                              directory.allocate(addr, new Entry(block_size_bytes)));
     return dir_entry;
   }
 
diff --git a/src/mem/protocol/MOESI_CMP_directory-dma.sm b/src/mem/protocol/MOESI_CMP_directory-dma.sm
--- a/src/mem/protocol/MOESI_CMP_directory-dma.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-dma.sm
@@ -71,7 +71,7 @@
     bool isPresent(Addr);
   }
 
-  TBETable * TBEs, template="<DMA_TBE>", constructor="m_number_of_TBEs";
+  TBETable * TBEs, template="<DMA_TBE>", constructor="m_number_of_TBEs, m_block_size_bytes";
   State cur_state;
 
   Tick clockEdge();
diff --git a/src/mem/protocol/MOESI_CMP_token-L1cache.sm b/src/mem/protocol/MOESI_CMP_token-L1cache.sm
--- a/src/mem/protocol/MOESI_CMP_token-L1cache.sm
+++ b/src/mem/protocol/MOESI_CMP_token-L1cache.sm
@@ -194,7 +194,7 @@
   void wakeUpBuffers(Addr a);
   Cycles curCycle();
 
-  TBETable * L1_TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs";
+  TBETable * L1_TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs, m_block_size_bytes";
 
   bool starving, default="false";
   int l2_select_low_bit, default="RubySystem::getBlockSizeBits()";
@@ -1532,14 +1532,14 @@
   action(ii_allocateL1DCacheBlock, "\i", desc="Set L1 D-cache tag equal to tag of block B.") {
     if (is_valid(cache_entry)) {
     } else {
-      set_cache_entry(L1Dcache.allocate(address, new Entry));
+      set_cache_entry(L1Dcache.allocate(address, new Entry(block_size_bytes)));
     }
   }
 
   action(pp_allocateL1ICacheBlock, "\p", desc="Set L1 I-cache tag equal to tag of block B.") {
     if (is_valid(cache_entry)) {
     } else {
-      set_cache_entry(L1Icache.allocate(address, new Entry));
+      set_cache_entry(L1Icache.allocate(address, new Entry(block_size_bytes)));
     }
   }
 
diff --git a/src/mem/protocol/GPU_VIPER-TCP.sm b/src/mem/protocol/GPU_VIPER-TCP.sm
--- a/src/mem/protocol/GPU_VIPER-TCP.sm
+++ b/src/mem/protocol/GPU_VIPER-TCP.sm
@@ -114,7 +114,7 @@
     bool isPresent(Addr);
   }
 
-  TBETable * TBEs, template="<TCP_TBE>", constructor="m_number_of_TBEs";
+  TBETable * TBEs, template="<TCP_TBE>", constructor="m_number_of_TBEs, m_block_size_bytes";
   int TCC_select_low_bit, default="RubySystem::getBlockSizeBits()";
   int WTcnt, default="0";
   int Fcnt, default="0";
@@ -448,7 +448,7 @@
 
   action(a_allocate, "a", desc="allocate block") {
     if (is_invalid(cache_entry)) {
-      set_cache_entry(L1cache.allocate(address, new Entry));
+      set_cache_entry(L1cache.allocate(address, new Entry(block_size_bytes)));
     }
     cache_entry.writeMask.clear(block_size_bytes);
   }
diff --git a/src/mem/protocol/GPU_VIPER_Region-TCC.sm b/src/mem/protocol/GPU_VIPER_Region-TCC.sm
--- a/src/mem/protocol/GPU_VIPER_Region-TCC.sm
+++ b/src/mem/protocol/GPU_VIPER_Region-TCC.sm
@@ -122,7 +122,7 @@
     bool isPresent(Addr);
   }
 
-  TBETable * TBEs, template="<TCC_TBE>", constructor="m_number_of_TBEs";
+  TBETable * TBEs, template="<TCC_TBE>", constructor="m_number_of_TBEs, m_block_size_bytes";
 
   void set_cache_entry(AbstractCacheEntry b);
   void unset_cache_entry();
@@ -468,7 +468,7 @@
 
   action(a_allocateBlock, "a", desc="allocate TCC block") {
     if (is_invalid(cache_entry)) {
-      set_cache_entry(L2cache.allocate(address, new Entry));
+      set_cache_entry(L2cache.allocate(address, new Entry(block_size_bytes)));
       cache_entry.writeMask.clear(block_size_bytes);
     }
   }
diff --git a/src/mem/protocol/MESI_Three_Level-L0cache.sm b/src/mem/protocol/MESI_Three_Level-L0cache.sm
--- a/src/mem/protocol/MESI_Three_Level-L0cache.sm
+++ b/src/mem/protocol/MESI_Three_Level-L0cache.sm
@@ -133,7 +133,7 @@
     bool isPresent(Addr);
   }
 
-  TBETable * TBEs, template="<L0Cache_TBE>", constructor="m_number_of_TBEs";
+  TBETable * TBEs, template="<L0Cache_TBE>", constructor="m_number_of_TBEs, m_block_size_bytes";
 
   Tick clockEdge();
   Cycles ticksToCycles(Tick t);
@@ -568,13 +568,13 @@
 
   action(oo_allocateDCacheBlock, "\o", desc="Set L1 D-cache tag equal to tag of block B.") {
     if (is_invalid(cache_entry)) {
-      set_cache_entry(Dcache.allocate(address, new Entry));
+      set_cache_entry(Dcache.allocate(address, new Entry(block_size_bytes)));
     }
   }
 
   action(pp_allocateICacheBlock, "\p", desc="Set L1 I-cache tag equal to tag of block B.") {
     if (is_invalid(cache_entry)) {
-      set_cache_entry(Icache.allocate(address, new Entry));
+      set_cache_entry(Icache.allocate(address, new Entry(block_size_bytes)));
     }
   }
 
diff --git a/src/mem/protocol/MESI_Three_Level-L1cache.sm b/src/mem/protocol/MESI_Three_Level-L1cache.sm
--- a/src/mem/protocol/MESI_Three_Level-L1cache.sm
+++ b/src/mem/protocol/MESI_Three_Level-L1cache.sm
@@ -147,7 +147,7 @@
     bool isPresent(Addr);
   }
 
-  TBETable * TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs";
+  TBETable * TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs, m_block_size_bytes";
 
   int l2_select_low_bit, default="RubySystem::getBlockSizeBits()";
 
@@ -715,7 +715,7 @@
 
   action(oo_allocateCacheBlock, "\o", desc="Set cache tag equal to tag of block B.") {
     if (is_invalid(cache_entry)) {
-      set_cache_entry(cache.allocate(address, new Entry));
+      set_cache_entry(cache.allocate(address, new Entry(block_size_bytes)));
     }
   }
 
diff --git a/src/mem/protocol/MESI_Two_Level-L1cache.sm b/src/mem/protocol/MESI_Two_Level-L1cache.sm
--- a/src/mem/protocol/MESI_Two_Level-L1cache.sm
+++ b/src/mem/protocol/MESI_Two_Level-L1cache.sm
@@ -152,7 +152,7 @@
     bool isPresent(Addr);
   }
 
-  TBETable * TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs";
+  TBETable * TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs, m_block_size_bytes";
 
   int l2_select_low_bit, default="RubySystem::getBlockSizeBits()";
 
@@ -930,13 +930,13 @@
 
   action(oo_allocateL1DCacheBlock, "\o", desc="Set L1 D-cache tag equal to tag of block B.") {
     if (is_invalid(cache_entry)) {
-      set_cache_entry(L1Dcache.allocate(address, new Entry));
+      set_cache_entry(L1Dcache.allocate(address, new Entry(block_size_bytes)));
     }
   }
 
   action(pp_allocateL1ICacheBlock, "\p", desc="Set L1 I-cache tag equal to tag of block B.") {
     if (is_invalid(cache_entry)) {
-      set_cache_entry(L1Icache.allocate(address, new Entry));
+      set_cache_entry(L1Icache.allocate(address, new Entry(block_size_bytes)));
     }
   }
 
diff --git a/src/mem/protocol/MESI_Two_Level-L2cache.sm b/src/mem/protocol/MESI_Two_Level-L2cache.sm
--- a/src/mem/protocol/MESI_Two_Level-L2cache.sm
+++ b/src/mem/protocol/MESI_Two_Level-L2cache.sm
@@ -146,7 +146,7 @@
     bool isPresent(Addr);
   }
 
-  TBETable * TBEs, template="<L2Cache_TBE>", constructor="m_number_of_TBEs";
+  TBETable * TBEs, template="<L2Cache_TBE>", constructor="m_number_of_TBEs, m_block_size_bytes";
 
   Tick clockEdge();
   Tick cyclesToTicks(Cycles c);
@@ -689,7 +689,7 @@
 
   action(qq_allocateL2CacheBlock, "\q", desc="Set L2 cache tag equal to tag of block B.") {
     if (is_invalid(cache_entry)) {
-      set_cache_entry(L2cache.allocate(address, new Entry));
+      set_cache_entry(L2cache.allocate(address, new Entry(block_size_bytes)));
     }
   }
 
diff --git a/src/mem/protocol/MESI_Two_Level-dir.sm b/src/mem/protocol/MESI_Two_Level-dir.sm
--- a/src/mem/protocol/MESI_Two_Level-dir.sm
+++ b/src/mem/protocol/MESI_Two_Level-dir.sm
@@ -96,7 +96,7 @@
 
 
   // ** OBJECTS **
-  TBETable * TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs";
+  TBETable * TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs, m_block_size_bytes";
 
   Tick clockEdge();
   Tick cyclesToTicks(Cycles c);
@@ -112,7 +112,7 @@
     }
 
     dir_entry :=  static_cast(Entry, "pointer",
-                              directory.allocate(addr, new Entry));
+                              directory.allocate(addr, new Entry(block_size_bytes)));
     return dir_entry;
   }
 
diff --git a/src/mem/protocol/MI_example-cache.sm b/src/mem/protocol/MI_example-cache.sm
--- a/src/mem/protocol/MI_example-cache.sm
+++ b/src/mem/protocol/MI_example-cache.sm
@@ -100,7 +100,7 @@
 
 
   // STRUCTURES
-  TBETable * TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs";
+  TBETable * TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs, m_block_size_bytes";
 
   // PROTOTYPES
   Tick clockEdge();
@@ -321,7 +321,7 @@
   action(i_allocateL1CacheBlock, "i", desc="Allocate a cache block") {
     if (is_valid(cache_entry)) {
     } else {
-      set_cache_entry(cacheMemory.allocate(address, new Entry));
+      set_cache_entry(cacheMemory.allocate(address, new Entry(block_size_bytes)));
     }
   }
 
diff --git a/src/mem/protocol/MI_example-dir.sm b/src/mem/protocol/MI_example-dir.sm
--- a/src/mem/protocol/MI_example-dir.sm
+++ b/src/mem/protocol/MI_example-dir.sm
@@ -106,7 +106,7 @@
   }
 
   // ** OBJECTS **
-  TBETable * TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs";
+  TBETable * TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs, m_block_size_bytes";
 
   Tick clockEdge();
   Cycles ticksToCycles(Tick t);
@@ -122,7 +122,7 @@
     }
 
     dir_entry :=  static_cast(Entry, "pointer",
-                              directory.allocate(addr, new Entry));
+                              directory.allocate(addr, new Entry(block_size_bytes)));
     return dir_entry;
   }
  
diff --git a/src/mem/protocol/MOESI_AMD_Base-CorePair.sm b/src/mem/protocol/MOESI_AMD_Base-CorePair.sm
--- a/src/mem/protocol/MOESI_AMD_Base-CorePair.sm
+++ b/src/mem/protocol/MOESI_AMD_Base-CorePair.sm
@@ -221,7 +221,7 @@
     bool isPresent(Addr);
   }
 
-  TBETable * TBEs, template="<CorePair_TBE>", constructor="m_number_of_TBEs";
+  TBETable * TBEs, template="<CorePair_TBE>", constructor="m_number_of_TBEs, m_block_size_bytes";
 
   void set_cache_entry(AbstractCacheEntry b);
   void unset_cache_entry();
@@ -775,25 +775,25 @@
 
   action(a0_allocateL1D, "a0", desc="Allocate L1D0 Block") {
     if (L1D0cache.isTagPresent(address) == false) {
-      L1D0cache.allocateVoid(address, new Entry);
+      L1D0cache.allocateVoid(address, new Entry(block_size_bytes));
     }
   }
 
   action(a1_allocateL1D, "a1", desc="Allocate L1D1 Block") {
     if (L1D1cache.isTagPresent(address) == false) {
-      L1D1cache.allocateVoid(address, new Entry);
+      L1D1cache.allocateVoid(address, new Entry(block_size_bytes));
     }
   }
 
   action(ai_allocateL1I, "ai", desc="Allocate L1I Block") {
     if (L1Icache.isTagPresent(address) == false) {
-      L1Icache.allocateVoid(address, new Entry);
+      L1Icache.allocateVoid(address, new Entry(block_size_bytes));
     }
   }
 
   action(a2_allocateL2, "a2", desc="Allocate L2 Block") {
     if (is_invalid(cache_entry)) {
-      set_cache_entry(L2cache.allocate(address, new Entry));
+      set_cache_entry(L2cache.allocate(address, new Entry(block_size_bytes)));
     }
   }
 
# Node ID ad5965016b8eed272bc9ec93bbe14302ef57730f
# Parent  5990fc6e2e539602e2e3e7294e3257aae36fde98
diff --git a/src/mem/protocol/GPU_RfO-SQC.sm b/src/mem/protocol/GPU_RfO-SQC.sm
--- a/src/mem/protocol/GPU_RfO-SQC.sm
+++ b/src/mem/protocol/GPU_RfO-SQC.sm
@@ -106,7 +106,7 @@
     bool isPresent(Addr);
   }
 
-  TBETable * TBEs, template="<SQC_TBE>", constructor="m_number_of_TBEs";
+  TBETable * TBEs, template="<SQC_TBE>", constructor="m_number_of_TBEs, m_block_size_bytes";
   int TCC_select_low_bit, default="RubySystem::getBlockSizeBits()";
 
   Tick clockEdge();
@@ -341,7 +341,7 @@
 
   action(a_allocate, "a", desc="allocate block") {
     if (is_invalid(cache_entry)) {
-      set_cache_entry(L1cache.allocate(address, new Entry));
+      set_cache_entry(L1cache.allocate(address, new Entry(block_size_bytes)));
     }
   }
 
diff --git a/src/mem/protocol/GPU_RfO-TCC.sm b/src/mem/protocol/GPU_RfO-TCC.sm
--- a/src/mem/protocol/GPU_RfO-TCC.sm
+++ b/src/mem/protocol/GPU_RfO-TCC.sm
@@ -146,7 +146,7 @@
     bool isPresent(Addr);
   }
 
-  TBETable * TBEs, template="<TCC_TBE>", constructor="m_number_of_TBEs";
+  TBETable * TBEs, template="<TCC_TBE>", constructor="m_number_of_TBEs, m_block_size_bytes";
   int TCC_select_low_bit, default="RubySystem::getBlockSizeBits()";
 
   void set_cache_entry(AbstractCacheEntry b);
@@ -594,7 +594,7 @@
 
   action(a_allocateBlock, "a", desc="allocate TCC block") {
     if (is_invalid(cache_entry)) {
-      set_cache_entry(L2cache.allocate(address, new Entry));
+      set_cache_entry(L2cache.allocate(address, new Entry(block_size_bytes)));
     }
   }
 
diff --git a/src/mem/protocol/GPU_RfO-TCCdir.sm b/src/mem/protocol/GPU_RfO-TCCdir.sm
--- a/src/mem/protocol/GPU_RfO-TCCdir.sm
+++ b/src/mem/protocol/GPU_RfO-TCCdir.sm
@@ -236,7 +236,7 @@
   }
 
   // ** OBJECTS **
-  TBETable * TBEs, template="<TCCdir_TBE>", constructor="m_number_of_TBEs";
+  TBETable * TBEs, template="<TCCdir_TBE>", constructor="m_number_of_TBEs, m_block_size_bytes";
   int TCC_select_low_bit, default="RubySystem::getBlockSizeBits()";
   NetDest TCC_dir_subtree;
   NetDest temp;
@@ -1528,7 +1528,7 @@
 
   action(d_allocateDir, "d", desc="allocate Directory Cache") {
     if (is_invalid(cache_entry)) {
-      set_cache_entry(directory.allocate(address, new Entry));
+      set_cache_entry(directory.allocate(address, new Entry(block_size_bytes)));
     }
   }
 
diff --git a/src/mem/protocol/GPU_RfO-TCP.sm b/src/mem/protocol/GPU_RfO-TCP.sm
--- a/src/mem/protocol/GPU_RfO-TCP.sm
+++ b/src/mem/protocol/GPU_RfO-TCP.sm
@@ -124,7 +124,7 @@
     bool isPresent(Addr);
   }
 
-  TBETable * TBEs, template="<TCP_TBE>", constructor="m_number_of_TBEs";
+  TBETable * TBEs, template="<TCP_TBE>", constructor="m_number_of_TBEs, m_block_size_bytes";
   int TCC_select_low_bit, default="RubySystem::getBlockSizeBits()";
 
   Tick clockEdge();
@@ -441,7 +441,7 @@
 
   action(a_allocate, "a", desc="allocate block") {
     if (is_invalid(cache_entry)) {
-      set_cache_entry(L1cache.allocate(address, new Entry));
+      set_cache_entry(L1cache.allocate(address, new Entry(block_size_bytes)));
     }
   }
 
diff --git a/src/mem/protocol/GPU_VIPER-SQC.sm b/src/mem/protocol/GPU_VIPER-SQC.sm
--- a/src/mem/protocol/GPU_VIPER-SQC.sm
+++ b/src/mem/protocol/GPU_VIPER-SQC.sm
@@ -90,7 +90,7 @@
     bool isPresent(Addr);
   }
 
-  TBETable * TBEs, template="<SQC_TBE>", constructor="m_number_of_TBEs";
+  TBETable * TBEs, template="<SQC_TBE>", constructor="m_number_of_TBEs, m_block_size_bytes";
   int TCC_select_low_bit, default="RubySystem::getBlockSizeBits()";
 
   void set_cache_entry(AbstractCacheEntry b);
@@ -273,7 +273,7 @@
 
   action(a_allocate, "a", desc="allocate block") {
     if (is_invalid(cache_entry)) {
-      set_cache_entry(L1cache.allocate(address, new Entry));
+      set_cache_entry(L1cache.allocate(address, new Entry(block_size_bytes)));
     }
   }
 
diff --git a/src/mem/protocol/GPU_VIPER-TCC.sm b/src/mem/protocol/GPU_VIPER-TCC.sm
--- a/src/mem/protocol/GPU_VIPER-TCC.sm
+++ b/src/mem/protocol/GPU_VIPER-TCC.sm
@@ -117,7 +117,7 @@
     bool isPresent(Addr);
   }
 
-  TBETable * TBEs, template="<TCC_TBE>", constructor="m_number_of_TBEs";
+  TBETable * TBEs, template="<TCC_TBE>", constructor="m_number_of_TBEs, m_block_size_bytes";
 
   void set_cache_entry(AbstractCacheEntry b);
   void unset_cache_entry();
@@ -436,7 +436,7 @@
 
   action(a_allocateBlock, "a", desc="allocate TCC block") {
     if (is_invalid(cache_entry)) {
-      set_cache_entry(L2cache.allocate(address, new Entry));
+      set_cache_entry(L2cache.allocate(address, new Entry(block_size_bytes)));
       cache_entry.writeMask.clear(block_size_bytes);
     }
   }