# Node ID 88018e899f82b4f9f1ea3dc5ca7cbc9f0c0f2117
# Parent  ad5965016b8eed272bc9ec93bbe14302ef57730f
diff --git a/src/mem/ruby/structures/PerfectCacheMemory.hh b/src/mem/ruby/structures/PerfectCacheMemory.hh
--- a/src/mem/ruby/structures/PerfectCacheMemory.hh
+++ b/src/mem/ruby/structures/PerfectCacheMemory.hh
@@ -39,7 +39,7 @@
 {
     PerfectCacheLineState() { m_permission = AccessPermission_NUM; }
     AccessPermission m_permission;
-    ENTRY m_entry;
+    ENTRY *m_entry;
 };
 
 template<class ENTRY>
@@ -131,7 +131,8 @@
 {
     PerfectCacheLineState<ENTRY> line_state;
     line_state.m_permission = AccessPermission_Invalid;
-    line_state.m_entry = ENTRY();
+    uint32_t block_size_bytes = 1 << m_block_size_bits;
+    line_state.m_entry = new ENTRY(block_size_bytes);
     m_map[makeLineAddress(address, m_block_size_bits)] = line_state;
 }
 
@@ -140,7 +141,9 @@
 inline void
 PerfectCacheMemory<ENTRY>::deallocate(Addr address)
 {
-    m_map.erase(makeLineAddress(address, m_block_size_bits));
+    Addr line_addr = makeLineAddress(address, m_block_size_bits);
+    delete m_map[line_addr].m_entry;
+    m_map.erase(line_addr);
 }
 
 // Returns with the physical address of the conflicting cache line
@@ -157,7 +160,7 @@
 inline ENTRY*
 PerfectCacheMemory<ENTRY>::lookup(Addr address)
 {
-    return &m_map[makeLineAddress(address, m_block_size_bits)].m_entry;
+    return m_map[makeLineAddress(address, m_block_size_bits)].m_entry;
 }
 
 // looks an address up in the cache
@@ -165,7 +168,7 @@
 inline const ENTRY*
 PerfectCacheMemory<ENTRY>::lookup(Addr address) const
 {
-    return &m_map[makeLineAddress(address, m_block_size_bits)].m_entry;
+    return m_map[makeLineAddress(address, m_block_size_bits)].m_entry;
 }
 
 template<class ENTRY>