diff -r 80664d8ba364 -r c5f1c3e23df4 src/cpu/o3/comm.hh
--- a/src/cpu/o3/comm.hh	Wed Jan 12 11:10:33 2011 -0600
+++ b/src/cpu/o3/comm.hh	Wed Jan 12 11:10:35 2011 -0600
@@ -87,6 +87,7 @@
 
     bool squash[Impl::MaxThreads];
     bool branchMispredict[Impl::MaxThreads];
+    DynInstPtr mispredictInst[Impl::MaxThreads];
     bool branchTaken[Impl::MaxThreads];
     Addr mispredPC[Impl::MaxThreads];
     TheISA::PCState pc[Impl::MaxThreads];
@@ -107,6 +108,7 @@
 /** Struct that defines all backwards communication. */
 template<class Impl>
 struct TimeBufStruct {
+    typedef typename Impl::DynInstPtr DynInstPtr;
     struct decodeComm {
         bool squash;
         bool predIncorrect;
@@ -117,6 +119,7 @@
         // @todo: Might want to package this kind of branch stuff into a single
         // struct as it is used pretty frequently.
         bool branchMispredict;
+        DynInstPtr mispredictInst;
         bool branchTaken;
         Addr mispredPC;
         TheISA::PCState nextPC;
@@ -156,6 +159,7 @@
         bool robSquashing;
 
         bool branchMispredict;
+        DynInstPtr mispredictInst;
         bool branchTaken;
         Addr mispredPC;
         TheISA::PCState pc;
@@ -175,7 +179,6 @@
         InstSeqNum nonSpecSeqNum;
 
         // Hack for now to send back an uncached access to the IEW stage.
-        typedef typename Impl::DynInstPtr DynInstPtr;
         bool uncached;
         DynInstPtr uncachedLoad;
 
diff -r 80664d8ba364 -r c5f1c3e23df4 src/cpu/o3/commit_impl.hh
--- a/src/cpu/o3/commit_impl.hh	Wed Jan 12 11:10:33 2011 -0600
+++ b/src/cpu/o3/commit_impl.hh	Wed Jan 12 11:10:35 2011 -0600
@@ -520,6 +520,7 @@
     toIEW->commitInfo[tid].robSquashing = true;
 
     toIEW->commitInfo[tid].branchMispredict = false;
+    toIEW->commitInfo[tid].mispredictInst = NULL;
 
     toIEW->commitInfo[tid].pc = pc[tid];
 }
@@ -814,7 +815,8 @@
 
             toIEW->commitInfo[tid].branchMispredict =
                 fromIEW->branchMispredict[tid];
-
+            toIEW->commitInfo[tid].mispredictInst =
+                fromIEW->mispredictInst[tid];
             toIEW->commitInfo[tid].branchTaken =
                 fromIEW->branchTaken[tid];
 
diff -r 80664d8ba364 -r c5f1c3e23df4 src/cpu/o3/fetch_impl.hh
--- a/src/cpu/o3/fetch_impl.hh	Wed Jan 12 11:10:33 2011 -0600
+++ b/src/cpu/o3/fetch_impl.hh	Wed Jan 12 11:10:35 2011 -0600
@@ -902,8 +902,14 @@
                fromCommit->commitInfo[tid].doneSeqNum,
                tid);
 
-        // Also check if there's a mispredict that happened.
-        if (fromCommit->commitInfo[tid].branchMispredict) {
+        // If it was a branch mispredict on a control instruction, update the
+        // branch predictor with that instruction, otherwise just kill the
+        // invalid state we generated in after sequence number
+        assert(!fromCommit->commitInfo[tid].branchMispredict ||
+                fromCommit->commitInfo[tid].mispredictInst);
+
+        if (fromCommit->commitInfo[tid].branchMispredict &&
+            fromCommit->commitInfo[tid].mispredictInst->isControl()) {
             branchPred.squash(fromCommit->commitInfo[tid].doneSeqNum,
                               fromCommit->commitInfo[tid].pc,
                               fromCommit->commitInfo[tid].branchTaken,
diff -r 80664d8ba364 -r c5f1c3e23df4 src/cpu/o3/iew_impl.hh
--- a/src/cpu/o3/iew_impl.hh	Wed Jan 12 11:10:33 2011 -0600
+++ b/src/cpu/o3/iew_impl.hh	Wed Jan 12 11:10:35 2011 -0600
@@ -456,6 +456,7 @@
     toCommit->squashedSeqNum[tid] = inst->seqNum;
     toCommit->mispredPC[tid] = inst->instAddr();
     toCommit->branchMispredict[tid] = true;
+    toCommit->mispredictInst[tid] = inst;
 
     toCommit->branchTaken[tid] = inst->pcState().branching();
     TheISA::PCState pc = inst->pcState();