diff -r f350889142b7 -r fbd113fddc98 src/arch/arm/predecoder.hh
--- a/src/arch/arm/predecoder.hh	Mon Dec 06 15:55:33 2010 -0800
+++ b/src/arch/arm/predecoder.hh	Mon Dec 06 15:55:36 2010 -0800
@@ -67,6 +67,7 @@
         bool outOfBytes;
         int offset;
         ITSTATE itstate;
+        bool preDecoderFlush;
 
       public:
         void reset()
@@ -76,6 +77,7 @@
             emi = 0;
             emiReady = false;
             outOfBytes = true;
+            preDecoderFlush = true;
         }
 
         Predecoder(ThreadContext * _tc) :
diff -r f350889142b7 -r fbd113fddc98 src/arch/arm/predecoder.cc
--- a/src/arch/arm/predecoder.cc	Mon Dec 06 15:55:33 2010 -0800
+++ b/src/arch/arm/predecoder.cc	Mon Dec 06 15:55:36 2010 -0800
@@ -162,9 +162,15 @@
     FPSCR fpscr = tc->readMiscReg(MISCREG_FPSCR);
     emi.fpscrLen = fpscr.len;
     emi.fpscrStride = fpscr.stride;
-    CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
-    itstate.top6 = cpsr.it2;
-    itstate.bottom2 = cpsr.it1;
+
+    if (preDecoderFlush)
+    {
+        CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
+        itstate.top6 = cpsr.it2;
+        itstate.bottom2 = cpsr.it1;
+        preDecoderFlush = false;
+    }
+
     outOfBytes = false;
     process();
 }
diff -r f350889142b7 -r fbd113fddc98 src/cpu/simple/base.cc
--- a/src/cpu/simple/base.cc	Mon Dec 06 15:55:33 2010 -0800
+++ b/src/cpu/simple/base.cc	Mon Dec 06 15:55:36 2010 -0800
@@ -394,6 +394,13 @@
                 curMacroStaticInst = StaticInst::nullStaticInstPtr;
             TheISA::PCState pcState = thread->pcState();
             TheISA::advancePC(pcState, curStaticInst);
+
+            // Reset the predecoder if a control flow change is detected.
+            if (thread->pcState().nextInstAddr() != pcState.nextInstAddr())
+            {
+                predecoder.reset();
+            }
+
             thread->pcState(pcState);
         }
     }