# Node ID 34fcc3f9f957cfb6a9c8e0767a526ad2f71d7cf6 # Parent 8d55f7299d8af4496d99c54e7bfe4f7d3d882117 diff --git a/configs/ruby/MESI_Three_Level.py b/configs/ruby/MESI_Three_Level.py --- a/configs/ruby/MESI_Three_Level.py +++ b/configs/ruby/MESI_Three_Level.py @@ -150,9 +150,13 @@ # Connect the L0 and L1 controllers l0_cntrl.mandatoryQueue = MessageBuffer() l0_cntrl.bufferToL1 = MessageBuffer(ordered = True) - l1_cntrl.bufferFromL0 = l0_cntrl.bufferToL1 + l0_cntrl.bufferToL1.master = ruby_system.network.slave + l1_cntrl.bufferFromL0 = MessageBuffer(ordered = True) + l1_cntrl.bufferFromL0.master = ruby_system.network.slave l0_cntrl.bufferFromL1 = MessageBuffer(ordered = True) - l1_cntrl.bufferToL0 = l0_cntrl.bufferFromL1 + l0_cntrl.bufferFromL1.master = ruby_system.network.slave + l1_cntrl.bufferToL0 = MessageBuffer(ordered = True) + l1_cntrl.bufferToL0.master = ruby_system.network.slave # Connect the L1 controllers and the network l1_cntrl.requestToL2 = MessageBuffer() @@ -291,6 +295,6 @@ all_cntrls = all_cntrls + [io_controller] - ruby_system.network.number_of_virtual_networks = 3 + ruby_system.network.number_of_virtual_networks = 5 topology = create_topology(all_cntrls, options) return (cpu_sequencers, dir_cntrl_nodes, topology) diff --git a/configs/topologies/MeshDirCorners.py b/configs/topologies/MeshDirCorners.py --- a/configs/topologies/MeshDirCorners.py +++ b/configs/topologies/MeshDirCorners.py @@ -53,8 +53,9 @@ dir_nodes = [] dma_nodes = [] for node in nodes: - if node.type == 'L1Cache_Controller' or \ - node.type == 'L2Cache_Controller': + if node.type == 'L0Cache_Controller' or \ + node.type == 'L1Cache_Controller' or \ + node.type == 'L2Cache_Controller': cache_nodes.append(node) elif node.type == 'Directory_Controller': dir_nodes.append(node) diff --git a/src/mem/protocol/MESI_Three_Level-L0cache.sm b/src/mem/protocol/MESI_Three_Level-L0cache.sm --- a/src/mem/protocol/MESI_Three_Level-L0cache.sm +++ b/src/mem/protocol/MESI_Three_Level-L0cache.sm @@ -35,10 +35,12 @@ bool send_evictions; // From this node's L0 cache to the network - MessageBuffer * bufferToL1, network="To"; + MessageBuffer * bufferToL1, network="To", virtual_network="3", + vnet_type="request"; // To this node's L0 cache FROM the network - MessageBuffer * bufferFromL1, network="From"; + MessageBuffer * bufferFromL1, network="From", virtual_network="4", + vnet_type="response"; // Message queue between this controller and the processor MessageBuffer * mandatoryQueue; @@ -259,7 +261,7 @@ in_port(messgeBuffer_in, CoherenceMsg, bufferFromL1, rank = 1) { if (messgeBuffer_in.isReady(clockEdge())) { peek(messgeBuffer_in, CoherenceMsg, block_on="addr") { - assert(in_msg.Dest == machineID); + assert(in_msg.Destination.isElement(machineID)); Entry cache_entry := getCacheEntry(in_msg.addr); TBE tbe := TBEs[in_msg.addr]; @@ -368,10 +370,10 @@ out_msg.addr := address; out_msg.Class := CoherenceClass:GETS; out_msg.Sender := machineID; - out_msg.Dest := createMachineID(MachineType:L1Cache, - machineID.getNum()); + out_msg.Destination.add(createMachineID(MachineType:L1Cache, + machineID.getNum())); DPRINTF(RubySlicc, "address: %#x, destination: %s\n", - address, out_msg.Dest); + address, out_msg.Destination); out_msg.MessageSize := MessageSizeType:Control; out_msg.AccessMode := in_msg.AccessMode; out_msg.DataBlk.alloc(block_size_bytes); @@ -386,11 +388,11 @@ out_msg.Class := CoherenceClass:GETX; out_msg.Sender := machineID; DPRINTF(RubySlicc, "%s\n", machineID); - out_msg.Dest := createMachineID(MachineType:L1Cache, - machineID.getNum()); + out_msg.Destination.add(createMachineID(MachineType:L1Cache, + machineID.getNum())); DPRINTF(RubySlicc, "address: %#x, destination: %s\n", - address, out_msg.Dest); + address, out_msg.Destination); out_msg.MessageSize := MessageSizeType:Control; out_msg.AccessMode := in_msg.AccessMode; out_msg.DataBlk.alloc(block_size_bytes); @@ -404,11 +406,11 @@ out_msg.addr := address; out_msg.Class := CoherenceClass:UPGRADE; out_msg.Sender := machineID; - out_msg.Dest := createMachineID(MachineType:L1Cache, - machineID.getNum()); + out_msg.Destination.add(createMachineID(MachineType:L1Cache, + machineID.getNum())); DPRINTF(RubySlicc, "address: %#x, destination: %s\n", - address, out_msg.Dest); + address, out_msg.Destination); out_msg.MessageSize := MessageSizeType:Control; out_msg.AccessMode := in_msg.AccessMode; out_msg.DataBlk.alloc(block_size_bytes); @@ -424,7 +426,8 @@ out_msg.DataBlk := cache_entry.DataBlk; out_msg.Dirty := cache_entry.Dirty; out_msg.Sender := machineID; - out_msg.Dest := createMachineID(MachineType:L1Cache, machineID.getNum()); + out_msg.Destination.add(createMachineID(MachineType:L1Cache, + machineID.getNum())); out_msg.MessageSize := MessageSizeType:Writeback_Data; } cache_entry.Dirty := false; @@ -436,8 +439,8 @@ out_msg.addr := address; out_msg.Class := CoherenceClass:INV_ACK; out_msg.Sender := machineID; - out_msg.Dest := createMachineID(MachineType:L1Cache, - machineID.getNum()); + out_msg.Destination.add(createMachineID(MachineType:L1Cache, + machineID.getNum())); out_msg.MessageSize := MessageSizeType:Response_Control; out_msg.DataBlk.alloc(block_size_bytes); } @@ -458,7 +461,8 @@ out_msg.Class := CoherenceClass:PUTX; out_msg.Dirty := cache_entry.Dirty; out_msg.Sender:= machineID; - out_msg.Dest := createMachineID(MachineType:L1Cache, machineID.getNum()); + out_msg.Destination.add(createMachineID(MachineType:L1Cache, + machineID.getNum())); if (cache_entry.Dirty) { out_msg.MessageSize := MessageSizeType:Writeback_Data; diff --git a/src/mem/protocol/MESI_Three_Level-L1cache.sm b/src/mem/protocol/MESI_Three_Level-L1cache.sm --- a/src/mem/protocol/MESI_Three_Level-L1cache.sm +++ b/src/mem/protocol/MESI_Three_Level-L1cache.sm @@ -36,10 +36,12 @@ // Message Buffers between the L1 and the L0 Cache // From the L1 cache to the L0 cache - MessageBuffer * bufferToL0, network="To"; + MessageBuffer * bufferToL0, network="To", virtual_network="4", + vnet_type="response"; // From the L0 cache to the L1 cache - MessageBuffer * bufferFromL0, network="From"; + MessageBuffer * bufferFromL0, network="From", virtual_network="3", + vnet_type="request"; // Message queue from this L1 cache TO the network / L2 MessageBuffer * requestToL2, network="To", virtual_network="0", @@ -553,8 +555,8 @@ out_msg.addr := address; out_msg.Class := CoherenceClass:INV; out_msg.Sender := machineID; - out_msg.Dest := createMachineID(MachineType:L0Cache, - machineID.getNum()); + out_msg.Destination.add(createMachineID(MachineType:L0Cache, + machineID.getNum())); out_msg.MessageSize := MessageSizeType:Control; out_msg.DataBlk.alloc(block_size_bytes); } @@ -613,8 +615,8 @@ out_msg.addr := address; out_msg.Class := CoherenceClass:DATA; out_msg.Sender := machineID; - out_msg.Dest := createMachineID(MachineType:L0Cache, - machineID.getNum()); + out_msg.Destination.add(createMachineID(MachineType:L0Cache, + machineID.getNum())); out_msg.DataBlk := cache_entry.DataBlk; out_msg.MessageSize := MessageSizeType:Response_Data; } @@ -627,8 +629,8 @@ out_msg.addr := address; out_msg.Class := CoherenceClass:DATA_EXCLUSIVE; out_msg.Sender := machineID; - out_msg.Dest := createMachineID(MachineType:L0Cache, - machineID.getNum()); + out_msg.Destination.add(createMachineID(MachineType:L0Cache, + machineID.getNum())); out_msg.DataBlk := cache_entry.DataBlk; out_msg.Dirty := cache_entry.Dirty; out_msg.MessageSize := MessageSizeType:Response_Data; diff --git a/src/mem/protocol/MESI_Three_Level-msg.sm b/src/mem/protocol/MESI_Three_Level-msg.sm --- a/src/mem/protocol/MESI_Three_Level-msg.sm +++ b/src/mem/protocol/MESI_Three_Level-msg.sm @@ -54,7 +54,7 @@ CoherenceClass Class, desc="Type of message (GetS, GetX, PutX, etc)"; RubyAccessMode AccessMode, desc="user/supervisor access type"; MachineID Sender, desc="What component sent this message"; - MachineID Dest, desc="What machine receives this message"; + NetDest Destination, desc="What machine receives this message"; MessageSizeType MessageSize, desc="size category of the message"; DataBlock DataBlk, desc="Data for the cache line (if PUTX)"; bool Dirty, default="false", desc="Dirty bit";