# Node ID 3e0817967515e82116555eb6cfc358d4fdb36c56
# Parent  b31738224fb0eb259efc25f6d6efab5a962f29d0
diff --git a/src/arch/hsail/gen.py b/src/arch/hsail/gen.py
--- a/src/arch/hsail/gen.py
+++ b/src/arch/hsail/gen.py
@@ -791,6 +791,52 @@
 } // namespace HsailISA
 ''')
 
+exec_code('''
+template<>
+void
+Abs<U32>::execute(GPUDynInstPtr gpuDynInst)
+{
+    Wavefront *w = gpuDynInst->wavefront();
+
+    const VectorMask &mask = w->get_pred();
+
+    for (int lane = 0; lane < VSZ; ++lane) {
+        if (mask[lane]) {
+            CType dest_val;
+            CType src_val;
+
+            src_val = this->src[0].template get<CType>(w, lane);
+
+            dest_val = (CType)(src_val);
+
+            this->dest.set(w, lane, dest_val);
+        }
+    }
+}
+
+template<>
+void
+Abs<U64>::execute(GPUDynInstPtr gpuDynInst)
+{
+    Wavefront *w = gpuDynInst->wavefront();
+
+    const VectorMask &mask = w->get_pred();
+
+    for (int lane = 0; lane < VSZ; ++lane) {
+        if (mask[lane]) {
+            CType dest_val;
+            CType src_val;
+
+            src_val = this->src[0].template get<CType>(w, lane);
+
+            dest_val = (CType)(src_val);
+
+            this->dest.set(w, lane, dest_val);
+        }
+    }
+}
+''')
+
 exec_code.dedent()
 exec_code('''
 } // namespace HsailISA
diff --git a/src/gpu-compute/gpu_static_inst.hh b/src/gpu-compute/gpu_static_inst.hh
--- a/src/gpu-compute/gpu_static_inst.hh
+++ b/src/gpu-compute/gpu_static_inst.hh
@@ -127,7 +127,6 @@
     // For flat memory accesses
     Enums::StorageClassType executed_as;
 
-  protected:
     virtual void
     execLdAcq(GPUDynInstPtr gpuDynInst)
     {
@@ -152,6 +151,7 @@
         fatal("calling execAtomicAcq() on a non-atomic instruction.\n");
     }
 
+  protected:
     const std::string opcode;
     std::string disassembly;
     int _instNum;