diff -r 1069ee6b7716 -r 742edaa484a1 src/mem/cache/cache.cc
--- a/src/mem/cache/cache.cc	Wed Apr 20 18:17:52 2016 +0100
+++ b/src/mem/cache/cache.cc	Wed Apr 20 18:17:54 2016 +0100
@@ -1226,18 +1226,6 @@
 void
 Cache::handleUncacheableWriteResp(PacketPtr pkt)
 {
-    WriteQueueEntry *wq_entry =
-        dynamic_cast<WriteQueueEntry*>(pkt->popSenderState());
-    assert(wq_entry);
-
-    WriteQueueEntry::Target *target = wq_entry->getTarget();
-
-    int stats_cmd_idx = target->cmd.toInt();
-    Tick miss_latency = curTick() - target->recvTime;
-    assert(pkt->req->masterId() < system->maxMasters());
-    mshr_uncacheable_lat[stats_cmd_idx][pkt->req->masterId()] +=
-        miss_latency;
-
     Tick completion_time = clockEdge(responseLatency) +
         pkt->headerDelay + pkt->payloadDelay;
 
@@ -1245,16 +1233,6 @@
     pkt->headerDelay = pkt->payloadDelay = 0;
 
     cpuSidePort->schedTimingResp(pkt, completion_time, true);
-
-    wq_entry->popTarget();
-    assert(!wq_entry->hasTargets());
-
-    bool wasFull = writeBuffer.isFull();
-    writeBuffer.deallocate(wq_entry);
-
-    if (wasFull && !writeBuffer.isFull()) {
-        clearBlocked(Blocked_NoWBBuffers);
-    }
 }
 
 void
@@ -2238,12 +2216,8 @@
     WriteQueueEntry *wq_entry = writeBuffer.getNext();
 
     // If we got a write buffer request ready, first priority is a
-    // full write buffer (but only if we have no uncacheable write
-    // responses outstanding, possibly revisit this last part),
-    // otherwhise we favour the miss requests
-    if (wq_entry &&
-        ((writeBuffer.isFull() && writeBuffer.numInService() == 0) ||
-         !miss_mshr)) {
+    // full write buffer, otherwhise we favour the miss requests
+    if (wq_entry && (writeBuffer.isFull() || !miss_mshr)) {
         // need to search MSHR queue for conflicting earlier miss.
         MSHR *conflict_mshr =
             mshrQueue.findPending(wq_entry->blkAddr,
@@ -2492,12 +2466,7 @@
             tgt_pkt->getSize());
 
     // forward as is, both for evictions and uncacheable writes
-    tgt_pkt->pushSenderState(wq_entry);
-
     if (!memSidePort->sendTimingReq(tgt_pkt)) {
-        // undo the addition of the sender state
-        tgt_pkt->popSenderState();
-
         // note that we have now masked any requestBus and
         // schedSendEvent (we will wait for a retry before
         // doing anything), and this is so even if we do not
diff -r 1069ee6b7716 -r 742edaa484a1 src/mem/cache/write_queue.cc
--- a/src/mem/cache/write_queue.cc	Wed Apr 20 18:17:52 2016 +0100
+++ b/src/mem/cache/write_queue.cc	Wed Apr 20 18:17:54 2016 +0100
@@ -75,17 +75,10 @@
 void
 WriteQueue::markInService(WriteQueueEntry *entry)
 {
-    if (!entry->isUncacheable()) {
-        // a normal eviction, such as a writeback or a clean evict, no
-        // more to do as we are done from the perspective of this
-        // cache
-        entry->popTarget();
-        deallocate(entry);
-    } else {
-        // uncacheable write, and we will eventually receive a
-        // response
-        entry->markInService();
-        readyList.erase(entry->readyIter);
-        _numInService += 1;
-    }
+    // for a normal eviction, such as a writeback or a clean evict,
+    // there is no more to do as we are done from the perspective of
+    // this cache, and for uncacheable write we do not need the entry
+    // as part of the response handling
+    entry->popTarget();
+    deallocate(entry);
 }
diff -r 1069ee6b7716 -r 742edaa484a1 src/mem/cache/write_queue_entry.hh
--- a/src/mem/cache/write_queue_entry.hh	Wed Apr 20 18:17:52 2016 +0100
+++ b/src/mem/cache/write_queue_entry.hh	Wed Apr 20 18:17:54 2016 +0100
@@ -78,11 +78,10 @@
         const Tick readyTime; //!< Time when request is ready to be serviced
         const Counter order;  //!< Global order (for memory consistency mgmt)
         const PacketPtr pkt;  //!< Pending request packet.
-        const MemCmd cmd;     //!< Command as first seen by the cache
 
         Target(PacketPtr _pkt, Tick _readyTime, Counter _order)
             : recvTime(curTick()), readyTime(_readyTime), order(_order),
-              pkt(_pkt), cmd(pkt->cmd)
+              pkt(_pkt)
         {}
     };
 
@@ -137,7 +136,6 @@
     void allocate(Addr blk_addr, unsigned blk_size, PacketPtr pkt,
                   Tick when_ready, Counter _order);
 
-    bool markInService();
 
     /**
      * Mark this entry as free.
diff -r 1069ee6b7716 -r 742edaa484a1 src/mem/cache/write_queue_entry.cc
--- a/src/mem/cache/write_queue_entry.cc	Wed Apr 20 18:17:52 2016 +0100
+++ b/src/mem/cache/write_queue_entry.cc	Wed Apr 20 18:17:54 2016 +0100
@@ -118,23 +118,6 @@
     targets.add(target, when_ready, _order);
 }
 
-bool
-WriteQueueEntry::markInService()
-{
-    assert(!inService);
-    if (!isUncacheable()) {
-        // we just forwarded the request packet & don't expect a
-        // response, so get rid of it
-        assert(getNumTargets() == 1);
-        popTarget();
-        return true;
-    }
-
-    inService = true;
-
-    return false;
-}
-
 void
 WriteQueueEntry::deallocate()
 {