diff -r 7ed9924b3f8b -r 851275763963 src/arch/arm/insts/macromem.cc
--- a/src/arch/arm/insts/macromem.cc	Mon Dec 06 15:57:53 2010 -0800
+++ b/src/arch/arm/insts/macromem.cc	Mon Dec 06 15:58:54 2010 -0800
@@ -42,7 +42,9 @@
 
 #include "arch/arm/insts/macromem.hh"
 #include "arch/arm/decoder.hh"
+#include <sstream>
 
+using namespace std;
 using namespace ArmISAInst;
 
 namespace ArmISA
@@ -180,7 +182,7 @@
                 size, machInst, rMid, rn, 0, align);
         break;
       default:
-        panic("Unrecognized number of registers %d.\n", regs);
+        microOps[uopIdx++] = new Unknown(machInst);
     }
     if (wb) {
         if (rm != 15 && rm != 13) {
@@ -216,7 +218,7 @@
             }
             break;
           default:
-            panic("Bad number of elements to deinterleave %d.\n", elems);
+            microOps[uopIdx++] = new Unknown(machInst);
         }
     }
     assert(uopIdx == numMicroops);
@@ -315,7 +317,7 @@
                 machInst, ufp0, rn, 0, align);
         break;
       default:
-        panic("Unrecognized load size %d.\n", regs);
+        microOps[uopIdx++] = new Unknown(machInst);
     }
     if (wb) {
         if (rm != 15 && rm != 13) {
@@ -358,7 +360,7 @@
             }
             break;
           default:
-            panic("Bad size %d.\n", size);
+            microOps[uopIdx++] = new Unknown(machInst);
             break;
         }
         break;
@@ -393,7 +395,7 @@
             }
             break;
           default:
-            panic("Bad size %d.\n", size);
+            microOps[uopIdx++] = new Unknown(machInst);
             break;
         }
         break;
@@ -429,7 +431,7 @@
             }
             break;
           default:
-            panic("Bad size %d.\n", size);
+            microOps[uopIdx++] = new Unknown(machInst);
             break;
         }
         break;
@@ -472,13 +474,13 @@
                 }
                 break;
               default:
-                panic("Bad size %d.\n", size);
+                microOps[uopIdx++] = new Unknown(machInst);
                 break;
             }
         }
         break;
       default:
-        panic("Bad number of elements to unpack %d.\n", elems);
+        microOps[uopIdx++] = new Unknown(machInst);
     }
     assert(uopIdx == numMicroops);
 
@@ -536,7 +538,7 @@
             }
             break;
           default:
-            panic("Bad number of elements to interleave %d.\n", elems);
+            microOps[uopIdx++] = new Unknown(machInst);
         }
     }
     switch (regs) {
@@ -561,7 +563,7 @@
                 size, machInst, rMid, rn, 0, align);
         break;
       default:
-        panic("Unrecognized number of registers %d.\n", regs);
+        microOps[uopIdx++] = new Unknown(machInst);
     }
     if (wb) {
         if (rm != 15 && rm != 13) {
@@ -627,7 +629,7 @@
                     machInst, ufp0, vd * 2, inc * 2, lane);
             break;
           default:
-            panic("Bad size %d.\n", size);
+            microOps[uopIdx++] = new Unknown(machInst);
             break;
         }
         break;
@@ -647,7 +649,7 @@
                     machInst, ufp0, vd * 2, inc * 2, lane);
             break;
           default:
-            panic("Bad size %d.\n", size);
+            microOps[uopIdx++] = new Unknown(machInst);
             break;
         }
         break;
@@ -668,7 +670,7 @@
                     machInst, ufp0, vd * 2, inc * 2, lane);
             break;
           default:
-            panic("Bad size %d.\n", size);
+            microOps[uopIdx++] = new Unknown(machInst);
             break;
         }
         break;
@@ -690,13 +692,13 @@
                         machInst, ufp0, (vd + offset) * 2, inc * 2, lane);
                 break;
               default:
-                panic("Bad size %d.\n", size);
+                microOps[uopIdx++] = new Unknown(machInst);
                 break;
             }
         }
         break;
       default:
-        panic("Bad number of elements to pack %d.\n", elems);
+        microOps[uopIdx++] = new Unknown(machInst);
     }
     switch (storeSize) {
       case 1:
@@ -757,7 +759,7 @@
                 machInst, ufp0, rn, 0, align);
         break;
       default:
-        panic("Unrecognized store size %d.\n", regs);
+        microOps[uopIdx++] = new Unknown(machInst);
     }
     if (wb) {
         if (rm != 15 && rm != 13) {
diff -r 7ed9924b3f8b -r 851275763963 src/arch/arm/insts/pred_inst.hh
--- a/src/arch/arm/insts/pred_inst.hh	Mon Dec 06 15:57:53 2010 -0800
+++ b/src/arch/arm/insts/pred_inst.hh	Mon Dec 06 15:58:54 2010 -0800
@@ -78,9 +78,10 @@
 }
 
 static inline uint64_t
-simd_modified_imm(bool op, uint8_t cmode, uint8_t data)
+simd_modified_imm(bool op, uint8_t cmode, uint8_t data, bool &immValid)
 {
     uint64_t bigData = data;
+    immValid = true;
     switch (cmode) {
       case 0x0:
       case 0x1:
@@ -139,9 +140,10 @@
             bigData |= (bigData << 32);
             break;
         }
-        // Fall through
+        // Fall through, immediate encoding is invalid.
       default:
-        panic("Illegal modified SIMD immediate parameters.\n");
+        immValid = false;
+        break;
     }
     return bigData;
 }
diff -r 7ed9924b3f8b -r 851275763963 src/arch/arm/isa/formats/fp.isa
--- a/src/arch/arm/isa/formats/fp.isa	Mon Dec 06 15:57:53 2010 -0800
+++ b/src/arch/arm/isa/formats/fp.isa	Mon Dec 06 15:58:54 2010 -0800
@@ -758,7 +758,17 @@
                                       bits(machInst, 24)) << 7) |
                             (bits(machInst, 18, 16) << 4) |
                             (bits(machInst, 3, 0) << 0);
-        const uint64_t bigImm = simd_modified_imm(op, cmode, imm);
+
+        /* It is possible to have invalid immediate encodings,
+         * in those cases return an unknown op.
+         */
+        bool immValid = true;
+        const uint64_t bigImm = simd_modified_imm(op, cmode, imm, immValid);
+        if (!immValid)
+        {
+            return new Unknown(machInst);
+        }
+
         if (op) {
             if (bits(cmode, 3) == 0) {
                 if (bits(cmode, 0) == 0) {
diff -r 7ed9924b3f8b -r 851275763963 src/arch/arm/isa/formats/misc.isa
--- a/src/arch/arm/isa/formats/misc.isa	Mon Dec 06 15:57:53 2010 -0800
+++ b/src/arch/arm/isa/formats/misc.isa	Mon Dec 06 15:58:54 2010 -0800
@@ -100,7 +100,10 @@
           case MISCREG_NOP:
             return new NopInst(machInst);
           case NUM_MISCREGS:
-            return new Unknown(machInst);
+            return new FailUnimplemented(
+                    csprintf("miscreg crn:%d opc1:%d crm:%d opc2:%d %s unknown",
+                    crn, opc1, crm, opc2, isRead ? "read" : "write").c_str(),
+                    machInst);
           case MISCREG_DCCISW:
             return new WarnUnimplemented(
                     isRead ? "mrc dccisw" : "mcr dcisw", machInst);
diff -r 7ed9924b3f8b -r 851275763963 src/arch/arm/isa/insts/neon.isa
--- a/src/arch/arm/isa/insts/neon.isa	Mon Dec 06 15:57:53 2010 -0800
+++ b/src/arch/arm/isa/insts/neon.isa	Mon Dec 06 15:58:54 2010 -0800
@@ -871,14 +871,22 @@
         if readDest:
             readDestCode = 'destElem = gtoh(destReg.elements[i]);'
         eWalkCode += '''
-        assert(imm >= 0 && imm < eCount);
-        for (unsigned i = 0; i < eCount; i++) {
-            Element srcElem1 = gtoh(srcReg1.elements[i]);
-            Element srcElem2 = gtoh(srcReg2.elements[imm]);
-            Element destElem;
-            %(readDest)s
-            %(op)s
-            destReg.elements[i] = htog(destElem);
+        //assert(imm >= 0 && imm < eCount);
+        if (imm < 0 && imm >= eCount) {
+#if FULL_SYSTEM
+            fault = new UndefinedInstruction;
+#else
+            fault = new UndefinedInstruction(false, mnemonic);
+#endif
+        } else {
+            for (unsigned i = 0; i < eCount; i++) {
+                Element srcElem1 = gtoh(srcReg1.elements[i]);
+                Element srcElem2 = gtoh(srcReg2.elements[imm]);
+                Element destElem;
+                %(readDest)s
+                %(op)s
+                destReg.elements[i] = htog(destElem);
+            }
         }
         ''' % { "op" : op, "readDest" : readDestCode }
         for reg in range(rCount):
@@ -919,14 +927,22 @@
         if readDest:
             readDestCode = 'destElem = gtoh(destReg.elements[i]);'
         eWalkCode += '''
-        assert(imm >= 0 && imm < eCount);
-        for (unsigned i = 0; i < eCount; i++) {
-            Element srcElem1 = gtoh(srcReg1.elements[i]);
-            Element srcElem2 = gtoh(srcReg2.elements[imm]);
-            BigElement destElem;
-            %(readDest)s
-            %(op)s
-            destReg.elements[i] = htog(destElem);
+        //assert(imm >= 0 && imm < eCount);
+        if (imm < 0 && imm >= eCount) {
+#if FULL_SYSTEM
+            fault = new UndefinedInstruction;
+#else
+            fault = new UndefinedInstruction(false, mnemonic);
+#endif
+        } else {
+            for (unsigned i = 0; i < eCount; i++) {
+                Element srcElem1 = gtoh(srcReg1.elements[i]);
+                Element srcElem2 = gtoh(srcReg2.elements[imm]);
+                BigElement destElem;
+                %(readDest)s
+                %(op)s
+                destReg.elements[i] = htog(destElem);
+            }
         }
         ''' % { "op" : op, "readDest" : readDestCode }
         for reg in range(2 * rCount):
@@ -965,14 +981,21 @@
         if readDest:
             readDestCode = 'destReg = destRegs[i];'
         eWalkCode += '''
-        assert(imm >= 0 && imm < rCount);
-        for (unsigned i = 0; i < rCount; i++) {
-            FloatReg srcReg1 = srcRegs1[i];
-            FloatReg srcReg2 = srcRegs2[imm];
-            FloatReg destReg;
-            %(readDest)s
-            %(op)s
-            destRegs[i] = destReg;
+        if (imm < 0 && imm >= eCount) {
+#if FULL_SYSTEM
+            fault = new UndefinedInstruction;
+#else
+            fault = new UndefinedInstruction(false, mnemonic);
+#endif
+        } else {
+            for (unsigned i = 0; i < rCount; i++) {
+                FloatReg srcReg1 = srcRegs1[i];
+                FloatReg srcReg2 = srcRegs2[imm];
+                FloatReg destReg;
+                %(readDest)s
+                %(op)s
+                destRegs[i] = destReg;
+            }
         }
         ''' % { "op" : op, "readDest" : readDestCode }
         for reg in range(rCount):
@@ -3277,8 +3300,14 @@
                 destReg.elements[i] = srcReg1.elements[index];
             } else {
                 index -= eCount;
-                assert(index < eCount);
-                destReg.elements[i] = srcReg2.elements[index];
+                if (index >= eCount)
+#if FULL_SYSTEM
+                    fault = new UndefinedInstruction;
+#else
+                    fault = new UndefinedInstruction(false, mnemonic);
+#endif
+                else
+                    destReg.elements[i] = srcReg2.elements[index];
             }
         }
     '''
diff -r 7ed9924b3f8b -r 851275763963 src/arch/arm/miscregs.cc
--- a/src/arch/arm/miscregs.cc	Mon Dec 06 15:57:53 2010 -0800
+++ b/src/arch/arm/miscregs.cc	Mon Dec 06 15:58:54 2010 -0800
@@ -451,8 +451,6 @@
         // Implementation defined
         break;
     }
-    warn("Unknown miscreg: CRn: %d Opc1: %d CRm: %d opc2: %d\n",
-            crn, opc1, crm, opc2);
     // Unrecognized register
     return NUM_MISCREGS;
 }