diff -r fc247b9c42b6 -r 51dec612f11b src/arch/x86/tlb.hh --- a/src/arch/x86/tlb.hh Thu May 19 15:19:35 2016 -0500 +++ b/src/arch/x86/tlb.hh Fri May 20 16:23:14 2016 -0500 @@ -74,7 +74,7 @@ typedef X86TLBParams Params; TLB(const Params *p); - void takeOverFrom(BaseTLB *otlb) override {} + void takeOverFrom(BaseTLB *otlb) override; TlbEntry *lookup(Addr va, bool update_lru = true); diff -r fc247b9c42b6 -r 51dec612f11b src/arch/x86/tlb.cc --- a/src/arch/x86/tlb.cc Thu May 19 15:19:35 2016 -0500 +++ b/src/arch/x86/tlb.cc Fri May 20 16:23:14 2016 -0500 @@ -120,6 +120,32 @@ return newEntry; } +void +TLB::takeOverFrom(BaseTLB *otlb) +{ + TLB *old = dynamic_cast(otlb); + fatal_if(!old, "Invalid TLB type to takeOverFrom.\n"); + fatal_if(size != old->size, "Cannot takeOverFrom different size TLB.\n"); + + flushAll(); + trie.clear(); + + for (int i = 0; i < size; i++) { + if (old->tlb[i].trieHandle) { + TlbEntry *entry = freeList.front(); + freeList.pop_front(); + + // Copy over all of the entries information + *entry = old->tlb[i]; + + entry->trieHandle = trie.insert(entry->vaddr, + TlbEntryTrie::MaxBits - entry->logBytes, entry); + } + } + + lruSeq = old->lruSeq; +} + TlbEntry * TLB::lookup(Addr va, bool update_lru) { diff -r fc247b9c42b6 -r 51dec612f11b src/cpu/base.cc --- a/src/cpu/base.cc Thu May 19 15:19:35 2016 -0500 +++ b/src/cpu/base.cc Fri May 20 16:23:14 2016 -0500 @@ -479,10 +479,6 @@ _switchedOut = true; if (profileEvent && profileEvent->scheduled()) deschedule(profileEvent); - - // Flush all TLBs in the CPU to avoid having stale translations if - // it gets switched in later. - flushTLBs(); } void @@ -538,7 +534,11 @@ old_dtb_port->unbind(); new_dtb_port->bind(slavePort); } + // Flush all TLBs in the CPU to avoid having stale translations if + // it was switched out previously. + newTC->getITBPtr()->flushAll(); newTC->getITBPtr()->takeOverFrom(oldTC->getITBPtr()); + newTC->getDTBPtr()->flushAll(); newTC->getDTBPtr()->takeOverFrom(oldTC->getDTBPtr()); // Checker whether or not we have to transfer CheckerCPU