diff -r fc247b9c42b6 src/arch/arm/pmu.cc
--- a/src/arch/arm/pmu.cc	Thu May 19 15:19:35 2016 -0500
+++ b/src/arch/arm/pmu.cc	Mon May 23 15:35:02 2016 +0200
@@ -113,7 +113,9 @@
     DPRINTF(PMUVerbose, "setMiscReg(%s, 0x%x)\n",
             miscRegName[unflattenMiscReg(misc_reg)], val);
 
-    switch (unflattenMiscReg(misc_reg)) {
+    misc_reg = unflattenMiscReg(misc_reg);
+
+    switch (misc_reg) {
       case MISCREG_PMCR_EL0:
       case MISCREG_PMCR:
         setControlReg(val);
@@ -152,6 +154,9 @@
 
       case MISCREG_PMSELR_EL0:
       case MISCREG_PMSELR:
+        DPRINTF(PMUVerbose, "Setting counter type: "
+                "[PMSELR: 0x%x, PMSELER.sel: 0x%x, EVTYPER: 0x%x]\n",
+                reg_pmselr, reg_pmselr.sel, val);
         reg_pmselr = val;
         return;
 
@@ -163,7 +168,7 @@
         return;
 
       case MISCREG_PMEVTYPER0_EL0...MISCREG_PMEVTYPER5_EL0:
-        setCounterTypeRegister(misc_reg - MISCREG_PMEVCNTR0_EL0, val);
+        setCounterTypeRegister(misc_reg - MISCREG_PMEVTYPER0_EL0, val);
         return;
 
       case MISCREG_PMCCFILTR:
@@ -252,6 +257,7 @@
       case MISCREG_PMSWINC: // Software Increment Register (RAZ)
         return 0;
 
+      case MISCREG_PMSELR_EL0:
       case MISCREG_PMSELR:
         return reg_pmselr;