diff -r 4aac82f10951 -r 9dba209f1590 src/mem/cache/tags/base.cc
--- a/src/mem/cache/tags/base.cc	Thu Jul 21 17:19:18 2016 +0100
+++ b/src/mem/cache/tags/base.cc	Mon Oct 24 16:21:42 2016 +0200
@@ -56,7 +56,11 @@
 
 BaseTags::BaseTags(const Params *p)
     : ClockedObject(p), blkSize(p->block_size), size(p->size),
-      accessLatency(p->hit_latency), cache(nullptr), warmupBound(0),
+      lookupLatency(p->tag_latency),
+      accessLatency(p->sequential_access ?
+                    p->tag_latency + p->data_latency :
+                    std::max(p->tag_latency, p->data_latency)),
+      cache(nullptr), warmupBound(0),
       warmedUp(false), numBlocks(0)
 {
 }
diff -r 4aac82f10951 -r 9dba209f1590 src/mem/cache/tags/base_set_assoc.hh
--- a/src/mem/cache/tags/base_set_assoc.hh	Thu Jul 21 17:19:18 2016 +0100
+++ b/src/mem/cache/tags/base_set_assoc.hh	Mon Oct 24 16:21:42 2016 +0200
@@ -208,7 +208,6 @@
         Addr tag = extractTag(addr);
         int set = extractSet(addr);
         BlkType *blk = sets[set].findBlk(tag, is_secure);
-        lat = accessLatency;;
 
         // Access all tags in parallel, hence one in each way.  The data side
         // either accesses all blocks in parallel, or one block sequentially on
@@ -223,12 +222,17 @@
         }
 
         if (blk != nullptr) {
+            // If a cache hit
+            lat = accessLatency;
             if (blk->whenReady > curTick()
                 && cache->ticksToCycles(blk->whenReady - curTick())
                 > accessLatency) {
                 lat = cache->ticksToCycles(blk->whenReady - curTick());
             }
             blk->refCount += 1;
+        } else {
+            // If a cache miss
+            lat = lookupLatency;
         }
 
         return blk;
diff -r 4aac82f10951 -r 9dba209f1590 src/mem/cache/tags/fa_lru.cc
--- a/src/mem/cache/tags/fa_lru.cc	Thu Jul 21 17:19:18 2016 +0100
+++ b/src/mem/cache/tags/fa_lru.cc	Mon Oct 24 16:21:42 2016 +0200
@@ -186,6 +186,8 @@
     FALRUBlk* blk = hashLookup(blkAddr);
 
     if (blk && blk->isValid()) {
+        // If a cache hit
+        lat = accessLatency;
         assert(blk->tag == blkAddr);
         tmp_in_cache = blk->inCache;
         for (unsigned i = 0; i < numCaches; i++) {
@@ -200,6 +202,8 @@
             moveToHead(blk);
         }
     } else {
+        // If a cache miss
+        lat = lookupLatency;
         blk = nullptr;
         for (unsigned i = 0; i <= numCaches; ++i) {
             misses[i]++;
@@ -209,7 +213,6 @@
         *inCache = tmp_in_cache;
     }
 
-    lat = accessLatency;
     //assert(check());
     return blk;
 }
diff -r 4aac82f10951 -r 9dba209f1590 configs/common/Caches.py
--- a/configs/common/Caches.py	Thu Jul 21 17:19:18 2016 +0100
+++ b/configs/common/Caches.py	Mon Oct 24 16:21:42 2016 +0200
@@ -48,7 +48,8 @@
 
 class L1Cache(Cache):
     assoc = 2
-    hit_latency = 2
+    tag_latency = 2
+    data_latency = 2
     response_latency = 2
     mshrs = 4
     tgts_per_mshr = 20
@@ -63,7 +64,8 @@
 
 class L2Cache(Cache):
     assoc = 8
-    hit_latency = 20
+    tag_latency = 20
+    data_latency = 20
     response_latency = 20
     mshrs = 20
     tgts_per_mshr = 12
@@ -71,7 +73,8 @@
 
 class IOCache(Cache):
     assoc = 8
-    hit_latency = 50
+    tag_latency = 50
+    data_latency = 50
     response_latency = 50
     mshrs = 20
     size = '1kB'
@@ -79,7 +82,8 @@
 
 class PageTableWalkerCache(Cache):
     assoc = 2
-    hit_latency = 2
+    tag_latency = 2
+    data_latency = 2
     response_latency = 2
     mshrs = 10
     size = '1kB'
diff -r 4aac82f10951 -r 9dba209f1590 configs/common/O3_ARM_v7a.py
--- a/configs/common/O3_ARM_v7a.py	Thu Jul 21 17:19:18 2016 +0100
+++ b/configs/common/O3_ARM_v7a.py	Mon Oct 24 16:21:42 2016 +0200
@@ -143,7 +143,8 @@
 
 # Instruction Cache
 class O3_ARM_v7a_ICache(Cache):
-    hit_latency = 1
+    tag_latency = 1
+    data_latency = 1
     response_latency = 1
     mshrs = 2
     tgts_per_mshr = 8
@@ -155,7 +156,8 @@
 
 # Data Cache
 class O3_ARM_v7a_DCache(Cache):
-    hit_latency = 2
+    tag_latency = 2
+    data_latency = 2
     response_latency = 2
     mshrs = 6
     tgts_per_mshr = 8
@@ -168,7 +170,8 @@
 # TLB Cache
 # Use a cache as a L2 TLB
 class O3_ARM_v7aWalkCache(Cache):
-    hit_latency = 4
+    tag_latency = 4
+    data_latency = 4
     response_latency = 4
     mshrs = 6
     tgts_per_mshr = 8
@@ -181,7 +184,8 @@
 
 # L2 Cache
 class O3_ARM_v7aL2(Cache):
-    hit_latency = 12
+    tag_latency = 12
+    data_latency = 12
     response_latency = 12
     mshrs = 16
     tgts_per_mshr = 8
diff -r 4aac82f10951 -r 9dba209f1590 configs/example/arm/devices.py
--- a/configs/example/arm/devices.py	Thu Jul 21 17:19:18 2016 +0100
+++ b/configs/example/arm/devices.py	Mon Oct 24 16:21:42 2016 +0200
@@ -44,7 +44,8 @@
 from Caches import *
 
 class L1I(L1_ICache):
-    hit_latency = 1
+    tag_latency = 1
+    data_latency = 1
     response_latency = 1
     mshrs = 4
     tgts_per_mshr = 8
@@ -53,7 +54,8 @@
 
 
 class L1D(L1_DCache):
-    hit_latency = 2
+    tag_latency = 2
+    data_latency = 2
     response_latency = 1
     mshrs = 16
     tgts_per_mshr = 16
@@ -63,7 +65,8 @@
 
 
 class WalkCache(PageTableWalkerCache):
-    hit_latency = 4
+    tag_latency = 4
+    data_latency = 4
     response_latency = 4
     mshrs = 6
     tgts_per_mshr = 8
@@ -73,7 +76,8 @@
 
 
 class L2(L2Cache):
-    hit_latency = 12
+    tag_latency = 12
+    data_latency = 12
     response_latency = 5
     mshrs = 32
     tgts_per_mshr = 8
@@ -86,7 +90,8 @@
 class L3(Cache):
     size = '16MB'
     assoc = 16
-    hit_latency = 20
+    tag_latency = 20
+    data_latency = 20
     response_latency = 20
     mshrs = 20
     tgts_per_mshr = 12
diff -r 4aac82f10951 -r 9dba209f1590 configs/learning_gem5/part1/caches.py
--- a/configs/learning_gem5/part1/caches.py	Thu Jul 21 17:19:18 2016 +0100
+++ b/configs/learning_gem5/part1/caches.py	Mon Oct 24 16:21:42 2016 +0200
@@ -45,7 +45,8 @@
     """Simple L1 Cache with default values"""
 
     assoc = 2
-    hit_latency = 2
+    tag_latency = 2
+    data_latency = 2
     response_latency = 2
     mshrs = 4
     tgts_per_mshr = 20
@@ -107,7 +108,8 @@
     # Default parameters
     size = '256kB'
     assoc = 8
-    hit_latency = 20
+    tag_latency = 20
+    data_latency = 20
     response_latency = 20
     mshrs = 20
     tgts_per_mshr = 12
diff -r 4aac82f10951 -r 9dba209f1590 src/mem/cache/Cache.py
--- a/src/mem/cache/Cache.py	Thu Jul 21 17:19:18 2016 +0100
+++ b/src/mem/cache/Cache.py	Mon Oct 24 16:21:42 2016 +0200
@@ -53,7 +53,8 @@
     size = Param.MemorySize("Capacity")
     assoc = Param.Unsigned("Associativity")
 
-    hit_latency = Param.Cycles("Hit latency")
+    tag_latency = Param.Cycles("Tag lookup latency")
+    data_latency = Param.Cycles("Data access latency")
     response_latency = Param.Cycles("Latency for the return path on a miss");
 
     max_miss_count = Param.Counter(0,
diff -r 4aac82f10951 -r 9dba209f1590 src/mem/cache/base.hh
--- a/src/mem/cache/base.hh	Thu Jul 21 17:19:18 2016 +0100
+++ b/src/mem/cache/base.hh	Mon Oct 24 16:21:42 2016 +0200
@@ -265,6 +265,12 @@
     const Cycles lookupLatency;
 
     /**
+     * The latency of data access of a cache. It occurs when there is
+     * an access to the cache.
+     */
+    const Cycles dataLatency;
+
+    /**
      * This is the forward latency of the cache. It occurs when there
      * is a cache miss and a request is forwarded downstream, in
      * particular an outbound miss.
diff -r 4aac82f10951 -r 9dba209f1590 src/mem/cache/base.cc
--- a/src/mem/cache/base.cc	Thu Jul 21 17:19:18 2016 +0100
+++ b/src/mem/cache/base.cc	Mon Oct 24 16:21:42 2016 +0200
@@ -72,9 +72,10 @@
       mshrQueue("MSHRs", p->mshrs, 0, p->demand_mshr_reserve), // see below
       writeBuffer("write buffer", p->write_buffers, p->mshrs), // see below
       blkSize(blk_size),
-      lookupLatency(p->hit_latency),
-      forwardLatency(p->hit_latency),
-      fillLatency(p->response_latency),
+      lookupLatency(p->tag_latency),
+      dataLatency(p->data_latency),
+      forwardLatency(p->tag_latency),
+      fillLatency(p->data_latency),
       responseLatency(p->response_latency),
       numTarget(p->tgts_per_mshr),
       forwardSnoops(true),
diff -r 4aac82f10951 -r 9dba209f1590 src/mem/cache/tags/Tags.py
--- a/src/mem/cache/tags/Tags.py	Thu Jul 21 17:19:18 2016 +0100
+++ b/src/mem/cache/tags/Tags.py	Mon Oct 24 16:21:42 2016 +0200
@@ -49,17 +49,22 @@
     # Get the block size from the parent (system)
     block_size = Param.Int(Parent.cache_line_size, "block size in bytes")
 
-    # Get the hit latency from the parent (cache)
-    hit_latency = Param.Cycles(Parent.hit_latency,
-                               "The hit latency for this cache")
+    # Get the tag lookup latency from the parent (cache)
+    tag_latency = Param.Cycles(Parent.tag_latency,
+                               "The tag lookup latency for this cache")
+
+    # Get the RAM access latency from the parent (cache)
+    data_latency = Param.Cycles(Parent.data_latency,
+                               "The data access latency for this cache")
+
+    sequential_access = Param.Bool(Parent.sequential_access,
+        "Whether to access tags and data sequentially")
 
 class BaseSetAssoc(BaseTags):
     type = 'BaseSetAssoc'
     abstract = True
     cxx_header = "mem/cache/tags/base_set_assoc.hh"
     assoc = Param.Int(Parent.assoc, "associativity")
-    sequential_access = Param.Bool(Parent.sequential_access,
-        "Whether to access tags and data sequentially")
 
 class LRU(BaseSetAssoc):
     type = 'LRU'
diff -r 4aac82f10951 -r 9dba209f1590 src/mem/cache/tags/base.hh
--- a/src/mem/cache/tags/base.hh	Thu Jul 21 17:19:18 2016 +0100
+++ b/src/mem/cache/tags/base.hh	Mon Oct 24 16:21:42 2016 +0200
@@ -69,7 +69,13 @@
     const unsigned blkSize;
     /** The size of the cache. */
     const unsigned size;
-    /** The access latency of the cache. */
+    /** The tag lookup latency of the cache. */
+    const Cycles lookupLatency;
+    /**
+     * The total access latency of the cache. This latency
+     * is different depending on the cache access mode
+     * (parallel or sequential)
+     */
     const Cycles accessLatency;
     /** Pointer to the parent cache. */
     BaseCache *cache;