diff --git a/util/tlm/examples/slave_port/main.cc b/util/tlm/examples/slave_port/main.cc
new file mode 100644
index 0000000..635abc8
--- /dev/null
+++ b/util/tlm/examples/slave_port/main.cc
@@ -0,0 +1,136 @@
+/*
+ * Copyright (c) 2015, University of Kaiserslautern
+ * All rights reserved.
+ *
+ * Copyright (c) 2016, TU Dresden
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Matthias Jung
+ *          Christian Menard
+ *          Abdul Mutaal Ahmad
+ */
+
+/**
+ * @file
+ *
+ *  Example top level file for SystemC-TLM integration with C++-only
+ *  instantiation.
+ *
+ */
+
+#include <tlm_utils/simple_target_socket.h>
+
+#include <cstdlib>
+#include <iomanip>
+#include <iostream>
+#include <sstream>
+#include <systemc>
+#include <tlm>
+#include <typeinfo>
+
+#include "base/statistics.hh"
+#include "base/str.hh"
+#include "base/trace.hh"
+#include "cpu/base.hh"
+#include "sc_logger.hh"
+#include "sc_module.hh"
+#include "sc_slave_port.hh"
+#include "sc_target.hh"
+#include "sim/cxx_config_ini.hh"
+#include "sim/cxx_manager.hh"
+#include "sim/init_signals.hh"
+#include "sim/serialize.hh"
+#include "sim/simulate.hh"
+#include "sim/stat_control.hh"
+#include "sim/system.hh"
+#include "sim_control.hh"
+#include "stats.hh"
+
+// Defining global string variable decalred in stats.hh
+std::string filename;
+
+void
+reportHandler(const sc_core::sc_report &report,
+              const sc_core::sc_actions &actions)
+{
+    uint64_t systemc_time = report.get_time().value();
+    uint64_t gem5_time = curTick();
+
+    std::cerr << report.get_time();
+
+    if (gem5_time < systemc_time) {
+        std::cerr << " (<) ";
+    } else if (gem5_time > systemc_time) {
+        std::cerr << " (!) ";
+    } else {
+        std::cerr << " (=) ";
+    }
+
+    std::cerr << ": " << report.get_msg_type()
+              << ' ' << report.get_msg() << '\n';
+}
+
+int
+sc_main(int argc, char **argv)
+{
+    sc_core::sc_report_handler::set_handler(reportHandler);
+
+    SimControl sim_control("gem5", argc, argv);
+    Target *memory;
+
+    filename = "m5out/stats-systemc.txt";
+
+    tlm::tlm_initiator_socket <> *mem_port =
+        dynamic_cast<tlm::tlm_initiator_socket<> *>(
+                    sc_core::sc_find_object("gem5.memory")
+                );
+
+    if (mem_port) {
+        SC_REPORT_INFO("sc_main", "Port Found");
+        unsigned long long int size = 512*1024*1024ULL;
+        memory = new Target("memory",
+                            sim_control.getDebugFlag(),
+                            size,
+                            sim_control.getOffset());
+
+        memory->socket.bind(*mem_port);
+    } else {
+        SC_REPORT_FATAL("sc_main", "Port Not Found");
+        std::exit(EXIT_FAILURE);
+    }
+
+    sc_core::sc_start();
+
+    SC_REPORT_INFO("sc_main", "End of Simulation");
+
+    CxxConfig::statsDump();
+
+    return EXIT_SUCCESS;
+}
diff --git a/util/tlm/main.cc b/util/tlm/sim_control.cc
similarity index 59%
rename from util/tlm/main.cc
rename to util/tlm/sim_control.cc
index bf442e0..1f800f7 100644
--- a/util/tlm/main.cc
+++ b/util/tlm/sim_control.cc
@@ -2,6 +2,9 @@
  * Copyright (c) 2015, University of Kaiserslautern
  * All rights reserved.
  *
+ * Copyright (c) 2016, TU Dresden
+ * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are
  * met:
@@ -31,6 +34,7 @@
  *
  * Authors: Matthias Jung
  *          Abdul Mutaal Ahmad
+ *          Christian Menard
  */
 
 /**
@@ -57,8 +61,7 @@
 #include "cpu/base.hh"
 #include "sc_logger.hh"
 #include "sc_module.hh"
-#include "sc_port.hh"
-#include "sc_target.hh"
+#include "sc_slave_port.hh"
 #include "sim/cxx_config_ini.hh"
 #include "sim/cxx_manager.hh"
 #include "sim/init_signals.hh"
@@ -66,62 +69,34 @@
 #include "sim/simulate.hh"
 #include "sim/stat_control.hh"
 #include "sim/system.hh"
+#include "sim_control.hh"
 #include "stats.hh"
 
-// Defining global string variable decalred in stats.hh
-std::string filename;
-
-void usage(const std::string &prog_name)
+void
+usage(const std::string& prog_name)
 {
-    std::cerr << "Usage: " << prog_name << (
-        " <config_file.ini> [ <option> ]\n\n"
-        "OPTIONS:\n"
-
-        "    -o <offset>                  -- set memory offset\n"
-        "    -p <object> <param> <value>  -- set a parameter\n"
-        "    -v <object> <param> <values> -- set a vector parameter from a\n"
-        "                                    comma separated values string\n"
-        "    -d <flag>                    -- set a debug flag\n"
-        "                                    (-<flag> clear a flag)\n"
-        "    -D                           -- debug on\n"
-        "    -e <ticks>                   -- end of simulation after a \n"
-        "                                    given number of ticks\n"
-        "\n"
-        );
+    std::cerr
+      << "Usage: " << prog_name
+      << (" <config_file.ini> [ <option> ]\n\n"
+          "OPTIONS:\n"
+
+          "    -o <offset>                  -- set memory offset\n"
+          "    -p <object> <param> <value>  -- set a parameter\n"
+          "    -v <object> <param> <values> -- set a vector parameter from a\n"
+          "                                    comma separated values string\n"
+          "    -d <flag>                    -- set a debug flag\n"
+          "                                    (-<flag> clear a flag)\n"
+          "    -D                           -- debug on\n"
+          "    -e <ticks>                   -- end of simulation after a \n"
+          "                                    given number of ticks\n"
+          "\n");
     std::exit(EXIT_FAILURE);
 }
 
-class SimControl : public Gem5SystemC::Module
-{
-    protected:
-    int argc;
-    char **argv;
-    CxxConfigManager *config_manager;
-    Gem5SystemC::Logger logger;
-
-    Tick sim_end;
-    bool debug;
-    unsigned int offset;
-
-    public:
-    SC_HAS_PROCESS(SimControl);
-
-    SimControl(sc_core::sc_module_name name, int argc_, char **argv_);
-
-    void before_end_of_elaboration();
-
-    bool getDebugFlag() { return debug; }
-
-    unsigned int getOffset() { return offset; }
-
-    void run();
-};
-
-SimControl::SimControl(sc_core::sc_module_name name,
-                       int argc_,
-                       char **argv_) : Gem5SystemC::Module(name),
-                                       argc(argc_),
-                                       argv(argv_)
+SimControl::SimControl(sc_core::sc_module_name name, int argc_, char** argv_)
+  : Gem5SystemC::Module(name)
+  , argc(argc_)
+  , argv(argv_)
 {
     SC_THREAD(run);
 
@@ -133,7 +108,7 @@ SimControl::SimControl(sc_core::sc_module_name name,
     }
 
     cxxConfigInit();
-    Gem5SystemC::registerSCPorts();
+    Gem5SystemC::SlavePort::registerPortHandler();
 
     Trace::setDebugLogger(&logger);
 
@@ -154,7 +129,7 @@ SimControl::SimControl(sc_core::sc_module_name name,
 
     const std::string config_file(argv[arg_ptr]);
 
-    CxxConfigFileBase *conf = new CxxIniFile();
+    CxxConfigFileBase* conf = new CxxIniFile();
 
     if (!conf->load(config_file.c_str())) {
         std::cerr << "Can't open config file: " << config_file << '\n';
@@ -176,7 +151,7 @@ SimControl::SimControl(sc_core::sc_module_name name,
                 }
 
                 config_manager->setParam(argv[arg_ptr], argv[arg_ptr + 1],
-                argv[arg_ptr + 2]);
+                                         argv[arg_ptr + 2]);
                 arg_ptr += 3;
             } else if (option == "-v") {
                 std::vector<std::string> values;
@@ -185,8 +160,7 @@ SimControl::SimControl(sc_core::sc_module_name name,
                     usage(prog_name);
                 }
                 tokenize(values, argv[2], ',');
-                config_manager->setParamVector(argv[arg_ptr],
-                                               argv[arg_ptr],
+                config_manager->setParamVector(argv[arg_ptr], argv[arg_ptr],
                                                values);
                 arg_ptr += 3;
             } else if (option == "-d") {
@@ -218,7 +192,7 @@ SimControl::SimControl(sc_core::sc_module_name name,
                 usage(prog_name);
             }
         }
-    } catch (CxxConfigManager::Exception &e) {
+    } catch (CxxConfigManager::Exception& e) {
         std::cerr << e.name << ": " << e.message << "\n";
         std::exit(EXIT_FAILURE);
     }
@@ -228,9 +202,9 @@ SimControl::SimControl(sc_core::sc_module_name name,
 
     try {
         config_manager->instantiate();
-    } catch (CxxConfigManager::Exception &e) {
-        std::cerr << "Config problem in sim object "
-                  << e.name << ": " << e.message << "\n";
+    } catch (CxxConfigManager::Exception& e) {
+        std::cerr << "Config problem in sim object " << e.name << ": "
+                  << e.message << "\n";
         std::exit(EXIT_FAILURE);
     }
 }
@@ -241,9 +215,9 @@ SimControl::before_end_of_elaboration()
     try {
         config_manager->initState();
         config_manager->startup();
-    } catch (CxxConfigManager::Exception &e) {
-        std::cerr << "Config problem in sim object "
-            << e.name << ": " << e.message << "\n";
+    } catch (CxxConfigManager::Exception& e) {
+        std::cerr << "Config problem in sim object " << e.name << ": "
+                  << e.message << "\n";
         std::exit(EXIT_FAILURE);
     }
 }
@@ -251,7 +225,7 @@ SimControl::before_end_of_elaboration()
 void
 SimControl::run()
 {
-    GlobalSimLoopExitEvent *exit_event = NULL;
+    GlobalSimLoopExitEvent* exit_event = NULL;
 
     if (sim_end == 0) {
         exit_event = simulate();
@@ -268,64 +242,3 @@ SimControl::run()
     config_manager->deleteObjects();
 #endif
 }
-
-
-void
-reportHandler(const sc_core::sc_report &report,
-              const sc_core::sc_actions &actions)
-{
-    uint64_t systemc_time = report.get_time().value();
-    uint64_t gem5_time = curTick();
-
-    std::cerr << report.get_time();
-
-    if (gem5_time < systemc_time) {
-        std::cerr << " (<) ";
-    } else if (gem5_time > systemc_time) {
-        std::cerr << " (!) ";
-    } else {
-        std::cerr << " (=) ";
-    }
-
-    std::cerr << ": " << report.get_msg_type()
-              << ' ' << report.get_msg() << '\n';
-}
-
-
-int
-sc_main(int argc, char **argv)
-{
-    sc_core::sc_report_handler::set_handler(reportHandler);
-
-    SimControl sim_control("gem5", argc, argv);
-    Target *memory;
-
-    filename = "m5out/stats-tlm.txt";
-
-    tlm::tlm_initiator_socket <> *mem_port =
-        dynamic_cast<tlm::tlm_initiator_socket<> *>(
-                    sc_core::sc_find_object("gem5.memory")
-                );
-
-    if (mem_port) {
-        SC_REPORT_INFO("sc_main", "Port Found");
-        unsigned long long int size = 512*1024*1024ULL;
-        memory = new Target("memory",
-                            sim_control.getDebugFlag(),
-                            size,
-                            sim_control.getOffset());
-
-        memory->socket.bind(*mem_port);
-    } else {
-        SC_REPORT_FATAL("sc_main", "Port Not Found");
-        std::exit(EXIT_FAILURE);
-    }
-
-    sc_core::sc_start();
-
-    SC_REPORT_INFO("sc_main", "End of Simulation");
-
-    CxxConfig::statsDump();
-
-    return EXIT_SUCCESS;
-}
diff --git a/util/tlm/payload_event.hh b/util/tlm/payload_event.hh
new file mode 100644
index 0000000..58293c2
--- /dev/null
+++ b/util/tlm/payload_event.hh
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2015, University of Kaiserslautern
+ * All rights reserved.
+ *
+ * Copyright (c) 2016, TU Dresden
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Matthias Jung
+ *          Christian Menard
+ */
+
+#pragma once
+
+// TLM includes
+#include <tlm.h>
+
+// gem5 includes
+#include <sim/eventq.hh>
+
+namespace Gem5SystemC {
+/**
+ * A 'Fake Payload Event Queue', similar to the TLM PEQs. This will help
+ * that gem5 behaves like a normal TLM Initiator
+ */
+template <typename OWNER>
+class PayloadEvent : public Event
+{
+  public:
+    OWNER& port;
+    const std::string eventName;
+    void (OWNER::*handler)(PayloadEvent<OWNER>* pe,
+                           tlm::tlm_generic_payload& trans,
+                           const tlm::tlm_phase& phase);
+
+  protected:
+    tlm::tlm_generic_payload* t;
+    tlm::tlm_phase p;
+
+    void process() { (port.*handler)(this, *t, p); }
+
+  public:
+    const std::string name() const { return eventName; }
+
+    PayloadEvent(OWNER& port_,
+                 void (OWNER::*handler_)(PayloadEvent<OWNER>* pe,
+                                         tlm::tlm_generic_payload& trans,
+                                         const tlm::tlm_phase& phase),
+                 const std::string& event_name)
+      : port(port_)
+      , eventName(event_name)
+      , handler(handler_)
+    {
+    }
+
+    /// Schedule an event into gem5
+    void notify(tlm::tlm_generic_payload& trans, const tlm::tlm_phase& phase,
+                const sc_core::sc_time& delay)
+    {
+        assert(!scheduled());
+
+        t = &trans;
+        p = phase;
+
+        /**
+         * Get time from SystemC as this will always be more up to date
+         * than gem5's
+         */
+        Tick nextEventTick = sc_core::sc_time_stamp().value() + delay.value();
+
+        port.owner.wakeupEventQueue(nextEventTick);
+        port.owner.schedule(this, nextEventTick);
+    }
+};
+}
diff --git a/util/tlm/run_gem5.sh b/util/tlm/examples/slave_port/run_gem5.sh
old mode 100644
new mode 100755
similarity index 97%
rename from util/tlm/run_gem5.sh
rename to util/tlm/examples/slave_port/run_gem5.sh
index c50391e..a4a0b80
--- a/util/tlm/run_gem5.sh
+++ b/util/tlm/examples/slave_port/run_gem5.sh
@@ -36,7 +36,7 @@ RCol='\e[0m'; # Text Reset
 BGre='\e[1;31m';
 echo -e "\n${BGre}Create gem5 Configuration${RCol}\n"
 
-../../build/ARM/gem5.opt ../../configs/example/fs.py        \
+../../../../build/ARM/gem5.opt ../../../../configs/example/fs.py \
 --tlm-memory=memory                                         \
 --cpu-type=timing                                           \
 --num-cpu=1                                                 \
diff --git a/util/tlm/sc_port.hh b/util/tlm/sc_slave_port.hh
similarity index 63%
rename from util/tlm/sc_port.hh
rename to util/tlm/sc_slave_port.hh
index 374a3cf..c48a399 100644
--- a/util/tlm/sc_port.hh
+++ b/util/tlm/sc_slave_port.hh
@@ -2,6 +2,9 @@
  * Copyright (c) 2015, University of Kaiserslautern
  * All rights reserved.
  *
+ * Copyright (c) 2016, TU Dresden
+ * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are
  * met:
@@ -30,6 +33,7 @@
  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  * Authors: Matthias Jung
+ *          Christian Menard
  */
 
 #ifndef __SIM_SC_TRANSACTOR_HH__
@@ -42,6 +46,7 @@
 #include <tlm>
 
 #include "mem/external_slave.hh"
+#include "payload_event.hh"
 #include "sc_mm.hh"
 #include "sc_module.hh"
 
@@ -55,73 +60,16 @@ namespace Gem5SystemC
 } while (0)
 
 
-class sc_transactor : public tlm::tlm_initiator_socket<>,
+class SlavePort : public tlm::tlm_initiator_socket<>,
         public tlm::tlm_bw_transport_if<>,
         public ExternalSlave::Port
 {
   public:
-    sc_transactor &iSocket;
-
-    /**
-     * A 'Fake Payload Event Queue', similar to the TLM PEQs. This will help
-     * that gem5 behaves like a normal TLM Initiator
-     */
-    template<typename OWNER>
-    class payloadEvent : public Event
-    {
-        public:
-        OWNER &port;
-        const std::string eventName;
-        void (OWNER::* handler)(payloadEvent<OWNER> * pe,
-            tlm::tlm_generic_payload& trans,
-            const tlm::tlm_phase &phase);
-
-        protected:
-        tlm::tlm_generic_payload *t;
-        tlm::tlm_phase p;
-
-        void process() { (port.*handler)(this,*t, p); }
-
-        public:
-        const std::string name() const { return eventName; }
-
-        payloadEvent(
-            OWNER &port_,
-            void (OWNER::* handler_)(payloadEvent<OWNER> * pe,
-                tlm::tlm_generic_payload& trans,
-                const tlm::tlm_phase &phase),
-            const std::string &event_name) :
-            port(port_),
-            eventName(event_name),
-            handler(handler_)
-        { }
-
-        /// Schedule an event into gem5
-        void
-        notify(tlm::tlm_generic_payload& trans,
-           const tlm::tlm_phase &phase,
-           const sc_core::sc_time& delay)
-        {
-            assert(!scheduled());
-
-            t = &trans;
-            p = phase;
-
-            /**
-             * Get time from SystemC as this will alway be more up to date
-             * than gem5's
-             */
-            Tick nextEventTick = sc_core::sc_time_stamp().value()
-                + delay.value();
-
-            port.owner.wakeupEventQueue(nextEventTick);
-            port.owner.schedule(this, nextEventTick);
-       }
-    };
+    SlavePort &iSocket;
 
     /** One instance of pe and the related callback needed */
-    //payloadEvent<sc_transactor> pe;
-    void pec(payloadEvent<sc_transactor> * pe,
+    //payloadEvent<SlavePort> pe;
+    void pec(PayloadEvent<SlavePort> * pe,
         tlm::tlm_generic_payload& trans, const tlm::tlm_phase& phase);
 
     /**
@@ -160,14 +108,14 @@ class sc_transactor : public tlm::tlm_initiator_socket<>,
                                    sc_dt::uint64 end_range);
 
   public:
-    sc_transactor(const std::string &name_,
-           const std::string &systemc_name,
-           ExternalSlave &owner_);
-};
+    SlavePort(const std::string &name_,
+              const std::string &systemc_name,
+              ExternalSlave &owner_);
 
-void registerPort(const std::string &name, Port &port);
+    static void registerPortHandler();
 
-void registerSCPorts();
+    friend PayloadEvent<SlavePort>;
+};
 
 }
 
diff --git a/util/tlm/sc_port.cc b/util/tlm/sc_slave_port.cc
similarity index 90%
rename from util/tlm/sc_port.cc
rename to util/tlm/sc_slave_port.cc
index ab94f73..894af5e 100644
--- a/util/tlm/sc_port.cc
+++ b/util/tlm/sc_slave_port.cc
@@ -40,7 +40,7 @@
 #include "debug/ExternalPort.hh"
 #include "sc_ext.hh"
 #include "sc_mm.hh"
-#include "sc_port.hh"
+#include "sc_slave_port.hh"
 
 namespace Gem5SystemC
 {
@@ -86,7 +86,7 @@ packet2payload(PacketPtr packet, tlm::tlm_generic_payload &trans)
  * Similar to TLM's blocking transport (LT)
  */
 Tick
-sc_transactor::recvAtomic(PacketPtr packet)
+SlavePort::recvAtomic(PacketPtr packet)
 {
     CAUGHT_UP;
     SC_REPORT_INFO("transactor", "recvAtomic hasn't been tested much");
@@ -136,7 +136,7 @@ sc_transactor::recvAtomic(PacketPtr packet)
  * Similar to TLM's debug transport
  */
 void
-sc_transactor::recvFunctional(PacketPtr packet)
+SlavePort::recvFunctional(PacketPtr packet)
 {
     /* Prepare the transaction */
     tlm::tlm_generic_payload * trans = mm.allocate();
@@ -157,7 +157,7 @@ sc_transactor::recvFunctional(PacketPtr packet)
 }
 
 bool
-sc_transactor::recvTimingSnoopResp(PacketPtr packet)
+SlavePort::recvTimingSnoopResp(PacketPtr packet)
 {
     /* Snooping should be implemented with tlm_dbg_transport */
     SC_REPORT_FATAL("transactor","unimplemented func.: recvTimingSnoopResp");
@@ -165,7 +165,7 @@ sc_transactor::recvTimingSnoopResp(PacketPtr packet)
 }
 
 void
-sc_transactor::recvFunctionalSnoop(PacketPtr packet)
+SlavePort::recvFunctionalSnoop(PacketPtr packet)
 {
     /* Snooping should be implemented with tlm_dbg_transport */
     SC_REPORT_FATAL("transactor","unimplemented func.: recvFunctionalSnoop");
@@ -175,7 +175,7 @@ sc_transactor::recvFunctionalSnoop(PacketPtr packet)
  *  Similar to TLM's non-blocking transport (AT)
  */
 bool
-sc_transactor::recvTimingReq(PacketPtr packet)
+SlavePort::recvTimingReq(PacketPtr packet)
 {
     CAUGHT_UP;
 
@@ -231,9 +231,9 @@ sc_transactor::recvTimingReq(PacketPtr packet)
         /* The Timing annotation must be honored: */
         sc_assert(phase == tlm::END_REQ || phase == tlm::BEGIN_RESP);
 
-        payloadEvent<sc_transactor> * pe;
-        pe = new payloadEvent<sc_transactor>(*this,
-            &sc_transactor::pec, "PEQ");
+        PayloadEvent<SlavePort> * pe;
+        pe = new PayloadEvent<SlavePort>(*this,
+            &SlavePort::pec, "PEQ");
         pe->notify(*trans, phase, delay);
     } else if (status == tlm::TLM_COMPLETED) {
         /* Transaction is over nothing has do be done. */
@@ -245,8 +245,8 @@ sc_transactor::recvTimingReq(PacketPtr packet)
 }
 
 void
-sc_transactor::pec(
-    sc_transactor::payloadEvent<sc_transactor> * pe,
+SlavePort::pec(
+    PayloadEvent<SlavePort> * pe,
     tlm::tlm_generic_payload& trans,
     const tlm::tlm_phase& phase)
 {
@@ -298,7 +298,7 @@ sc_transactor::pec(
 }
 
 void
-sc_transactor::recvRespRetry()
+SlavePort::recvRespRetry()
 {
     CAUGHT_UP;
 
@@ -321,24 +321,24 @@ sc_transactor::recvRespRetry()
 }
 
 tlm::tlm_sync_enum
-sc_transactor::nb_transport_bw(tlm::tlm_generic_payload& trans,
+SlavePort::nb_transport_bw(tlm::tlm_generic_payload& trans,
     tlm::tlm_phase& phase,
     sc_core::sc_time& delay)
 {
-    payloadEvent<sc_transactor> * pe;
-    pe = new payloadEvent<sc_transactor>(*this, &sc_transactor::pec, "PE");
+    PayloadEvent<SlavePort> * pe;
+    pe = new PayloadEvent<SlavePort>(*this, &SlavePort::pec, "PE");
     pe->notify(trans, phase, delay);
     return tlm::TLM_ACCEPTED;
 }
 
 void
-sc_transactor::invalidate_direct_mem_ptr(sc_dt::uint64 start_range,
+SlavePort::invalidate_direct_mem_ptr(sc_dt::uint64 start_range,
      sc_dt::uint64 end_range)
 {
     SC_REPORT_FATAL("transactor", "unimpl. func: invalidate_direct_mem_ptr");
 }
 
-sc_transactor::sc_transactor(const std::string &name_,
+SlavePort::SlavePort(const std::string &name_,
     const std::string &systemc_name,
     ExternalSlave &owner_) :
     tlm::tlm_initiator_socket<>(systemc_name.c_str()),
@@ -351,7 +351,7 @@ sc_transactor::sc_transactor(const std::string &name_,
     m_export.bind(*this);
 }
 
-class sc_transactorHandler : public ExternalSlave::Handler
+class SlavePortHandler : public ExternalSlave::Handler
 {
   public:
     ExternalSlave::Port *getExternalPort(const std::string &name,
@@ -359,14 +359,14 @@ class sc_transactorHandler : public ExternalSlave::Handler
         const std::string &port_data)
     {
         // This will make a new initiatiator port
-        return new sc_transactor(name, port_data, owner);
+        return new SlavePort(name, port_data, owner);
     }
 };
 
 void
-registerSCPorts()
+SlavePort::registerPortHandler()
 {
-    ExternalSlave::registerHandler("tlm", new sc_transactorHandler);
+    ExternalSlave::registerHandler("tlm_slave", new SlavePortHandler);
 }
 
 }
diff --git a/util/tlm/sc_target.hh b/util/tlm/examples/slave_port/sc_target.hh
similarity index 100%
rename from util/tlm/sc_target.hh
rename to util/tlm/examples/slave_port/sc_target.hh
diff --git a/util/tlm/sc_target.cc b/util/tlm/examples/slave_port/sc_target.cc
similarity index 100%
rename from util/tlm/sc_target.cc
rename to util/tlm/examples/slave_port/sc_target.cc
diff --git a/util/tlm/sim_control.hh b/util/tlm/sim_control.hh
new file mode 100644
index 0000000..4c9798b
--- /dev/null
+++ b/util/tlm/sim_control.hh
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2015, University of Kaiserslautern
+ * All rights reserved.
+ *
+ * Copyright (c) 2016, TU Dresden
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Matthias Jung
+ *          Christian Menard
+ */
+
+#include <tlm_utils/simple_target_socket.h>
+
+#include <systemc>
+#include <tlm>
+
+#include "sc_logger.hh"
+#include "sc_module.hh"
+#include "sim/cxx_config_ini.hh"
+#include "sim/cxx_manager.hh"
+#include "sim/system.hh"
+
+class SimControl : public Gem5SystemC::Module
+{
+  protected:
+    int argc;
+    char** argv;
+    CxxConfigManager* config_manager;
+    Gem5SystemC::Logger logger;
+
+    Tick sim_end;
+    bool debug;
+    unsigned int offset;
+
+  public:
+    SC_HAS_PROCESS(SimControl);
+
+    SimControl(sc_core::sc_module_name name, int argc_, char** argv_);
+
+    void before_end_of_elaboration();
+
+    bool getDebugFlag() { return debug; }
+
+    unsigned int getOffset() { return offset; }
+
+    void run();
+};

diff --git a/util/tlm/tgen.cfg b/util/tlm/examples/slave_port/tgen.cfg
similarity index 100%
rename from util/tlm/tgen.cfg
rename to util/tlm/examples/slave_port/tgen.cfg
diff --git a/util/tlm/tlm.py b/util/tlm/examples/slave_port/tlm.py
similarity index 96%
rename from util/tlm/tlm.py
rename to util/tlm/examples/slave_port/tlm.py
index e9025ab..9d6b26d 100644
--- a/util/tlm/tlm.py
+++ b/util/tlm/examples/slave_port/tlm.py
@@ -45,7 +45,7 @@ from m5.objects import *
 #         |      |            |
 # +-------v------v-------+    |
 # |        Membus        |    v
-# +----------------+-----+    External Port (see sc_port.*)
+# +----------------+-----+    External Port (see sc_slave_port.*)
 #                  |          ^
 #              +---v---+      | TLM World
 #              |  TLM  |      | (see sc_target.*)
@@ -63,7 +63,7 @@ system.clk_domain = SrcClockDomain(clock = '1.5GHz',
 # Create a external TLM port:
 system.tlm = ExternalSlave()
 system.tlm.addr_ranges = [AddrRange('512MB')]
-system.tlm.port_type = "tlm"
+system.tlm.port_type = "tlm_slave"
 system.tlm.port_data = "memory"
 
 # Route the connections:
diff --git a/util/tlm/tlm_elastic.py b/util/tlm/examples/slave_port/tlm_elastic.py
similarity index 100%
rename from util/tlm/tlm_elastic.py
rename to util/tlm/examples/slave_port/tlm_elastic.py
# HG changeset patch
# User Christian Menard <christian.menard@tu-dresden.de>
# Parent: cdb94f2332a6

diff --git a/configs/common/MemConfig.py b/configs/common/MemConfig.py
index 71e3bf4..2cfa25e 100644
--- a/configs/common/MemConfig.py
+++ b/configs/common/MemConfig.py
@@ -163,7 +163,7 @@ def config_mem(options, system):
 
     if options.tlm_memory:
         system.external_memory = m5.objects.ExternalSlave(
-            port_type="tlm",
+            port_type="tlm_slave",
             port_data=options.tlm_memory,
             port=system.membus.master,
             addr_ranges=system.mem_ranges)
diff --git a/util/tlm/Makefile b/util/tlm/examples/slave_port/Makefile
similarity index 64%
rename from util/tlm/Makefile
rename to util/tlm/examples/slave_port/Makefile
index 1fda3b1..0de9b50 100644
--- a/util/tlm/Makefile
+++ b/util/tlm/examples/slave_port/Makefile
@@ -1,6 +1,9 @@
 # Copyright (c) 2015, University of Kaiserslautern
 # All rights reserved.
 # 
+# Copyright (c) 2016, TU Dresden
+# All rights reserved.
+#
 # Redistribution and use in source and binary forms, with or without
 # modification, are permitted provided that the following conditions are
 # met:
@@ -29,6 +32,7 @@
 # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 # 
 # Authors: Matthias Jung
+# Authors: Christian Menard
 
 
 ARCH = ARM
@@ -36,10 +40,11 @@ VARIANT = opt
 #VARIANT = debug
 
 SYSTEMC_INC = /opt/systemc/include
-SYSTEMC_LIB = /opt/systemc/lib-linux64
+SYSTEMC_LIB = /opt/systemc/lib-linux
 
-CXXFLAGS = -I../../build/$(ARCH) -L../../build/$(ARCH)
-CXXFLAGS += -I../systemc/
+CXXFLAGS = -I../../../../build/$(ARCH) -L../../../../build/$(ARCH)
+CXXFLAGS += -I../../../systemc/
+CXXFLAGS += -I../../
 CXXFLAGS += -I$(SYSTEMC_INC) -L$(SYSTEMC_LIB)
 CXXFLAGS += -std=c++0x
 CXXFLAGS += -g
@@ -54,23 +59,29 @@ all: $(ALL)
 .cc.o:
 	$(CXX) $(CXXFLAGS) -c -o $@ $<
 
-sc_gem5_control.o: ../systemc/sc_gem5_control.cc \
-	../systemc/sc_gem5_control.hh
-sc_logger.o: ../systemc/sc_logger.cc ../systemc/sc_logger.hh
-sc_module.o: ../systemc/sc_module.cc ../systemc/sc_module.hh
-sc_mm.o: sc_mm.cc sc_mm.hh
-sc_ext.o: sc_ext.cc sc_ext.hh
-sc_port.o: sc_port.cc sc_port.hh
+sc_gem5_control.o: ../../../systemc/sc_gem5_control.cc \
+	../../../systemc/sc_gem5_control.hh
+sc_logger.o: ../../../systemc/sc_logger.cc ../../../systemc/sc_logger.hh
+sc_module.o: ../../../systemc/sc_module.cc ../../../systemc/sc_module.hh
+sc_mm.o: ../../sc_mm.cc ../../sc_mm.hh
+sc_ext.o: ../../sc_ext.cc ../../sc_ext.hh
+sc_slave_port.o: ../../sc_slave_port.cc ../../sc_slave_port.hh \
+	../../payload_event.hh
 sc_target.o: sc_target.cc sc_target.hh
-stats.o: ../systemc/stats.cc ../systemc/stats.hh
-main.o: main.cc ../systemc/sc_logger.hh ../systemc/sc_module.hh \
-	../systemc/stats.hh
+stats.o: ../../../systemc/stats.cc ../../../systemc/stats.hh
+sim_control.o: ../../sim_control.cc ../../sim_control.hh \
+	../../sc_slave_port.hh
+main.o: main.cc ../../../systemc/sc_logger.hh ../../../systemc/sc_module.hh \
+	../../../systemc/stats.hh
 
-gem5.$(VARIANT).sc: main.o ../systemc/stats.o ../systemc/sc_gem5_control.o \
-	../systemc/sc_logger.o ../systemc/sc_module.o sc_mm.o sc_ext.o sc_port.o sc_target.o
+gem5.$(VARIANT).sc: main.o ../../../systemc/stats.o \
+	../../../systemc/sc_gem5_control.o ../../../systemc/sc_logger.o \
+	../../../systemc/sc_module.o ../../sc_mm.o ../../sc_ext.o \
+	../../sc_slave_port.o ../../sim_control.o sc_target.o
 	$(CXX) $(CXXFLAGS) -o $@ $^ $(LIBS)
 
 clean:
 	$(RM) $(ALL)
 	$(RM) *.o
+	$(RM) ../../*.o
 	$(RM) -r m5out
diff --git a/util/tlm/README b/util/tlm/README
index fc620f1..f259139 100644
--- a/util/tlm/README
+++ b/util/tlm/README
@@ -5,13 +5,15 @@ system example.
 
 Files:
 
-    main.cc                -- demonstration top level
-    sc_port.{cc,hh}        -- transactor that translates beween gem5 and tlm
-    sc_mm.{cc,hh}          -- implementation of a tlm memory manager
-    sc_ext.{cc,hh}         -- a TLM extension that carries the gem5 packet
-    sc_target.{cc,hh}      -- an example TLM LT/AT memory module
-    tlm.py                 -- simple gem5 configuration
-    tgen.cfg               -- configuration file for the traceplayer
+    sc_slave_port.{cc,hh}   -- transactor that translates beween gem5 and tlm
+    sc_mm.{cc,hh}           -- implementation of a tlm memory manager
+    sc_ext.{cc,hh}          -- a TLM extension that carries the gem5 packet
+
+    example/slave_port/main.cc           -- demonstration of the slave port
+    example/slave_port/sc_target.{cc,hh} -- an example TLM LT/AT memory module
+    example/slave_port/tlm.py            -- simple gem5 configuration
+    example/slave_port/tgen.cfg          -- configuration file for the
+                                            traceplayer
 
 Other Files will be used from utils/systemc example:
 
@@ -33,7 +35,7 @@ without python.
 > cd ../..
 > scons build/ARM/gem5.opt
 > scons --with-cxx-config --without-python build/ARM/libgem5_opt.so
-> cd util/tlm
+> cd util/tlm/examples/slave_port
 
 Set a proper LD_LIBRARY_PATH e.g. for bash:
 > export LD_LIBRARY_PATH="$LD_LIBRARY_PATH:/path/to/gem5/build/ARM/"
@@ -44,7 +46,7 @@ Then edit the Makefile to set the paths for SystemC and run make
 
 Make a config file for the C++-configured gem5 using normal gem5
 
-> ../../build/ARM/gem5.opt ./tlm.py
+> ../../../../build/ARM/gem5.opt ./tlm.py
 
 The message "fatal: Can't find port handler type 'tlm'" is okay.
 The configuration will be stored in the m5out/ directory
@@ -73,7 +75,8 @@ II. Full System Setup
 Build gem5 as discribed in Section I. Then, make a config file for the
 C++-configured gem5 using normal gem5
 
-> ../../build/ARM/gem5.opt ../../configs/example/fs.py --tlm-memory=memory \
+> ../../../../build/ARM/gem5.opt ../../../../configs/example/fs.py         \
+  --tlm-memory=memory                                                      \
   --cpu-type=timing --num-cpu=1 --mem-type=SimpleMemory --mem-size=512MB   \
   --mem-channels=1  --caches --l2cache --machine-type=VExpress_EMM         \
   --dtb-filename=vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb              \
@@ -112,7 +115,7 @@ For more information on elastic traces please refer to:
 
 Similar to I. the simulation can be set up with this command:
 
-> ../../build/ARM/gem5.opt ./tlm_elastic.py
+> ../../../../build/ARM/gem5.opt ./tlm_elastic.py
 
 Then: