# HG changeset patch # Parent c6e92c923a9e1c8cfd06ce9da1f61476ae4cb007 diff --git a/configs/common/MemConfig.py b/configs/common/MemConfig.py --- a/configs/common/MemConfig.py +++ b/configs/common/MemConfig.py @@ -163,7 +163,7 @@ if options.tlm_memory: system.external_memory = m5.objects.ExternalSlave( - port_type="tlm", + port_type="tlm_slave", port_data=options.tlm_memory, port=system.membus.master, addr_ranges=system.mem_ranges) diff --git a/util/tlm/Makefile b/util/tlm/examples/slave_port/Makefile rename from util/tlm/Makefile rename to util/tlm/examples/slave_port/Makefile --- a/util/tlm/Makefile +++ b/util/tlm/examples/slave_port/Makefile @@ -1,21 +1,24 @@ # Copyright (c) 2015, University of Kaiserslautern # All rights reserved. -# +# +# Copyright (c) 2016, TU Dresden +# All rights reserved. +# # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are # met: -# +# # 1. Redistributions of source code must retain the above copyright notice, # this list of conditions and the following disclaimer. -# +# # 2. Redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution. -# +# # 3. Neither the name of the copyright holder nor the names of its # contributors may be used to endorse or promote products derived from # this software without specific prior written permission. -# +# # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED # TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR @@ -27,8 +30,9 @@ # LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# +# # Authors: Matthias Jung +# Authors: Christian Menard ARCH = ARM @@ -36,10 +40,11 @@ #VARIANT = debug SYSTEMC_INC = /opt/systemc/include -SYSTEMC_LIB = /opt/systemc/lib-linux64 +SYSTEMC_LIB = /opt/systemc/lib-linux -CXXFLAGS = -I../../build/$(ARCH) -L../../build/$(ARCH) -CXXFLAGS += -I../systemc/ +CXXFLAGS = -I../../../../build/$(ARCH) -L../../../../build/$(ARCH) +CXXFLAGS += -I../../../systemc/ +CXXFLAGS += -I../../ CXXFLAGS += -I$(SYSTEMC_INC) -L$(SYSTEMC_LIB) CXXFLAGS += -std=c++0x CXXFLAGS += -g @@ -54,23 +59,29 @@ .cc.o: $(CXX) $(CXXFLAGS) -c -o $@ $< -sc_gem5_control.o: ../systemc/sc_gem5_control.cc \ - ../systemc/sc_gem5_control.hh -sc_logger.o: ../systemc/sc_logger.cc ../systemc/sc_logger.hh -sc_module.o: ../systemc/sc_module.cc ../systemc/sc_module.hh -sc_mm.o: sc_mm.cc sc_mm.hh -sc_ext.o: sc_ext.cc sc_ext.hh -sc_port.o: sc_port.cc sc_port.hh +sc_gem5_control.o: ../../../systemc/sc_gem5_control.cc \ + ../../../systemc/sc_gem5_control.hh +sc_logger.o: ../../../systemc/sc_logger.cc ../../../systemc/sc_logger.hh +sc_module.o: ../../../systemc/sc_module.cc ../../../systemc/sc_module.hh +sc_mm.o: ../../sc_mm.cc ../../sc_mm.hh +sc_ext.o: ../../sc_ext.cc ../../sc_ext.hh +sc_slave_port.o: ../../sc_slave_port.cc ../../sc_slave_port.hh \ + ../../payload_event.hh sc_target.o: sc_target.cc sc_target.hh -stats.o: ../systemc/stats.cc ../systemc/stats.hh -main.o: main.cc ../systemc/sc_logger.hh ../systemc/sc_module.hh \ - ../systemc/stats.hh +stats.o: ../../../systemc/stats.cc ../../../systemc/stats.hh +sim_control.o: ../../sim_control.cc ../../sim_control.hh \ + ../../sc_slave_port.hh +main.o: main.cc ../../../systemc/sc_logger.hh ../../../systemc/sc_module.hh \ + ../../../systemc/stats.hh -gem5.$(VARIANT).sc: main.o ../systemc/stats.o ../systemc/sc_gem5_control.o \ - ../systemc/sc_logger.o ../systemc/sc_module.o sc_mm.o sc_ext.o sc_port.o sc_target.o +gem5.$(VARIANT).sc: main.o ../../../systemc/stats.o \ + ../../../systemc/sc_gem5_control.o ../../../systemc/sc_logger.o \ + ../../../systemc/sc_module.o ../../sc_mm.o ../../sc_ext.o \ + ../../sc_slave_port.o ../../sim_control.o sc_target.o $(CXX) $(CXXFLAGS) -o $@ $^ $(LIBS) clean: $(RM) $(ALL) $(RM) *.o + $(RM) ../../*.o $(RM) -r m5out diff --git a/util/tlm/README b/util/tlm/README --- a/util/tlm/README +++ b/util/tlm/README @@ -5,13 +5,15 @@ Files: - main.cc -- demonstration top level - sc_port.{cc,hh} -- transactor that translates beween gem5 and tlm - sc_mm.{cc,hh} -- implementation of a tlm memory manager - sc_ext.{cc,hh} -- a TLM extension that carries the gem5 packet - sc_target.{cc,hh} -- an example TLM LT/AT memory module - tlm.py -- simple gem5 configuration - tgen.cfg -- configuration file for the traceplayer + sc_slave_port.{cc,hh} -- transactor that translates beween gem5 and tlm + sc_mm.{cc,hh} -- implementation of a tlm memory manager + sc_ext.{cc,hh} -- a TLM extension that carries the gem5 packet + + example/slave_port/main.cc -- demonstration of the slave port + example/slave_port/sc_target.{cc,hh} -- an example TLM LT/AT memory module + example/slave_port/tlm.py -- simple gem5 configuration + example/slave_port/tgen.cfg -- configuration file for the + traceplayer Other Files will be used from utils/systemc example: @@ -33,7 +35,7 @@ > cd ../.. > scons build/ARM/gem5.opt > scons --with-cxx-config --without-python build/ARM/libgem5_opt.so -> cd util/tlm +> cd util/tlm/examples/slave_port Set a proper LD_LIBRARY_PATH e.g. for bash: > export LD_LIBRARY_PATH="$LD_LIBRARY_PATH:/path/to/gem5/build/ARM/" @@ -44,7 +46,7 @@ Make a config file for the C++-configured gem5 using normal gem5 -> ../../build/ARM/gem5.opt ./tlm.py +> ../../../../build/ARM/gem5.opt ./tlm.py The message "fatal: Can't find port handler type 'tlm'" is okay. The configuration will be stored in the m5out/ directory @@ -73,7 +75,8 @@ Build gem5 as discribed in Section I. Then, make a config file for the C++-configured gem5 using normal gem5 -> ../../build/ARM/gem5.opt ../../configs/example/fs.py --tlm-memory=memory \ +> ../../../../build/ARM/gem5.opt ../../../../configs/example/fs.py \ + --tlm-memory=memory \ --cpu-type=timing --num-cpu=1 --mem-type=SimpleMemory --mem-size=512MB \ --mem-channels=1 --caches --l2cache --machine-type=VExpress_EMM \ --dtb-filename=vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb \ @@ -112,7 +115,7 @@ Similar to I. the simulation can be set up with this command: -> ../../build/ARM/gem5.opt ./tlm_elastic.py +> ../../../../build/ARM/gem5.opt ./tlm_elastic.py Then: diff --git a/util/tlm/examples/slave_port/main.cc b/util/tlm/examples/slave_port/main.cc new file mode 100644 --- /dev/null +++ b/util/tlm/examples/slave_port/main.cc @@ -0,0 +1,136 @@ +/* + * Copyright (c) 2015, University of Kaiserslautern + * All rights reserved. + * + * Copyright (c) 2016, TU Dresden + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Matthias Jung + * Christian Menard + * Abdul Mutaal Ahmad + */ + +/** + * @file + * + * Example top level file for SystemC-TLM integration with C++-only + * instantiation. + * + */ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include "base/statistics.hh" +#include "base/str.hh" +#include "base/trace.hh" +#include "cpu/base.hh" +#include "sc_logger.hh" +#include "sc_module.hh" +#include "sc_slave_port.hh" +#include "sc_target.hh" +#include "sim/cxx_config_ini.hh" +#include "sim/cxx_manager.hh" +#include "sim/init_signals.hh" +#include "sim/serialize.hh" +#include "sim/simulate.hh" +#include "sim/stat_control.hh" +#include "sim/system.hh" +#include "sim_control.hh" +#include "stats.hh" + +// Defining global string variable decalred in stats.hh +std::string filename; + +void +reportHandler(const sc_core::sc_report &report, + const sc_core::sc_actions &actions) +{ + uint64_t systemc_time = report.get_time().value(); + uint64_t gem5_time = curTick(); + + std::cerr << report.get_time(); + + if (gem5_time < systemc_time) { + std::cerr << " (<) "; + } else if (gem5_time > systemc_time) { + std::cerr << " (!) "; + } else { + std::cerr << " (=) "; + } + + std::cerr << ": " << report.get_msg_type() + << ' ' << report.get_msg() << '\n'; +} + +int +sc_main(int argc, char **argv) +{ + sc_core::sc_report_handler::set_handler(reportHandler); + + SimControl sim_control("gem5", argc, argv); + Target *memory; + + filename = "m5out/stats-systemc.txt"; + + tlm::tlm_initiator_socket <> *mem_port = + dynamic_cast *>( + sc_core::sc_find_object("gem5.memory") + ); + + if (mem_port) { + SC_REPORT_INFO("sc_main", "Port Found"); + unsigned long long int size = 512*1024*1024ULL; + memory = new Target("memory", + sim_control.getDebugFlag(), + size, + sim_control.getOffset()); + + memory->socket.bind(*mem_port); + } else { + SC_REPORT_FATAL("sc_main", "Port Not Found"); + std::exit(EXIT_FAILURE); + } + + sc_core::sc_start(); + + SC_REPORT_INFO("sc_main", "End of Simulation"); + + CxxConfig::statsDump(); + + return EXIT_SUCCESS; +} diff --git a/util/tlm/main.cc b/util/tlm/sim_control.cc rename from util/tlm/main.cc rename to util/tlm/sim_control.cc --- a/util/tlm/main.cc +++ b/util/tlm/sim_control.cc @@ -2,6 +2,9 @@ * Copyright (c) 2015, University of Kaiserslautern * All rights reserved. * + * Copyright (c) 2016, TU Dresden + * All rights reserved. + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are * met: @@ -31,6 +34,7 @@ * * Authors: Matthias Jung * Abdul Mutaal Ahmad + * Christian Menard */ /** @@ -57,8 +61,7 @@ #include "cpu/base.hh" #include "sc_logger.hh" #include "sc_module.hh" -#include "sc_port.hh" -#include "sc_target.hh" +#include "sc_slave_port.hh" #include "sim/cxx_config_ini.hh" #include "sim/cxx_manager.hh" #include "sim/init_signals.hh" @@ -66,62 +69,34 @@ #include "sim/simulate.hh" #include "sim/stat_control.hh" #include "sim/system.hh" +#include "sim_control.hh" #include "stats.hh" -// Defining global string variable decalred in stats.hh -std::string filename; - -void usage(const std::string &prog_name) +void +usage(const std::string& prog_name) { - std::cerr << "Usage: " << prog_name << ( - " [