diff --git a/util/tlm/examples/master_port/tlm.py b/util/tlm/examples/master_port/tlm.py new file mode 100644 --- /dev/null +++ b/util/tlm/examples/master_port/tlm.py @@ -0,0 +1,80 @@ +# +# Copyright (c) 2016, TU Dresden +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# 3. Neither the name of the copyright holder nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER +# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# date: 23.05.2016 +# author: Christian Menard +# + +import m5 +from m5.objects import * + +import os + +# Base System Architecture: +# +-----+ ^ +# | TLM | | TLM World +# +--+--+ | (see main.cc) +# | v +# +----------v-----------+ External Port (see sc_master_port.*) +# | Membus | ^ +# +----------+-----------+ | +# | | gem5 World +# +---v----+ | +# | Memory | | +# +--------+ v +# + +# Create a system with a Crossbar and a simple Memory: +system = System() +system.membus = IOXBar(width = 16) +system.physmem = SimpleMemory(range = AddrRange('512MB')) +system.clk_domain = SrcClockDomain(clock = '1.5GHz', + voltage_domain = VoltageDomain(voltage = '1V')) + +#need a dummy cpu +#system.cpu = TrafficGen(config_file= "tgen.cfg") + +# Create a external TLM port: +system.tlm = ExternalMaster() +system.tlm.port_type = "tlm_master" +system.tlm.port_data = "memory" + +# Route the connections: +#system.cpu.port = system.membus.slave +system.system_port = system.membus.slave +system.physmem.port = system.membus.master +system.tlm.port = system.membus.slave +system.mem_mode = 'timing' + +# Start the simulation: +root = Root(full_system = False, system = system) +m5.instantiate() +m5.simulate() diff --git a/util/tlm/examples/master_port/main.cc b/util/tlm/examples/master_port/main.cc new file mode 100644 --- /dev/null +++ b/util/tlm/examples/master_port/main.cc @@ -0,0 +1,235 @@ +/* + * Copyright (c) 2016, TU Dresden + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * @date 25.05.2016 + * @author Christian Menard + */ + +#include +#include + +#include +#include +#include +#include +#include + +#include "sc_master_port.hh" +#include "sc_mm.hh" +#include "sim_control.hh" +#include "stats.hh" + +// Defining global string variable decalred in stats.hh +std::string filename; + +void +reportHandler(const sc_core::sc_report& report, + const sc_core::sc_actions& actions) +{ + uint64_t systemc_time = report.get_time().value(); + uint64_t gem5_time = curTick(); + + std::cerr << report.get_time(); + + if (gem5_time < systemc_time) { + std::cerr << " (<) "; + } else if (gem5_time > systemc_time) { + std::cerr << " (!) "; + } else { + std::cerr << " (=) "; + } + + std::cerr << ": " << report.get_msg_type() << ' ' << report.get_msg() + << '\n'; +} + +class TrafficGen : public sc_core::sc_module +{ + private: + MemoryManager mm; + + tlm::tlm_generic_payload* requestInProgress; + + uint32_t dataBuffer; + + sc_core::sc_event endRequestEvent; + + tlm_utils::peq_with_cb_and_phase peq; + + public: + tlm_utils::simple_initiator_socket socket; + + SC_CTOR(TrafficGen) + : socket("socket") + , requestInProgress(0), + peq(this, &TrafficGen::peq_cb) + { + socket.register_nb_transport_bw(this, &TrafficGen::nb_transport_bw); + SC_THREAD(process); + } + + void process() + { + srand(time(NULL)); + + unsigned const memSize = (1 << 10); // 512 MB + + while (true) { + + wait(sc_core::sc_time(rand() % 100, sc_core::SC_NS)); + + auto trans = mm.allocate(); + trans->acquire(); + + std::string cmdStr; + if (rand() % 2) // Generate a write request? + { + cmdStr = "write"; + trans->set_command(tlm::TLM_WRITE_COMMAND); + dataBuffer = rand(); + } else { + cmdStr = "read"; + trans->set_command(tlm::TLM_READ_COMMAND); + } + + trans->set_data_ptr(reinterpret_cast(&dataBuffer)); + trans->set_address(rand() % memSize); + trans->set_data_length(4); + trans->set_streaming_width(4); + trans->set_byte_enable_ptr(0); + trans->set_dmi_allowed(0); + trans->set_response_status(tlm::TLM_INCOMPLETE_RESPONSE); + + // honor the BEGIN_REQ/END_REQ exclusion rule + if (requestInProgress) + sc_core::wait(endRequestEvent); + + std::stringstream ss; + ss << "Send " << cmdStr << " request @0x" << std::hex + << trans->get_address(); + SC_REPORT_INFO("Traffic Generator", ss.str().c_str()); + + // send the request + requestInProgress = trans; + tlm::tlm_phase phase = tlm::BEGIN_REQ; + auto delay = sc_core::SC_ZERO_TIME; + + auto status = socket->nb_transport_fw(*trans, phase, delay); + + // Check status + if (status == tlm::TLM_UPDATED) { + peq.notify(*trans, phase, delay); + } else if (status == tlm::TLM_COMPLETED) { + requestInProgress = 0; + checkTransaction(*trans); + SC_REPORT_INFO("Traffic Generator", "request completed"); + trans->release(); + } + } + } + + void peq_cb(tlm::tlm_generic_payload& trans, const tlm::tlm_phase& phase) + { + if (phase == tlm::END_REQ || + (&trans == requestInProgress && phase == tlm::BEGIN_RESP)) { + // The end of the BEGIN_REQ phase + requestInProgress = 0; + endRequestEvent.notify(); + } else if (phase == tlm::BEGIN_REQ || phase == tlm::END_RESP) + SC_REPORT_FATAL("TLM-2", + "Illegal transaction phase received by initiator"); + + if (phase == tlm::BEGIN_RESP) { + checkTransaction(trans); + SC_REPORT_INFO("Traffic Generator", "received response"); + + // Send end response + tlm::tlm_phase fw_phase = tlm::END_RESP; + + // stress the retry mechanism by deferring the response + auto delay = sc_core::sc_time(rand() % 50, sc_core::SC_NS); + socket->nb_transport_fw(trans, fw_phase, delay); + trans.release(); + } + } + + void checkTransaction(tlm::tlm_generic_payload& trans) + { + if (trans.is_response_error()) { + char txt[100]; + sprintf(txt, + "Transaction returned with error, response status = %s", + trans.get_response_string().c_str()); + SC_REPORT_ERROR("TLM-2", txt); + } + } + + virtual tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload& trans, + tlm::tlm_phase& phase, + sc_core::sc_time& delay) + { + peq.notify(trans, phase, delay); + return tlm::TLM_ACCEPTED; + } +}; + +int +sc_main(int argc, char** argv) +{ + sc_core::sc_report_handler::set_handler(reportHandler); + + SimControl sim_control("gem5", argc, argv); + TrafficGen traffic_gen("traffic_gen"); + + filename = "m5out/stats-systemc.txt"; + + tlm::tlm_target_socket<>* mem_port = + dynamic_cast*>( + sc_core::sc_find_object("gem5.memory")); + + if (mem_port) { + SC_REPORT_INFO("sc_main", "Port Found"); + traffic_gen.socket.bind(*mem_port); + } else { + SC_REPORT_FATAL("sc_main", "Port Not Found"); + std::exit(EXIT_FAILURE); + } + + std::cout << "Starting sc_main" << std::endl; + + sc_core::sc_start(); // Run to end of simulation + + SC_REPORT_INFO("sc_main", "End of Simulation"); + + CxxConfig::statsDump(); + + return EXIT_SUCCESS; +} diff --git a/util/tlm/examples/slave_port/Makefile b/util/tlm/examples/slave_port/Makefile --- a/util/tlm/examples/slave_port/Makefile +++ b/util/tlm/examples/slave_port/Makefile @@ -48,7 +48,11 @@ CXXFLAGS += -I$(SYSTEMC_INC) -L$(SYSTEMC_LIB) CXXFLAGS += -std=c++0x CXXFLAGS += -g -CXXFLAGS += -DSC_INCLUDE_DYNAMIC_PROCESSES -DDEBUG -DTRACING_ON +CXXFLAGS += -DSC_INCLUDE_DYNAMIC_PROCESSES -DTRACING_ON + +ifeq ($(VARIANT), debug) + CXXFLAGS += -DDEBUG +endif LIBS = -lgem5_$(VARIANT) -lsystemc @@ -67,17 +71,20 @@ sc_ext.o: ../../sc_ext.cc ../../sc_ext.hh sc_slave_port.o: ../../sc_slave_port.cc ../../sc_slave_port.hh \ ../../payload_event.hh +sc_master_port.o: ../../sc_master_port.cc ../../sc_master_port.hh \ + ../../payload_event.hh sc_target.o: sc_target.cc sc_target.hh stats.o: ../../../systemc/stats.cc ../../../systemc/stats.hh sim_control.o: ../../sim_control.cc ../../sim_control.hh \ - ../../sc_slave_port.hh + ../../sc_slave_port.hh ../../sc_master_port.hh main.o: main.cc ../../../systemc/sc_logger.hh ../../../systemc/sc_module.hh \ ../../../systemc/stats.hh gem5.$(VARIANT).sc: main.o ../../../systemc/stats.o \ ../../../systemc/sc_gem5_control.o ../../../systemc/sc_logger.o \ ../../../systemc/sc_module.o ../../sc_mm.o ../../sc_ext.o \ - ../../sc_slave_port.o ../../sim_control.o sc_target.o + ../../sc_slave_port.o ../../sc_master_port.o ../../sim_control.o \ + sc_target.o $(CXX) $(CXXFLAGS) -o $@ $^ $(LIBS) clean: diff --git a/util/tlm/sc_master_port.hh b/util/tlm/sc_master_port.hh new file mode 100644 --- /dev/null +++ b/util/tlm/sc_master_port.hh @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2016, TU Dresden + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * @date 23.05.2016 + * @author Christian Menard + */ + +#pragma once + +#include +#include + +#include + +#include +#include +#include + +namespace Gem5SystemC { + +class MasterPort : public ExternalMaster::Port +{ + private: + struct TlmSenderState : public Packet::SenderState + { + tlm::tlm_generic_payload& trans; + TlmSenderState(tlm::tlm_generic_payload& trans) + : trans(trans) + { + } + }; + + tlm_utils::peq_with_cb_and_phase peq; + + bool waitForRetry; + tlm::tlm_generic_payload* pendingRequest; + + bool needToSendRetry; + + bool responseInProgress; + + // Keep a reference to the gem5 SystemC module + Module& module; + + public: + tlm_utils::simple_target_socket tSocket; + + protected: + // payload event call back + void peq_cb(tlm::tlm_generic_payload& trans, const tlm::tlm_phase& phase); + + // The TLM target interface + tlm::tlm_sync_enum nb_transport_fw(tlm::tlm_generic_payload& trans, + tlm::tlm_phase& phase, + sc_core::sc_time& t); + void b_transport(tlm::tlm_generic_payload& trans, sc_core::sc_time& t); + unsigned int transport_dbg(tlm::tlm_generic_payload& trans); + bool get_direct_mem_ptr(tlm::tlm_generic_payload& trans, + tlm::tlm_dmi& dmi_data); + + // Gem5 MasterPort interface + bool recvTimingResp(PacketPtr pkt); + void recvReqRetry(); + void recvRangeChange(); + + public: + MasterPort(const std::string& name_, + const std::string& systemc_name, + ExternalMaster& owner_, + Module& module); + + static void registerPortHandler(Module& module); + + friend PayloadEvent; + + private: + void sendEndReq(tlm::tlm_generic_payload& trans); + tlm::tlm_sync_enum sendBeginResp(tlm::tlm_generic_payload& trans, + sc_core::sc_time& delay); + + void handleBeginReq(tlm::tlm_generic_payload& trans); + void handleEndResp(tlm::tlm_generic_payload& trans); + + PacketPtr generatePacket(tlm::tlm_generic_payload& trans); + void destroyPacket(PacketPtr pkt); + + void checkTransaction(tlm::tlm_generic_payload& trans); +}; +} diff --git a/util/tlm/sc_master_port.cc b/util/tlm/sc_master_port.cc new file mode 100644 --- /dev/null +++ b/util/tlm/sc_master_port.cc @@ -0,0 +1,356 @@ +/* + * Copyright (c) 2016, TU Dresden + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * @date 23.05.2016 + * @author Christian Menard + */ + +#include "params/ExternalMaster.hh" +#include "sc_master_port.hh" +#include "sim/system.hh" + +namespace Gem5SystemC +{ + +PacketPtr +MasterPort::generatePacket(tlm::tlm_generic_payload& trans) +{ + Request::Flags flags; + auto req = new Request(trans.get_address(), trans.get_data_length(), flags, + owner.masterId); + + MemCmd cmd; + + switch (trans.get_command()) { + case tlm::TLM_READ_COMMAND: + cmd = MemCmd::ReadReq; + break; + case tlm::TLM_WRITE_COMMAND: + cmd = MemCmd::WriteReq; + break; + default: + SC_REPORT_FATAL("MasterPort", + "received transaction with unsupported command"); + } + + auto pkt = new Packet(req, cmd); + pkt->dataStatic(trans.get_data_ptr()); + + return pkt; +} + +void +MasterPort::destroyPacket(PacketPtr pkt) +{ + delete pkt; +} + +MasterPort::MasterPort(const std::string& name_, + const std::string& systemc_name, + ExternalMaster& owner_, + Module& module) + : ExternalMaster::Port(name_, owner_) + , tSocket(systemc_name.c_str()) + , peq(this, &MasterPort::peq_cb) + , waitForRetry(false) + , pendingRequest(nullptr) + , needToSendRetry(false) + , responseInProgress(false) + , module(module) +{ + auto system = + reinterpret_cast(owner_.params())->system; + + /* + * Register the TLM non-blocking interface when using gem5 Timing mode and + * the TLM blocking interface when using the gem5 Atomic mode. + * Then the magic (TM) in simple_target_socket automatically transforms + * non-blocking in blocking transactions and vice versa. + */ + if (system->isTimingMode()) { + SC_REPORT_INFO("MasterPort", "register non-blocking interface"); + tSocket.register_nb_transport_fw(this, + &MasterPort::nb_transport_fw); + } else if (system->isAtomicMode()) { + SC_REPORT_INFO("MasterPort", "register blocking interface"); + tSocket.register_b_transport(this, &MasterPort::b_transport); + } else { + panic("gem5 operates neither in Timing nor in Atomic mode"); + } + + tSocket.register_transport_dbg(this, &MasterPort::transport_dbg); +} + +void +MasterPort::checkTransaction(tlm::tlm_generic_payload& trans) +{ + if (trans.is_response_error()) { + char txt[100]; + sprintf(txt, + "Transaction returned with error, response status = %s", + trans.get_response_string().c_str()); + SC_REPORT_ERROR("TLM-2", txt); + } +} + +tlm::tlm_sync_enum +MasterPort::nb_transport_fw(tlm::tlm_generic_payload& trans, + tlm::tlm_phase& phase, sc_core::sc_time& delay) +{ + uint64_t adr = trans.get_address(); + unsigned len = trans.get_data_length(); + unsigned char* byteEnable = trans.get_byte_enable_ptr(); + unsigned width = trans.get_streaming_width(); + + // check the transaction attributes for unsupported features ... + if (byteEnable != 0) { + trans.set_response_status(tlm::TLM_BYTE_ENABLE_ERROR_RESPONSE); + return tlm::TLM_COMPLETED; + } + if (len > 4 || width < len) { + trans.set_response_status(tlm::TLM_BURST_ERROR_RESPONSE); + return tlm::TLM_COMPLETED; + } + + // ... and queue the valid transaction + peq.notify(trans, phase, delay); + return tlm::TLM_ACCEPTED; +} + +void +MasterPort::peq_cb(tlm::tlm_generic_payload& trans, + const tlm::tlm_phase& phase) +{ + // catch up with SystemC time + module.catchup(); + assert(curTick() == sc_core::sc_time_stamp().value()); + + switch (phase) { + case tlm::BEGIN_REQ: + handleBeginReq(trans); + break; + case tlm::END_RESP: + handleEndResp(trans); + break; + default: + panic("unimplemented phase in callback"); + } + + // the functions called above may have scheduled gem5 events + // -> notify the event loop handler + module.notify(); +} + +void +MasterPort::handleBeginReq(tlm::tlm_generic_payload& trans) +{ + sc_assert(!waitForRetry); + sc_assert(pendingRequest == nullptr); + + trans.acquire(); + auto pkt = generatePacket(trans); + + auto tlmSenderState = new TlmSenderState(trans); + pkt->pushSenderState(tlmSenderState); + + if (sendTimingReq(pkt)) { // port is free -> send END_REQ immediately + sendEndReq(trans); + } else { // port is blocked -> wait for retry before sending END_REQ + waitForRetry = true; + pendingRequest = &trans; + } +} + +void +MasterPort::handleEndResp(tlm::tlm_generic_payload& trans) +{ + sc_assert(responseInProgress); + + responseInProgress = false; + + checkTransaction(trans); + + if (needToSendRetry) { + sendRetryResp(); + needToSendRetry = false; + } + + trans.release(); +} + +void +MasterPort::sendEndReq(tlm::tlm_generic_payload& trans) +{ + tlm::tlm_phase phase = tlm::END_REQ; + auto delay = sc_core::SC_ZERO_TIME; + + auto status = tSocket->nb_transport_bw(trans, phase, delay); + panic_if(status != tlm::TLM_ACCEPTED, + "Unexpected status after sending END_REQ"); +} + +void +MasterPort::b_transport(tlm::tlm_generic_payload& trans, + sc_core::sc_time& t) +{ + auto pkt = generatePacket(trans); + + // send an atomic request to gem5 + Tick ticks = sendAtomic(pkt); + panic_if(!pkt->isResponse(), "Packet sending failed!\n"); + + // one tick is a pico second + auto delay = sc_core::sc_time(static_cast(ticks), sc_core::SC_PS); + + // update time + t += delay; + + destroyPacket(pkt); + + trans.set_response_status(tlm::TLM_OK_RESPONSE); +} + +unsigned int +MasterPort::transport_dbg(tlm::tlm_generic_payload& trans) +{ + auto pkt = generatePacket(trans); + + sendFunctional(pkt); + + destroyPacket(pkt); + + return trans.get_data_length(); +} + +bool +MasterPort::get_direct_mem_ptr(tlm::tlm_generic_payload& trans, + tlm::tlm_dmi& dmi_data) +{ + return false; +} + +bool +MasterPort::recvTimingResp(PacketPtr pkt) +{ + // exclusion rule + // We need to Wait for END_RESP before sending next BEGIN_RESP + if (responseInProgress) { + sc_assert(!needToSendRetry); + needToSendRetry = true; + return false; + } + + sc_assert(pkt->isResponse()); + responseInProgress = true; + + // pay for annotaded transport delays + auto delay = + sc_core::sc_time::from_value(pkt->payloadDelay + pkt->headerDelay); + + auto tlmSenderState = + reinterpret_cast(pkt->popSenderState()); + auto& trans = tlmSenderState->trans; + + // clean up + delete tlmSenderState; + destroyPacket(pkt); + + auto status = sendBeginResp(trans, delay); + + if (status == tlm::TLM_UPDATED) { + responseInProgress = false; + trans.release(); + } + + return true; +} + +tlm::tlm_sync_enum +MasterPort::sendBeginResp(tlm::tlm_generic_payload& trans, + sc_core::sc_time& delay) +{ + tlm::tlm_phase phase = tlm::BEGIN_RESP; + + trans.set_response_status(tlm::TLM_OK_RESPONSE); + + auto status = tSocket->nb_transport_bw(trans, phase, delay); + panic_if(status != tlm::TLM_ACCEPTED && status != tlm::TLM_COMPLETED, + "Unexpected status after sending BEGIN_RESP"); + + return status; +} + +void +MasterPort::recvReqRetry() +{ + sc_assert(waitForRetry); + sc_assert(pendingRequest != nullptr); + + auto& trans = *pendingRequest; + + waitForRetry = false; + pendingRequest = nullptr; + + // retry + handleBeginReq(trans); +} + +void +MasterPort::recvRangeChange() +{ + SC_REPORT_WARNING("MasterPort", + "received address range change but ignored it"); +} + +class MasterPortHandler : public ExternalMaster::Handler +{ + Module& module; + + public: + MasterPortHandler(Module& module) : module(module) {} + + ExternalMaster::Port* getExternalPort(const std::string& name, + ExternalMaster& owner, + const std::string& port_data) + { + // This will make a new initiatiator port + return new MasterPort(name, port_data, owner, module); + } +}; + +void +MasterPort::registerPortHandler(Module& module) +{ + ExternalMaster::registerHandler("tlm_master", + new MasterPortHandler(module)); +} + +} // namespace Gem5SystemC diff --git a/util/tlm/sim_control.cc b/util/tlm/sim_control.cc --- a/util/tlm/sim_control.cc +++ b/util/tlm/sim_control.cc @@ -60,6 +60,7 @@ #include "base/trace.hh" #include "cpu/base.hh" #include "sc_logger.hh" +#include "sc_master_port.hh" #include "sc_module.hh" #include "sc_slave_port.hh" #include "sim/cxx_config_ini.hh" @@ -109,6 +110,7 @@ cxxConfigInit(); Gem5SystemC::SlavePort::registerPortHandler(); + Gem5SystemC::MasterPort::registerPortHandler(*this); Trace::setDebugLogger(&logger); # HG changeset patch # User Christian Menard # Date 1468414545 -7200 # Wed Jul 13 14:55:45 2016 +0200 # Node ID 62d9e90bec32fcd0d6c8605ff95ab1676c96d3c5 # Parent 9da2132c2e7ad97ba7c96fb077bc1c7f1b35881b misc: add a TLM to Gem5 Master Port implementation diff --git a/util/tlm/README b/util/tlm/README --- a/util/tlm/README +++ b/util/tlm/README @@ -6,8 +6,11 @@ Files: sc_slave_port.{cc,hh} -- transactor that translates beween gem5 and tlm + sc_master_port.{cc,hh} -- transactor that translates beween tlm and gem5 sc_mm.{cc,hh} -- implementation of a tlm memory manager sc_ext.{cc,hh} -- a TLM extension that carries the gem5 packet + sim_control.{cc,hh} -- Central module that manages SystemC/gem5 + co-simulation example/slave_port/main.cc -- demonstration of the slave port example/slave_port/sc_target.{cc,hh} -- an example TLM LT/AT memory module @@ -15,6 +18,9 @@ example/slave_port/tgen.cfg -- configuration file for the traceplayer + example/master_port/main.cc -- demonstration of the master port + example/master_port/tlm.py -- simple gem5 configuration + Other Files will be used from utils/systemc example: sc_logger.{cc,hh}, @@ -23,8 +29,8 @@ stats.{cc,hh} -I. Traffic Generator Setup -========================== +I. Slave Port: Traffic Generator Setup +====================================== To build: @@ -69,8 +75,8 @@ > ./gem5.opt.sc m5out/config.ini -e 1000000 -d ExternalPort -II. Full System Setup -===================== +II. Slave Port: Full System Setup +================================= Build gem5 as discribed in Section I. Then, make a config file for the C++-configured gem5 using normal gem5 @@ -98,9 +104,8 @@ For conveniance a run_gem5.sh file holds all those commands - -III. Elastic Trace Setup -======================== +III. Slave Port: Elastic Trace Setup +==================================== Elastic traces can also be replayed into the SystemC world. For more information on elastic traces please refer to: @@ -120,3 +125,32 @@ Then: > ./gem5.opt.sc m5out/config.ini + +IV. Master Port: Traffic Generator Setup +======================================== + +Build normal gem5 and the gem5 library (see I). + +> cd examples/master_port + +Set a proper LD_LIBRARY_PATH e.g. for bash: +> export LD_LIBRARY_PATH="$LD_LIBRARY_PATH:/path/to/gem5/build/ARM/" + +Then edit the Makefile to set the paths for SystemC and run make + +> make + +Similar to I. the simulation can be set up with this command: + +> ../../../../build/ARM/gem5.opt ./tlm.py + +The message "fatal: Can't find port handler type 'tlm_master'" is okay. +The configuration will be stored in the m5out/ directory + +Then run the suimulation: + +> ./gem5.opt.sc m5out/config.ini + +To see more information use debug flags, i.e. XBar or MemoryAccess + +> ./gem5.opt.sc m5out/config.ini -d XBar -d MemoryAccess diff --git a/util/tlm/examples/master_port/Makefile b/util/tlm/examples/master_port/Makefile new file mode 100644 --- /dev/null +++ b/util/tlm/examples/master_port/Makefile @@ -0,0 +1,89 @@ +# Copyright (c) 2016, TU Dresden +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# 3. Neither the name of the copyright holder nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER +# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Christian Menard + + +ARCH = ARM +VARIANT = opt + +SYSTEMC_INC = /opt/systemc/include +SYSTEMC_LIB = /opt/systemc/lib-linux + +CXXFLAGS = -I../../../../build/$(ARCH) -L../../../../build/$(ARCH) +CXXFLAGS += -I../../../systemc/ +CXXFLAGS += -I../../ +CXXFLAGS += -I$(SYSTEMC_INC) -L$(SYSTEMC_LIB) +CXXFLAGS += -std=c++0x +CXXFLAGS += -g +CXXFLAGS += -DSC_INCLUDE_DYNAMIC_PROCESSES -DTRACING_ON + +ifeq ($(VARIANT), debug) + CXXFLAGS += -DDEBUG +endif + +LIBS = -lgem5_$(VARIANT) -lsystemc + +ALL = gem5.$(VARIANT).sc + +all: $(ALL) + +.cc.o: + $(CXX) $(CXXFLAGS) -c -o $@ $< + +sc_gem5_control.o: ../../../systemc/sc_gem5_control.cc \ + ../../../systemc/sc_gem5_control.hh +sc_logger.o: ../../../systemc/sc_logger.cc ../../../systemc/sc_logger.hh +sc_module.o: ../../../systemc/sc_module.cc ../../../systemc/sc_module.hh +sc_mm.o: ../../sc_mm.cc ../../sc_mm.hh +sc_ext.o: ../../sc_ext.cc ../../sc_ext.hh +sc_master_port.o: ../../sc_master_port.cc ../../sc_master_port.hh \ + ../../payload_event.hh +sc_master_port.o: ../../sc_master_port.cc ../../sc_master_port.hh \ + ../../payload_event.hh +sc_slave_port.o: ../../sc_slave_port.cc ../../sc_slave_port.hh \ + ../../payload_event.hh +stats.o: ../../../systemc/stats.cc ../../../systemc/stats.hh +sim_control.o: ../../sim_control.cc ../../sim_control.hh ../../ \ + ../../sc_slave_port.hh ../../sc_master_port.hh +main.o: main.cc ../../../systemc/sc_logger.hh ../../../systemc/sc_module.hh \ + ../../../systemc/stats.hh + +gem5.$(VARIANT).sc: main.o ../../../systemc/stats.o \ + ../../../systemc/sc_gem5_control.o ../../../systemc/sc_logger.o \ + ../../../systemc/sc_module.o ../../sc_mm.o ../../sc_ext.o \ + ../../sc_slave_port.o ../../sc_master_port.o ../../sim_control.o + $(CXX) $(CXXFLAGS) -o $@ $^ $(LIBS) + +clean: + $(RM) $(ALL) + $(RM) *.o + $(RM) ../../*.o + $(RM) -r m5out