# Node ID 707f0168d0fb0cfbfa0a31ff54132f1693f81197
# Parent  0913e00e93153a2e3708877a35fb9541cf04e28b
diff --git a/src/arch/SConscript b/src/arch/SConscript
--- a/src/arch/SConscript
+++ b/src/arch/SConscript
@@ -71,6 +71,7 @@
 if env['BUILD_GPU']:
     gpu_isa_switch_hdrs = Split('''
             gpu_decoder.hh
+            gpu_isa.hh
             gpu_types.hh
             ''')
 
diff --git a/src/arch/hsail/gpu_isa.hh b/src/arch/hsail/gpu_isa.hh
new file mode 100644
--- /dev/null
+++ b/src/arch/hsail/gpu_isa.hh
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2016 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * For use for simulation and test purposes only
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Anthony Gutierrez
+ */
+
+#ifndef __ARCH_HSAIL_GPU_ISA_HH__
+#define __ARCH_HSAIL_GPU_ISA_HH__
+
+#include <cstdint>
+
+#include "base/misc.hh"
+#include "gpu-compute/misc.hh"
+
+class Wavefront;
+
+namespace HsailISA
+{
+    typedef uint64_t MiscReg;
+
+    class GPUISA
+    {
+      public:
+        GPUISA(Wavefront &wf) : wavefront(wf)
+        {
+        }
+
+        void
+        writeMiscReg(int opIdx, MiscReg operandVal)
+        {
+            fatal("HSAIL does not implement misc registers yet\n");
+        }
+
+        MiscReg
+        readMiscReg(int opIdx) const
+        {
+            fatal("HSAIL does not implement misc registers yet\n");
+        }
+
+        bool hasScalarUnit() const { return false; }
+
+        uint32_t
+        advancePC(uint32_t old_pc, GPUDynInstPtr gpuDynInst)
+        {
+            return old_pc + 1;
+        }
+
+      private:
+        Wavefront &wavefront;
+    };
+}
+
+#endif // __ARCH_HSAIL_GPU_ISA_HH__
diff --git a/src/gpu-compute/gpu_exec_context.hh b/src/gpu-compute/gpu_exec_context.hh
--- a/src/gpu-compute/gpu_exec_context.hh
+++ b/src/gpu-compute/gpu_exec_context.hh
@@ -36,6 +36,9 @@
 #ifndef __GPU_EXEC_CONTEXT_HH__
 #define __GPU_EXEC_CONTEXT_HH__
 
+#include "arch/gpu_isa.hh"
+#include "config/the_gpu_isa.hh"
+
 class ComputeUnit;
 class Wavefront;
 
@@ -46,9 +49,13 @@
     Wavefront* wavefront();
     ComputeUnit* computeUnit();
 
+    TheGpuISA::MiscReg readMiscReg(int opIdx) const;
+    void writeMiscReg(int opIdx, TheGpuISA::MiscReg operandVal);
+
   protected:
     ComputeUnit *cu;
     Wavefront *wf;
+    TheGpuISA::GPUISA &gpuISA;
 };
 
 #endif // __GPU_EXEC_CONTEXT_HH__
diff --git a/src/gpu-compute/gpu_exec_context.cc b/src/gpu-compute/gpu_exec_context.cc
--- a/src/gpu-compute/gpu_exec_context.cc
+++ b/src/gpu-compute/gpu_exec_context.cc
@@ -34,9 +34,10 @@
  */
 
 #include "gpu-compute/gpu_exec_context.hh"
+#include "gpu-compute/wavefront.hh"
 
 GPUExecContext::GPUExecContext(ComputeUnit *_cu, Wavefront *_wf)
-    : cu(_cu), wf(_wf)
+    : cu(_cu), wf(_wf), gpuISA(_wf->gpuISA())
 {
 }
 
@@ -51,3 +52,15 @@
 {
     return wf;
 }
+
+TheGpuISA::MiscReg
+GPUExecContext::readMiscReg(int opIdx) const
+{
+    return gpuISA.readMiscReg(opIdx);
+}
+
+void
+GPUExecContext::writeMiscReg(int opIdx, TheGpuISA::MiscReg operandVal)
+{
+    gpuISA.writeMiscReg(opIdx, operandVal);
+}
diff --git a/src/gpu-compute/wavefront.hh b/src/gpu-compute/wavefront.hh
--- a/src/gpu-compute/wavefront.hh
+++ b/src/gpu-compute/wavefront.hh
@@ -42,6 +42,7 @@
 #include <stack>
 #include <vector>
 
+#include "arch/gpu_isa.hh"
 #include "base/misc.hh"
 #include "base/types.hh"
 #include "gpu-compute/condition_register_state.hh"
@@ -372,7 +373,14 @@
      */
     void setContext(const void *in);
 
+    TheGpuISA::GPUISA&
+    gpuISA()
+    {
+        return _gpuISA;
+    }
+
   private:
+    TheGpuISA::GPUISA _gpuISA;
     /**
      * Stack containing Control Flow Graph nodes (i.e., kernel instructions)
      * to be visited by the wavefront, and the associated execution masks. The
diff --git a/src/gpu-compute/wavefront.cc b/src/gpu-compute/wavefront.cc
--- a/src/gpu-compute/wavefront.cc
+++ b/src/gpu-compute/wavefront.cc
@@ -49,7 +49,7 @@
 }
 
 Wavefront::Wavefront(const Params *p)
-  : SimObject(p), callArgMem(nullptr)
+  : SimObject(p), callArgMem(nullptr), _gpuISA(*this)
 {
     lastTrace = 0;
     simdId = p->simdId;