# Node ID 7c1853b9eb729b3f25441675ab48bc065e02736f
# Parent  a828fb65da675b51552d5a3cb97ee0c85c645c53
diff --git a/src/mem/DRAMCtrl.py b/src/mem/DRAMCtrl.py
--- a/src/mem/DRAMCtrl.py
+++ b/src/mem/DRAMCtrl.py
@@ -312,6 +312,74 @@
     # Second voltage range defined by some DRAMs
     VDD2 = Param.Voltage("0V", "2nd Voltage Range")
 
+
+# A single DDR3-1600 x64 channel (one command and address bus), with
+# timings based on a DDR3-1600 4 Gbit datasheet (Micron MT41J512M8) in
+# an 8x8 configuration.
+class DDR3_1866_x64(DRAMCtrl):
+    # size of device in bytes
+    device_size = '512MB'
+
+    # 8x8 configuration, 8 devices each with an 8-bit interface
+    device_bus_width = 8
+
+    # DDR3 is a BL8 device
+    burst_length = 8
+
+    # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
+    device_rowbuffer_size = '1kB'
+
+    # 8x8 configuration, so 8 devices
+    devices_per_rank = 8
+
+    # Use two ranks
+    ranks_per_channel = 2
+
+    # DDR3 has 8 banks in all configurations
+    banks_per_rank = 8
+
+    # 933 MHz
+    tCK = '1.0718114ns'
+
+    # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz
+    tBURST = '4.28725ns'
+
+    # DDR3-1866 13-13-13
+    tRCD = '13.93ns'
+    tCL = '13.93ns'
+    tRP = '13.93ns'
+    tRAS = '35ns'
+    tRRD = '6ns'
+    tXAW = '30ns'
+    activation_limit = 4
+    tRFC = '260ns'
+
+    tWR = '15ns'
+
+    # Greater of 4 CK or 7.5 ns
+    tWTR = '7.5ns'
+
+    # Greater of 4 CK or 7.5 ns
+    tRTP = '7.5ns'
+
+    # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
+    tRTW = '2.5ns'
+
+    # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
+    tCS = '2.5ns'
+
+    # <=85C, half for >85C
+    tREFI = '7.8us'
+
+    # Current values from datasheet
+    IDD0 = '75mA'
+    IDD2N = '50mA'
+    IDD3N = '57mA'
+    IDD4W = '165mA'
+    IDD4R = '187mA'
+    IDD5 = '220mA'
+    VDD = '1.5V'
+
 # A single DDR3-1600 x64 channel (one command and address bus), with
 # timings based on a DDR3-1600 4 Gbit datasheet (Micron MT41J512M8) in
 # an 8x8 configuration.
@@ -507,6 +575,34 @@
     IDD5 = '250mA'
     VDD = '1.5V'
 
+# A single DDR3-2400 x64 channel refining a selected subset of the
+# options for the DDR-1600 configuration, based on the same DDR3-1600
+# 4 Gbit datasheet (Micron MT41J512M8). Most parameters are kept
+# consistent across the two configurations.
+class DDR3_2400_x64(DDR3_1600_x64):
+    # 1200 MHz
+    tCK = '0.833ns'
+
+    # 8 beats across an x64 interface translates to 4 clocks @ 1066 MHz
+    tBURST = '3.333ns'
+
+    # DDR3-2400 13-13-13
+    tRCD = '10.83ns'
+    tCL = '10.83ns'
+    tRP = '10.83ns'
+    tRAS = '33ns'
+    tRRD = '5ns'
+    tXAW = '25ns'
+
+    # Current values from datasheet
+    IDD0 = '70mA'
+    IDD2N = '37mA'
+    IDD3N = '44mA'
+    IDD4W = '157mA'
+    IDD4R = '191mA'
+    IDD5 = '250mA'
+    VDD = '1.5V'
+
 # A single DDR4-2400 x64 channel (one command and address bus), with
 # timings based on a DDR4-2400 4 Gbit datasheet (Micron MT40A512M8)
 # in an 8x8 configuration.