diff -r 9c7b55faea5d src/arch/arm/isa.cc
--- a/src/arch/arm/isa.cc       Tue Apr 05 08:08:12 2016 -0500
+++ b/src/arch/arm/isa.cc       Thu Oct 13 18:42:40 2016 +0000
@@ -540,7 +540,8 @@
         warn_once("The ccsidr register isn't implemented and "
                 "always reads as 0.\n");
         break;
-      case MISCREG_CTR:
+      case MISCREG_CTR:                 // AArch32, ARMv7, top bit set
+      case MISCREG_CTR_EL0:             // AArch64
         {
             //all caches have the same line size in gem5
             //4 byte words in ARM