diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/system.terminal --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/system.terminal Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,112 +0,0 @@ -M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 - Got Configuration 623 - memsize 8000000 pages 4000 - First free page after ROM 0xFFFFFC0000018000 - HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000 - kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x2 - CPU Clock at 2000 MHz IntrClockFrequency=1024 - Booting with 2 processor(s) - KSP: 0x20043FE8 PTBR 0x20 - KSP: 0x20043FE8 PTBR 0x20 - Console Callback at 0x0, fixup at 0x0, crb offset: 0x790 - Memory cluster 0 [0 - 392] - Memory cluster 1 [392 - 15992] - Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000 - ConsoleDispatch at virt 100008D8 phys 188D8 val FFFFFC00000100A8 - Bootstraping CPU 1 with sp=0xFFFFFC0000076000 - unix_boot_mem ends at FFFFFC0000078000 - k_argc = 0 - jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067) - CallbackFixup 0 18000, t7=FFFFFC000070C000 - Entering slaveloop for cpu 1 my_rpb=FFFFFC0000018400 - Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006 - Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM - Major Options: SMP LEGACY_START VERBOSE_MCHECK - Command line: root=/dev/hda1 console=ttyS0 - memcluster 0, usage 1, start 0, end 392 - memcluster 1, usage 0, start 392, end 16384 - freeing pages 1069:16384 - reserving pages 1069:1070 - SMP: 2 CPUs probed -- cpu_present_mask = 3 - Built 1 zonelists - Kernel command line: root=/dev/hda1 console=ttyS0 - PID hash table entries: 1024 (order: 10, 32768 bytes) - Using epoch = 1900 - Console: colour dummy device 80x25 - Dentry cache hash table entries: 32768 (order: 5, 262144 bytes) - Inode-cache hash table entries: 16384 (order: 4, 131072 bytes) - Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init) - Mount-cache hash table entries: 512 - SMP starting up secondaries. - Slave CPU 1 console command START -SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb FFFFFC0000018400 my_rpb_phys 18400 - Brought up 2 CPUs - SMP: Total of 2 processors activated (8000.15 BogoMIPS). - NET: Registered protocol family 16 - EISA bus registered - pci: enabling save/restore of SRM state - SCSI subsystem initialized - srm_env: version 0.0.5 loaded successfully - Installing knfsd (copyright (C) 1996 okir@monad.swb.de). - Initializing Cryptographic API - rtc: Standard PC (1900) epoch (1900) detected - Real Time Clock Driver v1.12 - Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled - ttyS0 at I/O 0x3f8 (irq = 4) is a 8250 - io scheduler noop registered - io scheduler anticipatory registered - io scheduler deadline registered - io scheduler cfq registered - loop: loaded (max 8 devices) - nbd: registered device at major 43 - ns83820.c: National Semiconductor DP83820 10/100/1000 driver. - PCI: Setting latency timer of device 0000:00:01.0 to 64 - eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000 - eth0: enabling optical transceiver - eth0: using 64 bit addressing. - eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=h,sg - tun: Universal TUN/TAP device driver, 1.6 - tun: (C) 1999-2004 Max Krasnyansky - Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2 - ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx - PIIX4: IDE controller at PCI slot 0000:00:00.0 - PIIX4: chipset revision 0 - PIIX4: 100% native mode on irq 31 - PCI: Setting latency timer of device 0000:00:00.0 to 64 - ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA - ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA - hda: M5 IDE Disk, ATA DISK drive - hdb: M5 IDE Disk, ATA DISK drive - ide0 at 0x8410-0x8417,0x8422 on irq 31 - hda: max request size: 128KiB - hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33) - hda: cache flushes not supported - hda: hda1 - hdb: max request size: 128KiB - hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33) - hdb: cache flushes not supported - hdb: unknown partition table - mice: PS/2 mouse device common for all mice - NET: Registered protocol family 2 - IP route cache hash table entries: 4096 (order: 2, 32768 bytes) - TCP established hash table entries: 16384 (order: 5, 262144 bytes) - TCP bind hash table entries: 16384 (order: 5, 262144 bytes) - TCP: Hash tables configured (established 16384 bind 16384) - TCP reno registered - ip_conntrack version 2.1 (512 buckets, 4096 max) - 296 bytes per conntrack - ip_tables: (C) 2000-2002 Netfilter core team - arp_tables: (C) 2002 David S. Miller - TCP bic registered - Initializing IPsec netlink socket - NET: Registered protocol family 1 - NET: Registered protocol family 17 - NET: Registered protocol family 15 - Bridge firewalling registered - 802.1Q VLAN Support v1.8 Ben Greear - All bugs added by David S. Miller - VFS: Mounted root (ext2 filesystem) readonly. - Freeing unused kernel memory: 224k freed - init started: BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary -mounting filesystems... -EXT2-fs warning: checktime reached, running e2fsck is recommended - loading script... diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,1278 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=true -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=LinuxAlphaSystem -children=bridge clk_domain cpu cpu_clk_domain disk0 disk2 dvfs_handler intrctrl iobus iocache membus physmem simple_disk terminal tsunami voltage_domain -boot_cpu_frequency=500 -boot_osflags=root=/dev/hda1 console=ttyS0 -cache_line_size=64 -clk_domain=system.clk_domain -console=/arm/projectscratch/randd/systems/dist/binaries/console -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=atomic -mem_ranges=0:134217727 -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pal=/arm/projectscratch/randd/systems/dist/binaries/ts_osfpal -power_model=Null -readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh -symbolfile= -system_rev=1024 -system_type=34 -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.bridge] -type=Bridge -clk_domain=system.clk_domain -default_p_state=UNDEFINED -delay=50000 -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -ranges=8796093022208:18446744073709551615 -req_size=16 -resp_size=16 -master=system.iobus.slave[0] -slave=system.membus.master[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=AtomicSimpleCPU -children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -fastmem=false -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -simulate_data_stalls=false -simulate_inst_stalls=false -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -width=1 -workload= -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=4 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=4 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=1 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=1 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=4194304 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=4194304 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.disk0] -type=IdeDisk -children=image -delay=1000000 -driveID=master -eventq_index=0 -image=system.disk0.image - -[system.disk0.image] -type=CowDiskImage -children=child -child=system.disk0.image.child -eventq_index=0 -image_file= -read_only=false -table_size=65536 - -[system.disk0.image.child] -type=RawDiskImage -eventq_index=0 -image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img -read_only=true - -[system.disk2] -type=IdeDisk -children=image -delay=1000000 -driveID=master -eventq_index=0 -image=system.disk2.image - -[system.disk2.image] -type=CowDiskImage -children=child -child=system.disk2.image.child -eventq_index=0 -image_file= -read_only=false -table_size=65536 - -[system.disk2.image.child] -type=RawDiskImage -eventq_index=0 -image_file=/arm/projectscratch/randd/systems/dist/disks/linux-bigswap2.img -read_only=true - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.intrctrl] -type=IntrControl -eventq_index=0 -sys=system - -[system.iobus] -type=NoncoherentXBar -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=1 -frontend_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -response_latency=2 -use_default_range=false -width=16 -master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side -slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma - -[system.iocache] -type=Cache -children=tags -addr_ranges=0:134217727 -assoc=8 -clk_domain=system.clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=50 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=50 -sequential_access=false -size=1024 -system=system -tags=system.iocache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.iobus.master[27] -mem_side=system.membus.slave[2] - -[system.iocache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=50 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=1024 - -[system.membus] -type=CoherentXBar -children=badaddr_responder -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=Null -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side - -[system.membus.badaddr_responder] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=0 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=true -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.membus.default - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=0:134217727 -port=system.membus.master[1] - -[system.simple_disk] -type=SimpleDisk -children=disk -disk=system.simple_disk.disk -eventq_index=0 -system=system - -[system.simple_disk.disk] -type=RawDiskImage -eventq_index=0 -image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img -read_only=true - -[system.terminal] -type=Terminal -eventq_index=0 -intr_control=system.intrctrl -number=0 -output=true -port=3456 - -[system.tsunami] -type=Tsunami -children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip uart -eventq_index=0 -intrctrl=system.intrctrl -system=system - -[system.tsunami.backdoor] -type=AlphaBackdoor -clk_domain=system.clk_domain -cpu=system.cpu -default_p_state=UNDEFINED -disk=system.simple_disk -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804682956800 -pio_latency=100000 -platform=system.tsunami -power_model=Null -system=system -terminal=system.terminal -pio=system.iobus.master[24] - -[system.tsunami.cchip] -type=TsunamiCChip -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8803072344064 -pio_latency=100000 -power_model=Null -system=system -tsunami=system.tsunami -pio=system.iobus.master[0] - -[system.tsunami.ethernet] -type=NSGigE -BAR0=1 -BAR0LegacyIO=false -BAR0Size=256 -BAR1=0 -BAR1LegacyIO=false -BAR1Size=4096 -BAR2=0 -BAR2LegacyIO=false -BAR2Size=0 -BAR3=0 -BAR3LegacyIO=false -BAR3Size=0 -BAR4=0 -BAR4LegacyIO=false -BAR4Size=0 -BAR5=0 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=2 -Command=0 -DeviceID=34 -ExpansionROM=0 -HeaderType=0 -InterruptLine=30 -InterruptPin=1 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=52 -MinimumGrant=176 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=0 -Revision=0 -Status=656 -SubClassCode=0 -SubsystemID=0 -SubsystemVendorID=0 -VendorID=4107 -clk_domain=system.clk_domain -config_latency=20000 -default_p_state=UNDEFINED -dma_data_free=false -dma_desc_free=false -dma_no_allocate=true -dma_read_delay=0 -dma_read_factor=0 -dma_write_delay=0 -dma_write_factor=0 -eventq_index=0 -hardware_address=00:90:00:00:00:01 -host=system.tsunami.pchip -intr_delay=10000000 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_bus=0 -pci_dev=1 -pci_func=0 -pio_latency=30000 -power_model=Null -rss=false -rx_delay=1000000 -rx_fifo_size=524288 -rx_filter=true -rx_thread=false -system=system -tx_delay=1000000 -tx_fifo_size=524288 -tx_thread=false -dma=system.iobus.slave[2] -pio=system.iobus.master[26] - -[system.tsunami.fake_OROM] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8796093677568 -pio_latency=100000 -pio_size=393216 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[8] - -[system.tsunami.fake_ata0] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848432 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[19] - -[system.tsunami.fake_ata1] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848304 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[20] - -[system.tsunami.fake_pnp_addr] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848569 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[9] - -[system.tsunami.fake_pnp_read0] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848451 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[11] - -[system.tsunami.fake_pnp_read1] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848515 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[12] - -[system.tsunami.fake_pnp_read2] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848579 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[13] - -[system.tsunami.fake_pnp_read3] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848643 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[14] - -[system.tsunami.fake_pnp_read4] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848707 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[15] - -[system.tsunami.fake_pnp_read5] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848771 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[16] - -[system.tsunami.fake_pnp_read6] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848835 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[17] - -[system.tsunami.fake_pnp_read7] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848899 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[18] - -[system.tsunami.fake_pnp_write] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615850617 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[10] - -[system.tsunami.fake_ppc] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848891 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[7] - -[system.tsunami.fake_sm_chip] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848816 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[2] - -[system.tsunami.fake_uart1] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848696 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[3] - -[system.tsunami.fake_uart2] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848936 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[4] - -[system.tsunami.fake_uart3] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848680 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[5] - -[system.tsunami.fake_uart4] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848944 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[6] - -[system.tsunami.fb] -type=BadDevice -clk_domain=system.clk_domain -default_p_state=UNDEFINED -devicename=FrameBuffer -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848912 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[21] - -[system.tsunami.ide] -type=IdeController -BAR0=1 -BAR0LegacyIO=false -BAR0Size=8 -BAR1=1 -BAR1LegacyIO=false -BAR1Size=4 -BAR2=1 -BAR2LegacyIO=false -BAR2Size=8 -BAR3=1 -BAR3LegacyIO=false -BAR3Size=4 -BAR4=1 -BAR4LegacyIO=false -BAR4Size=16 -BAR5=1 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=1 -Command=0 -DeviceID=28945 -ExpansionROM=0 -HeaderType=0 -InterruptLine=31 -InterruptPin=1 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=0 -MinimumGrant=0 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=133 -Revision=0 -Status=640 -SubClassCode=1 -SubsystemID=0 -SubsystemVendorID=0 -VendorID=32902 -clk_domain=system.clk_domain -config_latency=20000 -ctrl_offset=0 -default_p_state=UNDEFINED -disks=system.disk0 system.disk2 -eventq_index=0 -host=system.tsunami.pchip -io_shift=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_bus=0 -pci_dev=0 -pci_func=0 -pio_latency=30000 -power_model=Null -system=system -dma=system.iobus.slave[1] -pio=system.iobus.master[25] - -[system.tsunami.io] -type=TsunamiIO -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -frequency=976562500 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615847936 -pio_latency=100000 -power_model=Null -system=system -time=Thu Jan 1 00:00:00 2009 -tsunami=system.tsunami -year_is_bcd=false -pio=system.iobus.master[22] - -[system.tsunami.pchip] -type=TsunamiPChip -clk_domain=system.clk_domain -conf_base=8804649402368 -conf_device_bits=8 -conf_size=16777216 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_dma_base=0 -pci_mem_base=8796093022208 -pci_pio_base=8804615847936 -pio_addr=8802535473152 -pio_latency=100000 -platform=system.tsunami -power_model=Null -system=system -tsunami=system.tsunami -pio=system.iobus.master[1] - -[system.tsunami.uart] -type=Uart8250 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848952 -pio_latency=100000 -platform=system.tsunami -power_model=Null -system=system -terminal=system.terminal -pio=system.iobus.master[23] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,5 +0,0 @@ -warn: Sockets disabled, not accepting terminal connections -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,15 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 19 2016 12:24:27 -gem5 executing on e108600-lin, pid 39612 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic - -Global frequency set at 1000000000000 ticks per second -info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1829331993500 because m5_exit instruction encountered diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,687 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 1.829332 # Number of seconds simulated -sim_ticks 1829332003500 # Number of ticks simulated -final_tick 1829332003500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2980615 # Simulator instruction rate (inst/s) -host_op_rate 2980613 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 90817249233 # Simulator tick rate (ticks/s) -host_mem_usage 334036 # Number of bytes of host memory used -host_seconds 20.14 # Real time elapsed on the host -sim_insts 60038469 # Number of instructions simulated -sim_ops 60038469 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 850496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 66835072 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 67686528 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 850496 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 850496 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7415744 # Number of bytes written to this memory -system.physmem.bytes_written::total 7415744 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13289 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1044298 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1057602 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115871 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115871 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 464922 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 36535234 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 525 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 37000680 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 464922 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 464922 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4053799 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4053799 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4053799 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 464922 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 36535234 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 525 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 41054479 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9710423 # DTB read hits -system.cpu.dtb.read_misses 10329 # DTB read misses -system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_accesses 728856 # DTB read accesses -system.cpu.dtb.write_hits 6352496 # DTB write hits -system.cpu.dtb.write_misses 1142 # DTB write misses -system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_accesses 291931 # DTB write accesses -system.cpu.dtb.data_hits 16062919 # DTB hits -system.cpu.dtb.data_misses 11471 # DTB misses -system.cpu.dtb.data_acv 367 # DTB access violations -system.cpu.dtb.data_accesses 1020787 # DTB accesses -system.cpu.itb.fetch_hits 4974637 # ITB hits -system.cpu.itb.fetch_misses 5006 # ITB misses -system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4979643 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numPwrStateTransitions 12714 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 6357 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 283043477.146767 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 441371906.848107 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 6357 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::min_value 386000 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 6357 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 30024619278 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 1799307384222 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 3658670365 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211318 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74830 40.99% 40.99% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 243 0.13% 41.12% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1866 1.02% 42.14% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105622 57.86% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182561 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73463 49.29% 49.29% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149035 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1811929137500 99.05% 99.05% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 20110000 0.00% 99.05% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 80238000 0.00% 99.05% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 17302310500 0.95% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1829331796000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981732 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.695527 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.816357 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed -system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed -system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed -system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed -system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed -system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed -system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed -system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed -system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed -system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed -system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed -system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed -system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed -system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed -system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed -system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed -system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed -system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed -system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed -system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed -system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed -system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed -system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed -system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed -system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed -system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed -system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed -system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed -system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed -system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed -system.cpu.kern.syscall::total 326 # number of syscalls executed -system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4177 2.17% 2.18% # number of callpals executed -system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed -system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175248 91.19% 93.40% # number of callpals executed -system.cpu.kern.callpal::rdps 6771 3.52% 96.92% # number of callpals executed -system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed -system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed -system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed -system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed -system.cpu.kern.callpal::rti 5203 2.71% 99.64% # number of callpals executed -system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed -system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192179 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5949 # number of protection mode switches -system.cpu.kern.mode_switch::user 1737 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1908 -system.cpu.kern.mode_good::user 1737 -system.cpu.kern.mode_good::idle 171 -system.cpu.kern.mode_switch_good::kernel 0.320726 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.390064 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 26833316500 1.47% 1.47% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 1465069000 0.08% 1.55% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1801033409500 98.45% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4178 # number of times the context was actually changed -system.cpu.committedInsts 60038469 # Number of instructions committed -system.cpu.committedOps 60038469 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 55913692 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses -system.cpu.num_func_calls 1484182 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7110791 # number of instructions that are conditional controls -system.cpu.num_int_insts 55913692 # number of integer instructions -system.cpu.num_fp_insts 324460 # number of float instructions -system.cpu.num_int_register_reads 76954245 # number of times the integer registers were read -system.cpu.num_int_register_writes 41740352 # number of times the integer registers were written -system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read -system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written -system.cpu.num_mem_refs 16115703 # number of memory refs -system.cpu.num_load_insts 9747509 # Number of load instructions -system.cpu.num_store_insts 6368194 # Number of store instructions -system.cpu.num_idle_cycles 3598621022.088898 # Number of idle cycles -system.cpu.num_busy_cycles 60049342.911102 # Number of busy cycles -system.cpu.not_idle_fraction 0.016413 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.983587 # Percentage of idle cycles -system.cpu.Branches 9064428 # Number of branches fetched -system.cpu.op_class::No_OpClass 3199100 5.33% 5.33% # Class of executed instruction -system.cpu.op_class::IntAlu 39448406 65.69% 71.02% # Class of executed instruction -system.cpu.op_class::IntMult 60677 0.10% 71.12% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 71.12% # Class of executed instruction -system.cpu.op_class::FloatAdd 38087 0.06% 71.18% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 71.18% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 71.18% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 71.18% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 71.18% # Class of executed instruction -system.cpu.op_class::FloatDiv 3636 0.01% 71.19% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::MemRead 9830448 16.37% 87.56% # Class of executed instruction -system.cpu.op_class::MemWrite 6236007 10.38% 97.95% # Class of executed instruction -system.cpu.op_class::FloatMemRead 144629 0.24% 98.19% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 138108 0.23% 98.42% # Class of executed instruction -system.cpu.op_class::IprAccess 951209 1.58% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 60050307 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2042707 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.997802 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 14038420 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2043219 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 6.870737 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 443 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 66369780 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 66369780 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 7807772 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7807772 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5848209 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5848209 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183141 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199282 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13655981 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13655981 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13655981 # number of overall hits -system.cpu.dcache.overall_hits::total 13655981 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1721711 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1721711 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304363 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304363 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2026074 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2026074 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2026074 # number of overall misses -system.cpu.dcache.overall_misses::total 2026074 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 9529483 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9529483 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6152572 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6152572 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200303 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 199282 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15682055 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15682055 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15682055 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15682055 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180672 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.180672 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049469 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049469 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085680 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085680 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.129197 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.129197 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.129197 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.129197 # miss rate for overall accesses -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 833476 # number of writebacks -system.cpu.dcache.writebacks::total 833476 # number of writebacks -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 919606 # number of replacements -system.cpu.icache.tags.tagsinuse 511.215257 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 59130074 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 920118 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 64.263577 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 9686452000 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.215257 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.998467 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 332 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 60970540 # Number of tag accesses -system.cpu.icache.tags.data_accesses 60970540 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 59130074 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 59130074 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 59130074 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 59130074 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 59130074 # number of overall hits -system.cpu.icache.overall_hits::total 59130074 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 920233 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 920233 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 920233 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 920233 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 920233 # number of overall misses -system.cpu.icache.overall_misses::total 920233 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 60050307 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 60050307 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 60050307 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 60050307 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 60050307 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 60050307 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015324 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.015324 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.015324 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.015324 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.015324 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.015324 # miss rate for overall accesses -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 919606 # number of writebacks -system.cpu.icache.writebacks::total 919606 # number of writebacks -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 992419 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65520.104765 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4865571 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1057941 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.599095 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 264.552906 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4852.732213 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 60402.819646 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.004037 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.074047 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.921674 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.999757 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65522 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 606 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3042 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6629 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55077 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999786 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 48449706 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 48449706 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 833476 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 833476 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 919354 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 919354 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 12 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 12 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 187293 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 187293 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 906926 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 906926 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 811229 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 811229 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 906926 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 998522 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1905448 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 906926 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 998522 # number of overall hits -system.cpu.l2cache.overall_hits::total 1905448 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 4 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 4 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 117054 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 117054 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13289 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 13289 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 927644 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 927644 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 13289 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1044698 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1057987 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 13289 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1044698 # number of overall misses -system.cpu.l2cache.overall_misses::total 1057987 # number of overall misses -system.cpu.l2cache.WritebackDirty_accesses::writebacks 833476 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 833476 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 919354 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 919354 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 304347 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 304347 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 920215 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 920215 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1738873 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1738873 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 920215 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2043220 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2963435 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 920215 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2043220 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2963435 # number of overall (read+write) accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.250000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.250000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384607 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.384607 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014441 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014441 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.533474 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.533474 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014441 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.511300 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.357014 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014441 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.511300 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.357014 # miss rate for overall accesses -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 74359 # number of writebacks -system.cpu.l2cache.writebacks::total 74359 # number of writebacks -system.cpu.toL2Bus.snoop_filter.tot_requests 5925782 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2962435 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1834 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1449 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1449 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 7184 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2666290 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 9838 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 9838 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 833476 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 919606 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 1209231 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 16 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304347 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304347 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 920233 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1738873 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2760072 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6163223 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8923295 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 117749696 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184154670 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 301904366 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 993364 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 4774656 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 6936011 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000753 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.027431 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 6930788 99.92% 99.92% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5223 0.08% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 6936011 # Request fanout histogram -system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). -system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. -system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_txs 395 # Number of DMA write transactions. -system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. -system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. -system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 7358 # Transaction distribution -system.iobus.trans_dist::ReadResp 7358 # Transaction distribution -system.iobus.trans_dist::WriteReq 51390 # Transaction distribution -system.iobus.trans_dist::WriteResp 51390 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5248 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1010 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 1076 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18012 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 34044 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 117496 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20992 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2733 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 1392 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9006 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 46126 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2707742 # Cumulative packet size per connected master and slave (bytes) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 41686 # number of replacements -system.iocache.tags.tagsinuse 1.225569 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41702 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1685780588017 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.225569 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.076598 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.076598 # Average percentage of cache occupancy -system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id -system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375534 # Number of tag accesses -system.iocache.tags.data_accesses 375534 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses -system.iocache.ReadReq_misses::total 174 # number of ReadReq misses -system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses -system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses -system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses -system.iocache.demand_misses::total 41726 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses -system.iocache.overall_misses::total 41726 # number of overall misses -system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses -system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses -system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses -system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.writebacks::writebacks 41512 # number of writebacks -system.iocache.writebacks::total 41512 # number of writebacks -system.membus.snoop_filter.tot_requests 2132776 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 1034179 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 408 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 7184 # Transaction distribution -system.membus.trans_dist::ReadResp 948291 # Transaction distribution -system.membus.trans_dist::WriteReq 9838 # Transaction distribution -system.membus.trans_dist::WriteResp 9838 # Transaction distribution -system.membus.trans_dist::WritebackDirty 115871 # Transaction distribution -system.membus.trans_dist::CleanEvict 917188 # Transaction distribution -system.membus.trans_dist::UpgradeReq 133 # Transaction distribution -system.membus.trans_dist::UpgradeResp 133 # Transaction distribution -system.membus.trans_dist::ReadExReq 116925 # Transaction distribution -system.membus.trans_dist::ReadExResp 116925 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 941107 # Transaction distribution -system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 34044 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3107355 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3141399 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 125138 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 125138 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 3266537 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 46126 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 72461888 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 72508014 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2667904 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2667904 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 75175918 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 2149798 # Request fanout histogram -system.membus.snoop_fanout::mean 0.000494 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.022210 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2148737 99.95% 99.95% # Request fanout histogram -system.membus.snoop_fanout::1 1061 0.05% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2149798 # Request fanout histogram -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post -system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR -system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post -system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post -system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post -system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post -system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post -system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post -system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post -system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post -system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU -system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states -system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1829332003500 # Cumulative time (in ticks) in various power states - ----------- End Simulation Statistics ---------- diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/system.terminal --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/system.terminal Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,107 +0,0 @@ -M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 - Got Configuration 623 - memsize 8000000 pages 4000 - First free page after ROM 0xFFFFFC0000018000 - HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000 - kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x1 - CPU Clock at 2000 MHz IntrClockFrequency=1024 - Booting with 1 processor(s) - KSP: 0x20043FE8 PTBR 0x20 - Console Callback at 0x0, fixup at 0x0, crb offset: 0x510 - Memory cluster 0 [0 - 392] - Memory cluster 1 [392 - 15992] - Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000 - ConsoleDispatch at virt 10000658 phys 18658 val FFFFFC00000100A8 - unix_boot_mem ends at FFFFFC0000076000 - k_argc = 0 - jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067) - CallbackFixup 0 18000, t7=FFFFFC000070C000 - Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006 - Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM - Major Options: SMP LEGACY_START VERBOSE_MCHECK - Command line: root=/dev/hda1 console=ttyS0 - memcluster 0, usage 1, start 0, end 392 - memcluster 1, usage 0, start 392, end 16384 - freeing pages 1069:16384 - reserving pages 1069:1070 - SMP: 1 CPUs probed -- cpu_present_mask = 1 - Built 1 zonelists - Kernel command line: root=/dev/hda1 console=ttyS0 - PID hash table entries: 1024 (order: 10, 32768 bytes) - Using epoch = 1900 - Console: colour dummy device 80x25 - Dentry cache hash table entries: 32768 (order: 5, 262144 bytes) - Inode-cache hash table entries: 16384 (order: 4, 131072 bytes) - Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init) - Mount-cache hash table entries: 512 - SMP mode deactivated. - Brought up 1 CPUs - SMP: Total of 1 processors activated (4002.20 BogoMIPS). - NET: Registered protocol family 16 - EISA bus registered - pci: enabling save/restore of SRM state - SCSI subsystem initialized - srm_env: version 0.0.5 loaded successfully - Installing knfsd (copyright (C) 1996 okir@monad.swb.de). - Initializing Cryptographic API - rtc: Standard PC (1900) epoch (1900) detected - Real Time Clock Driver v1.12 - Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled - ttyS0 at I/O 0x3f8 (irq = 4) is a 8250 - io scheduler noop registered - io scheduler anticipatory registered - io scheduler deadline registered - io scheduler cfq registered - loop: loaded (max 8 devices) - nbd: registered device at major 43 - ns83820.c: National Semiconductor DP83820 10/100/1000 driver. - PCI: Setting latency timer of device 0000:00:01.0 to 64 - eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000 - eth0: enabling optical transceiver - eth0: using 64 bit addressing. - eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=h,sg - tun: Universal TUN/TAP device driver, 1.6 - tun: (C) 1999-2004 Max Krasnyansky - Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2 - ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx - PIIX4: IDE controller at PCI slot 0000:00:00.0 - PIIX4: chipset revision 0 - PIIX4: 100% native mode on irq 31 - PCI: Setting latency timer of device 0000:00:00.0 to 64 - ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA - ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA - hda: M5 IDE Disk, ATA DISK drive - hdb: M5 IDE Disk, ATA DISK drive - ide0 at 0x8410-0x8417,0x8422 on irq 31 - hda: max request size: 128KiB - hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33) - hda: cache flushes not supported - hda: hda1 - hdb: max request size: 128KiB - hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33) - hdb: cache flushes not supported - hdb: unknown partition table - mice: PS/2 mouse device common for all mice - NET: Registered protocol family 2 - IP route cache hash table entries: 4096 (order: 2, 32768 bytes) - TCP established hash table entries: 16384 (order: 5, 262144 bytes) - TCP bind hash table entries: 16384 (order: 5, 262144 bytes) - TCP: Hash tables configured (established 16384 bind 16384) - TCP reno registered - ip_conntrack version 2.1 (512 buckets, 4096 max) - 296 bytes per conntrack - ip_tables: (C) 2000-2002 Netfilter core team - arp_tables: (C) 2002 David S. Miller - TCP bic registered - Initializing IPsec netlink socket - NET: Registered protocol family 1 - NET: Registered protocol family 17 - NET: Registered protocol family 15 - Bridge firewalling registered - 802.1Q VLAN Support v1.8 Ben Greear - All bugs added by David S. Miller - VFS: Mounted root (ext2 filesystem) readonly. - Freeing unused kernel memory: 224k freed - init started: BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary -mounting filesystems... -EXT2-fs warning: checktime reached, running e2fsck is recommended - loading script... diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,1499 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=true -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=LinuxAlphaSystem -children=bridge clk_domain cpu0 cpu1 cpu_clk_domain disk0 disk2 dvfs_handler intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami voltage_domain -boot_cpu_frequency=500 -boot_osflags=root=/dev/hda1 console=ttyS0 -cache_line_size=64 -clk_domain=system.clk_domain -console=/arm/projectscratch/randd/systems/dist/binaries/console -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges=0:134217727:0:0:0:0 -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pal=/arm/projectscratch/randd/systems/dist/binaries/ts_osfpal -power_model=Null -readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh -symbolfile= -system_rev=1024 -system_type=34 -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.bridge] -type=Bridge -clk_domain=system.clk_domain -default_p_state=UNDEFINED -delay=50000 -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -ranges=8796093022208:18446744073709551615:0:0:0:0 -req_size=16 -resp_size=16 -master=system.iobus.slave[0] -slave=system.membus.master[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu0] -type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb tracer -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu0.dtb -eventq_index=0 -function_trace=false -function_trace_start=0 -interrupts=system.cpu0.interrupts -isa=system.cpu0.isa -itb=system.cpu0.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -tracer=system.cpu0.tracer -workload= -dcache_port=system.cpu0.dcache.cpu_side -icache_port=system.cpu0.icache.cpu_side - -[system.cpu0.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=4 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu0.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu0.dcache_port -mem_side=system.toL2Bus.slave[1] - -[system.cpu0.dcache.tags] -type=LRU -assoc=4 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu0.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu0.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=1 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu0.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu0.icache_port -mem_side=system.toL2Bus.slave[0] - -[system.cpu0.icache.tags] -type=LRU -assoc=1 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu0.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu0.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu0.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu0.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu1] -type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb tracer -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=1 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu1.dtb -eventq_index=0 -function_trace=false -function_trace_start=0 -interrupts=system.cpu1.interrupts -isa=system.cpu1.isa -itb=system.cpu1.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -tracer=system.cpu1.tracer -workload= -dcache_port=system.cpu1.dcache.cpu_side -icache_port=system.cpu1.icache.cpu_side - -[system.cpu1.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=4 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu1.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu1.dcache_port -mem_side=system.toL2Bus.slave[3] - -[system.cpu1.dcache.tags] -type=LRU -assoc=4 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu1.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu1.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=1 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu1.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu1.icache_port -mem_side=system.toL2Bus.slave[2] - -[system.cpu1.icache.tags] -type=LRU -assoc=1 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu1.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu1.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu1.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu1.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.disk0] -type=IdeDisk -children=image -delay=1000000 -driveID=master -eventq_index=0 -image=system.disk0.image - -[system.disk0.image] -type=CowDiskImage -children=child -child=system.disk0.image.child -eventq_index=0 -image_file= -read_only=false -table_size=65536 - -[system.disk0.image.child] -type=RawDiskImage -eventq_index=0 -image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img -read_only=true - -[system.disk2] -type=IdeDisk -children=image -delay=1000000 -driveID=master -eventq_index=0 -image=system.disk2.image - -[system.disk2.image] -type=CowDiskImage -children=child -child=system.disk2.image.child -eventq_index=0 -image_file= -read_only=false -table_size=65536 - -[system.disk2.image.child] -type=RawDiskImage -eventq_index=0 -image_file=/arm/projectscratch/randd/systems/dist/disks/linux-bigswap2.img -read_only=true - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.intrctrl] -type=IntrControl -eventq_index=0 -sys=system - -[system.iobus] -type=NoncoherentXBar -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=1 -frontend_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -response_latency=2 -use_default_range=false -width=16 -master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side -slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma - -[system.iocache] -type=Cache -children=tags -addr_ranges=0:134217727:0:0:0:0 -assoc=8 -clk_domain=system.clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=50 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=50 -sequential_access=false -size=1024 -system=system -tags=system.iocache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.iobus.master[27] -mem_side=system.membus.slave[2] - -[system.iocache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=50 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=1024 - -[system.l2c] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=4194304 -system=system -tags=system.l2c.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.l2c.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=4194304 - -[system.membus] -type=CoherentXBar -children=badaddr_responder snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.physmem.port -slave=system.system_port system.l2c.mem_side system.iocache.mem_side - -[system.membus.badaddr_responder] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=0 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=true -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.membus.default - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=0:134217727:0:0:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=6000 -tXPDLL=0 -tXS=270000 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[1] - -[system.simple_disk] -type=SimpleDisk -children=disk -disk=system.simple_disk.disk -eventq_index=0 -system=system - -[system.simple_disk.disk] -type=RawDiskImage -eventq_index=0 -image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img -read_only=true - -[system.terminal] -type=Terminal -eventq_index=0 -intr_control=system.intrctrl -number=0 -output=true -port=3456 - -[system.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.l2c.cpu_side -slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side - -[system.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.tsunami] -type=Tsunami -children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip uart -eventq_index=0 -intrctrl=system.intrctrl -system=system - -[system.tsunami.backdoor] -type=AlphaBackdoor -clk_domain=system.clk_domain -cpu=system.cpu0 -default_p_state=UNDEFINED -disk=system.simple_disk -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804682956800 -pio_latency=100000 -platform=system.tsunami -power_model=Null -system=system -terminal=system.terminal -pio=system.iobus.master[24] - -[system.tsunami.cchip] -type=TsunamiCChip -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8803072344064 -pio_latency=100000 -power_model=Null -system=system -tsunami=system.tsunami -pio=system.iobus.master[0] - -[system.tsunami.ethernet] -type=NSGigE -BAR0=1 -BAR0LegacyIO=false -BAR0Size=256 -BAR1=0 -BAR1LegacyIO=false -BAR1Size=4096 -BAR2=0 -BAR2LegacyIO=false -BAR2Size=0 -BAR3=0 -BAR3LegacyIO=false -BAR3Size=0 -BAR4=0 -BAR4LegacyIO=false -BAR4Size=0 -BAR5=0 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=2 -Command=0 -DeviceID=34 -ExpansionROM=0 -HeaderType=0 -InterruptLine=30 -InterruptPin=1 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=52 -MinimumGrant=176 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=0 -Revision=0 -Status=656 -SubClassCode=0 -SubsystemID=0 -SubsystemVendorID=0 -VendorID=4107 -clk_domain=system.clk_domain -config_latency=20000 -default_p_state=UNDEFINED -dma_data_free=false -dma_desc_free=false -dma_no_allocate=true -dma_read_delay=0 -dma_read_factor=0 -dma_write_delay=0 -dma_write_factor=0 -eventq_index=0 -hardware_address=00:90:00:00:00:01 -host=system.tsunami.pchip -intr_delay=10000000 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_bus=0 -pci_dev=1 -pci_func=0 -pio_latency=30000 -power_model=Null -rss=false -rx_delay=1000000 -rx_fifo_size=524288 -rx_filter=true -rx_thread=false -system=system -tx_delay=1000000 -tx_fifo_size=524288 -tx_thread=false -dma=system.iobus.slave[2] -pio=system.iobus.master[26] - -[system.tsunami.fake_OROM] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8796093677568 -pio_latency=100000 -pio_size=393216 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[8] - -[system.tsunami.fake_ata0] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848432 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[19] - -[system.tsunami.fake_ata1] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848304 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[20] - -[system.tsunami.fake_pnp_addr] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848569 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[9] - -[system.tsunami.fake_pnp_read0] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848451 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[11] - -[system.tsunami.fake_pnp_read1] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848515 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[12] - -[system.tsunami.fake_pnp_read2] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848579 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[13] - -[system.tsunami.fake_pnp_read3] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848643 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[14] - -[system.tsunami.fake_pnp_read4] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848707 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[15] - -[system.tsunami.fake_pnp_read5] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848771 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[16] - -[system.tsunami.fake_pnp_read6] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848835 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[17] - -[system.tsunami.fake_pnp_read7] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848899 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[18] - -[system.tsunami.fake_pnp_write] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615850617 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[10] - -[system.tsunami.fake_ppc] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848891 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[7] - -[system.tsunami.fake_sm_chip] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848816 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[2] - -[system.tsunami.fake_uart1] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848696 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[3] - -[system.tsunami.fake_uart2] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848936 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[4] - -[system.tsunami.fake_uart3] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848680 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[5] - -[system.tsunami.fake_uart4] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848944 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[6] - -[system.tsunami.fb] -type=BadDevice -clk_domain=system.clk_domain -default_p_state=UNDEFINED -devicename=FrameBuffer -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848912 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[21] - -[system.tsunami.ide] -type=IdeController -BAR0=1 -BAR0LegacyIO=false -BAR0Size=8 -BAR1=1 -BAR1LegacyIO=false -BAR1Size=4 -BAR2=1 -BAR2LegacyIO=false -BAR2Size=8 -BAR3=1 -BAR3LegacyIO=false -BAR3Size=4 -BAR4=1 -BAR4LegacyIO=false -BAR4Size=16 -BAR5=1 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=1 -Command=0 -DeviceID=28945 -ExpansionROM=0 -HeaderType=0 -InterruptLine=31 -InterruptPin=1 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=0 -MinimumGrant=0 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=133 -Revision=0 -Status=640 -SubClassCode=1 -SubsystemID=0 -SubsystemVendorID=0 -VendorID=32902 -clk_domain=system.clk_domain -config_latency=20000 -ctrl_offset=0 -default_p_state=UNDEFINED -disks=system.disk0 system.disk2 -eventq_index=0 -host=system.tsunami.pchip -io_shift=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_bus=0 -pci_dev=0 -pci_func=0 -pio_latency=30000 -power_model=Null -system=system -dma=system.iobus.slave[1] -pio=system.iobus.master[25] - -[system.tsunami.io] -type=TsunamiIO -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -frequency=976562500 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615847936 -pio_latency=100000 -power_model=Null -system=system -time=Thu Jan 1 00:00:00 2009 -tsunami=system.tsunami -year_is_bcd=false -pio=system.iobus.master[22] - -[system.tsunami.pchip] -type=TsunamiPChip -clk_domain=system.clk_domain -conf_base=8804649402368 -conf_device_bits=8 -conf_size=16777216 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_dma_base=0 -pci_mem_base=8796093022208 -pci_pio_base=8804615847936 -pio_addr=8802535473152 -pio_latency=100000 -platform=system.tsunami -power_model=Null -system=system -tsunami=system.tsunami -pio=system.iobus.master[1] - -[system.tsunami.uart] -type=Uart8250 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848952 -pio_latency=100000 -platform=system.tsunami -power_model=Null -system=system -terminal=system.terminal -pio=system.iobus.master[23] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,7 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Sockets disabled, not accepting terminal connections -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,16 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:19:44 -gem5 executing on e108600-lin, pid 28056 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual - -Global frequency set at 1000000000000 ticks per second -info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -info: Entering event queue @ 0. Starting simulation... -info: Launching CPU 1 @ 752919000 -Exiting @ tick 1966741627000 because m5_exit instruction encountered diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,1824 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 1.966742 # Number of seconds simulated -sim_ticks 1966741627000 # Number of ticks simulated -final_tick 1966741627000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1743154 # Simulator instruction rate (inst/s) -host_op_rate 1743154 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 56239519255 # Simulator tick rate (ticks/s) -host_mem_usage 337608 # Number of bytes of host memory used -host_seconds 34.97 # Real time elapsed on the host -sim_insts 60959478 # Number of instructions simulated -sim_ops 60959478 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.inst 796480 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24829632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 62464 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 430848 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26120384 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 796480 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 62464 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 858944 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7775296 # Number of bytes written to this memory -system.physmem.bytes_written::total 7775296 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 12445 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 387963 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 976 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 6732 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 408131 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 121489 # Number of write requests responded to by this memory -system.physmem.num_writes::total 121489 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 404974 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12624755 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 31760 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 219067 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 488 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13281045 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 404974 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 31760 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 436735 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3953390 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3953390 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3953390 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 404974 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12624755 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 31760 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 219067 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 488 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17234435 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 408131 # Number of read requests accepted -system.physmem.writeReqs 121489 # Number of write requests accepted -system.physmem.readBursts 408131 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 121489 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26113216 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7168 # Total number of bytes read from write queue -system.physmem.bytesWritten 7773568 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26120384 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7775296 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 112 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25299 # Per bank write bursts -system.physmem.perBankRdBursts::1 25599 # Per bank write bursts -system.physmem.perBankRdBursts::2 25910 # Per bank write bursts -system.physmem.perBankRdBursts::3 25657 # Per bank write bursts -system.physmem.perBankRdBursts::4 25586 # Per bank write bursts -system.physmem.perBankRdBursts::5 25177 # Per bank write bursts -system.physmem.perBankRdBursts::6 26012 # Per bank write bursts -system.physmem.perBankRdBursts::7 25110 # Per bank write bursts -system.physmem.perBankRdBursts::8 25002 # Per bank write bursts -system.physmem.perBankRdBursts::9 25326 # Per bank write bursts -system.physmem.perBankRdBursts::10 25348 # Per bank write bursts -system.physmem.perBankRdBursts::11 25350 # Per bank write bursts -system.physmem.perBankRdBursts::12 25736 # Per bank write bursts -system.physmem.perBankRdBursts::13 25396 # Per bank write bursts -system.physmem.perBankRdBursts::14 25673 # Per bank write bursts -system.physmem.perBankRdBursts::15 25838 # Per bank write bursts -system.physmem.perBankWrBursts::0 7888 # Per bank write bursts -system.physmem.perBankWrBursts::1 7973 # Per bank write bursts -system.physmem.perBankWrBursts::2 7891 # Per bank write bursts -system.physmem.perBankWrBursts::3 7697 # Per bank write bursts -system.physmem.perBankWrBursts::4 7528 # Per bank write bursts -system.physmem.perBankWrBursts::5 7375 # Per bank write bursts -system.physmem.perBankWrBursts::6 8079 # Per bank write bursts -system.physmem.perBankWrBursts::7 7030 # Per bank write bursts -system.physmem.perBankWrBursts::8 7056 # Per bank write bursts -system.physmem.perBankWrBursts::9 7058 # Per bank write bursts -system.physmem.perBankWrBursts::10 7243 # Per bank write bursts -system.physmem.perBankWrBursts::11 7671 # Per bank write bursts -system.physmem.perBankWrBursts::12 7657 # Per bank write bursts -system.physmem.perBankWrBursts::13 7555 # Per bank write bursts -system.physmem.perBankWrBursts::14 7813 # Per bank write bursts -system.physmem.perBankWrBursts::15 7948 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 71 # Number of times write queue was full causing retry -system.physmem.totGap 1966734334500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 408131 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 121489 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 407926 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 80 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1643 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2752 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5759 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5841 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6396 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6541 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7366 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8415 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6986 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7365 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8033 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7676 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6912 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7040 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5993 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5793 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 415 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 410 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 272 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 340 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 331 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 163 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65984 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 513.560621 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 309.956643 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 413.656575 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15493 23.48% 23.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 12381 18.76% 42.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4640 7.03% 49.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3311 5.02% 54.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3269 4.95% 59.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1542 2.34% 61.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1639 2.48% 64.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1098 1.66% 65.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22611 34.27% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65984 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5405 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 75.487327 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2871.274927 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5402 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5405 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5405 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.472155 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.786030 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 24.242091 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4888 90.43% 90.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 28 0.52% 90.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 175 3.24% 94.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 6 0.11% 94.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 5 0.09% 94.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 18 0.33% 94.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 9 0.17% 94.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 2 0.04% 94.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 25 0.46% 95.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 5 0.09% 95.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 152 2.81% 98.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 23 0.43% 98.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 6 0.11% 98.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 3 0.06% 98.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 4 0.07% 98.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 5 0.09% 99.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 2 0.04% 99.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 1 0.02% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 1 0.02% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 6 0.11% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 7 0.13% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 9 0.17% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 7 0.13% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 4 0.07% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 1 0.02% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 6 0.11% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 3 0.06% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 2 0.04% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-343 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5405 # Writes before turning the bus around for reads -system.physmem.totQLat 6252046750 # Total ticks spent queuing -system.physmem.totMemAccLat 13902403000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2040095000 # Total ticks spent in databus transfers -system.physmem.avgQLat 15322.93 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 34072.93 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.28 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.28 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.95 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.13 # Data bus utilization in percentage -system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.83 # Average write queue length when enqueuing -system.physmem.readRowHits 365911 # Number of row buffer hits during reads -system.physmem.writeRowHits 97586 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.68 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.32 # Row buffer hit rate for writes -system.physmem.avgGap 3713482.00 # Average gap between requests -system.physmem.pageHitRate 87.53 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 236241180 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 125565165 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1459059000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 320826420 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 5643624480.000001 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5139412980 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 370844640 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 13440056220 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 6440902560 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 458973488295 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 492152011950 # Total energy per rank (pJ) -system.physmem_0.averagePower 250.237247 # Core power per rank (mW) -system.physmem_0.totalIdleTime 1954499558250 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 615960500 # Time in different power states -system.physmem_0.memoryStateTime::REF 2400520000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 1908253811750 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 16773151500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 9224451750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 29473731500 # Time in different power states -system.physmem_1.actEnergy 234884580 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 124844115 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1454196660 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 313205220 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 5773313520.000001 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5158429890 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 364374240 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 13818451860 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 6703686720 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 458612092095 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 492560034510 # Total energy per rank (pJ) -system.physmem_1.averagePower 250.444709 # Core power per rank (mW) -system.physmem_1.totalIdleTime 1954406570250 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 598675750 # Time in different power states -system.physmem_1.memoryStateTime::REF 2455572000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 1906713566750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 17457468500 # Time in different power states -system.physmem_1.memoryStateTime::ACT 9212976500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 30303367500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dtb.fetch_hits 0 # ITB hits -system.cpu0.dtb.fetch_misses 0 # ITB misses -system.cpu0.dtb.fetch_acv 0 # ITB acv -system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7479115 # DTB read hits -system.cpu0.dtb.read_misses 7764 # DTB read misses -system.cpu0.dtb.read_acv 210 # DTB read access violations -system.cpu0.dtb.read_accesses 524068 # DTB read accesses -system.cpu0.dtb.write_hits 5079820 # DTB write hits -system.cpu0.dtb.write_misses 909 # DTB write misses -system.cpu0.dtb.write_acv 133 # DTB write access violations -system.cpu0.dtb.write_accesses 202594 # DTB write accesses -system.cpu0.dtb.data_hits 12558935 # DTB hits -system.cpu0.dtb.data_misses 8673 # DTB misses -system.cpu0.dtb.data_acv 343 # DTB access violations -system.cpu0.dtb.data_accesses 726662 # DTB accesses -system.cpu0.itb.fetch_hits 3638634 # ITB hits -system.cpu0.itb.fetch_misses 3984 # ITB misses -system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3642618 # ITB accesses -system.cpu0.itb.read_hits 0 # DTB read hits -system.cpu0.itb.read_misses 0 # DTB read misses -system.cpu0.itb.read_acv 0 # DTB read access violations -system.cpu0.itb.read_accesses 0 # DTB read accesses -system.cpu0.itb.write_hits 0 # DTB write hits -system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.write_acv 0 # DTB write access violations -system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.data_hits 0 # DTB hits -system.cpu0.itb.data_misses 0 # DTB misses -system.cpu0.itb.data_acv 0 # DTB access violations -system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numPwrStateTransitions 13588 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 6794 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 272289101.854578 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 432882462.064242 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 6794 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 249000 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 6794 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 116809469000 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 1849932158000 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 3933483254 # number of cpu cycles simulated -system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6794 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 163850 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 56218 40.17% 40.17% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.09% 40.26% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1975 1.41% 41.67% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 433 0.31% 41.98% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 81195 58.02% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 139952 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 55706 49.07% 49.07% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.12% 49.19% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1975 1.74% 50.93% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 433 0.38% 51.31% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 55273 48.69% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 113518 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1903167810000 96.77% 96.77% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 93266000 0.00% 96.77% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 790441500 0.04% 96.81% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 321171500 0.02% 96.83% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 62368212000 3.17% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1966740901000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.990893 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.680744 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.811121 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed -system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed -system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed -system.cpu0.kern.syscall::6 33 14.10% 27.78% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.43% 28.21% # number of syscalls executed -system.cpu0.kern.syscall::17 10 4.27% 32.48% # number of syscalls executed -system.cpu0.kern.syscall::19 10 4.27% 36.75% # number of syscalls executed -system.cpu0.kern.syscall::20 6 2.56% 39.32% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.43% 39.74% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.28% 41.03% # number of syscalls executed -system.cpu0.kern.syscall::33 8 3.42% 44.44% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.85% 45.30% # number of syscalls executed -system.cpu0.kern.syscall::45 39 16.67% 61.97% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.28% 63.25% # number of syscalls executed -system.cpu0.kern.syscall::48 10 4.27% 67.52% # number of syscalls executed -system.cpu0.kern.syscall::54 10 4.27% 71.79% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.43% 72.22% # number of syscalls executed -system.cpu0.kern.syscall::59 6 2.56% 74.79% # number of syscalls executed -system.cpu0.kern.syscall::71 27 11.54% 86.32% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.28% 87.61% # number of syscalls executed -system.cpu0.kern.syscall::74 7 2.99% 90.60% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.43% 91.03% # number of syscalls executed -system.cpu0.kern.syscall::90 3 1.28% 92.31% # number of syscalls executed -system.cpu0.kern.syscall::92 9 3.85% 96.15% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.85% 97.01% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.85% 97.86% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.43% 98.29% # number of syscalls executed -system.cpu0.kern.syscall::144 2 0.85% 99.15% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 234 # number of syscalls executed -system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 525 0.35% 0.36% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.36% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.36% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.36% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3064 2.07% 2.43% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.03% 2.46% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.46% # number of callpals executed -system.cpu0.kern.callpal::swpipl 133000 89.79% 92.25% # number of callpals executed -system.cpu0.kern.callpal::rdps 6513 4.40% 96.65% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.65% # number of callpals executed -system.cpu0.kern.callpal::wrusp 4 0.00% 96.65% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.66% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.66% # number of callpals executed -system.cpu0.kern.callpal::rti 4412 2.98% 99.64% # number of callpals executed -system.cpu0.kern.callpal::callsys 394 0.27% 99.91% # number of callpals executed -system.cpu0.kern.callpal::imb 139 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 148125 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6988 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1369 # number of protection mode switches -system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1368 -system.cpu0.kern.mode_good::user 1369 -system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.195764 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.327510 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1962821824500 99.80% 99.80% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3919074500 0.20% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3065 # number of times the context was actually changed -system.cpu0.committedInsts 47690735 # Number of instructions committed -system.cpu0.committedOps 47690735 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 44243506 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 210072 # Number of float alu accesses -system.cpu0.num_func_calls 1190980 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5607273 # number of instructions that are conditional controls -system.cpu0.num_int_insts 44243506 # number of integer instructions -system.cpu0.num_fp_insts 210072 # number of float instructions -system.cpu0.num_int_register_reads 60857324 # number of times the integer registers were read -system.cpu0.num_int_register_writes 32955789 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 102653 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 104432 # number of times the floating registers were written -system.cpu0.num_mem_refs 12599733 # number of memory refs -system.cpu0.num_load_insts 7506744 # Number of load instructions -system.cpu0.num_store_insts 5092989 # Number of store instructions -system.cpu0.num_idle_cycles 3699864315.998118 # Number of idle cycles -system.cpu0.num_busy_cycles 233618938.001881 # Number of busy cycles -system.cpu0.not_idle_fraction 0.059392 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.940608 # Percentage of idle cycles -system.cpu0.Branches 7182999 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2715471 5.69% 5.69% # Class of executed instruction -system.cpu0.op_class::IntAlu 31387897 65.80% 71.50% # Class of executed instruction -system.cpu0.op_class::IntMult 52053 0.11% 71.61% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 71.61% # Class of executed instruction -system.cpu0.op_class::FloatAdd 26676 0.06% 71.66% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::FloatMultAcc 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::FloatDiv 1883 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::FloatMisc 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.66% # Class of executed instruction -system.cpu0.op_class::MemRead 7588274 15.91% 87.57% # Class of executed instruction -system.cpu0.op_class::MemWrite 5010180 10.50% 98.08% # Class of executed instruction -system.cpu0.op_class::FloatMemRead 92589 0.19% 98.27% # Class of executed instruction -system.cpu0.op_class::FloatMemWrite 88924 0.19% 98.46% # Class of executed instruction -system.cpu0.op_class::IprAccess 735804 1.54% 100.00% # Class of executed instruction -system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 47699751 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 1183172 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.236482 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 11369674 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1183684 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.605329 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 121324500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.236482 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986790 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.986790 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 115 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 51472726 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 51472726 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 6400739 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6400739 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4669408 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4669408 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 138994 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 138994 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 146309 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 146309 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11070147 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 11070147 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11070147 # number of overall hits -system.cpu0.dcache.overall_hits::total 11070147 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 938380 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 938380 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 255338 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 255338 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13584 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13584 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5728 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 5728 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1193718 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1193718 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1193718 # number of overall misses -system.cpu0.dcache.overall_misses::total 1193718 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 31213946000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 31213946000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 12660198000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 12660198000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 149666500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 149666500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 31954500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 31954500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 43874144000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 43874144000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 43874144000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 43874144000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7339119 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7339119 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4924746 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4924746 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 152578 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 152578 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 152037 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 152037 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12263865 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12263865 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12263865 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12263865 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127860 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.127860 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051848 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.051848 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.089030 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.089030 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.037675 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.037675 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097336 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.097336 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097336 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.097336 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 33263.652252 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 33263.652252 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 49582.114687 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 49582.114687 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11017.851885 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11017.851885 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5578.648743 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5578.648743 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36754.194877 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 36754.194877 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36754.194877 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 36754.194877 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 681271 # number of writebacks -system.cpu0.dcache.writebacks::total 681271 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 938380 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 938380 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 255338 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 255338 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13584 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13584 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5728 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 5728 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1193718 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1193718 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1193718 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1193718 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7073 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7073 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10752 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10752 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17825 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17825 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 30275566000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 30275566000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 12404860000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 12404860000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 136082500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 136082500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 26226500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 26226500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 42680426000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 42680426000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 42680426000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 42680426000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1572135500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1572135500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1572135500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1572135500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127860 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127860 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051848 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051848 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.089030 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.089030 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.037675 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.037675 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097336 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.097336 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097336 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.097336 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 32263.652252 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 32263.652252 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 48582.114687 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 48582.114687 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10017.851885 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10017.851885 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4578.648743 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4578.648743 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35754.194877 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35754.194877 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35754.194877 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35754.194877 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222272.797964 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222272.797964 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 88198.345021 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 88198.345021 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 692001 # number of replacements -system.cpu0.icache.tags.tagsinuse 507.922544 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 47007113 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 692513 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 67.879033 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 44813245500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 507.922544 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992036 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.992036 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 435 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 48392391 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 48392391 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 47007113 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 47007113 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 47007113 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 47007113 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 47007113 # number of overall hits -system.cpu0.icache.overall_hits::total 47007113 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 692639 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 692639 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 692639 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 692639 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 692639 # number of overall misses -system.cpu0.icache.overall_misses::total 692639 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10340404000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 10340404000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 10340404000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 10340404000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 10340404000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 10340404000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 47699752 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 47699752 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 47699752 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 47699752 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 47699752 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 47699752 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014521 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014521 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014521 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014521 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014521 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014521 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14928.994758 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14928.994758 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14928.994758 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14928.994758 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14928.994758 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14928.994758 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 692001 # number of writebacks -system.cpu0.icache.writebacks::total 692001 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 692639 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 692639 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 692639 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 692639 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 692639 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 692639 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9647765000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 9647765000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9647765000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 9647765000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9647765000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 9647765000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014521 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014521 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014521 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014521 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014521 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014521 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13928.994758 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13928.994758 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13928.994758 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13928.994758 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13928.994758 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13928.994758 # average overall mshr miss latency -system.cpu1.dtb.fetch_hits 0 # ITB hits -system.cpu1.dtb.fetch_misses 0 # ITB misses -system.cpu1.dtb.fetch_acv 0 # ITB acv -system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2442522 # DTB read hits -system.cpu1.dtb.read_misses 2621 # DTB read misses -system.cpu1.dtb.read_acv 0 # DTB read access violations -system.cpu1.dtb.read_accesses 205338 # DTB read accesses -system.cpu1.dtb.write_hits 1749235 # DTB write hits -system.cpu1.dtb.write_misses 236 # DTB write misses -system.cpu1.dtb.write_acv 24 # DTB write access violations -system.cpu1.dtb.write_accesses 89740 # DTB write accesses -system.cpu1.dtb.data_hits 4191757 # DTB hits -system.cpu1.dtb.data_misses 2857 # DTB misses -system.cpu1.dtb.data_acv 24 # DTB access violations -system.cpu1.dtb.data_accesses 295078 # DTB accesses -system.cpu1.itb.fetch_hits 1826928 # ITB hits -system.cpu1.itb.fetch_misses 1064 # ITB misses -system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1827992 # ITB accesses -system.cpu1.itb.read_hits 0 # DTB read hits -system.cpu1.itb.read_misses 0 # DTB read misses -system.cpu1.itb.read_acv 0 # DTB read access violations -system.cpu1.itb.read_accesses 0 # DTB read accesses -system.cpu1.itb.write_hits 0 # DTB write hits -system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.write_acv 0 # DTB write access violations -system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.data_hits 0 # DTB hits -system.cpu1.itb.data_misses 0 # DTB misses -system.cpu1.itb.data_acv 0 # DTB access violations -system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numPwrStateTransitions 5609 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 2805 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 692202308.556150 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 417084374.205506 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 2805 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 82000 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 974673500 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 2805 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 25114151500 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 1941627475500 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 3931646339 # number of cpu cycles simulated -system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2805 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 79700 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 27196 38.42% 38.42% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1969 2.78% 41.20% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 525 0.74% 41.94% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 41097 58.06% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 70787 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 26331 48.20% 48.20% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1969 3.60% 51.80% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 525 0.96% 52.76% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 25806 47.24% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 54631 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1909855366000 97.15% 97.15% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 731068500 0.04% 97.19% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 371926000 0.02% 97.21% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 54864779000 2.79% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1965823139500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.968194 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.627929 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.771766 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed -system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed -system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed -system.cpu1.kern.syscall::17 5 5.43% 27.17% # number of syscalls executed -system.cpu1.kern.syscall::23 3 3.26% 30.43% # number of syscalls executed -system.cpu1.kern.syscall::24 3 3.26% 33.70% # number of syscalls executed -system.cpu1.kern.syscall::33 3 3.26% 36.96% # number of syscalls executed -system.cpu1.kern.syscall::45 15 16.30% 53.26% # number of syscalls executed -system.cpu1.kern.syscall::47 3 3.26% 56.52% # number of syscalls executed -system.cpu1.kern.syscall::59 1 1.09% 57.61% # number of syscalls executed -system.cpu1.kern.syscall::71 27 29.35% 86.96% # number of syscalls executed -system.cpu1.kern.syscall::74 9 9.78% 96.74% # number of syscalls executed -system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 92 # number of syscalls executed -system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 433 0.59% 0.59% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.60% # number of callpals executed -system.cpu1.kern.callpal::swpctx 2016 2.75% 3.35% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.00% 3.35% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 3.36% # number of callpals executed -system.cpu1.kern.callpal::swpipl 64567 88.14% 91.50% # number of callpals executed -system.cpu1.kern.callpal::rdps 2334 3.19% 94.68% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 94.68% # number of callpals executed -system.cpu1.kern.callpal::wrusp 3 0.00% 94.69% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 94.69% # number of callpals executed -system.cpu1.kern.callpal::rti 3725 5.08% 99.78% # number of callpals executed -system.cpu1.kern.callpal::callsys 121 0.17% 99.94% # number of callpals executed -system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed -system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 73259 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1964 # number of protection mode switches -system.cpu1.kern.mode_switch::user 367 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2923 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 816 -system.cpu1.kern.mode_good::user 367 -system.cpu1.kern.mode_good::idle 449 -system.cpu1.kern.mode_switch_good::kernel 0.415479 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.153609 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.310620 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 18376717500 0.94% 0.94% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1492465500 0.08% 1.01% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1945081083000 98.99% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 2017 # number of times the context was actually changed -system.cpu1.committedInsts 13268743 # Number of instructions committed -system.cpu1.committedOps 13268743 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 12224543 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 175144 # Number of float alu accesses -system.cpu1.num_func_calls 423393 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1315452 # number of instructions that are conditional controls -system.cpu1.num_int_insts 12224543 # number of integer instructions -system.cpu1.num_fp_insts 175144 # number of float instructions -system.cpu1.num_int_register_reads 16795911 # number of times the integer registers were read -system.cpu1.num_int_register_writes 8988763 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 90944 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 92918 # number of times the floating registers were written -system.cpu1.num_mem_refs 4214824 # number of memory refs -system.cpu1.num_load_insts 2456352 # Number of load instructions -system.cpu1.num_store_insts 1758472 # Number of store instructions -system.cpu1.num_idle_cycles 3881441492.340690 # Number of idle cycles -system.cpu1.num_busy_cycles 50204846.659310 # Number of busy cycles -system.cpu1.not_idle_fraction 0.012769 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.987231 # Percentage of idle cycles -system.cpu1.Branches 1899015 # Number of branches fetched -system.cpu1.op_class::No_OpClass 719201 5.42% 5.42% # Class of executed instruction -system.cpu1.op_class::IntAlu 7861154 59.23% 64.65% # Class of executed instruction -system.cpu1.op_class::IntMult 22602 0.17% 64.82% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 64.82% # Class of executed instruction -system.cpu1.op_class::FloatAdd 13252 0.10% 64.92% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 64.92% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 64.92% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 64.92% # Class of executed instruction -system.cpu1.op_class::FloatMultAcc 0 0.00% 64.92% # Class of executed instruction -system.cpu1.op_class::FloatDiv 1759 0.01% 64.94% # Class of executed instruction -system.cpu1.op_class::FloatMisc 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::MemRead 2447876 18.44% 83.38% # Class of executed instruction -system.cpu1.op_class::MemWrite 1681278 12.67% 96.05% # Class of executed instruction -system.cpu1.op_class::FloatMemRead 81935 0.62% 96.67% # Class of executed instruction -system.cpu1.op_class::FloatMemWrite 78198 0.59% 97.25% # Class of executed instruction -system.cpu1.op_class::IprAccess 364369 2.75% 100.00% # Class of executed instruction -system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 13271624 # Class of executed instruction -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 162095 # number of replacements -system.cpu1.dcache.tags.tagsinuse 484.320037 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 4015175 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 162424 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 24.720331 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 72635663500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 484.320037 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.945938 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.945938 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 329 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 297 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.642578 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 16996897 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 16996897 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 2273870 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2273870 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1634166 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1634166 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 51918 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 51918 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 52084 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 52084 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 3908036 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 3908036 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 3908036 # number of overall hits -system.cpu1.dcache.overall_hits::total 3908036 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 118670 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 118670 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 58749 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 58749 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9148 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 9148 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 6116 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 6116 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 177419 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 177419 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 177419 # number of overall misses -system.cpu1.dcache.overall_misses::total 177419 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1466187000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1466187000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1296760000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1296760000 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 84020000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 84020000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 34172000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 34172000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 2762947000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 2762947000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 2762947000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 2762947000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2392540 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2392540 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1692915 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1692915 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 61066 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 61066 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 58200 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 58200 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 4085455 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 4085455 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 4085455 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 4085455 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049600 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.049600 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034703 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.034703 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.149805 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.149805 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.105086 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.105086 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.043427 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.043427 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043427 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.043427 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12355.161372 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12355.161372 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22072.886347 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 22072.886347 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9184.521207 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9184.521207 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5587.311969 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5587.311969 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15573.005146 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 15573.005146 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15573.005146 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 15573.005146 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 111600 # number of writebacks -system.cpu1.dcache.writebacks::total 111600 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 118670 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 118670 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 58749 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 58749 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9148 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9148 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6116 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 6116 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 177419 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 177419 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 177419 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 177419 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 125 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 125 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3371 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3371 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3496 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3496 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1347517000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1347517000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1238011000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1238011000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 74872000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 74872000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 28056000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 28056000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2585528000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2585528000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2585528000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2585528000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 26291000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 26291000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 26291000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 26291000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049600 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049600 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034703 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034703 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.149805 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.149805 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.105086 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.105086 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043427 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.043427 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043427 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.043427 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11355.161372 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11355.161372 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 21072.886347 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21072.886347 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8184.521207 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8184.521207 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4587.311969 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4587.311969 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14573.005146 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14573.005146 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14573.005146 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14573.005146 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 210328 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 210328 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 7520.308924 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 7520.308924 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 326538 # number of replacements -system.cpu1.icache.tags.tagsinuse 445.783445 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 12944535 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 327049 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 39.579803 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1960887554500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 445.783445 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.870671 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.870671 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 75 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 434 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::4 2 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 13598713 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 13598713 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 12944535 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 12944535 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 12944535 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 12944535 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 12944535 # number of overall hits -system.cpu1.icache.overall_hits::total 12944535 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 327089 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 327089 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 327089 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 327089 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 327089 # number of overall misses -system.cpu1.icache.overall_misses::total 327089 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4450039000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4450039000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4450039000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4450039000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4450039000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4450039000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 13271624 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 13271624 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 13271624 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 13271624 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 13271624 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 13271624 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024646 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024646 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024646 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024646 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024646 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024646 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13604.979073 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13604.979073 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13604.979073 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13604.979073 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13604.979073 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13604.979073 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 326538 # number of writebacks -system.cpu1.icache.writebacks::total 326538 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 327089 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 327089 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 327089 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 327089 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 327089 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 327089 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4122950000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 4122950000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4122950000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 4122950000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4122950000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 4122950000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024646 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024646 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024646 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.024646 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024646 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.024646 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12604.979073 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12604.979073 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12604.979073 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 12604.979073 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12604.979073 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 12604.979073 # average overall mshr miss latency -system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). -system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. -system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_txs 395 # Number of DMA write transactions. -system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. -system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. -system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 7376 # Transaction distribution -system.iobus.trans_dist::ReadResp 7376 # Transaction distribution -system.iobus.trans_dist::WriteReq 55675 # Transaction distribution -system.iobus.trans_dist::WriteResp 55675 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14036 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1010 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2474 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 42642 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83460 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83460 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 126102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 56144 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2733 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 82394 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661648 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661648 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2744042 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 15108500 # Layer occupancy (ticks) -system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 758000 # Layer occupancy (ticks) -system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks) -system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 10000 # Layer occupancy (ticks) -system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 174000 # Layer occupancy (ticks) -system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 15840500 # Layer occupancy (ticks) -system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 2459000 # Layer occupancy (ticks) -system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 6051000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 82500 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 216235265 # Layer occupancy (ticks) -system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 28519000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 41956000 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 41698 # number of replacements -system.iocache.tags.tagsinuse 0.568421 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41714 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1760410342000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.568421 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.035526 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.035526 # Average percentage of cache occupancy -system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id -system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375570 # Number of tag accesses -system.iocache.tags.data_accesses 375570 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.iocache.ReadReq_misses::tsunami.ide 178 # number of ReadReq misses -system.iocache.ReadReq_misses::total 178 # number of ReadReq misses -system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses -system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses -system.iocache.demand_misses::tsunami.ide 41730 # number of demand (read+write) misses -system.iocache.demand_misses::total 41730 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41730 # number of overall misses -system.iocache.overall_misses::total 41730 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 22412883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 22412883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4956087382 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4956087382 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 4978500265 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4978500265 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 4978500265 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4978500265 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 178 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41730 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41730 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41730 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41730 # number of overall (read+write) accesses -system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses -system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses -system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125915.073034 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 125915.073034 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 119274.340152 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 119274.340152 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 119302.666307 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 119302.666307 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 119302.666307 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 119302.666307 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 1665 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 10 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 166.500000 # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.writebacks::writebacks 41520 # number of writebacks -system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 178 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 178 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41730 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41730 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41730 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41730 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13512883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13512883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2876027417 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2876027417 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 2889540300 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2889540300 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 2889540300 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2889540300 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75915.073034 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 75915.073034 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 69215.138068 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69215.138068 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 69243.716751 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 69243.716751 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 69243.716751 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 69243.716751 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 342937 # number of replacements -system.l2c.tags.tagsinuse 65389.954388 # Cycle average of tags in use -system.l2c.tags.total_refs 3989146 # Total number of references to valid blocks. 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-system.l2c.tags.occ_percent::cpu1.inst 0.002546 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.012816 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.997772 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65521 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 697 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1597 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6182 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 57022 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.999771 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 35591920 # Number of tag accesses -system.l2c.tags.data_accesses 35591920 # Number of data accesses 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ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 19270029000 # number of ReadSharedReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 1157389000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 28685534500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 90609000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 632059500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 30565592000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 1157389000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 28685534500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 90609000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 632059500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 30565592000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1483681000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 24728000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 1508409000 # number of ReadReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1483681000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 24728000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 1508409000 # number of overall MSHR uncacheable cycles -system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.001585 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.000424 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.001089 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.476210 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.129173 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.417756 # mshr miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.017968 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.002984 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013162 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.290454 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.003126 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.260510 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.017968 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.329070 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.002984 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.042657 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.173230 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.017968 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.329070 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.002984 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.042657 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.173230 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 50000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18500 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 44750 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 80922.669691 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 92439.554448 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 81522.486998 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 93000.321414 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 92837.090164 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 92988.450935 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 70829.226163 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 113794.117647 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 70882.960527 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 93000.321414 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 73865.729618 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 92837.090164 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 93513.759432 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 74819.025425 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 93000.321414 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 73865.729618 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 92837.090164 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 93513.759432 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 74819.025425 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209766.859890 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 197824 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209559.460961 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 83235.960729 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 7073.226545 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 70747.572816 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 856503 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 407142 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 413 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 7198 # Transaction distribution -system.membus.trans_dist::ReadResp 292654 # Transaction distribution -system.membus.trans_dist::WriteReq 14123 # Transaction distribution -system.membus.trans_dist::WriteResp 14123 # Transaction distribution -system.membus.trans_dist::WritebackDirty 121489 # Transaction distribution -system.membus.trans_dist::CleanEvict 262335 # Transaction distribution -system.membus.trans_dist::UpgradeReq 11693 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 9938 # Transaction distribution -system.membus.trans_dist::UpgradeResp 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 123969 # Transaction distribution -system.membus.trans_dist::ReadExResp 123101 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 285456 # Transaction distribution -system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42642 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1181120 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1223762 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83443 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 83443 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1307205 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 82394 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31237440 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31319834 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33978074 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 22774 # Total snoops (count) -system.membus.snoopTraffic 27264 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 493929 # Request fanout histogram -system.membus.snoop_fanout::mean 0.001371 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.036997 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 493252 99.86% 99.86% # Request fanout histogram -system.membus.snoop_fanout::1 677 0.14% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 493929 # Request fanout histogram -system.membus.reqLayer0.occupancy 40493000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1323047597 # Layer occupancy (ticks) -system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2182313750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 915117 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 4789247 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2394847 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 361788 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 989 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 928 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 61 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 7198 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2106871 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 14123 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 14123 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 872840 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1018539 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 815364 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 17050 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 11844 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 28894 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 297037 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 297037 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1019728 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1079947 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 246 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2077258 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3616236 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 980715 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 523549 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7197758 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 88615616 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119196292 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 41832064 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17309590 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 266953562 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 403246 # Total snoops (count) -system.toL2Bus.snoopTraffic 7576960 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 2790110 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.141029 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.348296 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 2396861 85.91% 85.91% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 393013 14.09% 99.99% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 235 0.01% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 1 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 2790110 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4223757496 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 302383 # Layer occupancy (ticks) -system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1039141633 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1817975093 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 491872018 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 276251327 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post -system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR -system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post -system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post -system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post -system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post -system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post -system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post -system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post -system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post -system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU -system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states -system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1966741627000 # Cumulative time (in ticks) in various power states - ----------- End Simulation Statistics ---------- diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,113 +0,0 @@ -M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 - Got Configuration 623 - memsize 8000000 pages 4000 - First free page after ROM 0xFFFFFC0000018000 - HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000 - kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x2 - CPU Clock at 2000 MHz IntrClockFrequency=1024 - Booting with 2 processor(s) - KSP: 0x20043FE8 PTBR 0x20 - KSP: 0x20043FE8 PTBR 0x20 - Console Callback at 0x0, fixup at 0x0, crb offset: 0x790 - Memory cluster 0 [0 - 392] - Memory cluster 1 [392 - 15992] - Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000 - ConsoleDispatch at virt 100008D8 phys 188D8 val FFFFFC00000100A8 - Bootstraping CPU 1 with sp=0xFFFFFC0000076000 - unix_boot_mem ends at FFFFFC0000078000 - k_argc = 0 - jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067) - Entering slaveloop for cpu 1 my_rpb=FFFFFC0000018400 - CallbackFixup 0 18000, t7=FFFFFC000070C000 - Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006 - Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM - Major Options: SMP LEGACY_START VERBOSE_MCHECK - Command line: root=/dev/hda1 console=ttyS0 - memcluster 0, usage 1, start 0, end 392 - memcluster 1, usage 0, start 392, end 16384 - freeing pages 1069:16384 - reserving pages 1069:1070 - 4096K Bcache detected; load hit latency 38 cycles, load miss latency 175 cycles - SMP: 2 CPUs probed -- cpu_present_mask = 3 - Built 1 zonelists - Kernel command line: root=/dev/hda1 console=ttyS0 - PID hash table entries: 1024 (order: 10, 32768 bytes) - Using epoch = 1900 - Console: colour dummy device 80x25 - Dentry cache hash table entries: 32768 (order: 5, 262144 bytes) - Inode-cache hash table entries: 16384 (order: 4, 131072 bytes) - Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init) - Mount-cache hash table entries: 512 - SMP starting up secondaries. - Slave CPU 1 console command START -SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb FFFFFC0000018400 my_rpb_phys 18400 - Brought up 2 CPUs - SMP: Total of 2 processors activated (8000.15 BogoMIPS). - NET: Registered protocol family 16 - EISA bus registered - pci: enabling save/restore of SRM state - SCSI subsystem initialized - srm_env: version 0.0.5 loaded successfully - Installing knfsd (copyright (C) 1996 okir@monad.swb.de). - Initializing Cryptographic API - rtc: Standard PC (1900) epoch (1900) detected - Real Time Clock Driver v1.12 - Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled - ttyS0 at I/O 0x3f8 (irq = 4) is a 8250 - io scheduler noop registered - io scheduler anticipatory registered - io scheduler deadline registered - io scheduler cfq registered - loop: loaded (max 8 devices) - nbd: registered device at major 43 - ns83820.c: National Semiconductor DP83820 10/100/1000 driver. - PCI: Setting latency timer of device 0000:00:01.0 to 64 - eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000 - eth0: enabling optical transceiver - eth0: using 64 bit addressing. - eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=h,sg - tun: Universal TUN/TAP device driver, 1.6 - tun: (C) 1999-2004 Max Krasnyansky - Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2 - ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx - PIIX4: IDE controller at PCI slot 0000:00:00.0 - PIIX4: chipset revision 0 - PIIX4: 100% native mode on irq 31 - PCI: Setting latency timer of device 0000:00:00.0 to 64 - ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA - ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA - hda: M5 IDE Disk, ATA DISK drive - hdb: M5 IDE Disk, ATA DISK drive - ide0 at 0x8410-0x8417,0x8422 on irq 31 - hda: max request size: 128KiB - hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33) - hda: cache flushes not supported - hda: hda1 - hdb: max request size: 128KiB - hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33) - hdb: cache flushes not supported - hdb: unknown partition table - mice: PS/2 mouse device common for all mice - NET: Registered protocol family 2 - IP route cache hash table entries: 4096 (order: 2, 32768 bytes) - TCP established hash table entries: 16384 (order: 5, 262144 bytes) - TCP bind hash table entries: 16384 (order: 5, 262144 bytes) - TCP: Hash tables configured (established 16384 bind 16384) - TCP reno registered - ip_conntrack version 2.1 (512 buckets, 4096 max) - 296 bytes per conntrack - ip_tables: (C) 2000-2002 Netfilter core team - arp_tables: (C) 2002 David S. Miller - TCP bic registered - Initializing IPsec netlink socket - NET: Registered protocol family 1 - NET: Registered protocol family 17 - NET: Registered protocol family 15 - Bridge firewalling registered - 802.1Q VLAN Support v1.8 Ben Greear - All bugs added by David S. Miller - VFS: Mounted root (ext2 filesystem) readonly. - Freeing unused kernel memory: 224k freed - init started: BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary -mounting filesystems... -EXT2-fs warning: checktime reached, running e2fsck is recommended - loading script... diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,1346 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=true -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=LinuxAlphaSystem -children=bridge clk_domain cpu cpu_clk_domain disk0 disk2 dvfs_handler intrctrl iobus iocache membus physmem simple_disk terminal tsunami voltage_domain -boot_cpu_frequency=500 -boot_osflags=root=/dev/hda1 console=ttyS0 -cache_line_size=64 -clk_domain=system.clk_domain -console=/arm/projectscratch/randd/systems/dist/binaries/console -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges=0:134217727:0:0:0:0 -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pal=/arm/projectscratch/randd/systems/dist/binaries/ts_osfpal -power_model=Null -readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh -symbolfile= -system_rev=1024 -system_type=34 -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.bridge] -type=Bridge -clk_domain=system.clk_domain -default_p_state=UNDEFINED -delay=50000 -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -ranges=8796093022208:18446744073709551615:0:0:0:0 -req_size=16 -resp_size=16 -master=system.iobus.slave[0] -slave=system.membus.master[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -workload= -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=4 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=4 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=1 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=1 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=4194304 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=4194304 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.disk0] -type=IdeDisk -children=image -delay=1000000 -driveID=master -eventq_index=0 -image=system.disk0.image - -[system.disk0.image] -type=CowDiskImage -children=child -child=system.disk0.image.child -eventq_index=0 -image_file= -read_only=false -table_size=65536 - -[system.disk0.image.child] -type=RawDiskImage -eventq_index=0 -image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img -read_only=true - -[system.disk2] -type=IdeDisk -children=image -delay=1000000 -driveID=master -eventq_index=0 -image=system.disk2.image - -[system.disk2.image] -type=CowDiskImage -children=child -child=system.disk2.image.child -eventq_index=0 -image_file= -read_only=false -table_size=65536 - -[system.disk2.image.child] -type=RawDiskImage -eventq_index=0 -image_file=/arm/projectscratch/randd/systems/dist/disks/linux-bigswap2.img -read_only=true - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.intrctrl] -type=IntrControl -eventq_index=0 -sys=system - -[system.iobus] -type=NoncoherentXBar -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=1 -frontend_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -response_latency=2 -use_default_range=false -width=16 -master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side -slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma - -[system.iocache] -type=Cache -children=tags -addr_ranges=0:134217727:0:0:0:0 -assoc=8 -clk_domain=system.clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=50 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=50 -sequential_access=false -size=1024 -system=system -tags=system.iocache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.iobus.master[27] -mem_side=system.membus.slave[2] - -[system.iocache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=50 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=1024 - -[system.membus] -type=CoherentXBar -children=badaddr_responder snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side - -[system.membus.badaddr_responder] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=0 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=true -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.membus.default - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=0:134217727:0:0:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=6000 -tXPDLL=0 -tXS=270000 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[1] - -[system.simple_disk] -type=SimpleDisk -children=disk -disk=system.simple_disk.disk -eventq_index=0 -system=system - -[system.simple_disk.disk] -type=RawDiskImage -eventq_index=0 -image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img -read_only=true - -[system.terminal] -type=Terminal -eventq_index=0 -intr_control=system.intrctrl -number=0 -output=true -port=3456 - -[system.tsunami] -type=Tsunami -children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip uart -eventq_index=0 -intrctrl=system.intrctrl -system=system - -[system.tsunami.backdoor] -type=AlphaBackdoor -clk_domain=system.clk_domain -cpu=system.cpu -default_p_state=UNDEFINED -disk=system.simple_disk -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804682956800 -pio_latency=100000 -platform=system.tsunami -power_model=Null -system=system -terminal=system.terminal -pio=system.iobus.master[24] - -[system.tsunami.cchip] -type=TsunamiCChip -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8803072344064 -pio_latency=100000 -power_model=Null -system=system -tsunami=system.tsunami -pio=system.iobus.master[0] - -[system.tsunami.ethernet] -type=NSGigE -BAR0=1 -BAR0LegacyIO=false -BAR0Size=256 -BAR1=0 -BAR1LegacyIO=false -BAR1Size=4096 -BAR2=0 -BAR2LegacyIO=false -BAR2Size=0 -BAR3=0 -BAR3LegacyIO=false -BAR3Size=0 -BAR4=0 -BAR4LegacyIO=false -BAR4Size=0 -BAR5=0 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=2 -Command=0 -DeviceID=34 -ExpansionROM=0 -HeaderType=0 -InterruptLine=30 -InterruptPin=1 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=52 -MinimumGrant=176 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=0 -Revision=0 -Status=656 -SubClassCode=0 -SubsystemID=0 -SubsystemVendorID=0 -VendorID=4107 -clk_domain=system.clk_domain -config_latency=20000 -default_p_state=UNDEFINED -dma_data_free=false -dma_desc_free=false -dma_no_allocate=true -dma_read_delay=0 -dma_read_factor=0 -dma_write_delay=0 -dma_write_factor=0 -eventq_index=0 -hardware_address=00:90:00:00:00:01 -host=system.tsunami.pchip -intr_delay=10000000 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_bus=0 -pci_dev=1 -pci_func=0 -pio_latency=30000 -power_model=Null -rss=false -rx_delay=1000000 -rx_fifo_size=524288 -rx_filter=true -rx_thread=false -system=system -tx_delay=1000000 -tx_fifo_size=524288 -tx_thread=false -dma=system.iobus.slave[2] -pio=system.iobus.master[26] - -[system.tsunami.fake_OROM] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8796093677568 -pio_latency=100000 -pio_size=393216 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[8] - -[system.tsunami.fake_ata0] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848432 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[19] - -[system.tsunami.fake_ata1] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848304 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[20] - -[system.tsunami.fake_pnp_addr] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848569 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[9] - -[system.tsunami.fake_pnp_read0] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848451 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[11] - -[system.tsunami.fake_pnp_read1] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848515 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[12] - -[system.tsunami.fake_pnp_read2] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848579 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[13] - -[system.tsunami.fake_pnp_read3] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848643 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[14] - -[system.tsunami.fake_pnp_read4] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848707 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[15] - -[system.tsunami.fake_pnp_read5] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848771 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[16] - -[system.tsunami.fake_pnp_read6] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848835 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[17] - -[system.tsunami.fake_pnp_read7] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848899 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[18] - -[system.tsunami.fake_pnp_write] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615850617 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[10] - -[system.tsunami.fake_ppc] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848891 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[7] - -[system.tsunami.fake_sm_chip] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848816 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[2] - -[system.tsunami.fake_uart1] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848696 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[3] - -[system.tsunami.fake_uart2] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848936 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[4] - -[system.tsunami.fake_uart3] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848680 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[5] - -[system.tsunami.fake_uart4] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848944 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[6] - -[system.tsunami.fb] -type=BadDevice -clk_domain=system.clk_domain -default_p_state=UNDEFINED -devicename=FrameBuffer -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848912 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[21] - -[system.tsunami.ide] -type=IdeController -BAR0=1 -BAR0LegacyIO=false -BAR0Size=8 -BAR1=1 -BAR1LegacyIO=false -BAR1Size=4 -BAR2=1 -BAR2LegacyIO=false -BAR2Size=8 -BAR3=1 -BAR3LegacyIO=false -BAR3Size=4 -BAR4=1 -BAR4LegacyIO=false -BAR4Size=16 -BAR5=1 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=1 -Command=0 -DeviceID=28945 -ExpansionROM=0 -HeaderType=0 -InterruptLine=31 -InterruptPin=1 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=0 -MinimumGrant=0 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=133 -Revision=0 -Status=640 -SubClassCode=1 -SubsystemID=0 -SubsystemVendorID=0 -VendorID=32902 -clk_domain=system.clk_domain -config_latency=20000 -ctrl_offset=0 -default_p_state=UNDEFINED -disks=system.disk0 system.disk2 -eventq_index=0 -host=system.tsunami.pchip -io_shift=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_bus=0 -pci_dev=0 -pci_func=0 -pio_latency=30000 -power_model=Null -system=system -dma=system.iobus.slave[1] -pio=system.iobus.master[25] - -[system.tsunami.io] -type=TsunamiIO -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -frequency=976562500 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615847936 -pio_latency=100000 -power_model=Null -system=system -time=Thu Jan 1 00:00:00 2009 -tsunami=system.tsunami -year_is_bcd=false -pio=system.iobus.master[22] - -[system.tsunami.pchip] -type=TsunamiPChip -clk_domain=system.clk_domain -conf_base=8804649402368 -conf_device_bits=8 -conf_size=16777216 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_dma_base=0 -pci_mem_base=8796093022208 -pci_pio_base=8804615847936 -pio_addr=8802535473152 -pio_latency=100000 -platform=system.tsunami -power_model=Null -system=system -tsunami=system.tsunami -pio=system.iobus.master[1] - -[system.tsunami.uart] -type=Uart8250 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848952 -pio_latency=100000 -platform=system.tsunami -power_model=Null -system=system -terminal=system.terminal -pio=system.iobus.master[23] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,6 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Sockets disabled, not accepting terminal connections -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,15 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:19:45 -gem5 executing on e108600-lin, pid 28068 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing - -Global frequency set at 1000000000000 ticks per second -info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1926421414000 because m5_exit instruction encountered diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,1255 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 1.926421 # Number of seconds simulated -sim_ticks 1926421414000 # Number of ticks simulated -final_tick 1926421414000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1670874 # Simulator instruction rate (inst/s) -host_op_rate 1670873 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 57279188873 # Simulator tick rate (ticks/s) -host_mem_usage 333776 # Number of bytes of host memory used -host_seconds 33.63 # Real time elapsed on the host -sim_insts 56195014 # Number of instructions simulated -sim_ops 56195014 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 844672 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24856896 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25702528 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 844672 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 844672 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7408960 # Number of bytes written to this memory -system.physmem.bytes_written::total 7408960 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13198 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388389 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 401602 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115765 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115765 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 438467 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12903146 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 498 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13342111 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 438467 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 438467 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3845971 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3845971 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3845971 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 438467 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12903146 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 498 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17188081 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 401602 # Number of read requests accepted -system.physmem.writeReqs 115765 # Number of write requests accepted -system.physmem.readBursts 401602 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 115765 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25695552 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6976 # Total number of bytes read from write queue -system.physmem.bytesWritten 7408000 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25702528 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7408960 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 109 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25229 # Per bank write bursts -system.physmem.perBankRdBursts::1 25631 # Per bank write bursts -system.physmem.perBankRdBursts::2 25563 # Per bank write bursts -system.physmem.perBankRdBursts::3 25503 # Per bank write bursts -system.physmem.perBankRdBursts::4 24978 # Per bank write bursts -system.physmem.perBankRdBursts::5 24964 # Per bank write bursts -system.physmem.perBankRdBursts::6 24209 # Per bank write bursts -system.physmem.perBankRdBursts::7 24494 # Per bank write bursts -system.physmem.perBankRdBursts::8 25180 # Per bank write bursts -system.physmem.perBankRdBursts::9 24757 # Per bank write bursts -system.physmem.perBankRdBursts::10 25269 # Per bank write bursts -system.physmem.perBankRdBursts::11 24873 # Per bank write bursts -system.physmem.perBankRdBursts::12 24512 # Per bank write bursts -system.physmem.perBankRdBursts::13 25367 # Per bank write bursts -system.physmem.perBankRdBursts::14 25615 # Per bank write bursts -system.physmem.perBankRdBursts::15 25349 # Per bank write bursts -system.physmem.perBankWrBursts::0 7626 # Per bank write bursts -system.physmem.perBankWrBursts::1 7640 # Per bank write bursts -system.physmem.perBankWrBursts::2 7866 # Per bank write bursts -system.physmem.perBankWrBursts::3 7539 # Per bank write bursts -system.physmem.perBankWrBursts::4 7128 # Per bank write bursts -system.physmem.perBankWrBursts::5 6982 # Per bank write bursts -system.physmem.perBankWrBursts::6 6324 # Per bank write bursts -system.physmem.perBankWrBursts::7 6321 # Per bank write bursts -system.physmem.perBankWrBursts::8 7317 # Per bank write bursts -system.physmem.perBankWrBursts::9 6511 # Per bank write bursts -system.physmem.perBankWrBursts::10 7117 # Per bank write bursts -system.physmem.perBankWrBursts::11 6900 # Per bank write bursts -system.physmem.perBankWrBursts::12 7101 # Per bank write bursts -system.physmem.perBankWrBursts::13 7827 # Per bank write bursts -system.physmem.perBankWrBursts::14 7864 # Per bank write bursts -system.physmem.perBankWrBursts::15 7687 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 65 # Number of times write queue was full causing retry -system.physmem.totGap 1926409540500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 401602 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 115765 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 401479 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1 # What read 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an incoming req see -system.physmem.wrQLenPdf::50 296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 341 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 159 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 63474 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 521.529319 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 315.079750 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 415.298836 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14953 23.56% 23.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11433 18.01% 41.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4319 6.80% 48.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3083 4.86% 53.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3219 5.07% 58.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1509 2.38% 60.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1583 2.49% 63.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 998 1.57% 64.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22377 35.25% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 63474 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5049 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 79.519311 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2969.676150 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5046 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5049 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5049 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.925332 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.952060 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 24.989890 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4540 89.92% 89.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 33 0.65% 90.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 164 3.25% 93.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 7 0.14% 93.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 1 0.02% 93.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 14 0.28% 94.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 7 0.14% 94.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 4 0.08% 94.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 36 0.71% 95.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 2 0.04% 95.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 139 2.75% 97.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 18 0.36% 98.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 13 0.26% 98.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 3 0.06% 98.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 6 0.12% 98.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 6 0.12% 98.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 3 0.06% 98.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 2 0.04% 98.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 13 0.26% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 4 0.08% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 12 0.24% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 10 0.20% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 1 0.02% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 1 0.02% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 6 0.12% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 2 0.04% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 2 0.04% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5049 # Writes before turning the bus around for reads -system.physmem.totQLat 6110965000 # Total ticks spent queuing -system.physmem.totMemAccLat 13638958750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2007465000 # Total ticks spent in databus transfers -system.physmem.avgQLat 15220.60 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 33970.60 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.34 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.85 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.34 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.85 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.13 # Data bus utilization in percentage -system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.93 # Average write queue length when enqueuing -system.physmem.readRowHits 360227 # Number of row buffer hits during reads -system.physmem.writeRowHits 93542 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.72 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.80 # Row buffer hit rate for writes -system.physmem.avgGap 3723487.47 # Average gap between requests -system.physmem.pageHitRate 87.73 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 220840200 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 117379350 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1432076940 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 299763720 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 5519467200.000001 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5038358250 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 366301440 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 13030830420 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 6357713760 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 449603447400 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 481990669050 # Total energy per rank (pJ) -system.physmem_0.averagePower 250.200016 # Core power per rank (mW) -system.physmem_0.totalIdleTime 1914256960750 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 613825000 # Time in different power states -system.physmem_0.memoryStateTime::REF 2347892000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 1869275563500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 16556600250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 9050884750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 28576648500 # Time in different power states -system.physmem_1.actEnergy 232364160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 123504480 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1434583080 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 304451280 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 5706932400.000001 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5157840510 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 361297920 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 13647845730 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 6595007040 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 449082638955 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 482651277075 # Total energy per rank (pJ) -system.physmem_1.averagePower 250.542936 # Core power per rank (mW) -system.physmem_1.totalIdleTime 1914153639500 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 598128250 # Time in different power states -system.physmem_1.memoryStateTime::REF 2427510000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 1867054823500 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 17174624250 # Time in different power states -system.physmem_1.memoryStateTime::ACT 9236704750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 29929623250 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9066536 # DTB read hits -system.cpu.dtb.read_misses 10331 # DTB read misses -system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_accesses 728865 # DTB read accesses -system.cpu.dtb.write_hits 6357492 # DTB write hits -system.cpu.dtb.write_misses 1143 # DTB write misses -system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_accesses 291932 # DTB write accesses -system.cpu.dtb.data_hits 15424028 # DTB hits -system.cpu.dtb.data_misses 11474 # DTB misses -system.cpu.dtb.data_acv 367 # DTB access violations -system.cpu.dtb.data_accesses 1020797 # DTB accesses -system.cpu.itb.fetch_hits 4975201 # ITB hits -system.cpu.itb.fetch_misses 5010 # ITB misses -system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4980211 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numPwrStateTransitions 12758 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 6379 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 281128919.188117 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 439406492.836173 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::underflows 1 0.02% 0.02% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 6378 99.98% 100.00% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 6379 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 133100038499 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 1793321375501 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 3852842828 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 212049 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74911 40.89% 40.89% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1934 1.06% 42.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106246 57.99% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183222 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73544 49.31% 49.31% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1934 1.30% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73544 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149153 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1859428695000 96.52% 96.52% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 94503000 0.00% 96.53% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 772442000 0.04% 96.57% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 66125040000 3.43% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1926420680000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981752 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.692205 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814056 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed -system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed -system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed -system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed -system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed -system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed -system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed -system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed -system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed -system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed -system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed -system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed -system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed -system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed -system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed -system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed -system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed -system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed -system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed -system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed -system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed -system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed -system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed -system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed -system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed -system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed -system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed -system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed -system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed -system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed -system.cpu.kern.syscall::total 326 # number of syscalls executed -system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4177 2.16% 2.17% # number of callpals executed -system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed -system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175997 91.22% 93.41% # number of callpals executed -system.cpu.kern.callpal::rdps 6834 3.54% 96.96% # number of callpals executed -system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::rti 5159 2.67% 99.64% # number of callpals executed -system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed -system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192947 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5906 # number of protection mode switches -system.cpu.kern.mode_switch::user 1738 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1908 -system.cpu.kern.mode_good::user 1738 -system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.323061 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.391786 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 47043056000 2.44% 2.44% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5370301500 0.28% 2.72% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1874007320500 97.28% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4178 # number of times the context was actually changed -system.cpu.committedInsts 56195014 # Number of instructions committed -system.cpu.committedOps 56195014 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 52066552 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses -system.cpu.num_func_calls 1483758 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6469897 # number of instructions that are conditional controls -system.cpu.num_int_insts 52066552 # number of integer instructions -system.cpu.num_fp_insts 324460 # number of float instructions -system.cpu.num_int_register_reads 71340789 # number of times the integer registers were read -system.cpu.num_int_register_writes 38530081 # number of times the integer registers were written -system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read -system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written -system.cpu.num_mem_refs 15476659 # number of memory refs -system.cpu.num_load_insts 9103400 # Number of load instructions -system.cpu.num_store_insts 6373259 # Number of store instructions -system.cpu.num_idle_cycles 3586642751.000138 # Number of idle cycles -system.cpu.num_busy_cycles 266200076.999862 # Number of busy cycles -system.cpu.not_idle_fraction 0.069092 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.930908 # Percentage of idle cycles -system.cpu.Branches 8424278 # Number of branches fetched -system.cpu.op_class::No_OpClass 3201027 5.70% 5.70% # Class of executed instruction -system.cpu.op_class::IntAlu 36239709 64.48% 70.17% # Class of executed instruction -system.cpu.op_class::IntMult 61024 0.11% 70.28% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 70.28% # Class of executed instruction -system.cpu.op_class::FloatAdd 38087 0.07% 70.35% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::FloatDiv 3636 0.01% 70.35% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::MemRead 9185894 16.34% 86.70% # Class of executed instruction -system.cpu.op_class::MemWrite 6241230 11.10% 97.80% # Class of executed instruction -system.cpu.op_class::FloatMemRead 144629 0.26% 98.06% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 138108 0.25% 98.30% # Class of executed instruction -system.cpu.op_class::IprAccess 953511 1.70% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 56206855 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 1390811 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.976541 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 14051752 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1391323 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 10.099561 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 121311500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.976541 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999954 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999954 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63163628 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63163628 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 7815905 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7815905 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5853570 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5853570 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183002 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183002 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199258 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199258 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13669475 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13669475 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13669475 # number of overall hits -system.cpu.dcache.overall_hits::total 13669475 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1069743 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1069743 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304319 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304319 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17279 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17279 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1374062 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1374062 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1374062 # number of overall misses -system.cpu.dcache.overall_misses::total 1374062 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 33050586500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 33050586500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 13442150000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 13442150000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 232520000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 232520000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 46492736500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 46492736500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 46492736500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 46492736500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 8885648 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 8885648 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6157889 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6157889 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200281 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200281 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 199258 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199258 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15043537 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15043537 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15043537 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15043537 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120390 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120390 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049419 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049419 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086274 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086274 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.091339 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.091339 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.091339 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.091339 # miss rate for overall accesses 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of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17279 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17279 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1374062 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1374062 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1374062 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1374062 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable -system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9652 # number of WriteReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::total 9652 # number of WriteReq MSHR uncacheable -system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16582 # number of overall MSHR uncacheable misses -system.cpu.dcache.overall_mshr_uncacheable_misses::total 16582 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 31980843500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 31980843500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13137831000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 13137831000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 215241000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 215241000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45118674500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 45118674500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45118674500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 45118674500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1533908500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1533908500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1533908500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 1533908500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120390 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120390 # mshr miss rate for ReadReq accesses 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mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43171.247934 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43171.247934 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12456.797268 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12456.797268 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32835.981564 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 32835.981564 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32835.981564 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 32835.981564 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221343.217893 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221343.217893 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92504.432517 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92504.432517 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 928683 # number of replacements -system.cpu.icache.tags.tagsinuse 507.830404 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 55277502 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 929194 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 59.489732 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 44439092500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 507.830404 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.991856 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.991856 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 438 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 57136210 # Number of tag accesses -system.cpu.icache.tags.data_accesses 57136210 # Number of data accesses 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# average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14321.430800 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14321.430800 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14321.430800 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 928683 # number of writebacks -system.cpu.icache.writebacks::total 928683 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929354 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 929354 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 929354 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 929354 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 929354 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 929354 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12380325000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12380325000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12380325000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12380325000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12380325000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12380325000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016535 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016535 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016535 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.016535 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016535 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.016535 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13321.430800 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13321.430800 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13321.430800 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13321.430800 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13321.430800 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13321.430800 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 336397 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65387.710851 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4236321 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 401919 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 10.540236 # Average number of references to valid blocks. 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# Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4685 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 59935 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999786 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 37511490 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 37511490 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 835205 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 835205 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 928450 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 928450 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 12 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 12 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 187485 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 187485 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 916136 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 916136 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 815048 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 815048 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 916136 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1002533 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1918669 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 916136 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1002533 # number of overall hits -system.cpu.l2cache.overall_hits::total 1918669 # number of overall hits -system.cpu.l2cache.UpgradeReq_misses::cpu.data 5 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 5 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 116817 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 116817 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13198 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 13198 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 271974 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 271974 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 13198 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 388791 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 401989 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 13198 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 388791 # number of overall misses -system.cpu.l2cache.overall_misses::total 401989 # number of overall misses -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 246500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 246500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10709040500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 10709040500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1353538000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 1353538000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 21993492000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 21993492000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1353538000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 32702532500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 34056070500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1353538000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 32702532500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 34056070500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 835205 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 835205 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 928450 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 928450 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 304302 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 304302 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 929334 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 929334 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1087022 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1087022 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 929334 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1391324 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2320658 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 929334 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1391324 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2320658 # number of overall (read+write) accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.294118 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.294118 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383885 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.383885 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014202 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014202 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.250201 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.250201 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014202 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.279440 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.173222 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014202 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.279440 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.173222 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 49300 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 49300 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 91673.647671 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 91673.647671 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 102556.296409 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 102556.296409 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80866.156324 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80866.156324 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 102556.296409 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84113.398973 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 84718.911463 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 102556.296409 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84113.398973 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 84718.911463 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 74253 # number of writebacks -system.cpu.l2cache.writebacks::total 74253 # number of writebacks -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 5 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 5 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116817 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 116817 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 13198 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 13198 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 271974 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 271974 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 13198 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 388791 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 401989 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 13198 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 388791 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 401989 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9652 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9652 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16582 # number of overall MSHR uncacheable misses -system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16582 # number of overall MSHR uncacheable misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 196500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 196500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9540870500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9540870500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1221558000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1221558000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19273752000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19273752000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1221558000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 28814622500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 30036180500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1221558000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 28814622500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 30036180500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1447252500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1447252500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1447252500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1447252500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.294118 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.294118 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383885 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383885 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.014202 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014202 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.250201 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.250201 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014202 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279440 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.173222 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014202 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279440 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.173222 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 39300 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 39300 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81673.647671 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81673.647671 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 92556.296409 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 92556.296409 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70866.156324 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70866.156324 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 92556.296409 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74113.398973 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 74718.911463 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 92556.296409 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74113.398973 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 74718.911463 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208838.744589 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208838.744589 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87278.524907 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87278.524907 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 4640189 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2319660 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1516 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 884 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 884 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2023463 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 9652 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 9652 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 909458 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 928683 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 817750 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304302 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304302 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 929354 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1087182 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 219 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2787371 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4206814 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6994185 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 118913088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142552484 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 261465572 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 336953 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 4763520 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2674053 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000958 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.030932 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2671492 99.90% 99.90% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2561 0.10% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2674053 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4097099500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 293383 # Layer occupancy (ticks) -system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1394031000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2098750500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). -system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. -system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_txs 395 # Number of DMA write transactions. -system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. -system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. -system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 7103 # Transaction distribution -system.iobus.trans_dist::ReadResp 7103 # Transaction distribution -system.iobus.trans_dist::WriteReq 51204 # Transaction distribution -system.iobus.trans_dist::WriteResp 51204 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5160 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33164 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 116614 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20640 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 44580 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2706188 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 5344500 # Layer occupancy (ticks) -system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 757500 # Layer occupancy (ticks) -system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks) -system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 10000 # Layer occupancy (ticks) -system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 174000 # Layer occupancy (ticks) -system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 15813000 # Layer occupancy (ticks) -system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 1891500 # Layer occupancy (ticks) -system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 6041500 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 82500 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 216215769 # Layer occupancy (ticks) -system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 23512000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.340614 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1760392723000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.340614 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.083788 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.083788 # Average percentage of cache occupancy -system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id -system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375525 # Number of tag accesses -system.iocache.tags.data_accesses 375525 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses -system.iocache.ReadReq_misses::total 173 # number of ReadReq misses -system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses -system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses -system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses -system.iocache.demand_misses::total 41725 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses -system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21848883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21848883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4937126886 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4937126886 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 4958975769 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4958975769 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 4958975769 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4958975769 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses -system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses -system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses -system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126294.121387 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 126294.121387 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118818.032489 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118818.032489 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 118849.029814 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 118849.029814 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 118849.029814 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 118849.029814 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 700 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 4 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 175 # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.writebacks::writebacks 41512 # number of writebacks -system.iocache.writebacks::total 41512 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13198883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13198883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2857073994 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2857073994 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 2870272877 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2870272877 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 2870272877 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2870272877 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76294.121387 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 76294.121387 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68759.000626 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68759.000626 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68790.242708 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68790.242708 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68790.242708 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68790.242708 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 821141 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 378246 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 407 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 6930 # Transaction distribution -system.membus.trans_dist::ReadResp 292275 # Transaction distribution -system.membus.trans_dist::WriteReq 9652 # Transaction distribution -system.membus.trans_dist::WriteResp 9652 # Transaction distribution -system.membus.trans_dist::WritebackDirty 115765 # Transaction distribution -system.membus.trans_dist::CleanEvict 261592 # Transaction distribution -system.membus.trans_dist::UpgradeReq 136 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 116686 # Transaction distribution -system.membus.trans_dist::ReadExResp 116686 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 285345 # Transaction distribution -system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33164 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1139253 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1172417 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1255842 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44580 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30453760 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30498340 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33156068 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 431 # Total snoops (count) -system.membus.snoopTraffic 27456 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 460301 # Request fanout histogram -system.membus.snoop_fanout::mean 0.001416 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.037609 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 459649 99.86% 99.86% # Request fanout histogram -system.membus.snoop_fanout::1 652 0.14% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 460301 # Request fanout histogram -system.membus.reqLayer0.occupancy 30124000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1287045337 # Layer occupancy (ticks) -system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2142987750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 887117 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post -system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR -system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post -system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post -system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post -system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post -system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post -system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post -system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post -system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post -system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU -system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states -system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1926421414000 # Cumulative time (in ticks) in various power states - ----------- End Simulation Statistics ---------- diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,108 +0,0 @@ -M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 - Got Configuration 623 - memsize 8000000 pages 4000 - First free page after ROM 0xFFFFFC0000018000 - HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000 - kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x1 - CPU Clock at 2000 MHz IntrClockFrequency=1024 - Booting with 1 processor(s) - KSP: 0x20043FE8 PTBR 0x20 - Console Callback at 0x0, fixup at 0x0, crb offset: 0x510 - Memory cluster 0 [0 - 392] - Memory cluster 1 [392 - 15992] - Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000 - ConsoleDispatch at virt 10000658 phys 18658 val FFFFFC00000100A8 - unix_boot_mem ends at FFFFFC0000076000 - k_argc = 0 - jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067) - CallbackFixup 0 18000, t7=FFFFFC000070C000 - Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006 - Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM - Major Options: SMP LEGACY_START VERBOSE_MCHECK - Command line: root=/dev/hda1 console=ttyS0 - memcluster 0, usage 1, start 0, end 392 - memcluster 1, usage 0, start 392, end 16384 - freeing pages 1069:16384 - reserving pages 1069:1070 - 4096K Bcache detected; load hit latency 38 cycles, load miss latency 175 cycles - SMP: 1 CPUs probed -- cpu_present_mask = 1 - Built 1 zonelists - Kernel command line: root=/dev/hda1 console=ttyS0 - PID hash table entries: 1024 (order: 10, 32768 bytes) - Using epoch = 1900 - Console: colour dummy device 80x25 - Dentry cache hash table entries: 32768 (order: 5, 262144 bytes) - Inode-cache hash table entries: 16384 (order: 4, 131072 bytes) - Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init) - Mount-cache hash table entries: 512 - SMP mode deactivated. - Brought up 1 CPUs - SMP: Total of 1 processors activated (4002.20 BogoMIPS). - NET: Registered protocol family 16 - EISA bus registered - pci: enabling save/restore of SRM state - SCSI subsystem initialized - srm_env: version 0.0.5 loaded successfully - Installing knfsd (copyright (C) 1996 okir@monad.swb.de). - Initializing Cryptographic API - rtc: Standard PC (1900) epoch (1900) detected - Real Time Clock Driver v1.12 - Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled - ttyS0 at I/O 0x3f8 (irq = 4) is a 8250 - io scheduler noop registered - io scheduler anticipatory registered - io scheduler deadline registered - io scheduler cfq registered - loop: loaded (max 8 devices) - nbd: registered device at major 43 - ns83820.c: National Semiconductor DP83820 10/100/1000 driver. - PCI: Setting latency timer of device 0000:00:01.0 to 64 - eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000 - eth0: enabling optical transceiver - eth0: using 64 bit addressing. - eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=h,sg - tun: Universal TUN/TAP device driver, 1.6 - tun: (C) 1999-2004 Max Krasnyansky - Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2 - ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx - PIIX4: IDE controller at PCI slot 0000:00:00.0 - PIIX4: chipset revision 0 - PIIX4: 100% native mode on irq 31 - PCI: Setting latency timer of device 0000:00:00.0 to 64 - ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA - ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA - hda: M5 IDE Disk, ATA DISK drive - hdb: M5 IDE Disk, ATA DISK drive - ide0 at 0x8410-0x8417,0x8422 on irq 31 - hda: max request size: 128KiB - hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33) - hda: cache flushes not supported - hda: hda1 - hdb: max request size: 128KiB - hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33) - hdb: cache flushes not supported - hdb: unknown partition table - mice: PS/2 mouse device common for all mice - NET: Registered protocol family 2 - IP route cache hash table entries: 4096 (order: 2, 32768 bytes) - TCP established hash table entries: 16384 (order: 5, 262144 bytes) - TCP bind hash table entries: 16384 (order: 5, 262144 bytes) - TCP: Hash tables configured (established 16384 bind 16384) - TCP reno registered - ip_conntrack version 2.1 (512 buckets, 4096 max) - 296 bytes per conntrack - ip_tables: (C) 2000-2002 Netfilter core team - arp_tables: (C) 2002 David S. Miller - TCP bic registered - Initializing IPsec netlink socket - NET: Registered protocol family 1 - NET: Registered protocol family 17 - NET: Registered protocol family 15 - Bridge firewalling registered - 802.1Q VLAN Support v1.8 Ben Greear - All bugs added by David S. Miller - VFS: Mounted root (ext2 filesystem) readonly. - Freeing unused kernel memory: 224k freed - init started: BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary -mounting filesystems... -EXT2-fs warning: checktime reached, running e2fsck is recommended - loading script... diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini --- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,2188 +0,0 @@ -[drivesys] -type=LinuxAlphaSystem -children=bridge clk_domain cpu disk0 disk2 dvfs_handler intrctrl iobridge iobus membus physmem simple_disk terminal tsunami voltage_domain -boot_cpu_frequency=250 -boot_osflags=root=/dev/hda1 console=ttyS0 -cache_line_size=64 -clk_domain=drivesys.clk_domain -console=/arm/projectscratch/randd/systems/dist/binaries/console -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=atomic -mem_ranges=0:134217727 -memories=drivesys.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pal=/arm/projectscratch/randd/systems/dist/binaries/ts_osfpal -power_model=Null -readfile=/work/curdun01/gem5-external.hg/configs/boot/netperf-server.rcS -symbolfile= -system_rev=1024 -system_type=34 -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=drivesys.membus.slave[0] - -[drivesys.bridge] -type=Bridge -clk_domain=drivesys.clk_domain -default_p_state=UNDEFINED -delay=50000 -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -ranges=8796093022208:18446744073709551615 -req_size=16 -resp_size=16 -master=drivesys.iobus.slave[0] -slave=drivesys.membus.master[0] - -[drivesys.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=drivesys.voltage_domain - -[drivesys.cpu] -type=AtomicSimpleCPU -children=clk_domain dtb interrupts isa itb tracer -branchPred=Null -checker=Null -clk_domain=drivesys.cpu.clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=drivesys.cpu.dtb -eventq_index=0 -fastmem=false -function_trace=false -function_trace_start=0 -interrupts=drivesys.cpu.interrupts -isa=drivesys.cpu.isa -itb=drivesys.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -simulate_data_stalls=false -simulate_inst_stalls=false -socket_id=0 -switched_out=false -system=drivesys -tracer=drivesys.cpu.tracer -width=1 -workload= -dcache_port=drivesys.membus.slave[2] -icache_port=drivesys.membus.slave[1] - -[drivesys.cpu.clk_domain] -type=SrcClockDomain -clock=250 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=drivesys.voltage_domain - -[drivesys.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[drivesys.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[drivesys.cpu.isa] -type=AlphaISA -eventq_index=0 -system=drivesys - -[drivesys.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[drivesys.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[drivesys.disk0] -type=IdeDisk -children=image -delay=1000000 -driveID=master -eventq_index=0 -image=drivesys.disk0.image - -[drivesys.disk0.image] -type=CowDiskImage -children=child -child=drivesys.disk0.image.child -eventq_index=0 -image_file= -read_only=false -table_size=65536 - -[drivesys.disk0.image.child] -type=RawDiskImage -eventq_index=0 -image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img -read_only=true - -[drivesys.disk2] -type=IdeDisk -children=image -delay=1000000 -driveID=master -eventq_index=0 -image=drivesys.disk2.image - -[drivesys.disk2.image] -type=CowDiskImage -children=child -child=drivesys.disk2.image.child -eventq_index=0 -image_file= -read_only=false -table_size=65536 - -[drivesys.disk2.image.child] -type=RawDiskImage -eventq_index=0 -image_file=/arm/projectscratch/randd/systems/dist/disks/linux-bigswap2.img -read_only=true - -[drivesys.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=drivesys.clk_domain -transition_latency=100000000 - -[drivesys.intrctrl] -type=IntrControl -eventq_index=0 -sys=drivesys - -[drivesys.iobridge] -type=Bridge -clk_domain=drivesys.clk_domain -default_p_state=UNDEFINED -delay=50000 -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -ranges=0:134217727 -req_size=16 -resp_size=16 -master=drivesys.membus.slave[3] -slave=drivesys.iobus.master[27] - -[drivesys.iobus] -type=NoncoherentXBar -clk_domain=drivesys.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=1 -frontend_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -response_latency=2 -use_default_range=false -width=16 -master=drivesys.tsunami.cchip.pio drivesys.tsunami.pchip.pio drivesys.tsunami.fake_sm_chip.pio drivesys.tsunami.fake_uart1.pio drivesys.tsunami.fake_uart2.pio drivesys.tsunami.fake_uart3.pio drivesys.tsunami.fake_uart4.pio drivesys.tsunami.fake_ppc.pio drivesys.tsunami.fake_OROM.pio drivesys.tsunami.fake_pnp_addr.pio drivesys.tsunami.fake_pnp_write.pio drivesys.tsunami.fake_pnp_read0.pio drivesys.tsunami.fake_pnp_read1.pio drivesys.tsunami.fake_pnp_read2.pio drivesys.tsunami.fake_pnp_read3.pio drivesys.tsunami.fake_pnp_read4.pio drivesys.tsunami.fake_pnp_read5.pio drivesys.tsunami.fake_pnp_read6.pio drivesys.tsunami.fake_pnp_read7.pio drivesys.tsunami.fake_ata0.pio drivesys.tsunami.fake_ata1.pio drivesys.tsunami.fb.pio drivesys.tsunami.io.pio drivesys.tsunami.uart.pio drivesys.tsunami.backdoor.pio drivesys.tsunami.ide.pio drivesys.tsunami.ethernet.pio drivesys.iobridge.slave -slave=drivesys.bridge.master drivesys.tsunami.ide.dma drivesys.tsunami.ethernet.dma - -[drivesys.membus] -type=CoherentXBar -children=badaddr_responder -clk_domain=drivesys.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=Null -snoop_response_latency=4 -system=drivesys -use_default_range=false -width=16 -default=drivesys.membus.badaddr_responder.pio -master=drivesys.bridge.slave drivesys.physmem.port -slave=drivesys.system_port drivesys.cpu.icache_port drivesys.cpu.dcache_port drivesys.iobridge.master - -[drivesys.membus.badaddr_responder] -type=IsaFake -clk_domain=drivesys.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=0 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=true -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=drivesys -update_data=false -warn_access= -pio=drivesys.membus.default - -[drivesys.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=drivesys.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=0:134217727 -port=drivesys.membus.master[1] - -[drivesys.simple_disk] -type=SimpleDisk -children=disk -disk=drivesys.simple_disk.disk -eventq_index=0 -system=drivesys - -[drivesys.simple_disk.disk] -type=RawDiskImage -eventq_index=0 -image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img -read_only=true - -[drivesys.terminal] -type=Terminal -eventq_index=0 -intr_control=drivesys.intrctrl -number=0 -output=true -port=3456 - -[drivesys.tsunami] -type=Tsunami -children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip uart -eventq_index=0 -intrctrl=drivesys.intrctrl -system=drivesys - -[drivesys.tsunami.backdoor] -type=AlphaBackdoor -clk_domain=drivesys.clk_domain -cpu=drivesys.cpu -default_p_state=UNDEFINED -disk=drivesys.simple_disk -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804682956800 -pio_latency=100000 -platform=drivesys.tsunami -power_model=Null -system=drivesys -terminal=drivesys.terminal -pio=drivesys.iobus.master[24] - -[drivesys.tsunami.cchip] -type=TsunamiCChip -clk_domain=drivesys.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8803072344064 -pio_latency=100000 -power_model=Null -system=drivesys -tsunami=drivesys.tsunami -pio=drivesys.iobus.master[0] - -[drivesys.tsunami.ethernet] -type=NSGigE -children=clk_domain -BAR0=1 -BAR0LegacyIO=false -BAR0Size=256 -BAR1=0 -BAR1LegacyIO=false -BAR1Size=4096 -BAR2=0 -BAR2LegacyIO=false -BAR2Size=0 -BAR3=0 -BAR3LegacyIO=false -BAR3Size=0 -BAR4=0 -BAR4LegacyIO=false -BAR4Size=0 -BAR5=0 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=2 -Command=0 -DeviceID=34 -ExpansionROM=0 -HeaderType=0 -InterruptLine=30 -InterruptPin=1 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=52 -MinimumGrant=176 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=0 -Revision=0 -Status=656 -SubClassCode=0 -SubsystemID=0 -SubsystemVendorID=0 -VendorID=4107 -clk_domain=drivesys.tsunami.ethernet.clk_domain -config_latency=20000 -default_p_state=UNDEFINED -dma_data_free=false -dma_desc_free=false -dma_no_allocate=true -dma_read_delay=0 -dma_read_factor=0 -dma_write_delay=0 -dma_write_factor=0 -eventq_index=0 -hardware_address=00:90:00:00:00:01 -host=drivesys.tsunami.pchip -intr_delay=10000000 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_bus=0 -pci_dev=1 -pci_func=0 -pio_latency=30000 -power_model=Null -rss=false -rx_delay=1000000 -rx_fifo_size=524288 -rx_filter=true -rx_thread=false -system=drivesys -tx_delay=1000000 -tx_fifo_size=524288 -tx_thread=false -dma=drivesys.iobus.slave[2] -interface=etherlink.int1 -pio=drivesys.iobus.master[26] - -[drivesys.tsunami.ethernet.clk_domain] -type=SrcClockDomain -clock=2000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=drivesys.voltage_domain - -[drivesys.tsunami.fake_OROM] -type=IsaFake -clk_domain=drivesys.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8796093677568 -pio_latency=100000 -pio_size=393216 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=drivesys -update_data=false -warn_access= -pio=drivesys.iobus.master[8] - -[drivesys.tsunami.fake_ata0] -type=IsaFake -clk_domain=drivesys.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848432 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=drivesys -update_data=false -warn_access= -pio=drivesys.iobus.master[19] - -[drivesys.tsunami.fake_ata1] -type=IsaFake -clk_domain=drivesys.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848304 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=drivesys -update_data=false -warn_access= -pio=drivesys.iobus.master[20] - -[drivesys.tsunami.fake_pnp_addr] -type=IsaFake -clk_domain=drivesys.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848569 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=drivesys -update_data=false -warn_access= -pio=drivesys.iobus.master[9] - -[drivesys.tsunami.fake_pnp_read0] -type=IsaFake -clk_domain=drivesys.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848451 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=drivesys -update_data=false -warn_access= -pio=drivesys.iobus.master[11] - -[drivesys.tsunami.fake_pnp_read1] -type=IsaFake -clk_domain=drivesys.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848515 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=drivesys -update_data=false -warn_access= -pio=drivesys.iobus.master[12] - -[drivesys.tsunami.fake_pnp_read2] -type=IsaFake -clk_domain=drivesys.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848579 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=drivesys -update_data=false -warn_access= -pio=drivesys.iobus.master[13] - -[drivesys.tsunami.fake_pnp_read3] -type=IsaFake -clk_domain=drivesys.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848643 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=drivesys -update_data=false -warn_access= -pio=drivesys.iobus.master[14] - -[drivesys.tsunami.fake_pnp_read4] -type=IsaFake -clk_domain=drivesys.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848707 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=drivesys -update_data=false -warn_access= -pio=drivesys.iobus.master[15] - -[drivesys.tsunami.fake_pnp_read5] -type=IsaFake -clk_domain=drivesys.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848771 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=drivesys -update_data=false -warn_access= -pio=drivesys.iobus.master[16] - -[drivesys.tsunami.fake_pnp_read6] -type=IsaFake -clk_domain=drivesys.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848835 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=drivesys -update_data=false -warn_access= -pio=drivesys.iobus.master[17] - -[drivesys.tsunami.fake_pnp_read7] -type=IsaFake -clk_domain=drivesys.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848899 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=drivesys -update_data=false -warn_access= -pio=drivesys.iobus.master[18] - -[drivesys.tsunami.fake_pnp_write] -type=IsaFake -clk_domain=drivesys.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615850617 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=drivesys -update_data=false -warn_access= -pio=drivesys.iobus.master[10] - -[drivesys.tsunami.fake_ppc] -type=IsaFake -clk_domain=drivesys.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848891 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=drivesys -update_data=false -warn_access= -pio=drivesys.iobus.master[7] - -[drivesys.tsunami.fake_sm_chip] -type=IsaFake -clk_domain=drivesys.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848816 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=drivesys -update_data=false -warn_access= -pio=drivesys.iobus.master[2] - -[drivesys.tsunami.fake_uart1] -type=IsaFake -clk_domain=drivesys.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848696 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=drivesys -update_data=false -warn_access= -pio=drivesys.iobus.master[3] - -[drivesys.tsunami.fake_uart2] -type=IsaFake -clk_domain=drivesys.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848936 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=drivesys -update_data=false -warn_access= -pio=drivesys.iobus.master[4] - -[drivesys.tsunami.fake_uart3] -type=IsaFake -clk_domain=drivesys.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848680 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=drivesys -update_data=false -warn_access= -pio=drivesys.iobus.master[5] - -[drivesys.tsunami.fake_uart4] -type=IsaFake -clk_domain=drivesys.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848944 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=drivesys -update_data=false -warn_access= -pio=drivesys.iobus.master[6] - -[drivesys.tsunami.fb] -type=BadDevice -clk_domain=drivesys.clk_domain -default_p_state=UNDEFINED -devicename=FrameBuffer -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848912 -pio_latency=100000 -power_model=Null -system=drivesys -pio=drivesys.iobus.master[21] - -[drivesys.tsunami.ide] -type=IdeController -BAR0=1 -BAR0LegacyIO=false -BAR0Size=8 -BAR1=1 -BAR1LegacyIO=false -BAR1Size=4 -BAR2=1 -BAR2LegacyIO=false -BAR2Size=8 -BAR3=1 -BAR3LegacyIO=false -BAR3Size=4 -BAR4=1 -BAR4LegacyIO=false -BAR4Size=16 -BAR5=1 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=1 -Command=0 -DeviceID=28945 -ExpansionROM=0 -HeaderType=0 -InterruptLine=31 -InterruptPin=1 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=0 -MinimumGrant=0 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=133 -Revision=0 -Status=640 -SubClassCode=1 -SubsystemID=0 -SubsystemVendorID=0 -VendorID=32902 -clk_domain=drivesys.clk_domain -config_latency=20000 -ctrl_offset=0 -default_p_state=UNDEFINED -disks=drivesys.disk0 drivesys.disk2 -eventq_index=0 -host=drivesys.tsunami.pchip -io_shift=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_bus=0 -pci_dev=0 -pci_func=0 -pio_latency=30000 -power_model=Null -system=drivesys -dma=drivesys.iobus.slave[1] -pio=drivesys.iobus.master[25] - -[drivesys.tsunami.io] -type=TsunamiIO -clk_domain=drivesys.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -frequency=976562500 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615847936 -pio_latency=100000 -power_model=Null -system=drivesys -time=Thu Jan 1 00:00:00 2009 -tsunami=drivesys.tsunami -year_is_bcd=false -pio=drivesys.iobus.master[22] - -[drivesys.tsunami.pchip] -type=TsunamiPChip -clk_domain=drivesys.clk_domain -conf_base=8804649402368 -conf_device_bits=8 -conf_size=16777216 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_dma_base=0 -pci_mem_base=8796093022208 -pci_pio_base=8804615847936 -pio_addr=8802535473152 -pio_latency=100000 -platform=drivesys.tsunami -power_model=Null -system=drivesys -tsunami=drivesys.tsunami -pio=drivesys.iobus.master[1] - -[drivesys.tsunami.uart] -type=Uart8250 -clk_domain=drivesys.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848952 -pio_latency=100000 -platform=drivesys.tsunami -power_model=Null -system=drivesys -terminal=drivesys.terminal -pio=drivesys.iobus.master[23] - -[drivesys.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - -[etherdump] -type=EtherDump -eventq_index=0 -file=ethertrace -maxlen=96 - -[etherlink] -type=EtherLink -delay=0 -delay_var=0 -dump=etherdump -eventq_index=0 -speed=8000.000000 -int0=testsys.tsunami.ethernet.interface -int1=drivesys.tsunami.ethernet.interface - -[root] -type=Root -children=drivesys etherdump etherlink testsys -eventq_index=0 -full_system=true -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[testsys] -type=LinuxAlphaSystem -children=bridge clk_domain cpu disk0 disk2 dvfs_handler intrctrl iobridge iobus membus physmem simple_disk terminal tsunami voltage_domain -boot_cpu_frequency=500 -boot_osflags=root=/dev/hda1 console=ttyS0 -cache_line_size=64 -clk_domain=testsys.clk_domain -console=/arm/projectscratch/randd/systems/dist/binaries/console -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=atomic -mem_ranges=0:134217727 -memories=testsys.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pal=/arm/projectscratch/randd/systems/dist/binaries/ts_osfpal -power_model=Null -readfile=/work/curdun01/gem5-external.hg/configs/boot/netperf-stream-client.rcS -symbolfile= -system_rev=1024 -system_type=34 -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=testsys.membus.slave[0] - -[testsys.bridge] -type=Bridge -clk_domain=testsys.clk_domain -default_p_state=UNDEFINED -delay=50000 -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -ranges=8796093022208:18446744073709551615 -req_size=16 -resp_size=16 -master=testsys.iobus.slave[0] -slave=testsys.membus.master[0] - -[testsys.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=testsys.voltage_domain - -[testsys.cpu] -type=AtomicSimpleCPU -children=clk_domain dtb interrupts isa itb tracer -branchPred=Null -checker=Null -clk_domain=testsys.cpu.clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=testsys.cpu.dtb -eventq_index=0 -fastmem=false -function_trace=false -function_trace_start=0 -interrupts=testsys.cpu.interrupts -isa=testsys.cpu.isa -itb=testsys.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -simulate_data_stalls=false -simulate_inst_stalls=false -socket_id=0 -switched_out=false -system=testsys -tracer=testsys.cpu.tracer -width=1 -workload= -dcache_port=testsys.membus.slave[2] -icache_port=testsys.membus.slave[1] - -[testsys.cpu.clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=testsys.voltage_domain - -[testsys.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[testsys.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[testsys.cpu.isa] -type=AlphaISA -eventq_index=0 -system=testsys - -[testsys.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[testsys.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[testsys.disk0] -type=IdeDisk -children=image -delay=1000000 -driveID=master -eventq_index=0 -image=testsys.disk0.image - -[testsys.disk0.image] -type=CowDiskImage -children=child -child=testsys.disk0.image.child -eventq_index=0 -image_file= -read_only=false -table_size=65536 - -[testsys.disk0.image.child] -type=RawDiskImage -eventq_index=0 -image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img -read_only=true - -[testsys.disk2] -type=IdeDisk -children=image -delay=1000000 -driveID=master -eventq_index=0 -image=testsys.disk2.image - -[testsys.disk2.image] -type=CowDiskImage -children=child -child=testsys.disk2.image.child -eventq_index=0 -image_file= -read_only=false -table_size=65536 - -[testsys.disk2.image.child] -type=RawDiskImage -eventq_index=0 -image_file=/arm/projectscratch/randd/systems/dist/disks/linux-bigswap2.img -read_only=true - -[testsys.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=testsys.clk_domain -transition_latency=100000000 - -[testsys.intrctrl] -type=IntrControl -eventq_index=0 -sys=testsys - -[testsys.iobridge] -type=Bridge -clk_domain=testsys.clk_domain -default_p_state=UNDEFINED -delay=50000 -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -ranges=0:134217727 -req_size=16 -resp_size=16 -master=testsys.membus.slave[3] -slave=testsys.iobus.master[27] - -[testsys.iobus] -type=NoncoherentXBar -clk_domain=testsys.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=1 -frontend_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -response_latency=2 -use_default_range=false -width=16 -master=testsys.tsunami.cchip.pio testsys.tsunami.pchip.pio testsys.tsunami.fake_sm_chip.pio testsys.tsunami.fake_uart1.pio testsys.tsunami.fake_uart2.pio testsys.tsunami.fake_uart3.pio testsys.tsunami.fake_uart4.pio testsys.tsunami.fake_ppc.pio testsys.tsunami.fake_OROM.pio testsys.tsunami.fake_pnp_addr.pio testsys.tsunami.fake_pnp_write.pio testsys.tsunami.fake_pnp_read0.pio testsys.tsunami.fake_pnp_read1.pio testsys.tsunami.fake_pnp_read2.pio testsys.tsunami.fake_pnp_read3.pio testsys.tsunami.fake_pnp_read4.pio testsys.tsunami.fake_pnp_read5.pio testsys.tsunami.fake_pnp_read6.pio testsys.tsunami.fake_pnp_read7.pio testsys.tsunami.fake_ata0.pio testsys.tsunami.fake_ata1.pio testsys.tsunami.fb.pio testsys.tsunami.io.pio testsys.tsunami.uart.pio testsys.tsunami.backdoor.pio testsys.tsunami.ide.pio testsys.tsunami.ethernet.pio testsys.iobridge.slave -slave=testsys.bridge.master testsys.tsunami.ide.dma testsys.tsunami.ethernet.dma - -[testsys.membus] -type=CoherentXBar -children=badaddr_responder -clk_domain=testsys.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=Null -snoop_response_latency=4 -system=testsys -use_default_range=false -width=16 -default=testsys.membus.badaddr_responder.pio -master=testsys.bridge.slave testsys.physmem.port -slave=testsys.system_port testsys.cpu.icache_port testsys.cpu.dcache_port testsys.iobridge.master - -[testsys.membus.badaddr_responder] -type=IsaFake -clk_domain=testsys.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=0 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=true -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=testsys -update_data=false -warn_access= -pio=testsys.membus.default - -[testsys.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=testsys.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=0:134217727 -port=testsys.membus.master[1] - -[testsys.simple_disk] -type=SimpleDisk -children=disk -disk=testsys.simple_disk.disk -eventq_index=0 -system=testsys - -[testsys.simple_disk.disk] -type=RawDiskImage -eventq_index=0 -image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img -read_only=true - -[testsys.terminal] -type=Terminal -eventq_index=0 -intr_control=testsys.intrctrl -number=0 -output=true -port=3456 - -[testsys.tsunami] -type=Tsunami -children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip uart -eventq_index=0 -intrctrl=testsys.intrctrl -system=testsys - -[testsys.tsunami.backdoor] -type=AlphaBackdoor -clk_domain=testsys.clk_domain -cpu=testsys.cpu -default_p_state=UNDEFINED -disk=testsys.simple_disk -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804682956800 -pio_latency=100000 -platform=testsys.tsunami -power_model=Null -system=testsys -terminal=testsys.terminal -pio=testsys.iobus.master[24] - -[testsys.tsunami.cchip] -type=TsunamiCChip -clk_domain=testsys.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8803072344064 -pio_latency=100000 -power_model=Null -system=testsys -tsunami=testsys.tsunami -pio=testsys.iobus.master[0] - -[testsys.tsunami.ethernet] -type=NSGigE -children=clk_domain -BAR0=1 -BAR0LegacyIO=false -BAR0Size=256 -BAR1=0 -BAR1LegacyIO=false -BAR1Size=4096 -BAR2=0 -BAR2LegacyIO=false -BAR2Size=0 -BAR3=0 -BAR3LegacyIO=false -BAR3Size=0 -BAR4=0 -BAR4LegacyIO=false -BAR4Size=0 -BAR5=0 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=2 -Command=0 -DeviceID=34 -ExpansionROM=0 -HeaderType=0 -InterruptLine=30 -InterruptPin=1 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=52 -MinimumGrant=176 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=0 -Revision=0 -Status=656 -SubClassCode=0 -SubsystemID=0 -SubsystemVendorID=0 -VendorID=4107 -clk_domain=testsys.tsunami.ethernet.clk_domain -config_latency=20000 -default_p_state=UNDEFINED -dma_data_free=false -dma_desc_free=false -dma_no_allocate=true -dma_read_delay=0 -dma_read_factor=0 -dma_write_delay=0 -dma_write_factor=0 -eventq_index=0 -hardware_address=00:90:00:00:00:02 -host=testsys.tsunami.pchip -intr_delay=10000000 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_bus=0 -pci_dev=1 -pci_func=0 -pio_latency=30000 -power_model=Null -rss=false -rx_delay=1000000 -rx_fifo_size=524288 -rx_filter=true -rx_thread=false -system=testsys -tx_delay=1000000 -tx_fifo_size=524288 -tx_thread=false -dma=testsys.iobus.slave[2] -interface=etherlink.int0 -pio=testsys.iobus.master[26] - -[testsys.tsunami.ethernet.clk_domain] -type=SrcClockDomain -clock=2000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=testsys.voltage_domain - -[testsys.tsunami.fake_OROM] -type=IsaFake -clk_domain=testsys.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8796093677568 -pio_latency=100000 -pio_size=393216 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=testsys -update_data=false -warn_access= -pio=testsys.iobus.master[8] - -[testsys.tsunami.fake_ata0] -type=IsaFake -clk_domain=testsys.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848432 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=testsys -update_data=false -warn_access= -pio=testsys.iobus.master[19] - -[testsys.tsunami.fake_ata1] -type=IsaFake -clk_domain=testsys.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848304 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=testsys -update_data=false -warn_access= -pio=testsys.iobus.master[20] - -[testsys.tsunami.fake_pnp_addr] -type=IsaFake -clk_domain=testsys.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848569 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=testsys -update_data=false -warn_access= -pio=testsys.iobus.master[9] - -[testsys.tsunami.fake_pnp_read0] -type=IsaFake -clk_domain=testsys.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848451 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=testsys -update_data=false -warn_access= -pio=testsys.iobus.master[11] - -[testsys.tsunami.fake_pnp_read1] -type=IsaFake -clk_domain=testsys.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848515 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=testsys -update_data=false -warn_access= -pio=testsys.iobus.master[12] - -[testsys.tsunami.fake_pnp_read2] -type=IsaFake -clk_domain=testsys.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848579 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=testsys -update_data=false -warn_access= -pio=testsys.iobus.master[13] - -[testsys.tsunami.fake_pnp_read3] -type=IsaFake -clk_domain=testsys.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848643 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=testsys -update_data=false -warn_access= -pio=testsys.iobus.master[14] - -[testsys.tsunami.fake_pnp_read4] -type=IsaFake -clk_domain=testsys.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848707 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=testsys -update_data=false -warn_access= -pio=testsys.iobus.master[15] - -[testsys.tsunami.fake_pnp_read5] -type=IsaFake -clk_domain=testsys.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848771 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=testsys -update_data=false -warn_access= -pio=testsys.iobus.master[16] - -[testsys.tsunami.fake_pnp_read6] -type=IsaFake -clk_domain=testsys.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848835 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=testsys -update_data=false -warn_access= -pio=testsys.iobus.master[17] - -[testsys.tsunami.fake_pnp_read7] -type=IsaFake -clk_domain=testsys.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848899 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=testsys -update_data=false -warn_access= -pio=testsys.iobus.master[18] - -[testsys.tsunami.fake_pnp_write] -type=IsaFake -clk_domain=testsys.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615850617 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=testsys -update_data=false -warn_access= -pio=testsys.iobus.master[10] - -[testsys.tsunami.fake_ppc] -type=IsaFake -clk_domain=testsys.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848891 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=testsys -update_data=false -warn_access= -pio=testsys.iobus.master[7] - -[testsys.tsunami.fake_sm_chip] -type=IsaFake -clk_domain=testsys.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848816 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=testsys -update_data=false -warn_access= -pio=testsys.iobus.master[2] - -[testsys.tsunami.fake_uart1] -type=IsaFake -clk_domain=testsys.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848696 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=testsys -update_data=false -warn_access= -pio=testsys.iobus.master[3] - -[testsys.tsunami.fake_uart2] -type=IsaFake -clk_domain=testsys.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848936 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=testsys -update_data=false -warn_access= -pio=testsys.iobus.master[4] - -[testsys.tsunami.fake_uart3] -type=IsaFake -clk_domain=testsys.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848680 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=testsys -update_data=false -warn_access= -pio=testsys.iobus.master[5] - -[testsys.tsunami.fake_uart4] -type=IsaFake -clk_domain=testsys.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848944 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=testsys -update_data=false -warn_access= -pio=testsys.iobus.master[6] - -[testsys.tsunami.fb] -type=BadDevice -clk_domain=testsys.clk_domain -default_p_state=UNDEFINED -devicename=FrameBuffer -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848912 -pio_latency=100000 -power_model=Null -system=testsys -pio=testsys.iobus.master[21] - -[testsys.tsunami.ide] -type=IdeController -BAR0=1 -BAR0LegacyIO=false -BAR0Size=8 -BAR1=1 -BAR1LegacyIO=false -BAR1Size=4 -BAR2=1 -BAR2LegacyIO=false -BAR2Size=8 -BAR3=1 -BAR3LegacyIO=false -BAR3Size=4 -BAR4=1 -BAR4LegacyIO=false -BAR4Size=16 -BAR5=1 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=1 -Command=0 -DeviceID=28945 -ExpansionROM=0 -HeaderType=0 -InterruptLine=31 -InterruptPin=1 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=0 -MinimumGrant=0 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=133 -Revision=0 -Status=640 -SubClassCode=1 -SubsystemID=0 -SubsystemVendorID=0 -VendorID=32902 -clk_domain=testsys.clk_domain -config_latency=20000 -ctrl_offset=0 -default_p_state=UNDEFINED -disks=testsys.disk0 testsys.disk2 -eventq_index=0 -host=testsys.tsunami.pchip -io_shift=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_bus=0 -pci_dev=0 -pci_func=0 -pio_latency=30000 -power_model=Null -system=testsys -dma=testsys.iobus.slave[1] -pio=testsys.iobus.master[25] - -[testsys.tsunami.io] -type=TsunamiIO -clk_domain=testsys.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -frequency=976562500 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615847936 -pio_latency=100000 -power_model=Null -system=testsys -time=Thu Jan 1 00:00:00 2009 -tsunami=testsys.tsunami -year_is_bcd=false -pio=testsys.iobus.master[22] - -[testsys.tsunami.pchip] -type=TsunamiPChip -clk_domain=testsys.clk_domain -conf_base=8804649402368 -conf_device_bits=8 -conf_size=16777216 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_dma_base=0 -pci_mem_base=8796093022208 -pci_pio_base=8804615847936 -pio_addr=8802535473152 -pio_latency=100000 -platform=testsys.tsunami -power_model=Null -system=testsys -tsunami=testsys.tsunami -pio=testsys.iobus.master[1] - -[testsys.tsunami.uart] -type=Uart8250 -clk_domain=testsys.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848952 -pio_latency=100000 -platform=testsys.tsunami -power_model=Null -system=testsys -terminal=testsys.terminal -pio=testsys.iobus.master[23] - -[testsys.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal --- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,114 +0,0 @@ -M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 - Got Configuration 623 - memsize 8000000 pages 4000 - First free page after ROM 0xFFFFFC0000018000 - HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000 - kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x1 - CPU Clock at 4000 MHz IntrClockFrequency=1024 - Booting with 1 processor(s) - KSP: 0x20043FE8 PTBR 0x20 - Console Callback at 0x0, fixup at 0x0, crb offset: 0x510 - Memory cluster 0 [0 - 392] - Memory cluster 1 [392 - 15992] - Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000 - ConsoleDispatch at virt 10000658 phys 18658 val FFFFFC00000100A8 - unix_boot_mem ends at FFFFFC0000076000 - k_argc = 0 - jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067) - CallbackFixup 0 18000, t7=FFFFFC000070C000 - Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006 - Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM - Major Options: SMP LEGACY_START VERBOSE_MCHECK - Command line: root=/dev/hda1 console=ttyS0 - memcluster 0, usage 1, start 0, end 392 - memcluster 1, usage 0, start 392, end 16384 - freeing pages 1069:16384 - reserving pages 1069:1070 - SMP: 1 CPUs probed -- cpu_present_mask = 1 - Built 1 zonelists - Kernel command line: root=/dev/hda1 console=ttyS0 - PID hash table entries: 1024 (order: 10, 32768 bytes) - Using epoch = 1900 - Console: colour dummy device 80x25 - Dentry cache hash table entries: 32768 (order: 5, 262144 bytes) - Inode-cache hash table entries: 16384 (order: 4, 131072 bytes) - Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init) - Mount-cache hash table entries: 512 - SMP mode deactivated. - Brought up 1 CPUs - SMP: Total of 1 processors activated (8000.15 BogoMIPS). - NET: Registered protocol family 16 - EISA bus registered - pci: enabling save/restore of SRM state - SCSI subsystem initialized - srm_env: version 0.0.5 loaded successfully - Installing knfsd (copyright (C) 1996 okir@monad.swb.de). - Initializing Cryptographic API - rtc: Standard PC (1900) epoch (1900) detected - Real Time Clock Driver v1.12 - Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled - ttyS0 at I/O 0x3f8 (irq = 4) is a 8250 - io scheduler noop registered - io scheduler anticipatory registered - io scheduler deadline registered - io scheduler cfq registered - loop: loaded (max 8 devices) - nbd: registered device at major 43 - ns83820.c: National Semiconductor DP83820 10/100/1000 driver. - PCI: Setting latency timer of device 0000:00:01.0 to 64 - eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000 - eth0: enabling optical transceiver - eth0: using 64 bit addressing. - eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=h,sg - tun: Universal TUN/TAP device driver, 1.6 - tun: (C) 1999-2004 Max Krasnyansky - Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2 - ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx - PIIX4: IDE controller at PCI slot 0000:00:00.0 - PIIX4: chipset revision 0 - PIIX4: 100% native mode on irq 31 - PCI: Setting latency timer of device 0000:00:00.0 to 64 - ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA - ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA - hda: M5 IDE Disk, ATA DISK drive - hdb: M5 IDE Disk, ATA DISK drive - ide0 at 0x8410-0x8417,0x8422 on irq 31 - hda: max request size: 128KiB - hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33) - hda: cache flushes not supported - hda: hda1 - hdb: max request size: 128KiB - hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33) - hdb: cache flushes not supported - hdb: unknown partition table - mice: PS/2 mouse device common for all mice - NET: Registered protocol family 2 - IP route cache hash table entries: 4096 (order: 2, 32768 bytes) - TCP established hash table entries: 16384 (order: 5, 262144 bytes) - TCP bind hash table entries: 16384 (order: 5, 262144 bytes) - TCP: Hash tables configured (established 16384 bind 16384) - TCP reno registered - ip_conntrack version 2.1 (512 buckets, 4096 max) - 296 bytes per conntrack - ip_tables: (C) 2000-2002 Netfilter core team - arp_tables: (C) 2002 David S. Miller - TCP bic registered - Initializing IPsec netlink socket - NET: Registered protocol family 1 - NET: Registered protocol family 17 - NET: Registered protocol family 15 - Bridge firewalling registered - 802.1Q VLAN Support v1.8 Ben Greear - All bugs added by David S. Miller - VFS: Mounted root (ext2 filesystem) readonly. - Freeing unused kernel memory: 224k freed - init started: BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary -mounting filesystems... -EXT2-fs warning: checktime reached, running e2fsck is recommended - loading script... -setting up network... -eth0: link now 1000F mbps, full duplex and up. - running netserver... -Starting netserver at port 12865 -signal client to begin...done. -starting bash... -# \ No newline at end of file diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr --- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,7 +0,0 @@ -warn: Sockets disabled, not accepting terminal connections -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Obsolete M5 ivlb instruction encountered. diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout --- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,17 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 19 2016 12:24:23 -gem5 executing on e108600-lin, pid 39549 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic - -Global frequency set at 1000000000000 ticks per second -info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux - 0: drivesys.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux - 0: testsys.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 4321620817500 because checkpoint diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt --- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,1358 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.200409 # Number of seconds simulated -sim_ticks 200409271000 # Number of ticks simulated -final_tick 4321213476000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 19542475 # Simulator instruction rate (inst/s) -host_op_rate 19542467 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7477344580 # Simulator tick rate (ticks/s) -host_mem_usage 503180 # Number of bytes of host memory used -host_seconds 26.80 # Real time elapsed on the host -sim_insts 523780905 # Number of instructions simulated -sim_ops 523780905 # Number of ops (including micro ops) simulated -drivesys.voltage_domain.voltage 1 # Voltage in Volts -drivesys.clk_domain.clock 1000 # Clock period in ticks -drivesys.physmem.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -drivesys.physmem.bytes_read::cpu.inst 76205572 # Number of bytes read from this memory -drivesys.physmem.bytes_read::cpu.data 26284292 # Number of bytes read from this memory -drivesys.physmem.bytes_read::tsunami.ethernet 57260550 # Number of bytes read from this memory -drivesys.physmem.bytes_read::total 159750414 # Number of bytes read from this memory -drivesys.physmem.bytes_inst_read::cpu.inst 76205572 # Number of instructions bytes read from this memory -drivesys.physmem.bytes_inst_read::total 76205572 # Number of instructions bytes read from this memory -drivesys.physmem.bytes_written::cpu.data 14619632 # Number of bytes written to this memory -drivesys.physmem.bytes_written::tsunami.ethernet 1064 # Number of bytes written to this memory -drivesys.physmem.bytes_written::total 14620696 # Number of bytes written to this memory -drivesys.physmem.num_reads::cpu.inst 19051393 # Number of read requests responded to by this memory -drivesys.physmem.num_reads::cpu.data 3647049 # Number of read requests responded to by this memory -drivesys.physmem.num_reads::tsunami.ethernet 2385839 # Number of read requests responded to by this memory -drivesys.physmem.num_reads::total 25084281 # Number of read requests responded to by this memory -drivesys.physmem.num_writes::cpu.data 2024776 # Number of write requests responded to by this memory -drivesys.physmem.num_writes::tsunami.ethernet 37 # Number of write requests responded to by this memory -drivesys.physmem.num_writes::total 2024813 # Number of write requests responded to by this memory -drivesys.physmem.bw_read::cpu.inst 380249734 # Total read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_read::cpu.data 131153074 # Total read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_read::tsunami.ethernet 285718069 # Total read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_read::total 797120878 # Total read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_inst_read::cpu.inst 380249734 # Instruction read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_inst_read::total 380249734 # Instruction read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_write::cpu.data 72948881 # Write bandwidth from this memory (bytes/s) -drivesys.physmem.bw_write::tsunami.ethernet 5309 # Write bandwidth from this memory (bytes/s) -drivesys.physmem.bw_write::total 72954190 # Write bandwidth from this memory (bytes/s) -drivesys.physmem.bw_total::cpu.inst 380249734 # Total bandwidth to/from this memory (bytes/s) -drivesys.physmem.bw_total::cpu.data 204101955 # Total bandwidth to/from this memory (bytes/s) -drivesys.physmem.bw_total::tsunami.ethernet 285723379 # Total bandwidth to/from this memory (bytes/s) -drivesys.physmem.bw_total::total 870075068 # Total bandwidth to/from this memory (bytes/s) -drivesys.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -drivesys.bridge.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -drivesys.cpu.clk_domain.clock 250 # Clock period in ticks -drivesys.cpu.dtb.fetch_hits 0 # ITB hits -drivesys.cpu.dtb.fetch_misses 0 # ITB misses -drivesys.cpu.dtb.fetch_acv 0 # ITB acv -drivesys.cpu.dtb.fetch_accesses 0 # ITB accesses -drivesys.cpu.dtb.read_hits 3725273 # DTB read hits -drivesys.cpu.dtb.read_misses 487 # DTB read misses -drivesys.cpu.dtb.read_acv 30 # DTB read access violations -drivesys.cpu.dtb.read_accesses 267991 # DTB read accesses -drivesys.cpu.dtb.write_hits 2084079 # DTB write hits -drivesys.cpu.dtb.write_misses 82 # DTB write misses -drivesys.cpu.dtb.write_acv 10 # DTB write access violations -drivesys.cpu.dtb.write_accesses 133239 # DTB write accesses -drivesys.cpu.dtb.data_hits 5809352 # DTB hits -drivesys.cpu.dtb.data_misses 569 # DTB misses -drivesys.cpu.dtb.data_acv 40 # DTB access violations -drivesys.cpu.dtb.data_accesses 401230 # DTB accesses -drivesys.cpu.itb.fetch_hits 4197628 # ITB hits -drivesys.cpu.itb.fetch_misses 194 # ITB misses -drivesys.cpu.itb.fetch_acv 22 # ITB acv -drivesys.cpu.itb.fetch_accesses 4197822 # ITB accesses -drivesys.cpu.itb.read_hits 0 # DTB read hits -drivesys.cpu.itb.read_misses 0 # DTB read misses -drivesys.cpu.itb.read_acv 0 # DTB read access violations -drivesys.cpu.itb.read_accesses 0 # DTB read accesses -drivesys.cpu.itb.write_hits 0 # DTB write hits -drivesys.cpu.itb.write_misses 0 # DTB write misses -drivesys.cpu.itb.write_acv 0 # DTB write access violations -drivesys.cpu.itb.write_accesses 0 # DTB write accesses -drivesys.cpu.itb.data_hits 0 # DTB hits -drivesys.cpu.itb.data_misses 0 # DTB misses -drivesys.cpu.itb.data_acv 0 # DTB access violations -drivesys.cpu.itb.data_accesses 0 # DTB accesses -drivesys.cpu.numPwrStateTransitions 39752 # Number of power state transitions -drivesys.cpu.pwrStateClkGateDist::samples 19877 # Distribution of time spent in the clock gated state -drivesys.cpu.pwrStateClkGateDist::mean 9843365.409770 # Distribution of time spent in the clock gated state -drivesys.cpu.pwrStateClkGateDist::stdev 830979.613808 # Distribution of time spent in the clock gated state -drivesys.cpu.pwrStateClkGateDist::1000-5e+10 19877 100.00% 100.00% # Distribution of time spent in the clock gated state -drivesys.cpu.pwrStateClkGateDist::min_value 25500 # Distribution of time spent in the clock gated state -drivesys.cpu.pwrStateClkGateDist::max_value 9947500 # Distribution of time spent in the clock gated state -drivesys.cpu.pwrStateClkGateDist::total 19877 # Distribution of time spent in the clock gated state -drivesys.cpu.pwrStateResidencyTicks::ON 4757933250 # Cumulative time (in ticks) in various power states -drivesys.cpu.pwrStateResidencyTicks::CLK_GATED 195656574250 # Cumulative time (in ticks) in various power states -drivesys.cpu.numCycles 801651324 # number of cpu cycles simulated -drivesys.cpu.numWorkItemsStarted 0 # number of work items this cpu started -drivesys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -drivesys.cpu.kern.inst.arm 0 # number of arm instructions executed -drivesys.cpu.kern.inst.quiesce 19876 # number of quiesce instructions executed -drivesys.cpu.kern.inst.hwrei 143591 # number of hwrei instructions executed -drivesys.cpu.kern.ipl_count::0 60359 42.42% 42.42% # number of times we switched to this ipl -drivesys.cpu.kern.ipl_count::21 19727 13.86% 56.28% # number of times we switched to this ipl -drivesys.cpu.kern.ipl_count::22 205 0.14% 56.42% # number of times we switched to this ipl -drivesys.cpu.kern.ipl_count::31 62011 43.58% 100.00% # number of times we switched to this ipl -drivesys.cpu.kern.ipl_count::total 142302 # number of times we switched to this ipl -drivesys.cpu.kern.ipl_good::0 60359 42.91% 42.91% # number of times we switched to this ipl from a different ipl -drivesys.cpu.kern.ipl_good::21 19727 14.03% 56.94% # number of times we switched to this ipl from a different ipl -drivesys.cpu.kern.ipl_good::22 205 0.15% 57.09% # number of times we switched to this ipl from a different ipl -drivesys.cpu.kern.ipl_good::31 60360 42.91% 100.00% # number of times we switched to this ipl from a different ipl -drivesys.cpu.kern.ipl_good::total 140651 # number of times we switched to this ipl from a different ipl -drivesys.cpu.kern.ipl_ticks::0 197399332500 98.50% 98.50% # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_ticks::21 798910750 0.40% 98.90% # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_ticks::22 4407500 0.00% 98.90% # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_ticks::31 2205211250 1.10% 100.00% # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_ticks::total 200407862000 # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_used::0 1 # fraction of swpipl calls that actually changed the ipl -drivesys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl -drivesys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -drivesys.cpu.kern.ipl_used::31 0.973376 # fraction of swpipl calls that actually changed the ipl -drivesys.cpu.kern.ipl_used::total 0.988398 # fraction of swpipl calls that actually changed the ipl -drivesys.cpu.kern.syscall::2 1 4.55% 4.55% # number of syscalls executed -drivesys.cpu.kern.syscall::6 3 13.64% 18.18% # number of syscalls executed -drivesys.cpu.kern.syscall::17 2 9.09% 27.27% # number of syscalls executed -drivesys.cpu.kern.syscall::97 1 4.55% 31.82% # number of syscalls executed -drivesys.cpu.kern.syscall::99 2 9.09% 40.91% # number of syscalls executed -drivesys.cpu.kern.syscall::101 2 9.09% 50.00% # number of syscalls executed -drivesys.cpu.kern.syscall::102 3 13.64% 63.64% # number of syscalls executed -drivesys.cpu.kern.syscall::104 1 4.55% 68.18% # number of syscalls executed -drivesys.cpu.kern.syscall::105 3 13.64% 81.82% # number of syscalls executed -drivesys.cpu.kern.syscall::106 1 4.55% 86.36% # number of syscalls executed -drivesys.cpu.kern.syscall::118 2 9.09% 95.45% # number of syscalls executed -drivesys.cpu.kern.syscall::150 1 4.55% 100.00% # number of syscalls executed -drivesys.cpu.kern.syscall::total 22 # number of syscalls executed -drivesys.cpu.kern.callpal::swpctx 72 0.06% 0.06% # number of callpals executed -drivesys.cpu.kern.callpal::tbi 5 0.00% 0.06% # number of callpals executed -drivesys.cpu.kern.callpal::swpipl 102333 83.31% 83.37% # number of callpals executed -drivesys.cpu.kern.callpal::rdps 354 0.29% 83.66% # number of callpals executed -drivesys.cpu.kern.callpal::rdusp 1 0.00% 83.66% # number of callpals executed -drivesys.cpu.kern.callpal::rti 20038 16.31% 99.97% # number of callpals executed -drivesys.cpu.kern.callpal::callsys 25 0.02% 99.99% # number of callpals executed -drivesys.cpu.kern.callpal::imb 7 0.01% 100.00% # number of callpals executed -drivesys.cpu.kern.callpal::total 122835 # number of callpals executed -drivesys.cpu.kern.mode_switch::kernel 214 # number of protection mode switches -drivesys.cpu.kern.mode_switch::user 140 # number of protection mode switches -drivesys.cpu.kern.mode_switch::idle 19896 # number of protection mode switches -drivesys.cpu.kern.mode_good::kernel 144 -drivesys.cpu.kern.mode_good::user 140 -drivesys.cpu.kern.mode_good::idle 4 -drivesys.cpu.kern.mode_switch_good::kernel 0.672897 # fraction of useful protection mode switches -drivesys.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -drivesys.cpu.kern.mode_switch_good::idle 0.000201 # fraction of useful protection mode switches -drivesys.cpu.kern.mode_switch_good::total 0.014222 # fraction of useful protection mode switches -drivesys.cpu.kern.mode_ticks::kernel 78134250 2.63% 2.63% # number of ticks spent at the given mode -drivesys.cpu.kern.mode_ticks::user 319668250 10.78% 13.41% # number of ticks spent at the given mode -drivesys.cpu.kern.mode_ticks::idle 2567942000 86.59% 100.00% # number of ticks spent at the given mode -drivesys.cpu.kern.swap_context 72 # number of times the context was actually changed -drivesys.cpu.committedInsts 19050784 # Number of instructions committed -drivesys.cpu.committedOps 19050784 # Number of ops (including micro ops) committed -drivesys.cpu.num_int_alu_accesses 17740632 # Number of integer alu accesses -drivesys.cpu.num_fp_alu_accesses 1412 # Number of float alu accesses -drivesys.cpu.num_func_calls 1265024 # number of times a function call or return occured -drivesys.cpu.num_conditional_control_insts 1264985 # number of instructions that are conditional controls -drivesys.cpu.num_int_insts 17740632 # number of integer instructions -drivesys.cpu.num_fp_insts 1412 # number of float instructions -drivesys.cpu.num_int_register_reads 23072330 # number of times the integer registers were read -drivesys.cpu.num_int_register_writes 13981107 # number of times the integer registers were written -drivesys.cpu.num_fp_register_reads 760 # number of times the floating registers were read -drivesys.cpu.num_fp_register_writes 766 # number of times the floating registers were written -drivesys.cpu.num_mem_refs 5830788 # number of memory refs -drivesys.cpu.num_load_insts 3746196 # Number of load instructions -drivesys.cpu.num_store_insts 2084592 # Number of store instructions -drivesys.cpu.num_idle_cycles 782619252.927065 # Number of idle cycles -drivesys.cpu.num_busy_cycles 19032071.072935 # Number of busy cycles -drivesys.cpu.not_idle_fraction 0.023741 # Percentage of non-idle cycles -drivesys.cpu.idle_fraction 0.976259 # Percentage of idle cycles -drivesys.cpu.Branches 2793313 # Number of branches fetched -drivesys.cpu.op_class::No_OpClass 623554 3.27% 3.27% # Class of executed instruction -drivesys.cpu.op_class::IntAlu 11538627 60.57% 63.84% # Class of executed instruction -drivesys.cpu.op_class::IntMult 20663 0.11% 63.95% # Class of executed instruction -drivesys.cpu.op_class::IntDiv 0 0.00% 63.95% # Class of executed instruction -drivesys.cpu.op_class::FloatAdd 141 0.00% 63.95% # Class of executed instruction -drivesys.cpu.op_class::FloatCmp 0 0.00% 63.95% # Class of executed instruction -drivesys.cpu.op_class::FloatCvt 0 0.00% 63.95% # Class of executed instruction -drivesys.cpu.op_class::FloatMult 0 0.00% 63.95% # Class of executed instruction -drivesys.cpu.op_class::FloatMultAcc 0 0.00% 63.95% # Class of executed instruction -drivesys.cpu.op_class::FloatDiv 23 0.00% 63.95% # Class of executed instruction -drivesys.cpu.op_class::FloatMisc 0 0.00% 63.95% # Class of executed instruction -drivesys.cpu.op_class::FloatSqrt 0 0.00% 63.95% # Class of executed instruction -drivesys.cpu.op_class::SimdAdd 0 0.00% 63.95% # Class of executed instruction -drivesys.cpu.op_class::SimdAddAcc 0 0.00% 63.95% # Class of executed instruction -drivesys.cpu.op_class::SimdAlu 0 0.00% 63.95% # Class of executed instruction -drivesys.cpu.op_class::SimdCmp 0 0.00% 63.95% # Class of executed instruction -drivesys.cpu.op_class::SimdCvt 0 0.00% 63.95% # Class of executed instruction -drivesys.cpu.op_class::SimdMisc 0 0.00% 63.95% # Class of executed instruction -drivesys.cpu.op_class::SimdMult 0 0.00% 63.95% # Class of executed instruction -drivesys.cpu.op_class::SimdMultAcc 0 0.00% 63.95% # Class of executed instruction -drivesys.cpu.op_class::SimdShift 0 0.00% 63.95% # Class of executed instruction -drivesys.cpu.op_class::SimdShiftAcc 0 0.00% 63.95% # Class of executed instruction -drivesys.cpu.op_class::SimdSqrt 0 0.00% 63.95% # Class of executed instruction -drivesys.cpu.op_class::SimdFloatAdd 0 0.00% 63.95% # Class of executed instruction -drivesys.cpu.op_class::SimdFloatAlu 0 0.00% 63.95% # Class of executed instruction -drivesys.cpu.op_class::SimdFloatCmp 0 0.00% 63.95% # Class of executed instruction -drivesys.cpu.op_class::SimdFloatCvt 0 0.00% 63.95% # Class of executed instruction -drivesys.cpu.op_class::SimdFloatDiv 0 0.00% 63.95% # Class of executed instruction -drivesys.cpu.op_class::SimdFloatMisc 0 0.00% 63.95% # Class of executed instruction -drivesys.cpu.op_class::SimdFloatMult 0 0.00% 63.95% # Class of executed instruction -drivesys.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.95% # Class of executed instruction -drivesys.cpu.op_class::SimdFloatSqrt 0 0.00% 63.95% # Class of executed instruction -drivesys.cpu.op_class::MemRead 4025389 21.13% 85.08% # Class of executed instruction -drivesys.cpu.op_class::MemWrite 2084412 10.94% 96.02% # Class of executed instruction -drivesys.cpu.op_class::FloatMemRead 639 0.00% 96.02% # Class of executed instruction -drivesys.cpu.op_class::FloatMemWrite 609 0.00% 96.02% # Class of executed instruction -drivesys.cpu.op_class::IprAccess 757336 3.98% 100.00% # Class of executed instruction -drivesys.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -drivesys.cpu.op_class::total 19051393 # Class of executed instruction -drivesys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -drivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -drivesys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). -drivesys.disk0.dma_write_full_pages 0 # Number of full page size DMA writes. -drivesys.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. -drivesys.disk0.dma_write_txs 0 # Number of DMA write transactions. -drivesys.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -drivesys.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -drivesys.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). -drivesys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes. -drivesys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes. -drivesys.disk2.dma_write_txs 0 # Number of DMA write transactions. -drivesys.iobridge.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -drivesys.iobus.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -drivesys.iobus.trans_dist::ReadReq 2484469 # Transaction distribution -drivesys.iobus.trans_dist::ReadResp 2484469 # Transaction distribution -drivesys.iobus.trans_dist::WriteReq 39723 # Transaction distribution -drivesys.iobus.trans_dist::WriteResp 39723 # Transaction distribution -drivesys.iobus.pkt_count_drivesys.bridge.master::drivesys.tsunami.cchip.pio 197670 # Packet count per connected master and slave (bytes) -drivesys.iobus.pkt_count_drivesys.bridge.master::drivesys.tsunami.ethernet.pio 78962 # Packet count per connected master and slave (bytes) -drivesys.iobus.pkt_count_drivesys.bridge.master::total 276632 # Packet count per connected master and slave (bytes) -drivesys.iobus.pkt_count_drivesys.tsunami.ethernet.dma::drivesys.iobridge.slave 4771752 # Packet count per connected master and slave (bytes) -drivesys.iobus.pkt_count_drivesys.tsunami.ethernet.dma::total 4771752 # Packet count per connected master and slave (bytes) -drivesys.iobus.pkt_count::total 5048384 # Packet count per connected master and slave (bytes) -drivesys.iobus.pkt_size_drivesys.bridge.master::drivesys.tsunami.cchip.pio 790680 # Cumulative packet size per connected master and slave (bytes) -drivesys.iobus.pkt_size_drivesys.bridge.master::drivesys.tsunami.ethernet.pio 157924 # Cumulative packet size per connected master and slave (bytes) -drivesys.iobus.pkt_size_drivesys.bridge.master::total 948604 # Cumulative packet size per connected master and slave (bytes) -drivesys.iobus.pkt_size_drivesys.tsunami.ethernet.dma::drivesys.iobridge.slave 57261614 # Cumulative packet size per connected master and slave (bytes) -drivesys.iobus.pkt_size_drivesys.tsunami.ethernet.dma::total 57261614 # Cumulative packet size per connected master and slave (bytes) -drivesys.iobus.pkt_size::total 58210218 # Cumulative packet size per connected master and slave (bytes) -drivesys.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -drivesys.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -drivesys.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -drivesys.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -drivesys.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -drivesys.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -drivesys.membus.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -drivesys.membus.trans_dist::ReadReq 25081955 # Transaction distribution -drivesys.membus.trans_dist::ReadResp 25182911 # Transaction distribution -drivesys.membus.trans_dist::WriteReq 1963575 # Transaction distribution -drivesys.membus.trans_dist::WriteResp 1963575 # Transaction distribution -drivesys.membus.trans_dist::LoadLockedReq 100956 # Transaction distribution -drivesys.membus.trans_dist::StoreCondReq 100924 # Transaction distribution -drivesys.membus.trans_dist::StoreCondResp 100924 # Transaction distribution -drivesys.membus.pkt_count_drivesys.cpu.icache_port::drivesys.physmem.port 38102786 # Packet count per connected master and slave (bytes) -drivesys.membus.pkt_count_drivesys.cpu.icache_port::total 38102786 # Packet count per connected master and slave (bytes) -drivesys.membus.pkt_count_drivesys.cpu.dcache_port::drivesys.bridge.slave 276632 # Packet count per connected master and slave (bytes) -drivesys.membus.pkt_count_drivesys.cpu.dcache_port::drivesys.physmem.port 11343650 # Packet count per connected master and slave (bytes) -drivesys.membus.pkt_count_drivesys.cpu.dcache_port::total 11620282 # Packet count per connected master and slave (bytes) -drivesys.membus.pkt_count_drivesys.iobridge.master::drivesys.physmem.port 4771752 # Packet count per connected master and slave (bytes) -drivesys.membus.pkt_count_drivesys.iobridge.master::total 4771752 # Packet count per connected master and slave (bytes) -drivesys.membus.pkt_count::total 54494820 # Packet count per connected master and slave (bytes) -drivesys.membus.pkt_size_drivesys.cpu.icache_port::drivesys.physmem.port 76205572 # Cumulative packet size per connected master and slave (bytes) -drivesys.membus.pkt_size_drivesys.cpu.icache_port::total 76205572 # Cumulative packet size per connected master and slave (bytes) -drivesys.membus.pkt_size_drivesys.cpu.dcache_port::drivesys.bridge.slave 948604 # Cumulative packet size per connected master and slave (bytes) -drivesys.membus.pkt_size_drivesys.cpu.dcache_port::drivesys.physmem.port 40903924 # Cumulative packet size per connected master and slave (bytes) -drivesys.membus.pkt_size_drivesys.cpu.dcache_port::total 41852528 # Cumulative packet size per connected master and slave (bytes) -drivesys.membus.pkt_size_drivesys.iobridge.master::drivesys.physmem.port 57261614 # Cumulative packet size per connected master and slave (bytes) -drivesys.membus.pkt_size_drivesys.iobridge.master::total 57261614 # Cumulative packet size per connected master and slave (bytes) -drivesys.membus.pkt_size::total 175319714 # Cumulative packet size per connected master and slave (bytes) -drivesys.membus.snoops 0 # Total snoops (count) -drivesys.membus.snoopTraffic 0 # Total snoop traffic (bytes) -drivesys.membus.snoop_fanout::samples 27247410 # Request fanout histogram -drivesys.membus.snoop_fanout::mean 0 # Request fanout histogram -drivesys.membus.snoop_fanout::stdev 0 # Request fanout histogram -drivesys.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -drivesys.membus.snoop_fanout::0 27247410 100.00% 100.00% # Request fanout histogram -drivesys.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -drivesys.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -drivesys.membus.snoop_fanout::min_value 0 # Request fanout histogram -drivesys.membus.snoop_fanout::max_value 0 # Request fanout histogram -drivesys.membus.snoop_fanout::total 27247410 # Request fanout histogram -drivesys.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -drivesys.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -drivesys.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -drivesys.tsunami.ethernet.clk_domain.clock 2000 # Clock period in ticks -drivesys.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -drivesys.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -drivesys.tsunami.ethernet.txBytes 798 # Bytes Transmitted -drivesys.tsunami.ethernet.rxBytes 960 # Bytes Received -drivesys.tsunami.ethernet.txPackets 5 # Number of Packets Transmitted -drivesys.tsunami.ethernet.rxPackets 8 # Number of Packets Received -drivesys.tsunami.ethernet.txIpChecksums 2 # Number of tx IP Checksums done by device -drivesys.tsunami.ethernet.rxIpChecksums 8 # Number of rx IP Checksums done by device -drivesys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device -drivesys.tsunami.ethernet.rxTcpChecksums 8 # Number of rx TCP Checksums done by device -drivesys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device -drivesys.tsunami.ethernet.rxUdpChecksums 0 # Number of rx UDP Checksums done by device -drivesys.tsunami.ethernet.descDMAReads 2385810 # Number of descriptors the device read w/ DMA -drivesys.tsunami.ethernet.descDMAWrites 13 # Number of descriptors the device wrote w/ DMA -drivesys.tsunami.ethernet.descDmaReadBytes 57259440 # number of descriptor bytes read w/ DMA -drivesys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA -drivesys.tsunami.ethernet.totBandwidth 70176 # Total Bandwidth (bits/s) -drivesys.tsunami.ethernet.totPackets 13 # Total Packets -drivesys.tsunami.ethernet.totBytes 1758 # Total Bytes -drivesys.tsunami.ethernet.totPPS 65 # Total Tranmission Rate (packets/s) -drivesys.tsunami.ethernet.txBandwidth 31855 # Transmit Bandwidth (bits/s) -drivesys.tsunami.ethernet.rxBandwidth 38322 # Receive Bandwidth (bits/s) -drivesys.tsunami.ethernet.txPPS 25 # Packet Tranmission Rate (packets/s) -drivesys.tsunami.ethernet.rxPPS 40 # Packet Reception Rate (packets/s) -drivesys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU -drivesys.tsunami.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post -drivesys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR -drivesys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -drivesys.tsunami.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post -drivesys.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -drivesys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -drivesys.tsunami.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post -drivesys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR -drivesys.tsunami.ethernet.postedRxDesc 8 # number of RxDesc interrupts posted to CPU -drivesys.tsunami.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post -drivesys.tsunami.ethernet.totalRxDesc 8 # total number of RxDesc written to ISR -drivesys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -drivesys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post -drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -drivesys.tsunami.ethernet.postedTxIdle 19726 # number of TxIdle interrupts posted to CPU -drivesys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post -drivesys.tsunami.ethernet.totalTxIdle 2385810 # total number of TxIdle written to ISR -drivesys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -drivesys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post -drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -drivesys.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -drivesys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post -drivesys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -drivesys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post -drivesys.tsunami.ethernet.postedInterrupts 2385831 # number of posts to CPU -drivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped -drivesys.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -drivesys.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -drivesys.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -drivesys.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -drivesys.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -drivesys.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -drivesys.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -drivesys.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -drivesys.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -drivesys.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -drivesys.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -drivesys.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -drivesys.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -drivesys.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -drivesys.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -drivesys.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -drivesys.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -drivesys.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -drivesys.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -drivesys.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -drivesys.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -drivesys.tsunami.io.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -drivesys.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -testsys.voltage_domain.voltage 1 # Voltage in Volts -testsys.clk_domain.clock 1000 # Clock period in ticks -testsys.physmem.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -testsys.physmem.bytes_read::cpu.inst 81044080 # Number of bytes read from this memory -testsys.physmem.bytes_read::cpu.data 27825116 # Number of bytes read from this memory -testsys.physmem.bytes_read::tsunami.ethernet 57260496 # Number of bytes read from this memory -testsys.physmem.bytes_read::total 166129692 # Number of bytes read from this memory -testsys.physmem.bytes_inst_read::cpu.inst 81044080 # Number of instructions bytes read from this memory -testsys.physmem.bytes_inst_read::total 81044080 # Number of instructions bytes read from this memory -testsys.physmem.bytes_written::cpu.data 16605404 # Number of bytes written to this memory -testsys.physmem.bytes_written::tsunami.ethernet 902 # Number of bytes written to this memory -testsys.physmem.bytes_written::total 16606306 # Number of bytes written to this memory -testsys.physmem.num_reads::cpu.inst 20261020 # Number of read requests responded to by this memory -testsys.physmem.num_reads::cpu.data 3842409 # Number of read requests responded to by this memory -testsys.physmem.num_reads::tsunami.ethernet 2385836 # Number of read requests responded to by this memory -testsys.physmem.num_reads::total 26489265 # Number of read requests responded to by this memory -testsys.physmem.num_writes::cpu.data 2258228 # Number of write requests responded to by this memory -testsys.physmem.num_writes::tsunami.ethernet 31 # Number of write requests responded to by this memory -testsys.physmem.num_writes::total 2258259 # Number of write requests responded to by this memory -testsys.physmem.bw_read::cpu.inst 404392869 # Total read bandwidth from this memory (bytes/s) -testsys.physmem.bw_read::cpu.data 138841461 # Total read bandwidth from this memory (bytes/s) -testsys.physmem.bw_read::tsunami.ethernet 285717800 # Total read bandwidth from this memory (bytes/s) -testsys.physmem.bw_read::total 828952130 # Total read bandwidth from this memory (bytes/s) -testsys.physmem.bw_inst_read::cpu.inst 404392869 # Instruction read bandwidth from this memory (bytes/s) -testsys.physmem.bw_inst_read::total 404392869 # Instruction read bandwidth from this memory (bytes/s) -testsys.physmem.bw_write::cpu.data 82857464 # Write bandwidth from this memory (bytes/s) -testsys.physmem.bw_write::tsunami.ethernet 4501 # Write bandwidth from this memory (bytes/s) -testsys.physmem.bw_write::total 82861965 # Write bandwidth from this memory (bytes/s) -testsys.physmem.bw_total::cpu.inst 404392869 # Total bandwidth to/from this memory (bytes/s) -testsys.physmem.bw_total::cpu.data 221698925 # Total bandwidth to/from this memory (bytes/s) -testsys.physmem.bw_total::tsunami.ethernet 285722301 # Total bandwidth to/from this memory (bytes/s) -testsys.physmem.bw_total::total 911814095 # Total bandwidth to/from this memory (bytes/s) -testsys.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -testsys.bridge.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -testsys.cpu.clk_domain.clock 500 # Clock period in ticks -testsys.cpu.dtb.fetch_hits 0 # ITB hits -testsys.cpu.dtb.fetch_misses 0 # ITB misses -testsys.cpu.dtb.fetch_acv 0 # ITB acv -testsys.cpu.dtb.fetch_accesses 0 # ITB accesses -testsys.cpu.dtb.read_hits 3916768 # DTB read hits -testsys.cpu.dtb.read_misses 3287 # DTB read misses -testsys.cpu.dtb.read_acv 80 # DTB read access violations -testsys.cpu.dtb.read_accesses 225414 # DTB read accesses -testsys.cpu.dtb.write_hits 2316721 # DTB write hits -testsys.cpu.dtb.write_misses 528 # DTB write misses -testsys.cpu.dtb.write_acv 81 # DTB write access violations -testsys.cpu.dtb.write_accesses 109988 # DTB write accesses -testsys.cpu.dtb.data_hits 6233489 # DTB hits -testsys.cpu.dtb.data_misses 3815 # DTB misses -testsys.cpu.dtb.data_acv 161 # DTB access violations -testsys.cpu.dtb.data_accesses 335402 # DTB accesses -testsys.cpu.itb.fetch_hits 4052237 # ITB hits -testsys.cpu.itb.fetch_misses 1497 # ITB misses -testsys.cpu.itb.fetch_acv 69 # ITB acv -testsys.cpu.itb.fetch_accesses 4053734 # ITB accesses -testsys.cpu.itb.read_hits 0 # DTB read hits -testsys.cpu.itb.read_misses 0 # DTB read misses -testsys.cpu.itb.read_acv 0 # DTB read access violations -testsys.cpu.itb.read_accesses 0 # DTB read accesses -testsys.cpu.itb.write_hits 0 # DTB write hits -testsys.cpu.itb.write_misses 0 # DTB write misses -testsys.cpu.itb.write_acv 0 # DTB write access violations -testsys.cpu.itb.write_accesses 0 # DTB write accesses -testsys.cpu.itb.data_hits 0 # DTB hits -testsys.cpu.itb.data_misses 0 # DTB misses -testsys.cpu.itb.data_acv 0 # DTB access violations -testsys.cpu.itb.data_accesses 0 # DTB accesses -testsys.cpu.numPwrStateTransitions 39159 # Number of power state transitions -testsys.cpu.pwrStateClkGateDist::samples 19580 # Distribution of time spent in the clock gated state -testsys.cpu.pwrStateClkGateDist::mean 9718476.378958 # Distribution of time spent in the clock gated state -testsys.cpu.pwrStateClkGateDist::stdev 783559.874332 # Distribution of time spent in the clock gated state -testsys.cpu.pwrStateClkGateDist::1000-5e+10 19580 100.00% 100.00% # Distribution of time spent in the clock gated state -testsys.cpu.pwrStateClkGateDist::min_value 105000 # Distribution of time spent in the clock gated state -testsys.cpu.pwrStateClkGateDist::max_value 9815000 # Distribution of time spent in the clock gated state -testsys.cpu.pwrStateClkGateDist::total 19580 # Distribution of time spent in the clock gated state -testsys.cpu.pwrStateResidencyTicks::ON 11102310500 # Cumulative time (in ticks) in various power states -testsys.cpu.pwrStateResidencyTicks::CLK_GATED 190287767500 # Cumulative time (in ticks) in various power states -testsys.cpu.numCycles 400825859 # number of cpu cycles simulated -testsys.cpu.numWorkItemsStarted 0 # number of work items this cpu started -testsys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -testsys.cpu.kern.inst.arm 0 # number of arm instructions executed -testsys.cpu.kern.inst.quiesce 19580 # number of quiesce instructions executed -testsys.cpu.kern.inst.hwrei 153669 # number of hwrei instructions executed -testsys.cpu.kern.ipl_count::0 62779 42.67% 42.67% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count::21 19625 13.34% 56.01% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count::22 205 0.14% 56.15% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count::31 64511 43.85% 100.00% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count::total 147120 # number of times we switched to this ipl -testsys.cpu.kern.ipl_good::0 62773 43.18% 43.18% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_good::21 19625 13.50% 56.67% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_good::22 205 0.14% 56.82% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_good::31 62785 43.18% 100.00% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_good::total 145388 # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_ticks::0 194347611000 96.98% 96.98% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks::21 1588986000 0.79% 97.77% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks::22 8815000 0.00% 97.78% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks::31 4457946500 2.22% 100.00% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks::total 200403358500 # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_used::0 0.999904 # fraction of swpipl calls that actually changed the ipl -testsys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl -testsys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -testsys.cpu.kern.ipl_used::31 0.973245 # fraction of swpipl calls that actually changed the ipl -testsys.cpu.kern.ipl_used::total 0.988227 # fraction of swpipl calls that actually changed the ipl -testsys.cpu.kern.syscall::2 3 3.61% 3.61% # number of syscalls executed -testsys.cpu.kern.syscall::3 7 8.43% 12.05% # number of syscalls executed -testsys.cpu.kern.syscall::4 1 1.20% 13.25% # number of syscalls executed -testsys.cpu.kern.syscall::6 7 8.43% 21.69% # number of syscalls executed -testsys.cpu.kern.syscall::17 7 8.43% 30.12% # number of syscalls executed -testsys.cpu.kern.syscall::19 2 2.41% 32.53% # number of syscalls executed -testsys.cpu.kern.syscall::20 1 1.20% 33.73% # number of syscalls executed -testsys.cpu.kern.syscall::33 3 3.61% 37.35% # number of syscalls executed -testsys.cpu.kern.syscall::45 10 12.05% 49.40% # number of syscalls executed -testsys.cpu.kern.syscall::48 5 6.02% 55.42% # number of syscalls executed -testsys.cpu.kern.syscall::54 1 1.20% 56.63% # number of syscalls executed -testsys.cpu.kern.syscall::59 3 3.61% 60.24% # number of syscalls executed -testsys.cpu.kern.syscall::71 15 18.07% 78.31% # number of syscalls executed -testsys.cpu.kern.syscall::74 4 4.82% 83.13% # number of syscalls executed -testsys.cpu.kern.syscall::97 2 2.41% 85.54% # number of syscalls executed -testsys.cpu.kern.syscall::98 2 2.41% 87.95% # number of syscalls executed -testsys.cpu.kern.syscall::101 2 2.41% 90.36% # number of syscalls executed -testsys.cpu.kern.syscall::102 2 2.41% 92.77% # number of syscalls executed -testsys.cpu.kern.syscall::104 1 1.20% 93.98% # number of syscalls executed -testsys.cpu.kern.syscall::105 3 3.61% 97.59% # number of syscalls executed -testsys.cpu.kern.syscall::118 2 2.41% 100.00% # number of syscalls executed -testsys.cpu.kern.syscall::total 83 # number of syscalls executed -testsys.cpu.kern.callpal::swpctx 438 0.34% 0.34% # number of callpals executed -testsys.cpu.kern.callpal::tbi 20 0.02% 0.36% # number of callpals executed -testsys.cpu.kern.callpal::swpipl 106832 83.26% 83.62% # number of callpals executed -testsys.cpu.kern.callpal::rdps 359 0.28% 83.90% # number of callpals executed -testsys.cpu.kern.callpal::wrusp 3 0.00% 83.90% # number of callpals executed -testsys.cpu.kern.callpal::rdusp 3 0.00% 83.90% # number of callpals executed -testsys.cpu.kern.callpal::rti 20470 15.95% 99.86% # number of callpals executed -testsys.cpu.kern.callpal::callsys 140 0.11% 99.97% # number of callpals executed -testsys.cpu.kern.callpal::imb 44 0.03% 100.00% # number of callpals executed -testsys.cpu.kern.callpal::total 128309 # number of callpals executed -testsys.cpu.kern.mode_switch::kernel 1280 # number of protection mode switches -testsys.cpu.kern.mode_switch::user 706 # number of protection mode switches -testsys.cpu.kern.mode_switch::idle 19629 # number of protection mode switches -testsys.cpu.kern.mode_good::kernel 711 -testsys.cpu.kern.mode_good::user 706 -testsys.cpu.kern.mode_good::idle 5 -testsys.cpu.kern.mode_switch_good::kernel 0.555469 # fraction of useful protection mode switches -testsys.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -testsys.cpu.kern.mode_switch_good::idle 0.000255 # fraction of useful protection mode switches -testsys.cpu.kern.mode_switch_good::total 0.065788 # fraction of useful protection mode switches -testsys.cpu.kern.mode_ticks::kernel 994253000 59.96% 59.96% # number of ticks spent at the given mode -testsys.cpu.kern.mode_ticks::user 533088000 32.15% 92.11% # number of ticks spent at the given mode -testsys.cpu.kern.mode_ticks::idle 130749000 7.89% 100.00% # number of ticks spent at the given mode -testsys.cpu.kern.swap_context 438 # number of times the context was actually changed -testsys.cpu.committedInsts 20257044 # Number of instructions committed -testsys.cpu.committedOps 20257044 # Number of ops (including micro ops) committed -testsys.cpu.num_int_alu_accesses 18836392 # Number of integer alu accesses -testsys.cpu.num_fp_alu_accesses 17380 # Number of float alu accesses -testsys.cpu.num_func_calls 1221158 # number of times a function call or return occured -testsys.cpu.num_conditional_control_insts 1442105 # number of instructions that are conditional controls -testsys.cpu.num_int_insts 18836392 # number of integer instructions -testsys.cpu.num_fp_insts 17380 # number of float instructions -testsys.cpu.num_int_register_reads 24786330 # number of times the integer registers were read -testsys.cpu.num_int_register_writes 14693469 # number of times the integer registers were written -testsys.cpu.num_fp_register_reads 11166 # number of times the floating registers were read -testsys.cpu.num_fp_register_writes 10823 # number of times the floating registers were written -testsys.cpu.num_mem_refs 6262732 # number of memory refs -testsys.cpu.num_load_insts 3943883 # Number of load instructions -testsys.cpu.num_store_insts 2318849 # Number of store instructions -testsys.cpu.num_idle_cycles 380582482.461103 # Number of idle cycles -testsys.cpu.num_busy_cycles 20243376.538897 # Number of busy cycles -testsys.cpu.not_idle_fraction 0.050504 # Percentage of non-idle cycles -testsys.cpu.idle_fraction 0.949496 # Percentage of idle cycles -testsys.cpu.Branches 2929782 # Number of branches fetched -testsys.cpu.op_class::No_OpClass 712785 3.52% 3.52% # Class of executed instruction -testsys.cpu.op_class::IntAlu 12147004 59.95% 63.47% # Class of executed instruction -testsys.cpu.op_class::IntMult 21654 0.11% 63.58% # Class of executed instruction -testsys.cpu.op_class::IntDiv 0 0.00% 63.58% # Class of executed instruction -testsys.cpu.op_class::FloatAdd 4655 0.02% 63.60% # Class of executed instruction -testsys.cpu.op_class::FloatCmp 1 0.00% 63.60% # Class of executed instruction -testsys.cpu.op_class::FloatCvt 0 0.00% 63.60% # Class of executed instruction -testsys.cpu.op_class::FloatMult 0 0.00% 63.60% # Class of executed instruction -testsys.cpu.op_class::FloatMultAcc 0 0.00% 63.60% # Class of executed instruction -testsys.cpu.op_class::FloatDiv 922 0.00% 63.60% # Class of executed instruction -testsys.cpu.op_class::FloatMisc 0 0.00% 63.60% # Class of executed instruction -testsys.cpu.op_class::FloatSqrt 0 0.00% 63.60% # Class of executed instruction -testsys.cpu.op_class::SimdAdd 0 0.00% 63.60% # Class of executed instruction -testsys.cpu.op_class::SimdAddAcc 0 0.00% 63.60% # Class of executed instruction -testsys.cpu.op_class::SimdAlu 0 0.00% 63.60% # Class of executed instruction -testsys.cpu.op_class::SimdCmp 0 0.00% 63.60% # Class of executed instruction -testsys.cpu.op_class::SimdCvt 0 0.00% 63.60% # Class of executed instruction -testsys.cpu.op_class::SimdMisc 0 0.00% 63.60% # Class of executed instruction -testsys.cpu.op_class::SimdMult 0 0.00% 63.60% # Class of executed instruction -testsys.cpu.op_class::SimdMultAcc 0 0.00% 63.60% # Class of executed instruction -testsys.cpu.op_class::SimdShift 0 0.00% 63.60% # Class of executed instruction -testsys.cpu.op_class::SimdShiftAcc 0 0.00% 63.60% # Class of executed instruction -testsys.cpu.op_class::SimdSqrt 0 0.00% 63.60% # Class of executed instruction -testsys.cpu.op_class::SimdFloatAdd 0 0.00% 63.60% # Class of executed instruction -testsys.cpu.op_class::SimdFloatAlu 0 0.00% 63.60% # Class of executed instruction -testsys.cpu.op_class::SimdFloatCmp 0 0.00% 63.60% # Class of executed instruction -testsys.cpu.op_class::SimdFloatCvt 0 0.00% 63.60% # Class of executed instruction -testsys.cpu.op_class::SimdFloatDiv 0 0.00% 63.60% # Class of executed instruction -testsys.cpu.op_class::SimdFloatMisc 0 0.00% 63.60% # Class of executed instruction -testsys.cpu.op_class::SimdFloatMult 0 0.00% 63.60% # Class of executed instruction -testsys.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.60% # Class of executed instruction -testsys.cpu.op_class::SimdFloatSqrt 0 0.00% 63.60% # Class of executed instruction -testsys.cpu.op_class::MemRead 4224290 20.85% 84.45% # Class of executed instruction -testsys.cpu.op_class::MemWrite 2313781 11.42% 95.87% # Class of executed instruction -testsys.cpu.op_class::FloatMemRead 6195 0.03% 95.90% # Class of executed instruction -testsys.cpu.op_class::FloatMemWrite 5607 0.03% 95.93% # Class of executed instruction -testsys.cpu.op_class::IprAccess 824126 4.07% 100.00% # Class of executed instruction -testsys.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -testsys.cpu.op_class::total 20261020 # Class of executed instruction -testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -testsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). -testsys.disk0.dma_write_full_pages 0 # Number of full page size DMA writes. -testsys.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. -testsys.disk0.dma_write_txs 0 # Number of DMA write transactions. -testsys.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -testsys.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -testsys.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). -testsys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes. -testsys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes. -testsys.disk2.dma_write_txs 0 # Number of DMA write transactions. -testsys.iobridge.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -testsys.iobus.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -testsys.iobus.trans_dist::ReadReq 2483943 # Transaction distribution -testsys.iobus.trans_dist::ReadResp 2483943 # Transaction distribution -testsys.iobus.trans_dist::WriteReq 39573 # Transaction distribution -testsys.iobus.trans_dist::WriteResp 39573 # Transaction distribution -testsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.cchip.pio 196204 # Packet count per connected master and slave (bytes) -testsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.io.pio 336 # Packet count per connected master and slave (bytes) -testsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.uart.pio 428 # Packet count per connected master and slave (bytes) -testsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.ethernet.pio 78330 # Packet count per connected master and slave (bytes) -testsys.iobus.pkt_count_testsys.bridge.master::total 275298 # Packet count per connected master and slave (bytes) -testsys.iobus.pkt_count_testsys.tsunami.ethernet.dma::testsys.iobridge.slave 4771734 # Packet count per connected master and slave (bytes) -testsys.iobus.pkt_count_testsys.tsunami.ethernet.dma::total 4771734 # Packet count per connected master and slave (bytes) -testsys.iobus.pkt_count::total 5047032 # Packet count per connected master and slave (bytes) -testsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.cchip.pio 784816 # Cumulative packet size per connected master and slave (bytes) -testsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.io.pio 462 # Cumulative packet size per connected master and slave (bytes) -testsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.uart.pio 214 # Cumulative packet size per connected master and slave (bytes) -testsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.ethernet.pio 156660 # Cumulative packet size per connected master and slave (bytes) -testsys.iobus.pkt_size_testsys.bridge.master::total 942152 # Cumulative packet size per connected master and slave (bytes) -testsys.iobus.pkt_size_testsys.tsunami.ethernet.dma::testsys.iobridge.slave 57261398 # Cumulative packet size per connected master and slave (bytes) -testsys.iobus.pkt_size_testsys.tsunami.ethernet.dma::total 57261398 # Cumulative packet size per connected master and slave (bytes) -testsys.iobus.pkt_size::total 58203550 # Cumulative packet size per connected master and slave (bytes) -testsys.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -testsys.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -testsys.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -testsys.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -testsys.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -testsys.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -testsys.membus.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -testsys.membus.trans_dist::ReadReq 26478762 # Transaction distribution -testsys.membus.trans_dist::ReadResp 26587372 # Transaction distribution -testsys.membus.trans_dist::WriteReq 2189273 # Transaction distribution -testsys.membus.trans_dist::WriteResp 2189273 # Transaction distribution -testsys.membus.trans_dist::LoadLockedReq 108610 # Transaction distribution -testsys.membus.trans_dist::StoreCondReq 108528 # Transaction distribution -testsys.membus.trans_dist::StoreCondResp 108528 # Transaction distribution -testsys.membus.pkt_count_testsys.cpu.icache_port::testsys.physmem.port 40522040 # Packet count per connected master and slave (bytes) -testsys.membus.pkt_count_testsys.cpu.icache_port::total 40522040 # Packet count per connected master and slave (bytes) -testsys.membus.pkt_count_testsys.cpu.dcache_port::testsys.bridge.slave 275298 # Packet count per connected master and slave (bytes) -testsys.membus.pkt_count_testsys.cpu.dcache_port::testsys.physmem.port 12201274 # Packet count per connected master and slave (bytes) -testsys.membus.pkt_count_testsys.cpu.dcache_port::total 12476572 # Packet count per connected master and slave (bytes) -testsys.membus.pkt_count_testsys.iobridge.master::testsys.physmem.port 4771734 # Packet count per connected master and slave (bytes) -testsys.membus.pkt_count_testsys.iobridge.master::total 4771734 # Packet count per connected master and slave (bytes) -testsys.membus.pkt_count::total 57770346 # Packet count per connected master and slave (bytes) -testsys.membus.pkt_size_testsys.cpu.icache_port::testsys.physmem.port 81044080 # Cumulative packet size per connected master and slave (bytes) -testsys.membus.pkt_size_testsys.cpu.icache_port::total 81044080 # Cumulative packet size per connected master and slave (bytes) -testsys.membus.pkt_size_testsys.cpu.dcache_port::testsys.bridge.slave 942152 # Cumulative packet size per connected master and slave (bytes) -testsys.membus.pkt_size_testsys.cpu.dcache_port::testsys.physmem.port 44430520 # Cumulative packet size per connected master and slave (bytes) -testsys.membus.pkt_size_testsys.cpu.dcache_port::total 45372672 # Cumulative packet size per connected master and slave (bytes) -testsys.membus.pkt_size_testsys.iobridge.master::testsys.physmem.port 57261398 # Cumulative packet size per connected master and slave (bytes) -testsys.membus.pkt_size_testsys.iobridge.master::total 57261398 # Cumulative packet size per connected master and slave (bytes) -testsys.membus.pkt_size::total 183678150 # Cumulative packet size per connected master and slave (bytes) -testsys.membus.snoops 0 # Total snoops (count) -testsys.membus.snoopTraffic 0 # Total snoop traffic (bytes) -testsys.membus.snoop_fanout::samples 28885173 # Request fanout histogram -testsys.membus.snoop_fanout::mean 0 # Request fanout histogram -testsys.membus.snoop_fanout::stdev 0 # Request fanout histogram -testsys.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -testsys.membus.snoop_fanout::0 28885173 100.00% 100.00% # Request fanout histogram -testsys.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -testsys.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -testsys.membus.snoop_fanout::min_value 0 # Request fanout histogram -testsys.membus.snoop_fanout::max_value 0 # Request fanout histogram -testsys.membus.snoop_fanout::total 28885173 # Request fanout histogram -testsys.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -testsys.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -testsys.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -testsys.tsunami.ethernet.clk_domain.clock 2000 # Clock period in ticks -testsys.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -testsys.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -testsys.tsunami.ethernet.txBytes 960 # Bytes Transmitted -testsys.tsunami.ethernet.rxBytes 798 # Bytes Received -testsys.tsunami.ethernet.txPackets 8 # Number of Packets Transmitted -testsys.tsunami.ethernet.rxPackets 5 # Number of Packets Received -testsys.tsunami.ethernet.txIpChecksums 2 # Number of tx IP Checksums done by device -testsys.tsunami.ethernet.rxIpChecksums 5 # Number of rx IP Checksums done by device -testsys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device -testsys.tsunami.ethernet.rxTcpChecksums 5 # Number of rx TCP Checksums done by device -testsys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device -testsys.tsunami.ethernet.rxUdpChecksums 0 # Number of rx UDP Checksums done by device -testsys.tsunami.ethernet.descDMAReads 2385801 # Number of descriptors the device read w/ DMA -testsys.tsunami.ethernet.descDMAWrites 13 # Number of descriptors the device wrote w/ DMA -testsys.tsunami.ethernet.descDmaReadBytes 57259224 # number of descriptor bytes read w/ DMA -testsys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA -testsys.tsunami.ethernet.totBandwidth 70176 # Total Bandwidth (bits/s) -testsys.tsunami.ethernet.totPackets 13 # Total Packets -testsys.tsunami.ethernet.totBytes 1758 # Total Bytes -testsys.tsunami.ethernet.totPPS 65 # Total Tranmission Rate (packets/s) -testsys.tsunami.ethernet.txBandwidth 38322 # Transmit Bandwidth (bits/s) -testsys.tsunami.ethernet.rxBandwidth 31855 # Receive Bandwidth (bits/s) -testsys.tsunami.ethernet.txPPS 40 # Packet Tranmission Rate (packets/s) -testsys.tsunami.ethernet.rxPPS 25 # Packet Reception Rate (packets/s) -testsys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU -testsys.tsunami.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post -testsys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR -testsys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -testsys.tsunami.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post -testsys.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -testsys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -testsys.tsunami.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post -testsys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR -testsys.tsunami.ethernet.postedRxDesc 5 # number of RxDesc interrupts posted to CPU -testsys.tsunami.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post -testsys.tsunami.ethernet.totalRxDesc 5 # total number of RxDesc written to ISR -testsys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -testsys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post -testsys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -testsys.tsunami.ethernet.postedTxIdle 19571 # number of TxIdle interrupts posted to CPU -testsys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post -testsys.tsunami.ethernet.totalTxIdle 2385801 # total number of TxIdle written to ISR -testsys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -testsys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post -testsys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -testsys.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -testsys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post -testsys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -testsys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post -testsys.tsunami.ethernet.postedInterrupts 2385819 # number of posts to CPU -testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped -testsys.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -testsys.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -testsys.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -testsys.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -testsys.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -testsys.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -testsys.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -testsys.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -testsys.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -testsys.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -testsys.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -testsys.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -testsys.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -testsys.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -testsys.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -testsys.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -testsys.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -testsys.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -testsys.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -testsys.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -testsys.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -testsys.tsunami.io.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states -testsys.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 4321213476000 # Cumulative time (in ticks) in various power states - ----------- End Simulation Statistics ---------- - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000407 # Number of seconds simulated -sim_ticks 407341500 # Number of ticks simulated -final_tick 4321620817500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 9980587708 # Simulator instruction rate (inst/s) -host_op_rate 9978728931 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7757989630 # Simulator tick rate (ticks/s) -host_mem_usage 503180 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host -sim_insts 523853183 # Number of instructions simulated -sim_ops 523853183 # Number of ops (including micro ops) simulated -drivesys.voltage_domain.voltage 1 # Voltage in Volts -drivesys.clk_domain.clock 1000 # Clock period in ticks -drivesys.physmem.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -drivesys.physmem.bytes_read::cpu.inst 144608 # Number of bytes read from this memory -drivesys.physmem.bytes_read::cpu.data 49952 # Number of bytes read from this memory -drivesys.physmem.bytes_read::tsunami.ethernet 116400 # Number of bytes read from this memory -drivesys.physmem.bytes_read::total 310960 # Number of bytes read from this memory -drivesys.physmem.bytes_inst_read::cpu.inst 144608 # Number of instructions bytes read from this memory -drivesys.physmem.bytes_inst_read::total 144608 # Number of instructions bytes read from this memory -drivesys.physmem.bytes_written::cpu.data 27688 # Number of bytes written to this memory -drivesys.physmem.bytes_written::total 27688 # Number of bytes written to this memory -drivesys.physmem.num_reads::cpu.inst 36152 # Number of read requests responded to by this memory -drivesys.physmem.num_reads::cpu.data 6909 # Number of read requests responded to by this memory -drivesys.physmem.num_reads::tsunami.ethernet 4850 # Number of read requests responded to by this memory -drivesys.physmem.num_reads::total 47911 # Number of read requests responded to by this memory -drivesys.physmem.num_writes::cpu.data 3812 # Number of write requests responded to by this memory -drivesys.physmem.num_writes::total 3812 # Number of write requests responded to by this memory -drivesys.physmem.bw_read::cpu.inst 355004339 # Total read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_read::cpu.data 122629293 # Total read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_read::tsunami.ethernet 285755318 # Total read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_read::total 763388950 # Total read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_inst_read::cpu.inst 355004339 # Instruction read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_inst_read::total 355004339 # Instruction read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_write::cpu.data 67972451 # Write bandwidth from this memory (bytes/s) -drivesys.physmem.bw_write::total 67972451 # Write bandwidth from this memory (bytes/s) -drivesys.physmem.bw_total::cpu.inst 355004339 # Total bandwidth to/from this memory (bytes/s) -drivesys.physmem.bw_total::cpu.data 190601743 # Total bandwidth to/from this memory (bytes/s) -drivesys.physmem.bw_total::tsunami.ethernet 285755318 # Total bandwidth to/from this memory (bytes/s) -drivesys.physmem.bw_total::total 831361401 # Total bandwidth to/from this memory (bytes/s) -drivesys.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -drivesys.bridge.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -drivesys.cpu.clk_domain.clock 250 # Clock period in ticks -drivesys.cpu.dtb.fetch_hits 0 # ITB hits -drivesys.cpu.dtb.fetch_misses 0 # ITB misses -drivesys.cpu.dtb.fetch_acv 0 # ITB acv -drivesys.cpu.dtb.fetch_accesses 0 # ITB accesses -drivesys.cpu.dtb.read_hits 7069 # DTB read hits -drivesys.cpu.dtb.read_misses 0 # DTB read misses -drivesys.cpu.dtb.read_acv 0 # DTB read access violations -drivesys.cpu.dtb.read_accesses 0 # DTB read accesses -drivesys.cpu.dtb.write_hits 3933 # DTB write hits -drivesys.cpu.dtb.write_misses 0 # DTB write misses -drivesys.cpu.dtb.write_acv 0 # DTB write access violations -drivesys.cpu.dtb.write_accesses 0 # DTB write accesses -drivesys.cpu.dtb.data_hits 11002 # DTB hits -drivesys.cpu.dtb.data_misses 0 # DTB misses -drivesys.cpu.dtb.data_acv 0 # DTB access violations -drivesys.cpu.dtb.data_accesses 0 # DTB accesses -drivesys.cpu.itb.fetch_hits 5992 # ITB hits -drivesys.cpu.itb.fetch_misses 0 # ITB misses -drivesys.cpu.itb.fetch_acv 0 # ITB acv -drivesys.cpu.itb.fetch_accesses 5992 # ITB accesses -drivesys.cpu.itb.read_hits 0 # DTB read hits -drivesys.cpu.itb.read_misses 0 # DTB read misses -drivesys.cpu.itb.read_acv 0 # DTB read access violations -drivesys.cpu.itb.read_accesses 0 # DTB read accesses -drivesys.cpu.itb.write_hits 0 # DTB write hits -drivesys.cpu.itb.write_misses 0 # DTB write misses -drivesys.cpu.itb.write_acv 0 # DTB write access violations -drivesys.cpu.itb.write_accesses 0 # DTB write accesses -drivesys.cpu.itb.data_hits 0 # DTB hits -drivesys.cpu.itb.data_misses 0 # DTB misses -drivesys.cpu.itb.data_acv 0 # DTB access violations -drivesys.cpu.itb.data_accesses 0 # DTB accesses -drivesys.cpu.numPwrStateTransitions 82 # Number of power state transitions -drivesys.cpu.pwrStateClkGateDist::samples 42 # Distribution of time spent in the clock gated state -drivesys.cpu.pwrStateClkGateDist::mean 9483660.714286 # Distribution of time spent in the clock gated state -drivesys.cpu.pwrStateClkGateDist::stdev 1743513.957554 # Distribution of time spent in the clock gated state -drivesys.cpu.pwrStateClkGateDist::1000-5e+10 42 100.00% 100.00% # Distribution of time spent in the clock gated state -drivesys.cpu.pwrStateClkGateDist::min_value 920000 # Distribution of time spent in the clock gated state -drivesys.cpu.pwrStateClkGateDist::max_value 9947500 # Distribution of time spent in the clock gated state -drivesys.cpu.pwrStateClkGateDist::total 42 # Distribution of time spent in the clock gated state -drivesys.cpu.pwrStateResidencyTicks::ON 9027750 # Cumulative time (in ticks) in various power states -drivesys.cpu.pwrStateResidencyTicks::CLK_GATED 398313750 # Cumulative time (in ticks) in various power states -drivesys.cpu.numCycles 1626281 # number of cpu cycles simulated -drivesys.cpu.numWorkItemsStarted 0 # number of work items this cpu started -drivesys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -drivesys.cpu.kern.inst.arm 0 # number of arm instructions executed -drivesys.cpu.kern.inst.quiesce 41 # number of quiesce instructions executed -drivesys.cpu.kern.inst.hwrei 295 # number of hwrei instructions executed -drivesys.cpu.kern.ipl_count::0 123 41.84% 41.84% # number of times we switched to this ipl -drivesys.cpu.kern.ipl_count::21 40 13.61% 55.44% # number of times we switched to this ipl -drivesys.cpu.kern.ipl_count::22 1 0.34% 55.78% # number of times we switched to this ipl -drivesys.cpu.kern.ipl_count::31 130 44.22% 100.00% # number of times we switched to this ipl -drivesys.cpu.kern.ipl_count::total 294 # number of times we switched to this ipl -drivesys.cpu.kern.ipl_good::0 123 42.86% 42.86% # number of times we switched to this ipl from a different ipl -drivesys.cpu.kern.ipl_good::21 40 13.94% 56.79% # number of times we switched to this ipl from a different ipl -drivesys.cpu.kern.ipl_good::22 1 0.35% 57.14% # number of times we switched to this ipl from a different ipl -drivesys.cpu.kern.ipl_good::31 123 42.86% 100.00% # number of times we switched to this ipl from a different ipl -drivesys.cpu.kern.ipl_good::total 287 # number of times we switched to this ipl from a different ipl -drivesys.cpu.kern.ipl_ticks::0 400289000 98.46% 98.46% # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_ticks::21 1620000 0.40% 98.86% # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_ticks::22 21500 0.01% 98.86% # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_ticks::31 4629500 1.14% 100.00% # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_ticks::total 406560000 # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_used::0 1 # fraction of swpipl calls that actually changed the ipl -drivesys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl -drivesys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -drivesys.cpu.kern.ipl_used::31 0.946154 # fraction of swpipl calls that actually changed the ipl -drivesys.cpu.kern.ipl_used::total 0.976190 # fraction of swpipl calls that actually changed the ipl -drivesys.cpu.kern.callpal::swpipl 212 83.46% 83.46% # number of callpals executed -drivesys.cpu.kern.callpal::rdps 1 0.39% 83.86% # number of callpals executed -drivesys.cpu.kern.callpal::rti 41 16.14% 100.00% # number of callpals executed -drivesys.cpu.kern.callpal::total 254 # number of callpals executed -drivesys.cpu.kern.mode_switch::kernel 0 # number of protection mode switches -drivesys.cpu.kern.mode_switch::user 0 # number of protection mode switches -drivesys.cpu.kern.mode_switch::idle 41 # number of protection mode switches -drivesys.cpu.kern.mode_good::kernel 0 -drivesys.cpu.kern.mode_good::user 0 -drivesys.cpu.kern.mode_good::idle 0 -drivesys.cpu.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches -drivesys.cpu.kern.mode_switch_good::user nan # fraction of useful protection mode switches -drivesys.cpu.kern.mode_switch_good::idle 0 # fraction of useful protection mode switches -drivesys.cpu.kern.mode_switch_good::total 0 # fraction of useful protection mode switches -drivesys.cpu.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode -drivesys.cpu.kern.mode_ticks::user 0 # number of ticks spent at the given mode -drivesys.cpu.kern.mode_ticks::idle 0 # number of ticks spent at the given mode -drivesys.cpu.kern.swap_context 0 # number of times the context was actually changed -drivesys.cpu.committedInsts 36152 # Number of instructions committed -drivesys.cpu.committedOps 36152 # Number of ops (including micro ops) committed -drivesys.cpu.num_int_alu_accesses 33516 # Number of integer alu accesses -drivesys.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -drivesys.cpu.num_func_calls 2388 # number of times a function call or return occured -drivesys.cpu.num_conditional_control_insts 2347 # number of instructions that are conditional controls -drivesys.cpu.num_int_insts 33516 # number of integer instructions -drivesys.cpu.num_fp_insts 0 # number of float instructions -drivesys.cpu.num_int_register_reads 43772 # number of times the integer registers were read -drivesys.cpu.num_int_register_writes 26499 # number of times the integer registers were written -drivesys.cpu.num_fp_register_reads 0 # number of times the floating registers were read -drivesys.cpu.num_fp_register_writes 0 # number of times the floating registers were written -drivesys.cpu.num_mem_refs 11043 # number of memory refs -drivesys.cpu.num_load_insts 7109 # Number of load instructions -drivesys.cpu.num_store_insts 3934 # Number of store instructions -drivesys.cpu.num_idle_cycles 1590238.371734 # Number of idle cycles -drivesys.cpu.num_busy_cycles 36042.628266 # Number of busy cycles -drivesys.cpu.not_idle_fraction 0.022163 # Percentage of non-idle cycles -drivesys.cpu.idle_fraction 0.977837 # Percentage of idle cycles -drivesys.cpu.Branches 5243 # Number of branches fetched -drivesys.cpu.op_class::No_OpClass 1262 3.49% 3.49% # Class of executed instruction -drivesys.cpu.op_class::IntAlu 21687 59.99% 63.48% # Class of executed instruction -drivesys.cpu.op_class::IntMult 44 0.12% 63.60% # Class of executed instruction -drivesys.cpu.op_class::IntDiv 0 0.00% 63.60% # Class of executed instruction -drivesys.cpu.op_class::FloatAdd 0 0.00% 63.60% # Class of executed instruction -drivesys.cpu.op_class::FloatCmp 0 0.00% 63.60% # Class of executed instruction -drivesys.cpu.op_class::FloatCvt 0 0.00% 63.60% # Class of executed instruction -drivesys.cpu.op_class::FloatMult 0 0.00% 63.60% # Class of executed instruction -drivesys.cpu.op_class::FloatMultAcc 0 0.00% 63.60% # Class of executed instruction -drivesys.cpu.op_class::FloatDiv 0 0.00% 63.60% # Class of executed instruction -drivesys.cpu.op_class::FloatMisc 0 0.00% 63.60% # Class of executed instruction -drivesys.cpu.op_class::FloatSqrt 0 0.00% 63.60% # Class of executed instruction -drivesys.cpu.op_class::SimdAdd 0 0.00% 63.60% # Class of executed instruction -drivesys.cpu.op_class::SimdAddAcc 0 0.00% 63.60% # Class of executed instruction -drivesys.cpu.op_class::SimdAlu 0 0.00% 63.60% # Class of executed instruction -drivesys.cpu.op_class::SimdCmp 0 0.00% 63.60% # Class of executed instruction -drivesys.cpu.op_class::SimdCvt 0 0.00% 63.60% # Class of executed instruction -drivesys.cpu.op_class::SimdMisc 0 0.00% 63.60% # Class of executed instruction -drivesys.cpu.op_class::SimdMult 0 0.00% 63.60% # Class of executed instruction -drivesys.cpu.op_class::SimdMultAcc 0 0.00% 63.60% # Class of executed instruction -drivesys.cpu.op_class::SimdShift 0 0.00% 63.60% # Class of executed instruction -drivesys.cpu.op_class::SimdShiftAcc 0 0.00% 63.60% # Class of executed instruction -drivesys.cpu.op_class::SimdSqrt 0 0.00% 63.60% # Class of executed instruction -drivesys.cpu.op_class::SimdFloatAdd 0 0.00% 63.60% # Class of executed instruction -drivesys.cpu.op_class::SimdFloatAlu 0 0.00% 63.60% # Class of executed instruction -drivesys.cpu.op_class::SimdFloatCmp 0 0.00% 63.60% # Class of executed instruction -drivesys.cpu.op_class::SimdFloatCvt 0 0.00% 63.60% # Class of executed instruction -drivesys.cpu.op_class::SimdFloatDiv 0 0.00% 63.60% # Class of executed instruction -drivesys.cpu.op_class::SimdFloatMisc 0 0.00% 63.60% # Class of executed instruction -drivesys.cpu.op_class::SimdFloatMult 0 0.00% 63.60% # Class of executed instruction -drivesys.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.60% # Class of executed instruction -drivesys.cpu.op_class::SimdFloatSqrt 0 0.00% 63.60% # Class of executed instruction -drivesys.cpu.op_class::MemRead 7678 21.24% 84.84% # Class of executed instruction -drivesys.cpu.op_class::MemWrite 3936 10.89% 95.73% # Class of executed instruction -drivesys.cpu.op_class::FloatMemRead 0 0.00% 95.73% # Class of executed instruction -drivesys.cpu.op_class::FloatMemWrite 0 0.00% 95.73% # Class of executed instruction -drivesys.cpu.op_class::IprAccess 1545 4.27% 100.00% # Class of executed instruction -drivesys.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -drivesys.cpu.op_class::total 36152 # Class of executed instruction -drivesys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -drivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -drivesys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). -drivesys.disk0.dma_write_full_pages 0 # Number of full page size DMA writes. -drivesys.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. -drivesys.disk0.dma_write_txs 0 # Number of DMA write transactions. -drivesys.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -drivesys.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -drivesys.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). -drivesys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes. -drivesys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes. -drivesys.disk2.dma_write_txs 0 # Number of DMA write transactions. -drivesys.iobridge.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -drivesys.iobus.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -drivesys.iobus.trans_dist::ReadReq 5050 # Transaction distribution -drivesys.iobus.trans_dist::ReadResp 5050 # Transaction distribution -drivesys.iobus.trans_dist::WriteReq 81 # Transaction distribution -drivesys.iobus.trans_dist::WriteResp 81 # Transaction distribution -drivesys.iobus.pkt_count_drivesys.bridge.master::drivesys.tsunami.cchip.pio 402 # Packet count per connected master and slave (bytes) -drivesys.iobus.pkt_count_drivesys.bridge.master::drivesys.tsunami.ethernet.pio 160 # Packet count per connected master and slave (bytes) -drivesys.iobus.pkt_count_drivesys.bridge.master::total 562 # Packet count per connected master and slave (bytes) -drivesys.iobus.pkt_count_drivesys.tsunami.ethernet.dma::drivesys.iobridge.slave 9700 # Packet count per connected master and slave (bytes) -drivesys.iobus.pkt_count_drivesys.tsunami.ethernet.dma::total 9700 # Packet count per connected master and slave (bytes) -drivesys.iobus.pkt_count::total 10262 # Packet count per connected master and slave (bytes) -drivesys.iobus.pkt_size_drivesys.bridge.master::drivesys.tsunami.cchip.pio 1608 # Cumulative packet size per connected master and slave (bytes) -drivesys.iobus.pkt_size_drivesys.bridge.master::drivesys.tsunami.ethernet.pio 320 # Cumulative packet size per connected master and slave (bytes) -drivesys.iobus.pkt_size_drivesys.bridge.master::total 1928 # Cumulative packet size per connected master and slave (bytes) -drivesys.iobus.pkt_size_drivesys.tsunami.ethernet.dma::drivesys.iobridge.slave 116400 # Cumulative packet size per connected master and slave (bytes) -drivesys.iobus.pkt_size_drivesys.tsunami.ethernet.dma::total 116400 # Cumulative packet size per connected master and slave (bytes) -drivesys.iobus.pkt_size::total 118328 # Cumulative packet size per connected master and slave (bytes) -drivesys.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -drivesys.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -drivesys.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -drivesys.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -drivesys.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -drivesys.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -drivesys.membus.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -drivesys.membus.trans_dist::ReadReq 47907 # Transaction distribution -drivesys.membus.trans_dist::ReadResp 48111 # Transaction distribution -drivesys.membus.trans_dist::WriteReq 3689 # Transaction distribution -drivesys.membus.trans_dist::WriteResp 3689 # Transaction distribution -drivesys.membus.trans_dist::LoadLockedReq 204 # Transaction distribution -drivesys.membus.trans_dist::StoreCondReq 204 # Transaction distribution -drivesys.membus.trans_dist::StoreCondResp 204 # Transaction distribution -drivesys.membus.pkt_count_drivesys.cpu.icache_port::drivesys.physmem.port 72304 # Packet count per connected master and slave (bytes) -drivesys.membus.pkt_count_drivesys.cpu.icache_port::total 72304 # Packet count per connected master and slave (bytes) -drivesys.membus.pkt_count_drivesys.cpu.dcache_port::drivesys.bridge.slave 562 # Packet count per connected master and slave (bytes) -drivesys.membus.pkt_count_drivesys.cpu.dcache_port::drivesys.physmem.port 21442 # Packet count per connected master and slave (bytes) -drivesys.membus.pkt_count_drivesys.cpu.dcache_port::total 22004 # Packet count per connected master and slave (bytes) -drivesys.membus.pkt_count_drivesys.iobridge.master::drivesys.physmem.port 9700 # Packet count per connected master and slave (bytes) -drivesys.membus.pkt_count_drivesys.iobridge.master::total 9700 # Packet count per connected master and slave (bytes) -drivesys.membus.pkt_count::total 104008 # Packet count per connected master and slave (bytes) -drivesys.membus.pkt_size_drivesys.cpu.icache_port::drivesys.physmem.port 144608 # Cumulative packet size per connected master and slave (bytes) -drivesys.membus.pkt_size_drivesys.cpu.icache_port::total 144608 # Cumulative packet size per connected master and slave (bytes) -drivesys.membus.pkt_size_drivesys.cpu.dcache_port::drivesys.bridge.slave 1928 # Cumulative packet size per connected master and slave (bytes) -drivesys.membus.pkt_size_drivesys.cpu.dcache_port::drivesys.physmem.port 77640 # Cumulative packet size per connected master and slave (bytes) -drivesys.membus.pkt_size_drivesys.cpu.dcache_port::total 79568 # Cumulative packet size per connected master and slave (bytes) -drivesys.membus.pkt_size_drivesys.iobridge.master::drivesys.physmem.port 116400 # Cumulative packet size per connected master and slave (bytes) -drivesys.membus.pkt_size_drivesys.iobridge.master::total 116400 # Cumulative packet size per connected master and slave (bytes) -drivesys.membus.pkt_size::total 340576 # Cumulative packet size per connected master and slave (bytes) -drivesys.membus.snoops 0 # Total snoops (count) -drivesys.membus.snoopTraffic 0 # Total snoop traffic (bytes) -drivesys.membus.snoop_fanout::samples 52004 # Request fanout histogram -drivesys.membus.snoop_fanout::mean 0 # Request fanout histogram -drivesys.membus.snoop_fanout::stdev 0 # Request fanout histogram -drivesys.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -drivesys.membus.snoop_fanout::0 52004 100.00% 100.00% # Request fanout histogram -drivesys.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -drivesys.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -drivesys.membus.snoop_fanout::min_value 0 # Request fanout histogram -drivesys.membus.snoop_fanout::max_value 0 # Request fanout histogram -drivesys.membus.snoop_fanout::total 52004 # Request fanout histogram -drivesys.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -drivesys.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -drivesys.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -drivesys.tsunami.ethernet.clk_domain.clock 2000 # Clock period in ticks -drivesys.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -drivesys.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -drivesys.tsunami.ethernet.descDMAReads 4850 # Number of descriptors the device read w/ DMA -drivesys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -drivesys.tsunami.ethernet.descDmaReadBytes 116400 # number of descriptor bytes read w/ DMA -drivesys.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -drivesys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU -drivesys.tsunami.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post -drivesys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR -drivesys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -drivesys.tsunami.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post -drivesys.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -drivesys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -drivesys.tsunami.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post -drivesys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR -drivesys.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -drivesys.tsunami.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post -drivesys.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -drivesys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -drivesys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post -drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -drivesys.tsunami.ethernet.postedTxIdle 40 # number of TxIdle interrupts posted to CPU -drivesys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post -drivesys.tsunami.ethernet.totalTxIdle 4850 # total number of TxIdle written to ISR -drivesys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -drivesys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post -drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -drivesys.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -drivesys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post -drivesys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -drivesys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post -drivesys.tsunami.ethernet.postedInterrupts 4850 # number of posts to CPU -drivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped -drivesys.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -drivesys.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -drivesys.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -drivesys.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -drivesys.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -drivesys.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -drivesys.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -drivesys.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -drivesys.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -drivesys.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -drivesys.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -drivesys.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -drivesys.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -drivesys.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -drivesys.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -drivesys.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -drivesys.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -drivesys.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -drivesys.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -drivesys.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -drivesys.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -drivesys.tsunami.io.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -drivesys.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -testsys.voltage_domain.voltage 1 # Voltage in Volts -testsys.clk_domain.clock 1000 # Clock period in ticks -testsys.physmem.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -testsys.physmem.bytes_read::cpu.inst 144504 # Number of bytes read from this memory -testsys.physmem.bytes_read::cpu.data 49936 # Number of bytes read from this memory -testsys.physmem.bytes_read::tsunami.ethernet 116376 # Number of bytes read from this memory -testsys.physmem.bytes_read::total 310816 # Number of bytes read from this memory -testsys.physmem.bytes_inst_read::cpu.inst 144504 # Number of instructions bytes read from this memory -testsys.physmem.bytes_inst_read::total 144504 # Number of instructions bytes read from this memory -testsys.physmem.bytes_written::cpu.data 27704 # Number of bytes written to this memory -testsys.physmem.bytes_written::total 27704 # Number of bytes written to this memory -testsys.physmem.num_reads::cpu.inst 36126 # Number of read requests responded to by this memory -testsys.physmem.num_reads::cpu.data 6905 # Number of read requests responded to by this memory -testsys.physmem.num_reads::tsunami.ethernet 4849 # Number of read requests responded to by this memory -testsys.physmem.num_reads::total 47880 # Number of read requests responded to by this memory -testsys.physmem.num_writes::cpu.data 3814 # Number of write requests responded to by this memory -testsys.physmem.num_writes::total 3814 # Number of write requests responded to by this memory -testsys.physmem.bw_read::cpu.inst 354749025 # Total read bandwidth from this memory (bytes/s) -testsys.physmem.bw_read::cpu.data 122590014 # Total read bandwidth from this memory (bytes/s) -testsys.physmem.bw_read::tsunami.ethernet 285696400 # Total read bandwidth from this memory (bytes/s) -testsys.physmem.bw_read::total 763035438 # Total read bandwidth from this memory (bytes/s) -testsys.physmem.bw_inst_read::cpu.inst 354749025 # Instruction read bandwidth from this memory (bytes/s) -testsys.physmem.bw_inst_read::total 354749025 # Instruction read bandwidth from this memory (bytes/s) -testsys.physmem.bw_write::cpu.data 68011730 # Write bandwidth from this memory (bytes/s) -testsys.physmem.bw_write::total 68011730 # Write bandwidth from this memory (bytes/s) -testsys.physmem.bw_total::cpu.inst 354749025 # Total bandwidth to/from this memory (bytes/s) -testsys.physmem.bw_total::cpu.data 190601743 # Total bandwidth to/from this memory (bytes/s) -testsys.physmem.bw_total::tsunami.ethernet 285696400 # Total bandwidth to/from this memory (bytes/s) -testsys.physmem.bw_total::total 831047168 # Total bandwidth to/from this memory (bytes/s) -testsys.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -testsys.bridge.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -testsys.cpu.clk_domain.clock 500 # Clock period in ticks -testsys.cpu.dtb.fetch_hits 0 # ITB hits -testsys.cpu.dtb.fetch_misses 0 # ITB misses -testsys.cpu.dtb.fetch_acv 0 # ITB acv -testsys.cpu.dtb.fetch_accesses 0 # ITB accesses -testsys.cpu.dtb.read_hits 7065 # DTB read hits -testsys.cpu.dtb.read_misses 0 # DTB read misses -testsys.cpu.dtb.read_acv 0 # DTB read access violations -testsys.cpu.dtb.read_accesses 0 # DTB read accesses -testsys.cpu.dtb.write_hits 3935 # DTB write hits -testsys.cpu.dtb.write_misses 0 # DTB write misses -testsys.cpu.dtb.write_acv 0 # DTB write access violations -testsys.cpu.dtb.write_accesses 0 # DTB write accesses -testsys.cpu.dtb.data_hits 11000 # DTB hits -testsys.cpu.dtb.data_misses 0 # DTB misses -testsys.cpu.dtb.data_acv 0 # DTB access violations -testsys.cpu.dtb.data_accesses 0 # DTB accesses -testsys.cpu.itb.fetch_hits 5992 # ITB hits -testsys.cpu.itb.fetch_misses 0 # ITB misses -testsys.cpu.itb.fetch_acv 0 # ITB acv -testsys.cpu.itb.fetch_accesses 5992 # ITB accesses -testsys.cpu.itb.read_hits 0 # DTB read hits -testsys.cpu.itb.read_misses 0 # DTB read misses -testsys.cpu.itb.read_acv 0 # DTB read access violations -testsys.cpu.itb.read_accesses 0 # DTB read accesses -testsys.cpu.itb.write_hits 0 # DTB write hits -testsys.cpu.itb.write_misses 0 # DTB write misses -testsys.cpu.itb.write_acv 0 # DTB write access violations -testsys.cpu.itb.write_accesses 0 # DTB write accesses -testsys.cpu.itb.data_hits 0 # DTB hits -testsys.cpu.itb.data_misses 0 # DTB misses -testsys.cpu.itb.data_acv 0 # DTB access violations -testsys.cpu.itb.data_accesses 0 # DTB accesses -testsys.cpu.numPwrStateTransitions 80 # Number of power state transitions -testsys.cpu.pwrStateClkGateDist::samples 41 # Distribution of time spent in the clock gated state -testsys.cpu.pwrStateClkGateDist::mean 9495085.365854 # Distribution of time spent in the clock gated state -testsys.cpu.pwrStateClkGateDist::stdev 1417220.659876 # Distribution of time spent in the clock gated state -testsys.cpu.pwrStateClkGateDist::1000-5e+10 41 100.00% 100.00% # Distribution of time spent in the clock gated state -testsys.cpu.pwrStateClkGateDist::min_value 2964500 # Distribution of time spent in the clock gated state -testsys.cpu.pwrStateClkGateDist::max_value 9815000 # Distribution of time spent in the clock gated state -testsys.cpu.pwrStateClkGateDist::total 41 # Distribution of time spent in the clock gated state -testsys.cpu.pwrStateResidencyTicks::ON 18043000 # Cumulative time (in ticks) in various power states -testsys.cpu.pwrStateResidencyTicks::CLK_GATED 389298500 # Cumulative time (in ticks) in various power states -testsys.cpu.numCycles 821056 # number of cpu cycles simulated -testsys.cpu.numWorkItemsStarted 0 # number of work items this cpu started -testsys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -testsys.cpu.kern.inst.arm 0 # number of arm instructions executed -testsys.cpu.kern.inst.quiesce 40 # number of quiesce instructions executed -testsys.cpu.kern.inst.hwrei 295 # number of hwrei instructions executed -testsys.cpu.kern.ipl_count::0 123 41.84% 41.84% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count::21 40 13.61% 55.44% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count::22 1 0.34% 55.78% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count::31 130 44.22% 100.00% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count::total 294 # number of times we switched to this ipl -testsys.cpu.kern.ipl_good::0 123 42.86% 42.86% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_good::21 40 13.94% 56.79% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_good::22 1 0.35% 57.14% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_good::31 123 42.86% 100.00% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_good::total 287 # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_ticks::0 397967000 96.95% 96.95% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks::21 3240000 0.79% 97.73% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks::22 43000 0.01% 97.74% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks::31 9258000 2.26% 100.00% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks::total 410508000 # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_used::0 1 # fraction of swpipl calls that actually changed the ipl -testsys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl -testsys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -testsys.cpu.kern.ipl_used::31 0.946154 # fraction of swpipl calls that actually changed the ipl -testsys.cpu.kern.ipl_used::total 0.976190 # fraction of swpipl calls that actually changed the ipl -testsys.cpu.kern.callpal::swpipl 212 83.46% 83.46% # number of callpals executed -testsys.cpu.kern.callpal::rdps 1 0.39% 83.86% # number of callpals executed -testsys.cpu.kern.callpal::rti 41 16.14% 100.00% # number of callpals executed -testsys.cpu.kern.callpal::total 254 # number of callpals executed -testsys.cpu.kern.mode_switch::kernel 0 # number of protection mode switches -testsys.cpu.kern.mode_switch::user 0 # number of protection mode switches -testsys.cpu.kern.mode_switch::idle 41 # number of protection mode switches -testsys.cpu.kern.mode_good::kernel 0 -testsys.cpu.kern.mode_good::user 0 -testsys.cpu.kern.mode_good::idle 0 -testsys.cpu.kern.mode_switch_good::kernel nan # fraction of useful protection mode switches -testsys.cpu.kern.mode_switch_good::user nan # fraction of useful protection mode switches -testsys.cpu.kern.mode_switch_good::idle 0 # fraction of useful protection mode switches -testsys.cpu.kern.mode_switch_good::total 0 # fraction of useful protection mode switches -testsys.cpu.kern.mode_ticks::kernel 0 # number of ticks spent at the given mode -testsys.cpu.kern.mode_ticks::user 0 # number of ticks spent at the given mode -testsys.cpu.kern.mode_ticks::idle 0 # number of ticks spent at the given mode -testsys.cpu.kern.swap_context 0 # number of times the context was actually changed -testsys.cpu.committedInsts 36126 # Number of instructions committed -testsys.cpu.committedOps 36126 # Number of ops (including micro ops) committed -testsys.cpu.num_int_alu_accesses 33492 # Number of integer alu accesses -testsys.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -testsys.cpu.num_func_calls 2384 # number of times a function call or return occured -testsys.cpu.num_conditional_control_insts 2346 # number of instructions that are conditional controls -testsys.cpu.num_int_insts 33492 # number of integer instructions -testsys.cpu.num_fp_insts 0 # number of float instructions -testsys.cpu.num_int_register_reads 43747 # number of times the integer registers were read -testsys.cpu.num_int_register_writes 26476 # number of times the integer registers were written -testsys.cpu.num_fp_register_reads 0 # number of times the floating registers were read -testsys.cpu.num_fp_register_writes 0 # number of times the floating registers were written -testsys.cpu.num_mem_refs 11041 # number of memory refs -testsys.cpu.num_load_insts 7105 # Number of load instructions -testsys.cpu.num_store_insts 3936 # Number of store instructions -testsys.cpu.num_idle_cycles 784687.711054 # Number of idle cycles -testsys.cpu.num_busy_cycles 36368.288946 # Number of busy cycles -testsys.cpu.not_idle_fraction 0.044295 # Percentage of non-idle cycles -testsys.cpu.idle_fraction 0.955705 # Percentage of idle cycles -testsys.cpu.Branches 5238 # Number of branches fetched -testsys.cpu.op_class::No_OpClass 1261 3.49% 3.49% # Class of executed instruction -testsys.cpu.op_class::IntAlu 21664 59.97% 63.46% # Class of executed instruction -testsys.cpu.op_class::IntMult 44 0.12% 63.58% # Class of executed instruction -testsys.cpu.op_class::IntDiv 0 0.00% 63.58% # Class of executed instruction -testsys.cpu.op_class::FloatAdd 0 0.00% 63.58% # Class of executed instruction -testsys.cpu.op_class::FloatCmp 0 0.00% 63.58% # Class of executed instruction -testsys.cpu.op_class::FloatCvt 0 0.00% 63.58% # Class of executed instruction -testsys.cpu.op_class::FloatMult 0 0.00% 63.58% # Class of executed instruction -testsys.cpu.op_class::FloatMultAcc 0 0.00% 63.58% # Class of executed instruction -testsys.cpu.op_class::FloatDiv 0 0.00% 63.58% # Class of executed instruction -testsys.cpu.op_class::FloatMisc 0 0.00% 63.58% # Class of executed instruction -testsys.cpu.op_class::FloatSqrt 0 0.00% 63.58% # Class of executed instruction -testsys.cpu.op_class::SimdAdd 0 0.00% 63.58% # Class of executed instruction -testsys.cpu.op_class::SimdAddAcc 0 0.00% 63.58% # Class of executed instruction -testsys.cpu.op_class::SimdAlu 0 0.00% 63.58% # Class of executed instruction -testsys.cpu.op_class::SimdCmp 0 0.00% 63.58% # Class of executed instruction -testsys.cpu.op_class::SimdCvt 0 0.00% 63.58% # Class of executed instruction -testsys.cpu.op_class::SimdMisc 0 0.00% 63.58% # Class of executed instruction -testsys.cpu.op_class::SimdMult 0 0.00% 63.58% # Class of executed instruction -testsys.cpu.op_class::SimdMultAcc 0 0.00% 63.58% # Class of executed instruction -testsys.cpu.op_class::SimdShift 0 0.00% 63.58% # Class of executed instruction -testsys.cpu.op_class::SimdShiftAcc 0 0.00% 63.58% # Class of executed instruction -testsys.cpu.op_class::SimdSqrt 0 0.00% 63.58% # Class of executed instruction -testsys.cpu.op_class::SimdFloatAdd 0 0.00% 63.58% # Class of executed instruction -testsys.cpu.op_class::SimdFloatAlu 0 0.00% 63.58% # Class of executed instruction -testsys.cpu.op_class::SimdFloatCmp 0 0.00% 63.58% # Class of executed instruction -testsys.cpu.op_class::SimdFloatCvt 0 0.00% 63.58% # Class of executed instruction -testsys.cpu.op_class::SimdFloatDiv 0 0.00% 63.58% # Class of executed instruction -testsys.cpu.op_class::SimdFloatMisc 0 0.00% 63.58% # Class of executed instruction -testsys.cpu.op_class::SimdFloatMult 0 0.00% 63.58% # Class of executed instruction -testsys.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.58% # Class of executed instruction -testsys.cpu.op_class::SimdFloatSqrt 0 0.00% 63.58% # Class of executed instruction -testsys.cpu.op_class::MemRead 7674 21.24% 84.82% # Class of executed instruction -testsys.cpu.op_class::MemWrite 3938 10.90% 95.72% # Class of executed instruction -testsys.cpu.op_class::FloatMemRead 0 0.00% 95.72% # Class of executed instruction -testsys.cpu.op_class::FloatMemWrite 0 0.00% 95.72% # Class of executed instruction -testsys.cpu.op_class::IprAccess 1545 4.28% 100.00% # Class of executed instruction -testsys.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -testsys.cpu.op_class::total 36126 # Class of executed instruction -testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -testsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). -testsys.disk0.dma_write_full_pages 0 # Number of full page size DMA writes. -testsys.disk0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. -testsys.disk0.dma_write_txs 0 # Number of DMA write transactions. -testsys.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -testsys.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -testsys.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). -testsys.disk2.dma_write_full_pages 0 # Number of full page size DMA writes. -testsys.disk2.dma_write_bytes 0 # Number of bytes transfered via DMA writes. -testsys.disk2.dma_write_txs 0 # Number of DMA write transactions. -testsys.iobridge.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -testsys.iobus.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -testsys.iobus.trans_dist::ReadReq 5049 # Transaction distribution -testsys.iobus.trans_dist::ReadResp 5049 # Transaction distribution -testsys.iobus.trans_dist::WriteReq 81 # Transaction distribution -testsys.iobus.trans_dist::WriteResp 81 # Transaction distribution -testsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.cchip.pio 402 # Packet count per connected master and slave (bytes) -testsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.ethernet.pio 160 # Packet count per connected master and slave (bytes) -testsys.iobus.pkt_count_testsys.bridge.master::total 562 # Packet count per connected master and slave (bytes) -testsys.iobus.pkt_count_testsys.tsunami.ethernet.dma::testsys.iobridge.slave 9698 # Packet count per connected master and slave (bytes) -testsys.iobus.pkt_count_testsys.tsunami.ethernet.dma::total 9698 # Packet count per connected master and slave (bytes) -testsys.iobus.pkt_count::total 10260 # Packet count per connected master and slave (bytes) -testsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.cchip.pio 1608 # Cumulative packet size per connected master and slave (bytes) -testsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.ethernet.pio 320 # Cumulative packet size per connected master and slave (bytes) -testsys.iobus.pkt_size_testsys.bridge.master::total 1928 # Cumulative packet size per connected master and slave (bytes) -testsys.iobus.pkt_size_testsys.tsunami.ethernet.dma::testsys.iobridge.slave 116376 # Cumulative packet size per connected master and slave (bytes) -testsys.iobus.pkt_size_testsys.tsunami.ethernet.dma::total 116376 # Cumulative packet size per connected master and slave (bytes) -testsys.iobus.pkt_size::total 118304 # Cumulative packet size per connected master and slave (bytes) -testsys.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -testsys.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -testsys.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -testsys.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -testsys.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -testsys.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -testsys.membus.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -testsys.membus.trans_dist::ReadReq 47876 # Transaction distribution -testsys.membus.trans_dist::ReadResp 48080 # Transaction distribution -testsys.membus.trans_dist::WriteReq 3691 # Transaction distribution -testsys.membus.trans_dist::WriteResp 3691 # Transaction distribution -testsys.membus.trans_dist::LoadLockedReq 204 # Transaction distribution -testsys.membus.trans_dist::StoreCondReq 204 # Transaction distribution -testsys.membus.trans_dist::StoreCondResp 204 # Transaction distribution -testsys.membus.pkt_count_testsys.cpu.icache_port::testsys.physmem.port 72252 # Packet count per connected master and slave (bytes) -testsys.membus.pkt_count_testsys.cpu.icache_port::total 72252 # Packet count per connected master and slave (bytes) -testsys.membus.pkt_count_testsys.cpu.dcache_port::testsys.bridge.slave 562 # Packet count per connected master and slave (bytes) -testsys.membus.pkt_count_testsys.cpu.dcache_port::testsys.physmem.port 21438 # Packet count per connected master and slave (bytes) -testsys.membus.pkt_count_testsys.cpu.dcache_port::total 22000 # Packet count per connected master and slave (bytes) -testsys.membus.pkt_count_testsys.iobridge.master::testsys.physmem.port 9698 # Packet count per connected master and slave (bytes) -testsys.membus.pkt_count_testsys.iobridge.master::total 9698 # Packet count per connected master and slave (bytes) -testsys.membus.pkt_count::total 103950 # Packet count per connected master and slave (bytes) -testsys.membus.pkt_size_testsys.cpu.icache_port::testsys.physmem.port 144504 # Cumulative packet size per connected master and slave (bytes) -testsys.membus.pkt_size_testsys.cpu.icache_port::total 144504 # Cumulative packet size per connected master and slave (bytes) -testsys.membus.pkt_size_testsys.cpu.dcache_port::testsys.bridge.slave 1928 # Cumulative packet size per connected master and slave (bytes) -testsys.membus.pkt_size_testsys.cpu.dcache_port::testsys.physmem.port 77640 # Cumulative packet size per connected master and slave (bytes) -testsys.membus.pkt_size_testsys.cpu.dcache_port::total 79568 # Cumulative packet size per connected master and slave (bytes) -testsys.membus.pkt_size_testsys.iobridge.master::testsys.physmem.port 116376 # Cumulative packet size per connected master and slave (bytes) -testsys.membus.pkt_size_testsys.iobridge.master::total 116376 # Cumulative packet size per connected master and slave (bytes) -testsys.membus.pkt_size::total 340448 # Cumulative packet size per connected master and slave (bytes) -testsys.membus.snoops 0 # Total snoops (count) -testsys.membus.snoopTraffic 0 # Total snoop traffic (bytes) -testsys.membus.snoop_fanout::samples 51975 # Request fanout histogram -testsys.membus.snoop_fanout::mean 0 # Request fanout histogram -testsys.membus.snoop_fanout::stdev 0 # Request fanout histogram -testsys.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -testsys.membus.snoop_fanout::0 51975 100.00% 100.00% # Request fanout histogram -testsys.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -testsys.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -testsys.membus.snoop_fanout::min_value 0 # Request fanout histogram -testsys.membus.snoop_fanout::max_value 0 # Request fanout histogram -testsys.membus.snoop_fanout::total 51975 # Request fanout histogram -testsys.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -testsys.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -testsys.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -testsys.tsunami.ethernet.clk_domain.clock 2000 # Clock period in ticks -testsys.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -testsys.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -testsys.tsunami.ethernet.descDMAReads 4849 # Number of descriptors the device read w/ DMA -testsys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -testsys.tsunami.ethernet.descDmaReadBytes 116376 # number of descriptor bytes read w/ DMA -testsys.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -testsys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU -testsys.tsunami.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post -testsys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR -testsys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -testsys.tsunami.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post -testsys.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -testsys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -testsys.tsunami.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post -testsys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR -testsys.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -testsys.tsunami.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post -testsys.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -testsys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -testsys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post -testsys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -testsys.tsunami.ethernet.postedTxIdle 40 # number of TxIdle interrupts posted to CPU -testsys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post -testsys.tsunami.ethernet.totalTxIdle 4849 # total number of TxIdle written to ISR -testsys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -testsys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post -testsys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -testsys.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -testsys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post -testsys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -testsys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post -testsys.tsunami.ethernet.postedInterrupts 4849 # number of posts to CPU -testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped -testsys.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -testsys.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -testsys.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -testsys.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -testsys.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -testsys.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -testsys.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -testsys.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -testsys.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -testsys.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -testsys.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -testsys.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -testsys.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -testsys.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -testsys.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -testsys.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -testsys.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -testsys.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -testsys.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -testsys.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -testsys.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -testsys.tsunami.io.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states -testsys.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 407341500 # Cumulative time (in ticks) in various power states - ----------- End Simulation Statistics ---------- diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal --- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,123 +0,0 @@ -M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 - Got Configuration 623 - memsize 8000000 pages 4000 - First free page after ROM 0xFFFFFC0000018000 - HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000 - kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x1 - CPU Clock at 2000 MHz IntrClockFrequency=1024 - Booting with 1 processor(s) - KSP: 0x20043FE8 PTBR 0x20 - Console Callback at 0x0, fixup at 0x0, crb offset: 0x510 - Memory cluster 0 [0 - 392] - Memory cluster 1 [392 - 15992] - Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000 - ConsoleDispatch at virt 10000658 phys 18658 val FFFFFC00000100A8 - unix_boot_mem ends at FFFFFC0000076000 - k_argc = 0 - jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067) - CallbackFixup 0 18000, t7=FFFFFC000070C000 - Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006 - Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM - Major Options: SMP LEGACY_START VERBOSE_MCHECK - Command line: root=/dev/hda1 console=ttyS0 - memcluster 0, usage 1, start 0, end 392 - memcluster 1, usage 0, start 392, end 16384 - freeing pages 1069:16384 - reserving pages 1069:1070 - SMP: 1 CPUs probed -- cpu_present_mask = 1 - Built 1 zonelists - Kernel command line: root=/dev/hda1 console=ttyS0 - PID hash table entries: 1024 (order: 10, 32768 bytes) - Using epoch = 1900 - Console: colour dummy device 80x25 - Dentry cache hash table entries: 32768 (order: 5, 262144 bytes) - Inode-cache hash table entries: 16384 (order: 4, 131072 bytes) - Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init) - Mount-cache hash table entries: 512 - SMP mode deactivated. - Brought up 1 CPUs - SMP: Total of 1 processors activated (4002.20 BogoMIPS). - NET: Registered protocol family 16 - EISA bus registered - pci: enabling save/restore of SRM state - SCSI subsystem initialized - srm_env: version 0.0.5 loaded successfully - Installing knfsd (copyright (C) 1996 okir@monad.swb.de). - Initializing Cryptographic API - rtc: Standard PC (1900) epoch (1900) detected - Real Time Clock Driver v1.12 - Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled - ttyS0 at I/O 0x3f8 (irq = 4) is a 8250 - io scheduler noop registered - io scheduler anticipatory registered - io scheduler deadline registered - io scheduler cfq registered - loop: loaded (max 8 devices) - nbd: registered device at major 43 - ns83820.c: National Semiconductor DP83820 10/100/1000 driver. - PCI: Setting latency timer of device 0000:00:01.0 to 64 - eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000 - eth0: enabling optical transceiver - eth0: using 64 bit addressing. - eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:02 io=0x09000000 irq=30 f=h,sg - tun: Universal TUN/TAP device driver, 1.6 - tun: (C) 1999-2004 Max Krasnyansky - Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2 - ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx - PIIX4: IDE controller at PCI slot 0000:00:00.0 - PIIX4: chipset revision 0 - PIIX4: 100% native mode on irq 31 - PCI: Setting latency timer of device 0000:00:00.0 to 64 - ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA - ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA - hda: M5 IDE Disk, ATA DISK drive - hdb: M5 IDE Disk, ATA DISK drive - ide0 at 0x8410-0x8417,0x8422 on irq 31 - hda: max request size: 128KiB - hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33) - hda: cache flushes not supported - hda: hda1 - hdb: max request size: 128KiB - hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33) - hdb: cache flushes not supported - hdb: unknown partition table - mice: PS/2 mouse device common for all mice - NET: Registered protocol family 2 - IP route cache hash table entries: 4096 (order: 2, 32768 bytes) - TCP established hash table entries: 16384 (order: 5, 262144 bytes) - TCP bind hash table entries: 16384 (order: 5, 262144 bytes) - TCP: Hash tables configured (established 16384 bind 16384) - TCP reno registered - ip_conntrack version 2.1 (512 buckets, 4096 max) - 296 bytes per conntrack - ip_tables: (C) 2000-2002 Netfilter core team - arp_tables: (C) 2002 David S. Miller - TCP bic registered - Initializing IPsec netlink socket - NET: Registered protocol family 1 - NET: Registered protocol family 17 - NET: Registered protocol family 15 - Bridge firewalling registered - 802.1Q VLAN Support v1.8 Ben Greear - All bugs added by David S. Miller - VFS: Mounted root (ext2 filesystem) readonly. - Freeing unused kernel memory: 224k freed - init started: BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary -mounting filesystems... -EXT2-fs warning: checktime reached, running e2fsck is recommended - loading script... -setting up network... -eth0: link now 1000F mbps, full duplex and up. - waiting for server...server ready -starting test... -netperf warmup -/benchmarks/netperf-bin/netperf -H 10.0.0.1 -t TCP_STREAM -l -100k -TCP STREAM TEST to 10.0.0.1 : dirty data -Recv Send Send -Socket Socket Message Elapsed -Size Size Size Time Throughput -bytes bytes bytes secs. 10^6bits/sec - -5000000 5000000 5000000 1.30 30.82 -netperf benchmark -/benchmarks/netperf-bin/netperf -H 10.0.0.1 -t TCP_STREAM -k16384,0 -K16384,0 -- -m 65536 -M 65536 -s 262144 -S 262144 -TCP STREAM TEST to 10.0.0.1 : dirty data diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini --- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,877 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=MinorCPU -children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload -branchPred=system.cpu.branchPred -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -decodeCycleInput=true -decodeInputBufferSize=3 -decodeInputWidth=2 -decodeToExecuteForwardDelay=1 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -enableIdling=true -eventq_index=0 -executeAllowEarlyMemoryIssue=true -executeBranchDelay=1 -executeCommitLimit=2 -executeCycleInput=true -executeFuncUnits=system.cpu.executeFuncUnits -executeInputBufferSize=7 -executeInputWidth=2 -executeIssueLimit=2 -executeLSQMaxStoreBufferStoresPerCycle=2 -executeLSQRequestsQueueSize=1 -executeLSQStoreBufferSize=5 -executeLSQTransfersQueueSize=2 -executeMaxAccessesInMemory=2 -executeMemoryCommitLimit=1 -executeMemoryIssueLimit=1 -executeMemoryWidth=0 -executeSetTraceTimeOnCommit=true -executeSetTraceTimeOnIssue=false -fetch1FetchLimit=1 -fetch1LineSnapWidth=0 -fetch1LineWidth=0 -fetch1ToFetch2BackwardDelay=1 -fetch1ToFetch2ForwardDelay=1 -fetch2CycleInput=true -fetch2InputBufferSize=2 -fetch2ToDecodeForwardDelay=1 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -threadPolicy=RoundRobin -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.branchPred] -type=TournamentBP -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -indirectHashGHR=true -indirectHashTargets=true -indirectPathLength=3 -indirectSets=256 -indirectTagSize=16 -indirectWays=2 -instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 -useIndirect=true - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.executeFuncUnits] -type=MinorFUPool -children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 -eventq_index=0 -funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 - -[system.cpu.executeFuncUnits.funcUnits0] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits0.timings - -[system.cpu.executeFuncUnits.funcUnits0.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntAlu - -[system.cpu.executeFuncUnits.funcUnits0.timings] -type=MinorFUTiming -children=opClasses -description=Int -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits1] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits1.timings - -[system.cpu.executeFuncUnits.funcUnits1.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntAlu - -[system.cpu.executeFuncUnits.funcUnits1.timings] -type=MinorFUTiming -children=opClasses -description=Int -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits2] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits2.timings - -[system.cpu.executeFuncUnits.funcUnits2.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntMult - -[system.cpu.executeFuncUnits.funcUnits2.timings] -type=MinorFUTiming -children=opClasses -description=Mul -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses -srcRegsRelativeLats=0 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits3] -type=MinorFU -children=opClasses -cantForwardFromFUIndices= -eventq_index=0 -issueLat=9 -opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses -opLat=9 -timings= - -[system.cpu.executeFuncUnits.funcUnits3.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntDiv - -[system.cpu.executeFuncUnits.funcUnits4] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses -opLat=6 -timings=system.cpu.executeFuncUnits.funcUnits4.timings - -[system.cpu.executeFuncUnits.funcUnits4.opClasses] -type=MinorOpClassSet -children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] -type=MinorOpClass -eventq_index=0 -opClass=FloatAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01] -type=MinorOpClass -eventq_index=0 -opClass=FloatCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02] -type=MinorOpClass -eventq_index=0 -opClass=FloatCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] -type=MinorOpClass -eventq_index=0 -opClass=FloatMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] -type=MinorOpClass -eventq_index=0 -opClass=FloatDiv - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] -type=MinorOpClass -eventq_index=0 -opClass=FloatSqrt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] -type=MinorOpClass -eventq_index=0 -opClass=SimdAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] -type=MinorOpClass -eventq_index=0 -opClass=SimdAddAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] -type=MinorOpClass -eventq_index=0 -opClass=SimdAlu - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] -type=MinorOpClass -eventq_index=0 -opClass=SimdCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] -type=MinorOpClass -eventq_index=0 -opClass=SimdCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] -type=MinorOpClass -eventq_index=0 -opClass=SimdMisc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] -type=MinorOpClass -eventq_index=0 -opClass=SimdMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] -type=MinorOpClass -eventq_index=0 -opClass=SimdMultAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] -type=MinorOpClass -eventq_index=0 -opClass=SimdShift - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] -type=MinorOpClass -eventq_index=0 -opClass=SimdShiftAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] -type=MinorOpClass -eventq_index=0 -opClass=SimdSqrt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatAlu - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatDiv - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMisc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMultAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatSqrt - -[system.cpu.executeFuncUnits.funcUnits4.timings] -type=MinorFUTiming -children=opClasses -description=FloatSimd -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits5] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses -opLat=1 -timings=system.cpu.executeFuncUnits.funcUnits5.timings - -[system.cpu.executeFuncUnits.funcUnits5.opClasses] -type=MinorOpClassSet -children=opClasses0 opClasses1 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 - -[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] -type=MinorOpClass -eventq_index=0 -opClass=MemRead - -[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] -type=MinorOpClass -eventq_index=0 -opClass=MemWrite - -[system.cpu.executeFuncUnits.funcUnits5.timings] -type=MinorFUTiming -children=opClasses -description=Mem -eventq_index=0 -extraAssumedLat=2 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses -srcRegsRelativeLats=1 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits6] -type=MinorFU -children=opClasses -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses -opLat=1 -timings= - -[system.cpu.executeFuncUnits.funcUnits6.opClasses] -type=MinorOpClassSet -children=opClasses0 opClasses1 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 - -[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] -type=MinorOpClass -eventq_index=0 -opClass=IprAccess - -[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] -type=MinorOpClass -eventq_index=0 -opClass=InstPrefetch - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=hello -cwd= -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/linux/hello -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=0:134217727:0:0:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=6000 -tXPDLL=0 -tXS=270000 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/linux/minor-timing/simerr --- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/simerr Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,3 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/linux/minor-timing/simout --- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/simout Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,15 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:19:43 -gem5 executing on e108600-lin, pid 28041 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/linux/minor-timing - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Hello world! -Exiting @ tick 41083000 because target called exit() diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt --- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,763 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000041 # Number of seconds simulated -sim_ticks 41083000 # Number of ticks simulated -final_tick 41083000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 217103 # Simulator instruction rate (inst/s) -host_op_rate 217013 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1389706699 # Simulator tick rate (ticks/s) -host_mem_usage 253264 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host -sim_insts 6413 # Number of instructions simulated -sim_ops 6413 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 23232 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10816 # Number of bytes read from this memory -system.physmem.bytes_read::total 34048 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 23232 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 23232 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 363 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 169 # Number of read requests responded to by this memory -system.physmem.num_reads::total 532 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 565489375 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 263271913 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 828761288 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 565489375 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 565489375 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 565489375 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 263271913 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 828761288 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 532 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 532 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 34048 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 34048 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 73 # Per bank write bursts -system.physmem.perBankRdBursts::1 39 # Per bank write bursts -system.physmem.perBankRdBursts::2 36 # Per bank write bursts -system.physmem.perBankRdBursts::3 54 # Per bank write bursts -system.physmem.perBankRdBursts::4 45 # Per bank write bursts -system.physmem.perBankRdBursts::5 21 # Per bank write bursts -system.physmem.perBankRdBursts::6 1 # Per bank write bursts -system.physmem.perBankRdBursts::7 5 # Per bank write bursts -system.physmem.perBankRdBursts::8 0 # Per bank write bursts -system.physmem.perBankRdBursts::9 1 # Per bank write bursts -system.physmem.perBankRdBursts::10 21 # Per bank write bursts -system.physmem.perBankRdBursts::11 29 # Per bank write bursts -system.physmem.perBankRdBursts::12 19 # Per bank write bursts -system.physmem.perBankRdBursts::13 127 # Per bank write bursts -system.physmem.perBankRdBursts::14 47 # Per bank write bursts -system.physmem.perBankRdBursts::15 14 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 40972000 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 532 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 443 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 85 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 91 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 363.604396 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 235.588514 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 321.826485 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22 24.18% 24.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 22 24.18% 48.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13 14.29% 62.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 8 8.79% 71.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5 5.49% 76.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 4 4.40% 81.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3 3.30% 84.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 8 8.79% 93.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6 6.59% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 91 # Bytes accessed per row activation -system.physmem.totQLat 6580250 # Total ticks spent queuing -system.physmem.totMemAccLat 16555250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2660000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12368.89 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31118.89 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 828.76 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 828.76 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 6.47 # Data bus utilization in percentage -system.physmem.busUtilRead 6.47 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.18 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 436 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.95 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 77015.04 # Average gap between requests -system.physmem.pageHitRate 81.95 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 264180 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 136620 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1956360 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3073200.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3932430 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 68640 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 13617300 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 928800 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 23977530 # Total energy per rank (pJ) -system.physmem_0.averagePower 583.625643 # Core power per rank (mW) -system.physmem_0.totalIdleTime 32009500 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 39500 # Time in different power states -system.physmem_0.memoryStateTime::REF 1300000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 0 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 2418500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 7463000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 29862000 # Time in different power states -system.physmem_1.actEnergy 421260 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 208725 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1842120 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3073200.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 4022490 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 174720 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 14292750 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 178080 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 24213345 # Total energy per rank (pJ) -system.physmem_1.averagePower 589.365503 # Core power per rank (mW) -system.physmem_1.totalIdleTime 31744250 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 288500 # Time in different power states -system.physmem_1.memoryStateTime::REF 1300000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 0 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 464250 # Time in different power states -system.physmem_1.memoryStateTime::ACT 7679500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 31350750 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 2003 # Number of BP lookups -system.cpu.branchPred.condPredicted 1238 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 379 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1605 # Number of BTB lookups -system.cpu.branchPred.BTBHits 377 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 23.489097 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 235 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 14 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 335 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 13 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 322 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 113 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1365 # DTB read hits -system.cpu.dtb.read_misses 11 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 1376 # DTB read accesses -system.cpu.dtb.write_hits 884 # DTB write hits -system.cpu.dtb.write_misses 3 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 887 # DTB write accesses -system.cpu.dtb.data_hits 2249 # DTB hits -system.cpu.dtb.data_misses 14 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 2263 # DTB accesses -system.cpu.itb.fetch_hits 2686 # ITB hits -system.cpu.itb.fetch_misses 17 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2703 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 41083000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 82166 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 6413 # Number of instructions committed -system.cpu.committedOps 6413 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1095 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 12.812412 # CPI: cycles per instruction -system.cpu.ipc 0.078049 # IPC: instructions per cycle -system.cpu.op_class_0::No_OpClass 19 0.30% 0.30% # Class of committed instruction -system.cpu.op_class_0::IntAlu 4331 67.53% 67.83% # Class of committed instruction -system.cpu.op_class_0::IntMult 1 0.02% 67.85% # Class of committed instruction -system.cpu.op_class_0::IntDiv 0 0.00% 67.85% # Class of committed instruction -system.cpu.op_class_0::FloatAdd 2 0.03% 67.88% # Class of committed instruction -system.cpu.op_class_0::FloatCmp 0 0.00% 67.88% # Class of committed instruction -system.cpu.op_class_0::FloatCvt 0 0.00% 67.88% # Class of committed instruction -system.cpu.op_class_0::FloatMult 0 0.00% 67.88% # Class of committed instruction -system.cpu.op_class_0::FloatMultAcc 0 0.00% 67.88% # Class of committed instruction -system.cpu.op_class_0::FloatDiv 0 0.00% 67.88% # Class of committed instruction -system.cpu.op_class_0::FloatMisc 0 0.00% 67.88% # Class of committed instruction -system.cpu.op_class_0::FloatSqrt 0 0.00% 67.88% # Class of committed instruction -system.cpu.op_class_0::SimdAdd 0 0.00% 67.88% # Class of committed instruction -system.cpu.op_class_0::SimdAddAcc 0 0.00% 67.88% # Class of committed instruction -system.cpu.op_class_0::SimdAlu 0 0.00% 67.88% # Class of committed instruction -system.cpu.op_class_0::SimdCmp 0 0.00% 67.88% # Class of committed instruction -system.cpu.op_class_0::SimdCvt 0 0.00% 67.88% # Class of committed instruction -system.cpu.op_class_0::SimdMisc 0 0.00% 67.88% # Class of committed instruction -system.cpu.op_class_0::SimdMult 0 0.00% 67.88% # Class of committed instruction -system.cpu.op_class_0::SimdMultAcc 0 0.00% 67.88% # Class of committed instruction -system.cpu.op_class_0::SimdShift 0 0.00% 67.88% # Class of committed instruction -system.cpu.op_class_0::SimdShiftAcc 0 0.00% 67.88% # Class of committed instruction -system.cpu.op_class_0::SimdSqrt 0 0.00% 67.88% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAdd 0 0.00% 67.88% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAlu 0 0.00% 67.88% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCmp 0 0.00% 67.88% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCvt 0 0.00% 67.88% # Class of committed instruction -system.cpu.op_class_0::SimdFloatDiv 0 0.00% 67.88% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMisc 0 0.00% 67.88% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMult 0 0.00% 67.88% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 67.88% # Class of committed instruction -system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 67.88% # Class of committed instruction -system.cpu.op_class_0::MemRead 1191 18.57% 86.45% # Class of committed instruction -system.cpu.op_class_0::MemWrite 861 13.43% 99.88% # Class of committed instruction -system.cpu.op_class_0::FloatMemRead 1 0.02% 99.89% # Class of committed instruction -system.cpu.op_class_0::FloatMemWrite 7 0.11% 100.00% # Class of committed instruction -system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 6413 # Class of committed instruction -system.cpu.tickCycles 12644 # Number of cycles that the object actually ticked -system.cpu.idleCycles 69522 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 103.984752 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1990 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.775148 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 103.984752 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.025387 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.025387 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 151 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.041260 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4591 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4591 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1250 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1250 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 740 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 740 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1990 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1990 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1990 # number of overall hits -system.cpu.dcache.overall_hits::total 1990 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 96 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 96 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 125 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 125 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 221 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 221 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 221 # number of overall misses -system.cpu.dcache.overall_misses::total 221 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8545500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8545500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10429000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10429000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 18974500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 18974500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 18974500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 18974500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1346 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1346 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2211 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2211 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2211 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2211 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.071322 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.071322 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.144509 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.144509 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.099955 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.099955 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.099955 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.099955 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 89015.625000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 89015.625000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 83432 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 83432 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 85857.466063 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 85857.466063 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 85857.466063 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 85857.466063 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 52 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 52 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 52 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 52 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 52 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 96 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 96 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 169 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 169 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8449500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 8449500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6089500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6089500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14539000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 14539000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14539000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 14539000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.071322 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071322 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076436 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.076436 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076436 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.076436 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 88015.625000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 88015.625000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 83417.808219 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 83417.808219 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 86029.585799 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 86029.585799 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 86029.585799 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 86029.585799 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 175.153182 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 2322 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 364 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6.379121 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 175.153182 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.085524 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.085524 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 364 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 271 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.177734 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 5736 # Number of tag accesses -system.cpu.icache.tags.data_accesses 5736 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 2322 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 2322 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 2322 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 2322 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 2322 # number of overall hits -system.cpu.icache.overall_hits::total 2322 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 364 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses -system.cpu.icache.overall_misses::total 364 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 30317500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 30317500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 30317500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 30317500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 30317500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 30317500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2686 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2686 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2686 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2686 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2686 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2686 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.135517 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.135517 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.135517 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.135517 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.135517 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.135517 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 83289.835165 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 83289.835165 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 83289.835165 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 83289.835165 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 83289.835165 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 83289.835165 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 364 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 364 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 364 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 364 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 364 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 364 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29953500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 29953500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29953500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 29953500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29953500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 29953500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.135517 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.135517 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.135517 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.135517 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.135517 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.135517 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 82289.835165 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 82289.835165 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 82289.835165 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 82289.835165 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 82289.835165 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 82289.835165 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 279.180738 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 532 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.001880 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 175.152793 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 104.027945 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005345 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.003175 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.008520 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 532 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 422 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.016235 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4796 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4796 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits -system.cpu.l2cache.overall_hits::total 1 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 363 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 363 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 96 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 96 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 363 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 169 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 532 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 363 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 169 # number of overall misses -system.cpu.l2cache.overall_misses::total 532 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5980000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5980000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 29396000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 29396000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8304000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 8304000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 29396000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 14284000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 43680000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 29396000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 14284000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 43680000 # number of overall miss cycles -system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 364 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 364 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 96 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 96 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 364 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 169 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 533 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 364 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 169 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 533 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.997253 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.997253 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.997253 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.998124 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.997253 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.998124 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81917.808219 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81917.808219 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80980.716253 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80980.716253 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80980.716253 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84520.710059 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 82105.263158 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80980.716253 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84520.710059 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 82105.263158 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 363 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 363 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 96 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 96 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 363 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 169 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 532 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 363 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 532 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5250000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5250000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 25766000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 25766000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7344000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7344000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 25766000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12594000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 38360000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25766000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12594000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 38360000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.997253 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.997253 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.997253 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.998124 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.997253 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.998124 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71917.808219 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71917.808219 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70980.716253 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70980.716253 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70980.716253 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74520.710059 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72105.263158 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70980.716253 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74520.710059 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72105.263158 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 533 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 460 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 364 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 96 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 728 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 338 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1066 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23296 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 34112 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 533 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001876 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.043315 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 532 99.81% 99.81% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1 0.19% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 533 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 266500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 546000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 253500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 532 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 459 # Transaction distribution -system.membus.trans_dist::ReadExReq 73 # Transaction distribution -system.membus.trans_dist::ReadExResp 73 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 459 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1064 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1064 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34048 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 34048 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 532 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 532 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 532 # Request fanout histogram -system.membus.reqLayer0.occupancy 607500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 2825000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 6.9 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,825 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=DerivO3CPU -children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload -LFSTSize=1024 -LQEntries=32 -LSQCheckLoads=true -LSQDepCheckShift=4 -SQEntries=32 -SSITSize=1024 -activity=0 -backComSize=5 -branchPred=system.cpu.branchPred -cachePorts=200 -checker=Null -clk_domain=system.cpu_clk_domain -commitToDecodeDelay=1 -commitToFetchDelay=1 -commitToIEWDelay=1 -commitToRenameDelay=1 -commitWidth=8 -cpu_id=0 -decodeToFetchDelay=1 -decodeToRenameDelay=1 -decodeWidth=8 -default_p_state=UNDEFINED -dispatchWidth=8 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -fetchBufferSize=64 -fetchQueueSize=32 -fetchToDecodeDelay=1 -fetchTrapLatency=1 -fetchWidth=8 -forwardComSize=5 -fuPool=system.cpu.fuPool -function_trace=false -function_trace_start=0 -iewToCommitDelay=1 -iewToDecodeDelay=1 -iewToFetchDelay=1 -iewToRenameDelay=1 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -issueToExecuteDelay=1 -issueWidth=8 -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -needsTSO=false -numIQEntries=64 -numPhysCCRegs=0 -numPhysFloatRegs=256 -numPhysIntRegs=256 -numROBEntries=192 -numRobs=1 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -renameToDecodeDelay=1 -renameToFetchDelay=1 -renameToIEWDelay=2 -renameToROBDelay=1 -renameWidth=8 -simpoint_start_insts= -smtCommitPolicy=RoundRobin -smtFetchPolicy=SingleThread -smtIQPolicy=Partitioned -smtIQThreshold=100 -smtLSQPolicy=Partitioned -smtLSQThreshold=100 -smtNumFetchingThreads=1 -smtROBPolicy=Partitioned -smtROBThreshold=100 -socket_id=0 -squashWidth=8 -store_set_clear_period=250000 -switched_out=false -system=system -tracer=system.cpu.tracer -trapLatency=13 -wbWidth=8 -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.branchPred] -type=TournamentBP -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -indirectHashGHR=true -indirectHashTargets=true -indirectPathLength=3 -indirectSets=256 -indirectTagSize=16 -indirectWays=2 -instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 -useIndirect=true - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.fuPool] -type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 -eventq_index=0 - -[system.cpu.fuPool.FUList0] -type=FUDesc -children=opList -count=6 -eventq_index=0 -opList=system.cpu.fuPool.FUList0.opList - -[system.cpu.fuPool.FUList0.opList] -type=OpDesc -eventq_index=0 -opClass=IntAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList1] -type=FUDesc -children=opList0 opList1 -count=2 -eventq_index=0 -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -eventq_index=0 -opClass=IntMult -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -eventq_index=0 -opClass=IntDiv -opLat=20 -pipelined=false - -[system.cpu.fuPool.FUList2] -type=FUDesc -children=opList0 opList1 opList2 -count=4 -eventq_index=0 -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -eventq_index=0 -opClass=FloatAdd -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -eventq_index=0 -opClass=FloatCmp -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -eventq_index=0 -opClass=FloatCvt -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList3] -type=FUDesc -children=opList0 opList1 opList2 -count=2 -eventq_index=0 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -eventq_index=0 -opClass=FloatMult -opLat=4 -pipelined=true - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -eventq_index=0 -opClass=FloatDiv -opLat=12 -pipelined=false - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -eventq_index=0 -opClass=FloatSqrt -opLat=24 -pipelined=false - -[system.cpu.fuPool.FUList4] -type=FUDesc -children=opList -count=0 -eventq_index=0 -opList=system.cpu.fuPool.FUList4.opList - -[system.cpu.fuPool.FUList4.opList] -type=OpDesc -eventq_index=0 -opClass=MemRead -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5] -type=FUDesc -children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 -count=4 -eventq_index=0 -opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 - -[system.cpu.fuPool.FUList5.opList00] -type=OpDesc -eventq_index=0 -opClass=SimdAdd -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList01] -type=OpDesc -eventq_index=0 -opClass=SimdAddAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList02] -type=OpDesc -eventq_index=0 -opClass=SimdAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList03] -type=OpDesc -eventq_index=0 -opClass=SimdCmp -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList04] -type=OpDesc -eventq_index=0 -opClass=SimdCvt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList05] -type=OpDesc -eventq_index=0 -opClass=SimdMisc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList06] -type=OpDesc -eventq_index=0 -opClass=SimdMult -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList07] -type=OpDesc -eventq_index=0 -opClass=SimdMultAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList08] -type=OpDesc -eventq_index=0 -opClass=SimdShift -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList09] -type=OpDesc -eventq_index=0 -opClass=SimdShiftAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList10] -type=OpDesc -eventq_index=0 -opClass=SimdSqrt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList11] -type=OpDesc -eventq_index=0 -opClass=SimdFloatAdd -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList12] -type=OpDesc -eventq_index=0 -opClass=SimdFloatAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList13] -type=OpDesc -eventq_index=0 -opClass=SimdFloatCmp -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList14] -type=OpDesc -eventq_index=0 -opClass=SimdFloatCvt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList15] -type=OpDesc -eventq_index=0 -opClass=SimdFloatDiv -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList16] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMisc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList17] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMult -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList18] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMultAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList19] -type=OpDesc -eventq_index=0 -opClass=SimdFloatSqrt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList6] -type=FUDesc -children=opList -count=0 -eventq_index=0 -opList=system.cpu.fuPool.FUList6.opList - -[system.cpu.fuPool.FUList6.opList] -type=OpDesc -eventq_index=0 -opClass=MemWrite -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList7] -type=FUDesc -children=opList0 opList1 -count=4 -eventq_index=0 -opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -eventq_index=0 -opClass=MemRead -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList7.opList1] -type=OpDesc -eventq_index=0 -opClass=MemWrite -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList8] -type=FUDesc -children=opList -count=1 -eventq_index=0 -opList=system.cpu.fuPool.FUList8.opList - -[system.cpu.fuPool.FUList8.opList] -type=OpDesc -eventq_index=0 -opClass=IprAccess -opLat=3 -pipelined=false - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=hello -cwd= -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/linux/hello -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=0:134217727:0:0:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=6000 -tXPDLL=0 -tXS=270000 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simerr --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simerr Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,3 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,15 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:19:49 -gem5 executing on e108600-lin, pid 28099 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/linux/o3-timing - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Hello world! -Exiting @ tick 23776000 because target called exit() diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,1024 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000024 # Number of seconds simulated -sim_ticks 23776000 # Number of ticks simulated -final_tick 23776000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 139405 # Simulator instruction rate (inst/s) -host_op_rate 139373 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 518883929 # Simulator tick rate (ticks/s) -host_mem_usage 254032 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host -sim_insts 6385 # Number of instructions simulated -sim_ops 6385 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 19968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 11072 # Number of bytes read from this memory -system.physmem.bytes_read::total 31040 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 19968 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 19968 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 312 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 173 # Number of read requests responded to by this memory -system.physmem.num_reads::total 485 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 839838493 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 465679677 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1305518170 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 839838493 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 839838493 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 839838493 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 465679677 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1305518170 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 485 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 485 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 31040 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 31040 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 69 # Per bank write bursts -system.physmem.perBankRdBursts::1 32 # Per bank write bursts -system.physmem.perBankRdBursts::2 33 # Per bank write bursts -system.physmem.perBankRdBursts::3 47 # Per bank write bursts -system.physmem.perBankRdBursts::4 42 # Per bank write bursts -system.physmem.perBankRdBursts::5 20 # Per bank write bursts -system.physmem.perBankRdBursts::6 1 # Per bank write bursts -system.physmem.perBankRdBursts::7 3 # Per bank write bursts -system.physmem.perBankRdBursts::8 0 # Per bank write bursts -system.physmem.perBankRdBursts::9 1 # Per bank write bursts -system.physmem.perBankRdBursts::10 22 # Per bank write bursts -system.physmem.perBankRdBursts::11 25 # Per bank write bursts -system.physmem.perBankRdBursts::12 14 # Per bank write bursts -system.physmem.perBankRdBursts::13 118 # Per bank write bursts -system.physmem.perBankRdBursts::14 45 # Per bank write bursts -system.physmem.perBankRdBursts::15 13 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 23381000 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 485 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 260 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 141 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 21 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 89 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 348.044944 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 230.274346 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 313.082327 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 21 23.60% 23.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 22 24.72% 48.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 15 16.85% 65.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 9 10.11% 75.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 6 6.74% 82.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3 3.37% 85.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 2.25% 87.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1 1.12% 88.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10 11.24% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 89 # Bytes accessed per row activation -system.physmem.totQLat 8009750 # Total ticks spent queuing -system.physmem.totMemAccLat 17103500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2425000 # Total ticks spent in databus transfers -system.physmem.avgQLat 16514.95 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 35264.95 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1305.52 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1305.52 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 10.20 # Data bus utilization in percentage -system.physmem.busUtilRead 10.20 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.82 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 395 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.44 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 48208.25 # Average gap between requests -system.physmem.pageHitRate 81.44 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 242760 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 125235 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1763580 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3005040 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 47520 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 7623180 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 132480 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 14783715 # Total energy per rank (pJ) -system.physmem_0.averagePower 621.784975 # Core power per rank (mW) -system.physmem_0.totalIdleTime 16957250 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 40500 # Time in different power states -system.physmem_0.memoryStateTime::REF 780000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 0 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 344500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 5900500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 16710500 # Time in different power states -system.physmem_1.actEnergy 399840 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 212520 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1699320 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2978250 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 130080 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 7628310 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 68160 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 14960400 # Total energy per rank (pJ) -system.physmem_1.averagePower 629.216130 # Core power per rank (mW) -system.physmem_1.totalIdleTime 16769000 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 214000 # Time in different power states -system.physmem_1.memoryStateTime::REF 780000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 0 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 178500 # Time in different power states -system.physmem_1.memoryStateTime::ACT 5875500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 16728000 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 2854 # Number of BP lookups -system.cpu.branchPred.condPredicted 1681 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2203 # Number of BTB lookups -system.cpu.branchPred.BTBHits 713 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 32.364957 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 441 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 42 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 462 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 25 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 437 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 123 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 2252 # DTB read hits -system.cpu.dtb.read_misses 48 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 2300 # DTB read accesses -system.cpu.dtb.write_hits 1038 # DTB write hits -system.cpu.dtb.write_misses 28 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 1066 # DTB write accesses -system.cpu.dtb.data_hits 3290 # DTB hits -system.cpu.dtb.data_misses 76 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 3366 # DTB accesses -system.cpu.itb.fetch_hits 2295 # ITB hits -system.cpu.itb.fetch_misses 27 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2322 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 23776000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 47553 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8496 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 16559 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2854 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1179 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 5759 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1046 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 656 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2295 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 335 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 15456 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.071364 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.458774 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 12470 80.68% 80.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 297 1.92% 82.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 230 1.49% 84.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 258 1.67% 85.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 292 1.89% 87.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 234 1.51% 89.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 282 1.82% 90.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 146 0.94% 91.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1247 8.07% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 15456 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.060017 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.348222 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8339 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4008 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2446 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 214 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 449 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 226 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 75 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 15004 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 221 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 449 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8498 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1841 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 655 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2476 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1537 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 14448 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 21 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 10 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1471 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 10929 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 17896 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 17887 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 8 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 4577 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6352 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 28 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 22 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 585 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2834 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1292 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 18 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 6 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 13054 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 27 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 10776 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 17 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6695 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3669 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 15456 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.697205 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.442232 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11416 73.86% 73.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1297 8.39% 82.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 916 5.93% 88.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 681 4.41% 92.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 517 3.34% 95.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 347 2.25% 98.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 200 1.29% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 55 0.36% 99.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 27 0.17% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 15456 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 21 14.89% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.89% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 83 58.87% 73.76% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 36 25.53% 99.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 0 0.00% 99.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 1 0.71% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7185 66.68% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2474 22.96% 89.68% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1104 10.24% 99.93% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 1 0.01% 99.94% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 7 0.06% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10776 # Type of FU issued -system.cpu.iq.rate 0.226610 # Inst issue rate -system.cpu.iq.fu_busy_cnt 141 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013085 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 37145 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 19787 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 9745 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 10904 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 119 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1649 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 23 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 427 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 78 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 449 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1429 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 338 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 13165 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 125 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2834 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1292 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 331 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 23 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 107 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 390 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 497 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 10290 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2300 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 486 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 84 # number of nop insts executed -system.cpu.iew.exec_refs 3376 # number of memory reference insts executed -system.cpu.iew.exec_branches 1642 # Number of branches executed -system.cpu.iew.exec_stores 1076 # Number of stores executed -system.cpu.iew.exec_rate 0.216390 # Inst execution rate -system.cpu.iew.wb_sent 9948 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 9755 # cumulative count of insts written-back -system.cpu.iew.wb_producers 5155 # num instructions producing a value -system.cpu.iew.wb_consumers 7025 # num instructions consuming a value -system.cpu.iew.wb_rate 0.205140 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.733808 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 6712 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 408 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 14219 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.450243 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.361136 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 11792 82.93% 82.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1158 8.14% 91.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 469 3.30% 94.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 205 1.44% 95.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 133 0.94% 96.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 85 0.60% 97.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 97 0.68% 98.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 88 0.62% 98.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 192 1.35% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 14219 # Number of insts commited each cycle -system.cpu.commit.committedInsts 6402 # Number of instructions committed -system.cpu.commit.committedOps 6402 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 2050 # Number of memory references committed -system.cpu.commit.loads 1185 # Number of loads committed -system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 1056 # Number of branches committed -system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. -system.cpu.commit.int_insts 6319 # Number of committed integer instructions. -system.cpu.commit.function_calls 127 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 19 0.30% 0.30% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 4330 67.64% 67.93% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 1 0.02% 67.95% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 67.95% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 2 0.03% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 1184 18.49% 86.47% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 858 13.40% 99.88% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemRead 1 0.02% 99.89% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemWrite 7 0.11% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 6402 # Class of committed instruction -system.cpu.commit.bw_lim_events 192 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 26790 # The number of ROB reads -system.cpu.rob.rob_writes 27482 # The number of ROB writes -system.cpu.timesIdled 250 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 32097 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 6385 # Number of Instructions Simulated -system.cpu.committedOps 6385 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.447612 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.447612 # CPI: Total CPI of All Threads -system.cpu.ipc 0.134271 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.134271 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12923 # number of integer regfile reads -system.cpu.int_regfile_writes 7437 # number of integer regfile writes -system.cpu.fp_regfile_reads 8 # number of floating regfile reads -system.cpu.fp_regfile_writes 2 # number of floating regfile writes -system.cpu.misc_regfile_reads 1 # number of misc regfile reads -system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 110.182603 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2402 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 173 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.884393 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 110.182603 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.026900 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.026900 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 173 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.042236 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 6051 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 6051 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1894 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1894 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 508 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 508 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2402 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2402 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2402 # number of overall hits -system.cpu.dcache.overall_hits::total 2402 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 180 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 180 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 357 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 357 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 537 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 537 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 537 # number of overall misses -system.cpu.dcache.overall_misses::total 537 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 13953000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 13953000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 31158482 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 31158482 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 45111482 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 45111482 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 45111482 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 45111482 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 2074 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 2074 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2939 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2939 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2939 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2939 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086789 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.086789 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.412717 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.412717 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.182715 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.182715 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.182715 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.182715 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77516.666667 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 77516.666667 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 87278.661064 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 87278.661064 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 84006.484171 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 84006.484171 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 84006.484171 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 84006.484171 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 3098 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 37 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 83.729730 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 79 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 79 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 285 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 285 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 364 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 364 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 364 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 364 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 101 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 72 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 173 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9401500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9401500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7013500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7013500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16415000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16415000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16415000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16415000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.048698 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.048698 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.058864 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.058864 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.058864 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.058864 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 93084.158416 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 93084.158416 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 97409.722222 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 97409.722222 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 94884.393064 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 94884.393064 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 94884.393064 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 94884.393064 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 160.538154 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1837 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 313 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.869010 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 160.538154 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.078388 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.078388 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 313 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 187 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.152832 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4903 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4903 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 1837 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1837 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1837 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1837 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1837 # number of overall hits -system.cpu.icache.overall_hits::total 1837 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 458 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 458 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 458 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 458 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 458 # number of overall misses -system.cpu.icache.overall_misses::total 458 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 35507500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 35507500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 35507500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 35507500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 35507500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 35507500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2295 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2295 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2295 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2295 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2295 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2295 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.199564 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.199564 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.199564 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.199564 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.199564 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.199564 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77527.292576 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 77527.292576 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 77527.292576 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 77527.292576 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 77527.292576 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 77527.292576 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 67 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 67 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 145 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 145 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 145 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 145 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 145 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 145 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 313 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 313 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 313 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 313 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 313 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26275500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 26275500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26275500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 26275500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26275500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 26275500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.136383 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.136383 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.136383 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.136383 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.136383 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.136383 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83947.284345 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83947.284345 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83947.284345 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 83947.284345 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83947.284345 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 83947.284345 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 270.818986 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 485 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.002062 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 160.559983 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 110.259003 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004900 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.003365 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.008265 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 485 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 167 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 318 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014801 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4373 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4373 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits -system.cpu.l2cache.overall_hits::total 1 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 72 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 72 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 312 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 312 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 101 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 101 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 312 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 173 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 485 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 312 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 173 # number of overall misses -system.cpu.l2cache.overall_misses::total 485 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6902500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6902500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25792500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 25792500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 9241500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 9241500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 25792500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 16144000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 41936500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 25792500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 16144000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 41936500 # number of overall miss cycles -system.cpu.l2cache.ReadExReq_accesses::cpu.data 72 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 72 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 313 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 313 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 101 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 101 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 313 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 173 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 486 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 313 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 173 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 486 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996805 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996805 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996805 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.997942 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996805 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.997942 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 95868.055556 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 95868.055556 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82668.269231 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82668.269231 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 91500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 91500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82668.269231 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93317.919075 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 86467.010309 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82668.269231 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93317.919075 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 86467.010309 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 72 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 72 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 312 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 312 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 101 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 101 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 312 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 173 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 485 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 312 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 485 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6182500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6182500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22672500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22672500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 8231500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 8231500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22672500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14414000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 37086500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22672500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14414000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 37086500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996805 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997942 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997942 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 85868.055556 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 85868.055556 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72668.269231 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72668.269231 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 81500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 81500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72668.269231 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83317.919075 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76467.010309 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72668.269231 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83317.919075 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76467.010309 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 486 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 414 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 313 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 101 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 626 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 346 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 972 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20032 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11072 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 31104 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 486 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.002058 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.045361 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 485 99.79% 99.79% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1 0.21% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 486 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 243000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 469500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 259500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 485 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 413 # Transaction distribution -system.membus.trans_dist::ReadExReq 72 # Transaction distribution -system.membus.trans_dist::ReadExResp 72 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 413 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 970 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 970 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 31040 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 485 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 485 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 485 # Request fanout histogram -system.membus.reqLayer0.occupancy 595000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 2572250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 10.8 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,203 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=atomic -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=AtomicSimpleCPU -children=dtb interrupts isa itb tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -fastmem=false -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -simulate_data_stalls=false -simulate_inst_stalls=false -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -width=1 -workload=system.cpu.workload -dcache_port=system.membus.slave[2] -icache_port=system.membus.slave[1] - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=hello -cwd= -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/linux/hello -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=Null -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.icache_port system.cpu.dcache_port - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=0:134217727 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simerr --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simerr Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,2 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,15 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 19 2016 12:24:27 -gem5 executing on e108600-lin, pid 39609 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/linux/simple-atomic - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Hello world! -Exiting @ tick 3214500 because target called exit() diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,167 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000003 # Number of seconds simulated -sim_ticks 3214500 # Number of ticks simulated -final_tick 3214500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1072411 # Simulator instruction rate (inst/s) -host_op_rate 1070683 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 536687952 # Simulator tick rate (ticks/s) -host_mem_usage 241476 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -sim_insts 6403 # Number of instructions simulated -sim_ops 6403 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 3214500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 25652 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8804 # Number of bytes read from this memory -system.physmem.bytes_read::total 34456 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 25652 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 25652 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 6696 # Number of bytes written to this memory -system.physmem.bytes_written::total 6696 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 6413 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1185 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7598 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 865 # Number of write requests responded to by this memory -system.physmem.num_writes::total 865 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7980090216 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2738839633 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10718929849 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7980090216 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7980090216 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 2083061129 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2083061129 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7980090216 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4821900762 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 12801990978 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 3214500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1185 # DTB read hits -system.cpu.dtb.read_misses 7 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 1192 # DTB read accesses -system.cpu.dtb.write_hits 865 # DTB write hits -system.cpu.dtb.write_misses 3 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 868 # DTB write accesses -system.cpu.dtb.data_hits 2050 # DTB hits -system.cpu.dtb.data_misses 10 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 2060 # DTB accesses -system.cpu.itb.fetch_hits 6413 # ITB hits -system.cpu.itb.fetch_misses 17 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 6430 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 3214500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 6430 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 6403 # Number of instructions committed -system.cpu.committedOps 6403 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 6329 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses -system.cpu.num_func_calls 251 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 754 # number of instructions that are conditional controls -system.cpu.num_int_insts 6329 # number of integer instructions -system.cpu.num_fp_insts 10 # number of float instructions -system.cpu.num_int_register_reads 8297 # number of times the integer registers were read -system.cpu.num_int_register_writes 4575 # number of times the integer registers were written -system.cpu.num_fp_register_reads 8 # number of times the floating registers were read -system.cpu.num_fp_register_writes 2 # number of times the floating registers were written -system.cpu.num_mem_refs 2060 # number of memory refs -system.cpu.num_load_insts 1192 # Number of load instructions -system.cpu.num_store_insts 868 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 6430 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 1056 # Number of branches fetched -system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction -system.cpu.op_class::IntAlu 4331 67.53% 67.83% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.02% 67.85% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 67.85% # Class of executed instruction -system.cpu.op_class::FloatAdd 2 0.03% 67.88% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::MemRead 1191 18.57% 86.45% # Class of executed instruction -system.cpu.op_class::MemWrite 861 13.43% 99.88% # Class of executed instruction -system.cpu.op_class::FloatMemRead 1 0.02% 99.89% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 7 0.11% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 6413 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 3214500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 7598 # Transaction distribution -system.membus.trans_dist::ReadResp 7598 # Transaction distribution -system.membus.trans_dist::WriteReq 865 # Transaction distribution -system.membus.trans_dist::WriteResp 865 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 12826 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 4100 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 16926 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 25652 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 15500 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 41152 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 8463 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 8463 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 8463 # Request fanout histogram - ----------- End Simulation Statistics ---------- diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,1456 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000 -time_sync_spin_threshold=100000 - -[system] -type=System -children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges=0:268435455:0:0:0:0 -memories=system.mem_ctrls -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.sys_port_proxy.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=TimingSimpleCPU -children=clk_domain dtb interrupts isa itb tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu.clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1] -icache_port=system.ruby.l1_cntrl0.sequencer.slave[0] - -[system.cpu.clk_domain] -type=SrcClockDomain -clock=1 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=hello -cwd= -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/linux/hello -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000 - -[system.mem_ctrls] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -page_policy=open_adaptive -power_model=Null -range=0:268435455:5:19:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10 -static_frontend_latency=10 -tBURST=5 -tCCD_L=0 -tCK=1 -tCL=14 -tCS=3 -tRAS=35 -tRCD=14 -tREFI=7800 -tRFC=260 -tRP=14 -tRRD=6 -tRRD_L=0 -tRTP=8 -tRTW=3 -tWR=15 -tWTR=8 -tXAW=30 -tXP=6 -tXPDLL=0 -tXS=270 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.ruby.dir_cntrl0.memory - -[system.ruby] -type=RubySystem -children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network -access_backing_store=false -all_instructions=false -block_size_bytes=64 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hot_lines=false -memory_size_bits=48 -num_of_sequencers=1 -number_of_virtual_networks=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -phys_mem=Null -power_model=Null -randomization=false - -[system.ruby.clk_domain] -type=SrcClockDomain -clock=1 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.ruby.dir_cntrl0] -type=Directory_Controller -children=directory requestToDir responseFromDir responseFromMemory responseToDir -buffer_size=0 -clk_domain=system.ruby.clk_domain -cluster_id=0 -default_p_state=UNDEFINED -directory=system.ruby.dir_cntrl0.directory -directory_latency=6 -eventq_index=0 -number_of_TBEs=256 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -recycle_latency=10 -requestToDir=system.ruby.dir_cntrl0.requestToDir -responseFromDir=system.ruby.dir_cntrl0.responseFromDir -responseFromMemory=system.ruby.dir_cntrl0.responseFromMemory -responseToDir=system.ruby.dir_cntrl0.responseToDir -ruby_system=system.ruby -system=system -to_mem_ctrl_latency=1 -transitions_per_cycle=4 -version=0 -memory=system.mem_ctrls.port - -[system.ruby.dir_cntrl0.directory] -type=RubyDirectoryMemory -eventq_index=0 -numa_high_bit=5 -size=268435456 -version=0 - -[system.ruby.dir_cntrl0.requestToDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[5] - -[system.ruby.dir_cntrl0.responseFromDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[6] - -[system.ruby.dir_cntrl0.responseFromMemory] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false - -[system.ruby.dir_cntrl0.responseToDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[6] - -[system.ruby.l1_cntrl0] -type=L1Cache_Controller -children=L1Dcache L1Icache mandatoryQueue optionalQueue prefetcher requestFromL1Cache requestToL1Cache responseFromL1Cache responseToL1Cache sequencer unblockFromL1Cache -L1Dcache=system.ruby.l1_cntrl0.L1Dcache -L1Icache=system.ruby.l1_cntrl0.L1Icache -buffer_size=0 -clk_domain=system.cpu.clk_domain -cluster_id=0 -default_p_state=UNDEFINED -enable_prefetch=false -eventq_index=0 -l1_request_latency=2 -l1_response_latency=2 -l2_select_num_bits=0 -mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue -number_of_TBEs=256 -optionalQueue=system.ruby.l1_cntrl0.optionalQueue -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -prefetcher=system.ruby.l1_cntrl0.prefetcher -recycle_latency=10 -requestFromL1Cache=system.ruby.l1_cntrl0.requestFromL1Cache -requestToL1Cache=system.ruby.l1_cntrl0.requestToL1Cache -responseFromL1Cache=system.ruby.l1_cntrl0.responseFromL1Cache -responseToL1Cache=system.ruby.l1_cntrl0.responseToL1Cache -ruby_system=system.ruby -send_evictions=false -sequencer=system.ruby.l1_cntrl0.sequencer -system=system -to_l2_latency=1 -transitions_per_cycle=4 -unblockFromL1Cache=system.ruby.l1_cntrl0.unblockFromL1Cache -version=0 - -[system.ruby.l1_cntrl0.L1Dcache] -type=RubyCache -children=replacement_policy -assoc=2 -block_size=0 -dataAccessLatency=1 -dataArrayBanks=1 -eventq_index=0 -is_icache=false -replacement_policy=system.ruby.l1_cntrl0.L1Dcache.replacement_policy -resourceStalls=false -ruby_system=system.ruby -size=256 -start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 - -[system.ruby.l1_cntrl0.L1Dcache.replacement_policy] -type=PseudoLRUReplacementPolicy -assoc=2 -block_size=64 -eventq_index=0 -size=256 - -[system.ruby.l1_cntrl0.L1Icache] -type=RubyCache -children=replacement_policy -assoc=2 -block_size=0 -dataAccessLatency=1 -dataArrayBanks=1 -eventq_index=0 -is_icache=true -replacement_policy=system.ruby.l1_cntrl0.L1Icache.replacement_policy -resourceStalls=false -ruby_system=system.ruby -size=256 -start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 - -[system.ruby.l1_cntrl0.L1Icache.replacement_policy] -type=PseudoLRUReplacementPolicy -assoc=2 -block_size=64 -eventq_index=0 -size=256 - -[system.ruby.l1_cntrl0.mandatoryQueue] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false - -[system.ruby.l1_cntrl0.optionalQueue] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false - -[system.ruby.l1_cntrl0.prefetcher] -type=Prefetcher -cross_page=false -eventq_index=0 -nonunit_filter=8 -num_startup_pfs=1 -num_streams=4 -pf_per_stream=1 -sys=system -train_misses=4 -unit_filter=8 - -[system.ruby.l1_cntrl0.requestFromL1Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[0] - -[system.ruby.l1_cntrl0.requestToL1Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[0] - -[system.ruby.l1_cntrl0.responseFromL1Cache] -type=MessageBuffer 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-[system.ruby.l2_cntrl0.L2cache.replacement_policy] -type=PseudoLRUReplacementPolicy -assoc=2 -block_size=64 -eventq_index=0 -size=512 - -[system.ruby.l2_cntrl0.responseFromL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[5] - -[system.ruby.l2_cntrl0.responseToL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[4] - -[system.ruby.l2_cntrl0.unblockToL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[2] - -[system.ruby.memctrl_clk_domain] -type=DerivedClockDomain -clk_divider=3 -clk_domain=system.ruby.clk_domain -eventq_index=0 - -[system.ruby.network] -type=SimpleNetwork -children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 routers0 routers1 routers2 routers3 -adaptive_routing=false -buffer_size=0 -clk_domain=system.ruby.clk_domain -control_msg_size=8 -default_p_state=UNDEFINED -endpoint_bandwidth=1000 -eventq_index=0 -ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2 -int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 -int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4 system.ruby.network.int_links5 -netifs= -number_of_virtual_networks=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 system.ruby.network.routers3 -ruby_system=system.ruby -topology=Crossbar -master=system.ruby.l1_cntrl0.requestToL1Cache.slave system.ruby.l1_cntrl0.responseToL1Cache.slave system.ruby.l2_cntrl0.unblockToL2Cache.slave system.ruby.l2_cntrl0.L1RequestToL2Cache.slave system.ruby.l2_cntrl0.responseToL2Cache.slave system.ruby.dir_cntrl0.requestToDir.slave system.ruby.dir_cntrl0.responseToDir.slave -slave=system.ruby.l1_cntrl0.requestFromL1Cache.master system.ruby.l1_cntrl0.responseFromL1Cache.master system.ruby.l1_cntrl0.unblockFromL1Cache.master system.ruby.l2_cntrl0.DirRequestFromL2Cache.master system.ruby.l2_cntrl0.L1RequestFromL2Cache.master system.ruby.l2_cntrl0.responseFromL2Cache.master system.ruby.dir_cntrl0.responseFromDir.master - -[system.ruby.network.ext_links0] -type=SimpleExtLink -bandwidth_factor=16 -eventq_index=0 -ext_node=system.ruby.l1_cntrl0 -int_node=system.ruby.network.routers0 -latency=1 -link_id=0 -weight=1 - -[system.ruby.network.ext_links1] -type=SimpleExtLink -bandwidth_factor=16 -eventq_index=0 -ext_node=system.ruby.l2_cntrl0 -int_node=system.ruby.network.routers1 -latency=1 -link_id=1 -weight=1 - -[system.ruby.network.ext_links2] -type=SimpleExtLink -bandwidth_factor=16 -eventq_index=0 -ext_node=system.ruby.dir_cntrl0 -int_node=system.ruby.network.routers2 -latency=1 -link_id=2 -weight=1 - -[system.ruby.network.int_link_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers06] 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-src_node=system.ruby.network.routers3 -src_outport= -weight=1 - -[system.ruby.network.int_links5] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers2 -eventq_index=0 -latency=1 -link_id=8 -src_node=system.ruby.network.routers3 -src_outport= -weight=1 - -[system.ruby.network.routers0] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 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-children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 -power_model=Null -router_id=1 -virt_nets=3 - -[system.ruby.network.routers1.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 -power_model=Null -router_id=2 -virt_nets=3 - -[system.ruby.network.routers2.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers3.port_buffers00 system.ruby.network.routers3.port_buffers01 system.ruby.network.routers3.port_buffers02 system.ruby.network.routers3.port_buffers03 system.ruby.network.routers3.port_buffers04 system.ruby.network.routers3.port_buffers05 system.ruby.network.routers3.port_buffers06 system.ruby.network.routers3.port_buffers07 system.ruby.network.routers3.port_buffers08 system.ruby.network.routers3.port_buffers09 system.ruby.network.routers3.port_buffers10 system.ruby.network.routers3.port_buffers11 system.ruby.network.routers3.port_buffers12 system.ruby.network.routers3.port_buffers13 system.ruby.network.routers3.port_buffers14 system.ruby.network.routers3.port_buffers15 system.ruby.network.routers3.port_buffers16 system.ruby.network.routers3.port_buffers17 -power_model=Null -router_id=3 -virt_nets=3 - -[system.ruby.network.routers3.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers15] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers16] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers17] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.sys_port_proxy] -type=RubyPortProxy -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_cpu_sequencer=true -no_retry_on_stall=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -ruby_system=system.ruby -support_data_reqs=true -support_inst_reqs=true -system=system -using_ruby_tester=false -version=0 -slave=system.system_port - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simerr --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simerr Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,10 +0,0 @@ -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simout --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simout Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,15 +0,0 @@ -Redirecting stdout to build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level/simout -Redirecting stderr to build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 13 2016 20:28:06 -gem5 started Oct 13 2016 20:28:31 -gem5 executing on e108600-lin, pid 8233 -command line: /work/curdun01/gem5-external.hg/build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level - -Global frequency set at 1000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Hello world! -Exiting @ tick 129075 because target called exit() diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,764 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000129 # Number of seconds simulated -sim_ticks 129075 # Number of ticks simulated -final_tick 129075 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 77143 # Simulator instruction rate (inst/s) -host_op_rate 77134 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1554751 # Simulator tick rate (ticks/s) -host_mem_usage 412952 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host -sim_insts 6403 # Number of instructions simulated -sim_ops 6403 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 129075 # Cumulative time (in ticks) in various power states -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 93504 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 93504 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 17728 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 17728 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 1461 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 1461 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 277 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 277 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 724416037 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 724416037 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 137346504 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 137346504 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 861762541 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 861762541 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 1461 # Number of read requests accepted -system.mem_ctrls.writeReqs 277 # Number of write requests accepted -system.mem_ctrls.readBursts 1461 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 277 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 74368 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 19136 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 6400 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 93504 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 17728 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 299 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 160 # Number of DRAM write bursts merged with an existing one -system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 102 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 61 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 90 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 90 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 101 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 22 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 1 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 4 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::9 1 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 78 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 75 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 26 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 395 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 67 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 49 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 24 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 7 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 7 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 21 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 41 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts -system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 128982 # Total gap between requests -system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 1461 # Read request sizes (log2) -system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 277 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 1162 # 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does an incoming req see -system.mem_ctrls.wrQLenPdf::16 3 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 215 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 364.055814 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 222.075931 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 347.859995 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 60 27.91% 27.91% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 55 25.58% 53.49% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 24 11.16% 64.65% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 15 6.98% 71.63% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 8 3.72% 75.35% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 9 4.19% 79.53% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 8 3.72% 83.26% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 5 2.33% 85.58% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 31 14.42% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 215 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 6 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 193.166667 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 134.817545 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 132.906609 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-31 1 16.67% 16.67% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::64-79 1 16.67% 33.33% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::192-207 1 16.67% 50.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::224-239 1 16.67% 66.67% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::240-255 1 16.67% 83.33% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::384-399 1 16.67% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 6 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 6 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.666667 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.640671 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 1.032796 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 4 66.67% 66.67% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 2 33.33% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 6 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 15493 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 37571 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 5810 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 13.33 # Average queueing delay per DRAM burst -system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 32.33 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 576.16 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 49.58 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 724.42 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 137.35 # Average system write bandwidth in MiByte/s -system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 4.89 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 4.50 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 0.39 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 22.78 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 949 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 91 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 81.67 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 77.78 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 74.21 # Average gap between requests -system.mem_ctrls.pageHitRate 81.31 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 514080 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 270480 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 5380704 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 258912 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 9834240.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 8608824 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 320256 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.actPowerDownEnergy 37409784 # Energy for active power-down per rank (pJ) -system.mem_ctrls_0.prePowerDownEnergy 6725376 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_0.selfRefreshEnergy 2906400 # Energy for self refresh per rank (pJ) -system.mem_ctrls_0.totalEnergy 72229056 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 559.589820 # Core power per rank (mW) -system.mem_ctrls_0.totalIdleTime 109312 # Total Idle time Per DRAM Rank -system.mem_ctrls_0.memoryStateTime::IDLE 366 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 4166 # Time in different power states -system.mem_ctrls_0.memoryStateTime::SREF 9809 # Time in different power states -system.mem_ctrls_0.memoryStateTime::PRE_PDN 17514 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 15181 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 82039 # Time in different power states -system.mem_ctrls_1.actEnergy 1071000 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 560280 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 7893984 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 576288 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 9834240.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 12597000 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 372480 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.actPowerDownEnergy 45058272 # Energy for active power-down per rank (pJ) -system.mem_ctrls_1.prePowerDownEnergy 640512 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrls_1.totalEnergy 78604056 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 608.979709 # Core power per rank (mW) -system.mem_ctrls_1.totalIdleTime 100248 # Total Idle time Per DRAM Rank -system.mem_ctrls_1.memoryStateTime::IDLE 270 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 4160 # Time in different power states -system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 1668 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 24165 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT_PDN 98812 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 129075 # Cumulative time (in ticks) in various power states -system.cpu.clk_domain.clock 1 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1185 # DTB read hits -system.cpu.dtb.read_misses 7 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 1192 # DTB read accesses -system.cpu.dtb.write_hits 865 # DTB write hits -system.cpu.dtb.write_misses 3 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 868 # DTB write accesses -system.cpu.dtb.data_hits 2050 # DTB hits -system.cpu.dtb.data_misses 10 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 2060 # DTB accesses -system.cpu.itb.fetch_hits 6414 # ITB hits -system.cpu.itb.fetch_misses 17 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 6431 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 129075 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 129075 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 6403 # Number of instructions committed -system.cpu.committedOps 6403 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 6329 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses -system.cpu.num_func_calls 251 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 754 # number of instructions that are conditional controls -system.cpu.num_int_insts 6329 # number of integer instructions -system.cpu.num_fp_insts 10 # number of float instructions -system.cpu.num_int_register_reads 8297 # number of times the integer registers were read -system.cpu.num_int_register_writes 4575 # number of times the integer registers were written -system.cpu.num_fp_register_reads 8 # number of times the floating registers were read -system.cpu.num_fp_register_writes 2 # number of times the floating registers were written -system.cpu.num_mem_refs 2060 # number of memory refs -system.cpu.num_load_insts 1192 # Number of load instructions -system.cpu.num_store_insts 868 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 129075 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 1056 # Number of branches fetched -system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction -system.cpu.op_class::IntAlu 4331 67.53% 67.83% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.02% 67.85% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 67.85% # Class of executed instruction -system.cpu.op_class::FloatAdd 2 0.03% 67.88% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::MemRead 1191 18.57% 86.45% # Class of executed instruction -system.cpu.op_class::MemWrite 861 13.43% 99.88% # Class of executed instruction -system.cpu.op_class::FloatMemRead 1 0.02% 99.89% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 7 0.11% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 6413 # Class of executed instruction -system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.pwrStateResidencyTicks::UNDEFINED 129075 # Cumulative time (in ticks) in various power states -system.ruby.delayHist::bucket_size 1 # delay histogram for all message -system.ruby.delayHist::max_bucket 9 # delay histogram for all message -system.ruby.delayHist::samples 9652 # delay histogram for all message -system.ruby.delayHist::mean 0.163697 # delay histogram for all message -system.ruby.delayHist::stdev 1.010840 # delay histogram for all message -system.ruby.delayHist | 9297 96.32% 96.32% | 0 0.00% 96.32% | 210 2.18% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 145 1.50% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 9652 # delay histogram for all message -system.ruby.outstanding_req_hist_seqr::bucket_size 1 -system.ruby.outstanding_req_hist_seqr::max_bucket 9 -system.ruby.outstanding_req_hist_seqr::samples 8464 -system.ruby.outstanding_req_hist_seqr::mean 1 -system.ruby.outstanding_req_hist_seqr::gmean 1 -system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 8464 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist_seqr::total 8464 -system.ruby.latency_hist_seqr::bucket_size 64 -system.ruby.latency_hist_seqr::max_bucket 639 -system.ruby.latency_hist_seqr::samples 8463 -system.ruby.latency_hist_seqr::mean 14.251684 -system.ruby.latency_hist_seqr::gmean 2.119385 -system.ruby.latency_hist_seqr::stdev 32.289040 -system.ruby.latency_hist_seqr | 7301 86.27% 86.27% | 1142 13.49% 99.76% | 3 0.04% 99.80% | 1 0.01% 99.81% | 6 0.07% 99.88% | 9 0.11% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% -system.ruby.latency_hist_seqr::total 8463 -system.ruby.hit_latency_hist_seqr::bucket_size 1 -system.ruby.hit_latency_hist_seqr::max_bucket 9 -system.ruby.hit_latency_hist_seqr::samples 6972 -system.ruby.hit_latency_hist_seqr::mean 1 -system.ruby.hit_latency_hist_seqr::gmean 1 -system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 6972 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist_seqr::total 6972 -system.ruby.miss_latency_hist_seqr::bucket_size 64 -system.ruby.miss_latency_hist_seqr::max_bucket 639 -system.ruby.miss_latency_hist_seqr::samples 1491 -system.ruby.miss_latency_hist_seqr::mean 76.217304 -system.ruby.miss_latency_hist_seqr::gmean 71.053455 -system.ruby.miss_latency_hist_seqr::stdev 35.454362 -system.ruby.miss_latency_hist_seqr | 329 22.07% 22.07% | 1142 76.59% 98.66% | 3 0.20% 98.86% | 1 0.07% 98.93% | 6 0.40% 99.33% | 9 0.60% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 1 0.07% 100.00% -system.ruby.miss_latency_hist_seqr::total 1491 -system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 129075 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.L1Dcache.demand_hits 1250 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 800 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2050 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Icache.demand_hits 5722 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Icache.demand_misses 691 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Icache.demand_accesses 6413 # Number of cache demand accesses -system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed -system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching -system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made -system.ruby.l1_cntrl0.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted -system.ruby.l1_cntrl0.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped -system.ruby.l1_cntrl0.prefetcher.hits 0 # number of prefetched blocks accessed -system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched -system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages -system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 129075 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 129075 # Cumulative time (in ticks) in various power states -system.ruby.l2_cntrl0.L2cache.demand_hits 30 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 1461 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 1491 # Number of cache demand accesses -system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 129075 # Cumulative time (in ticks) in various power states -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 129075 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.percent_links_utilized 4.058493 -system.ruby.network.routers0.msg_count.Control::0 1491 -system.ruby.network.routers0.msg_count.Request_Control::2 1041 -system.ruby.network.routers0.msg_count.Response_Data::1 1491 -system.ruby.network.routers0.msg_count.Response_Control::1 1337 -system.ruby.network.routers0.msg_count.Response_Control::2 800 -system.ruby.network.routers0.msg_count.Writeback_Data::0 145 -system.ruby.network.routers0.msg_count.Writeback_Data::1 141 -system.ruby.network.routers0.msg_count.Writeback_Control::0 292 -system.ruby.network.routers0.msg_bytes.Control::0 11928 -system.ruby.network.routers0.msg_bytes.Request_Control::2 8328 -system.ruby.network.routers0.msg_bytes.Response_Data::1 107352 -system.ruby.network.routers0.msg_bytes.Response_Control::1 10696 -system.ruby.network.routers0.msg_bytes.Response_Control::2 6400 -system.ruby.network.routers0.msg_bytes.Writeback_Data::0 10440 -system.ruby.network.routers0.msg_bytes.Writeback_Data::1 10152 -system.ruby.network.routers0.msg_bytes.Writeback_Control::0 2336 -system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 129075 # Cumulative time (in ticks) in various power states -system.ruby.network.routers1.percent_links_utilized 7.880302 -system.ruby.network.routers1.msg_count.Control::0 2952 -system.ruby.network.routers1.msg_count.Request_Control::2 1041 -system.ruby.network.routers1.msg_count.Response_Data::1 3229 -system.ruby.network.routers1.msg_count.Response_Control::1 3966 -system.ruby.network.routers1.msg_count.Response_Control::2 800 -system.ruby.network.routers1.msg_count.Writeback_Data::0 145 -system.ruby.network.routers1.msg_count.Writeback_Data::1 141 -system.ruby.network.routers1.msg_count.Writeback_Control::0 292 -system.ruby.network.routers1.msg_bytes.Control::0 23616 -system.ruby.network.routers1.msg_bytes.Request_Control::2 8328 -system.ruby.network.routers1.msg_bytes.Response_Data::1 232488 -system.ruby.network.routers1.msg_bytes.Response_Control::1 31728 -system.ruby.network.routers1.msg_bytes.Response_Control::2 6400 -system.ruby.network.routers1.msg_bytes.Writeback_Data::0 10440 -system.ruby.network.routers1.msg_bytes.Writeback_Data::1 10152 -system.ruby.network.routers1.msg_bytes.Writeback_Control::0 2336 -system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 129075 # Cumulative time (in ticks) in various power states -system.ruby.network.routers2.percent_links_utilized 3.821809 -system.ruby.network.routers2.msg_count.Control::0 1461 -system.ruby.network.routers2.msg_count.Response_Data::1 1738 -system.ruby.network.routers2.msg_count.Response_Control::1 2629 -system.ruby.network.routers2.msg_bytes.Control::0 11688 -system.ruby.network.routers2.msg_bytes.Response_Data::1 125136 -system.ruby.network.routers2.msg_bytes.Response_Control::1 21032 -system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 129075 # Cumulative time (in ticks) in various power states -system.ruby.network.routers3.percent_links_utilized 5.253535 -system.ruby.network.routers3.msg_count.Control::0 2952 -system.ruby.network.routers3.msg_count.Request_Control::2 1041 -system.ruby.network.routers3.msg_count.Response_Data::1 3229 -system.ruby.network.routers3.msg_count.Response_Control::1 3966 -system.ruby.network.routers3.msg_count.Response_Control::2 800 -system.ruby.network.routers3.msg_count.Writeback_Data::0 145 -system.ruby.network.routers3.msg_count.Writeback_Data::1 141 -system.ruby.network.routers3.msg_count.Writeback_Control::0 292 -system.ruby.network.routers3.msg_bytes.Control::0 23616 -system.ruby.network.routers3.msg_bytes.Request_Control::2 8328 -system.ruby.network.routers3.msg_bytes.Response_Data::1 232488 -system.ruby.network.routers3.msg_bytes.Response_Control::1 31728 -system.ruby.network.routers3.msg_bytes.Response_Control::2 6400 -system.ruby.network.routers3.msg_bytes.Writeback_Data::0 10440 -system.ruby.network.routers3.msg_bytes.Writeback_Data::1 10152 -system.ruby.network.routers3.msg_bytes.Writeback_Control::0 2336 -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 129075 # Cumulative time (in ticks) in various power states -system.ruby.network.msg_count.Control 8856 -system.ruby.network.msg_count.Request_Control 3123 -system.ruby.network.msg_count.Response_Data 9687 -system.ruby.network.msg_count.Response_Control 14298 -system.ruby.network.msg_count.Writeback_Data 858 -system.ruby.network.msg_count.Writeback_Control 876 -system.ruby.network.msg_byte.Control 70848 -system.ruby.network.msg_byte.Request_Control 24984 -system.ruby.network.msg_byte.Response_Data 697464 -system.ruby.network.msg_byte.Response_Control 114384 -system.ruby.network.msg_byte.Writeback_Data 61776 -system.ruby.network.msg_byte.Writeback_Control 7008 -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 129075 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.throttle0.link_utilization 5.770676 -system.ruby.network.routers0.throttle0.msg_count.Request_Control::2 1041 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 1491 -system.ruby.network.routers0.throttle0.msg_count.Response_Control::1 437 -system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::2 8328 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1 107352 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1 3496 -system.ruby.network.routers0.throttle1.link_utilization 2.346310 -system.ruby.network.routers0.throttle1.msg_count.Control::0 1491 -system.ruby.network.routers0.throttle1.msg_count.Response_Control::1 900 -system.ruby.network.routers0.throttle1.msg_count.Response_Control::2 800 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::0 145 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::1 141 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 292 -system.ruby.network.routers0.throttle1.msg_bytes.Control::0 11928 -system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::1 7200 -system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2 6400 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0 10440 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1 10152 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 2336 -system.ruby.network.routers1.throttle0.link_utilization 8.002712 -system.ruby.network.routers1.throttle0.msg_count.Control::0 1491 -system.ruby.network.routers1.throttle0.msg_count.Response_Data::1 1461 -system.ruby.network.routers1.throttle0.msg_count.Response_Control::1 2353 -system.ruby.network.routers1.throttle0.msg_count.Response_Control::2 800 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::0 145 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::1 141 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0 292 -system.ruby.network.routers1.throttle0.msg_bytes.Control::0 11928 -system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::1 105192 -system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::1 18824 -system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::2 6400 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::0 10440 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::1 10152 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 2336 -system.ruby.network.routers1.throttle1.link_utilization 7.757893 -system.ruby.network.routers1.throttle1.msg_count.Control::0 1461 -system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 1041 -system.ruby.network.routers1.throttle1.msg_count.Response_Data::1 1768 -system.ruby.network.routers1.throttle1.msg_count.Response_Control::1 1613 -system.ruby.network.routers1.throttle1.msg_bytes.Control::0 11688 -system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2 8328 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1 127296 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1 12904 -system.ruby.network.routers2.throttle0.link_utilization 1.987217 -system.ruby.network.routers2.throttle0.msg_count.Control::0 1461 -system.ruby.network.routers2.throttle0.msg_count.Response_Data::1 277 -system.ruby.network.routers2.throttle0.msg_count.Response_Control::1 1176 -system.ruby.network.routers2.throttle0.msg_bytes.Control::0 11688 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1 19944 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1 9408 -system.ruby.network.routers2.throttle1.link_utilization 5.656401 -system.ruby.network.routers2.throttle1.msg_count.Response_Data::1 1461 -system.ruby.network.routers2.throttle1.msg_count.Response_Control::1 1453 -system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1 105192 -system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1 11624 -system.ruby.network.routers3.throttle0.link_utilization 5.770676 -system.ruby.network.routers3.throttle0.msg_count.Request_Control::2 1041 -system.ruby.network.routers3.throttle0.msg_count.Response_Data::1 1491 -system.ruby.network.routers3.throttle0.msg_count.Response_Control::1 437 -system.ruby.network.routers3.throttle0.msg_bytes.Request_Control::2 8328 -system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1 107352 -system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1 3496 -system.ruby.network.routers3.throttle1.link_utilization 8.002712 -system.ruby.network.routers3.throttle1.msg_count.Control::0 1491 -system.ruby.network.routers3.throttle1.msg_count.Response_Data::1 1461 -system.ruby.network.routers3.throttle1.msg_count.Response_Control::1 2353 -system.ruby.network.routers3.throttle1.msg_count.Response_Control::2 800 -system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::0 145 -system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::1 141 -system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::0 292 -system.ruby.network.routers3.throttle1.msg_bytes.Control::0 11928 -system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::1 105192 -system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::1 18824 -system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::2 6400 -system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::0 10440 -system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::1 10152 -system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 2336 -system.ruby.network.routers3.throttle2.link_utilization 1.987217 -system.ruby.network.routers3.throttle2.msg_count.Control::0 1461 -system.ruby.network.routers3.throttle2.msg_count.Response_Data::1 277 -system.ruby.network.routers3.throttle2.msg_count.Response_Control::1 1176 -system.ruby.network.routers3.throttle2.msg_bytes.Control::0 11688 -system.ruby.network.routers3.throttle2.msg_bytes.Response_Data::1 19944 -system.ruby.network.routers3.throttle2.msg_bytes.Response_Control::1 9408 -system.ruby.delayVCHist.vnet_0::bucket_size 1 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::max_bucket 9 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::samples 2728 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::mean 0.425220 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::stdev 1.795029 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0 | 2583 94.68% 94.68% | 0 0.00% 94.68% | 0 0.00% 94.68% | 0 0.00% 94.68% | 0 0.00% 94.68% | 0 0.00% 94.68% | 0 0.00% 94.68% | 0 0.00% 94.68% | 145 5.32% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::total 2728 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::samples 5883 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::mean 0.071392 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::stdev 0.371094 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1 | 5673 96.43% 96.43% | 0 0.00% 96.43% | 210 3.57% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::total 5883 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::samples 1041 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2 | 1041 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::total 1041 # delay histogram for vnet_2 -system.ruby.LD.latency_hist_seqr::bucket_size 64 -system.ruby.LD.latency_hist_seqr::max_bucket 639 -system.ruby.LD.latency_hist_seqr::samples 1185 -system.ruby.LD.latency_hist_seqr::mean 36.416034 -system.ruby.LD.latency_hist_seqr::gmean 7.907367 -system.ruby.LD.latency_hist_seqr::stdev 46.041898 -system.ruby.LD.latency_hist_seqr | 802 67.68% 67.68% | 375 31.65% 99.32% | 1 0.08% 99.41% | 0 0.00% 99.41% | 3 0.25% 99.66% | 3 0.25% 99.92% | 0 0.00% 99.92% | 0 0.00% 99.92% | 0 0.00% 99.92% | 1 0.08% 100.00% -system.ruby.LD.latency_hist_seqr::total 1185 -system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 -system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 -system.ruby.LD.hit_latency_hist_seqr::samples 601 -system.ruby.LD.hit_latency_hist_seqr::mean 1 -system.ruby.LD.hit_latency_hist_seqr::gmean 1 -system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 601 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist_seqr::total 601 -system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 -system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 -system.ruby.LD.miss_latency_hist_seqr::samples 584 -system.ruby.LD.miss_latency_hist_seqr::mean 72.863014 -system.ruby.LD.miss_latency_hist_seqr::gmean 66.405671 -system.ruby.LD.miss_latency_hist_seqr::stdev 41.005857 -system.ruby.LD.miss_latency_hist_seqr | 201 34.42% 34.42% | 375 64.21% 98.63% | 1 0.17% 98.80% | 0 0.00% 98.80% | 3 0.51% 99.32% | 3 0.51% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 1 0.17% 100.00% -system.ruby.LD.miss_latency_hist_seqr::total 584 -system.ruby.ST.latency_hist_seqr::bucket_size 16 -system.ruby.ST.latency_hist_seqr::max_bucket 159 -system.ruby.ST.latency_hist_seqr::samples 865 -system.ruby.ST.latency_hist_seqr::mean 15.646243 -system.ruby.ST.latency_hist_seqr::gmean 2.719887 -system.ruby.ST.latency_hist_seqr::stdev 27.764380 -system.ruby.ST.latency_hist_seqr | 649 75.03% 75.03% | 12 1.39% 76.42% | 101 11.68% 88.09% | 10 1.16% 89.25% | 36 4.16% 93.41% | 52 6.01% 99.42% | 4 0.46% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist_seqr::total 865 -system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 -system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 -system.ruby.ST.hit_latency_hist_seqr::samples 649 -system.ruby.ST.hit_latency_hist_seqr::mean 1 -system.ruby.ST.hit_latency_hist_seqr::gmean 1 -system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 649 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist_seqr::total 649 -system.ruby.ST.miss_latency_hist_seqr::bucket_size 16 -system.ruby.ST.miss_latency_hist_seqr::max_bucket 159 -system.ruby.ST.miss_latency_hist_seqr::samples 216 -system.ruby.ST.miss_latency_hist_seqr::mean 59.652778 -system.ruby.ST.miss_latency_hist_seqr::gmean 54.981344 -system.ruby.ST.miss_latency_hist_seqr::stdev 22.464955 -system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 12 5.56% 5.56% | 101 46.76% 52.31% | 10 4.63% 56.94% | 36 16.67% 73.61% | 52 24.07% 97.69% | 4 1.85% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist_seqr::total 216 -system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 -system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.latency_hist_seqr::samples 6413 -system.ruby.IFETCH.latency_hist_seqr::mean 9.968034 -system.ruby.IFETCH.latency_hist_seqr::gmean 1.606700 -system.ruby.IFETCH.latency_hist_seqr::stdev 27.770381 -system.ruby.IFETCH.latency_hist_seqr | 5727 89.30% 89.30% | 674 10.51% 99.81% | 2 0.03% 99.84% | 1 0.02% 99.86% | 3 0.05% 99.91% | 6 0.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist_seqr::total 6413 -system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 -system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 -system.ruby.IFETCH.hit_latency_hist_seqr::samples 5722 -system.ruby.IFETCH.hit_latency_hist_seqr::mean 1 -system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 -system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 5722 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist_seqr::total 5722 -system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 -system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.miss_latency_hist_seqr::samples 691 -system.ruby.IFETCH.miss_latency_hist_seqr::mean 84.230101 -system.ruby.IFETCH.miss_latency_hist_seqr::gmean 81.513388 -system.ruby.IFETCH.miss_latency_hist_seqr::stdev 31.252511 -system.ruby.IFETCH.miss_latency_hist_seqr | 5 0.72% 0.72% | 674 97.54% 98.26% | 2 0.29% 98.55% | 1 0.14% 98.70% | 3 0.43% 99.13% | 6 0.87% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.miss_latency_hist_seqr::total 691 -system.ruby.Directory_Controller.Fetch 1461 0.00% 0.00% -system.ruby.Directory_Controller.Data 277 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 1461 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 277 0.00% 0.00% -system.ruby.Directory_Controller.CleanReplacement 1176 0.00% 0.00% -system.ruby.Directory_Controller.I.Fetch 1461 0.00% 0.00% -system.ruby.Directory_Controller.M.Data 277 0.00% 0.00% -system.ruby.Directory_Controller.M.CleanReplacement 1176 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 1461 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 277 0.00% 0.00% -system.ruby.L1Cache_Controller.Load 1185 0.00% 0.00% -system.ruby.L1Cache_Controller.Ifetch 6413 0.00% 0.00% -system.ruby.L1Cache_Controller.Store 865 0.00% 0.00% -system.ruby.L1Cache_Controller.Inv 1041 0.00% 0.00% -system.ruby.L1Cache_Controller.L1_Replacement 1355 0.00% 0.00% -system.ruby.L1Cache_Controller.Data_Exclusive 584 0.00% 0.00% -system.ruby.L1Cache_Controller.Data_all_Acks 907 0.00% 0.00% -system.ruby.L1Cache_Controller.WB_Ack 437 0.00% 0.00% -system.ruby.L1Cache_Controller.NP.Load 526 0.00% 0.00% -system.ruby.L1Cache_Controller.NP.Ifetch 646 0.00% 0.00% -system.ruby.L1Cache_Controller.NP.Store 191 0.00% 0.00% -system.ruby.L1Cache_Controller.NP.Inv 356 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Load 58 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Ifetch 45 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Store 25 0.00% 0.00% -system.ruby.L1Cache_Controller.I.L1_Replacement 556 0.00% 0.00% -system.ruby.L1Cache_Controller.S.Ifetch 5722 0.00% 0.00% -system.ruby.L1Cache_Controller.S.Inv 325 0.00% 0.00% -system.ruby.L1Cache_Controller.S.L1_Replacement 362 0.00% 0.00% -system.ruby.L1Cache_Controller.E.Load 453 0.00% 0.00% -system.ruby.L1Cache_Controller.E.Store 71 0.00% 0.00% -system.ruby.L1Cache_Controller.E.Inv 219 0.00% 0.00% -system.ruby.L1Cache_Controller.E.L1_Replacement 292 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Load 148 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Store 578 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Inv 141 0.00% 0.00% -system.ruby.L1Cache_Controller.M.L1_Replacement 145 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Data_Exclusive 584 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Data_all_Acks 691 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.Data_all_Acks 216 0.00% 0.00% -system.ruby.L1Cache_Controller.M_I.WB_Ack 437 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GET_INSTR 691 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETS 584 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETX 216 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTX 437 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement 142 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement_clean 1311 0.00% 0.00% -system.ruby.L2Cache_Controller.Mem_Data 1461 0.00% 0.00% -system.ruby.L2Cache_Controller.Mem_Ack 1453 0.00% 0.00% -system.ruby.L2Cache_Controller.WB_Data 141 0.00% 0.00% -system.ruby.L2Cache_Controller.Ack_all 900 0.00% 0.00% -system.ruby.L2Cache_Controller.Exclusive_Unblock 800 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GET_INSTR 686 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETS 571 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETX 204 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GET_INSTR 5 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 681 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETS 13 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETX 12 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement 134 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement_clean 278 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_PUTX 437 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L2_Replacement 8 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 352 0.00% 0.00% -system.ruby.L2Cache_Controller.M_I.Mem_Ack 1453 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_I.WB_Data 6 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_I.Ack_all 2 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.WB_Data 135 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.Ack_all 217 0.00% 0.00% -system.ruby.L2Cache_Controller.I_I.Ack_all 681 0.00% 0.00% -system.ruby.L2Cache_Controller.ISS.Mem_Data 571 0.00% 0.00% -system.ruby.L2Cache_Controller.IS.Mem_Data 686 0.00% 0.00% -system.ruby.L2Cache_Controller.IM.Mem_Data 204 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 800 0.00% 0.00% - ----------- End Simulation Statistics ---------- diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,1448 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000 -time_sync_spin_threshold=100000 - -[system] -type=System -children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges=0:268435455:0:0:0:0 -memories=system.mem_ctrls -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.sys_port_proxy.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=TimingSimpleCPU -children=clk_domain dtb interrupts isa itb tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu.clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1] -icache_port=system.ruby.l1_cntrl0.sequencer.slave[0] - -[system.cpu.clk_domain] -type=SrcClockDomain -clock=1 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=hello -cwd= -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/linux/hello -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000 - -[system.mem_ctrls] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -page_policy=open_adaptive -power_model=Null -range=0:268435455:5:19:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10 -static_frontend_latency=10 -tBURST=5 -tCCD_L=0 -tCK=1 -tCL=14 -tCS=3 -tRAS=35 -tRCD=14 -tREFI=7800 -tRFC=260 -tRP=14 -tRRD=6 -tRRD_L=0 -tRTP=8 -tRTW=3 -tWR=15 -tWTR=8 -tXAW=30 -tXP=6 -tXPDLL=0 -tXS=270 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.ruby.dir_cntrl0.memory - -[system.ruby] -type=RubySystem -children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network -access_backing_store=false -all_instructions=false -block_size_bytes=64 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hot_lines=false -memory_size_bits=48 -num_of_sequencers=1 -number_of_virtual_networks=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -phys_mem=Null -power_model=Null -randomization=false - -[system.ruby.clk_domain] -type=SrcClockDomain -clock=1 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.ruby.dir_cntrl0] -type=Directory_Controller -children=directory forwardFromDir requestToDir responseFromDir responseFromMemory responseToDir -buffer_size=0 -clk_domain=system.ruby.clk_domain -cluster_id=0 -default_p_state=UNDEFINED -directory=system.ruby.dir_cntrl0.directory -directory_latency=6 -eventq_index=0 -forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir -number_of_TBEs=256 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -recycle_latency=10 -requestToDir=system.ruby.dir_cntrl0.requestToDir -responseFromDir=system.ruby.dir_cntrl0.responseFromDir -responseFromMemory=system.ruby.dir_cntrl0.responseFromMemory -responseToDir=system.ruby.dir_cntrl0.responseToDir -ruby_system=system.ruby -system=system -to_memory_controller_latency=1 -transitions_per_cycle=4 -version=0 -memory=system.mem_ctrls.port - -[system.ruby.dir_cntrl0.directory] -type=RubyDirectoryMemory -eventq_index=0 -numa_high_bit=5 -size=268435456 -version=0 - -[system.ruby.dir_cntrl0.forwardFromDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[6] - -[system.ruby.dir_cntrl0.requestToDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[5] - -[system.ruby.dir_cntrl0.responseFromDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[5] - -[system.ruby.dir_cntrl0.responseFromMemory] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false - -[system.ruby.dir_cntrl0.responseToDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[6] - -[system.ruby.l1_cntrl0] -type=L1Cache_Controller -children=L1Dcache L1Icache mandatoryQueue requestFromL1Cache requestToL1Cache responseFromL1Cache responseToL1Cache sequencer triggerQueue -L1Dcache=system.ruby.l1_cntrl0.L1Dcache -L1Icache=system.ruby.l1_cntrl0.L1Icache -buffer_size=0 -clk_domain=system.cpu.clk_domain -cluster_id=0 -default_p_state=UNDEFINED -eventq_index=0 -l2_select_num_bits=0 -mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue -number_of_TBEs=256 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -recycle_latency=10 -requestFromL1Cache=system.ruby.l1_cntrl0.requestFromL1Cache -requestToL1Cache=system.ruby.l1_cntrl0.requestToL1Cache -request_latency=2 -responseFromL1Cache=system.ruby.l1_cntrl0.responseFromL1Cache -responseToL1Cache=system.ruby.l1_cntrl0.responseToL1Cache -ruby_system=system.ruby -send_evictions=false -sequencer=system.ruby.l1_cntrl0.sequencer -system=system -transitions_per_cycle=4 -triggerQueue=system.ruby.l1_cntrl0.triggerQueue -use_timeout_latency=50 -version=0 - -[system.ruby.l1_cntrl0.L1Dcache] -type=RubyCache -children=replacement_policy -assoc=2 -block_size=0 -dataAccessLatency=1 -dataArrayBanks=1 -eventq_index=0 -is_icache=false -replacement_policy=system.ruby.l1_cntrl0.L1Dcache.replacement_policy -resourceStalls=false -ruby_system=system.ruby -size=256 -start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 - -[system.ruby.l1_cntrl0.L1Dcache.replacement_policy] -type=PseudoLRUReplacementPolicy -assoc=2 -block_size=64 -eventq_index=0 -size=256 - -[system.ruby.l1_cntrl0.L1Icache] -type=RubyCache -children=replacement_policy -assoc=2 -block_size=0 -dataAccessLatency=1 -dataArrayBanks=1 -eventq_index=0 -is_icache=true -replacement_policy=system.ruby.l1_cntrl0.L1Icache.replacement_policy -resourceStalls=false -ruby_system=system.ruby -size=256 -start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 - -[system.ruby.l1_cntrl0.L1Icache.replacement_policy] -type=PseudoLRUReplacementPolicy -assoc=2 -block_size=64 -eventq_index=0 -size=256 - -[system.ruby.l1_cntrl0.mandatoryQueue] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false - -[system.ruby.l1_cntrl0.requestFromL1Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[0] - -[system.ruby.l1_cntrl0.requestToL1Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[0] - -[system.ruby.l1_cntrl0.responseFromL1Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[1] - -[system.ruby.l1_cntrl0.responseToL1Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[1] - -[system.ruby.l1_cntrl0.sequencer] -type=RubySequencer -clk_domain=system.cpu.clk_domain -coreid=99 -dcache=system.ruby.l1_cntrl0.L1Dcache -dcache_hit_latency=1 -deadlock_threshold=500000 -default_p_state=UNDEFINED -eventq_index=0 -garnet_standalone=false -icache=system.ruby.l1_cntrl0.L1Icache -icache_hit_latency=1 -is_cpu_sequencer=true -max_outstanding_requests=16 -no_retry_on_stall=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -ruby_system=system.ruby -support_data_reqs=true -support_inst_reqs=true -system=system -using_ruby_tester=false -version=0 -slave=system.cpu.icache_port system.cpu.dcache_port - -[system.ruby.l1_cntrl0.triggerQueue] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.l2_cntrl0] -type=L2Cache_Controller -children=GlobalRequestFromL2Cache GlobalRequestToL2Cache L1RequestFromL2Cache L1RequestToL2Cache L2cache responseFromL2Cache responseToL2Cache triggerQueue -GlobalRequestFromL2Cache=system.ruby.l2_cntrl0.GlobalRequestFromL2Cache -GlobalRequestToL2Cache=system.ruby.l2_cntrl0.GlobalRequestToL2Cache -L1RequestFromL2Cache=system.ruby.l2_cntrl0.L1RequestFromL2Cache -L1RequestToL2Cache=system.ruby.l2_cntrl0.L1RequestToL2Cache -L2cache=system.ruby.l2_cntrl0.L2cache -buffer_size=0 -clk_domain=system.ruby.clk_domain -cluster_id=0 -default_p_state=UNDEFINED -eventq_index=0 -number_of_TBEs=256 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -recycle_latency=10 -request_latency=2 -responseFromL2Cache=system.ruby.l2_cntrl0.responseFromL2Cache -responseToL2Cache=system.ruby.l2_cntrl0.responseToL2Cache -response_latency=2 -ruby_system=system.ruby -system=system -transitions_per_cycle=4 -triggerQueue=system.ruby.l2_cntrl0.triggerQueue -version=0 - -[system.ruby.l2_cntrl0.GlobalRequestFromL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[2] - -[system.ruby.l2_cntrl0.GlobalRequestToL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[2] - -[system.ruby.l2_cntrl0.L1RequestFromL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[3] - -[system.ruby.l2_cntrl0.L1RequestToL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[3] - -[system.ruby.l2_cntrl0.L2cache] -type=RubyCache -children=replacement_policy -assoc=2 -block_size=0 -dataAccessLatency=1 -dataArrayBanks=1 -eventq_index=0 -is_icache=false -replacement_policy=system.ruby.l2_cntrl0.L2cache.replacement_policy -resourceStalls=false -ruby_system=system.ruby -size=512 -start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 - -[system.ruby.l2_cntrl0.L2cache.replacement_policy] -type=PseudoLRUReplacementPolicy -assoc=2 -block_size=64 -eventq_index=0 -size=512 - -[system.ruby.l2_cntrl0.responseFromL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[4] - -[system.ruby.l2_cntrl0.responseToL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[4] - -[system.ruby.l2_cntrl0.triggerQueue] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.memctrl_clk_domain] -type=DerivedClockDomain -clk_divider=3 -clk_domain=system.ruby.clk_domain -eventq_index=0 - -[system.ruby.network] -type=SimpleNetwork -children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 routers0 routers1 routers2 routers3 -adaptive_routing=false -buffer_size=0 -clk_domain=system.ruby.clk_domain -control_msg_size=8 -default_p_state=UNDEFINED -endpoint_bandwidth=1000 -eventq_index=0 -ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2 -int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 -int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4 system.ruby.network.int_links5 -netifs= -number_of_virtual_networks=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 system.ruby.network.routers3 -ruby_system=system.ruby -topology=Crossbar -master=system.ruby.l1_cntrl0.requestToL1Cache.slave system.ruby.l1_cntrl0.responseToL1Cache.slave system.ruby.l2_cntrl0.GlobalRequestToL2Cache.slave system.ruby.l2_cntrl0.L1RequestToL2Cache.slave system.ruby.l2_cntrl0.responseToL2Cache.slave system.ruby.dir_cntrl0.requestToDir.slave system.ruby.dir_cntrl0.responseToDir.slave -slave=system.ruby.l1_cntrl0.requestFromL1Cache.master system.ruby.l1_cntrl0.responseFromL1Cache.master system.ruby.l2_cntrl0.GlobalRequestFromL2Cache.master system.ruby.l2_cntrl0.L1RequestFromL2Cache.master system.ruby.l2_cntrl0.responseFromL2Cache.master system.ruby.dir_cntrl0.responseFromDir.master system.ruby.dir_cntrl0.forwardFromDir.master - -[system.ruby.network.ext_links0] -type=SimpleExtLink -bandwidth_factor=16 -eventq_index=0 -ext_node=system.ruby.l1_cntrl0 -int_node=system.ruby.network.routers0 -latency=1 -link_id=0 -weight=1 - -[system.ruby.network.ext_links1] -type=SimpleExtLink -bandwidth_factor=16 -eventq_index=0 -ext_node=system.ruby.l2_cntrl0 -int_node=system.ruby.network.routers1 -latency=1 -link_id=1 -weight=1 - -[system.ruby.network.ext_links2] -type=SimpleExtLink -bandwidth_factor=16 -eventq_index=0 -ext_node=system.ruby.dir_cntrl0 -int_node=system.ruby.network.routers2 -latency=1 -link_id=2 -weight=1 - -[system.ruby.network.int_link_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers15] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers16] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers17] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers18] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers19] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers20] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers21] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers22] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers23] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers24] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers25] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers26] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers27] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers28] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers29] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers30] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers31] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers32] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers33] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers34] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers35] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_links0] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers3 -eventq_index=0 -latency=1 -link_id=3 -src_node=system.ruby.network.routers0 -src_outport= -weight=1 - -[system.ruby.network.int_links1] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers3 -eventq_index=0 -latency=1 -link_id=4 -src_node=system.ruby.network.routers1 -src_outport= -weight=1 - -[system.ruby.network.int_links2] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers3 -eventq_index=0 -latency=1 -link_id=5 -src_node=system.ruby.network.routers2 -src_outport= -weight=1 - -[system.ruby.network.int_links3] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers0 -eventq_index=0 -latency=1 -link_id=6 -src_node=system.ruby.network.routers3 -src_outport= -weight=1 - -[system.ruby.network.int_links4] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers1 -eventq_index=0 -latency=1 -link_id=7 -src_node=system.ruby.network.routers3 -src_outport= -weight=1 - -[system.ruby.network.int_links5] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers2 -eventq_index=0 -latency=1 -link_id=8 -src_node=system.ruby.network.routers3 -src_outport= -weight=1 - -[system.ruby.network.routers0] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 -power_model=Null -router_id=0 -virt_nets=3 - -[system.ruby.network.routers0.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 -power_model=Null -router_id=1 -virt_nets=3 - -[system.ruby.network.routers1.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 -power_model=Null -router_id=2 -virt_nets=3 - -[system.ruby.network.routers2.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers3.port_buffers00 system.ruby.network.routers3.port_buffers01 system.ruby.network.routers3.port_buffers02 system.ruby.network.routers3.port_buffers03 system.ruby.network.routers3.port_buffers04 system.ruby.network.routers3.port_buffers05 system.ruby.network.routers3.port_buffers06 system.ruby.network.routers3.port_buffers07 system.ruby.network.routers3.port_buffers08 system.ruby.network.routers3.port_buffers09 system.ruby.network.routers3.port_buffers10 system.ruby.network.routers3.port_buffers11 system.ruby.network.routers3.port_buffers12 system.ruby.network.routers3.port_buffers13 system.ruby.network.routers3.port_buffers14 system.ruby.network.routers3.port_buffers15 system.ruby.network.routers3.port_buffers16 system.ruby.network.routers3.port_buffers17 -power_model=Null -router_id=3 -virt_nets=3 - -[system.ruby.network.routers3.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers15] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers16] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers17] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.sys_port_proxy] -type=RubyPortProxy -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_cpu_sequencer=true -no_retry_on_stall=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -ruby_system=system.ruby -support_data_reqs=true -support_inst_reqs=true -system=system -using_ruby_tester=false -version=0 -slave=system.system_port - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,10 +0,0 @@ -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,15 +0,0 @@ -Redirecting stdout to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout -Redirecting stderr to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 13 2016 20:30:58 -gem5 started Oct 13 2016 20:31:25 -gem5 executing on e108600-lin, pid 17789 -command line: /work/curdun01/gem5-external.hg/build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory - -Global frequency set at 1000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Hello world! -Exiting @ tick 115948 because target called exit() diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,756 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000116 # Number of seconds simulated -sim_ticks 115948 # Number of ticks simulated -final_tick 115948 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 73551 # Simulator instruction rate (inst/s) -host_op_rate 73543 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1331606 # Simulator tick rate (ticks/s) -host_mem_usage 419184 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host -sim_insts 6403 # Number of instructions simulated -sim_ops 6403 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 115948 # Cumulative time (in ticks) in various power states -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 75712 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 75712 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 12416 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 12416 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 1183 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 1183 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 194 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 194 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 652982371 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 652982371 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 107082485 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 107082485 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 760064857 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 760064857 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 1183 # Number of read requests accepted -system.mem_ctrls.writeReqs 194 # Number of write requests accepted -system.mem_ctrls.readBursts 1183 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 194 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 65152 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 10560 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 5440 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 75712 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 12416 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 165 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 79 # Number of DRAM write bursts merged with an existing one -system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 83 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 51 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 81 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 75 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 99 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 18 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 2 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 3 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::9 1 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 56 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 51 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 21 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 367 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 69 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 41 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 19 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 3 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 20 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 43 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts -system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 115890 # Total gap between requests -system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 1183 # Read request sizes (log2) -system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 194 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 1018 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::12 0 # 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req see -system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 3 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 4 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 5 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 5 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 5 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see 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an incoming req see -system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 208 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 330.153846 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 204.681326 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 325.358480 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 61 29.33% 29.33% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 54 25.96% 55.29% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 30 14.42% 69.71% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 9 4.33% 74.04% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 16 7.69% 81.73% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 5 2.40% 84.13% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 5 2.40% 86.54% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 4 1.92% 88.46% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 24 11.54% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 208 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 5 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 142.600000 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 108.227176 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 79.531755 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-23 1 20.00% 20.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::128-135 1 20.00% 40.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::136-143 1 20.00% 60.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::200-207 1 20.00% 80.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::216-223 1 20.00% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 5 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 5 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 17 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.976446 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 1 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 2 40.00% 40.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 1 20.00% 60.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 2 40.00% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 5 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 13845 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 33187 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 5090 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 13.60 # Average queueing delay per DRAM burst -system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 32.60 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 561.91 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 46.92 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 652.98 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 107.08 # Average system write bandwidth in MiByte/s -system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 4.76 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 4.39 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 0.37 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 21.83 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 811 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 78 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 79.67 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 67.83 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 84.16 # Average gap between requests -system.mem_ctrls.pageHitRate 78.46 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 528360 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 278208 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 4706688 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 158688 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 9219600.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 8177904 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 299520 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.actPowerDownEnergy 33992976 # Energy for active power-down per rank (pJ) -system.mem_ctrls_0.prePowerDownEnergy 6547200 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_0.selfRefreshEnergy 1905360 # Energy for self refresh per rank (pJ) -system.mem_ctrls_0.totalEnergy 65814504 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 567.620865 # Core power per rank (mW) -system.mem_ctrls_0.totalIdleTime 97183 # Total Idle time Per DRAM Rank -system.mem_ctrls_0.memoryStateTime::IDLE 354 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 3906 # Time in different power states -system.mem_ctrls_0.memoryStateTime::SREF 5638 # Time in different power states -system.mem_ctrls_0.memoryStateTime::PRE_PDN 17050 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 14454 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 74546 # Time in different power states -system.mem_ctrls_1.actEnergy 999600 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 525504 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 6922944 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 551232 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 8604960.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 10734696 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 319488 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.actPowerDownEnergy 40821120 # Energy for active power-down per rank (pJ) -system.mem_ctrls_1.prePowerDownEnergy 789120 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrls_1.totalEnergy 70268664 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 606.036016 # Core power per rank (mW) -system.mem_ctrls_1.totalIdleTime 91295 # Total Idle time Per DRAM Rank -system.mem_ctrls_1.memoryStateTime::IDLE 272 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 3640 # Time in different power states -system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 2055 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 20461 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT_PDN 89520 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 115948 # Cumulative time (in ticks) in various power states -system.cpu.clk_domain.clock 1 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1185 # DTB read hits -system.cpu.dtb.read_misses 7 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 1192 # DTB read accesses -system.cpu.dtb.write_hits 865 # DTB write hits -system.cpu.dtb.write_misses 3 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 868 # DTB write accesses -system.cpu.dtb.data_hits 2050 # DTB hits -system.cpu.dtb.data_misses 10 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 2060 # DTB accesses -system.cpu.itb.fetch_hits 6414 # ITB hits -system.cpu.itb.fetch_misses 17 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 6431 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 115948 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 115948 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 6403 # Number of instructions committed -system.cpu.committedOps 6403 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 6329 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses -system.cpu.num_func_calls 251 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 754 # number of instructions that are conditional controls -system.cpu.num_int_insts 6329 # number of integer instructions -system.cpu.num_fp_insts 10 # number of float instructions -system.cpu.num_int_register_reads 8297 # number of times the integer registers were read -system.cpu.num_int_register_writes 4575 # number of times the integer registers were written -system.cpu.num_fp_register_reads 8 # number of times the floating registers were read -system.cpu.num_fp_register_writes 2 # number of times the floating registers were written -system.cpu.num_mem_refs 2060 # number of memory refs -system.cpu.num_load_insts 1192 # Number of load instructions -system.cpu.num_store_insts 868 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 115948 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 1056 # Number of branches fetched -system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction -system.cpu.op_class::IntAlu 4331 67.53% 67.83% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.02% 67.85% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 67.85% # Class of executed instruction -system.cpu.op_class::FloatAdd 2 0.03% 67.88% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::MemRead 1191 18.57% 86.45% # Class of executed instruction -system.cpu.op_class::MemWrite 861 13.43% 99.88% # Class of executed instruction -system.cpu.op_class::FloatMemRead 1 0.02% 99.89% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 7 0.11% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 6413 # Class of executed instruction -system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.pwrStateResidencyTicks::UNDEFINED 115948 # Cumulative time (in ticks) in various power states -system.ruby.outstanding_req_hist_seqr::bucket_size 1 -system.ruby.outstanding_req_hist_seqr::max_bucket 9 -system.ruby.outstanding_req_hist_seqr::samples 8464 -system.ruby.outstanding_req_hist_seqr::mean 1 -system.ruby.outstanding_req_hist_seqr::gmean 1 -system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 8464 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist_seqr::total 8464 -system.ruby.latency_hist_seqr::bucket_size 64 -system.ruby.latency_hist_seqr::max_bucket 639 -system.ruby.latency_hist_seqr::samples 8463 -system.ruby.latency_hist_seqr::mean 12.700579 -system.ruby.latency_hist_seqr::gmean 1.992540 -system.ruby.latency_hist_seqr::stdev 30.668579 -system.ruby.latency_hist_seqr | 7444 87.96% 87.96% | 1001 11.83% 99.79% | 3 0.04% 99.82% | 0 0.00% 99.82% | 6 0.07% 99.89% | 8 0.09% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% -system.ruby.latency_hist_seqr::total 8463 -system.ruby.hit_latency_hist_seqr::bucket_size 1 -system.ruby.hit_latency_hist_seqr::max_bucket 9 -system.ruby.hit_latency_hist_seqr::samples 7041 -system.ruby.hit_latency_hist_seqr::mean 1 -system.ruby.hit_latency_hist_seqr::gmean 1 -system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 7041 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist_seqr::total 7041 -system.ruby.miss_latency_hist_seqr::bucket_size 64 -system.ruby.miss_latency_hist_seqr::max_bucket 639 -system.ruby.miss_latency_hist_seqr::samples 1422 -system.ruby.miss_latency_hist_seqr::mean 70.635724 -system.ruby.miss_latency_hist_seqr::gmean 60.522119 -system.ruby.miss_latency_hist_seqr::stdev 39.545085 -system.ruby.miss_latency_hist_seqr | 403 28.34% 28.34% | 1001 70.39% 98.73% | 3 0.21% 98.95% | 0 0.00% 98.95% | 6 0.42% 99.37% | 8 0.56% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 1 0.07% 100.00% -system.ruby.miss_latency_hist_seqr::total 1422 -system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 115948 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.L1Dcache.demand_hits 1274 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 776 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2050 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Icache.demand_hits 5767 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Icache.demand_misses 646 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Icache.demand_accesses 6413 # Number of cache demand accesses -system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 115948 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 115948 # Cumulative time (in ticks) in various power states -system.ruby.l2_cntrl0.L2cache.demand_hits 239 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 1183 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 1422 # Number of cache demand accesses -system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 115948 # Cumulative time (in ticks) in various power states -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 115948 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.percent_links_utilized 6.507012 -system.ruby.network.routers0.msg_count.Request_Control::0 1422 -system.ruby.network.routers0.msg_count.Response_Data::2 1183 -system.ruby.network.routers0.msg_count.ResponseL2hit_Data::2 239 -system.ruby.network.routers0.msg_count.Writeback_Data::2 1309 -system.ruby.network.routers0.msg_count.Writeback_Control::0 2710 -system.ruby.network.routers0.msg_count.Unblock_Control::2 1468 -system.ruby.network.routers0.msg_bytes.Request_Control::0 11376 -system.ruby.network.routers0.msg_bytes.Response_Data::2 85176 -system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2 17208 -system.ruby.network.routers0.msg_bytes.Writeback_Data::2 94248 -system.ruby.network.routers0.msg_bytes.Writeback_Control::0 21680 -system.ruby.network.routers0.msg_bytes.Unblock_Control::2 11744 -system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 115948 # Cumulative time (in ticks) in various power states -system.ruby.network.routers1.percent_links_utilized 9.772915 -system.ruby.network.routers1.msg_count.Request_Control::0 1422 -system.ruby.network.routers1.msg_count.Request_Control::1 1183 -system.ruby.network.routers1.msg_count.Response_Data::2 2366 -system.ruby.network.routers1.msg_count.ResponseL2hit_Data::2 239 -system.ruby.network.routers1.msg_count.Writeback_Data::2 1503 -system.ruby.network.routers1.msg_count.Writeback_Control::0 2710 -system.ruby.network.routers1.msg_count.Writeback_Control::1 388 -system.ruby.network.routers1.msg_count.Unblock_Control::2 2651 -system.ruby.network.routers1.msg_bytes.Request_Control::0 11376 -system.ruby.network.routers1.msg_bytes.Request_Control::1 9464 -system.ruby.network.routers1.msg_bytes.Response_Data::2 170352 -system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::2 17208 -system.ruby.network.routers1.msg_bytes.Writeback_Data::2 108216 -system.ruby.network.routers1.msg_bytes.Writeback_Control::0 21680 -system.ruby.network.routers1.msg_bytes.Writeback_Control::1 3104 -system.ruby.network.routers1.msg_bytes.Unblock_Control::2 21208 -system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 115948 # Cumulative time (in ticks) in various power states -system.ruby.network.routers2.percent_links_utilized 3.265904 -system.ruby.network.routers2.msg_count.Request_Control::1 1183 -system.ruby.network.routers2.msg_count.Response_Data::2 1183 -system.ruby.network.routers2.msg_count.Writeback_Data::2 194 -system.ruby.network.routers2.msg_count.Writeback_Control::1 388 -system.ruby.network.routers2.msg_count.Unblock_Control::2 1183 -system.ruby.network.routers2.msg_bytes.Request_Control::1 9464 -system.ruby.network.routers2.msg_bytes.Response_Data::2 85176 -system.ruby.network.routers2.msg_bytes.Writeback_Data::2 13968 -system.ruby.network.routers2.msg_bytes.Writeback_Control::1 3104 -system.ruby.network.routers2.msg_bytes.Unblock_Control::2 9464 -system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 115948 # Cumulative time (in ticks) in various power states -system.ruby.network.routers3.percent_links_utilized 6.515277 -system.ruby.network.routers3.msg_count.Request_Control::0 1422 -system.ruby.network.routers3.msg_count.Request_Control::1 1183 -system.ruby.network.routers3.msg_count.Response_Data::2 2366 -system.ruby.network.routers3.msg_count.ResponseL2hit_Data::2 239 -system.ruby.network.routers3.msg_count.Writeback_Data::2 1503 -system.ruby.network.routers3.msg_count.Writeback_Control::0 2710 -system.ruby.network.routers3.msg_count.Writeback_Control::1 388 -system.ruby.network.routers3.msg_count.Unblock_Control::2 2651 -system.ruby.network.routers3.msg_bytes.Request_Control::0 11376 -system.ruby.network.routers3.msg_bytes.Request_Control::1 9464 -system.ruby.network.routers3.msg_bytes.Response_Data::2 170352 -system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::2 17208 -system.ruby.network.routers3.msg_bytes.Writeback_Data::2 108216 -system.ruby.network.routers3.msg_bytes.Writeback_Control::0 21680 -system.ruby.network.routers3.msg_bytes.Writeback_Control::1 3104 -system.ruby.network.routers3.msg_bytes.Unblock_Control::2 21208 -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 115948 # Cumulative time (in ticks) in various power states -system.ruby.network.msg_count.Request_Control 7815 -system.ruby.network.msg_count.Response_Data 7098 -system.ruby.network.msg_count.ResponseL2hit_Data 717 -system.ruby.network.msg_count.Writeback_Data 4509 -system.ruby.network.msg_count.Writeback_Control 9294 -system.ruby.network.msg_count.Unblock_Control 7953 -system.ruby.network.msg_byte.Request_Control 62520 -system.ruby.network.msg_byte.Response_Data 511056 -system.ruby.network.msg_byte.ResponseL2hit_Data 51624 -system.ruby.network.msg_byte.Writeback_Data 324648 -system.ruby.network.msg_byte.Writeback_Control 74352 -system.ruby.network.msg_byte.Unblock_Control 63624 -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 115948 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.throttle0.link_utilization 6.103167 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 1183 -system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2 239 -system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::0 1355 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::2 85176 -system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::2 17208 -system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::0 10840 -system.ruby.network.routers0.throttle1.link_utilization 6.910857 -system.ruby.network.routers0.throttle1.msg_count.Request_Control::0 1422 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::2 1309 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 1355 -system.ruby.network.routers0.throttle1.msg_count.Unblock_Control::2 1468 -system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::0 11376 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::2 94248 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 10840 -system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::2 11744 -system.ruby.network.routers1.throttle0.link_utilization 11.585797 -system.ruby.network.routers1.throttle0.msg_count.Request_Control::0 1422 -system.ruby.network.routers1.throttle0.msg_count.Response_Data::2 1183 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::2 1309 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0 1355 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::1 194 -system.ruby.network.routers1.throttle0.msg_count.Unblock_Control::2 1468 -system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::0 11376 -system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::2 85176 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::2 94248 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 10840 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::1 1552 -system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::2 11744 -system.ruby.network.routers1.throttle1.link_utilization 7.960034 -system.ruby.network.routers1.throttle1.msg_count.Request_Control::1 1183 -system.ruby.network.routers1.throttle1.msg_count.Response_Data::2 1183 -system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::2 239 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::2 194 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::0 1355 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::1 194 -system.ruby.network.routers1.throttle1.msg_count.Unblock_Control::2 1183 -system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::1 9464 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::2 85176 -system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::2 17208 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::2 13968 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::0 10840 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::1 1552 -system.ruby.network.routers1.throttle1.msg_bytes.Unblock_Control::2 9464 -system.ruby.network.routers2.throttle0.link_utilization 1.856867 -system.ruby.network.routers2.throttle0.msg_count.Request_Control::1 1183 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::2 194 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::1 194 -system.ruby.network.routers2.throttle0.msg_count.Unblock_Control::2 1183 -system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::1 9464 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::2 13968 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::1 1552 -system.ruby.network.routers2.throttle0.msg_bytes.Unblock_Control::2 9464 -system.ruby.network.routers2.throttle1.link_utilization 4.674940 -system.ruby.network.routers2.throttle1.msg_count.Response_Data::2 1183 -system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::1 194 -system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::2 85176 -system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::1 1552 -system.ruby.network.routers3.throttle0.link_utilization 6.103167 -system.ruby.network.routers3.throttle0.msg_count.Response_Data::2 1183 -system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::2 239 -system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::0 1355 -system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::2 85176 -system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::2 17208 -system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::0 10840 -system.ruby.network.routers3.throttle1.link_utilization 11.585797 -system.ruby.network.routers3.throttle1.msg_count.Request_Control::0 1422 -system.ruby.network.routers3.throttle1.msg_count.Response_Data::2 1183 -system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::2 1309 -system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::0 1355 -system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::1 194 -system.ruby.network.routers3.throttle1.msg_count.Unblock_Control::2 1468 -system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::0 11376 -system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::2 85176 -system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::2 94248 -system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 10840 -system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::1 1552 -system.ruby.network.routers3.throttle1.msg_bytes.Unblock_Control::2 11744 -system.ruby.network.routers3.throttle2.link_utilization 1.856867 -system.ruby.network.routers3.throttle2.msg_count.Request_Control::1 1183 -system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::2 194 -system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::1 194 -system.ruby.network.routers3.throttle2.msg_count.Unblock_Control::2 1183 -system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::1 9464 -system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::2 13968 -system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::1 1552 -system.ruby.network.routers3.throttle2.msg_bytes.Unblock_Control::2 9464 -system.ruby.LD.latency_hist_seqr::bucket_size 64 -system.ruby.LD.latency_hist_seqr::max_bucket 639 -system.ruby.LD.latency_hist_seqr::samples 1185 -system.ruby.LD.latency_hist_seqr::mean 29.289451 -system.ruby.LD.latency_hist_seqr::gmean 5.875383 -system.ruby.LD.latency_hist_seqr::stdev 39.627102 -system.ruby.LD.latency_hist_seqr | 857 72.32% 72.32% | 323 27.26% 99.58% | 2 0.17% 99.75% | 0 0.00% 99.75% | 1 0.08% 99.83% | 2 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist_seqr::total 1185 -system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 -system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 -system.ruby.LD.hit_latency_hist_seqr::samples 659 -system.ruby.LD.hit_latency_hist_seqr::mean 1 -system.ruby.LD.hit_latency_hist_seqr::gmean 1 -system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 659 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist_seqr::total 659 -system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 -system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 -system.ruby.LD.miss_latency_hist_seqr::samples 526 -system.ruby.LD.miss_latency_hist_seqr::mean 64.731939 -system.ruby.LD.miss_latency_hist_seqr::gmean 54.016248 -system.ruby.LD.miss_latency_hist_seqr::stdev 35.753260 -system.ruby.LD.miss_latency_hist_seqr | 198 37.64% 37.64% | 323 61.41% 99.05% | 2 0.38% 99.43% | 0 0.00% 99.43% | 1 0.19% 99.62% | 2 0.38% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist_seqr::total 526 -system.ruby.ST.latency_hist_seqr::bucket_size 64 -system.ruby.ST.latency_hist_seqr::max_bucket 639 -system.ruby.ST.latency_hist_seqr::samples 865 -system.ruby.ST.latency_hist_seqr::mean 17.729480 -system.ruby.ST.latency_hist_seqr::gmean 3.104775 -system.ruby.ST.latency_hist_seqr::stdev 31.273004 -system.ruby.ST.latency_hist_seqr | 749 86.59% 86.59% | 115 13.29% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist_seqr::total 865 -system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 -system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 -system.ruby.ST.hit_latency_hist_seqr::samples 615 -system.ruby.ST.hit_latency_hist_seqr::mean 1 -system.ruby.ST.hit_latency_hist_seqr::gmean 1 -system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 615 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist_seqr::total 615 -system.ruby.ST.miss_latency_hist_seqr::bucket_size 64 -system.ruby.ST.miss_latency_hist_seqr::max_bucket 639 -system.ruby.ST.miss_latency_hist_seqr::samples 250 -system.ruby.ST.miss_latency_hist_seqr::mean 58.884000 -system.ruby.ST.miss_latency_hist_seqr::gmean 50.399294 -system.ruby.ST.miss_latency_hist_seqr::stdev 31.651062 -system.ruby.ST.miss_latency_hist_seqr | 134 53.60% 53.60% | 115 46.00% 99.60% | 0 0.00% 99.60% | 0 0.00% 99.60% | 0 0.00% 99.60% | 1 0.40% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist_seqr::total 250 -system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 -system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.latency_hist_seqr::samples 6413 -system.ruby.IFETCH.latency_hist_seqr::mean 8.956962 -system.ruby.IFETCH.latency_hist_seqr::gmean 1.536905 -system.ruby.IFETCH.latency_hist_seqr::stdev 27.408738 -system.ruby.IFETCH.latency_hist_seqr | 5838 91.03% 91.03% | 563 8.78% 99.81% | 1 0.02% 99.83% | 0 0.00% 99.83% | 5 0.08% 99.91% | 5 0.08% 99.98% | 0 0.00% 99.98% | 0 0.00% 99.98% | 0 0.00% 99.98% | 1 0.02% 100.00% -system.ruby.IFETCH.latency_hist_seqr::total 6413 -system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 -system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 -system.ruby.IFETCH.hit_latency_hist_seqr::samples 5767 -system.ruby.IFETCH.hit_latency_hist_seqr::mean 1 -system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 -system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 5767 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist_seqr::total 5767 -system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 -system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.miss_latency_hist_seqr::samples 646 -system.ruby.IFETCH.miss_latency_hist_seqr::mean 79.990712 -system.ruby.IFETCH.miss_latency_hist_seqr::gmean 71.267502 -system.ruby.IFETCH.miss_latency_hist_seqr::stdev 42.993310 -system.ruby.IFETCH.miss_latency_hist_seqr | 71 10.99% 10.99% | 563 87.15% 98.14% | 1 0.15% 98.30% | 0 0.00% 98.30% | 5 0.77% 99.07% | 5 0.77% 99.85% | 0 0.00% 99.85% | 0 0.00% 99.85% | 0 0.00% 99.85% | 1 0.15% 100.00% -system.ruby.IFETCH.miss_latency_hist_seqr::total 646 -system.ruby.Directory_Controller.GETX 198 0.00% 0.00% -system.ruby.Directory_Controller.GETS 985 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 194 0.00% 0.00% -system.ruby.Directory_Controller.Unblock 466 0.00% 0.00% -system.ruby.Directory_Controller.Last_Unblock 518 0.00% 0.00% -system.ruby.Directory_Controller.Exclusive_Unblock 198 0.00% 0.00% -system.ruby.Directory_Controller.Dirty_Writeback 194 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 1183 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 194 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 111 0.00% 0.00% -system.ruby.Directory_Controller.I.GETS 466 0.00% 0.00% -system.ruby.Directory_Controller.I.Memory_Ack 194 0.00% 0.00% -system.ruby.Directory_Controller.S.GETX 87 0.00% 0.00% -system.ruby.Directory_Controller.S.GETS 519 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 194 0.00% 0.00% -system.ruby.Directory_Controller.IS.Unblock 466 0.00% 0.00% -system.ruby.Directory_Controller.IS.Memory_Data 466 0.00% 0.00% -system.ruby.Directory_Controller.SS.Last_Unblock 518 0.00% 0.00% -system.ruby.Directory_Controller.SS.Memory_Data 519 0.00% 0.00% -system.ruby.Directory_Controller.MM.Exclusive_Unblock 198 0.00% 0.00% -system.ruby.Directory_Controller.MM.Memory_Data 198 0.00% 0.00% -system.ruby.Directory_Controller.MI.Dirty_Writeback 194 0.00% 0.00% -system.ruby.L1Cache_Controller.Load 1185 0.00% 0.00% -system.ruby.L1Cache_Controller.Ifetch 6413 0.00% 0.00% -system.ruby.L1Cache_Controller.Store 865 0.00% 0.00% -system.ruby.L1Cache_Controller.L1_Replacement 1369 0.00% 0.00% -system.ruby.L1Cache_Controller.Data 1126 0.00% 0.00% -system.ruby.L1Cache_Controller.Exclusive_Data 296 0.00% 0.00% -system.ruby.L1Cache_Controller.Writeback_Ack 46 0.00% 0.00% -system.ruby.L1Cache_Controller.Writeback_Ack_Data 1309 0.00% 0.00% -system.ruby.L1Cache_Controller.All_acks 250 0.00% 0.00% -system.ruby.L1Cache_Controller.Use_Timeout 296 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Load 526 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Ifetch 646 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Store 191 0.00% 0.00% -system.ruby.L1Cache_Controller.S.Load 300 0.00% 0.00% -system.ruby.L1Cache_Controller.S.Ifetch 5767 0.00% 0.00% -system.ruby.L1Cache_Controller.S.Store 59 0.00% 0.00% -system.ruby.L1Cache_Controller.S.L1_Replacement 1060 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Load 79 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Store 18 0.00% 0.00% -system.ruby.L1Cache_Controller.M.L1_Replacement 27 0.00% 0.00% -system.ruby.L1Cache_Controller.M_W.Load 39 0.00% 0.00% -system.ruby.L1Cache_Controller.M_W.Store 1 0.00% 0.00% -system.ruby.L1Cache_Controller.M_W.Use_Timeout 45 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.Load 228 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.Store 242 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.L1_Replacement 268 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_W.Load 13 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_W.Store 354 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_W.L1_Replacement 14 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_W.Use_Timeout 251 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.Exclusive_Data 191 0.00% 0.00% -system.ruby.L1Cache_Controller.SM.Exclusive_Data 59 0.00% 0.00% -system.ruby.L1Cache_Controller.OM.All_acks 250 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Data 1126 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Exclusive_Data 46 0.00% 0.00% -system.ruby.L1Cache_Controller.SI.Writeback_Ack 46 0.00% 0.00% -system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data 1014 0.00% 0.00% -system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data 295 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETS 1172 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETX 250 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTX 295 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTS_only 1060 0.00% 0.00% -system.ruby.L2Cache_Controller.All_Acks 198 0.00% 0.00% -system.ruby.L2Cache_Controller.Data 1183 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_WBCLEANDATA 1014 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_WBDIRTYDATA 295 0.00% 0.00% -system.ruby.L2Cache_Controller.Writeback_Ack 194 0.00% 0.00% -system.ruby.L2Cache_Controller.Unblock 1172 0.00% 0.00% -system.ruby.L2Cache_Controller.Exclusive_Unblock 296 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement 1194 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETS 985 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETX 132 0.00% 0.00% -system.ruby.L2Cache_Controller.ILS.L1_GETX 57 0.00% 0.00% -system.ruby.L2Cache_Controller.ILS.L1_PUTS_only 1014 0.00% 0.00% -system.ruby.L2Cache_Controller.ILX.L1_PUTX 295 0.00% 0.00% -system.ruby.L2Cache_Controller.S.L1_GETS 141 0.00% 0.00% -system.ruby.L2Cache_Controller.S.L1_GETX 7 0.00% 0.00% -system.ruby.L2Cache_Controller.S.L2_Replacement 907 0.00% 0.00% -system.ruby.L2Cache_Controller.SLS.L1_GETX 2 0.00% 0.00% -system.ruby.L2Cache_Controller.SLS.L1_PUTS_only 46 0.00% 0.00% -system.ruby.L2Cache_Controller.SLS.L2_Replacement 93 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETS 46 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETX 52 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement 194 0.00% 0.00% -system.ruby.L2Cache_Controller.IW.L1_WBCLEANDATA 1014 0.00% 0.00% -system.ruby.L2Cache_Controller.SW.Unblock 46 0.00% 0.00% -system.ruby.L2Cache_Controller.ILXW.L1_WBDIRTYDATA 295 0.00% 0.00% -system.ruby.L2Cache_Controller.IGS.Data 985 0.00% 0.00% -system.ruby.L2Cache_Controller.IGS.Unblock 985 0.00% 0.00% -system.ruby.L2Cache_Controller.IGM.Data 139 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMLS.Data 59 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMO.All_Acks 198 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMO.Exclusive_Unblock 198 0.00% 0.00% -system.ruby.L2Cache_Controller.MM.Exclusive_Unblock 52 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.Unblock 141 0.00% 0.00% -system.ruby.L2Cache_Controller.OO.Exclusive_Unblock 46 0.00% 0.00% -system.ruby.L2Cache_Controller.MI.Writeback_Ack 194 0.00% 0.00% - ----------- End Simulation Statistics ---------- diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,2138 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000 -time_sync_spin_threshold=100000 - -[system] -type=System -children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges=0:268435455:0:0:0:0 -memories=system.mem_ctrls -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.sys_port_proxy.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=TimingSimpleCPU -children=clk_domain dtb interrupts isa itb tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu.clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1] -icache_port=system.ruby.l1_cntrl0.sequencer.slave[0] - -[system.cpu.clk_domain] -type=SrcClockDomain -clock=1 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=hello -cwd= -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/linux/hello -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000 - -[system.mem_ctrls] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -page_policy=open_adaptive -power_model=Null -range=0:268435455:5:19:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10 -static_frontend_latency=10 -tBURST=5 -tCCD_L=0 -tCK=1 -tCL=14 -tCS=3 -tRAS=35 -tRCD=14 -tREFI=7800 -tRFC=260 -tRP=14 -tRRD=6 -tRRD_L=0 -tRTP=8 -tRTW=3 -tWR=15 -tWTR=8 -tXAW=30 -tXP=6 -tXPDLL=0 -tXS=270 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.ruby.dir_cntrl0.memory - -[system.ruby] -type=RubySystem -children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network -access_backing_store=false -all_instructions=false -block_size_bytes=64 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hot_lines=false -memory_size_bits=48 -num_of_sequencers=1 -number_of_virtual_networks=6 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -phys_mem=Null -power_model=Null -randomization=false - -[system.ruby.clk_domain] -type=SrcClockDomain -clock=1 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.ruby.dir_cntrl0] -type=Directory_Controller -children=directory dmaRequestToDir dmaResponseFromDir persistentFromDir persistentToDir requestFromDir requestToDir responseFromDir responseFromMemory responseToDir -buffer_size=0 -clk_domain=system.ruby.clk_domain -cluster_id=0 -default_p_state=UNDEFINED -directory=system.ruby.dir_cntrl0.directory -directory_latency=5 -distributed_persistent=true -dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir -dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir -eventq_index=0 -fixed_timeout_latency=100 -l2_select_num_bits=0 -number_of_TBEs=256 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -persistentFromDir=system.ruby.dir_cntrl0.persistentFromDir -persistentToDir=system.ruby.dir_cntrl0.persistentToDir -power_model=Null -recycle_latency=10 -reissue_wakeup_latency=10 -requestFromDir=system.ruby.dir_cntrl0.requestFromDir -requestToDir=system.ruby.dir_cntrl0.requestToDir -responseFromDir=system.ruby.dir_cntrl0.responseFromDir -responseFromMemory=system.ruby.dir_cntrl0.responseFromMemory -responseToDir=system.ruby.dir_cntrl0.responseToDir -ruby_system=system.ruby -system=system -to_memory_controller_latency=1 -transitions_per_cycle=4 -version=0 -memory=system.mem_ctrls.port - -[system.ruby.dir_cntrl0.directory] -type=RubyDirectoryMemory -eventq_index=0 -numa_high_bit=5 -size=268435456 -version=0 - -[system.ruby.dir_cntrl0.dmaRequestToDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -slave=system.ruby.network.master[10] - -[system.ruby.dir_cntrl0.dmaResponseFromDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -master=system.ruby.network.slave[9] - -[system.ruby.dir_cntrl0.persistentFromDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -master=system.ruby.network.slave[8] - -[system.ruby.dir_cntrl0.persistentToDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -slave=system.ruby.network.master[9] - -[system.ruby.dir_cntrl0.requestFromDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[6] - -[system.ruby.dir_cntrl0.requestToDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[7] - -[system.ruby.dir_cntrl0.responseFromDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[7] - -[system.ruby.dir_cntrl0.responseFromMemory] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false - -[system.ruby.dir_cntrl0.responseToDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[8] - -[system.ruby.l1_cntrl0] -type=L1Cache_Controller -children=L1Dcache L1Icache mandatoryQueue persistentFromL1Cache persistentToL1Cache requestFromL1Cache requestToL1Cache responseFromL1Cache responseToL1Cache sequencer -L1Dcache=system.ruby.l1_cntrl0.L1Dcache -L1Icache=system.ruby.l1_cntrl0.L1Icache -N_tokens=2 -buffer_size=0 -clk_domain=system.cpu.clk_domain -cluster_id=0 -default_p_state=UNDEFINED -dynamic_timeout_enabled=true -eventq_index=0 -fixed_timeout_latency=300 -l1_request_latency=2 -l1_response_latency=2 -l2_select_num_bits=0 -mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue -no_mig_atomic=true -number_of_TBEs=256 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -persistentFromL1Cache=system.ruby.l1_cntrl0.persistentFromL1Cache -persistentToL1Cache=system.ruby.l1_cntrl0.persistentToL1Cache -power_model=Null -recycle_latency=10 -reissue_wakeup_latency=10 -requestFromL1Cache=system.ruby.l1_cntrl0.requestFromL1Cache -requestToL1Cache=system.ruby.l1_cntrl0.requestToL1Cache -responseFromL1Cache=system.ruby.l1_cntrl0.responseFromL1Cache -responseToL1Cache=system.ruby.l1_cntrl0.responseToL1Cache -retry_threshold=1 -ruby_system=system.ruby -send_evictions=false -sequencer=system.ruby.l1_cntrl0.sequencer -system=system -transitions_per_cycle=4 -use_timeout_latency=50 -version=0 - -[system.ruby.l1_cntrl0.L1Dcache] -type=RubyCache -children=replacement_policy -assoc=2 -block_size=0 -dataAccessLatency=1 -dataArrayBanks=1 -eventq_index=0 -is_icache=false -replacement_policy=system.ruby.l1_cntrl0.L1Dcache.replacement_policy -resourceStalls=false -ruby_system=system.ruby -size=256 -start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 - -[system.ruby.l1_cntrl0.L1Dcache.replacement_policy] -type=PseudoLRUReplacementPolicy -assoc=2 -block_size=64 -eventq_index=0 -size=256 - -[system.ruby.l1_cntrl0.L1Icache] -type=RubyCache -children=replacement_policy -assoc=2 -block_size=0 -dataAccessLatency=1 -dataArrayBanks=1 -eventq_index=0 -is_icache=false -replacement_policy=system.ruby.l1_cntrl0.L1Icache.replacement_policy -resourceStalls=false -ruby_system=system.ruby -size=256 -start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 - -[system.ruby.l1_cntrl0.L1Icache.replacement_policy] -type=PseudoLRUReplacementPolicy -assoc=2 -block_size=64 -eventq_index=0 -size=256 - -[system.ruby.l1_cntrl0.mandatoryQueue] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false - -[system.ruby.l1_cntrl0.persistentFromL1Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -master=system.ruby.network.slave[2] - -[system.ruby.l1_cntrl0.persistentToL1Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -slave=system.ruby.network.master[2] - -[system.ruby.l1_cntrl0.requestFromL1Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[0] - -[system.ruby.l1_cntrl0.requestToL1Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[0] - -[system.ruby.l1_cntrl0.responseFromL1Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[1] - -[system.ruby.l1_cntrl0.responseToL1Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[1] - -[system.ruby.l1_cntrl0.sequencer] -type=RubySequencer -clk_domain=system.cpu.clk_domain -coreid=99 -dcache=system.ruby.l1_cntrl0.L1Dcache -dcache_hit_latency=1 -deadlock_threshold=500000 -default_p_state=UNDEFINED -eventq_index=0 -garnet_standalone=false -icache=system.ruby.l1_cntrl0.L1Icache -icache_hit_latency=1 -is_cpu_sequencer=true -max_outstanding_requests=16 -no_retry_on_stall=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -ruby_system=system.ruby -support_data_reqs=true -support_inst_reqs=true -system=system -using_ruby_tester=false -version=0 -slave=system.cpu.icache_port system.cpu.dcache_port - -[system.ruby.l2_cntrl0] -type=L2Cache_Controller -children=GlobalRequestFromL2Cache GlobalRequestToL2Cache L1RequestFromL2Cache L1RequestToL2Cache L2cache persistentToL2Cache responseFromL2Cache responseToL2Cache -GlobalRequestFromL2Cache=system.ruby.l2_cntrl0.GlobalRequestFromL2Cache -GlobalRequestToL2Cache=system.ruby.l2_cntrl0.GlobalRequestToL2Cache -L1RequestFromL2Cache=system.ruby.l2_cntrl0.L1RequestFromL2Cache -L1RequestToL2Cache=system.ruby.l2_cntrl0.L1RequestToL2Cache -L2cache=system.ruby.l2_cntrl0.L2cache -N_tokens=2 -buffer_size=0 -clk_domain=system.ruby.clk_domain -cluster_id=0 -default_p_state=UNDEFINED -eventq_index=0 -filtering_enabled=true -l2_request_latency=5 -l2_response_latency=5 -number_of_TBEs=256 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -persistentToL2Cache=system.ruby.l2_cntrl0.persistentToL2Cache -power_model=Null -recycle_latency=10 -responseFromL2Cache=system.ruby.l2_cntrl0.responseFromL2Cache -responseToL2Cache=system.ruby.l2_cntrl0.responseToL2Cache -ruby_system=system.ruby -system=system -transitions_per_cycle=4 -version=0 - -[system.ruby.l2_cntrl0.GlobalRequestFromL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[3] - -[system.ruby.l2_cntrl0.GlobalRequestToL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[3] - -[system.ruby.l2_cntrl0.L1RequestFromL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[4] - -[system.ruby.l2_cntrl0.L1RequestToL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[4] - -[system.ruby.l2_cntrl0.L2cache] -type=RubyCache -children=replacement_policy -assoc=2 -block_size=0 -dataAccessLatency=1 -dataArrayBanks=1 -eventq_index=0 -is_icache=false -replacement_policy=system.ruby.l2_cntrl0.L2cache.replacement_policy -resourceStalls=false -ruby_system=system.ruby -size=512 -start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 - -[system.ruby.l2_cntrl0.L2cache.replacement_policy] -type=PseudoLRUReplacementPolicy -assoc=2 -block_size=64 -eventq_index=0 -size=512 - -[system.ruby.l2_cntrl0.persistentToL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -slave=system.ruby.network.master[6] - -[system.ruby.l2_cntrl0.responseFromL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[5] - -[system.ruby.l2_cntrl0.responseToL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[5] - -[system.ruby.memctrl_clk_domain] -type=DerivedClockDomain -clk_divider=3 -clk_domain=system.ruby.clk_domain -eventq_index=0 - -[system.ruby.network] -type=SimpleNetwork -children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_link_buffers40 int_link_buffers41 int_link_buffers42 int_link_buffers43 int_link_buffers44 int_link_buffers45 int_link_buffers46 int_link_buffers47 int_link_buffers48 int_link_buffers49 int_link_buffers50 int_link_buffers51 int_link_buffers52 int_link_buffers53 int_link_buffers54 int_link_buffers55 int_link_buffers56 int_link_buffers57 int_link_buffers58 int_link_buffers59 int_link_buffers60 int_link_buffers61 int_link_buffers62 int_link_buffers63 int_link_buffers64 int_link_buffers65 int_link_buffers66 int_link_buffers67 int_link_buffers68 int_link_buffers69 int_link_buffers70 int_link_buffers71 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 routers0 routers1 routers2 routers3 -adaptive_routing=false -buffer_size=0 -clk_domain=system.ruby.clk_domain -control_msg_size=8 -default_p_state=UNDEFINED -endpoint_bandwidth=1000 -eventq_index=0 -ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2 -int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 system.ruby.network.int_link_buffers40 system.ruby.network.int_link_buffers41 system.ruby.network.int_link_buffers42 system.ruby.network.int_link_buffers43 system.ruby.network.int_link_buffers44 system.ruby.network.int_link_buffers45 system.ruby.network.int_link_buffers46 system.ruby.network.int_link_buffers47 system.ruby.network.int_link_buffers48 system.ruby.network.int_link_buffers49 system.ruby.network.int_link_buffers50 system.ruby.network.int_link_buffers51 system.ruby.network.int_link_buffers52 system.ruby.network.int_link_buffers53 system.ruby.network.int_link_buffers54 system.ruby.network.int_link_buffers55 system.ruby.network.int_link_buffers56 system.ruby.network.int_link_buffers57 system.ruby.network.int_link_buffers58 system.ruby.network.int_link_buffers59 system.ruby.network.int_link_buffers60 system.ruby.network.int_link_buffers61 system.ruby.network.int_link_buffers62 system.ruby.network.int_link_buffers63 system.ruby.network.int_link_buffers64 system.ruby.network.int_link_buffers65 system.ruby.network.int_link_buffers66 system.ruby.network.int_link_buffers67 system.ruby.network.int_link_buffers68 system.ruby.network.int_link_buffers69 system.ruby.network.int_link_buffers70 system.ruby.network.int_link_buffers71 -int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4 system.ruby.network.int_links5 -netifs= -number_of_virtual_networks=6 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 system.ruby.network.routers3 -ruby_system=system.ruby -topology=Crossbar -master=system.ruby.l1_cntrl0.requestToL1Cache.slave system.ruby.l1_cntrl0.responseToL1Cache.slave system.ruby.l1_cntrl0.persistentToL1Cache.slave system.ruby.l2_cntrl0.GlobalRequestToL2Cache.slave system.ruby.l2_cntrl0.L1RequestToL2Cache.slave system.ruby.l2_cntrl0.responseToL2Cache.slave system.ruby.l2_cntrl0.persistentToL2Cache.slave system.ruby.dir_cntrl0.requestToDir.slave system.ruby.dir_cntrl0.responseToDir.slave system.ruby.dir_cntrl0.persistentToDir.slave system.ruby.dir_cntrl0.dmaRequestToDir.slave -slave=system.ruby.l1_cntrl0.requestFromL1Cache.master system.ruby.l1_cntrl0.responseFromL1Cache.master system.ruby.l1_cntrl0.persistentFromL1Cache.master system.ruby.l2_cntrl0.GlobalRequestFromL2Cache.master system.ruby.l2_cntrl0.L1RequestFromL2Cache.master system.ruby.l2_cntrl0.responseFromL2Cache.master system.ruby.dir_cntrl0.requestFromDir.master system.ruby.dir_cntrl0.responseFromDir.master system.ruby.dir_cntrl0.persistentFromDir.master system.ruby.dir_cntrl0.dmaResponseFromDir.master - -[system.ruby.network.ext_links0] -type=SimpleExtLink -bandwidth_factor=16 -eventq_index=0 -ext_node=system.ruby.l1_cntrl0 -int_node=system.ruby.network.routers0 -latency=1 -link_id=0 -weight=1 - -[system.ruby.network.ext_links1] -type=SimpleExtLink -bandwidth_factor=16 -eventq_index=0 -ext_node=system.ruby.l2_cntrl0 -int_node=system.ruby.network.routers1 -latency=1 -link_id=1 -weight=1 - -[system.ruby.network.ext_links2] -type=SimpleExtLink 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-[system.ruby.network.routers1.port_buffers23] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19 system.ruby.network.routers2.port_buffers20 system.ruby.network.routers2.port_buffers21 system.ruby.network.routers2.port_buffers22 system.ruby.network.routers2.port_buffers23 -power_model=Null -router_id=2 -virt_nets=6 - -[system.ruby.network.routers2.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers15] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers16] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers17] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers18] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers19] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers20] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers21] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers22] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers23] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23 port_buffers24 port_buffers25 port_buffers26 port_buffers27 port_buffers28 port_buffers29 port_buffers30 port_buffers31 port_buffers32 port_buffers33 port_buffers34 port_buffers35 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers3.port_buffers00 system.ruby.network.routers3.port_buffers01 system.ruby.network.routers3.port_buffers02 system.ruby.network.routers3.port_buffers03 system.ruby.network.routers3.port_buffers04 system.ruby.network.routers3.port_buffers05 system.ruby.network.routers3.port_buffers06 system.ruby.network.routers3.port_buffers07 system.ruby.network.routers3.port_buffers08 system.ruby.network.routers3.port_buffers09 system.ruby.network.routers3.port_buffers10 system.ruby.network.routers3.port_buffers11 system.ruby.network.routers3.port_buffers12 system.ruby.network.routers3.port_buffers13 system.ruby.network.routers3.port_buffers14 system.ruby.network.routers3.port_buffers15 system.ruby.network.routers3.port_buffers16 system.ruby.network.routers3.port_buffers17 system.ruby.network.routers3.port_buffers18 system.ruby.network.routers3.port_buffers19 system.ruby.network.routers3.port_buffers20 system.ruby.network.routers3.port_buffers21 system.ruby.network.routers3.port_buffers22 system.ruby.network.routers3.port_buffers23 system.ruby.network.routers3.port_buffers24 system.ruby.network.routers3.port_buffers25 system.ruby.network.routers3.port_buffers26 system.ruby.network.routers3.port_buffers27 system.ruby.network.routers3.port_buffers28 system.ruby.network.routers3.port_buffers29 system.ruby.network.routers3.port_buffers30 system.ruby.network.routers3.port_buffers31 system.ruby.network.routers3.port_buffers32 system.ruby.network.routers3.port_buffers33 system.ruby.network.routers3.port_buffers34 system.ruby.network.routers3.port_buffers35 -power_model=Null -router_id=3 -virt_nets=6 - -[system.ruby.network.routers3.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - 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-type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers18] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers19] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers20] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers21] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers22] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers23] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers24] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers25] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers26] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers27] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers28] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers29] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers30] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers31] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers32] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers33] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers34] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers35] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.sys_port_proxy] -type=RubyPortProxy -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_cpu_sequencer=true -no_retry_on_stall=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -ruby_system=system.ruby -support_data_reqs=true -support_inst_reqs=true -system=system -using_ruby_tester=false -version=0 -slave=system.system_port - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,10 +0,0 @@ -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,15 +0,0 @@ -Redirecting stdout to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout -Redirecting stderr to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 13 2016 20:33:48 -gem5 started Oct 13 2016 20:34:16 -gem5 executing on e108600-lin, pid 27525 -command line: /work/curdun01/gem5-external.hg/build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token - -Global frequency set at 1000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Hello world! -Exiting @ tick 113952 because target called exit() diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,853 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000114 # Number of seconds simulated -sim_ticks 113952 # Number of ticks simulated -final_tick 113952 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 100852 # Simulator instruction rate (inst/s) -host_op_rate 100836 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1794284 # Simulator tick rate (ticks/s) -host_mem_usage 414264 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host -sim_insts 6403 # Number of instructions simulated -sim_ops 6403 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 113952 # Cumulative time (in ticks) in various power states -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 75456 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 75456 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14656 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 14656 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 1179 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 1179 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 229 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 229 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 662173547 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 662173547 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 128615557 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 128615557 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 790789104 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 790789104 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 1179 # Number of read requests accepted -system.mem_ctrls.writeReqs 229 # Number of write requests accepted -system.mem_ctrls.readBursts 1179 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 229 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 64256 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 11200 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 5120 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 75456 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 14656 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 175 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 117 # Number of DRAM write bursts merged with an existing one -system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 86 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 52 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 82 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 77 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 92 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 18 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 1 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 3 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::9 1 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 51 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 53 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 22 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 360 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 61 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 45 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 20 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 6 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 2 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 15 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 37 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts -system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 113863 # Total gap between requests -system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 1179 # Read request sizes (log2) -system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 229 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 1004 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 5 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 201 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 338.149254 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 209.301438 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 329.237418 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 56 27.86% 27.86% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 54 26.87% 54.73% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 27 13.43% 68.16% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 9 4.48% 72.64% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 15 7.46% 80.10% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 6 2.99% 83.08% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 6 2.99% 86.07% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 4 1.99% 88.06% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 24 11.94% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 201 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 5 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 138 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 99.720637 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 86.905121 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-23 1 20.00% 20.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::80-87 1 20.00% 40.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::160-167 1 20.00% 60.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::208-215 1 20.00% 80.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::216-223 1 20.00% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 5 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 5 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 5 100.00% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 5 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 13296 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 32372 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 5020 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 13.24 # Average queueing delay per DRAM burst -system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 32.24 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 563.89 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 44.93 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 662.17 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 128.62 # Average system write bandwidth in MiByte/s -system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 4.76 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 4.41 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 0.35 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 22.60 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 806 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 73 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 80.28 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 65.18 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 80.87 # Average gap between requests -system.mem_ctrls.pageHitRate 78.76 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 471240 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 255024 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 4695264 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 217152 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 9219600.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 7578264 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 292992 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.actPowerDownEnergy 33706152 # Energy for active power-down per rank (pJ) -system.mem_ctrls_0.prePowerDownEnergy 7106688 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_0.selfRefreshEnergy 1604640 # Energy for self refresh per rank (pJ) -system.mem_ctrls_0.totalEnergy 65147016 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 570.509199 # Core power per rank (mW) -system.mem_ctrls_0.totalIdleTime 96809 # Total Idle time Per DRAM Rank -system.mem_ctrls_0.memoryStateTime::IDLE 351 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 3653 # Time in different power states -system.mem_ctrls_0.memoryStateTime::SREF 4385 # Time in different power states -system.mem_ctrls_0.memoryStateTime::PRE_PDN 18507 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 13139 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 73917 # Time in different power states -system.mem_ctrls_1.actEnergy 992460 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 521640 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 6774432 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 451008 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 8604960.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 10831824 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 319872 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.actPowerDownEnergy 39423936 # Energy for active power-down per rank (pJ) -system.mem_ctrls_1.prePowerDownEnergy 1117056 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrls_1.totalEnergy 69037188 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 605.844461 # Core power per rank (mW) -system.mem_ctrls_1.totalIdleTime 89154 # Total Idle time Per DRAM Rank -system.mem_ctrls_1.memoryStateTime::IDLE 259 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 3640 # Time in different power states -system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 2909 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 20688 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT_PDN 86456 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 113952 # Cumulative time (in ticks) in various power states -system.cpu.clk_domain.clock 1 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1185 # DTB read hits -system.cpu.dtb.read_misses 7 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 1192 # DTB read accesses -system.cpu.dtb.write_hits 865 # DTB write hits -system.cpu.dtb.write_misses 3 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 868 # DTB write accesses -system.cpu.dtb.data_hits 2050 # DTB hits -system.cpu.dtb.data_misses 10 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 2060 # DTB accesses -system.cpu.itb.fetch_hits 6414 # ITB hits -system.cpu.itb.fetch_misses 17 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 6431 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 113952 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 113952 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 6403 # Number of instructions committed -system.cpu.committedOps 6403 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 6329 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses -system.cpu.num_func_calls 251 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 754 # number of instructions that are conditional controls -system.cpu.num_int_insts 6329 # number of integer instructions -system.cpu.num_fp_insts 10 # number of float instructions -system.cpu.num_int_register_reads 8297 # number of times the integer registers were read -system.cpu.num_int_register_writes 4575 # number of times the integer registers were written -system.cpu.num_fp_register_reads 8 # number of times the floating registers were read -system.cpu.num_fp_register_writes 2 # number of times the floating registers were written -system.cpu.num_mem_refs 2060 # number of memory refs -system.cpu.num_load_insts 1192 # Number of load instructions -system.cpu.num_store_insts 868 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 113952 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 1056 # Number of branches fetched -system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction -system.cpu.op_class::IntAlu 4331 67.53% 67.83% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.02% 67.85% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 67.85% # Class of executed instruction -system.cpu.op_class::FloatAdd 2 0.03% 67.88% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::MemRead 1191 18.57% 86.45% # Class of executed instruction -system.cpu.op_class::MemWrite 861 13.43% 99.88% # Class of executed instruction -system.cpu.op_class::FloatMemRead 1 0.02% 99.89% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 7 0.11% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 6413 # Class of executed instruction -system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.pwrStateResidencyTicks::UNDEFINED 113952 # Cumulative time (in ticks) in various power states -system.ruby.outstanding_req_hist_seqr::bucket_size 1 -system.ruby.outstanding_req_hist_seqr::max_bucket 9 -system.ruby.outstanding_req_hist_seqr::samples 8464 -system.ruby.outstanding_req_hist_seqr::mean 1 -system.ruby.outstanding_req_hist_seqr::gmean 1 -system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 8464 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist_seqr::total 8464 -system.ruby.latency_hist_seqr::bucket_size 64 -system.ruby.latency_hist_seqr::max_bucket 639 -system.ruby.latency_hist_seqr::samples 8463 -system.ruby.latency_hist_seqr::mean 12.464729 -system.ruby.latency_hist_seqr::gmean 1.971984 -system.ruby.latency_hist_seqr::stdev 29.823065 -system.ruby.latency_hist_seqr | 7459 88.14% 88.14% | 983 11.62% 99.75% | 7 0.08% 99.83% | 3 0.04% 99.87% | 5 0.06% 99.93% | 5 0.06% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% -system.ruby.latency_hist_seqr::total 8463 -system.ruby.hit_latency_hist_seqr::bucket_size 8 -system.ruby.hit_latency_hist_seqr::max_bucket 79 -system.ruby.hit_latency_hist_seqr::samples 7284 -system.ruby.hit_latency_hist_seqr::mean 1.636052 -system.ruby.hit_latency_hist_seqr::gmean 1.092653 -system.ruby.hit_latency_hist_seqr::stdev 3.757041 -system.ruby.hit_latency_hist_seqr | 7080 97.20% 97.20% | 0 0.00% 97.20% | 21 0.29% 97.49% | 182 2.50% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist_seqr::total 7284 -system.ruby.miss_latency_hist_seqr::bucket_size 64 -system.ruby.miss_latency_hist_seqr::max_bucket 639 -system.ruby.miss_latency_hist_seqr::samples 1179 -system.ruby.miss_latency_hist_seqr::mean 79.365564 -system.ruby.miss_latency_hist_seqr::gmean 75.701428 -system.ruby.miss_latency_hist_seqr::stdev 33.123085 -system.ruby.miss_latency_hist_seqr | 175 14.84% 14.84% | 983 83.38% 98.22% | 7 0.59% 98.81% | 3 0.25% 99.07% | 5 0.42% 99.49% | 5 0.42% 99.92% | 0 0.00% 99.92% | 0 0.00% 99.92% | 0 0.00% 99.92% | 1 0.08% 100.00% -system.ruby.miss_latency_hist_seqr::total 1179 -system.ruby.Directory.incomplete_times_seqr 1178 -system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 113952 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.L1Dcache.demand_hits 1313 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 737 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2050 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Icache.demand_hits 5767 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Icache.demand_misses 646 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Icache.demand_accesses 6413 # Number of cache demand accesses -system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 113952 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 113952 # Cumulative time (in ticks) in various power states -system.ruby.l2_cntrl0.L2cache.demand_hits 187 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 1196 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 1383 # Number of cache demand accesses -system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 113952 # Cumulative time (in ticks) in various power states -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 113952 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.percent_links_utilized 5.719513 -system.ruby.network.routers0.msg_count.Request_Control::1 1383 -system.ruby.network.routers0.msg_count.Response_Data::4 1179 -system.ruby.network.routers0.msg_count.ResponseL2hit_Data::4 204 -system.ruby.network.routers0.msg_count.Response_Control::4 1 -system.ruby.network.routers0.msg_count.Writeback_Data::4 1355 -system.ruby.network.routers0.msg_count.Persistent_Control::3 44 -system.ruby.network.routers0.msg_bytes.Request_Control::1 11064 -system.ruby.network.routers0.msg_bytes.Response_Data::4 84888 -system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::4 14688 -system.ruby.network.routers0.msg_bytes.Response_Control::4 8 -system.ruby.network.routers0.msg_bytes.Writeback_Data::4 97560 -system.ruby.network.routers0.msg_bytes.Persistent_Control::3 352 -system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 113952 # Cumulative time (in ticks) in various power states -system.ruby.network.routers1.percent_links_utilized 4.313658 -system.ruby.network.routers1.msg_count.Request_Control::1 1383 -system.ruby.network.routers1.msg_count.Request_Control::2 1196 -system.ruby.network.routers1.msg_count.ResponseL2hit_Data::4 204 -system.ruby.network.routers1.msg_count.Response_Control::4 1 -system.ruby.network.routers1.msg_count.Writeback_Data::4 1584 -system.ruby.network.routers1.msg_count.Writeback_Control::4 968 -system.ruby.network.routers1.msg_count.Persistent_Control::3 22 -system.ruby.network.routers1.msg_bytes.Request_Control::1 11064 -system.ruby.network.routers1.msg_bytes.Request_Control::2 9568 -system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::4 14688 -system.ruby.network.routers1.msg_bytes.Response_Control::4 8 -system.ruby.network.routers1.msg_bytes.Writeback_Data::4 114048 -system.ruby.network.routers1.msg_bytes.Writeback_Control::4 7744 -system.ruby.network.routers1.msg_bytes.Persistent_Control::3 176 -system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 113952 # Cumulative time (in ticks) in various power states -system.ruby.network.routers2.percent_links_utilized 3.259706 -system.ruby.network.routers2.msg_count.Request_Control::2 1196 -system.ruby.network.routers2.msg_count.Response_Data::4 1179 -system.ruby.network.routers2.msg_count.Writeback_Data::4 229 -system.ruby.network.routers2.msg_count.Writeback_Control::4 968 -system.ruby.network.routers2.msg_count.Persistent_Control::3 22 -system.ruby.network.routers2.msg_bytes.Request_Control::2 9568 -system.ruby.network.routers2.msg_bytes.Response_Data::4 84888 -system.ruby.network.routers2.msg_bytes.Writeback_Data::4 16488 -system.ruby.network.routers2.msg_bytes.Writeback_Control::4 7744 -system.ruby.network.routers2.msg_bytes.Persistent_Control::3 176 -system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 113952 # Cumulative time (in ticks) in various power states -system.ruby.network.routers3.percent_links_utilized 4.430959 -system.ruby.network.routers3.msg_count.Request_Control::1 1383 -system.ruby.network.routers3.msg_count.Request_Control::2 1196 -system.ruby.network.routers3.msg_count.Response_Data::4 1179 -system.ruby.network.routers3.msg_count.ResponseL2hit_Data::4 204 -system.ruby.network.routers3.msg_count.Response_Control::4 1 -system.ruby.network.routers3.msg_count.Writeback_Data::4 1584 -system.ruby.network.routers3.msg_count.Writeback_Control::4 968 -system.ruby.network.routers3.msg_count.Persistent_Control::3 44 -system.ruby.network.routers3.msg_bytes.Request_Control::1 11064 -system.ruby.network.routers3.msg_bytes.Request_Control::2 9568 -system.ruby.network.routers3.msg_bytes.Response_Data::4 84888 -system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::4 14688 -system.ruby.network.routers3.msg_bytes.Response_Control::4 8 -system.ruby.network.routers3.msg_bytes.Writeback_Data::4 114048 -system.ruby.network.routers3.msg_bytes.Writeback_Control::4 7744 -system.ruby.network.routers3.msg_bytes.Persistent_Control::3 352 -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 113952 # Cumulative time (in ticks) in various power states -system.ruby.network.msg_count.Request_Control 7737 -system.ruby.network.msg_count.Response_Data 3537 -system.ruby.network.msg_count.ResponseL2hit_Data 612 -system.ruby.network.msg_count.Response_Control 3 -system.ruby.network.msg_count.Writeback_Data 4752 -system.ruby.network.msg_count.Writeback_Control 2904 -system.ruby.network.msg_count.Persistent_Control 132 -system.ruby.network.msg_byte.Request_Control 61896 -system.ruby.network.msg_byte.Response_Data 254664 -system.ruby.network.msg_byte.ResponseL2hit_Data 44064 -system.ruby.network.msg_byte.Response_Control 24 -system.ruby.network.msg_byte.Writeback_Data 342144 -system.ruby.network.msg_byte.Writeback_Control 23232 -system.ruby.network.msg_byte.Persistent_Control 1056 -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 113952 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.throttle0.link_utilization 5.471602 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1179 -system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4 204 -system.ruby.network.routers0.throttle0.msg_count.Response_Control::4 1 -system.ruby.network.routers0.throttle0.msg_count.Persistent_Control::3 22 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 84888 -system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::4 14688 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::4 8 -system.ruby.network.routers0.throttle0.msg_bytes.Persistent_Control::3 176 -system.ruby.network.routers0.throttle1.link_utilization 5.967425 -system.ruby.network.routers0.throttle1.msg_count.Request_Control::1 1383 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::4 1355 -system.ruby.network.routers0.throttle1.msg_count.Persistent_Control::3 22 -system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::1 11064 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::4 97560 -system.ruby.network.routers0.throttle1.msg_bytes.Persistent_Control::3 176 -system.ruby.network.routers1.throttle0.link_utilization 5.967425 -system.ruby.network.routers1.throttle0.msg_count.Request_Control::1 1383 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::4 1355 -system.ruby.network.routers1.throttle0.msg_count.Persistent_Control::3 22 -system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::1 11064 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::4 97560 -system.ruby.network.routers1.throttle0.msg_bytes.Persistent_Control::3 176 -system.ruby.network.routers1.throttle1.link_utilization 2.659892 -system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 1196 -system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::4 204 -system.ruby.network.routers1.throttle1.msg_count.Response_Control::4 1 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::4 229 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::4 968 -system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2 9568 -system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::4 14688 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::4 8 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::4 16488 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::4 7744 -system.ruby.network.routers2.throttle0.link_utilization 1.863504 -system.ruby.network.routers2.throttle0.msg_count.Request_Control::2 1196 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::4 229 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::4 968 -system.ruby.network.routers2.throttle0.msg_count.Persistent_Control::3 22 -system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::2 9568 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::4 16488 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::4 7744 -system.ruby.network.routers2.throttle0.msg_bytes.Persistent_Control::3 176 -system.ruby.network.routers2.throttle1.link_utilization 4.655908 -system.ruby.network.routers2.throttle1.msg_count.Response_Data::4 1179 -system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::4 84888 -system.ruby.network.routers3.throttle0.link_utilization 5.461949 -system.ruby.network.routers3.throttle0.msg_count.Response_Data::4 1179 -system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::4 204 -system.ruby.network.routers3.throttle0.msg_count.Response_Control::4 1 -system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::4 84888 -system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::4 14688 -system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::4 8 -system.ruby.network.routers3.throttle1.link_utilization 5.967425 -system.ruby.network.routers3.throttle1.msg_count.Request_Control::1 1383 -system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::4 1355 -system.ruby.network.routers3.throttle1.msg_count.Persistent_Control::3 22 -system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::1 11064 -system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::4 97560 -system.ruby.network.routers3.throttle1.msg_bytes.Persistent_Control::3 176 -system.ruby.network.routers3.throttle2.link_utilization 1.863504 -system.ruby.network.routers3.throttle2.msg_count.Request_Control::2 1196 -system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::4 229 -system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::4 968 -system.ruby.network.routers3.throttle2.msg_count.Persistent_Control::3 22 -system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::2 9568 -system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::4 16488 -system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::4 7744 -system.ruby.network.routers3.throttle2.msg_bytes.Persistent_Control::3 176 -system.ruby.LD.latency_hist_seqr::bucket_size 64 -system.ruby.LD.latency_hist_seqr::max_bucket 639 -system.ruby.LD.latency_hist_seqr::samples 1185 -system.ruby.LD.latency_hist_seqr::mean 29.824473 -system.ruby.LD.latency_hist_seqr::gmean 6.089961 -system.ruby.LD.latency_hist_seqr::stdev 38.602832 -system.ruby.LD.latency_hist_seqr | 854 72.07% 72.07% | 327 27.59% 99.66% | 2 0.17% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 2 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist_seqr::total 1185 -system.ruby.LD.hit_latency_hist_seqr::bucket_size 4 -system.ruby.LD.hit_latency_hist_seqr::max_bucket 39 -system.ruby.LD.hit_latency_hist_seqr::samples 759 -system.ruby.LD.hit_latency_hist_seqr::mean 4.025033 -system.ruby.LD.hit_latency_hist_seqr::gmean 1.519643 -system.ruby.LD.hit_latency_hist_seqr::stdev 7.772026 -system.ruby.LD.hit_latency_hist_seqr | 659 86.82% 86.82% | 0 0.00% 86.82% | 0 0.00% 86.82% | 0 0.00% 86.82% | 0 0.00% 86.82% | 1 0.13% 86.96% | 99 13.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist_seqr::total 759 -system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 -system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 -system.ruby.LD.miss_latency_hist_seqr::samples 426 -system.ruby.LD.miss_latency_hist_seqr::mean 75.791080 -system.ruby.LD.miss_latency_hist_seqr::gmean 72.234894 -system.ruby.LD.miss_latency_hist_seqr::stdev 27.150058 -system.ruby.LD.miss_latency_hist_seqr | 95 22.30% 22.30% | 327 76.76% 99.06% | 2 0.47% 99.53% | 0 0.00% 99.53% | 0 0.00% 99.53% | 2 0.47% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist_seqr::total 426 -system.ruby.ST.latency_hist_seqr::bucket_size 32 -system.ruby.ST.latency_hist_seqr::max_bucket 319 -system.ruby.ST.latency_hist_seqr::samples 865 -system.ruby.ST.latency_hist_seqr::mean 14.804624 -system.ruby.ST.latency_hist_seqr::gmean 2.602855 -system.ruby.ST.latency_hist_seqr::stdev 29.163214 -system.ruby.ST.latency_hist_seqr | 697 80.58% 80.58% | 80 9.25% 89.83% | 83 9.60% 99.42% | 2 0.23% 99.65% | 0 0.00% 99.65% | 1 0.12% 99.77% | 0 0.00% 99.77% | 1 0.12% 99.88% | 0 0.00% 99.88% | 1 0.12% 100.00% -system.ruby.ST.latency_hist_seqr::total 865 -system.ruby.ST.hit_latency_hist_seqr::bucket_size 4 -system.ruby.ST.hit_latency_hist_seqr::max_bucket 39 -system.ruby.ST.hit_latency_hist_seqr::samples 697 -system.ruby.ST.hit_latency_hist_seqr::mean 2.317073 -system.ruby.ST.hit_latency_hist_seqr::gmean 1.210984 -system.ruby.ST.hit_latency_hist_seqr::stdev 5.162159 -system.ruby.ST.hit_latency_hist_seqr | 654 93.83% 93.83% | 0 0.00% 93.83% | 0 0.00% 93.83% | 0 0.00% 93.83% | 0 0.00% 93.83% | 20 2.87% 96.70% | 23 3.30% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist_seqr::total 697 -system.ruby.ST.miss_latency_hist_seqr::bucket_size 32 -system.ruby.ST.miss_latency_hist_seqr::max_bucket 319 -system.ruby.ST.miss_latency_hist_seqr::samples 168 -system.ruby.ST.miss_latency_hist_seqr::mean 66.613095 -system.ruby.ST.miss_latency_hist_seqr::gmean 62.251080 -system.ruby.ST.miss_latency_hist_seqr::stdev 30.627944 -system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 80 47.62% 47.62% | 83 49.40% 97.02% | 2 1.19% 98.21% | 0 0.00% 98.21% | 1 0.60% 98.81% | 0 0.00% 98.81% | 1 0.60% 99.40% | 0 0.00% 99.40% | 1 0.60% 100.00% -system.ruby.ST.miss_latency_hist_seqr::total 168 -system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 -system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.latency_hist_seqr::samples 6413 -system.ruby.IFETCH.latency_hist_seqr::mean 8.941369 -system.ruby.IFETCH.latency_hist_seqr::gmean 1.542249 -system.ruby.IFETCH.latency_hist_seqr::stdev 26.742382 -system.ruby.IFETCH.latency_hist_seqr | 5828 90.88% 90.88% | 571 8.90% 99.78% | 4 0.06% 99.84% | 2 0.03% 99.88% | 4 0.06% 99.94% | 3 0.05% 99.98% | 0 0.00% 99.98% | 0 0.00% 99.98% | 0 0.00% 99.98% | 1 0.02% 100.00% -system.ruby.IFETCH.latency_hist_seqr::total 6413 -system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 8 -system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 79 -system.ruby.IFETCH.hit_latency_hist_seqr::samples 5828 -system.ruby.IFETCH.hit_latency_hist_seqr::mean 1.243480 -system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1.033914 -system.ruby.IFETCH.hit_latency_hist_seqr::stdev 2.376718 -system.ruby.IFETCH.hit_latency_hist_seqr | 5767 98.95% 98.95% | 0 0.00% 98.95% | 0 0.00% 98.95% | 60 1.03% 99.98% | 0 0.00% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist_seqr::total 5828 -system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 -system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.miss_latency_hist_seqr::samples 585 -system.ruby.IFETCH.miss_latency_hist_seqr::mean 85.630769 -system.ruby.IFETCH.miss_latency_hist_seqr::gmean 82.856413 -system.ruby.IFETCH.miss_latency_hist_seqr::stdev 36.234733 -system.ruby.IFETCH.miss_latency_hist_seqr | 0 0.00% 0.00% | 571 97.61% 97.61% | 4 0.68% 98.29% | 2 0.34% 98.63% | 4 0.68% 99.32% | 3 0.51% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 1 0.17% 100.00% -system.ruby.IFETCH.miss_latency_hist_seqr::total 585 -system.ruby.L1Cache.hit_mach_latency_hist_seqr::bucket_size 1 -system.ruby.L1Cache.hit_mach_latency_hist_seqr::max_bucket 9 -system.ruby.L1Cache.hit_mach_latency_hist_seqr::samples 7080 -system.ruby.L1Cache.hit_mach_latency_hist_seqr::mean 1 -system.ruby.L1Cache.hit_mach_latency_hist_seqr::gmean 1 -system.ruby.L1Cache.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 7080 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.hit_mach_latency_hist_seqr::total 7080 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::bucket_size 8 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::max_bucket 79 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::samples 204 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::mean 23.710784 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::gmean 23.661395 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::stdev 1.615711 -system.ruby.L2Cache.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 21 10.29% 10.29% | 182 89.22% 99.51% | 0 0.00% 99.51% | 1 0.49% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L2Cache.hit_mach_latency_hist_seqr::total 204 -system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 -system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 -system.ruby.Directory.miss_mach_latency_hist_seqr::samples 1179 -system.ruby.Directory.miss_mach_latency_hist_seqr::mean 79.365564 -system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 75.701428 -system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 33.123085 -system.ruby.Directory.miss_mach_latency_hist_seqr | 175 14.84% 14.84% | 983 83.38% 98.22% | 7 0.59% 98.81% | 3 0.25% 99.07% | 5 0.42% 99.49% | 5 0.42% 99.92% | 0 0.00% 99.92% | 0 0.00% 99.92% | 0 0.00% 99.92% | 1 0.08% 100.00% -system.ruby.Directory.miss_mach_latency_hist_seqr::total 1179 -system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 -system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 -system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1 -system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::stdev nan -system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 1 -system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 1 -system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::max_bucket 9 -system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::samples 1 -system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::stdev nan -system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::total 1 -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::bucket_size 1 -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::max_bucket 9 -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::samples 1 -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::stdev nan -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total 1 -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size 16 -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 159 -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 1 -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean 82 -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 82.000000 -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::samples 659 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::mean 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 659 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::total 659 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 4 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 39 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::samples 100 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::mean 23.960000 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::gmean 23.956283 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::stdev 0.400000 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 1.00% 1.00% | 99 99.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::total 100 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 426 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 75.791080 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 72.234894 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 27.150058 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 95 22.30% 22.30% | 327 76.76% 99.06% | 2 0.47% 99.53% | 0 0.00% 99.53% | 0 0.00% 99.53% | 2 0.47% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 426 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::samples 654 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::mean 1 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 654 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::total 654 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 4 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 39 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::samples 43 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::mean 22.348837 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::gmean 22.264733 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::stdev 1.938135 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 20 46.51% 46.51% | 23 53.49% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::total 43 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 168 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 66.613095 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 62.251080 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 30.627944 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 80 47.62% 47.62% | 83 49.40% 97.02% | 2 1.19% 98.21% | 0 0.00% 98.21% | 1 0.60% 98.81% | 0 0.00% 98.81% | 1 0.60% 99.40% | 0 0.00% 99.40% | 1 0.60% 100.00% -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 168 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::samples 5767 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::mean 1 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 5767 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::total 5767 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 8 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 79 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::samples 61 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::mean 24.262295 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::gmean 24.201824 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::stdev 2.048590 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 60 98.36% 98.36% | 0 0.00% 98.36% | 1 1.64% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::total 61 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 585 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 85.630769 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 82.856413 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 36.234733 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 571 97.61% 97.61% | 4 0.68% 98.29% | 2 0.34% 98.63% | 4 0.68% 99.32% | 3 0.51% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 1 0.17% 100.00% -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 585 -system.ruby.Directory_Controller.GETX 208 0.00% 0.00% -system.ruby.Directory_Controller.GETS 1017 0.00% 0.00% -system.ruby.Directory_Controller.Lockdown 11 0.00% 0.00% -system.ruby.Directory_Controller.Unlockdown 11 0.00% 0.00% -system.ruby.Directory_Controller.Data_Owner 9 0.00% 0.00% -system.ruby.Directory_Controller.Data_All_Tokens 220 0.00% 0.00% -system.ruby.Directory_Controller.Ack_Owner 29 0.00% 0.00% -system.ruby.Directory_Controller.Ack_Owner_All_Tokens 905 0.00% 0.00% -system.ruby.Directory_Controller.Ack_All_Tokens 34 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 1179 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 229 0.00% 0.00% -system.ruby.Directory_Controller.O.GETX 168 0.00% 0.00% -system.ruby.Directory_Controller.O.GETS 1011 0.00% 0.00% -system.ruby.Directory_Controller.O.Ack_All_Tokens 34 0.00% 0.00% -system.ruby.Directory_Controller.NO.GETX 17 0.00% 0.00% -system.ruby.Directory_Controller.NO.Data_Owner 9 0.00% 0.00% -system.ruby.Directory_Controller.NO.Data_All_Tokens 220 0.00% 0.00% -system.ruby.Directory_Controller.NO.Ack_Owner 29 0.00% 0.00% -system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens 905 0.00% 0.00% -system.ruby.Directory_Controller.L.Unlockdown 11 0.00% 0.00% -system.ruby.Directory_Controller.O_W.GETX 23 0.00% 0.00% -system.ruby.Directory_Controller.O_W.GETS 6 0.00% 0.00% -system.ruby.Directory_Controller.O_W.Memory_Ack 229 0.00% 0.00% -system.ruby.Directory_Controller.L_NO_W.Memory_Data 11 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.Lockdown 11 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.Memory_Data 1168 0.00% 0.00% -system.ruby.L1Cache_Controller.Load 1185 0.00% 0.00% -system.ruby.L1Cache_Controller.Ifetch 6413 0.00% 0.00% -system.ruby.L1Cache_Controller.Store 865 0.00% 0.00% -system.ruby.L1Cache_Controller.L1_Replacement 1368 0.00% 0.00% -system.ruby.L1Cache_Controller.Data_Shared 161 0.00% 0.00% -system.ruby.L1Cache_Controller.Data_All_Tokens 1222 0.00% 0.00% -system.ruby.L1Cache_Controller.Ack 1 0.00% 0.00% -system.ruby.L1Cache_Controller.Own_Lock_or_Unlock 22 0.00% 0.00% -system.ruby.L1Cache_Controller.Request_Timeout 11 0.00% 0.00% -system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers 1221 0.00% 0.00% -system.ruby.L1Cache_Controller.NP.Load 526 0.00% 0.00% -system.ruby.L1Cache_Controller.NP.Ifetch 646 0.00% 0.00% -system.ruby.L1Cache_Controller.NP.Store 191 0.00% 0.00% -system.ruby.L1Cache_Controller.S.Load 153 0.00% 0.00% -system.ruby.L1Cache_Controller.S.Ifetch 331 0.00% 0.00% -system.ruby.L1Cache_Controller.S.Store 20 0.00% 0.00% -system.ruby.L1Cache_Controller.S.L1_Replacement 141 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Load 181 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Ifetch 3196 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Store 33 0.00% 0.00% -system.ruby.L1Cache_Controller.M.L1_Replacement 946 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock 11 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.Load 218 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.Store 265 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.L1_Replacement 268 0.00% 0.00% -system.ruby.L1Cache_Controller.M_W.Load 84 0.00% 0.00% -system.ruby.L1Cache_Controller.M_W.Ifetch 2240 0.00% 0.00% -system.ruby.L1Cache_Controller.M_W.Store 25 0.00% 0.00% -system.ruby.L1Cache_Controller.M_W.L1_Replacement 9 0.00% 0.00% -system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers 985 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_W.Load 23 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_W.Store 331 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_W.L1_Replacement 4 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_W.Use_TimeoutNoStarvers 236 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.Data_All_Tokens 191 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.Ack 1 0.00% 0.00% -system.ruby.L1Cache_Controller.SM.Data_All_Tokens 20 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Data_Shared 161 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Data_All_Tokens 1011 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Own_Lock_or_Unlock 11 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Request_Timeout 11 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETS 1123 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETS_Last_Token 49 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETX 211 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement 1266 0.00% 0.00% -system.ruby.L2Cache_Controller.Writeback_Shared_Data 84 0.00% 0.00% -system.ruby.L2Cache_Controller.Writeback_All_Tokens 1271 0.00% 0.00% -system.ruby.L2Cache_Controller.Persistent_GETS 11 0.00% 0.00% -system.ruby.L2Cache_Controller.Own_Lock_or_Unlock 11 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETS 1011 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETX 166 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.Writeback_Shared_Data 81 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.Writeback_All_Tokens 1193 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.Own_Lock_or_Unlock 11 0.00% 0.00% -system.ruby.L2Cache_Controller.I.L1_GETX 1 0.00% 0.00% -system.ruby.L2Cache_Controller.I.L2_Replacement 69 0.00% 0.00% -system.ruby.L2Cache_Controller.I.Writeback_Shared_Data 3 0.00% 0.00% -system.ruby.L2Cache_Controller.I.Writeback_All_Tokens 21 0.00% 0.00% -system.ruby.L2Cache_Controller.S.L1_GETS_Last_Token 49 0.00% 0.00% -system.ruby.L2Cache_Controller.S.L1_GETX 1 0.00% 0.00% -system.ruby.L2Cache_Controller.S.L2_Replacement 34 0.00% 0.00% -system.ruby.L2Cache_Controller.O.L1_GETX 17 0.00% 0.00% -system.ruby.L2Cache_Controller.O.L2_Replacement 38 0.00% 0.00% -system.ruby.L2Cache_Controller.O.Writeback_All_Tokens 57 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETS 112 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETX 26 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement 1125 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.Persistent_GETS 11 0.00% 0.00% - ----------- End Simulation Statistics ---------- diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,1514 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000 -time_sync_spin_threshold=100000 - -[system] -type=System -children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges=0:268435455:0:0:0:0 -memories=system.mem_ctrls -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.sys_port_proxy.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=TimingSimpleCPU -children=clk_domain dtb interrupts isa itb tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu.clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1] -icache_port=system.ruby.l1_cntrl0.sequencer.slave[0] - -[system.cpu.clk_domain] -type=SrcClockDomain -clock=1 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=hello -cwd= -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/linux/hello -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000 - -[system.mem_ctrls] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -page_policy=open_adaptive -power_model=Null -range=0:268435455:5:19:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10 -static_frontend_latency=10 -tBURST=5 -tCCD_L=0 -tCK=1 -tCL=14 -tCS=3 -tRAS=35 -tRCD=14 -tREFI=7800 -tRFC=260 -tRP=14 -tRRD=6 -tRRD_L=0 -tRTP=8 -tRTW=3 -tWR=15 -tWTR=8 -tXAW=30 -tXP=6 -tXPDLL=0 -tXS=270 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.ruby.dir_cntrl0.memory - -[system.ruby] -type=RubySystem -children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network -access_backing_store=false -all_instructions=false -block_size_bytes=64 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hot_lines=false -memory_size_bits=48 -num_of_sequencers=1 -number_of_virtual_networks=6 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -phys_mem=Null -power_model=Null -randomization=false - -[system.ruby.clk_domain] -type=SrcClockDomain -clock=1 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.ruby.dir_cntrl0] -type=Directory_Controller -children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir probeFilter requestToDir responseFromDir responseFromMemory responseToDir triggerQueue unblockToDir -buffer_size=0 -clk_domain=system.ruby.clk_domain -cluster_id=0 -default_p_state=UNDEFINED -directory=system.ruby.dir_cntrl0.directory -dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir -dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir -eventq_index=0 -forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir -from_memory_controller_latency=2 -full_bit_dir_enabled=false -number_of_TBEs=256 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -probeFilter=system.ruby.dir_cntrl0.probeFilter -probe_filter_enabled=false -recycle_latency=10 -requestToDir=system.ruby.dir_cntrl0.requestToDir -responseFromDir=system.ruby.dir_cntrl0.responseFromDir -responseFromMemory=system.ruby.dir_cntrl0.responseFromMemory -responseToDir=system.ruby.dir_cntrl0.responseToDir -ruby_system=system.ruby -system=system -to_memory_controller_latency=1 -transitions_per_cycle=4 -triggerQueue=system.ruby.dir_cntrl0.triggerQueue -unblockToDir=system.ruby.dir_cntrl0.unblockToDir -version=0 -memory=system.mem_ctrls.port - -[system.ruby.dir_cntrl0.directory] -type=RubyDirectoryMemory -eventq_index=0 -numa_high_bit=5 -size=268435456 -version=0 - -[system.ruby.dir_cntrl0.dmaRequestToDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -slave=system.ruby.network.master[5] - -[system.ruby.dir_cntrl0.dmaResponseFromDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -master=system.ruby.network.slave[5] - -[system.ruby.dir_cntrl0.forwardFromDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[3] - -[system.ruby.dir_cntrl0.probeFilter] -type=RubyCache -children=replacement_policy -assoc=4 -block_size=0 -dataAccessLatency=1 -dataArrayBanks=1 -eventq_index=0 -is_icache=false -replacement_policy=system.ruby.dir_cntrl0.probeFilter.replacement_policy -resourceStalls=false -ruby_system=system.ruby -size=1024 -start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 - -[system.ruby.dir_cntrl0.probeFilter.replacement_policy] -type=PseudoLRUReplacementPolicy -assoc=4 -block_size=64 -eventq_index=0 -size=1024 - -[system.ruby.dir_cntrl0.requestToDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[4] - -[system.ruby.dir_cntrl0.responseFromDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[4] - -[system.ruby.dir_cntrl0.responseFromMemory] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false - -[system.ruby.dir_cntrl0.responseToDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[3] - -[system.ruby.dir_cntrl0.triggerQueue] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.dir_cntrl0.unblockToDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[2] - -[system.ruby.l1_cntrl0] -type=L1Cache_Controller -children=L1Dcache L1Icache L2cache forwardToCache mandatoryQueue requestFromCache responseFromCache responseToCache sequencer triggerQueue unblockFromCache -L1Dcache=system.ruby.l1_cntrl0.L1Dcache -L1Icache=system.ruby.l1_cntrl0.L1Icache -L2cache=system.ruby.l1_cntrl0.L2cache -buffer_size=0 -cache_response_latency=10 -clk_domain=system.cpu.clk_domain -cluster_id=0 -default_p_state=UNDEFINED -eventq_index=0 -forwardToCache=system.ruby.l1_cntrl0.forwardToCache -issue_latency=2 -l2_cache_hit_latency=10 -mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue -no_mig_atomic=true -number_of_TBEs=256 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -recycle_latency=10 -requestFromCache=system.ruby.l1_cntrl0.requestFromCache -responseFromCache=system.ruby.l1_cntrl0.responseFromCache -responseToCache=system.ruby.l1_cntrl0.responseToCache -ruby_system=system.ruby -send_evictions=false -sequencer=system.ruby.l1_cntrl0.sequencer -system=system -transitions_per_cycle=4 -triggerQueue=system.ruby.l1_cntrl0.triggerQueue -unblockFromCache=system.ruby.l1_cntrl0.unblockFromCache -version=0 - -[system.ruby.l1_cntrl0.L1Dcache] -type=RubyCache -children=replacement_policy -assoc=2 -block_size=0 -dataAccessLatency=1 -dataArrayBanks=1 -eventq_index=0 -is_icache=false -replacement_policy=system.ruby.l1_cntrl0.L1Dcache.replacement_policy -resourceStalls=false -ruby_system=system.ruby -size=256 -start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 - -[system.ruby.l1_cntrl0.L1Dcache.replacement_policy] -type=PseudoLRUReplacementPolicy -assoc=2 -block_size=64 -eventq_index=0 -size=256 - -[system.ruby.l1_cntrl0.L1Icache] -type=RubyCache -children=replacement_policy -assoc=2 -block_size=0 -dataAccessLatency=1 -dataArrayBanks=1 -eventq_index=0 -is_icache=true -replacement_policy=system.ruby.l1_cntrl0.L1Icache.replacement_policy -resourceStalls=false -ruby_system=system.ruby -size=256 -start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 - -[system.ruby.l1_cntrl0.L1Icache.replacement_policy] -type=PseudoLRUReplacementPolicy -assoc=2 -block_size=64 -eventq_index=0 -size=256 - -[system.ruby.l1_cntrl0.L2cache] -type=RubyCache -children=replacement_policy -assoc=2 -block_size=0 -dataAccessLatency=1 -dataArrayBanks=1 -eventq_index=0 -is_icache=false -replacement_policy=system.ruby.l1_cntrl0.L2cache.replacement_policy -resourceStalls=false -ruby_system=system.ruby -size=512 -start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 - -[system.ruby.l1_cntrl0.L2cache.replacement_policy] -type=PseudoLRUReplacementPolicy -assoc=2 -block_size=64 -eventq_index=0 -size=512 - -[system.ruby.l1_cntrl0.forwardToCache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[0] - -[system.ruby.l1_cntrl0.mandatoryQueue] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false - -[system.ruby.l1_cntrl0.requestFromCache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[0] - -[system.ruby.l1_cntrl0.responseFromCache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[1] - -[system.ruby.l1_cntrl0.responseToCache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[1] - -[system.ruby.l1_cntrl0.sequencer] -type=RubySequencer -clk_domain=system.cpu.clk_domain -coreid=99 -dcache=system.ruby.l1_cntrl0.L1Dcache -dcache_hit_latency=1 -deadlock_threshold=500000 -default_p_state=UNDEFINED -eventq_index=0 -garnet_standalone=false -icache=system.ruby.l1_cntrl0.L1Icache -icache_hit_latency=1 -is_cpu_sequencer=true -max_outstanding_requests=16 -no_retry_on_stall=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -ruby_system=system.ruby -support_data_reqs=true -support_inst_reqs=true -system=system -using_ruby_tester=false -version=0 -slave=system.cpu.icache_port system.cpu.dcache_port - -[system.ruby.l1_cntrl0.triggerQueue] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false - -[system.ruby.l1_cntrl0.unblockFromCache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[2] - -[system.ruby.memctrl_clk_domain] -type=DerivedClockDomain -clk_divider=3 -clk_domain=system.ruby.clk_domain -eventq_index=0 - -[system.ruby.network] -type=SimpleNetwork -children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_link_buffers40 int_link_buffers41 int_link_buffers42 int_link_buffers43 int_link_buffers44 int_link_buffers45 int_link_buffers46 int_link_buffers47 int_links0 int_links1 int_links2 int_links3 routers0 routers1 routers2 -adaptive_routing=false -buffer_size=0 -clk_domain=system.ruby.clk_domain -control_msg_size=8 -default_p_state=UNDEFINED -endpoint_bandwidth=1000 -eventq_index=0 -ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 -int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 system.ruby.network.int_link_buffers40 system.ruby.network.int_link_buffers41 system.ruby.network.int_link_buffers42 system.ruby.network.int_link_buffers43 system.ruby.network.int_link_buffers44 system.ruby.network.int_link_buffers45 system.ruby.network.int_link_buffers46 system.ruby.network.int_link_buffers47 -int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 -netifs= -number_of_virtual_networks=6 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 -ruby_system=system.ruby -topology=Crossbar -master=system.ruby.l1_cntrl0.forwardToCache.slave system.ruby.l1_cntrl0.responseToCache.slave system.ruby.dir_cntrl0.unblockToDir.slave system.ruby.dir_cntrl0.responseToDir.slave system.ruby.dir_cntrl0.requestToDir.slave system.ruby.dir_cntrl0.dmaRequestToDir.slave -slave=system.ruby.l1_cntrl0.requestFromCache.master system.ruby.l1_cntrl0.responseFromCache.master system.ruby.l1_cntrl0.unblockFromCache.master system.ruby.dir_cntrl0.forwardFromDir.master system.ruby.dir_cntrl0.responseFromDir.master system.ruby.dir_cntrl0.dmaResponseFromDir.master - -[system.ruby.network.ext_links0] -type=SimpleExtLink -bandwidth_factor=16 -eventq_index=0 -ext_node=system.ruby.l1_cntrl0 -int_node=system.ruby.network.routers0 -latency=1 -link_id=0 -weight=1 - -[system.ruby.network.ext_links1] -type=SimpleExtLink -bandwidth_factor=16 -eventq_index=0 -ext_node=system.ruby.dir_cntrl0 -int_node=system.ruby.network.routers1 -latency=1 -link_id=1 -weight=1 - -[system.ruby.network.int_link_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers15] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers16] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers17] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers18] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers19] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers20] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers21] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers22] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers23] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers24] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers25] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers26] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers27] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers28] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers29] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers30] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers31] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers32] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers33] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers34] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers35] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers36] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers37] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers38] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers39] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers40] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers41] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers42] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers43] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers44] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers45] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers46] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers47] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_links0] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers2 -eventq_index=0 -latency=1 -link_id=2 -src_node=system.ruby.network.routers0 -src_outport= -weight=1 - -[system.ruby.network.int_links1] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers2 -eventq_index=0 -latency=1 -link_id=3 -src_node=system.ruby.network.routers1 -src_outport= -weight=1 - -[system.ruby.network.int_links2] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers0 -eventq_index=0 -latency=1 -link_id=4 -src_node=system.ruby.network.routers2 -src_outport= -weight=1 - -[system.ruby.network.int_links3] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers1 -eventq_index=0 -latency=1 -link_id=5 -src_node=system.ruby.network.routers2 -src_outport= -weight=1 - -[system.ruby.network.routers0] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 system.ruby.network.routers0.port_buffers12 system.ruby.network.routers0.port_buffers13 system.ruby.network.routers0.port_buffers14 system.ruby.network.routers0.port_buffers15 system.ruby.network.routers0.port_buffers16 system.ruby.network.routers0.port_buffers17 -power_model=Null -router_id=0 -virt_nets=6 - -[system.ruby.network.routers0.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers15] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers16] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers17] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 system.ruby.network.routers1.port_buffers12 system.ruby.network.routers1.port_buffers13 system.ruby.network.routers1.port_buffers14 system.ruby.network.routers1.port_buffers15 system.ruby.network.routers1.port_buffers16 system.ruby.network.routers1.port_buffers17 -power_model=Null -router_id=1 -virt_nets=6 - -[system.ruby.network.routers1.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers15] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers16] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers17] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19 system.ruby.network.routers2.port_buffers20 system.ruby.network.routers2.port_buffers21 system.ruby.network.routers2.port_buffers22 system.ruby.network.routers2.port_buffers23 -power_model=Null -router_id=2 -virt_nets=6 - -[system.ruby.network.routers2.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers15] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers16] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers17] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers18] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers19] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers20] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers21] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers22] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers23] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.sys_port_proxy] -type=RubyPortProxy -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_cpu_sequencer=true -no_retry_on_stall=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -ruby_system=system.ruby -support_data_reqs=true -support_inst_reqs=true -system=system -using_ruby_tester=false -version=0 -slave=system.system_port - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,10 +0,0 @@ -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,15 +0,0 @@ -Redirecting stdout to build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer/simout -Redirecting stderr to build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 13 2016 20:24:36 -gem5 started Oct 13 2016 20:24:58 -gem5 executing on e108600-lin, pid 38872 -command line: /work/curdun01/gem5-external.hg/build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer - -Global frequency set at 1000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Hello world! -Exiting @ tick 93323 because target called exit() diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,782 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000093 # Number of seconds simulated -sim_ticks 93323 # Number of ticks simulated -final_tick 93323 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 111182 # Simulator instruction rate (inst/s) -host_op_rate 111161 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1619882 # Simulator tick rate (ticks/s) -host_mem_usage 412912 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host -sim_insts 6403 # Number of instructions simulated -sim_ops 6403 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 93323 # Cumulative time (in ticks) in various power states -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 74240 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 74240 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14080 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 14080 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 1160 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 1160 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 220 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 220 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 795516646 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 795516646 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 150873847 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 150873847 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 946390493 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 946390493 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 1160 # Number of read requests accepted -system.mem_ctrls.writeReqs 220 # Number of write requests accepted -system.mem_ctrls.readBursts 1160 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 220 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 63488 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 10752 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 5248 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 74240 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 14080 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 168 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 109 # Number of DRAM write bursts merged with an existing one -system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 86 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 52 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 82 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 77 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 90 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 18 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 1 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 3 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::9 1 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 54 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 47 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 22 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 358 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 60 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 41 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 17 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 6 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 2 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 15 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 42 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts -system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 93245 # Total gap between requests -system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 1160 # Read request sizes (log2) -system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 220 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 992 # 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write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 185 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 364.627027 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 225.304848 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 344.102671 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 47 25.41% 25.41% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 51 27.57% 52.97% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 22 11.89% 64.86% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 11 5.95% 70.81% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 10 5.41% 76.22% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 6 3.24% 79.46% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 6 3.24% 82.70% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 9 4.86% 87.57% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 23 12.43% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 185 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 5 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 135.600000 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 103.520831 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 76.774345 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-23 1 20.00% 20.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::120-127 1 20.00% 40.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::128-135 1 20.00% 60.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::184-191 1 20.00% 80.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::216-223 1 20.00% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 5 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 5 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.400000 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.381380 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 0.894427 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 4 80.00% 80.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 1 20.00% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 5 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 12811 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 31659 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 4960 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 12.91 # Average queueing delay per DRAM burst -system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 31.91 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 680.30 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 56.23 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 795.52 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 150.87 # Average system write bandwidth in MiByte/s -system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 5.75 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 5.31 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 0.44 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 22.62 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 805 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 78 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 81.15 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 70.27 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 67.57 # Average gap between requests -system.mem_ctrls.pageHitRate 80.05 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 449820 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 235704 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 4672416 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 192096 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 7375680.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 7678128 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 246528 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.actPowerDownEnergy 28111488 # Energy for active power-down per rank (pJ) -system.mem_ctrls_0.prePowerDownEnergy 4554240 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_0.selfRefreshEnergy 1112640 # Energy for self refresh per rank (pJ) -system.mem_ctrls_0.totalEnergy 54628740 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 585.372738 # Core power per rank (mW) -system.mem_ctrls_0.totalIdleTime 75800 # Total Idle time Per DRAM Rank -system.mem_ctrls_0.memoryStateTime::IDLE 328 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 3126 # Time in different power states -system.mem_ctrls_0.memoryStateTime::SREF 2335 # Time in different power states -system.mem_ctrls_0.memoryStateTime::PRE_PDN 11860 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 14026 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 61648 # Time in different power states -system.mem_ctrls_1.actEnergy 913920 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 479136 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 6660192 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 492768 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 6761040.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 10312440 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 226560 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.actPowerDownEnergy 31424328 # Energy for active power-down per rank (pJ) -system.mem_ctrls_1.prePowerDownEnergy 462720 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrls_1.totalEnergy 57733104 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 618.637463 # Core power per rank (mW) -system.mem_ctrls_1.totalIdleTime 69937 # Total Idle time Per DRAM Rank -system.mem_ctrls_1.memoryStateTime::IDLE 212 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 2860 # Time in different power states -system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 1205 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 20133 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT_PDN 68913 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 93323 # Cumulative time (in ticks) in various power states -system.cpu.clk_domain.clock 1 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1185 # DTB read hits -system.cpu.dtb.read_misses 7 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 1192 # DTB read accesses -system.cpu.dtb.write_hits 865 # DTB write hits -system.cpu.dtb.write_misses 3 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 868 # DTB write accesses -system.cpu.dtb.data_hits 2050 # DTB hits -system.cpu.dtb.data_misses 10 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 2060 # DTB accesses -system.cpu.itb.fetch_hits 6414 # ITB hits -system.cpu.itb.fetch_misses 17 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 6431 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 93323 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 93323 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 6403 # Number of instructions committed -system.cpu.committedOps 6403 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 6329 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses -system.cpu.num_func_calls 251 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 754 # number of instructions that are conditional controls -system.cpu.num_int_insts 6329 # number of integer instructions -system.cpu.num_fp_insts 10 # number of float instructions -system.cpu.num_int_register_reads 8297 # number of times the integer registers were read -system.cpu.num_int_register_writes 4575 # number of times the integer registers were written -system.cpu.num_fp_register_reads 8 # number of times the floating registers were read -system.cpu.num_fp_register_writes 2 # number of times the floating registers were written -system.cpu.num_mem_refs 2060 # number of memory refs -system.cpu.num_load_insts 1192 # Number of load instructions -system.cpu.num_store_insts 868 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 93323 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 1056 # Number of branches fetched -system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction -system.cpu.op_class::IntAlu 4331 67.53% 67.83% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.02% 67.85% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 67.85% # Class of executed instruction -system.cpu.op_class::FloatAdd 2 0.03% 67.88% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::MemRead 1191 18.57% 86.45% # Class of executed instruction -system.cpu.op_class::MemWrite 861 13.43% 99.88% # Class of executed instruction -system.cpu.op_class::FloatMemRead 1 0.02% 99.89% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 7 0.11% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 6413 # Class of executed instruction -system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.pwrStateResidencyTicks::UNDEFINED 93323 # Cumulative time (in ticks) in various power states -system.ruby.outstanding_req_hist_seqr::bucket_size 1 -system.ruby.outstanding_req_hist_seqr::max_bucket 9 -system.ruby.outstanding_req_hist_seqr::samples 8464 -system.ruby.outstanding_req_hist_seqr::mean 1 -system.ruby.outstanding_req_hist_seqr::gmean 1 -system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 8464 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist_seqr::total 8464 -system.ruby.latency_hist_seqr::bucket_size 64 -system.ruby.latency_hist_seqr::max_bucket 639 -system.ruby.latency_hist_seqr::samples 8463 -system.ruby.latency_hist_seqr::mean 10.027177 -system.ruby.latency_hist_seqr::gmean 1.860537 -system.ruby.latency_hist_seqr::stdev 25.112208 -system.ruby.latency_hist_seqr | 8219 97.12% 97.12% | 231 2.73% 99.85% | 1 0.01% 99.86% | 1 0.01% 99.87% | 5 0.06% 99.93% | 5 0.06% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% -system.ruby.latency_hist_seqr::total 8463 -system.ruby.hit_latency_hist_seqr::bucket_size 2 -system.ruby.hit_latency_hist_seqr::max_bucket 19 -system.ruby.hit_latency_hist_seqr::samples 7303 -system.ruby.hit_latency_hist_seqr::mean 1.277968 -system.ruby.hit_latency_hist_seqr::gmean 1.068925 -system.ruby.hit_latency_hist_seqr::stdev 1.644014 -system.ruby.hit_latency_hist_seqr | 7100 97.22% 97.22% | 0 0.00% 97.22% | 0 0.00% 97.22% | 0 0.00% 97.22% | 0 0.00% 97.22% | 203 2.78% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist_seqr::total 7303 -system.ruby.miss_latency_hist_seqr::bucket_size 64 -system.ruby.miss_latency_hist_seqr::max_bucket 639 -system.ruby.miss_latency_hist_seqr::samples 1160 -system.ruby.miss_latency_hist_seqr::mean 65.109483 -system.ruby.miss_latency_hist_seqr::gmean 60.947221 -system.ruby.miss_latency_hist_seqr::stdev 32.683425 -system.ruby.miss_latency_hist_seqr | 916 78.97% 78.97% | 231 19.91% 98.88% | 1 0.09% 98.97% | 1 0.09% 99.05% | 5 0.43% 99.48% | 5 0.43% 99.91% | 0 0.00% 99.91% | 0 0.00% 99.91% | 0 0.00% 99.91% | 1 0.09% 100.00% -system.ruby.miss_latency_hist_seqr::total 1160 -system.ruby.Directory.incomplete_times_seqr 1159 -system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits -system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses -system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses -system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 93323 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.L1Dcache.demand_hits 1333 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 717 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2050 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Icache.demand_hits 5767 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Icache.demand_misses 646 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Icache.demand_accesses 6413 # Number of cache demand accesses -system.ruby.l1_cntrl0.L2cache.demand_hits 203 # Number of cache demand hits -system.ruby.l1_cntrl0.L2cache.demand_misses 1160 # Number of cache demand misses -system.ruby.l1_cntrl0.L2cache.demand_accesses 1363 # Number of cache demand accesses -system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 93323 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 93323 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.fully_busy_cycles 7 # cycles for which number of transistions == max transitions -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 93323 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.percent_links_utilized 4.809104 -system.ruby.network.routers0.msg_count.Request_Control::2 1160 -system.ruby.network.routers0.msg_count.Response_Data::4 1160 -system.ruby.network.routers0.msg_count.Writeback_Data::5 220 -system.ruby.network.routers0.msg_count.Writeback_Control::2 1144 -system.ruby.network.routers0.msg_count.Writeback_Control::3 1144 -system.ruby.network.routers0.msg_count.Writeback_Control::5 924 -system.ruby.network.routers0.msg_count.Unblock_Control::5 1160 -system.ruby.network.routers0.msg_bytes.Request_Control::2 9280 -system.ruby.network.routers0.msg_bytes.Response_Data::4 83520 -system.ruby.network.routers0.msg_bytes.Writeback_Data::5 15840 -system.ruby.network.routers0.msg_bytes.Writeback_Control::2 9152 -system.ruby.network.routers0.msg_bytes.Writeback_Control::3 9152 -system.ruby.network.routers0.msg_bytes.Writeback_Control::5 7392 -system.ruby.network.routers0.msg_bytes.Unblock_Control::5 9280 -system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 93323 # Cumulative time (in ticks) in various power states -system.ruby.network.routers1.percent_links_utilized 4.808836 -system.ruby.network.routers1.msg_count.Request_Control::2 1160 -system.ruby.network.routers1.msg_count.Response_Data::4 1160 -system.ruby.network.routers1.msg_count.Writeback_Data::5 220 -system.ruby.network.routers1.msg_count.Writeback_Control::2 1144 -system.ruby.network.routers1.msg_count.Writeback_Control::3 1144 -system.ruby.network.routers1.msg_count.Writeback_Control::5 924 -system.ruby.network.routers1.msg_count.Unblock_Control::5 1159 -system.ruby.network.routers1.msg_bytes.Request_Control::2 9280 -system.ruby.network.routers1.msg_bytes.Response_Data::4 83520 -system.ruby.network.routers1.msg_bytes.Writeback_Data::5 15840 -system.ruby.network.routers1.msg_bytes.Writeback_Control::2 9152 -system.ruby.network.routers1.msg_bytes.Writeback_Control::3 9152 -system.ruby.network.routers1.msg_bytes.Writeback_Control::5 7392 -system.ruby.network.routers1.msg_bytes.Unblock_Control::5 9272 -system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 93323 # Cumulative time (in ticks) in various power states -system.ruby.network.routers2.percent_links_utilized 4.809104 -system.ruby.network.routers2.msg_count.Request_Control::2 1160 -system.ruby.network.routers2.msg_count.Response_Data::4 1160 -system.ruby.network.routers2.msg_count.Writeback_Data::5 220 -system.ruby.network.routers2.msg_count.Writeback_Control::2 1144 -system.ruby.network.routers2.msg_count.Writeback_Control::3 1144 -system.ruby.network.routers2.msg_count.Writeback_Control::5 924 -system.ruby.network.routers2.msg_count.Unblock_Control::5 1160 -system.ruby.network.routers2.msg_bytes.Request_Control::2 9280 -system.ruby.network.routers2.msg_bytes.Response_Data::4 83520 -system.ruby.network.routers2.msg_bytes.Writeback_Data::5 15840 -system.ruby.network.routers2.msg_bytes.Writeback_Control::2 9152 -system.ruby.network.routers2.msg_bytes.Writeback_Control::3 9152 -system.ruby.network.routers2.msg_bytes.Writeback_Control::5 7392 -system.ruby.network.routers2.msg_bytes.Unblock_Control::5 9280 -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 93323 # Cumulative time (in ticks) in various power states -system.ruby.network.msg_count.Request_Control 3480 -system.ruby.network.msg_count.Response_Data 3480 -system.ruby.network.msg_count.Writeback_Data 660 -system.ruby.network.msg_count.Writeback_Control 9636 -system.ruby.network.msg_count.Unblock_Control 3479 -system.ruby.network.msg_byte.Request_Control 27840 -system.ruby.network.msg_byte.Response_Data 250560 -system.ruby.network.msg_byte.Writeback_Data 47520 -system.ruby.network.msg_byte.Writeback_Control 77088 -system.ruby.network.msg_byte.Unblock_Control 27832 -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 93323 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.throttle0.link_utilization 6.206401 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1160 -system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1144 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 83520 -system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 9152 -system.ruby.network.routers0.throttle1.link_utilization 3.411806 -system.ruby.network.routers0.throttle1.msg_count.Request_Control::2 1160 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::5 220 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::2 1144 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::5 924 -system.ruby.network.routers0.throttle1.msg_count.Unblock_Control::5 1160 -system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::2 9280 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::5 15840 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::2 9152 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::5 7392 -system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::5 9280 -system.ruby.network.routers1.throttle0.link_utilization 3.411271 -system.ruby.network.routers1.throttle0.msg_count.Request_Control::2 1160 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::5 220 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::2 1144 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::5 924 -system.ruby.network.routers1.throttle0.msg_count.Unblock_Control::5 1159 -system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::2 9280 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::5 15840 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::2 9152 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::5 7392 -system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::5 9272 -system.ruby.network.routers1.throttle1.link_utilization 6.206401 -system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1160 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1144 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 83520 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 9152 -system.ruby.network.routers2.throttle0.link_utilization 6.206401 -system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1160 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1144 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 83520 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 9152 -system.ruby.network.routers2.throttle1.link_utilization 3.411806 -system.ruby.network.routers2.throttle1.msg_count.Request_Control::2 1160 -system.ruby.network.routers2.throttle1.msg_count.Writeback_Data::5 220 -system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::2 1144 -system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::5 924 -system.ruby.network.routers2.throttle1.msg_count.Unblock_Control::5 1160 -system.ruby.network.routers2.throttle1.msg_bytes.Request_Control::2 9280 -system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Data::5 15840 -system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::2 9152 -system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::5 7392 -system.ruby.network.routers2.throttle1.msg_bytes.Unblock_Control::5 9280 -system.ruby.LD.latency_hist_seqr::bucket_size 64 -system.ruby.LD.latency_hist_seqr::max_bucket 639 -system.ruby.LD.latency_hist_seqr::samples 1185 -system.ruby.LD.latency_hist_seqr::mean 23.222785 -system.ruby.LD.latency_hist_seqr::gmean 5.170883 -system.ruby.LD.latency_hist_seqr::stdev 33.395677 -system.ruby.LD.latency_hist_seqr | 1100 92.83% 92.83% | 82 6.92% 99.75% | 0 0.00% 99.75% | 0 0.00% 99.75% | 0 0.00% 99.75% | 3 0.25% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist_seqr::total 1185 -system.ruby.LD.hit_latency_hist_seqr::bucket_size 2 -system.ruby.LD.hit_latency_hist_seqr::max_bucket 19 -system.ruby.LD.hit_latency_hist_seqr::samples 764 -system.ruby.LD.hit_latency_hist_seqr::mean 2.374346 -system.ruby.LD.hit_latency_hist_seqr::gmean 1.390347 -system.ruby.LD.hit_latency_hist_seqr::stdev 3.445311 -system.ruby.LD.hit_latency_hist_seqr | 659 86.26% 86.26% | 0 0.00% 86.26% | 0 0.00% 86.26% | 0 0.00% 86.26% | 0 0.00% 86.26% | 105 13.74% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist_seqr::total 764 -system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 -system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 -system.ruby.LD.miss_latency_hist_seqr::samples 421 -system.ruby.LD.miss_latency_hist_seqr::mean 61.057007 -system.ruby.LD.miss_latency_hist_seqr::gmean 56.073786 -system.ruby.LD.miss_latency_hist_seqr::stdev 29.948950 -system.ruby.LD.miss_latency_hist_seqr | 336 79.81% 79.81% | 82 19.48% 99.29% | 0 0.00% 99.29% | 0 0.00% 99.29% | 0 0.00% 99.29% | 3 0.71% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist_seqr::total 421 -system.ruby.ST.latency_hist_seqr::bucket_size 16 -system.ruby.ST.latency_hist_seqr::max_bucket 159 -system.ruby.ST.latency_hist_seqr::samples 865 -system.ruby.ST.latency_hist_seqr::mean 11.254335 -system.ruby.ST.latency_hist_seqr::gmean 2.251088 -system.ruby.ST.latency_hist_seqr::stdev 22.172254 -system.ruby.ST.latency_hist_seqr | 707 81.73% 81.73% | 44 5.09% 86.82% | 0 0.00% 86.82% | 73 8.44% 95.26% | 36 4.16% 99.42% | 4 0.46% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist_seqr::total 865 -system.ruby.ST.hit_latency_hist_seqr::bucket_size 2 -system.ruby.ST.hit_latency_hist_seqr::max_bucket 19 -system.ruby.ST.hit_latency_hist_seqr::samples 707 -system.ruby.ST.hit_latency_hist_seqr::mean 1.466761 -system.ruby.ST.hit_latency_hist_seqr::gmean 1.118428 -system.ruby.ST.hit_latency_hist_seqr::stdev 2.110935 -system.ruby.ST.hit_latency_hist_seqr | 674 95.33% 95.33% | 0 0.00% 95.33% | 0 0.00% 95.33% | 0 0.00% 95.33% | 0 0.00% 95.33% | 33 4.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist_seqr::total 707 -system.ruby.ST.miss_latency_hist_seqr::bucket_size 16 -system.ruby.ST.miss_latency_hist_seqr::max_bucket 159 -system.ruby.ST.miss_latency_hist_seqr::samples 158 -system.ruby.ST.miss_latency_hist_seqr::mean 55.050633 -system.ruby.ST.miss_latency_hist_seqr::gmean 51.490981 -system.ruby.ST.miss_latency_hist_seqr::stdev 17.990372 -system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 44 27.85% 27.85% | 0 0.00% 27.85% | 73 46.20% 74.05% | 36 22.78% 96.84% | 4 2.53% 99.37% | 1 0.63% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist_seqr::total 158 -system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 -system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.latency_hist_seqr::samples 6413 -system.ruby.IFETCH.latency_hist_seqr::mean 7.423359 -system.ruby.IFETCH.latency_hist_seqr::gmean 1.501230 -system.ruby.IFETCH.latency_hist_seqr::stdev 22.823134 -system.ruby.IFETCH.latency_hist_seqr | 6295 98.16% 98.16% | 108 1.68% 99.84% | 1 0.02% 99.86% | 1 0.02% 99.88% | 5 0.08% 99.95% | 2 0.03% 99.98% | 0 0.00% 99.98% | 0 0.00% 99.98% | 0 0.00% 99.98% | 1 0.02% 100.00% -system.ruby.IFETCH.latency_hist_seqr::total 6413 -system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 2 -system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 19 -system.ruby.IFETCH.hit_latency_hist_seqr::samples 5832 -system.ruby.IFETCH.hit_latency_hist_seqr::mean 1.111454 -system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1.027086 -system.ruby.IFETCH.hit_latency_hist_seqr::stdev 1.049908 -system.ruby.IFETCH.hit_latency_hist_seqr | 5767 98.89% 98.89% | 0 0.00% 98.89% | 0 0.00% 98.89% | 0 0.00% 98.89% | 0 0.00% 98.89% | 65 1.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist_seqr::total 5832 -system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 -system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.miss_latency_hist_seqr::samples 581 -system.ruby.IFETCH.miss_latency_hist_seqr::mean 70.781411 -system.ruby.IFETCH.miss_latency_hist_seqr::gmean 67.778682 -system.ruby.IFETCH.miss_latency_hist_seqr::stdev 36.410761 -system.ruby.IFETCH.miss_latency_hist_seqr | 463 79.69% 79.69% | 108 18.59% 98.28% | 1 0.17% 98.45% | 1 0.17% 98.62% | 5 0.86% 99.48% | 2 0.34% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 1 0.17% 100.00% -system.ruby.IFETCH.miss_latency_hist_seqr::total 581 -system.ruby.L1Cache.hit_mach_latency_hist_seqr::bucket_size 1 -system.ruby.L1Cache.hit_mach_latency_hist_seqr::max_bucket 9 -system.ruby.L1Cache.hit_mach_latency_hist_seqr::samples 7100 -system.ruby.L1Cache.hit_mach_latency_hist_seqr::mean 1 -system.ruby.L1Cache.hit_mach_latency_hist_seqr::gmean 1 -system.ruby.L1Cache.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 7100 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.hit_mach_latency_hist_seqr::total 7100 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::bucket_size 2 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::max_bucket 19 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::samples 203 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::mean 11 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::gmean 11.000000 -system.ruby.L2Cache.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 203 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L2Cache.hit_mach_latency_hist_seqr::total 203 -system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 -system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 -system.ruby.Directory.miss_mach_latency_hist_seqr::samples 1160 -system.ruby.Directory.miss_mach_latency_hist_seqr::mean 65.109483 -system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 60.947221 -system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 32.683425 -system.ruby.Directory.miss_mach_latency_hist_seqr | 916 78.97% 78.97% | 231 19.91% 98.88% | 1 0.09% 98.97% | 1 0.09% 99.05% | 5 0.43% 99.48% | 5 0.43% 99.91% | 0 0.00% 99.91% | 0 0.00% 99.91% | 0 0.00% 99.91% | 1 0.09% 100.00% -system.ruby.Directory.miss_mach_latency_hist_seqr::total 1160 -system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 -system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 -system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1 -system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::stdev nan -system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 1 -system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 1 -system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::max_bucket 9 -system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::samples 1 -system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::stdev nan -system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::total 1 -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::bucket_size 8 -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::max_bucket 79 -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::samples 1 -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::mean 75 -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::gmean 75.000000 -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::stdev nan -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total 1 -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size 1 -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 9 -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 1 -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::samples 659 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::mean 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 659 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::total 659 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 2 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 19 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::samples 105 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::mean 11 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::gmean 11.000000 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 105 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::total 105 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 421 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 61.057007 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 56.073786 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 29.948950 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 336 79.81% 79.81% | 82 19.48% 99.29% | 0 0.00% 99.29% | 0 0.00% 99.29% | 0 0.00% 99.29% | 3 0.71% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 421 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::samples 674 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::mean 1 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 674 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::total 674 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 2 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 19 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::samples 33 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::mean 11 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::gmean 11.000000 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 33 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::total 33 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 16 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 159 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 158 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 55.050633 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 51.490981 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 17.990372 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 44 27.85% 27.85% | 0 0.00% 27.85% | 73 46.20% 74.05% | 36 22.78% 96.84% | 4 2.53% 99.37% | 1 0.63% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 158 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::samples 5767 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::mean 1 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 5767 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::total 5767 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 2 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 19 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::samples 65 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::mean 11 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::gmean 11.000000 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 65 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::total 65 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 581 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 70.781411 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 67.778682 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 36.410761 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 463 79.69% 79.69% | 108 18.59% 98.28% | 1 0.17% 98.45% | 1 0.17% 98.62% | 5 0.86% 99.48% | 2 0.34% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 1 0.17% 100.00% -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 581 -system.ruby.Directory_Controller.GETX 185 0.00% 0.00% -system.ruby.Directory_Controller.GETS 1021 0.00% 0.00% -system.ruby.Directory_Controller.PUT 1144 0.00% 0.00% -system.ruby.Directory_Controller.UnblockM 1159 0.00% 0.00% -system.ruby.Directory_Controller.Writeback_Exclusive_Clean 924 0.00% 0.00% -system.ruby.Directory_Controller.Writeback_Exclusive_Dirty 220 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 1160 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 220 0.00% 0.00% -system.ruby.Directory_Controller.NO.PUT 1144 0.00% 0.00% -system.ruby.Directory_Controller.E.GETX 158 0.00% 0.00% -system.ruby.Directory_Controller.E.GETS 1002 0.00% 0.00% -system.ruby.Directory_Controller.NO_B.UnblockM 1159 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_W.Memory_Data 1160 0.00% 0.00% -system.ruby.Directory_Controller.WB.GETX 27 0.00% 0.00% -system.ruby.Directory_Controller.WB.GETS 19 0.00% 0.00% -system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean 924 0.00% 0.00% -system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty 220 0.00% 0.00% -system.ruby.Directory_Controller.WB_E_W.Memory_Ack 220 0.00% 0.00% -system.ruby.L1Cache_Controller.Load 1193 0.00% 0.00% -system.ruby.L1Cache_Controller.Ifetch 6424 0.00% 0.00% -system.ruby.L1Cache_Controller.Store 892 0.00% 0.00% -system.ruby.L1Cache_Controller.L2_Replacement 1144 0.00% 0.00% -system.ruby.L1Cache_Controller.L1_to_L2 1355 0.00% 0.00% -system.ruby.L1Cache_Controller.Trigger_L2_to_L1D 138 0.00% 0.00% -system.ruby.L1Cache_Controller.Trigger_L2_to_L1I 65 0.00% 0.00% -system.ruby.L1Cache_Controller.Complete_L2_to_L1 203 0.00% 0.00% -system.ruby.L1Cache_Controller.Exclusive_Data 1160 0.00% 0.00% -system.ruby.L1Cache_Controller.Writeback_Ack 1144 0.00% 0.00% -system.ruby.L1Cache_Controller.All_acks_no_sharers 1160 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Load 421 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Ifetch 581 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Store 158 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Load 305 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Ifetch 5767 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Store 60 0.00% 0.00% -system.ruby.L1Cache_Controller.M.L2_Replacement 924 0.00% 0.00% -system.ruby.L1Cache_Controller.M.L1_to_L2 1062 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1D 68 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1I 65 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.Load 354 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.Store 614 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.L2_Replacement 220 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.L1_to_L2 293 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1D 70 0.00% 0.00% -system.ruby.L1Cache_Controller.MR.Load 62 0.00% 0.00% -system.ruby.L1Cache_Controller.MR.Ifetch 65 0.00% 0.00% -system.ruby.L1Cache_Controller.MR.Store 6 0.00% 0.00% -system.ruby.L1Cache_Controller.MMR.Load 43 0.00% 0.00% -system.ruby.L1Cache_Controller.MMR.Store 27 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.Exclusive_Data 158 0.00% 0.00% -system.ruby.L1Cache_Controller.M_W.All_acks_no_sharers 1002 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_W.All_acks_no_sharers 158 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Exclusive_Data 1002 0.00% 0.00% -system.ruby.L1Cache_Controller.MI.Load 8 0.00% 0.00% -system.ruby.L1Cache_Controller.MI.Ifetch 11 0.00% 0.00% -system.ruby.L1Cache_Controller.MI.Store 27 0.00% 0.00% -system.ruby.L1Cache_Controller.MI.Writeback_Ack 1144 0.00% 0.00% -system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1 133 0.00% 0.00% -system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1 70 0.00% 0.00% - ----------- End Simulation Statistics ---------- diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,1266 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000 -time_sync_spin_threshold=100000 - -[system] -type=System -children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges=0:268435455:0:0:0:0 -memories=system.mem_ctrls -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.sys_port_proxy.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=TimingSimpleCPU -children=clk_domain dtb interrupts isa itb tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu.clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1] -icache_port=system.ruby.l1_cntrl0.sequencer.slave[0] - -[system.cpu.clk_domain] -type=SrcClockDomain -clock=1 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=hello -cwd= -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/linux/hello -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000 - -[system.mem_ctrls] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -page_policy=open_adaptive -power_model=Null -range=0:268435455:5:19:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10 -static_frontend_latency=10 -tBURST=5 -tCCD_L=0 -tCK=1 -tCL=14 -tCS=3 -tRAS=35 -tRCD=14 -tREFI=7800 -tRFC=260 -tRP=14 -tRRD=6 -tRRD_L=0 -tRTP=8 -tRTW=3 -tWR=15 -tWTR=8 -tXAW=30 -tXP=6 -tXPDLL=0 -tXS=270 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.ruby.dir_cntrl0.memory - -[system.ruby] -type=RubySystem -children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network -access_backing_store=false -all_instructions=false -block_size_bytes=64 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hot_lines=false -memory_size_bits=48 -num_of_sequencers=1 -number_of_virtual_networks=5 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -phys_mem=Null -power_model=Null -randomization=false - -[system.ruby.clk_domain] -type=SrcClockDomain -clock=1 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.ruby.dir_cntrl0] -type=Directory_Controller -children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir requestToDir responseFromDir responseFromMemory -buffer_size=0 -clk_domain=system.ruby.clk_domain -cluster_id=0 -default_p_state=UNDEFINED -directory=system.ruby.dir_cntrl0.directory -directory_latency=12 -dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir -dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir -eventq_index=0 -forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir -number_of_TBEs=256 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -recycle_latency=10 -requestToDir=system.ruby.dir_cntrl0.requestToDir -responseFromDir=system.ruby.dir_cntrl0.responseFromDir -responseFromMemory=system.ruby.dir_cntrl0.responseFromMemory -ruby_system=system.ruby -system=system -to_memory_controller_latency=1 -transitions_per_cycle=4 -version=0 -memory=system.mem_ctrls.port - -[system.ruby.dir_cntrl0.directory] -type=RubyDirectoryMemory -eventq_index=0 -numa_high_bit=5 -size=268435456 -version=0 - -[system.ruby.dir_cntrl0.dmaRequestToDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -slave=system.ruby.network.master[3] - -[system.ruby.dir_cntrl0.dmaResponseFromDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -master=system.ruby.network.slave[3] - -[system.ruby.dir_cntrl0.forwardFromDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[4] - -[system.ruby.dir_cntrl0.requestToDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -slave=system.ruby.network.master[2] - -[system.ruby.dir_cntrl0.responseFromDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[2] - -[system.ruby.dir_cntrl0.responseFromMemory] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false - -[system.ruby.l1_cntrl0] -type=L1Cache_Controller -children=cacheMemory forwardToCache mandatoryQueue requestFromCache responseFromCache responseToCache sequencer -buffer_size=0 -cacheMemory=system.ruby.l1_cntrl0.cacheMemory -cache_response_latency=12 -clk_domain=system.cpu.clk_domain -cluster_id=0 -default_p_state=UNDEFINED -eventq_index=0 -forwardToCache=system.ruby.l1_cntrl0.forwardToCache -issue_latency=2 -mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue -number_of_TBEs=256 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -recycle_latency=10 -requestFromCache=system.ruby.l1_cntrl0.requestFromCache -responseFromCache=system.ruby.l1_cntrl0.responseFromCache -responseToCache=system.ruby.l1_cntrl0.responseToCache -ruby_system=system.ruby -send_evictions=false -sequencer=system.ruby.l1_cntrl0.sequencer -system=system -transitions_per_cycle=4 -version=0 - -[system.ruby.l1_cntrl0.cacheMemory] -type=RubyCache -children=replacement_policy -assoc=2 -block_size=0 -dataAccessLatency=1 -dataArrayBanks=1 -eventq_index=0 -is_icache=false -replacement_policy=system.ruby.l1_cntrl0.cacheMemory.replacement_policy -resourceStalls=false -ruby_system=system.ruby -size=256 -start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 - -[system.ruby.l1_cntrl0.cacheMemory.replacement_policy] -type=PseudoLRUReplacementPolicy -assoc=2 -block_size=64 -eventq_index=0 -size=256 - -[system.ruby.l1_cntrl0.forwardToCache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -slave=system.ruby.network.master[0] - -[system.ruby.l1_cntrl0.mandatoryQueue] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false - -[system.ruby.l1_cntrl0.requestFromCache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -master=system.ruby.network.slave[0] - -[system.ruby.l1_cntrl0.responseFromCache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -master=system.ruby.network.slave[1] - -[system.ruby.l1_cntrl0.responseToCache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -slave=system.ruby.network.master[1] - -[system.ruby.l1_cntrl0.sequencer] -type=RubySequencer -clk_domain=system.cpu.clk_domain -coreid=99 -dcache=system.ruby.l1_cntrl0.cacheMemory -dcache_hit_latency=1 -deadlock_threshold=500000 -default_p_state=UNDEFINED -eventq_index=0 -garnet_standalone=false -icache=system.ruby.l1_cntrl0.cacheMemory -icache_hit_latency=1 -is_cpu_sequencer=true -max_outstanding_requests=16 -no_retry_on_stall=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -ruby_system=system.ruby -support_data_reqs=true -support_inst_reqs=true -system=system -using_ruby_tester=false -version=0 -slave=system.cpu.icache_port system.cpu.dcache_port - -[system.ruby.memctrl_clk_domain] -type=DerivedClockDomain -clk_divider=3 -clk_domain=system.ruby.clk_domain -eventq_index=0 - -[system.ruby.network] -type=SimpleNetwork -children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_links0 int_links1 int_links2 int_links3 routers0 routers1 routers2 -adaptive_routing=false -buffer_size=0 -clk_domain=system.ruby.clk_domain -control_msg_size=8 -default_p_state=UNDEFINED -endpoint_bandwidth=1000 -eventq_index=0 -ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 -int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 -int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 -netifs= -number_of_virtual_networks=5 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 -ruby_system=system.ruby -topology=Crossbar -master=system.ruby.l1_cntrl0.forwardToCache.slave system.ruby.l1_cntrl0.responseToCache.slave system.ruby.dir_cntrl0.requestToDir.slave system.ruby.dir_cntrl0.dmaRequestToDir.slave -slave=system.ruby.l1_cntrl0.requestFromCache.master system.ruby.l1_cntrl0.responseFromCache.master system.ruby.dir_cntrl0.responseFromDir.master system.ruby.dir_cntrl0.dmaResponseFromDir.master system.ruby.dir_cntrl0.forwardFromDir.master - -[system.ruby.network.ext_links0] -type=SimpleExtLink -bandwidth_factor=16 -eventq_index=0 -ext_node=system.ruby.l1_cntrl0 -int_node=system.ruby.network.routers0 -latency=1 -link_id=0 -weight=1 - -[system.ruby.network.ext_links1] -type=SimpleExtLink -bandwidth_factor=16 -eventq_index=0 -ext_node=system.ruby.dir_cntrl0 -int_node=system.ruby.network.routers1 -latency=1 -link_id=1 -weight=1 - -[system.ruby.network.int_link_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers15] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers16] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers17] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers18] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers19] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers20] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers21] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers22] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers23] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers24] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers25] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers26] -type=MessageBuffer -buffer_size=0 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-[system.ruby.network.int_link_buffers34] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers35] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers36] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers37] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers38] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers39] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_links0] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers2 -eventq_index=0 -latency=1 -link_id=2 -src_node=system.ruby.network.routers0 -src_outport= -weight=1 - -[system.ruby.network.int_links1] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers2 -eventq_index=0 -latency=1 -link_id=3 -src_node=system.ruby.network.routers1 -src_outport= -weight=1 - -[system.ruby.network.int_links2] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers0 -eventq_index=0 -latency=1 -link_id=4 -src_node=system.ruby.network.routers2 -src_outport= -weight=1 - -[system.ruby.network.int_links3] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers1 -eventq_index=0 -latency=1 -link_id=5 -src_node=system.ruby.network.routers2 -src_outport= -weight=1 - -[system.ruby.network.routers0] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 system.ruby.network.routers0.port_buffers12 system.ruby.network.routers0.port_buffers13 system.ruby.network.routers0.port_buffers14 -power_model=Null -router_id=0 -virt_nets=5 - -[system.ruby.network.routers0.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 system.ruby.network.routers1.port_buffers12 system.ruby.network.routers1.port_buffers13 system.ruby.network.routers1.port_buffers14 -power_model=Null -router_id=1 -virt_nets=5 - -[system.ruby.network.routers1.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19 -power_model=Null -router_id=2 -virt_nets=5 - -[system.ruby.network.routers2.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers15] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers16] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers17] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers18] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers19] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.sys_port_proxy] -type=RubyPortProxy -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_cpu_sequencer=true -no_retry_on_stall=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -ruby_system=system.ruby -support_data_reqs=true -support_inst_reqs=true -system=system -using_ruby_tester=false -version=0 -slave=system.system_port - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,10 +0,0 @@ -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,15 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:19:45 -gem5 executing on e108600-lin, pid 28066 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/linux/simple-timing-ruby - -Global frequency set at 1000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Hello world! -Exiting @ tick 112490 because target called exit() diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,656 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000112 # Number of seconds simulated -sim_ticks 112490 # Number of ticks simulated -final_tick 112490 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 109209 # Simulator instruction rate (inst/s) -host_op_rate 109187 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1917933 # Simulator tick rate (ticks/s) -host_mem_usage 416076 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host -sim_insts 6403 # Number of instructions simulated -sim_ops 6403 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 110784 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 110784 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 110528 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 110528 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 1731 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 1731 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 1727 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 1727 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 984834207 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 984834207 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 982558450 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 982558450 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 1967392657 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 1967392657 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 1731 # Number of read requests accepted -system.mem_ctrls.writeReqs 1727 # Number of write requests accepted -system.mem_ctrls.readBursts 1731 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 1727 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 56704 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 54080 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 57088 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 110784 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 110528 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 845 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 803 # Number of DRAM write bursts merged with an existing one -system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 83 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 50 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 70 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 63 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 108 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 23 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 1 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 3 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::9 1 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 55 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 36 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 18 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 270 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 81 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 24 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 82 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 51 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 73 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 60 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 126 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 27 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 1 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 3 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 1 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 50 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 33 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 12 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 268 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 81 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::15 24 # Per bank write bursts -system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 112412 # Total gap between requests -system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 1731 # Read request sizes (log2) -system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 1727 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 886 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 51 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 57 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 57 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 56 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 60 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 57 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 56 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 56 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 56 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 56 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 56 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 56 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 56 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 56 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 56 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 55 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 264 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 424 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 260.079273 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 372.426347 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 66 25.00% 25.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 58 21.97% 46.97% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 27 10.23% 57.20% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 16 6.06% 63.26% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 17 6.44% 69.70% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 8 3.03% 72.73% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 12 4.55% 77.27% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 10 3.79% 81.06% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 50 18.94% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 264 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 55 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 15.818182 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 15.638991 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 2.938196 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::12-13 3 5.45% 5.45% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::14-15 24 43.64% 49.09% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-17 23 41.82% 90.91% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::18-19 4 7.27% 98.18% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::34-35 1 1.82% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 55 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 55 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.218182 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.206001 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 0.658025 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 49 89.09% 89.09% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 1 1.82% 90.91% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 4 7.27% 98.18% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 1 1.82% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 55 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 16225 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 33059 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 4430 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 18.31 # Average queueing delay per DRAM burst -system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 37.31 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 504.08 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 507.49 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 984.83 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 982.56 # Average system write bandwidth in MiByte/s -system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 7.90 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 3.94 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 3.96 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 26.10 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 674 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 833 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 76.07 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 90.15 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 32.51 # Average gap between requests -system.mem_ctrls.pageHitRate 83.26 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 735420 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 386400 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 4581024 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 3532896 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 8604960.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 13923048 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 195072 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.actPowerDownEnergy 30921360 # Energy for active power-down per rank (pJ) -system.mem_ctrls_0.prePowerDownEnergy 5237376 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrls_0.totalEnergy 68117556 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 605.543213 # Core power per rank (mW) -system.mem_ctrls_0.totalIdleTime 81406 # Total Idle time Per DRAM Rank -system.mem_ctrls_0.memoryStateTime::IDLE 88 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 3640 # Time in different power states -system.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::PRE_PDN 13639 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 27313 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 67810 # Time in different power states -system.mem_ctrls_1.actEnergy 1199520 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 633696 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 5540640 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 3917088 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 8604960.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 12524952 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 314880 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.actPowerDownEnergy 33139344 # Energy for active power-down per rank (pJ) -system.mem_ctrls_1.prePowerDownEnergy 4427136 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrls_1.totalEnergy 70302216 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 624.964139 # Core power per rank (mW) -system.mem_ctrls_1.totalIdleTime 83983 # Total Idle time Per DRAM Rank -system.mem_ctrls_1.memoryStateTime::IDLE 260 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 3640 # Time in different power states -system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 11529 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 24387 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT_PDN 72674 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states -system.cpu.clk_domain.clock 1 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1185 # DTB read hits -system.cpu.dtb.read_misses 7 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 1192 # DTB read accesses -system.cpu.dtb.write_hits 865 # DTB write hits -system.cpu.dtb.write_misses 3 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 868 # DTB write accesses -system.cpu.dtb.data_hits 2050 # DTB hits -system.cpu.dtb.data_misses 10 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 2060 # DTB accesses -system.cpu.itb.fetch_hits 6414 # ITB hits -system.cpu.itb.fetch_misses 17 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 6431 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 112490 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 112490 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 6403 # Number of instructions committed -system.cpu.committedOps 6403 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 6329 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses -system.cpu.num_func_calls 251 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 754 # number of instructions that are conditional controls -system.cpu.num_int_insts 6329 # number of integer instructions -system.cpu.num_fp_insts 10 # number of float instructions -system.cpu.num_int_register_reads 8297 # number of times the integer registers were read -system.cpu.num_int_register_writes 4575 # number of times the integer registers were written -system.cpu.num_fp_register_reads 8 # number of times the floating registers were read -system.cpu.num_fp_register_writes 2 # number of times the floating registers were written -system.cpu.num_mem_refs 2060 # number of memory refs -system.cpu.num_load_insts 1192 # Number of load instructions -system.cpu.num_store_insts 868 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 112490 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 1056 # Number of branches fetched -system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction -system.cpu.op_class::IntAlu 4331 67.53% 67.83% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.02% 67.85% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 67.85% # Class of executed instruction -system.cpu.op_class::FloatAdd 2 0.03% 67.88% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::MemRead 1191 18.57% 86.45% # Class of executed instruction -system.cpu.op_class::MemWrite 861 13.43% 99.88% # Class of executed instruction -system.cpu.op_class::FloatMemRead 1 0.02% 99.89% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 7 0.11% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 6413 # Class of executed instruction -system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states -system.ruby.delayHist::bucket_size 1 # delay histogram for all message -system.ruby.delayHist::max_bucket 9 # delay histogram for all message -system.ruby.delayHist::samples 3458 # delay histogram for all message -system.ruby.delayHist | 3458 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 3458 # delay histogram for all message -system.ruby.outstanding_req_hist_seqr::bucket_size 1 -system.ruby.outstanding_req_hist_seqr::max_bucket 9 -system.ruby.outstanding_req_hist_seqr::samples 8464 -system.ruby.outstanding_req_hist_seqr::mean 1 -system.ruby.outstanding_req_hist_seqr::gmean 1 -system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 8464 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist_seqr::total 8464 -system.ruby.latency_hist_seqr::bucket_size 64 -system.ruby.latency_hist_seqr::max_bucket 639 -system.ruby.latency_hist_seqr::samples 8463 -system.ruby.latency_hist_seqr::mean 12.291977 -system.ruby.latency_hist_seqr::gmean 2.221869 -system.ruby.latency_hist_seqr::stdev 27.407806 -system.ruby.latency_hist_seqr | 7608 89.90% 89.90% | 798 9.43% 99.33% | 40 0.47% 99.80% | 5 0.06% 99.86% | 6 0.07% 99.93% | 6 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist_seqr::total 8463 -system.ruby.hit_latency_hist_seqr::bucket_size 1 -system.ruby.hit_latency_hist_seqr::max_bucket 9 -system.ruby.hit_latency_hist_seqr::samples 6732 -system.ruby.hit_latency_hist_seqr::mean 1 -system.ruby.hit_latency_hist_seqr::gmean 1 -system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 6732 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist_seqr::total 6732 -system.ruby.miss_latency_hist_seqr::bucket_size 64 -system.ruby.miss_latency_hist_seqr::max_bucket 639 -system.ruby.miss_latency_hist_seqr::samples 1731 -system.ruby.miss_latency_hist_seqr::mean 56.207395 -system.ruby.miss_latency_hist_seqr::gmean 49.560362 -system.ruby.miss_latency_hist_seqr::stdev 35.333412 -system.ruby.miss_latency_hist_seqr | 876 50.61% 50.61% | 798 46.10% 96.71% | 40 2.31% 99.02% | 5 0.29% 99.31% | 6 0.35% 99.65% | 6 0.35% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist_seqr::total 1731 -system.ruby.Directory.incomplete_times_seqr 1730 -system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.cacheMemory.demand_hits 6732 # Number of cache demand hits -system.ruby.l1_cntrl0.cacheMemory.demand_misses 1731 # Number of cache demand misses -system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8463 # Number of cache demand accesses -system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.percent_links_utilized 7.685128 -system.ruby.network.routers0.msg_count.Control::2 1731 -system.ruby.network.routers0.msg_count.Data::2 1727 -system.ruby.network.routers0.msg_count.Response_Data::4 1731 -system.ruby.network.routers0.msg_count.Writeback_Control::3 1727 -system.ruby.network.routers0.msg_bytes.Control::2 13848 -system.ruby.network.routers0.msg_bytes.Data::2 124344 -system.ruby.network.routers0.msg_bytes.Response_Data::4 124632 -system.ruby.network.routers0.msg_bytes.Writeback_Control::3 13816 -system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states -system.ruby.network.routers1.percent_links_utilized 7.685128 -system.ruby.network.routers1.msg_count.Control::2 1731 -system.ruby.network.routers1.msg_count.Data::2 1727 -system.ruby.network.routers1.msg_count.Response_Data::4 1731 -system.ruby.network.routers1.msg_count.Writeback_Control::3 1727 -system.ruby.network.routers1.msg_bytes.Control::2 13848 -system.ruby.network.routers1.msg_bytes.Data::2 124344 -system.ruby.network.routers1.msg_bytes.Response_Data::4 124632 -system.ruby.network.routers1.msg_bytes.Writeback_Control::3 13816 -system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states -system.ruby.network.routers2.percent_links_utilized 7.685128 -system.ruby.network.routers2.msg_count.Control::2 1731 -system.ruby.network.routers2.msg_count.Data::2 1727 -system.ruby.network.routers2.msg_count.Response_Data::4 1731 -system.ruby.network.routers2.msg_count.Writeback_Control::3 1727 -system.ruby.network.routers2.msg_bytes.Control::2 13848 -system.ruby.network.routers2.msg_bytes.Data::2 124344 -system.ruby.network.routers2.msg_bytes.Response_Data::4 124632 -system.ruby.network.routers2.msg_bytes.Writeback_Control::3 13816 -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states -system.ruby.network.msg_count.Control 5193 -system.ruby.network.msg_count.Data 5181 -system.ruby.network.msg_count.Response_Data 5193 -system.ruby.network.msg_count.Writeback_Control 5181 -system.ruby.network.msg_byte.Control 41544 -system.ruby.network.msg_byte.Data 373032 -system.ruby.network.msg_byte.Response_Data 373896 -system.ruby.network.msg_byte.Writeback_Control 41448 -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.throttle0.link_utilization 7.692239 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1731 -system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1727 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 124632 -system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 13816 -system.ruby.network.routers0.throttle1.link_utilization 7.678016 -system.ruby.network.routers0.throttle1.msg_count.Control::2 1731 -system.ruby.network.routers0.throttle1.msg_count.Data::2 1727 -system.ruby.network.routers0.throttle1.msg_bytes.Control::2 13848 -system.ruby.network.routers0.throttle1.msg_bytes.Data::2 124344 -system.ruby.network.routers1.throttle0.link_utilization 7.678016 -system.ruby.network.routers1.throttle0.msg_count.Control::2 1731 -system.ruby.network.routers1.throttle0.msg_count.Data::2 1727 -system.ruby.network.routers1.throttle0.msg_bytes.Control::2 13848 -system.ruby.network.routers1.throttle0.msg_bytes.Data::2 124344 -system.ruby.network.routers1.throttle1.link_utilization 7.692239 -system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1731 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1727 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 124632 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 13816 -system.ruby.network.routers2.throttle0.link_utilization 7.692239 -system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1731 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1727 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 124632 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 13816 -system.ruby.network.routers2.throttle1.link_utilization 7.678016 -system.ruby.network.routers2.throttle1.msg_count.Control::2 1731 -system.ruby.network.routers2.throttle1.msg_count.Data::2 1727 -system.ruby.network.routers2.throttle1.msg_bytes.Control::2 13848 -system.ruby.network.routers2.throttle1.msg_bytes.Data::2 124344 -system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::samples 1731 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1 | 1731 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::total 1731 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::samples 1727 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2 | 1727 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::total 1727 # delay histogram for vnet_2 -system.ruby.LD.latency_hist_seqr::bucket_size 64 -system.ruby.LD.latency_hist_seqr::max_bucket 639 -system.ruby.LD.latency_hist_seqr::samples 1185 -system.ruby.LD.latency_hist_seqr::mean 33.356118 -system.ruby.LD.latency_hist_seqr::gmean 10.708915 -system.ruby.LD.latency_hist_seqr::stdev 36.387225 -system.ruby.LD.latency_hist_seqr | 862 72.74% 72.74% | 301 25.40% 98.14% | 16 1.35% 99.49% | 3 0.25% 99.75% | 1 0.08% 99.83% | 2 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist_seqr::total 1185 -system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 -system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 -system.ruby.LD.hit_latency_hist_seqr::samples 457 -system.ruby.LD.hit_latency_hist_seqr::mean 1 -system.ruby.LD.hit_latency_hist_seqr::gmean 1 -system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 457 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist_seqr::total 457 -system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 -system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 -system.ruby.LD.miss_latency_hist_seqr::samples 728 -system.ruby.LD.miss_latency_hist_seqr::mean 53.667582 -system.ruby.LD.miss_latency_hist_seqr::gmean 47.442261 -system.ruby.LD.miss_latency_hist_seqr::stdev 32.940895 -system.ruby.LD.miss_latency_hist_seqr | 405 55.63% 55.63% | 301 41.35% 96.98% | 16 2.20% 99.18% | 3 0.41% 99.59% | 1 0.14% 99.73% | 2 0.27% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist_seqr::total 728 -system.ruby.ST.latency_hist_seqr::bucket_size 32 -system.ruby.ST.latency_hist_seqr::max_bucket 319 -system.ruby.ST.latency_hist_seqr::samples 865 -system.ruby.ST.latency_hist_seqr::mean 17.479769 -system.ruby.ST.latency_hist_seqr::gmean 3.361529 -system.ruby.ST.latency_hist_seqr::stdev 31.340829 -system.ruby.ST.latency_hist_seqr | 592 68.44% 68.44% | 160 18.50% 86.94% | 102 11.79% 98.73% | 0 0.00% 98.73% | 4 0.46% 99.19% | 4 0.46% 99.65% | 1 0.12% 99.77% | 0 0.00% 99.77% | 1 0.12% 99.88% | 1 0.12% 100.00% -system.ruby.ST.latency_hist_seqr::total 865 -system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 -system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 -system.ruby.ST.hit_latency_hist_seqr::samples 592 -system.ruby.ST.hit_latency_hist_seqr::mean 1 -system.ruby.ST.hit_latency_hist_seqr::gmean 1 -system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 592 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist_seqr::total 592 -system.ruby.ST.miss_latency_hist_seqr::bucket_size 32 -system.ruby.ST.miss_latency_hist_seqr::max_bucket 319 -system.ruby.ST.miss_latency_hist_seqr::samples 273 -system.ruby.ST.miss_latency_hist_seqr::mean 53.216117 -system.ruby.ST.miss_latency_hist_seqr::gmean 46.594106 -system.ruby.ST.miss_latency_hist_seqr::stdev 35.315815 -system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 160 58.61% 58.61% | 102 37.36% 95.97% | 0 0.00% 95.97% | 4 1.47% 97.44% | 4 1.47% 98.90% | 1 0.37% 99.27% | 0 0.00% 99.27% | 1 0.37% 99.63% | 1 0.37% 100.00% -system.ruby.ST.miss_latency_hist_seqr::total 273 -system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 -system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.latency_hist_seqr::samples 6413 -system.ruby.IFETCH.latency_hist_seqr::mean 7.699984 -system.ruby.IFETCH.latency_hist_seqr::gmean 1.571280 -system.ruby.IFETCH.latency_hist_seqr::stdev 22.534194 -system.ruby.IFETCH.latency_hist_seqr | 5994 93.47% 93.47% | 395 6.16% 99.63% | 16 0.25% 99.88% | 1 0.02% 99.89% | 3 0.05% 99.94% | 4 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist_seqr::total 6413 -system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 -system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 -system.ruby.IFETCH.hit_latency_hist_seqr::samples 5683 -system.ruby.IFETCH.hit_latency_hist_seqr::mean 1 -system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 -system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 5683 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist_seqr::total 5683 -system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 -system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.miss_latency_hist_seqr::samples 730 -system.ruby.IFETCH.miss_latency_hist_seqr::mean 59.858904 -system.ruby.IFETCH.miss_latency_hist_seqr::gmean 52.975537 -system.ruby.IFETCH.miss_latency_hist_seqr::stdev 37.310775 -system.ruby.IFETCH.miss_latency_hist_seqr | 311 42.60% 42.60% | 395 54.11% 96.71% | 16 2.19% 98.90% | 1 0.14% 99.04% | 3 0.41% 99.45% | 4 0.55% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.miss_latency_hist_seqr::total 730 -system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 -system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 -system.ruby.Directory.miss_mach_latency_hist_seqr::samples 1731 -system.ruby.Directory.miss_mach_latency_hist_seqr::mean 56.207395 -system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 49.560362 -system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 35.333412 -system.ruby.Directory.miss_mach_latency_hist_seqr | 876 50.61% 50.61% | 798 46.10% 96.71% | 40 2.31% 99.02% | 5 0.29% 99.31% | 6 0.35% 99.65% | 6 0.35% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_mach_latency_hist_seqr::total 1731 -system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 -system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 -system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1 -system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::stdev nan -system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 1 -system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 1 -system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::max_bucket 9 -system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::samples 1 -system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::stdev nan -system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::total 1 -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::bucket_size 1 -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::max_bucket 9 -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::samples 1 -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::stdev nan -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total 1 -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size 8 -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 79 -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 1 -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean 75 -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 75.000000 -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 728 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 53.667582 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 47.442261 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 32.940895 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 405 55.63% 55.63% | 301 41.35% 96.98% | 16 2.20% 99.18% | 3 0.41% 99.59% | 1 0.14% 99.73% | 2 0.27% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 728 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 273 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 53.216117 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 46.594106 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 35.315815 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 160 58.61% 58.61% | 102 37.36% 95.97% | 0 0.00% 95.97% | 4 1.47% 97.44% | 4 1.47% 98.90% | 1 0.37% 99.27% | 0 0.00% 99.27% | 1 0.37% 99.63% | 1 0.37% 100.00% -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 273 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 730 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 59.858904 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 52.975537 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 37.310775 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 311 42.60% 42.60% | 395 54.11% 96.71% | 16 2.19% 98.90% | 1 0.14% 99.04% | 3 0.41% 99.45% | 4 0.55% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 730 -system.ruby.Directory_Controller.GETX 1731 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 1727 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 1731 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 1727 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 1731 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 1727 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 1731 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 1727 0.00% 0.00% -system.ruby.L1Cache_Controller.Load 1185 0.00% 0.00% -system.ruby.L1Cache_Controller.Ifetch 6413 0.00% 0.00% -system.ruby.L1Cache_Controller.Store 865 0.00% 0.00% -system.ruby.L1Cache_Controller.Data 1731 0.00% 0.00% -system.ruby.L1Cache_Controller.Replacement 1727 0.00% 0.00% -system.ruby.L1Cache_Controller.Writeback_Ack 1727 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Load 728 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Ifetch 730 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Store 273 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Load 457 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Ifetch 5683 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Store 592 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Replacement 1727 0.00% 0.00% -system.ruby.L1Cache_Controller.MI.Writeback_Ack 1727 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Data 1458 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.Data 273 0.00% 0.00% - ----------- End Simulation Statistics ---------- diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,366 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=hello -cwd= -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/linux/hello -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=Null -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=0:134217727 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simerr --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simerr Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,2 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,15 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 19 2016 12:24:28 -gem5 executing on e108600-lin, pid 39614 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/linux/simple-timing - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Hello world! -Exiting @ tick 35682500 because target called exit() diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,525 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000036 # Number of seconds simulated -sim_ticks 36128500 # Number of ticks simulated -final_tick 36128500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 739000 # Simulator instruction rate (inst/s) -host_op_rate 738191 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4160971439 # Simulator tick rate (ticks/s) -host_mem_usage 251728 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -sim_insts 6403 # Number of instructions simulated -sim_ops 6403 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 36128500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10752 # Number of bytes read from this memory -system.physmem.bytes_read::total 28544 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory -system.physmem.num_reads::total 446 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 492464398 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 297604384 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 790068782 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 492464398 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 492464398 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 492464398 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 297604384 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 790068782 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 36128500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1185 # DTB read hits -system.cpu.dtb.read_misses 7 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 1192 # DTB read accesses -system.cpu.dtb.write_hits 865 # DTB write hits -system.cpu.dtb.write_misses 3 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 868 # DTB write accesses -system.cpu.dtb.data_hits 2050 # DTB hits -system.cpu.dtb.data_misses 10 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 2060 # DTB accesses -system.cpu.itb.fetch_hits 6414 # ITB hits -system.cpu.itb.fetch_misses 17 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 6431 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 36128500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 72257 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 6403 # Number of instructions committed -system.cpu.committedOps 6403 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 6329 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses -system.cpu.num_func_calls 251 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 754 # number of instructions that are conditional controls -system.cpu.num_int_insts 6329 # number of integer instructions -system.cpu.num_fp_insts 10 # number of float instructions -system.cpu.num_int_register_reads 8297 # number of times the integer registers were read -system.cpu.num_int_register_writes 4575 # number of times the integer registers were written -system.cpu.num_fp_register_reads 8 # number of times the floating registers were read -system.cpu.num_fp_register_writes 2 # number of times the floating registers were written -system.cpu.num_mem_refs 2060 # number of memory refs -system.cpu.num_load_insts 1192 # Number of load instructions -system.cpu.num_store_insts 868 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 72257 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 1056 # Number of branches fetched -system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction -system.cpu.op_class::IntAlu 4331 67.53% 67.83% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.02% 67.85% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 67.85% # Class of executed instruction -system.cpu.op_class::FloatAdd 2 0.03% 67.88% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.88% # Class of executed instruction -system.cpu.op_class::MemRead 1191 18.57% 86.45% # Class of executed instruction -system.cpu.op_class::MemWrite 861 13.43% 99.88% # Class of executed instruction -system.cpu.op_class::FloatMemRead 1 0.02% 99.89% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 7 0.11% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 6413 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 36128500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 103.721081 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1882 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.202381 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 103.721081 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.025323 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.025323 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.041016 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4268 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4268 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 36128500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1090 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1090 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1882 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1882 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1882 # number of overall hits -system.cpu.dcache.overall_hits::total 1882 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 95 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 95 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 73 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 168 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses -system.cpu.dcache.overall_misses::total 168 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5985000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5985000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4599000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4599000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 10584000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 10584000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 10584000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 10584000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1185 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1185 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2050 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2050 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2050 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2050 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080169 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.080169 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084393 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.084393 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.081951 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.081951 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.081951 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.081951 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5890000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5890000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4526000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4526000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10416000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10416000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10416000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10416000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080169 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080169 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.081951 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.081951 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 36128500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 127.170991 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 6135 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 279 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 21.989247 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 127.170991 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.062095 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.062095 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 279 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 185 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.136230 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 13107 # Number of tag accesses -system.cpu.icache.tags.data_accesses 13107 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 36128500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 6135 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 6135 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 6135 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 6135 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 6135 # number of overall hits -system.cpu.icache.overall_hits::total 6135 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 279 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 279 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 279 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 279 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 279 # number of overall misses -system.cpu.icache.overall_misses::total 279 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17528500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17528500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17528500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17528500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17528500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17528500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 6414 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 6414 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 6414 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 6414 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 6414 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 6414 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043499 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.043499 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.043499 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.043499 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.043499 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.043499 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62826.164875 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 62826.164875 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 62826.164875 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 62826.164875 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 62826.164875 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 62826.164875 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 279 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 279 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 279 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 279 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 279 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17249500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 17249500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17249500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 17249500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17249500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 17249500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043499 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043499 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043499 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.043499 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043499 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.043499 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61826.164875 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61826.164875 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61826.164875 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 61826.164875 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61826.164875 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 61826.164875 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 36128500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 230.937880 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 446 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.002242 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 127.167974 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 103.769906 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003881 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.003167 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.007048 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 446 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.013611 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4022 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4022 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 36128500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits -system.cpu.l2cache.overall_hits::total 1 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 278 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 278 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 95 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 95 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 168 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 446 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses -system.cpu.l2cache.overall_misses::total 446 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4416500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4416500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 16819500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 16819500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5747500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 5747500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 16819500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10164000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 26983500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 16819500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10164000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 26983500 # number of overall miss cycles -system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 279 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 279 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 95 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 95 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 279 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 168 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 447 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 279 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 168 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 447 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996416 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996416 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996416 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.997763 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996416 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.997763 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60501.798561 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60501.798561 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60501.798561 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 60501.121076 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60501.798561 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 60501.121076 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 278 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 278 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 95 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 95 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 446 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3686500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3686500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 14039500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 14039500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4797500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4797500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14039500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8484000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 22523500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14039500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8484000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 22523500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996416 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997763 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997763 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50501.798561 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50501.798561 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50501.798561 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.121076 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50501.798561 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.121076 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 447 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 36128500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 374 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 279 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 95 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 558 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 336 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 894 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17856 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 28608 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 447 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.002237 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.047298 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 446 99.78% 99.78% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1 0.22% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 447 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 418500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 252000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 446 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 36128500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 373 # Transaction distribution -system.membus.trans_dist::ReadExReq 73 # Transaction distribution -system.membus.trans_dist::ReadExResp 73 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 373 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 892 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28544 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 446 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 446 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 446 # Request fanout histogram -system.membus.reqLayer0.occupancy 446500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 2230000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 6.2 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini --- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,877 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=MinorCPU -children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload -branchPred=system.cpu.branchPred -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -decodeCycleInput=true -decodeInputBufferSize=3 -decodeInputWidth=2 -decodeToExecuteForwardDelay=1 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -enableIdling=true -eventq_index=0 -executeAllowEarlyMemoryIssue=true -executeBranchDelay=1 -executeCommitLimit=2 -executeCycleInput=true -executeFuncUnits=system.cpu.executeFuncUnits -executeInputBufferSize=7 -executeInputWidth=2 -executeIssueLimit=2 -executeLSQMaxStoreBufferStoresPerCycle=2 -executeLSQRequestsQueueSize=1 -executeLSQStoreBufferSize=5 -executeLSQTransfersQueueSize=2 -executeMaxAccessesInMemory=2 -executeMemoryCommitLimit=1 -executeMemoryIssueLimit=1 -executeMemoryWidth=0 -executeSetTraceTimeOnCommit=true -executeSetTraceTimeOnIssue=false -fetch1FetchLimit=1 -fetch1LineSnapWidth=0 -fetch1LineWidth=0 -fetch1ToFetch2BackwardDelay=1 -fetch1ToFetch2ForwardDelay=1 -fetch2CycleInput=true -fetch2InputBufferSize=2 -fetch2ToDecodeForwardDelay=1 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -threadPolicy=RoundRobin -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.branchPred] -type=TournamentBP -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -indirectHashGHR=true -indirectHashTargets=true -indirectPathLength=3 -indirectSets=256 -indirectTagSize=16 -indirectWays=2 -instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 -useIndirect=true - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.executeFuncUnits] -type=MinorFUPool -children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 -eventq_index=0 -funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 - -[system.cpu.executeFuncUnits.funcUnits0] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits0.timings - -[system.cpu.executeFuncUnits.funcUnits0.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntAlu - -[system.cpu.executeFuncUnits.funcUnits0.timings] -type=MinorFUTiming -children=opClasses -description=Int -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits1] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits1.timings - -[system.cpu.executeFuncUnits.funcUnits1.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntAlu - -[system.cpu.executeFuncUnits.funcUnits1.timings] -type=MinorFUTiming -children=opClasses -description=Int -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits2] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits2.timings - -[system.cpu.executeFuncUnits.funcUnits2.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntMult - -[system.cpu.executeFuncUnits.funcUnits2.timings] -type=MinorFUTiming -children=opClasses -description=Mul -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses -srcRegsRelativeLats=0 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits3] -type=MinorFU -children=opClasses -cantForwardFromFUIndices= -eventq_index=0 -issueLat=9 -opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses -opLat=9 -timings= - -[system.cpu.executeFuncUnits.funcUnits3.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntDiv - -[system.cpu.executeFuncUnits.funcUnits4] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses -opLat=6 -timings=system.cpu.executeFuncUnits.funcUnits4.timings - -[system.cpu.executeFuncUnits.funcUnits4.opClasses] -type=MinorOpClassSet -children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] -type=MinorOpClass -eventq_index=0 -opClass=FloatAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01] -type=MinorOpClass -eventq_index=0 -opClass=FloatCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02] -type=MinorOpClass -eventq_index=0 -opClass=FloatCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] -type=MinorOpClass -eventq_index=0 -opClass=FloatMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] -type=MinorOpClass -eventq_index=0 -opClass=FloatDiv - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] -type=MinorOpClass -eventq_index=0 -opClass=FloatSqrt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] -type=MinorOpClass -eventq_index=0 -opClass=SimdAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] -type=MinorOpClass -eventq_index=0 -opClass=SimdAddAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] -type=MinorOpClass -eventq_index=0 -opClass=SimdAlu - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] -type=MinorOpClass -eventq_index=0 -opClass=SimdCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] -type=MinorOpClass -eventq_index=0 -opClass=SimdCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] -type=MinorOpClass -eventq_index=0 -opClass=SimdMisc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] -type=MinorOpClass -eventq_index=0 -opClass=SimdMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] -type=MinorOpClass -eventq_index=0 -opClass=SimdMultAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] -type=MinorOpClass -eventq_index=0 -opClass=SimdShift - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] -type=MinorOpClass -eventq_index=0 -opClass=SimdShiftAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] -type=MinorOpClass -eventq_index=0 -opClass=SimdSqrt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatAlu - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatDiv - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMisc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMultAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatSqrt - -[system.cpu.executeFuncUnits.funcUnits4.timings] -type=MinorFUTiming -children=opClasses -description=FloatSimd -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits5] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses -opLat=1 -timings=system.cpu.executeFuncUnits.funcUnits5.timings - -[system.cpu.executeFuncUnits.funcUnits5.opClasses] -type=MinorOpClassSet -children=opClasses0 opClasses1 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 - -[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] -type=MinorOpClass -eventq_index=0 -opClass=MemRead - -[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] -type=MinorOpClass -eventq_index=0 -opClass=MemWrite - -[system.cpu.executeFuncUnits.funcUnits5.timings] -type=MinorFUTiming -children=opClasses -description=Mem -eventq_index=0 -extraAssumedLat=2 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses -srcRegsRelativeLats=1 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits6] -type=MinorFU -children=opClasses -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses -opLat=1 -timings= - -[system.cpu.executeFuncUnits.funcUnits6.opClasses] -type=MinorOpClassSet -children=opClasses0 opClasses1 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 - -[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] -type=MinorOpClass -eventq_index=0 -opClass=IprAccess - -[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] -type=MinorOpClass -eventq_index=0 -opClass=InstPrefetch - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=hello -cwd= -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/tru64/hello -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=0:134217727:0:0:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=6000 -tXPDLL=0 -tXS=270000 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/simerr --- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/simerr Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,4 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: ignoring syscall sigprocmask(1, ...) diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/simout --- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/simout Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,15 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/minor-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/minor-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:19:45 -gem5 executing on e108600-lin, pid 28071 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/tru64/minor-timing - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Hello world! -Exiting @ tick 22083000 because target called exit() diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt --- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,759 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000022 # Number of seconds simulated -sim_ticks 22083000 # Number of ticks simulated -final_tick 22083000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 166693 # Simulator instruction rate (inst/s) -host_op_rate 166561 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1421880228 # Simulator tick rate (ticks/s) -host_mem_usage 251952 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -sim_insts 2585 # Number of instructions simulated -sim_ops 2585 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 22083000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 5440 # Number of bytes read from this memory -system.physmem.bytes_read::total 19840 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 14400 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 14400 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory -system.physmem.num_reads::total 310 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 652085314 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 246343341 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 898428656 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 652085314 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 652085314 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 652085314 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 246343341 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 898428656 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 310 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 310 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 19840 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 19840 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 0 # Per bank write bursts -system.physmem.perBankRdBursts::1 1 # Per bank write bursts -system.physmem.perBankRdBursts::2 3 # Per bank write bursts -system.physmem.perBankRdBursts::3 24 # Per bank write bursts -system.physmem.perBankRdBursts::4 21 # Per bank write bursts -system.physmem.perBankRdBursts::5 0 # Per bank write bursts -system.physmem.perBankRdBursts::6 27 # Per bank write bursts -system.physmem.perBankRdBursts::7 48 # Per bank write bursts -system.physmem.perBankRdBursts::8 68 # Per bank write bursts -system.physmem.perBankRdBursts::9 2 # Per bank write bursts -system.physmem.perBankRdBursts::10 15 # Per bank write bursts -system.physmem.perBankRdBursts::11 15 # Per bank write bursts -system.physmem.perBankRdBursts::12 18 # Per bank write bursts -system.physmem.perBankRdBursts::13 52 # Per bank write bursts -system.physmem.perBankRdBursts::14 15 # Per bank write bursts -system.physmem.perBankRdBursts::15 1 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 21988500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 310 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 245 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 62 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 41 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 429.268293 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 281.212133 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 334.776868 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 10 24.39% 24.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 6 14.63% 39.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6 14.63% 53.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2 4.88% 58.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3 7.32% 65.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 4.88% 70.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7 17.07% 87.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 4.88% 92.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3 7.32% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 41 # Bytes accessed per row activation -system.physmem.totQLat 3615250 # Total ticks spent queuing -system.physmem.totMemAccLat 9427750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1550000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11662.10 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30412.10 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 898.43 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 898.43 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 7.02 # Data bus utilization in percentage -system.physmem.busUtilRead 7.02 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.26 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 260 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.87 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 70930.65 # Average gap between requests -system.physmem.pageHitRate 83.87 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 114240 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 45540 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 885360 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1636470 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 32160 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 7529700 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 729120 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 12201870 # Total energy per rank (pJ) -system.physmem_0.averagePower 552.527084 # Core power per rank (mW) -system.physmem_0.totalIdleTime 18356500 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 27500 # Time in different power states -system.physmem_0.memoryStateTime::REF 520000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 0 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 1898500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 3124750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 16512250 # Time in different power states -system.physmem_1.actEnergy 242760 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 110055 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1328040 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2565570 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 217440 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 7221900 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 20640 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 12935685 # Total energy per rank (pJ) -system.physmem_1.averagePower 585.755816 # Core power per rank (mW) -system.physmem_1.totalIdleTime 15168500 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 498000 # Time in different power states -system.physmem_1.memoryStateTime::REF 520000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 0 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 53000 # Time in different power states -system.physmem_1.memoryStateTime::ACT 5182750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 15829250 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 22083000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 793 # Number of BP lookups -system.cpu.branchPred.condPredicted 395 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 170 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 561 # Number of BTB lookups -system.cpu.branchPred.BTBHits 54 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 9.625668 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 144 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 2 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 83 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 0 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 83 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 32 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 506 # DTB read hits -system.cpu.dtb.read_misses 6 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 512 # DTB read accesses -system.cpu.dtb.write_hits 307 # DTB write hits -system.cpu.dtb.write_misses 6 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 313 # DTB write accesses -system.cpu.dtb.data_hits 813 # DTB hits -system.cpu.dtb.data_misses 12 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 825 # DTB accesses -system.cpu.itb.fetch_hits 980 # ITB hits -system.cpu.itb.fetch_misses 13 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 993 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 22083000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 44166 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 2585 # Number of instructions committed -system.cpu.committedOps 2585 # Number of ops (including micro ops) committed -system.cpu.discardedOps 573 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 17.085493 # CPI: cycles per instruction -system.cpu.ipc 0.058529 # IPC: instructions per cycle -system.cpu.op_class_0::No_OpClass 189 7.31% 7.31% # Class of committed instruction -system.cpu.op_class_0::IntAlu 1678 64.91% 72.22% # Class of committed instruction -system.cpu.op_class_0::IntMult 1 0.04% 72.26% # Class of committed instruction -system.cpu.op_class_0::IntDiv 0 0.00% 72.26% # Class of committed instruction -system.cpu.op_class_0::FloatAdd 0 0.00% 72.26% # Class of committed instruction -system.cpu.op_class_0::FloatCmp 0 0.00% 72.26% # Class of committed instruction -system.cpu.op_class_0::FloatCvt 0 0.00% 72.26% # Class of committed instruction -system.cpu.op_class_0::FloatMult 0 0.00% 72.26% # Class of committed instruction -system.cpu.op_class_0::FloatMultAcc 0 0.00% 72.26% # Class of committed instruction -system.cpu.op_class_0::FloatDiv 0 0.00% 72.26% # Class of committed instruction -system.cpu.op_class_0::FloatMisc 0 0.00% 72.26% # Class of committed instruction -system.cpu.op_class_0::FloatSqrt 0 0.00% 72.26% # Class of committed instruction -system.cpu.op_class_0::SimdAdd 0 0.00% 72.26% # Class of committed instruction -system.cpu.op_class_0::SimdAddAcc 0 0.00% 72.26% # Class of committed instruction -system.cpu.op_class_0::SimdAlu 0 0.00% 72.26% # Class of committed instruction -system.cpu.op_class_0::SimdCmp 0 0.00% 72.26% # Class of committed instruction -system.cpu.op_class_0::SimdCvt 0 0.00% 72.26% # Class of committed instruction -system.cpu.op_class_0::SimdMisc 0 0.00% 72.26% # Class of committed instruction -system.cpu.op_class_0::SimdMult 0 0.00% 72.26% # Class of committed instruction -system.cpu.op_class_0::SimdMultAcc 0 0.00% 72.26% # Class of committed instruction -system.cpu.op_class_0::SimdShift 0 0.00% 72.26% # Class of committed instruction -system.cpu.op_class_0::SimdShiftAcc 0 0.00% 72.26% # Class of committed instruction -system.cpu.op_class_0::SimdSqrt 0 0.00% 72.26% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAdd 0 0.00% 72.26% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAlu 0 0.00% 72.26% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCmp 0 0.00% 72.26% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCvt 0 0.00% 72.26% # Class of committed instruction -system.cpu.op_class_0::SimdFloatDiv 0 0.00% 72.26% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMisc 0 0.00% 72.26% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMult 0 0.00% 72.26% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 72.26% # Class of committed instruction -system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 72.26% # Class of committed instruction -system.cpu.op_class_0::MemRead 419 16.21% 88.47% # Class of committed instruction -system.cpu.op_class_0::MemWrite 292 11.30% 99.77% # Class of committed instruction -system.cpu.op_class_0::FloatMemRead 0 0.00% 99.77% # Class of committed instruction -system.cpu.op_class_0::FloatMemWrite 6 0.23% 100.00% # Class of committed instruction -system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 2585 # Class of committed instruction -system.cpu.tickCycles 5429 # Number of cycles that the object actually ticked -system.cpu.idleCycles 38737 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22083000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 48.291787 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 692 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.141176 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 48.291787 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.011790 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011790 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 54 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1673 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1673 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22083000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 441 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 441 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 251 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 251 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 692 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 692 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 692 # number of overall hits -system.cpu.dcache.overall_hits::total 692 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 59 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 59 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 43 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 102 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 102 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 102 # number of overall misses -system.cpu.dcache.overall_misses::total 102 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5143500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5143500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3553000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3553000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 8696500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 8696500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 8696500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 8696500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 500 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 500 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 794 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 794 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 794 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 794 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.118000 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.118000 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.146259 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.146259 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.128463 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.128463 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.128463 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.128463 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 87177.966102 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 87177.966102 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 82627.906977 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 82627.906977 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 85259.803922 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 85259.803922 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 85259.803922 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 85259.803922 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 17 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 17 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 17 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 58 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 58 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 27 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 27 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5007000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5007000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2203500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2203500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7210500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7210500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7210500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7210500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.116000 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.116000 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.091837 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.091837 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.107053 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.107053 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.107053 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.107053 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 86327.586207 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 86327.586207 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81611.111111 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81611.111111 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84829.411765 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 84829.411765 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84829.411765 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 84829.411765 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22083000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 118.973491 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 755 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 225 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3.355556 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 118.973491 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.058093 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.058093 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 225 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 135 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.109863 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 2185 # Number of tag accesses -system.cpu.icache.tags.data_accesses 2185 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 22083000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 755 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 755 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 755 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 755 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 755 # number of overall hits -system.cpu.icache.overall_hits::total 755 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 225 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 225 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 225 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 225 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 225 # number of overall misses -system.cpu.icache.overall_misses::total 225 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 18729500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 18729500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 18729500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 18729500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 18729500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 18729500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 980 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 980 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 980 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 980 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 980 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 980 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.229592 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.229592 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.229592 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.229592 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.229592 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.229592 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 83242.222222 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 83242.222222 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 83242.222222 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 83242.222222 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 83242.222222 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 83242.222222 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 225 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 225 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 225 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 225 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 225 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18504500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 18504500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18504500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 18504500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18504500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 18504500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.229592 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.229592 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.229592 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.229592 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.229592 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.229592 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 82242.222222 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 82242.222222 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 82242.222222 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 82242.222222 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 82242.222222 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 82242.222222 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 22083000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 167.412677 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 310 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 119.080474 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 48.332203 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003634 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001475 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005109 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 310 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 189 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009460 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 2790 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 2790 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 22083000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadExReq_misses::cpu.data 27 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 27 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 225 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 225 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 58 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 58 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 225 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 85 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 310 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 225 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses -system.cpu.l2cache.overall_misses::total 310 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2163000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2163000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 18167000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 18167000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4919000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 4919000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 18167000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7082000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 25249000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 18167000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7082000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 25249000 # number of overall miss cycles -system.cpu.l2cache.ReadExReq_accesses::cpu.data 27 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 27 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 225 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 225 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 58 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 58 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 225 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 85 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 310 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 225 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 85 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 310 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80111.111111 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80111.111111 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80742.222222 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80742.222222 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84810.344828 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84810.344828 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80742.222222 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83317.647059 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 81448.387097 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80742.222222 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83317.647059 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 81448.387097 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 27 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 27 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 225 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 225 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 58 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 58 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 225 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 310 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 310 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1893000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1893000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 15917000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 15917000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4339000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4339000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15917000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6232000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 22149000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15917000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6232000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 22149000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70111.111111 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70111.111111 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70742.222222 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70742.222222 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74810.344828 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74810.344828 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70742.222222 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73317.647059 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71448.387097 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70742.222222 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73317.647059 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71448.387097 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 310 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22083000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 283 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 27 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 225 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 58 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 450 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 170 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 620 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 14400 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5440 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 19840 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 310 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 310 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 310 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 155000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 337500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 127500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 310 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 22083000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 283 # Transaction distribution -system.membus.trans_dist::ReadExReq 27 # Transaction distribution -system.membus.trans_dist::ReadExResp 27 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 283 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 620 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 620 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 19840 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19840 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 310 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 310 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 310 # Request fanout histogram -system.membus.reqLayer0.occupancy 362500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 1648750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 7.5 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,825 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=DerivO3CPU -children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload -LFSTSize=1024 -LQEntries=32 -LSQCheckLoads=true -LSQDepCheckShift=4 -SQEntries=32 -SSITSize=1024 -activity=0 -backComSize=5 -branchPred=system.cpu.branchPred -cachePorts=200 -checker=Null -clk_domain=system.cpu_clk_domain -commitToDecodeDelay=1 -commitToFetchDelay=1 -commitToIEWDelay=1 -commitToRenameDelay=1 -commitWidth=8 -cpu_id=0 -decodeToFetchDelay=1 -decodeToRenameDelay=1 -decodeWidth=8 -default_p_state=UNDEFINED -dispatchWidth=8 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -fetchBufferSize=64 -fetchQueueSize=32 -fetchToDecodeDelay=1 -fetchTrapLatency=1 -fetchWidth=8 -forwardComSize=5 -fuPool=system.cpu.fuPool -function_trace=false -function_trace_start=0 -iewToCommitDelay=1 -iewToDecodeDelay=1 -iewToFetchDelay=1 -iewToRenameDelay=1 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -issueToExecuteDelay=1 -issueWidth=8 -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -needsTSO=false -numIQEntries=64 -numPhysCCRegs=0 -numPhysFloatRegs=256 -numPhysIntRegs=256 -numROBEntries=192 -numRobs=1 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -renameToDecodeDelay=1 -renameToFetchDelay=1 -renameToIEWDelay=2 -renameToROBDelay=1 -renameWidth=8 -simpoint_start_insts= -smtCommitPolicy=RoundRobin -smtFetchPolicy=SingleThread -smtIQPolicy=Partitioned -smtIQThreshold=100 -smtLSQPolicy=Partitioned -smtLSQThreshold=100 -smtNumFetchingThreads=1 -smtROBPolicy=Partitioned -smtROBThreshold=100 -socket_id=0 -squashWidth=8 -store_set_clear_period=250000 -switched_out=false -system=system -tracer=system.cpu.tracer -trapLatency=13 -wbWidth=8 -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.branchPred] -type=TournamentBP -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -indirectHashGHR=true -indirectHashTargets=true -indirectPathLength=3 -indirectSets=256 -indirectTagSize=16 -indirectWays=2 -instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 -useIndirect=true - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.fuPool] -type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 -eventq_index=0 - -[system.cpu.fuPool.FUList0] -type=FUDesc -children=opList -count=6 -eventq_index=0 -opList=system.cpu.fuPool.FUList0.opList - -[system.cpu.fuPool.FUList0.opList] -type=OpDesc -eventq_index=0 -opClass=IntAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList1] -type=FUDesc -children=opList0 opList1 -count=2 -eventq_index=0 -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -eventq_index=0 -opClass=IntMult -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -eventq_index=0 -opClass=IntDiv -opLat=20 -pipelined=false - -[system.cpu.fuPool.FUList2] -type=FUDesc -children=opList0 opList1 opList2 -count=4 -eventq_index=0 -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -eventq_index=0 -opClass=FloatAdd -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -eventq_index=0 -opClass=FloatCmp -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -eventq_index=0 -opClass=FloatCvt -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList3] -type=FUDesc -children=opList0 opList1 opList2 -count=2 -eventq_index=0 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -eventq_index=0 -opClass=FloatMult -opLat=4 -pipelined=true - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -eventq_index=0 -opClass=FloatDiv -opLat=12 -pipelined=false - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -eventq_index=0 -opClass=FloatSqrt -opLat=24 -pipelined=false - -[system.cpu.fuPool.FUList4] -type=FUDesc -children=opList -count=0 -eventq_index=0 -opList=system.cpu.fuPool.FUList4.opList - -[system.cpu.fuPool.FUList4.opList] -type=OpDesc -eventq_index=0 -opClass=MemRead -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5] -type=FUDesc -children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 -count=4 -eventq_index=0 -opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 - -[system.cpu.fuPool.FUList5.opList00] -type=OpDesc -eventq_index=0 -opClass=SimdAdd -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList01] -type=OpDesc -eventq_index=0 -opClass=SimdAddAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList02] -type=OpDesc -eventq_index=0 -opClass=SimdAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList03] -type=OpDesc -eventq_index=0 -opClass=SimdCmp -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList04] -type=OpDesc -eventq_index=0 -opClass=SimdCvt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList05] -type=OpDesc -eventq_index=0 -opClass=SimdMisc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList06] -type=OpDesc -eventq_index=0 -opClass=SimdMult -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList07] -type=OpDesc -eventq_index=0 -opClass=SimdMultAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList08] -type=OpDesc -eventq_index=0 -opClass=SimdShift -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList09] -type=OpDesc -eventq_index=0 -opClass=SimdShiftAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList10] -type=OpDesc -eventq_index=0 -opClass=SimdSqrt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList11] -type=OpDesc -eventq_index=0 -opClass=SimdFloatAdd -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList12] -type=OpDesc -eventq_index=0 -opClass=SimdFloatAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList13] -type=OpDesc -eventq_index=0 -opClass=SimdFloatCmp -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList14] -type=OpDesc -eventq_index=0 -opClass=SimdFloatCvt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList15] -type=OpDesc -eventq_index=0 -opClass=SimdFloatDiv -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList16] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMisc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList17] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMult -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList18] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMultAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList19] -type=OpDesc -eventq_index=0 -opClass=SimdFloatSqrt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList6] -type=FUDesc -children=opList -count=0 -eventq_index=0 -opList=system.cpu.fuPool.FUList6.opList - -[system.cpu.fuPool.FUList6.opList] -type=OpDesc -eventq_index=0 -opClass=MemWrite -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList7] -type=FUDesc -children=opList0 opList1 -count=4 -eventq_index=0 -opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -eventq_index=0 -opClass=MemRead -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList7.opList1] -type=OpDesc -eventq_index=0 -opClass=MemWrite -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList8] -type=FUDesc -children=opList -count=1 -eventq_index=0 -opList=system.cpu.fuPool.FUList8.opList - -[system.cpu.fuPool.FUList8.opList] -type=OpDesc -eventq_index=0 -opClass=IprAccess -opLat=3 -pipelined=false - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=hello -cwd= -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/tru64/hello -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=0:134217727:0:0:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=6000 -tXPDLL=0 -tXS=270000 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simerr --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simerr Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,5 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(1, ...) diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,15 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:19:49 -gem5 executing on e108600-lin, pid 28097 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/tru64/o3-timing - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Hello world! -Exiting @ tick 13358500 because target called exit() diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,1016 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000013 # Number of seconds simulated -sim_ticks 13358500 # Number of ticks simulated -final_tick 13358500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 102485 # Simulator instruction rate (inst/s) -host_op_rate 102439 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 573050673 # Simulator tick rate (ticks/s) -host_mem_usage 252720 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -sim_insts 2387 # Number of instructions simulated -sim_ops 2387 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 13358500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 11968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 5440 # Number of bytes read from this memory -system.physmem.bytes_read::total 17408 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 11968 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 11968 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 187 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory -system.physmem.num_reads::total 272 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 895908972 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 407231351 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1303140323 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 895908972 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 895908972 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 895908972 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 407231351 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1303140323 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 272 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 272 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 17408 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 17408 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 0 # Per bank write bursts -system.physmem.perBankRdBursts::1 1 # Per bank write bursts -system.physmem.perBankRdBursts::2 2 # Per bank write bursts -system.physmem.perBankRdBursts::3 24 # Per bank write bursts -system.physmem.perBankRdBursts::4 18 # Per bank write bursts -system.physmem.perBankRdBursts::5 0 # Per bank write bursts -system.physmem.perBankRdBursts::6 24 # Per bank write bursts -system.physmem.perBankRdBursts::7 37 # Per bank write bursts -system.physmem.perBankRdBursts::8 60 # Per bank write bursts -system.physmem.perBankRdBursts::9 2 # Per bank write bursts -system.physmem.perBankRdBursts::10 15 # Per bank write bursts -system.physmem.perBankRdBursts::11 9 # Per bank write bursts -system.physmem.perBankRdBursts::12 17 # Per bank write bursts -system.physmem.perBankRdBursts::13 50 # Per bank write bursts -system.physmem.perBankRdBursts::14 12 # Per bank write bursts -system.physmem.perBankRdBursts::15 1 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 13255000 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 272 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 155 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 80 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 36 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 384 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 235.532687 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 344.140835 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12 33.33% 33.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 4 11.11% 44.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4 11.11% 55.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 6 16.67% 72.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2 5.56% 77.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1 2.78% 80.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1 2.78% 83.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1 2.78% 86.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5 13.89% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 36 # Bytes accessed per row activation -system.physmem.totQLat 3364250 # Total ticks spent queuing -system.physmem.totMemAccLat 8464250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1360000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12368.57 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31118.57 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1303.14 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1303.14 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 10.18 # Data bus utilization in percentage -system.physmem.busUtilRead 10.18 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.73 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 224 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.35 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 48731.62 # Average gap between requests -system.physmem.pageHitRate 82.35 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 99960 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 37950 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 756840 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 614640.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1355460 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 21600 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 4583370 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 107040 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 7576860 # Total energy per rank (pJ) -system.physmem_0.averagePower 567.183307 # Core power per rank (mW) -system.physmem_0.totalIdleTime 10278500 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 28500 # Time in different power states -system.physmem_0.memoryStateTime::REF 260000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 0 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 279000 # Time in different power states -system.physmem_0.memoryStateTime::ACT 2735250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 10055750 # Time in different power states -system.physmem_1.actEnergy 242760 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 98670 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1185240 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 614640.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1822290 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 183840 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 4050420 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 480 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 8198340 # Total energy per rank (pJ) -system.physmem_1.averagePower 613.705624 # Core power per rank (mW) -system.physmem_1.totalIdleTime 8246250 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 450500 # Time in different power states -system.physmem_1.memoryStateTime::REF 260000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 0 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 1250 # Time in different power states -system.physmem_1.memoryStateTime::ACT 3767500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 8879250 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 13358500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 994 # Number of BP lookups -system.cpu.branchPred.condPredicted 488 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 213 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 684 # Number of BTB lookups -system.cpu.branchPred.BTBHits 175 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 25.584795 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 218 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 18 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 99 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 2 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 97 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 33 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 705 # DTB read hits -system.cpu.dtb.read_misses 10 # DTB read misses -system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_accesses 715 # DTB read accesses -system.cpu.dtb.write_hits 349 # DTB write hits -system.cpu.dtb.write_misses 16 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 365 # DTB write accesses -system.cpu.dtb.data_hits 1054 # DTB hits -system.cpu.dtb.data_misses 26 # DTB misses -system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 1080 # DTB accesses -system.cpu.itb.fetch_hits 872 # ITB hits -system.cpu.itb.fetch_misses 32 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 904 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 13358500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 26718 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 4379 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 6026 # Number of instructions fetch has processed -system.cpu.fetch.Branches 994 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 395 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1172 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 472 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1202 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 872 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 147 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 7018 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.858649 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.260497 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 5993 85.39% 85.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 27 0.38% 85.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 97 1.38% 87.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 87 1.24% 88.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 140 1.99% 90.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 81 1.15% 91.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 45 0.64% 92.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 75 1.07% 93.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 473 6.74% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 7018 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.037203 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.225541 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5261 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 642 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 913 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 39 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 163 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 144 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 75 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 5228 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 263 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 163 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 5336 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 333 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 302 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 873 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 11 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 5015 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full -system.cpu.rename.RenamedOperands 3598 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5603 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 5596 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 6 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1830 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 8 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 62 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 838 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 424 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 4336 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 3724 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 19 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 1954 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 987 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 7018 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.530636 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.266302 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 5580 79.51% 79.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 466 6.64% 86.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 341 4.86% 91.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 254 3.62% 94.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 190 2.71% 97.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 104 1.48% 98.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 55 0.78% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 20 0.28% 99.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 8 0.11% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 7018 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6 9.84% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 30 49.18% 59.02% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 24 39.34% 98.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 0 0.00% 98.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 1 1.64% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 2606 69.98% 69.98% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.03% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 745 20.01% 90.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 366 9.83% 99.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 99.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 6 0.16% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 3724 # Type of FU issued -system.cpu.iq.rate 0.139382 # Inst issue rate -system.cpu.iq.fu_busy_cnt 61 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.016380 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 14533 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 6293 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 3394 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 3778 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 32 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 423 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 4 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 130 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 42 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 163 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 304 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 3 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 4648 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 46 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 838 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 424 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 4 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 33 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 132 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 165 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 3600 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 717 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 124 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 306 # number of nop insts executed -system.cpu.iew.exec_refs 1082 # number of memory reference insts executed -system.cpu.iew.exec_branches 595 # Number of branches executed -system.cpu.iew.exec_stores 365 # Number of stores executed -system.cpu.iew.exec_rate 0.134741 # Inst execution rate -system.cpu.iew.wb_sent 3453 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 3400 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1619 # num instructions producing a value -system.cpu.iew.wb_consumers 2076 # num instructions consuming a value -system.cpu.iew.wb_rate 0.127255 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.779865 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 2070 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 140 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 6610 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.389713 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.245121 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 5740 86.84% 86.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 197 2.98% 89.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 319 4.83% 94.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 117 1.77% 96.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 63 0.95% 97.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 53 0.80% 98.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 36 0.54% 98.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 23 0.35% 99.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 62 0.94% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 6610 # Number of insts commited each cycle -system.cpu.commit.committedInsts 2576 # Number of instructions committed -system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 709 # Number of memory references committed -system.cpu.commit.loads 415 # Number of loads committed -system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 396 # Number of branches committed -system.cpu.commit.fp_insts 6 # Number of committed floating point instructions. -system.cpu.commit.int_insts 2367 # Number of committed integer instructions. -system.cpu.commit.function_calls 71 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 189 7.34% 7.34% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 1677 65.10% 72.44% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 1 0.04% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 72.48% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 415 16.11% 88.59% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 288 11.18% 99.77% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 99.77% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemWrite 6 0.23% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 2576 # Class of committed instruction -system.cpu.commit.bw_lim_events 62 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 10947 # The number of ROB reads -system.cpu.rob.rob_writes 9704 # The number of ROB writes -system.cpu.timesIdled 154 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19700 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 2387 # Number of Instructions Simulated -system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 11.193129 # CPI: Cycles Per Instruction -system.cpu.cpi_total 11.193129 # CPI: Total CPI of All Threads -system.cpu.ipc 0.089341 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.089341 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4344 # number of integer regfile reads -system.cpu.int_regfile_writes 2618 # number of integer regfile writes -system.cpu.fp_regfile_reads 6 # number of floating regfile reads -system.cpu.misc_regfile_reads 1 # number of misc regfile reads -system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 13358500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 45.378002 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 743 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.741176 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 45.378002 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.011079 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011079 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1935 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1935 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 13358500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 530 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 530 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 213 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 743 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 743 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 743 # number of overall hits -system.cpu.dcache.overall_hits::total 743 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 101 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 101 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 182 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 182 # number of overall misses -system.cpu.dcache.overall_misses::total 182 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7124500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7124500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 6134000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 6134000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13258500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13258500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13258500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13258500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 631 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 631 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 925 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 925 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 925 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 925 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.160063 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.160063 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.275510 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.275510 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.196757 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.196757 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.196757 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.196757 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70539.603960 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 70539.603960 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75728.395062 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 75728.395062 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 72848.901099 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 72848.901099 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 72848.901099 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 72848.901099 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 269 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 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-system.cpu.dcache.overall_mshr_hits::total 97 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 24 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5157500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5157500 # number of ReadReq MSHR miss cycles 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WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091892 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091892 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091892 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091892 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 84549.180328 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 84549.180328 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 83500 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 83500 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84252.941176 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 84252.941176 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84252.941176 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 84252.941176 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 13358500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 89.996713 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 618 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 187 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3.304813 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 89.996713 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.043944 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.043944 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 187 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 150 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.091309 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1931 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1931 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 13358500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 618 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 618 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 618 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 618 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(read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 20808999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 20808999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 872 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 872 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 872 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 872 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 872 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 872 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.291284 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.291284 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.291284 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.291284 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.291284 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.291284 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 81925.192913 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 81925.192913 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 81925.192913 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 81925.192913 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 81925.192913 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 81925.192913 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 131 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 65.500000 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 67 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 67 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 67 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 67 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 67 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 187 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 187 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 187 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 187 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 187 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15635499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15635499 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15635499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15635499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15635499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15635499 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.214450 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.214450 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.214450 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.214450 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.214450 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.214450 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83612.294118 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83612.294118 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83612.294118 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 83612.294118 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83612.294118 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 83612.294118 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 13358500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 135.588512 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 272 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 90.143699 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 45.444813 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002751 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001387 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004138 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 272 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 207 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.008301 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 2448 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 2448 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 13358500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadExReq_misses::cpu.data 24 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 24 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 187 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 187 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 61 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 61 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 187 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 85 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 272 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 187 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses -system.cpu.l2cache.overall_misses::total 272 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1966500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1966500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 15354000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 15354000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5066000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 5066000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 15354000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7032500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 22386500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 15354000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7032500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 22386500 # number of overall miss cycles -system.cpu.l2cache.ReadExReq_accesses::cpu.data 24 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 24 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 187 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 187 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 61 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 61 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 187 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 85 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 272 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 187 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 85 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 272 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss 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-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82106.951872 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82735.294118 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 82303.308824 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82106.951872 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82735.294118 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 82303.308824 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 24 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 24 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 187 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 187 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 61 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 61 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 187 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 272 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 272 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1726500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1726500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 13484000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 13484000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4456000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4456000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13484000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6182500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 19666500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13484000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6182500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19666500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71937.500000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71937.500000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72106.951872 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72106.951872 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73049.180328 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73049.180328 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72106.951872 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72735.294118 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72303.308824 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72106.951872 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72735.294118 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72303.308824 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 272 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 13358500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 248 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 24 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 24 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 187 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 61 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 374 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 170 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 544 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11968 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5440 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 17408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 272 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 272 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 272 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 136000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 280500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 127500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 272 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 13358500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 248 # Transaction distribution -system.membus.trans_dist::ReadExReq 24 # Transaction distribution -system.membus.trans_dist::ReadExResp 24 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 248 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 544 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 544 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17408 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17408 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 272 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 272 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 272 # Request fanout histogram -system.membus.reqLayer0.occupancy 337500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 1437500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 10.8 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,203 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=atomic -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=AtomicSimpleCPU -children=dtb interrupts isa itb tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -fastmem=false -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -simulate_data_stalls=false -simulate_inst_stalls=false -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -width=1 -workload=system.cpu.workload -dcache_port=system.membus.slave[2] -icache_port=system.membus.slave[1] - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=hello -cwd= -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/tru64/hello -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=Null -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.icache_port system.cpu.dcache_port - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=0:134217727 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simerr --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simerr Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,3 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: ignoring syscall sigprocmask(1, ...) diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,15 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 19 2016 12:24:25 -gem5 executing on e108600-lin, pid 39590 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/tru64/simple-atomic - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Hello world! -Exiting @ tick 1297500 because target called exit() diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,167 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000001 # Number of seconds simulated -sim_ticks 1297500 # Number of ticks simulated -final_tick 1297500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 601225 # Simulator instruction rate (inst/s) -host_op_rate 599847 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 301371607 # Simulator tick rate (ticks/s) -host_mem_usage 241196 # Number of bytes of host memory used -host_seconds 0.00 # Real time elapsed on the host -sim_insts 2577 # Number of instructions simulated -sim_ops 2577 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1297500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 10340 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 3016 # Number of bytes read from this memory -system.physmem.bytes_read::total 13356 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 10340 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 10340 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 2058 # Number of bytes written to this memory -system.physmem.bytes_written::total 2058 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2585 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 415 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3000 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 294 # Number of write requests responded to by this memory -system.physmem.num_writes::total 294 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7969171484 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2324470135 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10293641618 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7969171484 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7969171484 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1586127168 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1586127168 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7969171484 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3910597303 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 11879768786 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 1297500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 415 # DTB read hits -system.cpu.dtb.read_misses 4 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 419 # DTB read accesses -system.cpu.dtb.write_hits 294 # DTB write hits -system.cpu.dtb.write_misses 4 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 298 # DTB write accesses -system.cpu.dtb.data_hits 709 # DTB hits -system.cpu.dtb.data_misses 8 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 717 # DTB accesses -system.cpu.itb.fetch_hits 2585 # ITB hits -system.cpu.itb.fetch_misses 11 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2596 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 1297500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 2596 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 2577 # Number of instructions committed -system.cpu.committedOps 2577 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses -system.cpu.num_func_calls 140 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls -system.cpu.num_int_insts 2375 # number of integer instructions -system.cpu.num_fp_insts 6 # number of float instructions -system.cpu.num_int_register_reads 2998 # number of times the integer registers were read -system.cpu.num_int_register_writes 1768 # number of times the integer registers were written -system.cpu.num_fp_register_reads 6 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 717 # number of memory refs -system.cpu.num_load_insts 419 # Number of load instructions -system.cpu.num_store_insts 298 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 2596 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 396 # Number of branches fetched -system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction -system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction -system.cpu.op_class::MemWrite 292 11.30% 99.77% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 99.77% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 6 0.23% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 2585 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1297500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 3000 # Transaction distribution -system.membus.trans_dist::ReadResp 3000 # Transaction distribution -system.membus.trans_dist::WriteReq 294 # Transaction distribution -system.membus.trans_dist::WriteResp 294 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 5170 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1418 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6588 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 10340 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 5074 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15414 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 3294 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3294 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3294 # Request fanout histogram - ----------- End Simulation Statistics ---------- diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,1456 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000 -time_sync_spin_threshold=100000 - -[system] -type=System -children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges=0:268435455:0:0:0:0 -memories=system.mem_ctrls -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.sys_port_proxy.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=TimingSimpleCPU -children=clk_domain dtb interrupts isa itb tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu.clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1] -icache_port=system.ruby.l1_cntrl0.sequencer.slave[0] - -[system.cpu.clk_domain] -type=SrcClockDomain -clock=1 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=hello -cwd= -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/tru64/hello -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000 - -[system.mem_ctrls] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -page_policy=open_adaptive -power_model=Null -range=0:268435455:5:19:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10 -static_frontend_latency=10 -tBURST=5 -tCCD_L=0 -tCK=1 -tCL=14 -tCS=3 -tRAS=35 -tRCD=14 -tREFI=7800 -tRFC=260 -tRP=14 -tRRD=6 -tRRD_L=0 -tRTP=8 -tRTW=3 -tWR=15 -tWTR=8 -tXAW=30 -tXP=6 -tXPDLL=0 -tXS=270 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.ruby.dir_cntrl0.memory - -[system.ruby] -type=RubySystem -children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network -access_backing_store=false -all_instructions=false -block_size_bytes=64 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hot_lines=false -memory_size_bits=48 -num_of_sequencers=1 -number_of_virtual_networks=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -phys_mem=Null -power_model=Null -randomization=false - -[system.ruby.clk_domain] -type=SrcClockDomain -clock=1 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.ruby.dir_cntrl0] -type=Directory_Controller -children=directory requestToDir responseFromDir responseFromMemory responseToDir -buffer_size=0 -clk_domain=system.ruby.clk_domain -cluster_id=0 -default_p_state=UNDEFINED -directory=system.ruby.dir_cntrl0.directory -directory_latency=6 -eventq_index=0 -number_of_TBEs=256 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -recycle_latency=10 -requestToDir=system.ruby.dir_cntrl0.requestToDir -responseFromDir=system.ruby.dir_cntrl0.responseFromDir -responseFromMemory=system.ruby.dir_cntrl0.responseFromMemory -responseToDir=system.ruby.dir_cntrl0.responseToDir -ruby_system=system.ruby -system=system -to_mem_ctrl_latency=1 -transitions_per_cycle=4 -version=0 -memory=system.mem_ctrls.port - -[system.ruby.dir_cntrl0.directory] -type=RubyDirectoryMemory -eventq_index=0 -numa_high_bit=5 -size=268435456 -version=0 - -[system.ruby.dir_cntrl0.requestToDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[5] - -[system.ruby.dir_cntrl0.responseFromDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[6] - -[system.ruby.dir_cntrl0.responseFromMemory] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false - -[system.ruby.dir_cntrl0.responseToDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[6] - -[system.ruby.l1_cntrl0] -type=L1Cache_Controller -children=L1Dcache L1Icache mandatoryQueue optionalQueue prefetcher requestFromL1Cache requestToL1Cache responseFromL1Cache responseToL1Cache sequencer unblockFromL1Cache -L1Dcache=system.ruby.l1_cntrl0.L1Dcache -L1Icache=system.ruby.l1_cntrl0.L1Icache -buffer_size=0 -clk_domain=system.cpu.clk_domain -cluster_id=0 -default_p_state=UNDEFINED -enable_prefetch=false -eventq_index=0 -l1_request_latency=2 -l1_response_latency=2 -l2_select_num_bits=0 -mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue -number_of_TBEs=256 -optionalQueue=system.ruby.l1_cntrl0.optionalQueue -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -prefetcher=system.ruby.l1_cntrl0.prefetcher -recycle_latency=10 -requestFromL1Cache=system.ruby.l1_cntrl0.requestFromL1Cache -requestToL1Cache=system.ruby.l1_cntrl0.requestToL1Cache -responseFromL1Cache=system.ruby.l1_cntrl0.responseFromL1Cache -responseToL1Cache=system.ruby.l1_cntrl0.responseToL1Cache -ruby_system=system.ruby -send_evictions=false -sequencer=system.ruby.l1_cntrl0.sequencer -system=system -to_l2_latency=1 -transitions_per_cycle=4 -unblockFromL1Cache=system.ruby.l1_cntrl0.unblockFromL1Cache -version=0 - -[system.ruby.l1_cntrl0.L1Dcache] -type=RubyCache -children=replacement_policy -assoc=2 -block_size=0 -dataAccessLatency=1 -dataArrayBanks=1 -eventq_index=0 -is_icache=false -replacement_policy=system.ruby.l1_cntrl0.L1Dcache.replacement_policy -resourceStalls=false -ruby_system=system.ruby -size=256 -start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 - -[system.ruby.l1_cntrl0.L1Dcache.replacement_policy] -type=PseudoLRUReplacementPolicy -assoc=2 -block_size=64 -eventq_index=0 -size=256 - -[system.ruby.l1_cntrl0.L1Icache] -type=RubyCache -children=replacement_policy -assoc=2 -block_size=0 -dataAccessLatency=1 -dataArrayBanks=1 -eventq_index=0 -is_icache=true -replacement_policy=system.ruby.l1_cntrl0.L1Icache.replacement_policy -resourceStalls=false -ruby_system=system.ruby -size=256 -start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 - -[system.ruby.l1_cntrl0.L1Icache.replacement_policy] -type=PseudoLRUReplacementPolicy -assoc=2 -block_size=64 -eventq_index=0 -size=256 - -[system.ruby.l1_cntrl0.mandatoryQueue] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false - -[system.ruby.l1_cntrl0.optionalQueue] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false - -[system.ruby.l1_cntrl0.prefetcher] -type=Prefetcher -cross_page=false -eventq_index=0 -nonunit_filter=8 -num_startup_pfs=1 -num_streams=4 -pf_per_stream=1 -sys=system -train_misses=4 -unit_filter=8 - -[system.ruby.l1_cntrl0.requestFromL1Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[0] - -[system.ruby.l1_cntrl0.requestToL1Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[0] - -[system.ruby.l1_cntrl0.responseFromL1Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[1] - -[system.ruby.l1_cntrl0.responseToL1Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[1] - -[system.ruby.l1_cntrl0.sequencer] -type=RubySequencer -clk_domain=system.cpu.clk_domain -coreid=99 -dcache=system.ruby.l1_cntrl0.L1Dcache -dcache_hit_latency=1 -deadlock_threshold=500000 -default_p_state=UNDEFINED -eventq_index=0 -garnet_standalone=false -icache=system.ruby.l1_cntrl0.L1Icache -icache_hit_latency=1 -is_cpu_sequencer=true -max_outstanding_requests=16 -no_retry_on_stall=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -ruby_system=system.ruby -support_data_reqs=true -support_inst_reqs=true -system=system -using_ruby_tester=false -version=0 -slave=system.cpu.icache_port system.cpu.dcache_port - -[system.ruby.l1_cntrl0.unblockFromL1Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[2] - -[system.ruby.l2_cntrl0] -type=L2Cache_Controller -children=DirRequestFromL2Cache L1RequestFromL2Cache L1RequestToL2Cache L2cache responseFromL2Cache responseToL2Cache unblockToL2Cache -DirRequestFromL2Cache=system.ruby.l2_cntrl0.DirRequestFromL2Cache -L1RequestFromL2Cache=system.ruby.l2_cntrl0.L1RequestFromL2Cache -L1RequestToL2Cache=system.ruby.l2_cntrl0.L1RequestToL2Cache -L2cache=system.ruby.l2_cntrl0.L2cache -buffer_size=0 -clk_domain=system.ruby.clk_domain -cluster_id=0 -default_p_state=UNDEFINED -eventq_index=0 -l2_request_latency=2 -l2_response_latency=2 -number_of_TBEs=256 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -recycle_latency=10 -responseFromL2Cache=system.ruby.l2_cntrl0.responseFromL2Cache -responseToL2Cache=system.ruby.l2_cntrl0.responseToL2Cache -ruby_system=system.ruby -system=system -to_l1_latency=1 -transitions_per_cycle=4 -unblockToL2Cache=system.ruby.l2_cntrl0.unblockToL2Cache -version=0 - -[system.ruby.l2_cntrl0.DirRequestFromL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[3] - -[system.ruby.l2_cntrl0.L1RequestFromL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[4] - -[system.ruby.l2_cntrl0.L1RequestToL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[3] - -[system.ruby.l2_cntrl0.L2cache] -type=RubyCache -children=replacement_policy -assoc=2 -block_size=0 -dataAccessLatency=1 -dataArrayBanks=1 -eventq_index=0 -is_icache=false -replacement_policy=system.ruby.l2_cntrl0.L2cache.replacement_policy -resourceStalls=false -ruby_system=system.ruby -size=512 -start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 - -[system.ruby.l2_cntrl0.L2cache.replacement_policy] -type=PseudoLRUReplacementPolicy -assoc=2 -block_size=64 -eventq_index=0 -size=512 - -[system.ruby.l2_cntrl0.responseFromL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[5] - -[system.ruby.l2_cntrl0.responseToL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[4] - -[system.ruby.l2_cntrl0.unblockToL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[2] - -[system.ruby.memctrl_clk_domain] -type=DerivedClockDomain -clk_divider=3 -clk_domain=system.ruby.clk_domain -eventq_index=0 - -[system.ruby.network] -type=SimpleNetwork -children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 routers0 routers1 routers2 routers3 -adaptive_routing=false -buffer_size=0 -clk_domain=system.ruby.clk_domain -control_msg_size=8 -default_p_state=UNDEFINED -endpoint_bandwidth=1000 -eventq_index=0 -ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2 -int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 -int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4 system.ruby.network.int_links5 -netifs= -number_of_virtual_networks=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 system.ruby.network.routers3 -ruby_system=system.ruby -topology=Crossbar -master=system.ruby.l1_cntrl0.requestToL1Cache.slave system.ruby.l1_cntrl0.responseToL1Cache.slave system.ruby.l2_cntrl0.unblockToL2Cache.slave system.ruby.l2_cntrl0.L1RequestToL2Cache.slave system.ruby.l2_cntrl0.responseToL2Cache.slave system.ruby.dir_cntrl0.requestToDir.slave system.ruby.dir_cntrl0.responseToDir.slave -slave=system.ruby.l1_cntrl0.requestFromL1Cache.master system.ruby.l1_cntrl0.responseFromL1Cache.master system.ruby.l1_cntrl0.unblockFromL1Cache.master system.ruby.l2_cntrl0.DirRequestFromL2Cache.master system.ruby.l2_cntrl0.L1RequestFromL2Cache.master system.ruby.l2_cntrl0.responseFromL2Cache.master system.ruby.dir_cntrl0.responseFromDir.master - -[system.ruby.network.ext_links0] -type=SimpleExtLink -bandwidth_factor=16 -eventq_index=0 -ext_node=system.ruby.l1_cntrl0 -int_node=system.ruby.network.routers0 -latency=1 -link_id=0 -weight=1 - -[system.ruby.network.ext_links1] -type=SimpleExtLink -bandwidth_factor=16 -eventq_index=0 -ext_node=system.ruby.l2_cntrl0 -int_node=system.ruby.network.routers1 -latency=1 -link_id=1 -weight=1 - -[system.ruby.network.ext_links2] -type=SimpleExtLink -bandwidth_factor=16 -eventq_index=0 -ext_node=system.ruby.dir_cntrl0 -int_node=system.ruby.network.routers2 -latency=1 -link_id=2 -weight=1 - -[system.ruby.network.int_link_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers15] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers16] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers17] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers18] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers19] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers20] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers21] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers22] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers23] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers24] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers25] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers26] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers27] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers28] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers29] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers30] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers31] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers32] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers33] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers34] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers35] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_links0] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers3 -eventq_index=0 -latency=1 -link_id=3 -src_node=system.ruby.network.routers0 -src_outport= -weight=1 - -[system.ruby.network.int_links1] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers3 -eventq_index=0 -latency=1 -link_id=4 -src_node=system.ruby.network.routers1 -src_outport= -weight=1 - -[system.ruby.network.int_links2] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers3 -eventq_index=0 -latency=1 -link_id=5 -src_node=system.ruby.network.routers2 -src_outport= -weight=1 - -[system.ruby.network.int_links3] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers0 -eventq_index=0 -latency=1 -link_id=6 -src_node=system.ruby.network.routers3 -src_outport= -weight=1 - -[system.ruby.network.int_links4] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers1 -eventq_index=0 -latency=1 -link_id=7 -src_node=system.ruby.network.routers3 -src_outport= -weight=1 - -[system.ruby.network.int_links5] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers2 -eventq_index=0 -latency=1 -link_id=8 -src_node=system.ruby.network.routers3 -src_outport= -weight=1 - -[system.ruby.network.routers0] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 -power_model=Null -router_id=0 -virt_nets=3 - -[system.ruby.network.routers0.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 -power_model=Null -router_id=1 -virt_nets=3 - -[system.ruby.network.routers1.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 -power_model=Null -router_id=2 -virt_nets=3 - -[system.ruby.network.routers2.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers3.port_buffers00 system.ruby.network.routers3.port_buffers01 system.ruby.network.routers3.port_buffers02 system.ruby.network.routers3.port_buffers03 system.ruby.network.routers3.port_buffers04 system.ruby.network.routers3.port_buffers05 system.ruby.network.routers3.port_buffers06 system.ruby.network.routers3.port_buffers07 system.ruby.network.routers3.port_buffers08 system.ruby.network.routers3.port_buffers09 system.ruby.network.routers3.port_buffers10 system.ruby.network.routers3.port_buffers11 system.ruby.network.routers3.port_buffers12 system.ruby.network.routers3.port_buffers13 system.ruby.network.routers3.port_buffers14 system.ruby.network.routers3.port_buffers15 system.ruby.network.routers3.port_buffers16 system.ruby.network.routers3.port_buffers17 -power_model=Null -router_id=3 -virt_nets=3 - -[system.ruby.network.routers3.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers15] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers16] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers17] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.sys_port_proxy] -type=RubyPortProxy -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_cpu_sequencer=true -no_retry_on_stall=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -ruby_system=system.ruby -support_data_reqs=true -support_inst_reqs=true -system=system -using_ruby_tester=false -version=0 -slave=system.system_port - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,11 +0,0 @@ -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! -warn: ignoring syscall sigprocmask(1, ...) diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simout --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simout Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,15 +0,0 @@ -Redirecting stdout to build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simout -Redirecting stderr to build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 13 2016 20:28:06 -gem5 started Oct 13 2016 20:28:32 -gem5 executing on e108600-lin, pid 8237 -command line: /work/curdun01/gem5-external.hg/build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_Two_Level -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_Two_Level - -Global frequency set at 1000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Hello world! -Exiting @ tick 48659 because target called exit() diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,758 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000049 # Number of seconds simulated -sim_ticks 48659 # Number of ticks simulated -final_tick 48659 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 67712 # Simulator instruction rate (inst/s) -host_op_rate 67695 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1277923 # Simulator tick rate (ticks/s) -host_mem_usage 411644 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host -sim_insts 2577 # Number of instructions simulated -sim_ops 2577 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 35008 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 35008 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 6592 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 6592 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 547 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 547 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 103 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 103 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 719455805 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 719455805 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 135473396 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 135473396 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 854929201 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 854929201 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 547 # Number of read requests accepted -system.mem_ctrls.writeReqs 103 # Number of write requests accepted -system.mem_ctrls.readBursts 547 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 103 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 28032 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 6976 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 1024 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 35008 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 6592 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 109 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 57 # Number of DRAM write bursts merged with an existing one -system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 1 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 1 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 43 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 31 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 26 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 84 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 84 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::9 4 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 37 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 24 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 26 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 64 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 12 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 1 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 3 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 5 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 7 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::15 1 # Per bank write bursts -system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 48574 # Total gap between requests -system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 547 # Read request sizes (log2) -system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 103 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 438 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::12 0 # 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-system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 2 # What 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-system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does 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write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 83 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 339.277108 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 221.785975 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 292.728223 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 23 27.71% 27.71% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 19 22.89% 50.60% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 6 7.23% 57.83% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 10 12.05% 69.88% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 11 13.25% 83.13% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 4 4.82% 87.95% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 3 3.61% 91.57% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 3 3.61% 95.18% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 4 4.82% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 83 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 1 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 268 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 268.000000 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev nan # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::256-271 1 100.00% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 1 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 1 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev nan # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 1 100.00% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 1 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 5659 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 13981 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 2190 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 12.92 # Average queueing delay per DRAM burst -system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 31.92 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 576.09 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 21.04 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 719.46 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 135.47 # Average system write bandwidth in MiByte/s -system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 4.67 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 4.50 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 0.16 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 22.48 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 349 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 15 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 79.68 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 32.61 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 74.73 # Average gap between requests -system.mem_ctrls.pageHitRate 75.21 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 199920 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 92736 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 2124864 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 3687840.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 3071616 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 85248 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.actPowerDownEnergy 18833256 # Energy for active power-down per rank (pJ) -system.mem_ctrls_0.prePowerDownEnergy 153600 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrls_0.totalEnergy 28249080 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 580.552005 # Core power per rank (mW) -system.mem_ctrls_0.totalIdleTime 41659 # Total Idle time Per DRAM Rank -system.mem_ctrls_0.memoryStateTime::IDLE 54 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 1560 # Time in different power states -system.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::PRE_PDN 400 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 5344 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 41301 # Time in different power states -system.mem_ctrls_1.actEnergy 442680 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 227976 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 2878848 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 133632 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 3687840.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 4289136 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 272256 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.actPowerDownEnergy 17021568 # Energy for active power-down per rank (pJ) -system.mem_ctrls_1.prePowerDownEnergy 466944 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrls_1.totalEnergy 29420880 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 604.633881 # Core power per rank (mW) -system.mem_ctrls_1.totalIdleTime 37647 # Total Idle time Per DRAM Rank -system.mem_ctrls_1.memoryStateTime::IDLE 541 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 1560 # Time in different power states -system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 1216 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 8014 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT_PDN 37328 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states -system.cpu.clk_domain.clock 1 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 415 # DTB read hits -system.cpu.dtb.read_misses 4 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 419 # DTB read accesses -system.cpu.dtb.write_hits 294 # DTB write hits -system.cpu.dtb.write_misses 4 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 298 # DTB write accesses -system.cpu.dtb.data_hits 709 # DTB hits -system.cpu.dtb.data_misses 8 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 717 # DTB accesses -system.cpu.itb.fetch_hits 2586 # ITB hits -system.cpu.itb.fetch_misses 11 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2597 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 48659 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 48659 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 2577 # Number of instructions committed -system.cpu.committedOps 2577 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses -system.cpu.num_func_calls 140 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls -system.cpu.num_int_insts 2375 # number of integer instructions -system.cpu.num_fp_insts 6 # number of float instructions -system.cpu.num_int_register_reads 2998 # number of times the integer registers were read -system.cpu.num_int_register_writes 1768 # number of times the integer registers were written -system.cpu.num_fp_register_reads 6 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 717 # number of memory refs -system.cpu.num_load_insts 419 # Number of load instructions -system.cpu.num_store_insts 298 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 48659 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 396 # Number of branches fetched -system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction -system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction -system.cpu.op_class::MemWrite 292 11.30% 99.77% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 99.77% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 6 0.23% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 2585 # Class of executed instruction -system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states -system.ruby.delayHist::bucket_size 1 # delay histogram for all message -system.ruby.delayHist::max_bucket 9 # delay histogram for all message -system.ruby.delayHist::samples 3612 # delay histogram for all message -system.ruby.delayHist::mean 0.144518 # delay histogram for all message -system.ruby.delayHist::stdev 0.930805 # delay histogram for all message -system.ruby.delayHist | 3486 96.51% 96.51% | 0 0.00% 96.51% | 81 2.24% 98.75% | 0 0.00% 98.75% | 0 0.00% 98.75% | 0 0.00% 98.75% | 0 0.00% 98.75% | 0 0.00% 98.75% | 45 1.25% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 3612 # delay histogram for all message -system.ruby.outstanding_req_hist_seqr::bucket_size 1 -system.ruby.outstanding_req_hist_seqr::max_bucket 9 -system.ruby.outstanding_req_hist_seqr::samples 3295 -system.ruby.outstanding_req_hist_seqr::mean 1 -system.ruby.outstanding_req_hist_seqr::gmean 1 -system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 3295 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist_seqr::total 3295 -system.ruby.latency_hist_seqr::bucket_size 64 -system.ruby.latency_hist_seqr::max_bucket 639 -system.ruby.latency_hist_seqr::samples 3294 -system.ruby.latency_hist_seqr::mean 13.772010 -system.ruby.latency_hist_seqr::gmean 2.084389 -system.ruby.latency_hist_seqr::stdev 31.264017 -system.ruby.latency_hist_seqr | 2856 86.70% 86.70% | 431 13.08% 99.79% | 1 0.03% 99.82% | 0 0.00% 99.82% | 2 0.06% 99.88% | 4 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist_seqr::total 3294 -system.ruby.hit_latency_hist_seqr::bucket_size 1 -system.ruby.hit_latency_hist_seqr::max_bucket 9 -system.ruby.hit_latency_hist_seqr::samples 2722 -system.ruby.hit_latency_hist_seqr::mean 1 -system.ruby.hit_latency_hist_seqr::gmean 1 -system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 2722 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist_seqr::total 2722 -system.ruby.miss_latency_hist_seqr::bucket_size 64 -system.ruby.miss_latency_hist_seqr::max_bucket 639 -system.ruby.miss_latency_hist_seqr::samples 572 -system.ruby.miss_latency_hist_seqr::mean 74.550699 -system.ruby.miss_latency_hist_seqr::gmean 68.693513 -system.ruby.miss_latency_hist_seqr::stdev 34.041428 -system.ruby.miss_latency_hist_seqr | 134 23.43% 23.43% | 431 75.35% 98.78% | 1 0.17% 98.95% | 0 0.00% 98.95% | 2 0.35% 99.30% | 4 0.70% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist_seqr::total 572 -system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.L1Dcache.demand_hits 437 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 272 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Icache.demand_hits 2285 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Icache.demand_misses 300 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Icache.demand_accesses 2585 # Number of cache demand accesses -system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed -system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching -system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made -system.ruby.l1_cntrl0.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted -system.ruby.l1_cntrl0.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped -system.ruby.l1_cntrl0.prefetcher.hits 0 # number of prefetched blocks accessed -system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched -system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages -system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states -system.ruby.l2_cntrl0.L2cache.demand_hits 25 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 547 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 572 # Number of cache demand accesses -system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.percent_links_utilized 4.088658 -system.ruby.network.routers0.msg_count.Control::0 572 -system.ruby.network.routers0.msg_count.Request_Control::2 431 -system.ruby.network.routers0.msg_count.Response_Data::1 572 -system.ruby.network.routers0.msg_count.Response_Control::1 493 -system.ruby.network.routers0.msg_count.Response_Control::2 272 -system.ruby.network.routers0.msg_count.Writeback_Data::0 45 -system.ruby.network.routers0.msg_count.Writeback_Data::1 62 -system.ruby.network.routers0.msg_count.Writeback_Control::0 79 -system.ruby.network.routers0.msg_bytes.Control::0 4576 -system.ruby.network.routers0.msg_bytes.Request_Control::2 3448 -system.ruby.network.routers0.msg_bytes.Response_Data::1 41184 -system.ruby.network.routers0.msg_bytes.Response_Control::1 3944 -system.ruby.network.routers0.msg_bytes.Response_Control::2 2176 -system.ruby.network.routers0.msg_bytes.Writeback_Data::0 3240 -system.ruby.network.routers0.msg_bytes.Writeback_Data::1 4464 -system.ruby.network.routers0.msg_bytes.Writeback_Control::0 632 -system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states -system.ruby.network.routers1.percent_links_utilized 7.876241 -system.ruby.network.routers1.msg_count.Control::0 1119 -system.ruby.network.routers1.msg_count.Request_Control::2 431 -system.ruby.network.routers1.msg_count.Response_Data::1 1222 -system.ruby.network.routers1.msg_count.Response_Control::1 1468 -system.ruby.network.routers1.msg_count.Response_Control::2 272 -system.ruby.network.routers1.msg_count.Writeback_Data::0 45 -system.ruby.network.routers1.msg_count.Writeback_Data::1 62 -system.ruby.network.routers1.msg_count.Writeback_Control::0 79 -system.ruby.network.routers1.msg_bytes.Control::0 8952 -system.ruby.network.routers1.msg_bytes.Request_Control::2 3448 -system.ruby.network.routers1.msg_bytes.Response_Data::1 87984 -system.ruby.network.routers1.msg_bytes.Response_Control::1 11744 -system.ruby.network.routers1.msg_bytes.Response_Control::2 2176 -system.ruby.network.routers1.msg_bytes.Writeback_Data::0 3240 -system.ruby.network.routers1.msg_bytes.Writeback_Data::1 4464 -system.ruby.network.routers1.msg_bytes.Writeback_Control::0 632 -system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states -system.ruby.network.routers2.percent_links_utilized 3.787583 -system.ruby.network.routers2.msg_count.Control::0 547 -system.ruby.network.routers2.msg_count.Response_Data::1 650 -system.ruby.network.routers2.msg_count.Response_Control::1 975 -system.ruby.network.routers2.msg_bytes.Control::0 4376 -system.ruby.network.routers2.msg_bytes.Response_Data::1 46800 -system.ruby.network.routers2.msg_bytes.Response_Control::1 7800 -system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states -system.ruby.network.routers3.percent_links_utilized 5.250827 -system.ruby.network.routers3.msg_count.Control::0 1119 -system.ruby.network.routers3.msg_count.Request_Control::2 431 -system.ruby.network.routers3.msg_count.Response_Data::1 1222 -system.ruby.network.routers3.msg_count.Response_Control::1 1468 -system.ruby.network.routers3.msg_count.Response_Control::2 272 -system.ruby.network.routers3.msg_count.Writeback_Data::0 45 -system.ruby.network.routers3.msg_count.Writeback_Data::1 62 -system.ruby.network.routers3.msg_count.Writeback_Control::0 79 -system.ruby.network.routers3.msg_bytes.Control::0 8952 -system.ruby.network.routers3.msg_bytes.Request_Control::2 3448 -system.ruby.network.routers3.msg_bytes.Response_Data::1 87984 -system.ruby.network.routers3.msg_bytes.Response_Control::1 11744 -system.ruby.network.routers3.msg_bytes.Response_Control::2 2176 -system.ruby.network.routers3.msg_bytes.Writeback_Data::0 3240 -system.ruby.network.routers3.msg_bytes.Writeback_Data::1 4464 -system.ruby.network.routers3.msg_bytes.Writeback_Control::0 632 -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states -system.ruby.network.msg_count.Control 3357 -system.ruby.network.msg_count.Request_Control 1293 -system.ruby.network.msg_count.Response_Data 3666 -system.ruby.network.msg_count.Response_Control 5220 -system.ruby.network.msg_count.Writeback_Data 321 -system.ruby.network.msg_count.Writeback_Control 237 -system.ruby.network.msg_byte.Control 26856 -system.ruby.network.msg_byte.Request_Control 10344 -system.ruby.network.msg_byte.Response_Data 263952 -system.ruby.network.msg_byte.Response_Control 41760 -system.ruby.network.msg_byte.Writeback_Data 23112 -system.ruby.network.msg_byte.Writeback_Control 1896 -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.throttle0.link_utilization 5.860170 -system.ruby.network.routers0.throttle0.msg_count.Request_Control::2 431 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 572 -system.ruby.network.routers0.throttle0.msg_count.Response_Control::1 124 -system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::2 3448 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1 41184 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1 992 -system.ruby.network.routers0.throttle1.link_utilization 2.317146 -system.ruby.network.routers0.throttle1.msg_count.Control::0 572 -system.ruby.network.routers0.throttle1.msg_count.Response_Control::1 369 -system.ruby.network.routers0.throttle1.msg_count.Response_Control::2 272 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::0 45 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::1 62 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 79 -system.ruby.network.routers0.throttle1.msg_bytes.Control::0 4576 -system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::1 2952 -system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2 2176 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0 3240 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1 4464 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 632 -system.ruby.network.routers1.throttle0.link_utilization 7.929674 -system.ruby.network.routers1.throttle0.msg_count.Control::0 572 -system.ruby.network.routers1.throttle0.msg_count.Response_Data::1 547 -system.ruby.network.routers1.throttle0.msg_count.Response_Control::1 908 -system.ruby.network.routers1.throttle0.msg_count.Response_Control::2 272 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::0 45 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::1 62 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0 79 -system.ruby.network.routers1.throttle0.msg_bytes.Control::0 4576 -system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::1 39384 -system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::1 7264 -system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::2 2176 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::0 3240 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::1 4464 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 632 -system.ruby.network.routers1.throttle1.link_utilization 7.822808 -system.ruby.network.routers1.throttle1.msg_count.Control::0 547 -system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 431 -system.ruby.network.routers1.throttle1.msg_count.Response_Data::1 675 -system.ruby.network.routers1.throttle1.msg_count.Response_Control::1 560 -system.ruby.network.routers1.throttle1.msg_bytes.Control::0 4376 -system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2 3448 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1 48600 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1 4480 -system.ruby.network.routers2.throttle0.link_utilization 1.962638 -system.ruby.network.routers2.throttle0.msg_count.Control::0 547 -system.ruby.network.routers2.throttle0.msg_count.Response_Data::1 103 -system.ruby.network.routers2.throttle0.msg_count.Response_Control::1 436 -system.ruby.network.routers2.throttle0.msg_bytes.Control::0 4376 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1 7416 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1 3488 -system.ruby.network.routers2.throttle1.link_utilization 5.612528 -system.ruby.network.routers2.throttle1.msg_count.Response_Data::1 547 -system.ruby.network.routers2.throttle1.msg_count.Response_Control::1 539 -system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1 39384 -system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1 4312 -system.ruby.network.routers3.throttle0.link_utilization 5.860170 -system.ruby.network.routers3.throttle0.msg_count.Request_Control::2 431 -system.ruby.network.routers3.throttle0.msg_count.Response_Data::1 572 -system.ruby.network.routers3.throttle0.msg_count.Response_Control::1 124 -system.ruby.network.routers3.throttle0.msg_bytes.Request_Control::2 3448 -system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1 41184 -system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1 992 -system.ruby.network.routers3.throttle1.link_utilization 7.929674 -system.ruby.network.routers3.throttle1.msg_count.Control::0 572 -system.ruby.network.routers3.throttle1.msg_count.Response_Data::1 547 -system.ruby.network.routers3.throttle1.msg_count.Response_Control::1 908 -system.ruby.network.routers3.throttle1.msg_count.Response_Control::2 272 -system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::0 45 -system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::1 62 -system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::0 79 -system.ruby.network.routers3.throttle1.msg_bytes.Control::0 4576 -system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::1 39384 -system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::1 7264 -system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::2 2176 -system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::0 3240 -system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::1 4464 -system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 632 -system.ruby.network.routers3.throttle2.link_utilization 1.962638 -system.ruby.network.routers3.throttle2.msg_count.Control::0 547 -system.ruby.network.routers3.throttle2.msg_count.Response_Data::1 103 -system.ruby.network.routers3.throttle2.msg_count.Response_Control::1 436 -system.ruby.network.routers3.throttle2.msg_bytes.Control::0 4376 -system.ruby.network.routers3.throttle2.msg_bytes.Response_Data::1 7416 -system.ruby.network.routers3.throttle2.msg_bytes.Response_Control::1 3488 -system.ruby.delayVCHist.vnet_0::bucket_size 1 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::max_bucket 9 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::samples 968 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::mean 0.371901 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::stdev 1.685180 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0 | 923 95.35% 95.35% | 0 0.00% 95.35% | 0 0.00% 95.35% | 0 0.00% 95.35% | 0 0.00% 95.35% | 0 0.00% 95.35% | 0 0.00% 95.35% | 0 0.00% 95.35% | 45 4.65% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::total 968 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::samples 2213 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::mean 0.073204 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::stdev 0.375650 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1 | 2132 96.34% 96.34% | 0 0.00% 96.34% | 81 3.66% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::total 2213 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::samples 431 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2 | 431 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::total 431 # delay histogram for vnet_2 -system.ruby.LD.latency_hist_seqr::bucket_size 64 -system.ruby.LD.latency_hist_seqr::max_bucket 639 -system.ruby.LD.latency_hist_seqr::samples 415 -system.ruby.LD.latency_hist_seqr::mean 33.824096 -system.ruby.LD.latency_hist_seqr::gmean 7.531942 -system.ruby.LD.latency_hist_seqr::stdev 41.807535 -system.ruby.LD.latency_hist_seqr | 298 71.81% 71.81% | 115 27.71% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 2 0.48% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist_seqr::total 415 -system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 -system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 -system.ruby.LD.hit_latency_hist_seqr::samples 211 -system.ruby.LD.hit_latency_hist_seqr::mean 1 -system.ruby.LD.hit_latency_hist_seqr::gmean 1 -system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 211 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist_seqr::total 211 -system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 -system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 -system.ruby.LD.miss_latency_hist_seqr::samples 204 -system.ruby.LD.miss_latency_hist_seqr::mean 67.774510 -system.ruby.LD.miss_latency_hist_seqr::gmean 60.800044 -system.ruby.LD.miss_latency_hist_seqr::stdev 35.866860 -system.ruby.LD.miss_latency_hist_seqr | 87 42.65% 42.65% | 115 56.37% 99.02% | 0 0.00% 99.02% | 0 0.00% 99.02% | 0 0.00% 99.02% | 2 0.98% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist_seqr::total 204 -system.ruby.ST.latency_hist_seqr::bucket_size 16 -system.ruby.ST.latency_hist_seqr::max_bucket 159 -system.ruby.ST.latency_hist_seqr::samples 294 -system.ruby.ST.latency_hist_seqr::mean 14.469388 -system.ruby.ST.latency_hist_seqr::gmean 2.523301 -system.ruby.ST.latency_hist_seqr::stdev 26.779037 -system.ruby.ST.latency_hist_seqr | 226 76.87% 76.87% | 4 1.36% 78.23% | 33 11.22% 89.46% | 1 0.34% 89.80% | 14 4.76% 94.56% | 14 4.76% 99.32% | 2 0.68% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist_seqr::total 294 -system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 -system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 -system.ruby.ST.hit_latency_hist_seqr::samples 226 -system.ruby.ST.hit_latency_hist_seqr::mean 1 -system.ruby.ST.hit_latency_hist_seqr::gmean 1 -system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 226 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist_seqr::total 226 -system.ruby.ST.miss_latency_hist_seqr::bucket_size 16 -system.ruby.ST.miss_latency_hist_seqr::max_bucket 159 -system.ruby.ST.miss_latency_hist_seqr::samples 68 -system.ruby.ST.miss_latency_hist_seqr::mean 59.235294 -system.ruby.ST.miss_latency_hist_seqr::gmean 54.692111 -system.ruby.ST.miss_latency_hist_seqr::stdev 22.140068 -system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 4 5.88% 5.88% | 33 48.53% 54.41% | 1 1.47% 55.88% | 14 20.59% 76.47% | 14 20.59% 97.06% | 2 2.94% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist_seqr::total 68 -system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 -system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.latency_hist_seqr::samples 2585 -system.ruby.IFETCH.latency_hist_seqr::mean 10.473501 -system.ruby.IFETCH.latency_hist_seqr::gmean 1.659469 -system.ruby.IFETCH.latency_hist_seqr::stdev 28.438724 -system.ruby.IFETCH.latency_hist_seqr | 2294 88.74% 88.74% | 286 11.06% 99.81% | 1 0.04% 99.85% | 0 0.00% 99.85% | 2 0.08% 99.92% | 2 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist_seqr::total 2585 -system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 -system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 -system.ruby.IFETCH.hit_latency_hist_seqr::samples 2285 -system.ruby.IFETCH.hit_latency_hist_seqr::mean 1 -system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 -system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 2285 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist_seqr::total 2285 -system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 -system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.miss_latency_hist_seqr::samples 300 -system.ruby.IFETCH.miss_latency_hist_seqr::mean 82.630000 -system.ruby.IFETCH.miss_latency_hist_seqr::gmean 78.596235 -system.ruby.IFETCH.miss_latency_hist_seqr::stdev 32.857141 -system.ruby.IFETCH.miss_latency_hist_seqr | 9 3.00% 3.00% | 286 95.33% 98.33% | 1 0.33% 98.67% | 0 0.00% 98.67% | 2 0.67% 99.33% | 2 0.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.miss_latency_hist_seqr::total 300 -system.ruby.Directory_Controller.Fetch 547 0.00% 0.00% -system.ruby.Directory_Controller.Data 103 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 547 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 103 0.00% 0.00% -system.ruby.Directory_Controller.CleanReplacement 436 0.00% 0.00% -system.ruby.Directory_Controller.I.Fetch 547 0.00% 0.00% -system.ruby.Directory_Controller.M.Data 103 0.00% 0.00% -system.ruby.Directory_Controller.M.CleanReplacement 436 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 547 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 103 0.00% 0.00% -system.ruby.L1Cache_Controller.Load 415 0.00% 0.00% -system.ruby.L1Cache_Controller.Ifetch 2585 0.00% 0.00% -system.ruby.L1Cache_Controller.Store 294 0.00% 0.00% -system.ruby.L1Cache_Controller.Inv 431 0.00% 0.00% -system.ruby.L1Cache_Controller.L1_Replacement 502 0.00% 0.00% -system.ruby.L1Cache_Controller.Data_Exclusive 204 0.00% 0.00% -system.ruby.L1Cache_Controller.Data_all_Acks 368 0.00% 0.00% -system.ruby.L1Cache_Controller.WB_Ack 124 0.00% 0.00% -system.ruby.L1Cache_Controller.NP.Load 182 0.00% 0.00% -system.ruby.L1Cache_Controller.NP.Ifetch 270 0.00% 0.00% -system.ruby.L1Cache_Controller.NP.Store 58 0.00% 0.00% -system.ruby.L1Cache_Controller.NP.Inv 162 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Load 22 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Ifetch 30 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Store 10 0.00% 0.00% -system.ruby.L1Cache_Controller.I.L1_Replacement 206 0.00% 0.00% -system.ruby.L1Cache_Controller.S.Ifetch 2285 0.00% 0.00% -system.ruby.L1Cache_Controller.S.Inv 124 0.00% 0.00% -system.ruby.L1Cache_Controller.S.L1_Replacement 172 0.00% 0.00% -system.ruby.L1Cache_Controller.E.Load 140 0.00% 0.00% -system.ruby.L1Cache_Controller.E.Store 41 0.00% 0.00% -system.ruby.L1Cache_Controller.E.Inv 83 0.00% 0.00% -system.ruby.L1Cache_Controller.E.L1_Replacement 79 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Load 71 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Store 185 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Inv 62 0.00% 0.00% -system.ruby.L1Cache_Controller.M.L1_Replacement 45 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Data_Exclusive 204 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Data_all_Acks 300 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.Data_all_Acks 68 0.00% 0.00% -system.ruby.L1Cache_Controller.M_I.WB_Ack 124 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GET_INSTR 300 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETS 204 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETX 68 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTX 124 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement 43 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement_clean 496 0.00% 0.00% -system.ruby.L2Cache_Controller.Mem_Data 547 0.00% 0.00% -system.ruby.L2Cache_Controller.Mem_Ack 539 0.00% 0.00% -system.ruby.L2Cache_Controller.WB_Data 62 0.00% 0.00% -system.ruby.L2Cache_Controller.Ack_all 369 0.00% 0.00% -system.ruby.L2Cache_Controller.Exclusive_Unblock 272 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GET_INSTR 291 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETS 192 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETX 64 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GET_INSTR 9 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 286 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETS 12 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETX 4 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement 39 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement_clean 69 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_PUTX 124 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L2_Replacement 4 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 141 0.00% 0.00% -system.ruby.L2Cache_Controller.M_I.Mem_Ack 539 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_I.WB_Data 2 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_I.Ack_all 2 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.WB_Data 60 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.Ack_all 81 0.00% 0.00% -system.ruby.L2Cache_Controller.I_I.Ack_all 286 0.00% 0.00% -system.ruby.L2Cache_Controller.ISS.Mem_Data 192 0.00% 0.00% -system.ruby.L2Cache_Controller.IS.Mem_Data 291 0.00% 0.00% -system.ruby.L2Cache_Controller.IM.Mem_Data 64 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 272 0.00% 0.00% - ----------- End Simulation Statistics ---------- diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,1448 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000 -time_sync_spin_threshold=100000 - -[system] -type=System -children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges=0:268435455:0:0:0:0 -memories=system.mem_ctrls -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.sys_port_proxy.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=TimingSimpleCPU -children=clk_domain dtb interrupts isa itb tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu.clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1] -icache_port=system.ruby.l1_cntrl0.sequencer.slave[0] - -[system.cpu.clk_domain] -type=SrcClockDomain -clock=1 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=hello -cwd= -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/tru64/hello -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000 - -[system.mem_ctrls] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -page_policy=open_adaptive -power_model=Null -range=0:268435455:5:19:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10 -static_frontend_latency=10 -tBURST=5 -tCCD_L=0 -tCK=1 -tCL=14 -tCS=3 -tRAS=35 -tRCD=14 -tREFI=7800 -tRFC=260 -tRP=14 -tRRD=6 -tRRD_L=0 -tRTP=8 -tRTW=3 -tWR=15 -tWTR=8 -tXAW=30 -tXP=6 -tXPDLL=0 -tXS=270 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.ruby.dir_cntrl0.memory - -[system.ruby] -type=RubySystem -children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network -access_backing_store=false -all_instructions=false -block_size_bytes=64 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hot_lines=false -memory_size_bits=48 -num_of_sequencers=1 -number_of_virtual_networks=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -phys_mem=Null -power_model=Null -randomization=false - -[system.ruby.clk_domain] -type=SrcClockDomain -clock=1 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.ruby.dir_cntrl0] -type=Directory_Controller -children=directory forwardFromDir requestToDir responseFromDir responseFromMemory responseToDir -buffer_size=0 -clk_domain=system.ruby.clk_domain -cluster_id=0 -default_p_state=UNDEFINED -directory=system.ruby.dir_cntrl0.directory -directory_latency=6 -eventq_index=0 -forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir -number_of_TBEs=256 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -recycle_latency=10 -requestToDir=system.ruby.dir_cntrl0.requestToDir -responseFromDir=system.ruby.dir_cntrl0.responseFromDir -responseFromMemory=system.ruby.dir_cntrl0.responseFromMemory -responseToDir=system.ruby.dir_cntrl0.responseToDir -ruby_system=system.ruby -system=system -to_memory_controller_latency=1 -transitions_per_cycle=4 -version=0 -memory=system.mem_ctrls.port - -[system.ruby.dir_cntrl0.directory] -type=RubyDirectoryMemory -eventq_index=0 -numa_high_bit=5 -size=268435456 -version=0 - -[system.ruby.dir_cntrl0.forwardFromDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[6] - -[system.ruby.dir_cntrl0.requestToDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[5] - -[system.ruby.dir_cntrl0.responseFromDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[5] - -[system.ruby.dir_cntrl0.responseFromMemory] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false - -[system.ruby.dir_cntrl0.responseToDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[6] - -[system.ruby.l1_cntrl0] -type=L1Cache_Controller -children=L1Dcache L1Icache mandatoryQueue requestFromL1Cache requestToL1Cache responseFromL1Cache responseToL1Cache sequencer triggerQueue -L1Dcache=system.ruby.l1_cntrl0.L1Dcache -L1Icache=system.ruby.l1_cntrl0.L1Icache -buffer_size=0 -clk_domain=system.cpu.clk_domain -cluster_id=0 -default_p_state=UNDEFINED -eventq_index=0 -l2_select_num_bits=0 -mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue -number_of_TBEs=256 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -recycle_latency=10 -requestFromL1Cache=system.ruby.l1_cntrl0.requestFromL1Cache -requestToL1Cache=system.ruby.l1_cntrl0.requestToL1Cache -request_latency=2 -responseFromL1Cache=system.ruby.l1_cntrl0.responseFromL1Cache -responseToL1Cache=system.ruby.l1_cntrl0.responseToL1Cache -ruby_system=system.ruby -send_evictions=false -sequencer=system.ruby.l1_cntrl0.sequencer -system=system -transitions_per_cycle=4 -triggerQueue=system.ruby.l1_cntrl0.triggerQueue -use_timeout_latency=50 -version=0 - -[system.ruby.l1_cntrl0.L1Dcache] -type=RubyCache -children=replacement_policy -assoc=2 -block_size=0 -dataAccessLatency=1 -dataArrayBanks=1 -eventq_index=0 -is_icache=false -replacement_policy=system.ruby.l1_cntrl0.L1Dcache.replacement_policy -resourceStalls=false -ruby_system=system.ruby -size=256 -start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 - -[system.ruby.l1_cntrl0.L1Dcache.replacement_policy] -type=PseudoLRUReplacementPolicy -assoc=2 -block_size=64 -eventq_index=0 -size=256 - -[system.ruby.l1_cntrl0.L1Icache] -type=RubyCache -children=replacement_policy -assoc=2 -block_size=0 -dataAccessLatency=1 -dataArrayBanks=1 -eventq_index=0 -is_icache=true -replacement_policy=system.ruby.l1_cntrl0.L1Icache.replacement_policy -resourceStalls=false -ruby_system=system.ruby -size=256 -start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 - -[system.ruby.l1_cntrl0.L1Icache.replacement_policy] -type=PseudoLRUReplacementPolicy -assoc=2 -block_size=64 -eventq_index=0 -size=256 - -[system.ruby.l1_cntrl0.mandatoryQueue] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false - -[system.ruby.l1_cntrl0.requestFromL1Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[0] - -[system.ruby.l1_cntrl0.requestToL1Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[0] - -[system.ruby.l1_cntrl0.responseFromL1Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[1] - -[system.ruby.l1_cntrl0.responseToL1Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[1] - -[system.ruby.l1_cntrl0.sequencer] -type=RubySequencer -clk_domain=system.cpu.clk_domain -coreid=99 -dcache=system.ruby.l1_cntrl0.L1Dcache -dcache_hit_latency=1 -deadlock_threshold=500000 -default_p_state=UNDEFINED -eventq_index=0 -garnet_standalone=false -icache=system.ruby.l1_cntrl0.L1Icache -icache_hit_latency=1 -is_cpu_sequencer=true -max_outstanding_requests=16 -no_retry_on_stall=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -ruby_system=system.ruby -support_data_reqs=true -support_inst_reqs=true -system=system -using_ruby_tester=false -version=0 -slave=system.cpu.icache_port system.cpu.dcache_port - -[system.ruby.l1_cntrl0.triggerQueue] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.l2_cntrl0] -type=L2Cache_Controller -children=GlobalRequestFromL2Cache GlobalRequestToL2Cache L1RequestFromL2Cache L1RequestToL2Cache L2cache responseFromL2Cache responseToL2Cache triggerQueue -GlobalRequestFromL2Cache=system.ruby.l2_cntrl0.GlobalRequestFromL2Cache -GlobalRequestToL2Cache=system.ruby.l2_cntrl0.GlobalRequestToL2Cache -L1RequestFromL2Cache=system.ruby.l2_cntrl0.L1RequestFromL2Cache -L1RequestToL2Cache=system.ruby.l2_cntrl0.L1RequestToL2Cache -L2cache=system.ruby.l2_cntrl0.L2cache -buffer_size=0 -clk_domain=system.ruby.clk_domain -cluster_id=0 -default_p_state=UNDEFINED -eventq_index=0 -number_of_TBEs=256 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -recycle_latency=10 -request_latency=2 -responseFromL2Cache=system.ruby.l2_cntrl0.responseFromL2Cache -responseToL2Cache=system.ruby.l2_cntrl0.responseToL2Cache -response_latency=2 -ruby_system=system.ruby -system=system -transitions_per_cycle=4 -triggerQueue=system.ruby.l2_cntrl0.triggerQueue -version=0 - -[system.ruby.l2_cntrl0.GlobalRequestFromL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[2] - -[system.ruby.l2_cntrl0.GlobalRequestToL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[2] - -[system.ruby.l2_cntrl0.L1RequestFromL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[3] - -[system.ruby.l2_cntrl0.L1RequestToL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[3] - -[system.ruby.l2_cntrl0.L2cache] -type=RubyCache -children=replacement_policy -assoc=2 -block_size=0 -dataAccessLatency=1 -dataArrayBanks=1 -eventq_index=0 -is_icache=false -replacement_policy=system.ruby.l2_cntrl0.L2cache.replacement_policy -resourceStalls=false -ruby_system=system.ruby -size=512 -start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 - -[system.ruby.l2_cntrl0.L2cache.replacement_policy] -type=PseudoLRUReplacementPolicy -assoc=2 -block_size=64 -eventq_index=0 -size=512 - -[system.ruby.l2_cntrl0.responseFromL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[4] - -[system.ruby.l2_cntrl0.responseToL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[4] - -[system.ruby.l2_cntrl0.triggerQueue] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.memctrl_clk_domain] -type=DerivedClockDomain -clk_divider=3 -clk_domain=system.ruby.clk_domain -eventq_index=0 - -[system.ruby.network] -type=SimpleNetwork -children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 routers0 routers1 routers2 routers3 -adaptive_routing=false -buffer_size=0 -clk_domain=system.ruby.clk_domain -control_msg_size=8 -default_p_state=UNDEFINED -endpoint_bandwidth=1000 -eventq_index=0 -ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2 -int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 -int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4 system.ruby.network.int_links5 -netifs= -number_of_virtual_networks=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 system.ruby.network.routers3 -ruby_system=system.ruby -topology=Crossbar -master=system.ruby.l1_cntrl0.requestToL1Cache.slave system.ruby.l1_cntrl0.responseToL1Cache.slave system.ruby.l2_cntrl0.GlobalRequestToL2Cache.slave system.ruby.l2_cntrl0.L1RequestToL2Cache.slave system.ruby.l2_cntrl0.responseToL2Cache.slave system.ruby.dir_cntrl0.requestToDir.slave system.ruby.dir_cntrl0.responseToDir.slave -slave=system.ruby.l1_cntrl0.requestFromL1Cache.master system.ruby.l1_cntrl0.responseFromL1Cache.master system.ruby.l2_cntrl0.GlobalRequestFromL2Cache.master system.ruby.l2_cntrl0.L1RequestFromL2Cache.master system.ruby.l2_cntrl0.responseFromL2Cache.master system.ruby.dir_cntrl0.responseFromDir.master system.ruby.dir_cntrl0.forwardFromDir.master - -[system.ruby.network.ext_links0] -type=SimpleExtLink -bandwidth_factor=16 -eventq_index=0 -ext_node=system.ruby.l1_cntrl0 -int_node=system.ruby.network.routers0 -latency=1 -link_id=0 -weight=1 - -[system.ruby.network.ext_links1] -type=SimpleExtLink -bandwidth_factor=16 -eventq_index=0 -ext_node=system.ruby.l2_cntrl0 -int_node=system.ruby.network.routers1 -latency=1 -link_id=1 -weight=1 - -[system.ruby.network.ext_links2] -type=SimpleExtLink -bandwidth_factor=16 -eventq_index=0 -ext_node=system.ruby.dir_cntrl0 -int_node=system.ruby.network.routers2 -latency=1 -link_id=2 -weight=1 - -[system.ruby.network.int_link_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers15] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers16] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers17] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers18] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers19] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers20] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers21] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers22] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers23] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers24] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers25] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers26] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers27] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - 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-[system.ruby.network.int_links4] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers1 -eventq_index=0 -latency=1 -link_id=7 -src_node=system.ruby.network.routers3 -src_outport= -weight=1 - -[system.ruby.network.int_links5] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers2 -eventq_index=0 -latency=1 -link_id=8 -src_node=system.ruby.network.routers3 -src_outport= -weight=1 - -[system.ruby.network.routers0] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 -power_model=Null -router_id=0 -virt_nets=3 - -[system.ruby.network.routers0.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 -power_model=Null -router_id=1 -virt_nets=3 - -[system.ruby.network.routers1.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 -power_model=Null -router_id=2 -virt_nets=3 - -[system.ruby.network.routers2.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers3.port_buffers00 system.ruby.network.routers3.port_buffers01 system.ruby.network.routers3.port_buffers02 system.ruby.network.routers3.port_buffers03 system.ruby.network.routers3.port_buffers04 system.ruby.network.routers3.port_buffers05 system.ruby.network.routers3.port_buffers06 system.ruby.network.routers3.port_buffers07 system.ruby.network.routers3.port_buffers08 system.ruby.network.routers3.port_buffers09 system.ruby.network.routers3.port_buffers10 system.ruby.network.routers3.port_buffers11 system.ruby.network.routers3.port_buffers12 system.ruby.network.routers3.port_buffers13 system.ruby.network.routers3.port_buffers14 system.ruby.network.routers3.port_buffers15 system.ruby.network.routers3.port_buffers16 system.ruby.network.routers3.port_buffers17 -power_model=Null -router_id=3 -virt_nets=3 - -[system.ruby.network.routers3.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers15] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers16] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers17] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.sys_port_proxy] -type=RubyPortProxy -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_cpu_sequencer=true -no_retry_on_stall=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -ruby_system=system.ruby -support_data_reqs=true -support_inst_reqs=true -system=system -using_ruby_tester=false -version=0 -slave=system.system_port - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,11 +0,0 @@ -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! -warn: ignoring syscall sigprocmask(1, ...) diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,15 +0,0 @@ -Redirecting stdout to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout -Redirecting stderr to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 13 2016 20:30:58 -gem5 started Oct 13 2016 20:31:25 -gem5 executing on e108600-lin, pid 17791 -command line: /work/curdun01/gem5-external.hg/build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory - -Global frequency set at 1000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Hello world! -Exiting @ tick 44230 because target called exit() diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,752 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000044 # Number of seconds simulated -sim_ticks 44230 # Number of ticks simulated -final_tick 44230 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 73967 # Simulator instruction rate (inst/s) -host_op_rate 73941 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1268663 # Simulator tick rate (ticks/s) -host_mem_usage 415828 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host -sim_insts 2577 # Number of instructions simulated -sim_ops 2577 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 29696 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 29696 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 4992 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 4992 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 464 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 464 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 78 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 78 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 671399503 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 671399503 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 112864572 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 112864572 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 784264074 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 784264074 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 464 # Number of read requests accepted -system.mem_ctrls.writeReqs 78 # Number of write requests accepted -system.mem_ctrls.readBursts 464 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 78 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 24576 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 5120 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 1024 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 29696 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 4992 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 80 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 32 # Number of DRAM write bursts merged with an existing one -system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 1 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 1 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 36 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 26 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 24 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 69 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 71 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::9 4 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 30 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 16 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 29 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 66 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 10 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 1 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 3 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 5 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 7 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::15 1 # Per bank write bursts -system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 44144 # Total gap between requests -system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 464 # Read request sizes (log2) -system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 78 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 384 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 75 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 308.906667 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 203.362375 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 281.413861 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 21 28.00% 28.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 20 26.67% 54.67% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 8 10.67% 65.33% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 8 10.67% 76.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 6 8.00% 84.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 3 4.00% 88.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 4 5.33% 93.33% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 1 1.33% 94.67% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 4 5.33% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 75 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 1 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 248 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 248.000000 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev nan # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::248-255 1 100.00% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 1 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 1 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev nan # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 1 100.00% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 1 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 4911 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 12207 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 1920 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 12.79 # Average queueing delay per DRAM burst -system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 31.79 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 555.64 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 23.15 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 671.40 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 112.86 # Average system write bandwidth in MiByte/s -system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 4.52 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 4.34 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 0.18 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 21.61 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 302 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 15 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 78.65 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 32.61 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 81.45 # Average gap between requests -system.mem_ctrls.pageHitRate 73.72 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 178500 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 81144 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 1793568 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 3073200.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 2736456 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 72192 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.actPowerDownEnergy 16199400 # Energy for active power-down per rank (pJ) -system.mem_ctrls_0.prePowerDownEnergy 966144 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrls_0.totalEnergy 25100604 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 567.501786 # Core power per rank (mW) -system.mem_ctrls_0.totalIdleTime 37998 # Total Idle time Per DRAM Rank -system.mem_ctrls_0.memoryStateTime::IDLE 48 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 1300 # Time in different power states -system.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::PRE_PDN 2516 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 4841 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 35525 # Time in different power states -system.mem_ctrls_1.actEnergy 414120 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 208656 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 2593248 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 133632 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 3073200.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 3830856 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 258048 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.actPowerDownEnergy 15964560 # Energy for active power-down per rank (pJ) -system.mem_ctrls_1.prePowerDownEnergy 56448 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrls_1.totalEnergy 26532768 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 599.881709 # Core power per rank (mW) -system.mem_ctrls_1.totalIdleTime 34371 # Total Idle time Per DRAM Rank -system.mem_ctrls_1.memoryStateTime::IDLE 532 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 1300 # Time in different power states -system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 147 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 7241 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT_PDN 35010 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states -system.cpu.clk_domain.clock 1 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 415 # DTB read hits -system.cpu.dtb.read_misses 4 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 419 # DTB read accesses -system.cpu.dtb.write_hits 294 # DTB write hits -system.cpu.dtb.write_misses 4 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 298 # DTB write accesses -system.cpu.dtb.data_hits 709 # DTB hits -system.cpu.dtb.data_misses 8 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 717 # DTB accesses -system.cpu.itb.fetch_hits 2586 # ITB hits -system.cpu.itb.fetch_misses 11 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2597 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 44230 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 44230 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 2577 # Number of instructions committed -system.cpu.committedOps 2577 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses -system.cpu.num_func_calls 140 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls -system.cpu.num_int_insts 2375 # number of integer instructions -system.cpu.num_fp_insts 6 # number of float instructions -system.cpu.num_int_register_reads 2998 # number of times the integer registers were read -system.cpu.num_int_register_writes 1768 # number of times the integer registers were written -system.cpu.num_fp_register_reads 6 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 717 # number of memory refs -system.cpu.num_load_insts 419 # Number of load instructions -system.cpu.num_store_insts 298 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 44230 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 396 # Number of branches fetched -system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction -system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction -system.cpu.op_class::MemWrite 292 11.30% 99.77% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 99.77% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 6 0.23% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 2585 # Class of executed instruction -system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states -system.ruby.outstanding_req_hist_seqr::bucket_size 1 -system.ruby.outstanding_req_hist_seqr::max_bucket 9 -system.ruby.outstanding_req_hist_seqr::samples 3295 -system.ruby.outstanding_req_hist_seqr::mean 1 -system.ruby.outstanding_req_hist_seqr::gmean 1 -system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 3295 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist_seqr::total 3295 -system.ruby.latency_hist_seqr::bucket_size 64 -system.ruby.latency_hist_seqr::max_bucket 639 -system.ruby.latency_hist_seqr::samples 3294 -system.ruby.latency_hist_seqr::mean 12.427444 -system.ruby.latency_hist_seqr::gmean 1.971908 -system.ruby.latency_hist_seqr::stdev 29.452789 -system.ruby.latency_hist_seqr | 2910 88.34% 88.34% | 377 11.45% 99.79% | 2 0.06% 99.85% | 0 0.00% 99.85% | 3 0.09% 99.94% | 2 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist_seqr::total 3294 -system.ruby.hit_latency_hist_seqr::bucket_size 1 -system.ruby.hit_latency_hist_seqr::max_bucket 9 -system.ruby.hit_latency_hist_seqr::samples 2750 -system.ruby.hit_latency_hist_seqr::mean 1 -system.ruby.hit_latency_hist_seqr::gmean 1 -system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 2750 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist_seqr::total 2750 -system.ruby.miss_latency_hist_seqr::bucket_size 64 -system.ruby.miss_latency_hist_seqr::max_bucket 639 -system.ruby.miss_latency_hist_seqr::samples 544 -system.ruby.miss_latency_hist_seqr::mean 70.194853 -system.ruby.miss_latency_hist_seqr::gmean 61.035379 -system.ruby.miss_latency_hist_seqr::stdev 35.442152 -system.ruby.miss_latency_hist_seqr | 160 29.41% 29.41% | 377 69.30% 98.71% | 2 0.37% 99.08% | 0 0.00% 99.08% | 3 0.55% 99.63% | 2 0.37% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist_seqr::total 544 -system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.L1Dcache.demand_hits 435 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 274 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Icache.demand_hits 2315 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Icache.demand_misses 270 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Icache.demand_accesses 2585 # Number of cache demand accesses -system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states -system.ruby.l2_cntrl0.L2cache.demand_hits 80 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 464 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 544 # Number of cache demand accesses -system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.percent_links_utilized 6.413068 -system.ruby.network.routers0.msg_count.Request_Control::0 544 -system.ruby.network.routers0.msg_count.Response_Data::2 464 -system.ruby.network.routers0.msg_count.ResponseL2hit_Data::2 80 -system.ruby.network.routers0.msg_count.Writeback_Data::2 482 -system.ruby.network.routers0.msg_count.Writeback_Control::0 1004 -system.ruby.network.routers0.msg_count.Unblock_Control::2 564 -system.ruby.network.routers0.msg_bytes.Request_Control::0 4352 -system.ruby.network.routers0.msg_bytes.Response_Data::2 33408 -system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2 5760 -system.ruby.network.routers0.msg_bytes.Writeback_Data::2 34704 -system.ruby.network.routers0.msg_bytes.Writeback_Control::0 8032 -system.ruby.network.routers0.msg_bytes.Unblock_Control::2 4512 -system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states -system.ruby.network.routers1.percent_links_utilized 9.782388 -system.ruby.network.routers1.msg_count.Request_Control::0 544 -system.ruby.network.routers1.msg_count.Request_Control::1 464 -system.ruby.network.routers1.msg_count.Response_Data::2 928 -system.ruby.network.routers1.msg_count.ResponseL2hit_Data::2 80 -system.ruby.network.routers1.msg_count.Writeback_Data::2 560 -system.ruby.network.routers1.msg_count.Writeback_Control::0 1004 -system.ruby.network.routers1.msg_count.Writeback_Control::1 156 -system.ruby.network.routers1.msg_count.Unblock_Control::2 1027 -system.ruby.network.routers1.msg_bytes.Request_Control::0 4352 -system.ruby.network.routers1.msg_bytes.Request_Control::1 3712 -system.ruby.network.routers1.msg_bytes.Response_Data::2 66816 -system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::2 5760 -system.ruby.network.routers1.msg_bytes.Writeback_Data::2 40320 -system.ruby.network.routers1.msg_bytes.Writeback_Control::0 8032 -system.ruby.network.routers1.msg_bytes.Writeback_Control::1 1248 -system.ruby.network.routers1.msg_bytes.Unblock_Control::2 8216 -system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states -system.ruby.network.routers2.percent_links_utilized 3.369319 -system.ruby.network.routers2.msg_count.Request_Control::1 464 -system.ruby.network.routers2.msg_count.Response_Data::2 464 -system.ruby.network.routers2.msg_count.Writeback_Data::2 78 -system.ruby.network.routers2.msg_count.Writeback_Control::1 156 -system.ruby.network.routers2.msg_count.Unblock_Control::2 463 -system.ruby.network.routers2.msg_bytes.Request_Control::1 3712 -system.ruby.network.routers2.msg_bytes.Response_Data::2 33408 -system.ruby.network.routers2.msg_bytes.Writeback_Data::2 5616 -system.ruby.network.routers2.msg_bytes.Writeback_Control::1 1248 -system.ruby.network.routers2.msg_bytes.Unblock_Control::2 3704 -system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states -system.ruby.network.routers3.percent_links_utilized 6.521592 -system.ruby.network.routers3.msg_count.Request_Control::0 544 -system.ruby.network.routers3.msg_count.Request_Control::1 464 -system.ruby.network.routers3.msg_count.Response_Data::2 928 -system.ruby.network.routers3.msg_count.ResponseL2hit_Data::2 80 -system.ruby.network.routers3.msg_count.Writeback_Data::2 560 -system.ruby.network.routers3.msg_count.Writeback_Control::0 1004 -system.ruby.network.routers3.msg_count.Writeback_Control::1 156 -system.ruby.network.routers3.msg_count.Unblock_Control::2 1027 -system.ruby.network.routers3.msg_bytes.Request_Control::0 4352 -system.ruby.network.routers3.msg_bytes.Request_Control::1 3712 -system.ruby.network.routers3.msg_bytes.Response_Data::2 66816 -system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::2 5760 -system.ruby.network.routers3.msg_bytes.Writeback_Data::2 40320 -system.ruby.network.routers3.msg_bytes.Writeback_Control::0 8032 -system.ruby.network.routers3.msg_bytes.Writeback_Control::1 1248 -system.ruby.network.routers3.msg_bytes.Unblock_Control::2 8216 -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states -system.ruby.network.msg_count.Request_Control 3024 -system.ruby.network.msg_count.Response_Data 2784 -system.ruby.network.msg_count.ResponseL2hit_Data 240 -system.ruby.network.msg_count.Writeback_Data 1680 -system.ruby.network.msg_count.Writeback_Control 3480 -system.ruby.network.msg_count.Unblock_Control 3081 -system.ruby.network.msg_byte.Request_Control 24192 -system.ruby.network.msg_byte.Response_Data 200448 -system.ruby.network.msg_byte.ResponseL2hit_Data 17280 -system.ruby.network.msg_byte.Writeback_Data 120960 -system.ruby.network.msg_byte.Writeback_Control 27840 -system.ruby.network.msg_byte.Unblock_Control 24648 -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.throttle0.link_utilization 6.102193 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 464 -system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2 80 -system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::0 502 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::2 33408 -system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::2 5760 -system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::0 4016 -system.ruby.network.routers0.throttle1.link_utilization 6.723943 -system.ruby.network.routers0.throttle1.msg_count.Request_Control::0 544 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::2 482 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 502 -system.ruby.network.routers0.throttle1.msg_count.Unblock_Control::2 564 -system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::0 4352 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::2 34704 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 4016 -system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::2 4512 -system.ruby.network.routers1.throttle0.link_utilization 11.532896 -system.ruby.network.routers1.throttle0.msg_count.Request_Control::0 544 -system.ruby.network.routers1.throttle0.msg_count.Response_Data::2 464 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::2 482 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0 502 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::1 78 -system.ruby.network.routers1.throttle0.msg_count.Unblock_Control::2 564 -system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::0 4352 -system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::2 33408 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::2 34704 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 4016 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::1 624 -system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::2 4512 -system.ruby.network.routers1.throttle1.link_utilization 8.031879 -system.ruby.network.routers1.throttle1.msg_count.Request_Control::1 464 -system.ruby.network.routers1.throttle1.msg_count.Response_Data::2 464 -system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::2 80 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::2 78 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::0 502 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::1 78 -system.ruby.network.routers1.throttle1.msg_count.Unblock_Control::2 463 -system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::1 3712 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::2 33408 -system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::2 5760 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::2 5616 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::0 4016 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::1 624 -system.ruby.network.routers1.throttle1.msg_bytes.Unblock_Control::2 3704 -system.ruby.network.routers2.throttle0.link_utilization 1.929686 -system.ruby.network.routers2.throttle0.msg_count.Request_Control::1 464 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::2 78 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::1 78 -system.ruby.network.routers2.throttle0.msg_count.Unblock_Control::2 463 -system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::1 3712 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::2 5616 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::1 624 -system.ruby.network.routers2.throttle0.msg_bytes.Unblock_Control::2 3704 -system.ruby.network.routers2.throttle1.link_utilization 4.808953 -system.ruby.network.routers2.throttle1.msg_count.Response_Data::2 464 -system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::1 78 -system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::2 33408 -system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::1 624 -system.ruby.network.routers3.throttle0.link_utilization 6.102193 -system.ruby.network.routers3.throttle0.msg_count.Response_Data::2 464 -system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::2 80 -system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::0 502 -system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::2 33408 -system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::2 5760 -system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::0 4016 -system.ruby.network.routers3.throttle1.link_utilization 11.532896 -system.ruby.network.routers3.throttle1.msg_count.Request_Control::0 544 -system.ruby.network.routers3.throttle1.msg_count.Response_Data::2 464 -system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::2 482 -system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::0 502 -system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::1 78 -system.ruby.network.routers3.throttle1.msg_count.Unblock_Control::2 564 -system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::0 4352 -system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::2 33408 -system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::2 34704 -system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 4016 -system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::1 624 -system.ruby.network.routers3.throttle1.msg_bytes.Unblock_Control::2 4512 -system.ruby.network.routers3.throttle2.link_utilization 1.929686 -system.ruby.network.routers3.throttle2.msg_count.Request_Control::1 464 -system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::2 78 -system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::1 78 -system.ruby.network.routers3.throttle2.msg_count.Unblock_Control::2 463 -system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::1 3712 -system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::2 5616 -system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::1 624 -system.ruby.network.routers3.throttle2.msg_bytes.Unblock_Control::2 3704 -system.ruby.LD.latency_hist_seqr::bucket_size 64 -system.ruby.LD.latency_hist_seqr::max_bucket 639 -system.ruby.LD.latency_hist_seqr::samples 415 -system.ruby.LD.latency_hist_seqr::mean 27.790361 -system.ruby.LD.latency_hist_seqr::gmean 5.600782 -system.ruby.LD.latency_hist_seqr::stdev 40.269706 -system.ruby.LD.latency_hist_seqr | 320 77.11% 77.11% | 92 22.17% 99.28% | 1 0.24% 99.52% | 0 0.00% 99.52% | 1 0.24% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist_seqr::total 415 -system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 -system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 -system.ruby.LD.hit_latency_hist_seqr::samples 233 -system.ruby.LD.hit_latency_hist_seqr::mean 1 -system.ruby.LD.hit_latency_hist_seqr::gmean 1 -system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 233 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist_seqr::total 233 -system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 -system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 -system.ruby.LD.miss_latency_hist_seqr::samples 182 -system.ruby.LD.miss_latency_hist_seqr::mean 62.087912 -system.ruby.LD.miss_latency_hist_seqr::gmean 50.836003 -system.ruby.LD.miss_latency_hist_seqr::stdev 40.030554 -system.ruby.LD.miss_latency_hist_seqr | 87 47.80% 47.80% | 92 50.55% 98.35% | 1 0.55% 98.90% | 0 0.00% 98.90% | 1 0.55% 99.45% | 1 0.55% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist_seqr::total 182 -system.ruby.ST.latency_hist_seqr::bucket_size 16 -system.ruby.ST.latency_hist_seqr::max_bucket 159 -system.ruby.ST.latency_hist_seqr::samples 294 -system.ruby.ST.latency_hist_seqr::mean 19.755102 -system.ruby.ST.latency_hist_seqr::gmean 3.497030 -system.ruby.ST.latency_hist_seqr::stdev 31.010753 -system.ruby.ST.latency_hist_seqr | 202 68.71% 68.71% | 12 4.08% 72.79% | 34 11.56% 84.35% | 1 0.34% 84.69% | 0 0.00% 84.69% | 44 14.97% 99.66% | 1 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist_seqr::total 294 -system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 -system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 -system.ruby.ST.hit_latency_hist_seqr::samples 202 -system.ruby.ST.hit_latency_hist_seqr::mean 1 -system.ruby.ST.hit_latency_hist_seqr::gmean 1 -system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 202 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist_seqr::total 202 -system.ruby.ST.miss_latency_hist_seqr::bucket_size 16 -system.ruby.ST.miss_latency_hist_seqr::max_bucket 159 -system.ruby.ST.miss_latency_hist_seqr::samples 92 -system.ruby.ST.miss_latency_hist_seqr::mean 60.934783 -system.ruby.ST.miss_latency_hist_seqr::gmean 54.635401 -system.ruby.ST.miss_latency_hist_seqr::stdev 24.518127 -system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 12 13.04% 13.04% | 34 36.96% 50.00% | 1 1.09% 51.09% | 0 0.00% 51.09% | 44 47.83% 98.91% | 1 1.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist_seqr::total 92 -system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 -system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.latency_hist_seqr::samples 2585 -system.ruby.IFETCH.latency_hist_seqr::mean 9.127660 -system.ruby.IFETCH.latency_hist_seqr::gmean 1.562445 -system.ruby.IFETCH.latency_hist_seqr::stdev 26.109704 -system.ruby.IFETCH.latency_hist_seqr | 2341 90.56% 90.56% | 240 9.28% 99.85% | 1 0.04% 99.88% | 0 0.00% 99.88% | 2 0.08% 99.96% | 1 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist_seqr::total 2585 -system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 -system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 -system.ruby.IFETCH.hit_latency_hist_seqr::samples 2315 -system.ruby.IFETCH.hit_latency_hist_seqr::mean 1 -system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 -system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 2315 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist_seqr::total 2315 -system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 -system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.miss_latency_hist_seqr::samples 270 -system.ruby.IFETCH.miss_latency_hist_seqr::mean 78.814815 -system.ruby.IFETCH.miss_latency_hist_seqr::gmean 71.697206 -system.ruby.IFETCH.miss_latency_hist_seqr::stdev 33.251813 -system.ruby.IFETCH.miss_latency_hist_seqr | 26 9.63% 9.63% | 240 88.89% 98.52% | 1 0.37% 98.89% | 0 0.00% 98.89% | 2 0.74% 99.63% | 1 0.37% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.miss_latency_hist_seqr::total 270 -system.ruby.Directory_Controller.GETX 80 0.00% 0.00% -system.ruby.Directory_Controller.GETS 384 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 78 0.00% 0.00% -system.ruby.Directory_Controller.Unblock 262 0.00% 0.00% -system.ruby.Directory_Controller.Last_Unblock 121 0.00% 0.00% -system.ruby.Directory_Controller.Exclusive_Unblock 80 0.00% 0.00% -system.ruby.Directory_Controller.Dirty_Writeback 78 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 464 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 78 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 40 0.00% 0.00% -system.ruby.Directory_Controller.I.GETS 262 0.00% 0.00% -system.ruby.Directory_Controller.I.Memory_Ack 77 0.00% 0.00% -system.ruby.Directory_Controller.S.GETX 40 0.00% 0.00% -system.ruby.Directory_Controller.S.GETS 122 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 78 0.00% 0.00% -system.ruby.Directory_Controller.IS.Unblock 262 0.00% 0.00% -system.ruby.Directory_Controller.IS.Memory_Data 262 0.00% 0.00% -system.ruby.Directory_Controller.SS.Last_Unblock 121 0.00% 0.00% -system.ruby.Directory_Controller.SS.Memory_Data 122 0.00% 0.00% -system.ruby.Directory_Controller.MM.Exclusive_Unblock 80 0.00% 0.00% -system.ruby.Directory_Controller.MM.Memory_Data 80 0.00% 0.00% -system.ruby.Directory_Controller.MM.Memory_Ack 1 0.00% 0.00% -system.ruby.Directory_Controller.MI.Dirty_Writeback 78 0.00% 0.00% -system.ruby.L1Cache_Controller.Load 415 0.00% 0.00% -system.ruby.L1Cache_Controller.Ifetch 2585 0.00% 0.00% -system.ruby.L1Cache_Controller.Store 294 0.00% 0.00% -system.ruby.L1Cache_Controller.L1_Replacement 508 0.00% 0.00% -system.ruby.L1Cache_Controller.Data 436 0.00% 0.00% -system.ruby.L1Cache_Controller.Exclusive_Data 108 0.00% 0.00% -system.ruby.L1Cache_Controller.Writeback_Ack 20 0.00% 0.00% -system.ruby.L1Cache_Controller.Writeback_Ack_Data 482 0.00% 0.00% -system.ruby.L1Cache_Controller.All_acks 92 0.00% 0.00% -system.ruby.L1Cache_Controller.Use_Timeout 108 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Load 182 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Ifetch 270 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Store 58 0.00% 0.00% -system.ruby.L1Cache_Controller.S.Load 108 0.00% 0.00% -system.ruby.L1Cache_Controller.S.Ifetch 2315 0.00% 0.00% -system.ruby.L1Cache_Controller.S.Store 34 0.00% 0.00% -system.ruby.L1Cache_Controller.S.L1_Replacement 396 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Load 9 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Store 4 0.00% 0.00% -system.ruby.L1Cache_Controller.M.L1_Replacement 10 0.00% 0.00% -system.ruby.L1Cache_Controller.M_W.Load 14 0.00% 0.00% -system.ruby.L1Cache_Controller.M_W.Store 2 0.00% 0.00% -system.ruby.L1Cache_Controller.M_W.Use_Timeout 14 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.Load 89 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.Store 84 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.L1_Replacement 96 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_W.Load 13 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_W.Store 112 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_W.L1_Replacement 6 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_W.Use_Timeout 94 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.Exclusive_Data 58 0.00% 0.00% -system.ruby.L1Cache_Controller.SM.Exclusive_Data 34 0.00% 0.00% -system.ruby.L1Cache_Controller.OM.All_acks 92 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Data 436 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Exclusive_Data 16 0.00% 0.00% -system.ruby.L1Cache_Controller.SI.Writeback_Ack 20 0.00% 0.00% -system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data 376 0.00% 0.00% -system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data 106 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETS 452 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETX 93 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTX 106 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTS_only 396 0.00% 0.00% -system.ruby.L2Cache_Controller.All_Acks 80 0.00% 0.00% -system.ruby.L2Cache_Controller.Data 464 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_WBCLEANDATA 376 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_WBDIRTYDATA 106 0.00% 0.00% -system.ruby.L2Cache_Controller.Writeback_Ack 78 0.00% 0.00% -system.ruby.L2Cache_Controller.Unblock 455 0.00% 0.00% -system.ruby.L2Cache_Controller.Exclusive_Unblock 108 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement 443 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETS 384 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETX 45 0.00% 0.00% -system.ruby.L2Cache_Controller.ILS.L1_GETX 32 0.00% 0.00% -system.ruby.L2Cache_Controller.ILS.L1_PUTS_only 376 0.00% 0.00% -system.ruby.L2Cache_Controller.ILX.L1_PUTX 106 0.00% 0.00% -system.ruby.L2Cache_Controller.S.L1_GETS 52 0.00% 0.00% -system.ruby.L2Cache_Controller.S.L1_GETX 1 0.00% 0.00% -system.ruby.L2Cache_Controller.S.L2_Replacement 335 0.00% 0.00% -system.ruby.L2Cache_Controller.SLS.L1_GETX 2 0.00% 0.00% -system.ruby.L2Cache_Controller.SLS.L1_PUTS_only 20 0.00% 0.00% -system.ruby.L2Cache_Controller.SLS.L2_Replacement 30 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETS 16 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETX 12 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement 78 0.00% 0.00% -system.ruby.L2Cache_Controller.IW.L1_WBCLEANDATA 376 0.00% 0.00% -system.ruby.L2Cache_Controller.SW.Unblock 20 0.00% 0.00% -system.ruby.L2Cache_Controller.ILXW.L1_WBDIRTYDATA 106 0.00% 0.00% -system.ruby.L2Cache_Controller.IGS.Data 384 0.00% 0.00% -system.ruby.L2Cache_Controller.IGS.Unblock 383 0.00% 0.00% -system.ruby.L2Cache_Controller.IGM.Data 46 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMLS.Data 34 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMO.All_Acks 80 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMO.Exclusive_Unblock 80 0.00% 0.00% -system.ruby.L2Cache_Controller.MM.Exclusive_Unblock 12 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.Unblock 52 0.00% 0.00% -system.ruby.L2Cache_Controller.OO.Exclusive_Unblock 16 0.00% 0.00% -system.ruby.L2Cache_Controller.MI.L1_GETX 1 0.00% 0.00% -system.ruby.L2Cache_Controller.MI.Writeback_Ack 78 0.00% 0.00% - ----------- End Simulation Statistics ---------- diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,2138 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000 -time_sync_spin_threshold=100000 - -[system] -type=System -children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges=0:268435455:0:0:0:0 -memories=system.mem_ctrls -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.sys_port_proxy.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=TimingSimpleCPU -children=clk_domain dtb interrupts isa itb tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu.clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1] -icache_port=system.ruby.l1_cntrl0.sequencer.slave[0] - -[system.cpu.clk_domain] -type=SrcClockDomain -clock=1 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=hello -cwd= -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/tru64/hello -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000 - -[system.mem_ctrls] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -page_policy=open_adaptive -power_model=Null -range=0:268435455:5:19:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10 -static_frontend_latency=10 -tBURST=5 -tCCD_L=0 -tCK=1 -tCL=14 -tCS=3 -tRAS=35 -tRCD=14 -tREFI=7800 -tRFC=260 -tRP=14 -tRRD=6 -tRRD_L=0 -tRTP=8 -tRTW=3 -tWR=15 -tWTR=8 -tXAW=30 -tXP=6 -tXPDLL=0 -tXS=270 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.ruby.dir_cntrl0.memory - -[system.ruby] -type=RubySystem -children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network -access_backing_store=false -all_instructions=false -block_size_bytes=64 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hot_lines=false -memory_size_bits=48 -num_of_sequencers=1 -number_of_virtual_networks=6 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -phys_mem=Null -power_model=Null -randomization=false - -[system.ruby.clk_domain] -type=SrcClockDomain -clock=1 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.ruby.dir_cntrl0] -type=Directory_Controller -children=directory dmaRequestToDir dmaResponseFromDir persistentFromDir persistentToDir requestFromDir requestToDir responseFromDir responseFromMemory responseToDir -buffer_size=0 -clk_domain=system.ruby.clk_domain -cluster_id=0 -default_p_state=UNDEFINED -directory=system.ruby.dir_cntrl0.directory -directory_latency=5 -distributed_persistent=true -dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir -dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir -eventq_index=0 -fixed_timeout_latency=100 -l2_select_num_bits=0 -number_of_TBEs=256 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -persistentFromDir=system.ruby.dir_cntrl0.persistentFromDir -persistentToDir=system.ruby.dir_cntrl0.persistentToDir -power_model=Null -recycle_latency=10 -reissue_wakeup_latency=10 -requestFromDir=system.ruby.dir_cntrl0.requestFromDir -requestToDir=system.ruby.dir_cntrl0.requestToDir -responseFromDir=system.ruby.dir_cntrl0.responseFromDir -responseFromMemory=system.ruby.dir_cntrl0.responseFromMemory -responseToDir=system.ruby.dir_cntrl0.responseToDir -ruby_system=system.ruby -system=system -to_memory_controller_latency=1 -transitions_per_cycle=4 -version=0 -memory=system.mem_ctrls.port - -[system.ruby.dir_cntrl0.directory] -type=RubyDirectoryMemory -eventq_index=0 -numa_high_bit=5 -size=268435456 -version=0 - -[system.ruby.dir_cntrl0.dmaRequestToDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -slave=system.ruby.network.master[10] - -[system.ruby.dir_cntrl0.dmaResponseFromDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -master=system.ruby.network.slave[9] - -[system.ruby.dir_cntrl0.persistentFromDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -master=system.ruby.network.slave[8] - -[system.ruby.dir_cntrl0.persistentToDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -slave=system.ruby.network.master[9] - -[system.ruby.dir_cntrl0.requestFromDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[6] - -[system.ruby.dir_cntrl0.requestToDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[7] - -[system.ruby.dir_cntrl0.responseFromDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[7] - -[system.ruby.dir_cntrl0.responseFromMemory] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false - -[system.ruby.dir_cntrl0.responseToDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[8] - -[system.ruby.l1_cntrl0] -type=L1Cache_Controller -children=L1Dcache L1Icache mandatoryQueue persistentFromL1Cache persistentToL1Cache requestFromL1Cache requestToL1Cache responseFromL1Cache responseToL1Cache sequencer -L1Dcache=system.ruby.l1_cntrl0.L1Dcache -L1Icache=system.ruby.l1_cntrl0.L1Icache -N_tokens=2 -buffer_size=0 -clk_domain=system.cpu.clk_domain -cluster_id=0 -default_p_state=UNDEFINED -dynamic_timeout_enabled=true -eventq_index=0 -fixed_timeout_latency=300 -l1_request_latency=2 -l1_response_latency=2 -l2_select_num_bits=0 -mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue -no_mig_atomic=true -number_of_TBEs=256 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -persistentFromL1Cache=system.ruby.l1_cntrl0.persistentFromL1Cache -persistentToL1Cache=system.ruby.l1_cntrl0.persistentToL1Cache -power_model=Null -recycle_latency=10 -reissue_wakeup_latency=10 -requestFromL1Cache=system.ruby.l1_cntrl0.requestFromL1Cache -requestToL1Cache=system.ruby.l1_cntrl0.requestToL1Cache -responseFromL1Cache=system.ruby.l1_cntrl0.responseFromL1Cache -responseToL1Cache=system.ruby.l1_cntrl0.responseToL1Cache -retry_threshold=1 -ruby_system=system.ruby -send_evictions=false -sequencer=system.ruby.l1_cntrl0.sequencer -system=system -transitions_per_cycle=4 -use_timeout_latency=50 -version=0 - -[system.ruby.l1_cntrl0.L1Dcache] -type=RubyCache -children=replacement_policy -assoc=2 -block_size=0 -dataAccessLatency=1 -dataArrayBanks=1 -eventq_index=0 -is_icache=false -replacement_policy=system.ruby.l1_cntrl0.L1Dcache.replacement_policy -resourceStalls=false -ruby_system=system.ruby -size=256 -start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 - -[system.ruby.l1_cntrl0.L1Dcache.replacement_policy] -type=PseudoLRUReplacementPolicy -assoc=2 -block_size=64 -eventq_index=0 -size=256 - -[system.ruby.l1_cntrl0.L1Icache] -type=RubyCache -children=replacement_policy -assoc=2 -block_size=0 -dataAccessLatency=1 -dataArrayBanks=1 -eventq_index=0 -is_icache=false -replacement_policy=system.ruby.l1_cntrl0.L1Icache.replacement_policy -resourceStalls=false -ruby_system=system.ruby -size=256 -start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 - -[system.ruby.l1_cntrl0.L1Icache.replacement_policy] -type=PseudoLRUReplacementPolicy -assoc=2 -block_size=64 -eventq_index=0 -size=256 - -[system.ruby.l1_cntrl0.mandatoryQueue] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false - -[system.ruby.l1_cntrl0.persistentFromL1Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -master=system.ruby.network.slave[2] - -[system.ruby.l1_cntrl0.persistentToL1Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -slave=system.ruby.network.master[2] - -[system.ruby.l1_cntrl0.requestFromL1Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[0] - -[system.ruby.l1_cntrl0.requestToL1Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[0] - -[system.ruby.l1_cntrl0.responseFromL1Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[1] - -[system.ruby.l1_cntrl0.responseToL1Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[1] - -[system.ruby.l1_cntrl0.sequencer] -type=RubySequencer -clk_domain=system.cpu.clk_domain -coreid=99 -dcache=system.ruby.l1_cntrl0.L1Dcache -dcache_hit_latency=1 -deadlock_threshold=500000 -default_p_state=UNDEFINED -eventq_index=0 -garnet_standalone=false -icache=system.ruby.l1_cntrl0.L1Icache -icache_hit_latency=1 -is_cpu_sequencer=true -max_outstanding_requests=16 -no_retry_on_stall=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -ruby_system=system.ruby -support_data_reqs=true -support_inst_reqs=true -system=system -using_ruby_tester=false -version=0 -slave=system.cpu.icache_port system.cpu.dcache_port - -[system.ruby.l2_cntrl0] -type=L2Cache_Controller -children=GlobalRequestFromL2Cache GlobalRequestToL2Cache L1RequestFromL2Cache L1RequestToL2Cache L2cache persistentToL2Cache responseFromL2Cache responseToL2Cache -GlobalRequestFromL2Cache=system.ruby.l2_cntrl0.GlobalRequestFromL2Cache -GlobalRequestToL2Cache=system.ruby.l2_cntrl0.GlobalRequestToL2Cache -L1RequestFromL2Cache=system.ruby.l2_cntrl0.L1RequestFromL2Cache -L1RequestToL2Cache=system.ruby.l2_cntrl0.L1RequestToL2Cache -L2cache=system.ruby.l2_cntrl0.L2cache -N_tokens=2 -buffer_size=0 -clk_domain=system.ruby.clk_domain -cluster_id=0 -default_p_state=UNDEFINED -eventq_index=0 -filtering_enabled=true -l2_request_latency=5 -l2_response_latency=5 -number_of_TBEs=256 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -persistentToL2Cache=system.ruby.l2_cntrl0.persistentToL2Cache -power_model=Null -recycle_latency=10 -responseFromL2Cache=system.ruby.l2_cntrl0.responseFromL2Cache -responseToL2Cache=system.ruby.l2_cntrl0.responseToL2Cache -ruby_system=system.ruby -system=system -transitions_per_cycle=4 -version=0 - -[system.ruby.l2_cntrl0.GlobalRequestFromL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[3] - -[system.ruby.l2_cntrl0.GlobalRequestToL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[3] - -[system.ruby.l2_cntrl0.L1RequestFromL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[4] - -[system.ruby.l2_cntrl0.L1RequestToL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[4] - -[system.ruby.l2_cntrl0.L2cache] -type=RubyCache -children=replacement_policy -assoc=2 -block_size=0 -dataAccessLatency=1 -dataArrayBanks=1 -eventq_index=0 -is_icache=false -replacement_policy=system.ruby.l2_cntrl0.L2cache.replacement_policy -resourceStalls=false -ruby_system=system.ruby -size=512 -start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 - -[system.ruby.l2_cntrl0.L2cache.replacement_policy] -type=PseudoLRUReplacementPolicy -assoc=2 -block_size=64 -eventq_index=0 -size=512 - -[system.ruby.l2_cntrl0.persistentToL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -slave=system.ruby.network.master[6] - -[system.ruby.l2_cntrl0.responseFromL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[5] - -[system.ruby.l2_cntrl0.responseToL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[5] - -[system.ruby.memctrl_clk_domain] -type=DerivedClockDomain -clk_divider=3 -clk_domain=system.ruby.clk_domain -eventq_index=0 - -[system.ruby.network] -type=SimpleNetwork -children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_link_buffers40 int_link_buffers41 int_link_buffers42 int_link_buffers43 int_link_buffers44 int_link_buffers45 int_link_buffers46 int_link_buffers47 int_link_buffers48 int_link_buffers49 int_link_buffers50 int_link_buffers51 int_link_buffers52 int_link_buffers53 int_link_buffers54 int_link_buffers55 int_link_buffers56 int_link_buffers57 int_link_buffers58 int_link_buffers59 int_link_buffers60 int_link_buffers61 int_link_buffers62 int_link_buffers63 int_link_buffers64 int_link_buffers65 int_link_buffers66 int_link_buffers67 int_link_buffers68 int_link_buffers69 int_link_buffers70 int_link_buffers71 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 routers0 routers1 routers2 routers3 -adaptive_routing=false -buffer_size=0 -clk_domain=system.ruby.clk_domain -control_msg_size=8 -default_p_state=UNDEFINED -endpoint_bandwidth=1000 -eventq_index=0 -ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2 -int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 system.ruby.network.int_link_buffers40 system.ruby.network.int_link_buffers41 system.ruby.network.int_link_buffers42 system.ruby.network.int_link_buffers43 system.ruby.network.int_link_buffers44 system.ruby.network.int_link_buffers45 system.ruby.network.int_link_buffers46 system.ruby.network.int_link_buffers47 system.ruby.network.int_link_buffers48 system.ruby.network.int_link_buffers49 system.ruby.network.int_link_buffers50 system.ruby.network.int_link_buffers51 system.ruby.network.int_link_buffers52 system.ruby.network.int_link_buffers53 system.ruby.network.int_link_buffers54 system.ruby.network.int_link_buffers55 system.ruby.network.int_link_buffers56 system.ruby.network.int_link_buffers57 system.ruby.network.int_link_buffers58 system.ruby.network.int_link_buffers59 system.ruby.network.int_link_buffers60 system.ruby.network.int_link_buffers61 system.ruby.network.int_link_buffers62 system.ruby.network.int_link_buffers63 system.ruby.network.int_link_buffers64 system.ruby.network.int_link_buffers65 system.ruby.network.int_link_buffers66 system.ruby.network.int_link_buffers67 system.ruby.network.int_link_buffers68 system.ruby.network.int_link_buffers69 system.ruby.network.int_link_buffers70 system.ruby.network.int_link_buffers71 -int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4 system.ruby.network.int_links5 -netifs= -number_of_virtual_networks=6 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 system.ruby.network.routers3 -ruby_system=system.ruby -topology=Crossbar -master=system.ruby.l1_cntrl0.requestToL1Cache.slave system.ruby.l1_cntrl0.responseToL1Cache.slave system.ruby.l1_cntrl0.persistentToL1Cache.slave system.ruby.l2_cntrl0.GlobalRequestToL2Cache.slave system.ruby.l2_cntrl0.L1RequestToL2Cache.slave system.ruby.l2_cntrl0.responseToL2Cache.slave system.ruby.l2_cntrl0.persistentToL2Cache.slave system.ruby.dir_cntrl0.requestToDir.slave system.ruby.dir_cntrl0.responseToDir.slave system.ruby.dir_cntrl0.persistentToDir.slave system.ruby.dir_cntrl0.dmaRequestToDir.slave -slave=system.ruby.l1_cntrl0.requestFromL1Cache.master system.ruby.l1_cntrl0.responseFromL1Cache.master system.ruby.l1_cntrl0.persistentFromL1Cache.master system.ruby.l2_cntrl0.GlobalRequestFromL2Cache.master system.ruby.l2_cntrl0.L1RequestFromL2Cache.master system.ruby.l2_cntrl0.responseFromL2Cache.master system.ruby.dir_cntrl0.requestFromDir.master system.ruby.dir_cntrl0.responseFromDir.master system.ruby.dir_cntrl0.persistentFromDir.master system.ruby.dir_cntrl0.dmaResponseFromDir.master - -[system.ruby.network.ext_links0] -type=SimpleExtLink -bandwidth_factor=16 -eventq_index=0 -ext_node=system.ruby.l1_cntrl0 -int_node=system.ruby.network.routers0 -latency=1 -link_id=0 -weight=1 - -[system.ruby.network.ext_links1] -type=SimpleExtLink -bandwidth_factor=16 -eventq_index=0 -ext_node=system.ruby.l2_cntrl0 -int_node=system.ruby.network.routers1 -latency=1 -link_id=1 -weight=1 - -[system.ruby.network.ext_links2] -type=SimpleExtLink -bandwidth_factor=16 -eventq_index=0 -ext_node=system.ruby.dir_cntrl0 -int_node=system.ruby.network.routers2 -latency=1 -link_id=2 -weight=1 - -[system.ruby.network.int_link_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers15] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers16] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers17] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers18] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers19] -type=MessageBuffer -buffer_size=0 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-dst_node=system.ruby.network.routers1 -eventq_index=0 -latency=1 -link_id=7 -src_node=system.ruby.network.routers3 -src_outport= -weight=1 - -[system.ruby.network.int_links5] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers2 -eventq_index=0 -latency=1 -link_id=8 -src_node=system.ruby.network.routers3 -src_outport= -weight=1 - -[system.ruby.network.routers0] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 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system.ruby.network.routers3.port_buffers18 system.ruby.network.routers3.port_buffers19 system.ruby.network.routers3.port_buffers20 system.ruby.network.routers3.port_buffers21 system.ruby.network.routers3.port_buffers22 system.ruby.network.routers3.port_buffers23 system.ruby.network.routers3.port_buffers24 system.ruby.network.routers3.port_buffers25 system.ruby.network.routers3.port_buffers26 system.ruby.network.routers3.port_buffers27 system.ruby.network.routers3.port_buffers28 system.ruby.network.routers3.port_buffers29 system.ruby.network.routers3.port_buffers30 system.ruby.network.routers3.port_buffers31 system.ruby.network.routers3.port_buffers32 system.ruby.network.routers3.port_buffers33 system.ruby.network.routers3.port_buffers34 system.ruby.network.routers3.port_buffers35 -power_model=Null -router_id=3 -virt_nets=6 - -[system.ruby.network.routers3.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers15] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers16] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers17] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers18] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers19] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers20] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers21] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers22] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers23] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers24] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers25] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers26] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers27] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers28] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers29] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers30] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers31] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers32] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers33] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers34] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers35] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.sys_port_proxy] -type=RubyPortProxy -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_cpu_sequencer=true -no_retry_on_stall=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -ruby_system=system.ruby -support_data_reqs=true -support_inst_reqs=true -system=system -using_ruby_tester=false -version=0 -slave=system.system_port - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,11 +0,0 @@ -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! -warn: ignoring syscall sigprocmask(1, ...) diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,15 +0,0 @@ -Redirecting stdout to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout -Redirecting stderr to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 13 2016 20:33:48 -gem5 started Oct 13 2016 20:34:16 -gem5 executing on e108600-lin, pid 27527 -command line: /work/curdun01/gem5-external.hg/build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token - -Global frequency set at 1000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Hello world! -Exiting @ tick 42756 because target called exit() diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,850 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000043 # Number of seconds simulated -sim_ticks 42756 # Number of ticks simulated -final_tick 42756 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 103649 # Simulator instruction rate (inst/s) -host_op_rate 103608 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1718399 # Simulator tick rate (ticks/s) -host_mem_usage 412956 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -sim_insts 2577 # Number of instructions simulated -sim_ops 2577 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 28672 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 28672 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 5376 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 5376 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 448 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 448 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 84 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 84 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 670595940 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 670595940 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 125736739 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 125736739 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 796332678 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 796332678 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 448 # Number of read requests accepted -system.mem_ctrls.writeReqs 84 # Number of write requests accepted -system.mem_ctrls.readBursts 448 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 84 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 24000 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 4672 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 1024 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 28672 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 5376 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 73 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 38 # Number of DRAM write bursts merged with an existing one -system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 1 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 1 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 37 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 26 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 24 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 70 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 72 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::9 4 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 29 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 16 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 23 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 60 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 11 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 1 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 3 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 5 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 7 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::15 1 # Per bank write bursts -system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 42675 # Total gap between requests -system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 448 # Read request sizes (log2) -system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 84 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 375 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 2 # What write 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-system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 72 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 326.222222 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 214.888456 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 283.209683 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 20 27.78% 27.78% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 16 22.22% 50.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 10 13.89% 63.89% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 5 6.94% 70.83% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 9 12.50% 83.33% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 2 2.78% 86.11% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 6 8.33% 94.44% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 2 2.78% 97.22% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 2 2.78% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 72 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 1 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 245 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 245.000000 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev nan # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::240-247 1 100.00% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 1 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 1 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev nan # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 1 100.00% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 1 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 4832 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 11957 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 1875 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 12.89 # Average queueing delay per DRAM burst -system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 31.89 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 561.32 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 23.95 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 670.60 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 125.74 # Average system write bandwidth in MiByte/s -system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 4.57 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 4.39 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 0.19 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 21.84 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 296 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 15 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 78.93 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 32.61 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 80.22 # Average gap between requests -system.mem_ctrls.pageHitRate 73.87 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 178500 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 81144 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 1816416 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 3073200.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 2612424 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 73344 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.actPowerDownEnergy 15837336 # Energy for active power-down per rank (pJ) -system.mem_ctrls_0.prePowerDownEnergy 808320 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrls_0.totalEnergy 24480684 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 572.567219 # Core power per rank (mW) -system.mem_ctrls_0.totalIdleTime 36801 # Total Idle time Per DRAM Rank -system.mem_ctrls_0.memoryStateTime::IDLE 51 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 1300 # Time in different power states -system.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::PRE_PDN 2105 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 4569 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 34731 # Time in different power states -system.mem_ctrls_1.actEnergy 392700 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 197064 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 2467584 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 133632 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 3073200.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 3542208 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 293376 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.actPowerDownEnergy 15524520 # Energy for active power-down per rank (pJ) -system.mem_ctrls_1.prePowerDownEnergy 68736 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrls_1.totalEnergy 25693020 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 600.921976 # Core power per rank (mW) -system.mem_ctrls_1.totalIdleTime 33391 # Total Idle time Per DRAM Rank -system.mem_ctrls_1.memoryStateTime::IDLE 512 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 1300 # Time in different power states -system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 179 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 6720 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT_PDN 34045 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states -system.cpu.clk_domain.clock 1 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 415 # DTB read hits -system.cpu.dtb.read_misses 4 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 419 # DTB read accesses -system.cpu.dtb.write_hits 294 # DTB write hits -system.cpu.dtb.write_misses 4 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 298 # DTB write accesses -system.cpu.dtb.data_hits 709 # DTB hits -system.cpu.dtb.data_misses 8 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 717 # DTB accesses -system.cpu.itb.fetch_hits 2586 # ITB hits -system.cpu.itb.fetch_misses 11 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2597 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 42756 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 42756 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 2577 # Number of instructions committed -system.cpu.committedOps 2577 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses -system.cpu.num_func_calls 140 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls -system.cpu.num_int_insts 2375 # number of integer instructions -system.cpu.num_fp_insts 6 # number of float instructions -system.cpu.num_int_register_reads 2998 # number of times the integer registers were read -system.cpu.num_int_register_writes 1768 # number of times the integer registers were written -system.cpu.num_fp_register_reads 6 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 717 # number of memory refs -system.cpu.num_load_insts 419 # Number of load instructions -system.cpu.num_store_insts 298 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 42756 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 396 # Number of branches fetched -system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction -system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction -system.cpu.op_class::MemWrite 292 11.30% 99.77% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 99.77% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 6 0.23% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 2585 # Class of executed instruction -system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states -system.ruby.outstanding_req_hist_seqr::bucket_size 1 -system.ruby.outstanding_req_hist_seqr::max_bucket 9 -system.ruby.outstanding_req_hist_seqr::samples 3295 -system.ruby.outstanding_req_hist_seqr::mean 1 -system.ruby.outstanding_req_hist_seqr::gmean 1 -system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 3295 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist_seqr::total 3295 -system.ruby.latency_hist_seqr::bucket_size 64 -system.ruby.latency_hist_seqr::max_bucket 639 -system.ruby.latency_hist_seqr::samples 3294 -system.ruby.latency_hist_seqr::mean 11.979964 -system.ruby.latency_hist_seqr::gmean 1.922311 -system.ruby.latency_hist_seqr::stdev 28.863148 -system.ruby.latency_hist_seqr | 2919 88.62% 88.62% | 368 11.17% 99.79% | 2 0.06% 99.85% | 1 0.03% 99.88% | 0 0.00% 99.88% | 4 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist_seqr::total 3294 -system.ruby.hit_latency_hist_seqr::bucket_size 4 -system.ruby.hit_latency_hist_seqr::max_bucket 39 -system.ruby.hit_latency_hist_seqr::samples 2846 -system.ruby.hit_latency_hist_seqr::mean 1.555868 -system.ruby.hit_latency_hist_seqr::gmean 1.080822 -system.ruby.hit_latency_hist_seqr::stdev 3.505788 -system.ruby.hit_latency_hist_seqr | 2776 97.54% 97.54% | 0 0.00% 97.54% | 0 0.00% 97.54% | 0 0.00% 97.54% | 0 0.00% 97.54% | 8 0.28% 97.82% | 62 2.18% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist_seqr::total 2846 -system.ruby.miss_latency_hist_seqr::bucket_size 64 -system.ruby.miss_latency_hist_seqr::max_bucket 639 -system.ruby.miss_latency_hist_seqr::samples 448 -system.ruby.miss_latency_hist_seqr::mean 78.200893 -system.ruby.miss_latency_hist_seqr::gmean 74.547837 -system.ruby.miss_latency_hist_seqr::stdev 31.179064 -system.ruby.miss_latency_hist_seqr | 73 16.29% 16.29% | 368 82.14% 98.44% | 2 0.45% 98.88% | 1 0.22% 99.11% | 0 0.00% 99.11% | 4 0.89% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist_seqr::total 448 -system.ruby.Directory.incomplete_times_seqr 447 -system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.L1Dcache.demand_hits 461 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 248 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Icache.demand_hits 2315 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Icache.demand_misses 270 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Icache.demand_accesses 2585 # Number of cache demand accesses -system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states -system.ruby.l2_cntrl0.L2cache.demand_hits 64 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 454 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 518 # Number of cache demand accesses -system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.percent_links_utilized 5.680489 -system.ruby.network.routers0.msg_count.Request_Control::1 518 -system.ruby.network.routers0.msg_count.Response_Data::4 448 -system.ruby.network.routers0.msg_count.ResponseL2hit_Data::4 70 -system.ruby.network.routers0.msg_count.Response_Control::4 1 -system.ruby.network.routers0.msg_count.Writeback_Data::4 502 -system.ruby.network.routers0.msg_count.Persistent_Control::3 16 -system.ruby.network.routers0.msg_bytes.Request_Control::1 4144 -system.ruby.network.routers0.msg_bytes.Response_Data::4 32256 -system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::4 5040 -system.ruby.network.routers0.msg_bytes.Response_Control::4 8 -system.ruby.network.routers0.msg_bytes.Writeback_Data::4 36144 -system.ruby.network.routers0.msg_bytes.Persistent_Control::3 128 -system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states -system.ruby.network.routers1.percent_links_utilized 4.239171 -system.ruby.network.routers1.msg_count.Request_Control::1 518 -system.ruby.network.routers1.msg_count.Request_Control::2 454 -system.ruby.network.routers1.msg_count.ResponseL2hit_Data::4 70 -system.ruby.network.routers1.msg_count.Response_Control::4 1 -system.ruby.network.routers1.msg_count.Writeback_Data::4 586 -system.ruby.network.routers1.msg_count.Writeback_Control::4 365 -system.ruby.network.routers1.msg_count.Persistent_Control::3 8 -system.ruby.network.routers1.msg_bytes.Request_Control::1 4144 -system.ruby.network.routers1.msg_bytes.Request_Control::2 3632 -system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::4 5040 -system.ruby.network.routers1.msg_bytes.Response_Control::4 8 -system.ruby.network.routers1.msg_bytes.Writeback_Data::4 42192 -system.ruby.network.routers1.msg_bytes.Writeback_Control::4 2920 -system.ruby.network.routers1.msg_bytes.Persistent_Control::3 64 -system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states -system.ruby.network.routers2.percent_links_utilized 3.283165 -system.ruby.network.routers2.msg_count.Request_Control::2 454 -system.ruby.network.routers2.msg_count.Response_Data::4 448 -system.ruby.network.routers2.msg_count.Writeback_Data::4 84 -system.ruby.network.routers2.msg_count.Writeback_Control::4 365 -system.ruby.network.routers2.msg_count.Persistent_Control::3 8 -system.ruby.network.routers2.msg_bytes.Request_Control::2 3632 -system.ruby.network.routers2.msg_bytes.Response_Data::4 32256 -system.ruby.network.routers2.msg_bytes.Writeback_Data::4 6048 -system.ruby.network.routers2.msg_bytes.Writeback_Control::4 2920 -system.ruby.network.routers2.msg_bytes.Persistent_Control::3 64 -system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states -system.ruby.network.routers3.percent_links_utilized 4.400942 -system.ruby.network.routers3.msg_count.Request_Control::1 518 -system.ruby.network.routers3.msg_count.Request_Control::2 454 -system.ruby.network.routers3.msg_count.Response_Data::4 448 -system.ruby.network.routers3.msg_count.ResponseL2hit_Data::4 70 -system.ruby.network.routers3.msg_count.Response_Control::4 1 -system.ruby.network.routers3.msg_count.Writeback_Data::4 586 -system.ruby.network.routers3.msg_count.Writeback_Control::4 365 -system.ruby.network.routers3.msg_count.Persistent_Control::3 16 -system.ruby.network.routers3.msg_bytes.Request_Control::1 4144 -system.ruby.network.routers3.msg_bytes.Request_Control::2 3632 -system.ruby.network.routers3.msg_bytes.Response_Data::4 32256 -system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::4 5040 -system.ruby.network.routers3.msg_bytes.Response_Control::4 8 -system.ruby.network.routers3.msg_bytes.Writeback_Data::4 42192 -system.ruby.network.routers3.msg_bytes.Writeback_Control::4 2920 -system.ruby.network.routers3.msg_bytes.Persistent_Control::3 128 -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states -system.ruby.network.msg_count.Request_Control 2916 -system.ruby.network.msg_count.Response_Data 1344 -system.ruby.network.msg_count.ResponseL2hit_Data 210 -system.ruby.network.msg_count.Response_Control 3 -system.ruby.network.msg_count.Writeback_Data 1758 -system.ruby.network.msg_count.Writeback_Control 1095 -system.ruby.network.msg_count.Persistent_Control 48 -system.ruby.network.msg_byte.Request_Control 23328 -system.ruby.network.msg_byte.Response_Data 96768 -system.ruby.network.msg_byte.ResponseL2hit_Data 15120 -system.ruby.network.msg_byte.Response_Control 24 -system.ruby.network.msg_byte.Writeback_Data 126576 -system.ruby.network.msg_byte.Writeback_Control 8760 -system.ruby.network.msg_byte.Persistent_Control 384 -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.throttle0.link_utilization 5.462391 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 448 -system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4 70 -system.ruby.network.routers0.throttle0.msg_count.Response_Control::4 1 -system.ruby.network.routers0.throttle0.msg_count.Persistent_Control::3 8 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 32256 -system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::4 5040 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::4 8 -system.ruby.network.routers0.throttle0.msg_bytes.Persistent_Control::3 64 -system.ruby.network.routers0.throttle1.link_utilization 5.898587 -system.ruby.network.routers0.throttle1.msg_count.Request_Control::1 518 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::4 502 -system.ruby.network.routers0.throttle1.msg_count.Persistent_Control::3 8 -system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::1 4144 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::4 36144 -system.ruby.network.routers0.throttle1.msg_bytes.Persistent_Control::3 64 -system.ruby.network.routers1.throttle0.link_utilization 5.898587 -system.ruby.network.routers1.throttle0.msg_count.Request_Control::1 518 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::4 502 -system.ruby.network.routers1.throttle0.msg_count.Persistent_Control::3 8 -system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::1 4144 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::4 36144 -system.ruby.network.routers1.throttle0.msg_bytes.Persistent_Control::3 64 -system.ruby.network.routers1.throttle1.link_utilization 2.579755 -system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 454 -system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::4 70 -system.ruby.network.routers1.throttle1.msg_count.Response_Control::4 1 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::4 84 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::4 365 -system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2 3632 -system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::4 5040 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::4 8 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::4 6048 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::4 2920 -system.ruby.network.routers2.throttle0.link_utilization 1.851202 -system.ruby.network.routers2.throttle0.msg_count.Request_Control::2 454 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::4 84 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::4 365 -system.ruby.network.routers2.throttle0.msg_count.Persistent_Control::3 8 -system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::2 3632 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::4 6048 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::4 2920 -system.ruby.network.routers2.throttle0.msg_bytes.Persistent_Control::3 64 -system.ruby.network.routers2.throttle1.link_utilization 4.715128 -system.ruby.network.routers2.throttle1.msg_count.Response_Data::4 448 -system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::4 32256 -system.ruby.network.routers3.throttle0.link_utilization 5.453036 -system.ruby.network.routers3.throttle0.msg_count.Response_Data::4 448 -system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::4 70 -system.ruby.network.routers3.throttle0.msg_count.Response_Control::4 1 -system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::4 32256 -system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::4 5040 -system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::4 8 -system.ruby.network.routers3.throttle1.link_utilization 5.898587 -system.ruby.network.routers3.throttle1.msg_count.Request_Control::1 518 -system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::4 502 -system.ruby.network.routers3.throttle1.msg_count.Persistent_Control::3 8 -system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::1 4144 -system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::4 36144 -system.ruby.network.routers3.throttle1.msg_bytes.Persistent_Control::3 64 -system.ruby.network.routers3.throttle2.link_utilization 1.851202 -system.ruby.network.routers3.throttle2.msg_count.Request_Control::2 454 -system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::4 84 -system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::4 365 -system.ruby.network.routers3.throttle2.msg_count.Persistent_Control::3 8 -system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::2 3632 -system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::4 6048 -system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::4 2920 -system.ruby.network.routers3.throttle2.msg_bytes.Persistent_Control::3 64 -system.ruby.LD.latency_hist_seqr::bucket_size 16 -system.ruby.LD.latency_hist_seqr::max_bucket 159 -system.ruby.LD.latency_hist_seqr::samples 415 -system.ruby.LD.latency_hist_seqr::mean 27.997590 -system.ruby.LD.latency_hist_seqr::gmean 5.837138 -system.ruby.LD.latency_hist_seqr::stdev 35.585408 -system.ruby.LD.latency_hist_seqr | 233 56.14% 56.14% | 33 7.95% 64.10% | 48 11.57% 75.66% | 2 0.48% 76.14% | 68 16.39% 92.53% | 18 4.34% 96.87% | 10 2.41% 99.28% | 1 0.24% 99.52% | 0 0.00% 99.52% | 2 0.48% 100.00% -system.ruby.LD.latency_hist_seqr::total 415 -system.ruby.LD.hit_latency_hist_seqr::bucket_size 4 -system.ruby.LD.hit_latency_hist_seqr::max_bucket 39 -system.ruby.LD.hit_latency_hist_seqr::samples 266 -system.ruby.LD.hit_latency_hist_seqr::mean 3.845865 -system.ruby.LD.hit_latency_hist_seqr::gmean 1.482816 -system.ruby.LD.hit_latency_hist_seqr::stdev 7.577195 -system.ruby.LD.hit_latency_hist_seqr | 233 87.59% 87.59% | 0 0.00% 87.59% | 0 0.00% 87.59% | 0 0.00% 87.59% | 0 0.00% 87.59% | 1 0.38% 87.97% | 32 12.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist_seqr::total 266 -system.ruby.LD.miss_latency_hist_seqr::bucket_size 16 -system.ruby.LD.miss_latency_hist_seqr::max_bucket 159 -system.ruby.LD.miss_latency_hist_seqr::samples 149 -system.ruby.LD.miss_latency_hist_seqr::mean 71.114094 -system.ruby.LD.miss_latency_hist_seqr::gmean 67.393219 -system.ruby.LD.miss_latency_hist_seqr::stdev 22.792700 -system.ruby.LD.miss_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 48 32.21% 32.21% | 2 1.34% 33.56% | 68 45.64% 79.19% | 18 12.08% 91.28% | 10 6.71% 97.99% | 1 0.67% 98.66% | 0 0.00% 98.66% | 2 1.34% 100.00% -system.ruby.LD.miss_latency_hist_seqr::total 149 -system.ruby.ST.latency_hist_seqr::bucket_size 16 -system.ruby.ST.latency_hist_seqr::max_bucket 159 -system.ruby.ST.latency_hist_seqr::samples 294 -system.ruby.ST.latency_hist_seqr::mean 13.153061 -system.ruby.ST.latency_hist_seqr::gmean 2.398410 -system.ruby.ST.latency_hist_seqr::stdev 25.296880 -system.ruby.ST.latency_hist_seqr | 228 77.55% 77.55% | 14 4.76% 82.31% | 20 6.80% 89.12% | 3 1.02% 90.14% | 23 7.82% 97.96% | 6 2.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist_seqr::total 294 -system.ruby.ST.hit_latency_hist_seqr::bucket_size 4 -system.ruby.ST.hit_latency_hist_seqr::max_bucket 39 -system.ruby.ST.hit_latency_hist_seqr::samples 242 -system.ruby.ST.hit_latency_hist_seqr::mean 2.223140 -system.ruby.ST.hit_latency_hist_seqr::gmean 1.195990 -system.ruby.ST.hit_latency_hist_seqr::stdev 4.967926 -system.ruby.ST.hit_latency_hist_seqr | 228 94.21% 94.21% | 0 0.00% 94.21% | 0 0.00% 94.21% | 0 0.00% 94.21% | 0 0.00% 94.21% | 7 2.89% 97.11% | 7 2.89% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist_seqr::total 242 -system.ruby.ST.miss_latency_hist_seqr::bucket_size 16 -system.ruby.ST.miss_latency_hist_seqr::max_bucket 159 -system.ruby.ST.miss_latency_hist_seqr::samples 52 -system.ruby.ST.miss_latency_hist_seqr::mean 64.019231 -system.ruby.ST.miss_latency_hist_seqr::gmean 61.135942 -system.ruby.ST.miss_latency_hist_seqr::stdev 18.838311 -system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 20 38.46% 38.46% | 3 5.77% 44.23% | 23 44.23% 88.46% | 6 11.54% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist_seqr::total 52 -system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 -system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.latency_hist_seqr::samples 2585 -system.ruby.IFETCH.latency_hist_seqr::mean 9.275048 -system.ruby.IFETCH.latency_hist_seqr::gmean 1.568384 -system.ruby.IFETCH.latency_hist_seqr::stdev 27.157574 -system.ruby.IFETCH.latency_hist_seqr | 2338 90.44% 90.44% | 242 9.36% 99.81% | 0 0.00% 99.81% | 1 0.04% 99.85% | 0 0.00% 99.85% | 4 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist_seqr::total 2585 -system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 4 -system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 39 -system.ruby.IFETCH.hit_latency_hist_seqr::samples 2338 -system.ruby.IFETCH.hit_latency_hist_seqr::mean 1.226262 -system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1.031758 -system.ruby.IFETCH.hit_latency_hist_seqr::stdev 2.270469 -system.ruby.IFETCH.hit_latency_hist_seqr | 2315 99.02% 99.02% | 0 0.00% 99.02% | 0 0.00% 99.02% | 0 0.00% 99.02% | 0 0.00% 99.02% | 0 0.00% 99.02% | 23 0.98% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist_seqr::total 2338 -system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 -system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.miss_latency_hist_seqr::samples 247 -system.ruby.IFETCH.miss_latency_hist_seqr::mean 85.461538 -system.ruby.IFETCH.miss_latency_hist_seqr::gmean 82.604305 -system.ruby.IFETCH.miss_latency_hist_seqr::stdev 35.418255 -system.ruby.IFETCH.miss_latency_hist_seqr | 0 0.00% 0.00% | 242 97.98% 97.98% | 0 0.00% 97.98% | 1 0.40% 98.38% | 0 0.00% 98.38% | 4 1.62% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.miss_latency_hist_seqr::total 247 -system.ruby.L1Cache.hit_mach_latency_hist_seqr::bucket_size 1 -system.ruby.L1Cache.hit_mach_latency_hist_seqr::max_bucket 9 -system.ruby.L1Cache.hit_mach_latency_hist_seqr::samples 2776 -system.ruby.L1Cache.hit_mach_latency_hist_seqr::mean 1 -system.ruby.L1Cache.hit_mach_latency_hist_seqr::gmean 1 -system.ruby.L1Cache.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 2776 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.hit_mach_latency_hist_seqr::total 2776 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::bucket_size 4 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::max_bucket 39 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::samples 70 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::mean 23.600000 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::gmean 23.569187 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::stdev 1.159710 -system.ruby.L2Cache.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 8 11.43% 11.43% | 62 88.57% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L2Cache.hit_mach_latency_hist_seqr::total 70 -system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 -system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 -system.ruby.Directory.miss_mach_latency_hist_seqr::samples 448 -system.ruby.Directory.miss_mach_latency_hist_seqr::mean 78.200893 -system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 74.547837 -system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 31.179064 -system.ruby.Directory.miss_mach_latency_hist_seqr | 73 16.29% 16.29% | 368 82.14% 98.44% | 2 0.45% 98.88% | 1 0.22% 99.11% | 0 0.00% 99.11% | 4 0.89% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_mach_latency_hist_seqr::total 448 -system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 -system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 -system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1 -system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::stdev nan -system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 1 -system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 1 -system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::max_bucket 9 -system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::samples 1 -system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::stdev nan -system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::total 1 -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::bucket_size 1 -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::max_bucket 9 -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::samples 1 -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::stdev nan -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total 1 -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size 16 -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 159 -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 1 -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean 82 -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 82.000000 -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::samples 233 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::mean 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 233 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::total 233 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 4 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 39 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::samples 33 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::mean 23.939394 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::gmean 23.936802 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::stdev 0.348155 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 3.03% 3.03% | 32 96.97% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::total 33 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 16 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 159 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 149 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 71.114094 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 67.393219 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 22.792700 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 48 32.21% 32.21% | 2 1.34% 33.56% | 68 45.64% 79.19% | 18 12.08% 91.28% | 10 6.71% 97.99% | 1 0.67% 98.66% | 0 0.00% 98.66% | 2 1.34% 100.00% -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 149 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::samples 228 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::mean 1 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 228 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::total 228 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 4 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 39 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::samples 14 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::mean 22.142857 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::gmean 22.058564 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::stdev 1.994498 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 7 50.00% 50.00% | 7 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::total 14 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 16 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 159 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 52 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 64.019231 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 61.135942 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 18.838311 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 20 38.46% 38.46% | 3 5.77% 44.23% | 23 44.23% 88.46% | 6 11.54% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 52 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::samples 2315 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::mean 1 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 2315 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::total 2315 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 4 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 39 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::samples 23 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::mean 24 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::gmean 24.000000 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 23 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::total 23 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 247 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 85.461538 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 82.604305 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 35.418255 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 242 97.98% 97.98% | 0 0.00% 97.98% | 1 0.40% 98.38% | 0 0.00% 98.38% | 4 1.62% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 247 -system.ruby.Directory_Controller.GETX 61 0.00% 0.00% -system.ruby.Directory_Controller.GETS 398 0.00% 0.00% -system.ruby.Directory_Controller.Lockdown 4 0.00% 0.00% -system.ruby.Directory_Controller.Unlockdown 4 0.00% 0.00% -system.ruby.Directory_Controller.Data_Owner 3 0.00% 0.00% -system.ruby.Directory_Controller.Data_All_Tokens 81 0.00% 0.00% -system.ruby.Directory_Controller.Ack_Owner 16 0.00% 0.00% -system.ruby.Directory_Controller.Ack_Owner_All_Tokens 334 0.00% 0.00% -system.ruby.Directory_Controller.Ack_All_Tokens 15 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 448 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 84 0.00% 0.00% -system.ruby.Directory_Controller.O.GETX 52 0.00% 0.00% -system.ruby.Directory_Controller.O.GETS 396 0.00% 0.00% -system.ruby.Directory_Controller.O.Ack_All_Tokens 15 0.00% 0.00% -system.ruby.Directory_Controller.NO.GETX 6 0.00% 0.00% -system.ruby.Directory_Controller.NO.Lockdown 1 0.00% 0.00% -system.ruby.Directory_Controller.NO.Data_Owner 3 0.00% 0.00% -system.ruby.Directory_Controller.NO.Data_All_Tokens 81 0.00% 0.00% -system.ruby.Directory_Controller.NO.Ack_Owner 16 0.00% 0.00% -system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens 334 0.00% 0.00% -system.ruby.Directory_Controller.L.Unlockdown 4 0.00% 0.00% -system.ruby.Directory_Controller.O_W.GETX 3 0.00% 0.00% -system.ruby.Directory_Controller.O_W.GETS 2 0.00% 0.00% -system.ruby.Directory_Controller.O_W.Memory_Ack 84 0.00% 0.00% -system.ruby.Directory_Controller.L_NO_W.Memory_Data 3 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.Lockdown 3 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.Memory_Data 445 0.00% 0.00% -system.ruby.L1Cache_Controller.Load 415 0.00% 0.00% -system.ruby.L1Cache_Controller.Ifetch 2585 0.00% 0.00% -system.ruby.L1Cache_Controller.Store 294 0.00% 0.00% -system.ruby.L1Cache_Controller.L1_Replacement 504 0.00% 0.00% -system.ruby.L1Cache_Controller.Data_Shared 56 0.00% 0.00% -system.ruby.L1Cache_Controller.Data_All_Tokens 462 0.00% 0.00% -system.ruby.L1Cache_Controller.Ack 1 0.00% 0.00% -system.ruby.L1Cache_Controller.Own_Lock_or_Unlock 8 0.00% 0.00% -system.ruby.L1Cache_Controller.Request_Timeout 4 0.00% 0.00% -system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers 461 0.00% 0.00% -system.ruby.L1Cache_Controller.NP.Load 182 0.00% 0.00% -system.ruby.L1Cache_Controller.NP.Ifetch 270 0.00% 0.00% -system.ruby.L1Cache_Controller.NP.Store 58 0.00% 0.00% -system.ruby.L1Cache_Controller.S.Load 29 0.00% 0.00% -system.ruby.L1Cache_Controller.S.Ifetch 158 0.00% 0.00% -system.ruby.L1Cache_Controller.S.Store 8 0.00% 0.00% -system.ruby.L1Cache_Controller.S.L1_Replacement 48 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Load 66 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Ifetch 1098 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Store 29 0.00% 0.00% -system.ruby.L1Cache_Controller.M.L1_Replacement 358 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock 4 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.Load 96 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.Store 103 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.L1_Replacement 96 0.00% 0.00% -system.ruby.L1Cache_Controller.M_W.Load 36 0.00% 0.00% -system.ruby.L1Cache_Controller.M_W.Ifetch 1059 0.00% 0.00% -system.ruby.L1Cache_Controller.M_W.Store 3 0.00% 0.00% -system.ruby.L1Cache_Controller.M_W.L1_Replacement 1 0.00% 0.00% -system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers 392 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_W.Load 6 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_W.Store 93 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_W.L1_Replacement 1 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_W.Use_TimeoutNoStarvers 69 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.Data_All_Tokens 58 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.Ack 1 0.00% 0.00% -system.ruby.L1Cache_Controller.SM.Data_All_Tokens 8 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Data_Shared 56 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Data_All_Tokens 396 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Own_Lock_or_Unlock 4 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Request_Timeout 4 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETS 448 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETS_Last_Token 4 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETX 66 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement 458 0.00% 0.00% -system.ruby.L2Cache_Controller.Writeback_Shared_Data 21 0.00% 0.00% -system.ruby.L2Cache_Controller.Writeback_All_Tokens 481 0.00% 0.00% -system.ruby.L2Cache_Controller.Persistent_GETS 4 0.00% 0.00% -system.ruby.L2Cache_Controller.Own_Lock_or_Unlock 4 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETS 396 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETX 50 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.Writeback_Shared_Data 18 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.Writeback_All_Tokens 448 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.Own_Lock_or_Unlock 4 0.00% 0.00% -system.ruby.L2Cache_Controller.I.L1_GETX 1 0.00% 0.00% -system.ruby.L2Cache_Controller.I.L2_Replacement 9 0.00% 0.00% -system.ruby.L2Cache_Controller.I.Writeback_Shared_Data 3 0.00% 0.00% -system.ruby.L2Cache_Controller.I.Writeback_All_Tokens 6 0.00% 0.00% -system.ruby.L2Cache_Controller.S.L1_GETS_Last_Token 4 0.00% 0.00% -system.ruby.L2Cache_Controller.S.L1_GETX 1 0.00% 0.00% -system.ruby.L2Cache_Controller.S.L2_Replacement 15 0.00% 0.00% -system.ruby.L2Cache_Controller.O.L1_GETX 6 0.00% 0.00% -system.ruby.L2Cache_Controller.O.L2_Replacement 19 0.00% 0.00% -system.ruby.L2Cache_Controller.O.Writeback_All_Tokens 27 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETS 52 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETX 8 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement 415 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.Persistent_GETS 4 0.00% 0.00% - ----------- End Simulation Statistics ---------- diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,1514 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000 -time_sync_spin_threshold=100000 - -[system] -type=System -children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges=0:268435455:0:0:0:0 -memories=system.mem_ctrls -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.sys_port_proxy.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=TimingSimpleCPU -children=clk_domain dtb interrupts isa itb tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu.clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1] -icache_port=system.ruby.l1_cntrl0.sequencer.slave[0] - -[system.cpu.clk_domain] -type=SrcClockDomain -clock=1 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=hello -cwd= -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/tru64/hello -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000 - -[system.mem_ctrls] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -page_policy=open_adaptive -power_model=Null -range=0:268435455:5:19:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10 -static_frontend_latency=10 -tBURST=5 -tCCD_L=0 -tCK=1 -tCL=14 -tCS=3 -tRAS=35 -tRCD=14 -tREFI=7800 -tRFC=260 -tRP=14 -tRRD=6 -tRRD_L=0 -tRTP=8 -tRTW=3 -tWR=15 -tWTR=8 -tXAW=30 -tXP=6 -tXPDLL=0 -tXS=270 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.ruby.dir_cntrl0.memory - -[system.ruby] -type=RubySystem -children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network -access_backing_store=false -all_instructions=false -block_size_bytes=64 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hot_lines=false -memory_size_bits=48 -num_of_sequencers=1 -number_of_virtual_networks=6 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -phys_mem=Null -power_model=Null -randomization=false - -[system.ruby.clk_domain] -type=SrcClockDomain -clock=1 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.ruby.dir_cntrl0] -type=Directory_Controller -children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir probeFilter requestToDir responseFromDir responseFromMemory responseToDir triggerQueue unblockToDir -buffer_size=0 -clk_domain=system.ruby.clk_domain -cluster_id=0 -default_p_state=UNDEFINED -directory=system.ruby.dir_cntrl0.directory -dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir -dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir -eventq_index=0 -forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir -from_memory_controller_latency=2 -full_bit_dir_enabled=false -number_of_TBEs=256 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -probeFilter=system.ruby.dir_cntrl0.probeFilter -probe_filter_enabled=false -recycle_latency=10 -requestToDir=system.ruby.dir_cntrl0.requestToDir -responseFromDir=system.ruby.dir_cntrl0.responseFromDir -responseFromMemory=system.ruby.dir_cntrl0.responseFromMemory -responseToDir=system.ruby.dir_cntrl0.responseToDir -ruby_system=system.ruby -system=system -to_memory_controller_latency=1 -transitions_per_cycle=4 -triggerQueue=system.ruby.dir_cntrl0.triggerQueue -unblockToDir=system.ruby.dir_cntrl0.unblockToDir -version=0 -memory=system.mem_ctrls.port - -[system.ruby.dir_cntrl0.directory] -type=RubyDirectoryMemory -eventq_index=0 -numa_high_bit=5 -size=268435456 -version=0 - -[system.ruby.dir_cntrl0.dmaRequestToDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -slave=system.ruby.network.master[5] - -[system.ruby.dir_cntrl0.dmaResponseFromDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -master=system.ruby.network.slave[5] - -[system.ruby.dir_cntrl0.forwardFromDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[3] - -[system.ruby.dir_cntrl0.probeFilter] -type=RubyCache -children=replacement_policy -assoc=4 -block_size=0 -dataAccessLatency=1 -dataArrayBanks=1 -eventq_index=0 -is_icache=false -replacement_policy=system.ruby.dir_cntrl0.probeFilter.replacement_policy -resourceStalls=false -ruby_system=system.ruby -size=1024 -start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 - -[system.ruby.dir_cntrl0.probeFilter.replacement_policy] -type=PseudoLRUReplacementPolicy -assoc=4 -block_size=64 -eventq_index=0 -size=1024 - -[system.ruby.dir_cntrl0.requestToDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[4] - -[system.ruby.dir_cntrl0.responseFromDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[4] - -[system.ruby.dir_cntrl0.responseFromMemory] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false - -[system.ruby.dir_cntrl0.responseToDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[3] - -[system.ruby.dir_cntrl0.triggerQueue] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.dir_cntrl0.unblockToDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[2] - -[system.ruby.l1_cntrl0] -type=L1Cache_Controller -children=L1Dcache L1Icache L2cache forwardToCache mandatoryQueue requestFromCache responseFromCache responseToCache sequencer triggerQueue unblockFromCache -L1Dcache=system.ruby.l1_cntrl0.L1Dcache -L1Icache=system.ruby.l1_cntrl0.L1Icache -L2cache=system.ruby.l1_cntrl0.L2cache -buffer_size=0 -cache_response_latency=10 -clk_domain=system.cpu.clk_domain -cluster_id=0 -default_p_state=UNDEFINED -eventq_index=0 -forwardToCache=system.ruby.l1_cntrl0.forwardToCache -issue_latency=2 -l2_cache_hit_latency=10 -mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue -no_mig_atomic=true -number_of_TBEs=256 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -recycle_latency=10 -requestFromCache=system.ruby.l1_cntrl0.requestFromCache -responseFromCache=system.ruby.l1_cntrl0.responseFromCache -responseToCache=system.ruby.l1_cntrl0.responseToCache -ruby_system=system.ruby -send_evictions=false -sequencer=system.ruby.l1_cntrl0.sequencer -system=system -transitions_per_cycle=4 -triggerQueue=system.ruby.l1_cntrl0.triggerQueue -unblockFromCache=system.ruby.l1_cntrl0.unblockFromCache -version=0 - -[system.ruby.l1_cntrl0.L1Dcache] -type=RubyCache -children=replacement_policy -assoc=2 -block_size=0 -dataAccessLatency=1 -dataArrayBanks=1 -eventq_index=0 -is_icache=false -replacement_policy=system.ruby.l1_cntrl0.L1Dcache.replacement_policy -resourceStalls=false -ruby_system=system.ruby -size=256 -start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 - -[system.ruby.l1_cntrl0.L1Dcache.replacement_policy] -type=PseudoLRUReplacementPolicy -assoc=2 -block_size=64 -eventq_index=0 -size=256 - -[system.ruby.l1_cntrl0.L1Icache] -type=RubyCache -children=replacement_policy -assoc=2 -block_size=0 -dataAccessLatency=1 -dataArrayBanks=1 -eventq_index=0 -is_icache=true -replacement_policy=system.ruby.l1_cntrl0.L1Icache.replacement_policy -resourceStalls=false -ruby_system=system.ruby -size=256 -start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 - -[system.ruby.l1_cntrl0.L1Icache.replacement_policy] -type=PseudoLRUReplacementPolicy -assoc=2 -block_size=64 -eventq_index=0 -size=256 - -[system.ruby.l1_cntrl0.L2cache] -type=RubyCache -children=replacement_policy -assoc=2 -block_size=0 -dataAccessLatency=1 -dataArrayBanks=1 -eventq_index=0 -is_icache=false -replacement_policy=system.ruby.l1_cntrl0.L2cache.replacement_policy -resourceStalls=false -ruby_system=system.ruby -size=512 -start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 - -[system.ruby.l1_cntrl0.L2cache.replacement_policy] -type=PseudoLRUReplacementPolicy -assoc=2 -block_size=64 -eventq_index=0 -size=512 - -[system.ruby.l1_cntrl0.forwardToCache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[0] - -[system.ruby.l1_cntrl0.mandatoryQueue] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false - -[system.ruby.l1_cntrl0.requestFromCache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[0] - -[system.ruby.l1_cntrl0.responseFromCache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[1] - -[system.ruby.l1_cntrl0.responseToCache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[1] - -[system.ruby.l1_cntrl0.sequencer] -type=RubySequencer -clk_domain=system.cpu.clk_domain -coreid=99 -dcache=system.ruby.l1_cntrl0.L1Dcache -dcache_hit_latency=1 -deadlock_threshold=500000 -default_p_state=UNDEFINED -eventq_index=0 -garnet_standalone=false -icache=system.ruby.l1_cntrl0.L1Icache -icache_hit_latency=1 -is_cpu_sequencer=true -max_outstanding_requests=16 -no_retry_on_stall=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -ruby_system=system.ruby -support_data_reqs=true -support_inst_reqs=true -system=system -using_ruby_tester=false -version=0 -slave=system.cpu.icache_port system.cpu.dcache_port - -[system.ruby.l1_cntrl0.triggerQueue] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false - -[system.ruby.l1_cntrl0.unblockFromCache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[2] - -[system.ruby.memctrl_clk_domain] -type=DerivedClockDomain -clk_divider=3 -clk_domain=system.ruby.clk_domain -eventq_index=0 - -[system.ruby.network] -type=SimpleNetwork -children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_link_buffers40 int_link_buffers41 int_link_buffers42 int_link_buffers43 int_link_buffers44 int_link_buffers45 int_link_buffers46 int_link_buffers47 int_links0 int_links1 int_links2 int_links3 routers0 routers1 routers2 -adaptive_routing=false -buffer_size=0 -clk_domain=system.ruby.clk_domain -control_msg_size=8 -default_p_state=UNDEFINED -endpoint_bandwidth=1000 -eventq_index=0 -ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 -int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 system.ruby.network.int_link_buffers40 system.ruby.network.int_link_buffers41 system.ruby.network.int_link_buffers42 system.ruby.network.int_link_buffers43 system.ruby.network.int_link_buffers44 system.ruby.network.int_link_buffers45 system.ruby.network.int_link_buffers46 system.ruby.network.int_link_buffers47 -int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 -netifs= -number_of_virtual_networks=6 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 -ruby_system=system.ruby -topology=Crossbar -master=system.ruby.l1_cntrl0.forwardToCache.slave system.ruby.l1_cntrl0.responseToCache.slave system.ruby.dir_cntrl0.unblockToDir.slave system.ruby.dir_cntrl0.responseToDir.slave system.ruby.dir_cntrl0.requestToDir.slave system.ruby.dir_cntrl0.dmaRequestToDir.slave -slave=system.ruby.l1_cntrl0.requestFromCache.master system.ruby.l1_cntrl0.responseFromCache.master system.ruby.l1_cntrl0.unblockFromCache.master system.ruby.dir_cntrl0.forwardFromDir.master system.ruby.dir_cntrl0.responseFromDir.master system.ruby.dir_cntrl0.dmaResponseFromDir.master - -[system.ruby.network.ext_links0] -type=SimpleExtLink -bandwidth_factor=16 -eventq_index=0 -ext_node=system.ruby.l1_cntrl0 -int_node=system.ruby.network.routers0 -latency=1 -link_id=0 -weight=1 - -[system.ruby.network.ext_links1] -type=SimpleExtLink -bandwidth_factor=16 -eventq_index=0 -ext_node=system.ruby.dir_cntrl0 -int_node=system.ruby.network.routers1 -latency=1 -link_id=1 -weight=1 - -[system.ruby.network.int_link_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers15] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers16] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers17] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers18] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers19] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers20] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers21] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers22] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers23] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers24] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers25] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers26] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers27] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers28] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers29] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers30] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers31] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers32] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers33] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers34] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers35] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers36] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers37] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers38] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers39] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers40] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers41] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers42] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers43] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers44] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers45] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers46] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers47] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_links0] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers2 -eventq_index=0 -latency=1 -link_id=2 -src_node=system.ruby.network.routers0 -src_outport= -weight=1 - -[system.ruby.network.int_links1] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers2 -eventq_index=0 -latency=1 -link_id=3 -src_node=system.ruby.network.routers1 -src_outport= -weight=1 - -[system.ruby.network.int_links2] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers0 -eventq_index=0 -latency=1 -link_id=4 -src_node=system.ruby.network.routers2 -src_outport= -weight=1 - -[system.ruby.network.int_links3] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers1 -eventq_index=0 -latency=1 -link_id=5 -src_node=system.ruby.network.routers2 -src_outport= -weight=1 - -[system.ruby.network.routers0] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 system.ruby.network.routers0.port_buffers12 system.ruby.network.routers0.port_buffers13 system.ruby.network.routers0.port_buffers14 system.ruby.network.routers0.port_buffers15 system.ruby.network.routers0.port_buffers16 system.ruby.network.routers0.port_buffers17 -power_model=Null -router_id=0 -virt_nets=6 - -[system.ruby.network.routers0.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers15] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers16] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers17] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 system.ruby.network.routers1.port_buffers12 system.ruby.network.routers1.port_buffers13 system.ruby.network.routers1.port_buffers14 system.ruby.network.routers1.port_buffers15 system.ruby.network.routers1.port_buffers16 system.ruby.network.routers1.port_buffers17 -power_model=Null -router_id=1 -virt_nets=6 - -[system.ruby.network.routers1.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers15] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers16] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers17] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19 system.ruby.network.routers2.port_buffers20 system.ruby.network.routers2.port_buffers21 system.ruby.network.routers2.port_buffers22 system.ruby.network.routers2.port_buffers23 -power_model=Null -router_id=2 -virt_nets=6 - -[system.ruby.network.routers2.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers15] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers16] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers17] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers18] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers19] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers20] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers21] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers22] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers23] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.sys_port_proxy] -type=RubyPortProxy -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_cpu_sequencer=true -no_retry_on_stall=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -ruby_system=system.ruby -support_data_reqs=true -support_inst_reqs=true -system=system -using_ruby_tester=false -version=0 -slave=system.system_port - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,11 +0,0 @@ -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! -warn: ignoring syscall sigprocmask(1, ...) diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,15 +0,0 @@ -Redirecting stdout to build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout -Redirecting stderr to build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 13 2016 20:24:36 -gem5 started Oct 13 2016 20:24:58 -gem5 executing on e108600-lin, pid 38874 -command line: /work/curdun01/gem5-external.hg/build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer - -Global frequency set at 1000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Hello world! -Exiting @ tick 35056 because target called exit() diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,778 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000035 # Number of seconds simulated -sim_ticks 35056 # Number of ticks simulated -final_tick 35056 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 89727 # Simulator instruction rate (inst/s) -host_op_rate 89697 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1219820 # Simulator tick rate (ticks/s) -host_mem_usage 412632 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host -sim_insts 2577 # Number of instructions simulated -sim_ops 2577 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 35056 # Cumulative time (in ticks) in various power states -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 28224 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 28224 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 5184 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 5184 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 441 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 441 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 81 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 81 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 805111821 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 805111821 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 147877681 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 147877681 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 952989503 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 952989503 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 441 # Number of read requests accepted -system.mem_ctrls.writeReqs 81 # Number of write requests accepted -system.mem_ctrls.readBursts 441 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 81 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 24000 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 4224 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 1024 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 28224 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 5184 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 66 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 35 # Number of DRAM write bursts merged with an existing one -system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 1 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 1 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 37 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 26 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 24 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 72 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 71 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::9 4 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 29 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 16 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 23 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 59 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 11 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 1 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 3 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 5 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 7 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::15 1 # Per bank write bursts -system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 34986 # Total gap between requests -system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 441 # Read request sizes (log2) -system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 81 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 375 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 67 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 356.298507 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 230.035457 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 306.978482 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 19 28.36% 28.36% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 11 16.42% 44.78% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 10 14.93% 59.70% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 7 10.45% 70.15% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 6 8.96% 79.10% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 4 5.97% 85.07% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 3 4.48% 89.55% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 3 4.48% 94.03% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 4 5.97% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 67 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 1 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 245 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 245.000000 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev nan # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::240-247 1 100.00% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 1 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 1 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev nan # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 1 100.00% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 1 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 4501 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 11626 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 1875 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 12.00 # Average queueing delay per DRAM burst -system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 31.00 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 684.62 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 29.21 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 805.11 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 147.88 # Average system write bandwidth in MiByte/s -system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 5.58 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 5.35 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 0.23 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 21.49 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 302 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 15 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 80.53 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 32.61 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 67.02 # Average gap between requests -system.mem_ctrls.pageHitRate 75.30 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 164220 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 77280 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 1839264 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 2458560.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 2689032 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 56064 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.actPowerDownEnergy 13011960 # Energy for active power-down per rank (pJ) -system.mem_ctrls_0.prePowerDownEnergy 183552 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrls_0.totalEnergy 20479932 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 584.206184 # Core power per rank (mW) -system.mem_ctrls_0.totalIdleTime 29013 # Total Idle time Per DRAM Rank -system.mem_ctrls_0.memoryStateTime::IDLE 34 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 1040 # Time in different power states -system.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::PRE_PDN 478 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 4969 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 28535 # Time in different power states -system.mem_ctrls_1.actEnergy 364140 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 181608 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 2444736 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 133632 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 2458560.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 3405408 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 211968 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.actPowerDownEnergy 12011952 # Energy for active power-down per rank (pJ) -system.mem_ctrls_1.prePowerDownEnergy 266496 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrls_1.totalEnergy 21478500 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 612.691123 # Core power per rank (mW) -system.mem_ctrls_1.totalIdleTime 26306 # Total Idle time Per DRAM Rank -system.mem_ctrls_1.memoryStateTime::IDLE 440 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 1040 # Time in different power states -system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 694 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 6540 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT_PDN 26342 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 35056 # Cumulative time (in ticks) in various power states -system.cpu.clk_domain.clock 1 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 415 # DTB read hits -system.cpu.dtb.read_misses 4 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 419 # DTB read accesses -system.cpu.dtb.write_hits 294 # DTB write hits -system.cpu.dtb.write_misses 4 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 298 # DTB write accesses -system.cpu.dtb.data_hits 709 # DTB hits -system.cpu.dtb.data_misses 8 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 717 # DTB accesses -system.cpu.itb.fetch_hits 2586 # ITB hits -system.cpu.itb.fetch_misses 11 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2597 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 35056 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 35056 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 2577 # Number of instructions committed -system.cpu.committedOps 2577 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses -system.cpu.num_func_calls 140 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls -system.cpu.num_int_insts 2375 # number of integer instructions -system.cpu.num_fp_insts 6 # number of float instructions -system.cpu.num_int_register_reads 2998 # number of times the integer registers were read -system.cpu.num_int_register_writes 1768 # number of times the integer registers were written -system.cpu.num_fp_register_reads 6 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 717 # number of memory refs -system.cpu.num_load_insts 419 # Number of load instructions -system.cpu.num_store_insts 298 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 35056 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 396 # Number of branches fetched -system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction -system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction -system.cpu.op_class::MemWrite 292 11.30% 99.77% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 99.77% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 6 0.23% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 2585 # Class of executed instruction -system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.pwrStateResidencyTicks::UNDEFINED 35056 # Cumulative time (in ticks) in various power states -system.ruby.outstanding_req_hist_seqr::bucket_size 1 -system.ruby.outstanding_req_hist_seqr::max_bucket 9 -system.ruby.outstanding_req_hist_seqr::samples 3295 -system.ruby.outstanding_req_hist_seqr::mean 1 -system.ruby.outstanding_req_hist_seqr::gmean 1 -system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 3295 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist_seqr::total 3295 -system.ruby.latency_hist_seqr::bucket_size 32 -system.ruby.latency_hist_seqr::max_bucket 319 -system.ruby.latency_hist_seqr::samples 3294 -system.ruby.latency_hist_seqr::mean 9.642380 -system.ruby.latency_hist_seqr::gmean 1.819734 -system.ruby.latency_hist_seqr::stdev 23.663336 -system.ruby.latency_hist_seqr | 2910 88.34% 88.34% | 293 8.89% 97.24% | 85 2.58% 99.82% | 2 0.06% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 4 0.12% 100.00% -system.ruby.latency_hist_seqr::total 3294 -system.ruby.hit_latency_hist_seqr::bucket_size 2 -system.ruby.hit_latency_hist_seqr::max_bucket 19 -system.ruby.hit_latency_hist_seqr::samples 2853 -system.ruby.hit_latency_hist_seqr::mean 1.241851 -system.ruby.hit_latency_hist_seqr::gmean 1.059708 -system.ruby.hit_latency_hist_seqr::stdev 1.536503 -system.ruby.hit_latency_hist_seqr | 2784 97.58% 97.58% | 0 0.00% 97.58% | 0 0.00% 97.58% | 0 0.00% 97.58% | 0 0.00% 97.58% | 69 2.42% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist_seqr::total 2853 -system.ruby.miss_latency_hist_seqr::bucket_size 32 -system.ruby.miss_latency_hist_seqr::max_bucket 319 -system.ruby.miss_latency_hist_seqr::samples 441 -system.ruby.miss_latency_hist_seqr::mean 63.988662 -system.ruby.miss_latency_hist_seqr::gmean 60.139666 -system.ruby.miss_latency_hist_seqr::stdev 27.525151 -system.ruby.miss_latency_hist_seqr | 57 12.93% 12.93% | 293 66.44% 79.37% | 85 19.27% 98.64% | 2 0.45% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 4 0.91% 100.00% -system.ruby.miss_latency_hist_seqr::total 441 -system.ruby.Directory.incomplete_times_seqr 440 -system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits -system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses -system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses -system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 35056 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.L1Dcache.demand_hits 469 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 240 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Icache.demand_hits 2315 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Icache.demand_misses 270 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Icache.demand_accesses 2585 # Number of cache demand accesses -system.ruby.l1_cntrl0.L2cache.demand_hits 69 # Number of cache demand hits -system.ruby.l1_cntrl0.L2cache.demand_misses 441 # Number of cache demand misses -system.ruby.l1_cntrl0.L2cache.demand_accesses 510 # Number of cache demand accesses -system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 35056 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 35056 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.fully_busy_cycles 5 # cycles for which number of transistions == max transitions -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 35056 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.percent_links_utilized 4.830129 -system.ruby.network.routers0.msg_count.Request_Control::2 441 -system.ruby.network.routers0.msg_count.Response_Data::4 441 -system.ruby.network.routers0.msg_count.Writeback_Data::5 81 -system.ruby.network.routers0.msg_count.Writeback_Control::2 425 -system.ruby.network.routers0.msg_count.Writeback_Control::3 425 -system.ruby.network.routers0.msg_count.Writeback_Control::5 344 -system.ruby.network.routers0.msg_count.Unblock_Control::5 440 -system.ruby.network.routers0.msg_bytes.Request_Control::2 3528 -system.ruby.network.routers0.msg_bytes.Response_Data::4 31752 -system.ruby.network.routers0.msg_bytes.Writeback_Data::5 5832 -system.ruby.network.routers0.msg_bytes.Writeback_Control::2 3400 -system.ruby.network.routers0.msg_bytes.Writeback_Control::3 3400 -system.ruby.network.routers0.msg_bytes.Writeback_Control::5 2752 -system.ruby.network.routers0.msg_bytes.Unblock_Control::5 3520 -system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 35056 # Cumulative time (in ticks) in various power states -system.ruby.network.routers1.percent_links_utilized 4.830129 -system.ruby.network.routers1.msg_count.Request_Control::2 441 -system.ruby.network.routers1.msg_count.Response_Data::4 441 -system.ruby.network.routers1.msg_count.Writeback_Data::5 81 -system.ruby.network.routers1.msg_count.Writeback_Control::2 425 -system.ruby.network.routers1.msg_count.Writeback_Control::3 425 -system.ruby.network.routers1.msg_count.Writeback_Control::5 344 -system.ruby.network.routers1.msg_count.Unblock_Control::5 440 -system.ruby.network.routers1.msg_bytes.Request_Control::2 3528 -system.ruby.network.routers1.msg_bytes.Response_Data::4 31752 -system.ruby.network.routers1.msg_bytes.Writeback_Data::5 5832 -system.ruby.network.routers1.msg_bytes.Writeback_Control::2 3400 -system.ruby.network.routers1.msg_bytes.Writeback_Control::3 3400 -system.ruby.network.routers1.msg_bytes.Writeback_Control::5 2752 -system.ruby.network.routers1.msg_bytes.Unblock_Control::5 3520 -system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 35056 # Cumulative time (in ticks) in various power states -system.ruby.network.routers2.percent_links_utilized 4.830129 -system.ruby.network.routers2.msg_count.Request_Control::2 441 -system.ruby.network.routers2.msg_count.Response_Data::4 441 -system.ruby.network.routers2.msg_count.Writeback_Data::5 81 -system.ruby.network.routers2.msg_count.Writeback_Control::2 425 -system.ruby.network.routers2.msg_count.Writeback_Control::3 425 -system.ruby.network.routers2.msg_count.Writeback_Control::5 344 -system.ruby.network.routers2.msg_count.Unblock_Control::5 440 -system.ruby.network.routers2.msg_bytes.Request_Control::2 3528 -system.ruby.network.routers2.msg_bytes.Response_Data::4 31752 -system.ruby.network.routers2.msg_bytes.Writeback_Data::5 5832 -system.ruby.network.routers2.msg_bytes.Writeback_Control::2 3400 -system.ruby.network.routers2.msg_bytes.Writeback_Control::3 3400 -system.ruby.network.routers2.msg_bytes.Writeback_Control::5 2752 -system.ruby.network.routers2.msg_bytes.Unblock_Control::5 3520 -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 35056 # Cumulative time (in ticks) in various power states -system.ruby.network.msg_count.Request_Control 1323 -system.ruby.network.msg_count.Response_Data 1323 -system.ruby.network.msg_count.Writeback_Data 243 -system.ruby.network.msg_count.Writeback_Control 3582 -system.ruby.network.msg_count.Unblock_Control 1320 -system.ruby.network.msg_byte.Request_Control 10584 -system.ruby.network.msg_byte.Response_Data 95256 -system.ruby.network.msg_byte.Writeback_Data 17496 -system.ruby.network.msg_byte.Writeback_Control 28656 -system.ruby.network.msg_byte.Unblock_Control 10560 -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 35056 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.throttle0.link_utilization 6.267115 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 441 -system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 425 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 31752 -system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 3400 -system.ruby.network.routers0.throttle1.link_utilization 3.393142 -system.ruby.network.routers0.throttle1.msg_count.Request_Control::2 441 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::5 81 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::2 425 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::5 344 -system.ruby.network.routers0.throttle1.msg_count.Unblock_Control::5 440 -system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::2 3528 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::5 5832 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::2 3400 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::5 2752 -system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::5 3520 -system.ruby.network.routers1.throttle0.link_utilization 3.393142 -system.ruby.network.routers1.throttle0.msg_count.Request_Control::2 441 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::5 81 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::2 425 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::5 344 -system.ruby.network.routers1.throttle0.msg_count.Unblock_Control::5 440 -system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::2 3528 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::5 5832 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::2 3400 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::5 2752 -system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::5 3520 -system.ruby.network.routers1.throttle1.link_utilization 6.267115 -system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 441 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 425 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 31752 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 3400 -system.ruby.network.routers2.throttle0.link_utilization 6.267115 -system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 441 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 425 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 31752 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 3400 -system.ruby.network.routers2.throttle1.link_utilization 3.393142 -system.ruby.network.routers2.throttle1.msg_count.Request_Control::2 441 -system.ruby.network.routers2.throttle1.msg_count.Writeback_Data::5 81 -system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::2 425 -system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::5 344 -system.ruby.network.routers2.throttle1.msg_count.Unblock_Control::5 440 -system.ruby.network.routers2.throttle1.msg_bytes.Request_Control::2 3528 -system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Data::5 5832 -system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::2 3400 -system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::5 2752 -system.ruby.network.routers2.throttle1.msg_bytes.Unblock_Control::5 3520 -system.ruby.LD.latency_hist_seqr::bucket_size 16 -system.ruby.LD.latency_hist_seqr::max_bucket 159 -system.ruby.LD.latency_hist_seqr::samples 415 -system.ruby.LD.latency_hist_seqr::mean 21.354217 -system.ruby.LD.latency_hist_seqr::gmean 4.945859 -system.ruby.LD.latency_hist_seqr::stdev 28.670834 -system.ruby.LD.latency_hist_seqr | 269 64.82% 64.82% | 42 10.12% 74.94% | 3 0.72% 75.66% | 69 16.63% 92.29% | 18 4.34% 96.63% | 14 3.37% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist_seqr::total 415 -system.ruby.LD.hit_latency_hist_seqr::bucket_size 2 -system.ruby.LD.hit_latency_hist_seqr::max_bucket 19 -system.ruby.LD.hit_latency_hist_seqr::samples 269 -system.ruby.LD.hit_latency_hist_seqr::mean 2.338290 -system.ruby.LD.hit_latency_hist_seqr::gmean 1.378379 -system.ruby.LD.hit_latency_hist_seqr::stdev 3.411031 -system.ruby.LD.hit_latency_hist_seqr | 233 86.62% 86.62% | 0 0.00% 86.62% | 0 0.00% 86.62% | 0 0.00% 86.62% | 0 0.00% 86.62% | 36 13.38% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist_seqr::total 269 -system.ruby.LD.miss_latency_hist_seqr::bucket_size 16 -system.ruby.LD.miss_latency_hist_seqr::max_bucket 159 -system.ruby.LD.miss_latency_hist_seqr::samples 146 -system.ruby.LD.miss_latency_hist_seqr::mean 56.390411 -system.ruby.LD.miss_latency_hist_seqr::gmean 52.068669 -system.ruby.LD.miss_latency_hist_seqr::stdev 20.461022 -system.ruby.LD.miss_latency_hist_seqr | 0 0.00% 0.00% | 42 28.77% 28.77% | 3 2.05% 30.82% | 69 47.26% 78.08% | 18 12.33% 90.41% | 14 9.59% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist_seqr::total 146 -system.ruby.ST.latency_hist_seqr::bucket_size 8 -system.ruby.ST.latency_hist_seqr::max_bucket 79 -system.ruby.ST.latency_hist_seqr::samples 294 -system.ruby.ST.latency_hist_seqr::mean 9.778912 -system.ruby.ST.latency_hist_seqr::gmean 2.043604 -system.ruby.ST.latency_hist_seqr::stdev 20.538869 -system.ruby.ST.latency_hist_seqr | 236 80.27% 80.27% | 11 3.74% 84.01% | 0 0.00% 84.01% | 15 5.10% 89.12% | 0 0.00% 89.12% | 0 0.00% 89.12% | 0 0.00% 89.12% | 22 7.48% 96.60% | 5 1.70% 98.30% | 5 1.70% 100.00% -system.ruby.ST.latency_hist_seqr::total 294 -system.ruby.ST.hit_latency_hist_seqr::bucket_size 2 -system.ruby.ST.hit_latency_hist_seqr::max_bucket 19 -system.ruby.ST.hit_latency_hist_seqr::samples 247 -system.ruby.ST.hit_latency_hist_seqr::mean 1.445344 -system.ruby.ST.hit_latency_hist_seqr::gmean 1.112699 -system.ruby.ST.hit_latency_hist_seqr::stdev 2.066980 -system.ruby.ST.hit_latency_hist_seqr | 236 95.55% 95.55% | 0 0.00% 95.55% | 0 0.00% 95.55% | 0 0.00% 95.55% | 0 0.00% 95.55% | 11 4.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist_seqr::total 247 -system.ruby.ST.miss_latency_hist_seqr::bucket_size 8 -system.ruby.ST.miss_latency_hist_seqr::max_bucket 79 -system.ruby.ST.miss_latency_hist_seqr::samples 47 -system.ruby.ST.miss_latency_hist_seqr::mean 53.574468 -system.ruby.ST.miss_latency_hist_seqr::gmean 49.876949 -system.ruby.ST.miss_latency_hist_seqr::stdev 18.206240 -system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 15 31.91% 31.91% | 0 0.00% 31.91% | 0 0.00% 31.91% | 0 0.00% 31.91% | 22 46.81% 78.72% | 5 10.64% 89.36% | 5 10.64% 100.00% -system.ruby.ST.miss_latency_hist_seqr::total 47 -system.ruby.IFETCH.latency_hist_seqr::bucket_size 32 -system.ruby.IFETCH.latency_hist_seqr::max_bucket 319 -system.ruby.IFETCH.latency_hist_seqr::samples 2585 -system.ruby.IFETCH.latency_hist_seqr::mean 7.746615 -system.ruby.IFETCH.latency_hist_seqr::gmean 1.529553 -system.ruby.IFETCH.latency_hist_seqr::stdev 22.548460 -system.ruby.IFETCH.latency_hist_seqr | 2337 90.41% 90.41% | 199 7.70% 98.10% | 43 1.66% 99.77% | 2 0.08% 99.85% | 0 0.00% 99.85% | 0 0.00% 99.85% | 0 0.00% 99.85% | 0 0.00% 99.85% | 0 0.00% 99.85% | 4 0.15% 100.00% -system.ruby.IFETCH.latency_hist_seqr::total 2585 -system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 2 -system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 19 -system.ruby.IFETCH.hit_latency_hist_seqr::samples 2337 -system.ruby.IFETCH.hit_latency_hist_seqr::mean 1.094138 -system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1.022830 -system.ruby.IFETCH.hit_latency_hist_seqr::stdev 0.965875 -system.ruby.IFETCH.hit_latency_hist_seqr | 2315 99.06% 99.06% | 0 0.00% 99.06% | 0 0.00% 99.06% | 0 0.00% 99.06% | 0 0.00% 99.06% | 22 0.94% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist_seqr::total 2337 -system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 32 -system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 319 -system.ruby.IFETCH.miss_latency_hist_seqr::samples 248 -system.ruby.IFETCH.miss_latency_hist_seqr::mean 70.435484 -system.ruby.IFETCH.miss_latency_hist_seqr::gmean 67.827440 -system.ruby.IFETCH.miss_latency_hist_seqr::stdev 30.751253 -system.ruby.IFETCH.miss_latency_hist_seqr | 0 0.00% 0.00% | 199 80.24% 80.24% | 43 17.34% 97.58% | 2 0.81% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 4 1.61% 100.00% -system.ruby.IFETCH.miss_latency_hist_seqr::total 248 -system.ruby.L1Cache.hit_mach_latency_hist_seqr::bucket_size 1 -system.ruby.L1Cache.hit_mach_latency_hist_seqr::max_bucket 9 -system.ruby.L1Cache.hit_mach_latency_hist_seqr::samples 2784 -system.ruby.L1Cache.hit_mach_latency_hist_seqr::mean 1 -system.ruby.L1Cache.hit_mach_latency_hist_seqr::gmean 1 -system.ruby.L1Cache.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 2784 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.hit_mach_latency_hist_seqr::total 2784 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::bucket_size 2 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::max_bucket 19 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::samples 69 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::mean 11 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::gmean 11.000000 -system.ruby.L2Cache.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 69 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L2Cache.hit_mach_latency_hist_seqr::total 69 -system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 32 -system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 319 -system.ruby.Directory.miss_mach_latency_hist_seqr::samples 441 -system.ruby.Directory.miss_mach_latency_hist_seqr::mean 63.988662 -system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 60.139666 -system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 27.525151 -system.ruby.Directory.miss_mach_latency_hist_seqr | 57 12.93% 12.93% | 293 66.44% 79.37% | 85 19.27% 98.64% | 2 0.45% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 4 0.91% 100.00% -system.ruby.Directory.miss_mach_latency_hist_seqr::total 441 -system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 -system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 -system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1 -system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::stdev nan -system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 1 -system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 1 -system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::max_bucket 9 -system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::samples 1 -system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::stdev nan -system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::total 1 -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::bucket_size 8 -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::max_bucket 79 -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::samples 1 -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::mean 75 -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::gmean 75.000000 -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::stdev nan -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total 1 -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size 1 -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 9 -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 1 -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::samples 233 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::mean 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 233 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::total 233 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 2 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 19 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::samples 36 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::mean 11 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::gmean 11.000000 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 36 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::total 36 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 16 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 159 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 146 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 56.390411 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 52.068669 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 20.461022 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 42 28.77% 28.77% | 3 2.05% 30.82% | 69 47.26% 78.08% | 18 12.33% 90.41% | 14 9.59% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 146 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::samples 236 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::mean 1 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 236 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::total 236 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 2 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 19 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::samples 11 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::mean 11 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::gmean 11.000000 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 11 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::total 11 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 8 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 79 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 47 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 53.574468 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 49.876949 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 18.206240 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 15 31.91% 31.91% | 0 0.00% 31.91% | 0 0.00% 31.91% | 0 0.00% 31.91% | 22 46.81% 78.72% | 5 10.64% 89.36% | 5 10.64% 100.00% -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 47 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::samples 2315 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::mean 1 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1 -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 2315 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::total 2315 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 2 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 19 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::samples 22 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::mean 11 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::gmean 11.000000 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 22 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::total 22 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 248 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 70.435484 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 67.827440 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 30.751253 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 199 80.24% 80.24% | 43 17.34% 97.58% | 2 0.81% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 4 1.61% 100.00% -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 248 -system.ruby.Directory_Controller.GETX 51 0.00% 0.00% -system.ruby.Directory_Controller.GETS 410 0.00% 0.00% -system.ruby.Directory_Controller.PUT 425 0.00% 0.00% -system.ruby.Directory_Controller.UnblockM 440 0.00% 0.00% -system.ruby.Directory_Controller.Writeback_Exclusive_Clean 344 0.00% 0.00% -system.ruby.Directory_Controller.Writeback_Exclusive_Dirty 81 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 441 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 81 0.00% 0.00% -system.ruby.Directory_Controller.NO.PUT 425 0.00% 0.00% -system.ruby.Directory_Controller.E.GETX 47 0.00% 0.00% -system.ruby.Directory_Controller.E.GETS 394 0.00% 0.00% -system.ruby.Directory_Controller.NO_B.UnblockM 440 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_W.Memory_Data 441 0.00% 0.00% -system.ruby.Directory_Controller.WB.GETX 4 0.00% 0.00% -system.ruby.Directory_Controller.WB.GETS 14 0.00% 0.00% -system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean 344 0.00% 0.00% -system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty 81 0.00% 0.00% -system.ruby.Directory_Controller.WB_E_W.GETS 2 0.00% 0.00% -system.ruby.Directory_Controller.WB_E_W.Memory_Ack 81 0.00% 0.00% -system.ruby.L1Cache_Controller.Load 422 0.00% 0.00% -system.ruby.L1Cache_Controller.Ifetch 2591 0.00% 0.00% -system.ruby.L1Cache_Controller.Store 298 0.00% 0.00% -system.ruby.L1Cache_Controller.L2_Replacement 425 0.00% 0.00% -system.ruby.L1Cache_Controller.L1_to_L2 502 0.00% 0.00% -system.ruby.L1Cache_Controller.Trigger_L2_to_L1D 47 0.00% 0.00% -system.ruby.L1Cache_Controller.Trigger_L2_to_L1I 22 0.00% 0.00% -system.ruby.L1Cache_Controller.Complete_L2_to_L1 69 0.00% 0.00% -system.ruby.L1Cache_Controller.Exclusive_Data 441 0.00% 0.00% -system.ruby.L1Cache_Controller.Writeback_Ack 425 0.00% 0.00% -system.ruby.L1Cache_Controller.All_acks_no_sharers 441 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Load 146 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Ifetch 248 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Store 47 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Load 109 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Ifetch 2315 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Store 35 0.00% 0.00% -system.ruby.L1Cache_Controller.M.L2_Replacement 344 0.00% 0.00% -system.ruby.L1Cache_Controller.M.L1_to_L2 397 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1D 23 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1I 22 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.Load 124 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.Store 201 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.L2_Replacement 81 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.L1_to_L2 105 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1D 24 0.00% 0.00% -system.ruby.L1Cache_Controller.MR.Load 22 0.00% 0.00% -system.ruby.L1Cache_Controller.MR.Ifetch 22 0.00% 0.00% -system.ruby.L1Cache_Controller.MR.Store 1 0.00% 0.00% -system.ruby.L1Cache_Controller.MMR.Load 14 0.00% 0.00% -system.ruby.L1Cache_Controller.MMR.Store 10 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.Exclusive_Data 47 0.00% 0.00% -system.ruby.L1Cache_Controller.M_W.All_acks_no_sharers 394 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_W.All_acks_no_sharers 47 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Exclusive_Data 394 0.00% 0.00% -system.ruby.L1Cache_Controller.MI.Load 7 0.00% 0.00% -system.ruby.L1Cache_Controller.MI.Ifetch 6 0.00% 0.00% -system.ruby.L1Cache_Controller.MI.Store 4 0.00% 0.00% -system.ruby.L1Cache_Controller.MI.Writeback_Ack 425 0.00% 0.00% -system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1 45 0.00% 0.00% -system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1 24 0.00% 0.00% - ----------- End Simulation Statistics ---------- diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,1266 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000 -time_sync_spin_threshold=100000 - -[system] -type=System -children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges=0:268435455:0:0:0:0 -memories=system.mem_ctrls -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.sys_port_proxy.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=TimingSimpleCPU -children=clk_domain dtb interrupts isa itb tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu.clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1] -icache_port=system.ruby.l1_cntrl0.sequencer.slave[0] - -[system.cpu.clk_domain] -type=SrcClockDomain -clock=1 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=hello -cwd= -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/tru64/hello -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000 - -[system.mem_ctrls] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -page_policy=open_adaptive -power_model=Null -range=0:268435455:5:19:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10 -static_frontend_latency=10 -tBURST=5 -tCCD_L=0 -tCK=1 -tCL=14 -tCS=3 -tRAS=35 -tRCD=14 -tREFI=7800 -tRFC=260 -tRP=14 -tRRD=6 -tRRD_L=0 -tRTP=8 -tRTW=3 -tWR=15 -tWTR=8 -tXAW=30 -tXP=6 -tXPDLL=0 -tXS=270 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.ruby.dir_cntrl0.memory - -[system.ruby] -type=RubySystem -children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network -access_backing_store=false -all_instructions=false -block_size_bytes=64 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hot_lines=false -memory_size_bits=48 -num_of_sequencers=1 -number_of_virtual_networks=5 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -phys_mem=Null -power_model=Null -randomization=false - -[system.ruby.clk_domain] -type=SrcClockDomain -clock=1 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.ruby.dir_cntrl0] -type=Directory_Controller -children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir requestToDir responseFromDir responseFromMemory -buffer_size=0 -clk_domain=system.ruby.clk_domain -cluster_id=0 -default_p_state=UNDEFINED -directory=system.ruby.dir_cntrl0.directory -directory_latency=12 -dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir -dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir -eventq_index=0 -forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir -number_of_TBEs=256 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -recycle_latency=10 -requestToDir=system.ruby.dir_cntrl0.requestToDir -responseFromDir=system.ruby.dir_cntrl0.responseFromDir -responseFromMemory=system.ruby.dir_cntrl0.responseFromMemory -ruby_system=system.ruby -system=system -to_memory_controller_latency=1 -transitions_per_cycle=4 -version=0 -memory=system.mem_ctrls.port - -[system.ruby.dir_cntrl0.directory] -type=RubyDirectoryMemory -eventq_index=0 -numa_high_bit=5 -size=268435456 -version=0 - -[system.ruby.dir_cntrl0.dmaRequestToDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -slave=system.ruby.network.master[3] - -[system.ruby.dir_cntrl0.dmaResponseFromDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -master=system.ruby.network.slave[3] - -[system.ruby.dir_cntrl0.forwardFromDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[4] - -[system.ruby.dir_cntrl0.requestToDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -slave=system.ruby.network.master[2] - -[system.ruby.dir_cntrl0.responseFromDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[2] - -[system.ruby.dir_cntrl0.responseFromMemory] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false - -[system.ruby.l1_cntrl0] -type=L1Cache_Controller -children=cacheMemory forwardToCache mandatoryQueue requestFromCache responseFromCache responseToCache sequencer -buffer_size=0 -cacheMemory=system.ruby.l1_cntrl0.cacheMemory -cache_response_latency=12 -clk_domain=system.cpu.clk_domain -cluster_id=0 -default_p_state=UNDEFINED -eventq_index=0 -forwardToCache=system.ruby.l1_cntrl0.forwardToCache -issue_latency=2 -mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue -number_of_TBEs=256 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -recycle_latency=10 -requestFromCache=system.ruby.l1_cntrl0.requestFromCache -responseFromCache=system.ruby.l1_cntrl0.responseFromCache -responseToCache=system.ruby.l1_cntrl0.responseToCache -ruby_system=system.ruby -send_evictions=false -sequencer=system.ruby.l1_cntrl0.sequencer -system=system -transitions_per_cycle=4 -version=0 - -[system.ruby.l1_cntrl0.cacheMemory] -type=RubyCache -children=replacement_policy -assoc=2 -block_size=0 -dataAccessLatency=1 -dataArrayBanks=1 -eventq_index=0 -is_icache=false -replacement_policy=system.ruby.l1_cntrl0.cacheMemory.replacement_policy -resourceStalls=false -ruby_system=system.ruby -size=256 -start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 - -[system.ruby.l1_cntrl0.cacheMemory.replacement_policy] -type=PseudoLRUReplacementPolicy -assoc=2 -block_size=64 -eventq_index=0 -size=256 - -[system.ruby.l1_cntrl0.forwardToCache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -slave=system.ruby.network.master[0] - -[system.ruby.l1_cntrl0.mandatoryQueue] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false - -[system.ruby.l1_cntrl0.requestFromCache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -master=system.ruby.network.slave[0] - -[system.ruby.l1_cntrl0.responseFromCache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -master=system.ruby.network.slave[1] - -[system.ruby.l1_cntrl0.responseToCache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -slave=system.ruby.network.master[1] - -[system.ruby.l1_cntrl0.sequencer] -type=RubySequencer -clk_domain=system.cpu.clk_domain -coreid=99 -dcache=system.ruby.l1_cntrl0.cacheMemory -dcache_hit_latency=1 -deadlock_threshold=500000 -default_p_state=UNDEFINED -eventq_index=0 -garnet_standalone=false -icache=system.ruby.l1_cntrl0.cacheMemory -icache_hit_latency=1 -is_cpu_sequencer=true -max_outstanding_requests=16 -no_retry_on_stall=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -ruby_system=system.ruby -support_data_reqs=true -support_inst_reqs=true -system=system -using_ruby_tester=false -version=0 -slave=system.cpu.icache_port system.cpu.dcache_port - -[system.ruby.memctrl_clk_domain] -type=DerivedClockDomain -clk_divider=3 -clk_domain=system.ruby.clk_domain -eventq_index=0 - -[system.ruby.network] -type=SimpleNetwork -children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_links0 int_links1 int_links2 int_links3 routers0 routers1 routers2 -adaptive_routing=false -buffer_size=0 -clk_domain=system.ruby.clk_domain -control_msg_size=8 -default_p_state=UNDEFINED -endpoint_bandwidth=1000 -eventq_index=0 -ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 -int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 -int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 -netifs= -number_of_virtual_networks=5 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 -ruby_system=system.ruby -topology=Crossbar -master=system.ruby.l1_cntrl0.forwardToCache.slave system.ruby.l1_cntrl0.responseToCache.slave system.ruby.dir_cntrl0.requestToDir.slave system.ruby.dir_cntrl0.dmaRequestToDir.slave -slave=system.ruby.l1_cntrl0.requestFromCache.master system.ruby.l1_cntrl0.responseFromCache.master system.ruby.dir_cntrl0.responseFromDir.master system.ruby.dir_cntrl0.dmaResponseFromDir.master system.ruby.dir_cntrl0.forwardFromDir.master - -[system.ruby.network.ext_links0] -type=SimpleExtLink -bandwidth_factor=16 -eventq_index=0 -ext_node=system.ruby.l1_cntrl0 -int_node=system.ruby.network.routers0 -latency=1 -link_id=0 -weight=1 - -[system.ruby.network.ext_links1] -type=SimpleExtLink -bandwidth_factor=16 -eventq_index=0 -ext_node=system.ruby.dir_cntrl0 -int_node=system.ruby.network.routers1 -latency=1 -link_id=1 -weight=1 - -[system.ruby.network.int_link_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers15] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers16] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers17] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers18] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers19] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers20] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers21] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers22] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers23] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers24] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers25] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers26] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers27] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers28] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers29] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers30] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers31] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers32] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers33] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers34] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers35] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers36] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers37] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers38] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers39] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_links0] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers2 -eventq_index=0 -latency=1 -link_id=2 -src_node=system.ruby.network.routers0 -src_outport= -weight=1 - -[system.ruby.network.int_links1] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers2 -eventq_index=0 -latency=1 -link_id=3 -src_node=system.ruby.network.routers1 -src_outport= -weight=1 - -[system.ruby.network.int_links2] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers0 -eventq_index=0 -latency=1 -link_id=4 -src_node=system.ruby.network.routers2 -src_outport= -weight=1 - -[system.ruby.network.int_links3] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers1 -eventq_index=0 -latency=1 -link_id=5 -src_node=system.ruby.network.routers2 -src_outport= -weight=1 - -[system.ruby.network.routers0] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 system.ruby.network.routers0.port_buffers12 system.ruby.network.routers0.port_buffers13 system.ruby.network.routers0.port_buffers14 -power_model=Null -router_id=0 -virt_nets=5 - -[system.ruby.network.routers0.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 system.ruby.network.routers1.port_buffers12 system.ruby.network.routers1.port_buffers13 system.ruby.network.routers1.port_buffers14 -power_model=Null -router_id=1 -virt_nets=5 - -[system.ruby.network.routers1.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19 -power_model=Null -router_id=2 -virt_nets=5 - -[system.ruby.network.routers2.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers15] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers16] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers17] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers18] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers19] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.sys_port_proxy] -type=RubyPortProxy -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_cpu_sequencer=true -no_retry_on_stall=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -ruby_system=system.ruby -support_data_reqs=true -support_inst_reqs=true -system=system -using_ruby_tester=false -version=0 -slave=system.system_port - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,11 +0,0 @@ -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! -warn: ignoring syscall sigprocmask(1, ...) diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,15 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:19:46 -gem5 executing on e108600-lin, pid 28078 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/tru64/simple-timing-ruby - -Global frequency set at 1000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Hello world! -Exiting @ tick 43520 because target called exit() diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,654 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000044 # Number of seconds simulated -sim_ticks 43520 # Number of ticks simulated -final_tick 43520 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 112756 # Simulator instruction rate (inst/s) -host_op_rate 112704 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1902499 # Simulator tick rate (ticks/s) -host_mem_usage 412460 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -sim_insts 2577 # Number of instructions simulated -sim_ops 2577 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 43520 # Cumulative time (in ticks) in various power states -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 40064 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 40064 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 39808 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 39808 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 626 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 626 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 622 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 622 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 920588235 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 920588235 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 914705882 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 914705882 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 1835294118 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 1835294118 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 626 # Number of read requests accepted -system.mem_ctrls.writeReqs 622 # Number of write requests accepted -system.mem_ctrls.readBursts 626 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 622 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 24512 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 15552 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 23424 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 40064 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 39808 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 243 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 231 # Number of DRAM write bursts merged with an existing one -system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 1 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 1 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 30 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 24 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 53 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 53 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 68 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::9 5 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 25 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 14 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 30 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 68 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 10 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 1 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 1 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 1 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 32 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 23 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 48 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 43 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::8 68 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 5 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 23 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 15 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 31 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 65 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 10 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::15 1 # Per bank write bursts -system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 43487 # Total gap between requests -system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 626 # Read request sizes (log2) -system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 622 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 383 # What read queue length does an incoming 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does an incoming req see -system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 113 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 404.389381 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 273.588270 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 327.373952 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 20 17.70% 17.70% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 26 23.01% 40.71% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 16 14.16% 54.87% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 15 13.27% 68.14% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 5 4.42% 72.57% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 6 5.31% 77.88% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 8 7.08% 84.96% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 5 4.42% 89.38% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 12 10.62% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 113 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 22 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 17 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 16.662586 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 4.253850 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::14-15 8 36.36% 36.36% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-17 8 36.36% 72.73% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::18-19 5 22.73% 95.45% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::34-35 1 4.55% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 22 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 22 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.636364 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.596436 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 1.216766 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 17 77.27% 77.27% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 1 4.55% 81.82% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 4 18.18% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 22 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 6435 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 13712 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 1915 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 16.80 # Average queueing delay per DRAM burst -system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 35.80 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 563.24 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 538.24 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 920.59 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 914.71 # Average system write bandwidth in MiByte/s -system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 8.61 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 4.40 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 4.20 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 24.70 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 286 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 342 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 74.67 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 87.47 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 34.85 # Average gap between requests -system.mem_ctrls.pageHitRate 81.14 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 264180 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 127512 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 1850688 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 1236096 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 3073200.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 3917040 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 69120 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.actPowerDownEnergy 15256848 # Energy for active power-down per rank (pJ) -system.mem_ctrls_0.prePowerDownEnergy 496128 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrls_0.totalEnergy 26290812 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 604.108732 # Core power per rank (mW) -system.mem_ctrls_0.totalIdleTime 34684 # Total Idle time Per DRAM Rank -system.mem_ctrls_0.memoryStateTime::IDLE 40 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 1300 # Time in different power states -system.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::PRE_PDN 1292 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 7430 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 33458 # Time in different power states -system.mem_ctrls_1.actEnergy 599760 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 309120 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 2524704 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 1820736 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 3073200.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 5746968 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 231168 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.actPowerDownEnergy 13781232 # Energy for active power-down per rank (pJ) -system.mem_ctrls_1.prePowerDownEnergy 35712 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrls_1.totalEnergy 28122600 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 646.199449 # Core power per rank (mW) -system.mem_ctrls_1.totalIdleTime 29649 # Total Idle time Per DRAM Rank -system.mem_ctrls_1.memoryStateTime::IDLE 448 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 1300 # Time in different power states -system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 93 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 11457 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT_PDN 30222 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 43520 # Cumulative time (in ticks) in various power states -system.cpu.clk_domain.clock 1 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 415 # DTB read hits -system.cpu.dtb.read_misses 4 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 419 # DTB read accesses -system.cpu.dtb.write_hits 294 # DTB write hits -system.cpu.dtb.write_misses 4 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 298 # DTB write accesses -system.cpu.dtb.data_hits 709 # DTB hits -system.cpu.dtb.data_misses 8 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 717 # DTB accesses -system.cpu.itb.fetch_hits 2586 # ITB hits -system.cpu.itb.fetch_misses 11 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2597 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 43520 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 43520 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 2577 # Number of instructions committed -system.cpu.committedOps 2577 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses -system.cpu.num_func_calls 140 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls -system.cpu.num_int_insts 2375 # number of integer instructions -system.cpu.num_fp_insts 6 # number of float instructions -system.cpu.num_int_register_reads 2998 # number of times the integer registers were read -system.cpu.num_int_register_writes 1768 # number of times the integer registers were written -system.cpu.num_fp_register_reads 6 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 717 # number of memory refs -system.cpu.num_load_insts 419 # Number of load instructions -system.cpu.num_store_insts 298 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 43520 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 396 # Number of branches fetched -system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction -system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction -system.cpu.op_class::MemWrite 292 11.30% 99.77% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 99.77% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 6 0.23% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 2585 # Class of executed instruction -system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.pwrStateResidencyTicks::UNDEFINED 43520 # Cumulative time (in ticks) in various power states -system.ruby.delayHist::bucket_size 1 # delay histogram for all message -system.ruby.delayHist::max_bucket 9 # delay histogram for all message -system.ruby.delayHist::samples 1248 # delay histogram for all message -system.ruby.delayHist | 1248 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 1248 # delay histogram for all message -system.ruby.outstanding_req_hist_seqr::bucket_size 1 -system.ruby.outstanding_req_hist_seqr::max_bucket 9 -system.ruby.outstanding_req_hist_seqr::samples 3295 -system.ruby.outstanding_req_hist_seqr::mean 1 -system.ruby.outstanding_req_hist_seqr::gmean 1 -system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 3295 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist_seqr::total 3295 -system.ruby.latency_hist_seqr::bucket_size 64 -system.ruby.latency_hist_seqr::max_bucket 639 -system.ruby.latency_hist_seqr::samples 3294 -system.ruby.latency_hist_seqr::mean 12.211900 -system.ruby.latency_hist_seqr::gmean 2.131468 -system.ruby.latency_hist_seqr::stdev 27.594720 -system.ruby.latency_hist_seqr | 2924 88.77% 88.77% | 353 10.72% 99.48% | 12 0.36% 99.85% | 0 0.00% 99.85% | 2 0.06% 99.91% | 3 0.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist_seqr::total 3294 -system.ruby.hit_latency_hist_seqr::bucket_size 1 -system.ruby.hit_latency_hist_seqr::max_bucket 9 -system.ruby.hit_latency_hist_seqr::samples 2668 -system.ruby.hit_latency_hist_seqr::mean 1 -system.ruby.hit_latency_hist_seqr::gmean 1 -system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 2668 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist_seqr::total 2668 -system.ruby.miss_latency_hist_seqr::bucket_size 64 -system.ruby.miss_latency_hist_seqr::max_bucket 639 -system.ruby.miss_latency_hist_seqr::samples 626 -system.ruby.miss_latency_hist_seqr::mean 59.996805 -system.ruby.miss_latency_hist_seqr::gmean 53.641558 -system.ruby.miss_latency_hist_seqr::stdev 34.472574 -system.ruby.miss_latency_hist_seqr | 256 40.89% 40.89% | 353 56.39% 97.28% | 12 1.92% 99.20% | 0 0.00% 99.20% | 2 0.32% 99.52% | 3 0.48% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist_seqr::total 626 -system.ruby.Directory.incomplete_times_seqr 625 -system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 43520 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.cacheMemory.demand_hits 2668 # Number of cache demand hits -system.ruby.l1_cntrl0.cacheMemory.demand_misses 626 # Number of cache demand misses -system.ruby.l1_cntrl0.cacheMemory.demand_accesses 3294 # Number of cache demand accesses -system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 43520 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 43520 # Cumulative time (in ticks) in various power states -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 43520 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.percent_links_utilized 7.169118 -system.ruby.network.routers0.msg_count.Control::2 626 -system.ruby.network.routers0.msg_count.Data::2 622 -system.ruby.network.routers0.msg_count.Response_Data::4 626 -system.ruby.network.routers0.msg_count.Writeback_Control::3 622 -system.ruby.network.routers0.msg_bytes.Control::2 5008 -system.ruby.network.routers0.msg_bytes.Data::2 44784 -system.ruby.network.routers0.msg_bytes.Response_Data::4 45072 -system.ruby.network.routers0.msg_bytes.Writeback_Control::3 4976 -system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 43520 # Cumulative time (in ticks) in various power states -system.ruby.network.routers1.percent_links_utilized 7.169118 -system.ruby.network.routers1.msg_count.Control::2 626 -system.ruby.network.routers1.msg_count.Data::2 622 -system.ruby.network.routers1.msg_count.Response_Data::4 626 -system.ruby.network.routers1.msg_count.Writeback_Control::3 622 -system.ruby.network.routers1.msg_bytes.Control::2 5008 -system.ruby.network.routers1.msg_bytes.Data::2 44784 -system.ruby.network.routers1.msg_bytes.Response_Data::4 45072 -system.ruby.network.routers1.msg_bytes.Writeback_Control::3 4976 -system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 43520 # Cumulative time (in ticks) in various power states -system.ruby.network.routers2.percent_links_utilized 7.169118 -system.ruby.network.routers2.msg_count.Control::2 626 -system.ruby.network.routers2.msg_count.Data::2 622 -system.ruby.network.routers2.msg_count.Response_Data::4 626 -system.ruby.network.routers2.msg_count.Writeback_Control::3 622 -system.ruby.network.routers2.msg_bytes.Control::2 5008 -system.ruby.network.routers2.msg_bytes.Data::2 44784 -system.ruby.network.routers2.msg_bytes.Response_Data::4 45072 -system.ruby.network.routers2.msg_bytes.Writeback_Control::3 4976 -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 43520 # Cumulative time (in ticks) in various power states -system.ruby.network.msg_count.Control 1878 -system.ruby.network.msg_count.Data 1866 -system.ruby.network.msg_count.Response_Data 1878 -system.ruby.network.msg_count.Writeback_Control 1866 -system.ruby.network.msg_byte.Control 15024 -system.ruby.network.msg_byte.Data 134352 -system.ruby.network.msg_byte.Response_Data 135216 -system.ruby.network.msg_byte.Writeback_Control 14928 -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 43520 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.throttle0.link_utilization 7.187500 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 626 -system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 622 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 45072 -system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 4976 -system.ruby.network.routers0.throttle1.link_utilization 7.150735 -system.ruby.network.routers0.throttle1.msg_count.Control::2 626 -system.ruby.network.routers0.throttle1.msg_count.Data::2 622 -system.ruby.network.routers0.throttle1.msg_bytes.Control::2 5008 -system.ruby.network.routers0.throttle1.msg_bytes.Data::2 44784 -system.ruby.network.routers1.throttle0.link_utilization 7.150735 -system.ruby.network.routers1.throttle0.msg_count.Control::2 626 -system.ruby.network.routers1.throttle0.msg_count.Data::2 622 -system.ruby.network.routers1.throttle0.msg_bytes.Control::2 5008 -system.ruby.network.routers1.throttle0.msg_bytes.Data::2 44784 -system.ruby.network.routers1.throttle1.link_utilization 7.187500 -system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 626 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 622 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 45072 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 4976 -system.ruby.network.routers2.throttle0.link_utilization 7.187500 -system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 626 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 622 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 45072 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 4976 -system.ruby.network.routers2.throttle1.link_utilization 7.150735 -system.ruby.network.routers2.throttle1.msg_count.Control::2 626 -system.ruby.network.routers2.throttle1.msg_count.Data::2 622 -system.ruby.network.routers2.throttle1.msg_bytes.Control::2 5008 -system.ruby.network.routers2.throttle1.msg_bytes.Data::2 44784 -system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::samples 626 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1 | 626 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::total 626 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::samples 622 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2 | 622 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::total 622 # delay histogram for vnet_2 -system.ruby.LD.latency_hist_seqr::bucket_size 64 -system.ruby.LD.latency_hist_seqr::max_bucket 639 -system.ruby.LD.latency_hist_seqr::samples 415 -system.ruby.LD.latency_hist_seqr::mean 33.354217 -system.ruby.LD.latency_hist_seqr::gmean 9.992707 -system.ruby.LD.latency_hist_seqr::stdev 38.395820 -system.ruby.LD.latency_hist_seqr | 297 71.57% 71.57% | 114 27.47% 99.04% | 2 0.48% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 2 0.48% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist_seqr::total 415 -system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 -system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 -system.ruby.LD.hit_latency_hist_seqr::samples 170 -system.ruby.LD.hit_latency_hist_seqr::mean 1 -system.ruby.LD.hit_latency_hist_seqr::gmean 1 -system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 170 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist_seqr::total 170 -system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 -system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 -system.ruby.LD.miss_latency_hist_seqr::samples 245 -system.ruby.LD.miss_latency_hist_seqr::mean 55.804082 -system.ruby.LD.miss_latency_hist_seqr::gmean 49.356103 -system.ruby.LD.miss_latency_hist_seqr::stdev 35.580698 -system.ruby.LD.miss_latency_hist_seqr | 127 51.84% 51.84% | 114 46.53% 98.37% | 2 0.82% 99.18% | 0 0.00% 99.18% | 0 0.00% 99.18% | 2 0.82% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist_seqr::total 245 -system.ruby.ST.latency_hist_seqr::bucket_size 32 -system.ruby.ST.latency_hist_seqr::max_bucket 319 -system.ruby.ST.latency_hist_seqr::samples 294 -system.ruby.ST.latency_hist_seqr::mean 16.173469 -system.ruby.ST.latency_hist_seqr::gmean 3.033104 -system.ruby.ST.latency_hist_seqr::stdev 28.208400 -system.ruby.ST.latency_hist_seqr | 210 71.43% 71.43% | 44 14.97% 86.39% | 36 12.24% 98.64% | 1 0.34% 98.98% | 2 0.68% 99.66% | 1 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist_seqr::total 294 -system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 -system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 -system.ruby.ST.hit_latency_hist_seqr::samples 210 -system.ruby.ST.hit_latency_hist_seqr::mean 1 -system.ruby.ST.hit_latency_hist_seqr::gmean 1 -system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 210 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist_seqr::total 210 -system.ruby.ST.miss_latency_hist_seqr::bucket_size 32 -system.ruby.ST.miss_latency_hist_seqr::max_bucket 319 -system.ruby.ST.miss_latency_hist_seqr::samples 84 -system.ruby.ST.miss_latency_hist_seqr::mean 54.107143 -system.ruby.ST.miss_latency_hist_seqr::gmean 48.596564 -system.ruby.ST.miss_latency_hist_seqr::stdev 27.751487 -system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 44 52.38% 52.38% | 36 42.86% 95.24% | 1 1.19% 96.43% | 2 2.38% 98.81% | 1 1.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist_seqr::total 84 -system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 -system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.latency_hist_seqr::samples 2585 -system.ruby.IFETCH.latency_hist_seqr::mean 8.367118 -system.ruby.IFETCH.latency_hist_seqr::gmean 1.597827 -system.ruby.IFETCH.latency_hist_seqr::stdev 23.571466 -system.ruby.IFETCH.latency_hist_seqr | 2373 91.80% 91.80% | 202 7.81% 99.61% | 7 0.27% 99.88% | 0 0.00% 99.88% | 2 0.08% 99.96% | 1 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist_seqr::total 2585 -system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 -system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 -system.ruby.IFETCH.hit_latency_hist_seqr::samples 2288 -system.ruby.IFETCH.hit_latency_hist_seqr::mean 1 -system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 -system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 2288 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist_seqr::total 2288 -system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 -system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.miss_latency_hist_seqr::samples 297 -system.ruby.IFETCH.miss_latency_hist_seqr::mean 65.121212 -system.ruby.IFETCH.miss_latency_hist_seqr::gmean 59.083052 -system.ruby.IFETCH.miss_latency_hist_seqr::stdev 34.625488 -system.ruby.IFETCH.miss_latency_hist_seqr | 85 28.62% 28.62% | 202 68.01% 96.63% | 7 2.36% 98.99% | 0 0.00% 98.99% | 2 0.67% 99.66% | 1 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.miss_latency_hist_seqr::total 297 -system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 -system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 -system.ruby.Directory.miss_mach_latency_hist_seqr::samples 626 -system.ruby.Directory.miss_mach_latency_hist_seqr::mean 59.996805 -system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 53.641558 -system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 34.472574 -system.ruby.Directory.miss_mach_latency_hist_seqr | 256 40.89% 40.89% | 353 56.39% 97.28% | 12 1.92% 99.20% | 0 0.00% 99.20% | 2 0.32% 99.52% | 3 0.48% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_mach_latency_hist_seqr::total 626 -system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 -system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 -system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1 -system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::stdev nan -system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 1 -system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 1 -system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::max_bucket 9 -system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::samples 1 -system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::stdev nan -system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::total 1 -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::bucket_size 1 -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::max_bucket 9 -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::samples 1 -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::stdev nan -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total 1 -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size 8 -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 79 -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 1 -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean 75 -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 75.000000 -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% -system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 245 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 55.804082 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 49.356103 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 35.580698 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 127 51.84% 51.84% | 114 46.53% 98.37% | 2 0.82% 99.18% | 0 0.00% 99.18% | 0 0.00% 99.18% | 2 0.82% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 245 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 84 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 54.107143 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 48.596564 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 27.751487 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 44 52.38% 52.38% | 36 42.86% 95.24% | 1 1.19% 96.43% | 2 2.38% 98.81% | 1 1.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 84 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 297 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 65.121212 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 59.083052 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 34.625488 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 85 28.62% 28.62% | 202 68.01% 96.63% | 7 2.36% 98.99% | 0 0.00% 98.99% | 2 0.67% 99.66% | 1 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 297 -system.ruby.Directory_Controller.GETX 626 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 622 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 626 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 622 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 626 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 622 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 626 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 622 0.00% 0.00% -system.ruby.L1Cache_Controller.Load 415 0.00% 0.00% -system.ruby.L1Cache_Controller.Ifetch 2585 0.00% 0.00% -system.ruby.L1Cache_Controller.Store 294 0.00% 0.00% -system.ruby.L1Cache_Controller.Data 626 0.00% 0.00% -system.ruby.L1Cache_Controller.Replacement 622 0.00% 0.00% -system.ruby.L1Cache_Controller.Writeback_Ack 622 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Load 245 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Ifetch 297 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Store 84 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Load 170 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Ifetch 2288 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Store 210 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Replacement 622 0.00% 0.00% -system.ruby.L1Cache_Controller.MI.Writeback_Ack 622 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Data 542 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.Data 84 0.00% 0.00% - ----------- End Simulation Statistics ---------- diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,366 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=hello -cwd= -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/tru64/hello -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=Null -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=0:134217727 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simerr --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simerr Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,3 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: ignoring syscall sigprocmask(1, ...) diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,15 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 19 2016 12:24:23 -gem5 executing on e108600-lin, pid 39547 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/tru64/simple-timing - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Hello world! -Exiting @ tick 18239500 because target called exit() diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,519 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000018 # Number of seconds simulated -sim_ticks 18484500 # Number of ticks simulated -final_tick 18484500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 287292 # Simulator instruction rate (inst/s) -host_op_rate 286342 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2049000197 # Simulator tick rate (ticks/s) -host_mem_usage 250420 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -sim_insts 2577 # Number of instructions simulated -sim_ops 2577 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 18484500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 10432 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 5248 # Number of bytes read from this memory -system.physmem.bytes_read::total 15680 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 10432 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 10432 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 163 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 82 # Number of read requests responded to by this memory -system.physmem.num_reads::total 245 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 564364738 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 283913549 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 848278287 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 564364738 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 564364738 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 564364738 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 283913549 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 848278287 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 18484500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 415 # DTB read hits -system.cpu.dtb.read_misses 4 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 419 # DTB read accesses -system.cpu.dtb.write_hits 294 # DTB write hits -system.cpu.dtb.write_misses 4 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 298 # DTB write accesses -system.cpu.dtb.data_hits 709 # DTB hits -system.cpu.dtb.data_misses 8 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 717 # DTB accesses -system.cpu.itb.fetch_hits 2586 # ITB hits -system.cpu.itb.fetch_misses 11 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2597 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 18484500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 36969 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 2577 # Number of instructions committed -system.cpu.committedOps 2577 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses -system.cpu.num_func_calls 140 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls -system.cpu.num_int_insts 2375 # number of integer instructions -system.cpu.num_fp_insts 6 # number of float instructions -system.cpu.num_int_register_reads 2998 # number of times the integer registers were read -system.cpu.num_int_register_writes 1768 # number of times the integer registers were written -system.cpu.num_fp_register_reads 6 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 717 # number of memory refs -system.cpu.num_load_insts 419 # Number of load instructions -system.cpu.num_store_insts 298 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 36969 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 396 # Number of branches fetched -system.cpu.op_class::No_OpClass 189 7.31% 7.31% # Class of executed instruction -system.cpu.op_class::IntAlu 1678 64.91% 72.22% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.04% 72.26% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 72.26% # Class of executed instruction -system.cpu.op_class::MemRead 419 16.21% 88.47% # Class of executed instruction -system.cpu.op_class::MemWrite 292 11.30% 99.77% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 99.77% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 6 0.23% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 2585 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 18484500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 47.258408 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 627 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 82 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 7.646341 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 47.258408 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.011538 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011538 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 82 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 49 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.020020 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1500 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1500 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 18484500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 360 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 360 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 267 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 267 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 627 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 627 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 627 # number of overall hits -system.cpu.dcache.overall_hits::total 627 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 27 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 27 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 82 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 82 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 82 # number of overall misses -system.cpu.dcache.overall_misses::total 82 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3465000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3465000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1701000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1701000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 5166000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 5166000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 5166000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 5166000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 415 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 415 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 709 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 709 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 709 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 709 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.132530 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.132530 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.091837 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.091837 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.115656 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.115656 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.115656 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.115656 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 27 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 27 # number of WriteReq MSHR misses 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rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50503.067485 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50503.067485 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50503.067485 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50502.040816 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50503.067485 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50502.040816 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 245 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 18484500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 218 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 27 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 163 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 55 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 326 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 164 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 490 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10432 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5248 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 15680 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 245 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 245 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 245 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 122500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 244500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 123000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 245 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 18484500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 218 # Transaction distribution -system.membus.trans_dist::ReadExReq 27 # Transaction distribution -system.membus.trans_dist::ReadExResp 27 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 218 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 490 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 490 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15680 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15680 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 245 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 245 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 245 # Request fanout histogram -system.membus.reqLayer0.occupancy 245500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 1225000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 6.6 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,857 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=true -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=DerivO3CPU -children=branchPred dcache dtb fuPool icache interrupts0 interrupts1 isa0 isa1 itb l2cache toL2Bus tracer workload0 workload1 -LFSTSize=1024 -LQEntries=32 -LSQCheckLoads=true -LSQDepCheckShift=4 -SQEntries=32 -SSITSize=1024 -activity=0 -backComSize=5 -branchPred=system.cpu.branchPred -cachePorts=200 -checker=Null -clk_domain=system.cpu_clk_domain -commitToDecodeDelay=1 -commitToFetchDelay=1 -commitToIEWDelay=1 -commitToRenameDelay=1 -commitWidth=8 -cpu_id=0 -decodeToFetchDelay=1 -decodeToRenameDelay=1 -decodeWidth=8 -default_p_state=UNDEFINED -dispatchWidth=8 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -fetchBufferSize=64 -fetchQueueSize=32 -fetchToDecodeDelay=1 -fetchTrapLatency=1 -fetchWidth=8 -forwardComSize=5 -fuPool=system.cpu.fuPool -function_trace=false -function_trace_start=0 -iewToCommitDelay=1 -iewToDecodeDelay=1 -iewToFetchDelay=1 -iewToRenameDelay=1 -interrupts=system.cpu.interrupts0 system.cpu.interrupts1 -isa=system.cpu.isa0 system.cpu.isa1 -issueToExecuteDelay=1 -issueWidth=8 -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -needsTSO=false -numIQEntries=64 -numPhysCCRegs=0 -numPhysFloatRegs=256 -numPhysIntRegs=256 -numROBEntries=192 -numRobs=1 -numThreads=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -renameToDecodeDelay=1 -renameToFetchDelay=1 -renameToIEWDelay=2 -renameToROBDelay=1 -renameWidth=8 -simpoint_start_insts= -smtCommitPolicy=RoundRobin -smtFetchPolicy=SingleThread -smtIQPolicy=Partitioned -smtIQThreshold=100 -smtLSQPolicy=Partitioned -smtLSQThreshold=100 -smtNumFetchingThreads=1 -smtROBPolicy=Partitioned -smtROBThreshold=100 -socket_id=0 -squashWidth=8 -store_set_clear_period=250000 -switched_out=false -system=system -tracer=system.cpu.tracer -trapLatency=13 -wbWidth=8 -workload=system.cpu.workload0 system.cpu.workload1 -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.branchPred] -type=TournamentBP -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -indirectHashGHR=true -indirectHashTargets=true -indirectPathLength=3 -indirectSets=256 -indirectTagSize=16 -indirectWays=2 -instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=2 -useIndirect=true - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.fuPool] -type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 -eventq_index=0 - -[system.cpu.fuPool.FUList0] -type=FUDesc -children=opList -count=6 -eventq_index=0 -opList=system.cpu.fuPool.FUList0.opList - -[system.cpu.fuPool.FUList0.opList] -type=OpDesc -eventq_index=0 -opClass=IntAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList1] -type=FUDesc -children=opList0 opList1 -count=2 -eventq_index=0 -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -eventq_index=0 -opClass=IntMult -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -eventq_index=0 -opClass=IntDiv -opLat=20 -pipelined=false - -[system.cpu.fuPool.FUList2] -type=FUDesc -children=opList0 opList1 opList2 -count=4 -eventq_index=0 -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -eventq_index=0 -opClass=FloatAdd -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -eventq_index=0 -opClass=FloatCmp -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -eventq_index=0 -opClass=FloatCvt -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList3] -type=FUDesc -children=opList0 opList1 opList2 -count=2 -eventq_index=0 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -eventq_index=0 -opClass=FloatMult -opLat=4 -pipelined=true - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -eventq_index=0 -opClass=FloatDiv -opLat=12 -pipelined=false - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -eventq_index=0 -opClass=FloatSqrt -opLat=24 -pipelined=false - -[system.cpu.fuPool.FUList4] -type=FUDesc -children=opList -count=0 -eventq_index=0 -opList=system.cpu.fuPool.FUList4.opList - -[system.cpu.fuPool.FUList4.opList] -type=OpDesc -eventq_index=0 -opClass=MemRead -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5] -type=FUDesc -children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 -count=4 -eventq_index=0 -opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 - -[system.cpu.fuPool.FUList5.opList00] -type=OpDesc -eventq_index=0 -opClass=SimdAdd -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList01] -type=OpDesc -eventq_index=0 -opClass=SimdAddAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList02] -type=OpDesc -eventq_index=0 -opClass=SimdAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList03] -type=OpDesc -eventq_index=0 -opClass=SimdCmp -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList04] -type=OpDesc -eventq_index=0 -opClass=SimdCvt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList05] -type=OpDesc -eventq_index=0 -opClass=SimdMisc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList06] -type=OpDesc -eventq_index=0 -opClass=SimdMult -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList07] -type=OpDesc -eventq_index=0 -opClass=SimdMultAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList08] -type=OpDesc -eventq_index=0 -opClass=SimdShift -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList09] -type=OpDesc -eventq_index=0 -opClass=SimdShiftAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList10] -type=OpDesc -eventq_index=0 -opClass=SimdSqrt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList11] -type=OpDesc -eventq_index=0 -opClass=SimdFloatAdd -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList12] -type=OpDesc -eventq_index=0 -opClass=SimdFloatAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList13] -type=OpDesc -eventq_index=0 -opClass=SimdFloatCmp -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList14] -type=OpDesc -eventq_index=0 -opClass=SimdFloatCvt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList15] -type=OpDesc -eventq_index=0 -opClass=SimdFloatDiv -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList16] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMisc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList17] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMult -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList18] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMultAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList19] -type=OpDesc -eventq_index=0 -opClass=SimdFloatSqrt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList6] -type=FUDesc -children=opList -count=0 -eventq_index=0 -opList=system.cpu.fuPool.FUList6.opList - -[system.cpu.fuPool.FUList6.opList] -type=OpDesc -eventq_index=0 -opClass=MemWrite -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList7] -type=FUDesc -children=opList0 opList1 -count=4 -eventq_index=0 -opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -eventq_index=0 -opClass=MemRead -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList7.opList1] -type=OpDesc -eventq_index=0 -opClass=MemWrite -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList8] -type=FUDesc -children=opList -count=1 -eventq_index=0 -opList=system.cpu.fuPool.FUList8.opList - -[system.cpu.fuPool.FUList8.opList] -type=OpDesc -eventq_index=0 -opClass=IprAccess -opLat=3 -pipelined=false - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 - -[system.cpu.interrupts0] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.interrupts1] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa0] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.isa1] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload0] -type=LiveProcess -cmd=hello -cwd= -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/linux/hello -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu.workload1] -type=LiveProcess -cmd=hello -cwd= -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/linux/hello -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=0:134217727:0:0:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=6000 -tXPDLL=0 -tXS=270000 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simerr --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simerr Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,4 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: ClockedObject: Already in the requested power state, request ignored diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,17 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:19:48 -gem5 executing on e108600-lin, pid 28095 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -info: Increasing stack size by one page. -Hello world! -Hello world! -Exiting @ tick 26661500 because target called exit() diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,1185 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000027 # Number of seconds simulated -sim_ticks 26661500 # Number of ticks simulated -final_tick 26661500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 139098 # Simulator instruction rate (inst/s) -host_op_rate 139080 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 290337480 # Simulator tick rate (ticks/s) -host_mem_usage 255644 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host -sim_insts 12770 # Number of instructions simulated -sim_ops 12770 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 40000 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 21888 # Number of bytes read from this memory -system.physmem.bytes_read::total 61888 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 40000 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 40000 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 625 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 342 # Number of read requests responded to by this memory -system.physmem.num_reads::total 967 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1500290681 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 820959061 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2321249742 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1500290681 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1500290681 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1500290681 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 820959061 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2321249742 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 968 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 968 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 61952 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 61952 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 84 # Per bank write bursts -system.physmem.perBankRdBursts::1 150 # Per bank write bursts -system.physmem.perBankRdBursts::2 77 # Per bank write bursts -system.physmem.perBankRdBursts::3 58 # Per bank write bursts -system.physmem.perBankRdBursts::4 90 # Per bank write bursts -system.physmem.perBankRdBursts::5 45 # Per bank write bursts -system.physmem.perBankRdBursts::6 33 # Per bank write bursts -system.physmem.perBankRdBursts::7 50 # Per bank write bursts -system.physmem.perBankRdBursts::8 42 # Per bank write bursts -system.physmem.perBankRdBursts::9 38 # Per bank write bursts -system.physmem.perBankRdBursts::10 28 # Per bank write bursts -system.physmem.perBankRdBursts::11 34 # Per bank write bursts -system.physmem.perBankRdBursts::12 15 # Per bank write bursts -system.physmem.perBankRdBursts::13 120 # Per bank write bursts -system.physmem.perBankRdBursts::14 67 # Per bank write bursts -system.physmem.perBankRdBursts::15 37 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 26630500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 968 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 332 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 313 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 185 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 94 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 37 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 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-system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 202 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 289.584158 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 180.299588 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 295.891915 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 69 34.16% 34.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 55 27.23% 61.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 20 9.90% 71.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 16 7.92% 79.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 9 4.46% 83.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7 3.47% 87.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 9 4.46% 91.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3 1.49% 93.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 14 6.93% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 202 # Bytes accessed per row activation -system.physmem.totQLat 15942250 # Total ticks spent queuing -system.physmem.totMemAccLat 34092250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4840000 # Total ticks spent in databus transfers -system.physmem.avgQLat 16469.27 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 35219.27 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2323.65 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2323.65 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 18.15 # Data bus utilization in percentage -system.physmem.busUtilRead 18.15 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.46 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 755 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 78.00 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 27510.85 # Average gap between requests -system.physmem.pageHitRate 78.00 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 849660 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 436425 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4191180 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 6127500 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 47520 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 5972460 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 1440 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 19470105 # Total energy per rank (pJ) -system.physmem_0.averagePower 730.243038 # Core power per rank (mW) -system.physmem_0.totalIdleTime 12953500 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 40500 # Time in different power states -system.physmem_0.memoryStateTime::REF 780000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 0 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 3750 # Time in different power states -system.physmem_0.memoryStateTime::ACT 12735000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 13102250 # Time in different power states -system.physmem_1.actEnergy 671160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 330165 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 2720340 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 4612440 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 162240 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 6908970 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 373920 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 17623155 # Total energy per rank (pJ) -system.physmem_1.averagePower 660.971589 # Core power per rank (mW) -system.physmem_1.totalIdleTime 16131250 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 312000 # Time in different power states -system.physmem_1.memoryStateTime::REF 780000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 0 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 973000 # Time in different power states -system.physmem_1.memoryStateTime::ACT 9438250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 15158250 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 4864 # Number of BP lookups -system.cpu.branchPred.condPredicted 2895 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 795 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 3714 # Number of BTB lookups -system.cpu.branchPred.BTBHits 1183 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 31.852450 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 710 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 56 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 762 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 147 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 615 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 133 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 4130 # DTB read hits -system.cpu.dtb.read_misses 76 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 4206 # DTB read accesses -system.cpu.dtb.write_hits 2011 # DTB write hits -system.cpu.dtb.write_misses 48 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 2059 # DTB write accesses -system.cpu.dtb.data_hits 6141 # DTB hits -system.cpu.dtb.data_misses 124 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 6265 # DTB accesses -system.cpu.itb.fetch_hits 3836 # ITB hits -system.cpu.itb.fetch_misses 50 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 3886 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload0.num_syscalls 17 # Number of system calls -system.cpu.workload1.num_syscalls 17 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 26661500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 53324 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 748 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 27869 # Number of instructions fetch has processed -system.cpu.fetch.Branches 4864 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 2040 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 9408 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 875 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 344 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 3836 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 566 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 26300 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.059658 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.449516 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 21275 80.89% 80.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 504 1.92% 82.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 391 1.49% 84.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 446 1.70% 85.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 478 1.82% 87.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 367 1.40% 89.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 469 1.78% 90.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 276 1.05% 92.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2094 7.96% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 26300 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.091216 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.522635 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 36528 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 10375 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3958 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 495 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 725 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 405 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 151 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 24583 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 377 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 725 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 36872 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3499 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1435 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 4116 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5434 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 23584 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 36 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 223 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 328 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4703 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 17574 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 29532 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 29514 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 9154 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 8420 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 57 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 45 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 1621 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1925 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1093 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.memDep1.insertedLoads 2578 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep1.insertedStores 1286 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep1.conflictingLoads 15 # Number of conflicting loads. -system.cpu.memDep1.conflictingStores 4 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 21800 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 51 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 19296 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 51 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 9080 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4753 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 26300 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.733688 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.450617 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 18970 72.13% 72.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 2362 8.98% 81.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1626 6.18% 87.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1294 4.92% 92.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1061 4.03% 96.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 563 2.14% 98.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 282 1.07% 99.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 87 0.33% 99.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 55 0.21% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 26300 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 29 9.67% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 191 63.67% 73.33% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 77 25.67% 99.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 0 0.00% 99.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 3 1.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5884 66.04% 66.06% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 66.07% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2014 22.60% 88.70% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 999 11.21% 99.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 1 0.01% 99.92% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 7 0.08% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8910 # Type of FU issued -system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_1::IntAlu 6849 65.94% 65.96% # Type of FU issued -system.cpu.iq.FU_type_1::IntMult 1 0.01% 65.97% # Type of FU issued -system.cpu.iq.FU_type_1::IntDiv 0 0.00% 65.97% # Type of FU issued -system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::FloatMult 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::FloatMultAcc 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::FloatMisc 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMult 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShift 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 65.99% # Type of FU issued -system.cpu.iq.FU_type_1::MemRead 2410 23.20% 89.20% # Type of FU issued -system.cpu.iq.FU_type_1::MemWrite 1114 10.73% 99.92% # Type of FU issued -system.cpu.iq.FU_type_1::FloatMemRead 1 0.01% 99.93% # Type of FU issued -system.cpu.iq.FU_type_1::FloatMemWrite 7 0.07% 100.00% # Type of FU issued -system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_1::total 10386 # Type of FU issued -system.cpu.iq.FU_type::total 19296 0.00% 0.00% # Type of FU issued -system.cpu.iq.rate 0.361863 # Inst issue rate -system.cpu.iq.fu_busy_cnt::0 152 # FU busy when requested -system.cpu.iq.fu_busy_cnt::1 148 # FU busy when requested -system.cpu.iq.fu_busy_cnt::total 300 # FU busy when requested -system.cpu.iq.fu_busy_rate::0 0.007877 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::1 0.007670 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::total 0.015547 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 65200 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 30942 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 17504 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 43 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 19569 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 23 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 39 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 740 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 228 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 290 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread1.forwLoads 97 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread1.squashedLoads 1393 # Number of loads squashed -system.cpu.iew.lsq.thread1.ignoredResponses 14 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread1.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread1.squashedStores 421 # Number of stores squashed -system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread1.cacheBlocked 234 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 725 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1992 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 420 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 21985 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 174 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 4503 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2379 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 51 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 21 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 390 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 32 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 134 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 638 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 772 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 18585 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts::0 1945 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::1 2264 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::total 4209 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 711 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp::0 0 # number of swp insts executed -system.cpu.iew.exec_swp::1 0 # number of swp insts executed -system.cpu.iew.exec_swp::total 0 # number of swp insts executed -system.cpu.iew.exec_nop::0 63 # number of nop insts executed -system.cpu.iew.exec_nop::1 71 # number of nop insts executed -system.cpu.iew.exec_nop::total 134 # number of nop insts executed -system.cpu.iew.exec_refs::0 2942 # number of memory reference insts executed -system.cpu.iew.exec_refs::1 3338 # number of memory reference insts executed -system.cpu.iew.exec_refs::total 6280 # number of memory reference insts executed -system.cpu.iew.exec_branches::0 1393 # Number of branches executed -system.cpu.iew.exec_branches::1 1580 # Number of branches executed -system.cpu.iew.exec_branches::total 2973 # Number of branches executed -system.cpu.iew.exec_stores::0 997 # Number of stores executed -system.cpu.iew.exec_stores::1 1074 # Number of stores executed -system.cpu.iew.exec_stores::total 2071 # Number of stores executed -system.cpu.iew.exec_rate 0.348530 # Inst execution rate -system.cpu.iew.wb_sent::0 8281 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::1 9496 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::total 17777 # cumulative count of insts sent to commit -system.cpu.iew.wb_count::0 8197 # cumulative count of insts written-back -system.cpu.iew.wb_count::1 9327 # cumulative count of insts written-back -system.cpu.iew.wb_count::total 17524 # cumulative count of insts written-back -system.cpu.iew.wb_producers::0 4340 # num instructions producing a value -system.cpu.iew.wb_producers::1 4919 # num instructions producing a value -system.cpu.iew.wb_producers::total 9259 # num instructions producing a value -system.cpu.iew.wb_consumers::0 5879 # num instructions consuming a value -system.cpu.iew.wb_consumers::1 6619 # num instructions consuming a value -system.cpu.iew.wb_consumers::total 12498 # num instructions consuming a value -system.cpu.iew.wb_rate::0 0.153721 # insts written-back per cycle -system.cpu.iew.wb_rate::1 0.174912 # insts written-back per cycle -system.cpu.iew.wb_rate::total 0.328633 # insts written-back per cycle -system.cpu.iew.wb_fanout::0 0.738221 # average fanout of values written-back -system.cpu.iew.wb_fanout::1 0.743164 # average fanout of values written-back -system.cpu.iew.wb_fanout::total 0.740839 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 9130 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 646 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 26282 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.487178 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.404713 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 21298 81.04% 81.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 2499 9.51% 90.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 926 3.52% 94.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 403 1.53% 95.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 249 0.95% 96.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 154 0.59% 97.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 215 0.82% 97.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 116 0.44% 98.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 422 1.61% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 26282 # Number of insts commited each cycle -system.cpu.commit.committedInsts::0 6402 # Number of instructions committed -system.cpu.commit.committedInsts::1 6402 # Number of instructions committed -system.cpu.commit.committedInsts::total 12804 # Number of instructions committed -system.cpu.commit.committedOps::0 6402 # Number of ops (including micro ops) committed -system.cpu.commit.committedOps::1 6402 # Number of ops (including micro ops) committed -system.cpu.commit.committedOps::total 12804 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count::0 0 # Number of s/w prefetches committed -system.cpu.commit.swp_count::1 0 # Number of s/w prefetches committed -system.cpu.commit.swp_count::total 0 # Number of s/w prefetches committed -system.cpu.commit.refs::0 2050 # Number of memory references committed -system.cpu.commit.refs::1 2050 # Number of memory references committed -system.cpu.commit.refs::total 4100 # Number of memory references committed -system.cpu.commit.loads::0 1185 # Number of loads committed -system.cpu.commit.loads::1 1185 # Number of loads committed -system.cpu.commit.loads::total 2370 # Number of loads committed -system.cpu.commit.membars::0 0 # Number of memory barriers committed -system.cpu.commit.membars::1 0 # Number of memory barriers committed -system.cpu.commit.membars::total 0 # Number of memory barriers committed -system.cpu.commit.branches::0 1056 # Number of branches committed -system.cpu.commit.branches::1 1056 # Number of branches committed -system.cpu.commit.branches::total 2112 # Number of branches committed -system.cpu.commit.fp_insts::0 10 # Number of committed floating point instructions. -system.cpu.commit.fp_insts::1 10 # Number of committed floating point instructions. -system.cpu.commit.fp_insts::total 20 # Number of committed floating point instructions. -system.cpu.commit.int_insts::0 6319 # Number of committed integer instructions. -system.cpu.commit.int_insts::1 6319 # Number of committed integer instructions. -system.cpu.commit.int_insts::total 12638 # Number of committed integer instructions. -system.cpu.commit.function_calls::0 127 # Number of function calls committed. -system.cpu.commit.function_calls::1 127 # Number of function calls committed. -system.cpu.commit.function_calls::total 254 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 19 0.30% 0.30% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 4330 67.64% 67.93% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 1 0.02% 67.95% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 67.95% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 2 0.03% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 1184 18.49% 86.47% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 858 13.40% 99.88% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemRead 1 0.02% 99.89% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemWrite 7 0.11% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 6402 # Class of committed instruction -system.cpu.commit.op_class_1::No_OpClass 19 0.30% 0.30% # Class of committed instruction -system.cpu.commit.op_class_1::IntAlu 4330 67.64% 67.93% # Class of committed instruction -system.cpu.commit.op_class_1::IntMult 1 0.02% 67.95% # Class of committed instruction -system.cpu.commit.op_class_1::IntDiv 0 0.00% 67.95% # Class of committed instruction -system.cpu.commit.op_class_1::FloatAdd 2 0.03% 67.98% # Class of committed instruction -system.cpu.commit.op_class_1::FloatCmp 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_1::FloatCvt 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_1::FloatMult 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_1::FloatMultAcc 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_1::FloatDiv 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_1::FloatMisc 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_1::FloatSqrt 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_1::SimdAdd 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_1::SimdAddAcc 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_1::SimdAlu 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_1::SimdCmp 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_1::SimdCvt 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_1::SimdMisc 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_1::SimdMult 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_1::SimdMultAcc 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_1::SimdShift 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_1::SimdShiftAcc 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_1::SimdSqrt 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_1::SimdFloatAdd 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_1::SimdFloatAlu 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_1::SimdFloatCmp 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_1::SimdFloatCvt 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_1::SimdFloatDiv 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_1::SimdFloatMisc 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_1::SimdFloatMult 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_1::SimdFloatMultAcc 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_1::SimdFloatSqrt 0 0.00% 67.98% # Class of committed instruction -system.cpu.commit.op_class_1::MemRead 1184 18.49% 86.47% # Class of committed instruction -system.cpu.commit.op_class_1::MemWrite 858 13.40% 99.88% # Class of committed instruction -system.cpu.commit.op_class_1::FloatMemRead 1 0.02% 99.89% # Class of committed instruction -system.cpu.commit.op_class_1::FloatMemWrite 7 0.11% 100.00% # Class of committed instruction -system.cpu.commit.op_class_1::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_1::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_1::total 6402 # Class of committed instruction -system.cpu.commit.op_class::total 12804 0.00% 0.00% # Class of committed instruction -system.cpu.commit.bw_lim_events 422 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 113054 # The number of ROB reads -system.cpu.rob.rob_writes 45570 # The number of ROB writes -system.cpu.timesIdled 413 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 27024 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts::0 6385 # Number of Instructions Simulated -system.cpu.committedInsts::1 6385 # Number of Instructions Simulated -system.cpu.committedInsts::total 12770 # Number of Instructions Simulated -system.cpu.committedOps::0 6385 # Number of Ops (including micro ops) Simulated -system.cpu.committedOps::1 6385 # Number of Ops (including micro ops) Simulated -system.cpu.committedOps::total 12770 # Number of Ops (including micro ops) Simulated -system.cpu.cpi::0 8.351449 # CPI: Cycles Per Instruction -system.cpu.cpi::1 8.351449 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.175724 # CPI: Total CPI of All Threads -system.cpu.ipc::0 0.119740 # IPC: Instructions Per Cycle -system.cpu.ipc::1 0.119740 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.239479 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 23475 # number of integer regfile reads -system.cpu.int_regfile_writes 13132 # number of integer regfile writes -system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.fp_regfile_writes 4 # number of floating regfile writes -system.cpu.misc_regfile_reads 2 # number of misc regfile reads -system.cpu.misc_regfile_writes 2 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements::0 0 # number of replacements -system.cpu.dcache.tags.replacements::1 0 # number of replacements -system.cpu.dcache.tags.replacements::total 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 216.020971 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 4236 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 342 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.385965 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 216.020971 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.052739 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.052739 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 342 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 270 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.083496 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 10868 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 10868 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 3224 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 3224 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 1012 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 1012 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 4236 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 4236 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 4236 # number of overall hits -system.cpu.dcache.overall_hits::total 4236 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 309 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 309 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 718 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 718 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1027 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1027 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1027 # number of overall misses -system.cpu.dcache.overall_misses::total 1027 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 24016000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 24016000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 51330451 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 51330451 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 75346451 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 75346451 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 75346451 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 75346451 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 3533 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 3533 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 5263 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 5263 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 5263 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 5263 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087461 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.087461 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.195136 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.195136 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.195136 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.195136 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77721.682848 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 77721.682848 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71490.878830 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 71490.878830 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 73365.580331 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 73365.580331 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 73365.580331 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 73365.580331 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5997 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 108 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 55.527778 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 110 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 110 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 574 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 574 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 684 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 684 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 684 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 684 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 199 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 199 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 144 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 144 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 343 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 343 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 343 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 343 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17847000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 17847000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12459487 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12459487 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 30306487 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 30306487 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 30306487 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 30306487 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.056326 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.056326 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.065172 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.065172 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.065172 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.065172 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89683.417085 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89683.417085 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 86524.215278 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 86524.215278 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 88357.104956 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 88357.104956 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 88357.104956 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 88357.104956 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements::0 7 # number of replacements -system.cpu.icache.tags.replacements::1 0 # number of replacements -system.cpu.icache.tags.replacements::total 7 # number of replacements -system.cpu.icache.tags.tagsinuse 318.055053 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 2937 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 628 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 4.676752 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 318.055053 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.155300 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.155300 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 621 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 238 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 383 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.303223 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 8292 # Number of tag accesses -system.cpu.icache.tags.data_accesses 8292 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 2937 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 2937 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 2937 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 2937 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 2937 # number of overall hits -system.cpu.icache.overall_hits::total 2937 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 895 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 895 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 895 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 895 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 895 # number of overall misses -system.cpu.icache.overall_misses::total 895 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 72806995 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 72806995 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 72806995 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 72806995 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 72806995 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 72806995 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 3832 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 3832 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 3832 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 3832 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 3832 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 3832 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.233559 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.233559 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.233559 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.233559 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.233559 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.233559 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 81348.597765 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 81348.597765 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 81348.597765 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 81348.597765 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 81348.597765 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 81348.597765 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 3504 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 58 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 60.413793 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 7 # number of writebacks -system.cpu.icache.writebacks::total 7 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 267 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 267 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 267 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 267 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 267 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 267 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 628 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 628 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 628 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 628 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 628 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 628 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 54757996 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 54757996 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 54757996 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 54757996 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 54757996 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 54757996 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.163883 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.163883 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.163883 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.163883 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.163883 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.163883 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 87194.261146 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 87194.261146 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 87194.261146 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 87194.261146 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 87194.261146 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 87194.261146 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements::0 0 # number of replacements -system.cpu.l2cache.tags.replacements::1 0 # number of replacements -system.cpu.l2cache.tags.replacements::total 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 534.674828 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 10 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 967 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.010341 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 318.519168 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 216.155660 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009720 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.006597 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.016317 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 967 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 306 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 661 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.029510 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 8791 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 8791 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackClean_hits::writebacks 7 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 7 # number of WritebackClean hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 3 # number of ReadCleanReq hits -system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits -system.cpu.l2cache.overall_hits::total 3 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 145 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 145 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 625 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 625 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 198 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 198 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 625 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 343 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 968 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 625 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 343 # number of overall misses -system.cpu.l2cache.overall_misses::total 968 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12308500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 12308500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 53778000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 53778000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17466000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 17466000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 53778000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 29774500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 83552500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 53778000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 29774500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 83552500 # number of overall miss cycles -system.cpu.l2cache.WritebackClean_accesses::writebacks 7 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 7 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 145 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 145 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 628 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 628 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 198 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 198 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 628 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 343 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 971 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 628 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 343 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 971 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.995223 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.995223 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.995223 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.996910 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995223 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.996910 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 84886.206897 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 84886.206897 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 86044.800000 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 86044.800000 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 88212.121212 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 88212.121212 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 86044.800000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86806.122449 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 86314.566116 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 86044.800000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86806.122449 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 86314.566116 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 145 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 145 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 625 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 625 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 198 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 198 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 625 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 343 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 968 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 625 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 343 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 968 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10858500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10858500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 47528000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 47528000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15496000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15496000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 47528000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26354500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 73882500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 47528000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26354500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 73882500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.995223 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.995223 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995223 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.996910 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995223 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.996910 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 74886.206897 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 74886.206897 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 76044.800000 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 76044.800000 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78262.626263 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78262.626263 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76044.800000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76835.276968 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76324.896694 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76044.800000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76835.276968 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76324.896694 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 978 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 9 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 825 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 7 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 145 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 145 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 628 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 198 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1263 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 685 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1948 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40640 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21888 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 62528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 971 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.002060 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.045361 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 969 99.79% 99.79% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2 0.21% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 971 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 496000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 942000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 3.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 513000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.9 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 968 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 822 # Transaction distribution -system.membus.trans_dist::ReadExReq 145 # Transaction distribution -system.membus.trans_dist::ReadExResp 145 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 823 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1935 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1935 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 61888 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 61888 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 968 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 968 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 968 # Request fanout histogram -system.membus.reqLayer0.occupancy 1179500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 4.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 5127250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 19.2 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/config.ini --- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/config.ini Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,265 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu dvfs_handler mem_ctrl membus -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges=0:536870911:0:0:0:0 -memories=system.mem_ctrl -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[2] - -[system.clk_domain] -type=SrcClockDomain -children=voltage_domain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.clk_domain.voltage_domain - -[system.clk_domain.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - -[system.cpu] -type=TimingSimpleCPU -children=dtb interrupts isa itb tracer workload -branchPred=Null -checker=Null -clk_domain=system.clk_domain -cpu_id=-1 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.membus.slave[1] -icache_port=system.membus.slave[0] - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=tests/test-progs/hello/bin/alpha/linux/hello -cwd= -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable= -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.mem_ctrl] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=0:536870911:0:0:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=6000 -tXPDLL=0 -tXS=270000 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[0] - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.mem_ctrl.port -slave=system.cpu.icache_port system.cpu.dcache_port system.system_port - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/simerr --- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/simerr Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,3 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/simout --- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/simout Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,16 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:19:47 -gem5 executing on e108600-lin, pid 28091 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple - -Global frequency set at 1000000000000 ticks per second -Beginning simulation! -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Hello world! -Exiting @ tick 461109000 because target called exit() diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt --- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,417 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000461 # Number of seconds simulated -sim_ticks 461109000 # Number of ticks simulated -final_tick 461109000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 260049 # Simulator instruction rate (inst/s) -host_op_rate 259797 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 18548021181 # Simulator tick rate (ticks/s) -host_mem_usage 634440 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host -sim_insts 6453 # Number of instructions simulated -sim_ops 6453 # Number of ops (including micro ops) simulated -system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 461109000 # Cumulative time (in ticks) in various power states -system.mem_ctrl.bytes_read::cpu.inst 25852 # Number of bytes read from this memory -system.mem_ctrl.bytes_read::cpu.data 8844 # Number of bytes read from this memory -system.mem_ctrl.bytes_read::total 34696 # Number of bytes read from this memory -system.mem_ctrl.bytes_inst_read::cpu.inst 25852 # Number of instructions bytes read from this memory -system.mem_ctrl.bytes_inst_read::total 25852 # Number of instructions bytes read from this memory -system.mem_ctrl.bytes_written::cpu.data 6696 # Number of bytes written to this memory -system.mem_ctrl.bytes_written::total 6696 # Number of bytes written to this memory -system.mem_ctrl.num_reads::cpu.inst 6463 # Number of read requests responded to by this memory -system.mem_ctrl.num_reads::cpu.data 1190 # Number of read requests responded to by this memory -system.mem_ctrl.num_reads::total 7653 # Number of read requests responded to by this memory -system.mem_ctrl.num_writes::cpu.data 865 # Number of write requests responded to by this memory -system.mem_ctrl.num_writes::total 865 # Number of write requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 56064835 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 19179847 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 75244682 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 56064835 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 56064835 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::cpu.data 14521512 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_write::total 14521512 # Write bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 56064835 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 33701359 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 89766194 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.readReqs 7654 # Number of read requests accepted -system.mem_ctrl.writeReqs 865 # Number of write requests accepted -system.mem_ctrl.readBursts 7654 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrl.writeBursts 865 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrl.bytesReadDRAM 477504 # Total number of bytes read from DRAM -system.mem_ctrl.bytesReadWrQ 12352 # Total number of bytes read from write queue -system.mem_ctrl.bytesWritten 6144 # Total number of bytes written to DRAM -system.mem_ctrl.bytesReadSys 34700 # Total read bytes from the system interface side -system.mem_ctrl.bytesWrittenSys 6696 # Total written bytes from the system interface side -system.mem_ctrl.servicedByWrQ 193 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrl.mergedWrBursts 752 # Number of DRAM write bursts merged with an existing one -system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrl.perBankRdBursts::0 1736 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::1 393 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::2 768 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::3 800 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::4 764 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::5 293 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::6 6 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::7 26 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::8 0 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::9 1 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::10 249 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::11 578 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::12 167 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::13 1431 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::14 91 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::15 158 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::4 18 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::5 7 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::9 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::10 7 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::13 20 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::14 44 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts -system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 461032000 # Total gap between requests -system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::2 6633 # Read request sizes (log2) -system.mem_ctrl.readPktSize::3 1021 # Read request sizes (log2) -system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::6 0 # Read request sizes (log2) -system.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::1 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::2 56 # Write request sizes (log2) -system.mem_ctrl.writePktSize::3 809 # Write request sizes (log2) -system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) -system.mem_ctrl.rdQLenPdf::0 7461 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::15 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::16 1 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::17 6 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::18 6 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::19 6 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::20 6 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::21 6 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::22 6 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::23 6 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::24 6 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::25 6 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::26 6 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::27 6 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::28 6 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::29 6 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::30 6 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::31 6 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::32 6 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 766 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 629.556136 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 420.481555 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 399.288519 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 144 18.80% 18.80% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 67 8.75% 27.55% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 42 5.48% 33.03% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 49 6.40% 39.43% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 40 5.22% 44.65% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 39 5.09% 49.74% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 38 4.96% 54.70% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::896-1023 34 4.44% 59.14% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 313 40.86% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 766 # Bytes accessed per row activation -system.mem_ctrl.rdPerTurnAround::samples 6 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::mean 1237 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::gmean 1086.549947 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::stdev 686.122730 # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::512-639 2 33.33% 33.33% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1152-1279 2 33.33% 66.67% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::1408-1535 1 16.67% 83.33% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::2304-2431 1 16.67% 100.00% # Reads before turning the bus around for writes -system.mem_ctrl.rdPerTurnAround::total 6 # Reads before turning the bus around for writes -system.mem_ctrl.wrPerTurnAround::samples 6 # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::16 6 100.00% 100.00% # Writes before turning the bus around for reads -system.mem_ctrl.wrPerTurnAround::total 6 # Writes before turning the bus around for reads -system.mem_ctrl.totQLat 73323250 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 213217000 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrl.totBusLat 37305000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 9827.54 # Average queueing delay per DRAM burst -system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 28577.54 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 1035.56 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrl.avgWrBW 13.32 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 75.25 # Average system read bandwidth in MiByte/s -system.mem_ctrl.avgWrBWSys 14.52 # Average system write bandwidth in MiByte/s -system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 8.19 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 8.09 # Data bus utilization in percentage for reads -system.mem_ctrl.busUtilWrite 0.10 # Data bus utilization in percentage for writes -system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrl.avgWrQLen 23.97 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 6701 # Number of row buffer hits during reads -system.mem_ctrl.writeRowHits 86 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 89.81 # Row buffer hit rate for reads -system.mem_ctrl.writeRowHitRate 76.11 # Row buffer hit rate for writes -system.mem_ctrl.avgGap 54118.09 # Average gap between requests -system.mem_ctrl.pageHitRate 89.61 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 3184440 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 1681185 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 34164900 # Energy for read commands per rank (pJ) -system.mem_ctrl_0.writeEnergy 130500 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 36263760.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 65335680 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 1899360 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.actPowerDownEnergy 128211240 # Energy for active power-down per rank (pJ) -system.mem_ctrl_0.prePowerDownEnergy 12180000 # Energy for precharge power-down per rank (pJ) -system.mem_ctrl_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrl_0.totalEnergy 283051065 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 613.847162 # Core power per rank (mW) -system.mem_ctrl_0.totalIdleTime 312833500 # Total Idle time Per DRAM Rank -system.mem_ctrl_0.memoryStateTime::IDLE 882000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::REF 15340000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::PRE_PDN 31715250 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 132053500 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT_PDN 281118250 # Time in different power states -system.mem_ctrl_1.actEnergy 2313360 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 1225785 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 19099500 # Energy for read commands per rank (pJ) -system.mem_ctrl_1.writeEnergy 370620 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 35649120.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 44402430 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 1287360 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.actPowerDownEnergy 129142620 # Energy for active power-down per rank (pJ) -system.mem_ctrl_1.prePowerDownEnergy 18055680 # Energy for precharge power-down per rank (pJ) -system.mem_ctrl_1.selfRefreshEnergy 8894220 # Energy for self refresh per rank (pJ) -system.mem_ctrl_1.totalEnergy 260440695 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 564.812507 # Core power per rank (mW) -system.mem_ctrl_1.totalIdleTime 359701750 # Total Idle time Per DRAM Rank -system.mem_ctrl_1.memoryStateTime::IDLE 1420000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::REF 15098000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::SREF 30156500 # Time in different power states -system.mem_ctrl_1.memoryStateTime::PRE_PDN 47020500 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 84176750 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT_PDN 283237250 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 461109000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1190 # DTB read hits -system.cpu.dtb.read_misses 7 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 1197 # DTB read accesses -system.cpu.dtb.write_hits 865 # DTB write hits -system.cpu.dtb.write_misses 3 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 868 # DTB write accesses -system.cpu.dtb.data_hits 2055 # DTB hits -system.cpu.dtb.data_misses 10 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 2065 # DTB accesses -system.cpu.itb.fetch_hits 6464 # ITB hits -system.cpu.itb.fetch_misses 17 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 6481 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 461109000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 461109 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 6453 # Number of instructions committed -system.cpu.committedOps 6453 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 6380 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses -system.cpu.num_func_calls 251 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 759 # number of instructions that are conditional controls -system.cpu.num_int_insts 6380 # number of integer instructions -system.cpu.num_fp_insts 10 # number of float instructions -system.cpu.num_int_register_reads 8392 # number of times the integer registers were read -system.cpu.num_int_register_writes 4621 # number of times the integer registers were written -system.cpu.num_fp_register_reads 8 # number of times the floating registers were read -system.cpu.num_fp_register_writes 2 # number of times the floating registers were written -system.cpu.num_mem_refs 2065 # number of memory refs -system.cpu.num_load_insts 1197 # Number of load instructions -system.cpu.num_store_insts 868 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 461109 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 1060 # Number of branches fetched -system.cpu.op_class::No_OpClass 19 0.29% 0.29% # Class of executed instruction -system.cpu.op_class::IntAlu 4376 67.71% 68.00% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.02% 68.02% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 68.02% # Class of executed instruction -system.cpu.op_class::FloatAdd 2 0.03% 68.05% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::MemRead 1196 18.51% 86.55% # Class of executed instruction -system.cpu.op_class::MemWrite 861 13.32% 99.88% # Class of executed instruction -system.cpu.op_class::FloatMemRead 1 0.02% 99.89% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 7 0.11% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 6463 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 461109000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 7654 # Transaction distribution -system.membus.trans_dist::ReadResp 7653 # Transaction distribution -system.membus.trans_dist::WriteReq 865 # Transaction distribution -system.membus.trans_dist::WriteResp 865 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.mem_ctrl.port 12927 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.mem_ctrl.port 4110 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 17037 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.mem_ctrl.port 25852 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.mem_ctrl.port 15540 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 41392 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 8519 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 8519 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 8519 # Request fanout histogram -system.membus.reqLayer0.occupancy 9384000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 14690000 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 3572750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.8 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/config.ini --- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/config.ini Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,432 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu dvfs_handler l2bus l2cache mem_ctrl membus -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges=0:536870911:0:0:0:0 -memories=system.mem_ctrl -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[1] - -[system.clk_domain] -type=SrcClockDomain -children=voltage_domain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.clk_domain.voltage_domain - -[system.clk_domain.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - -[system.cpu] -type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb tracer workload -branchPred=Null -checker=Null -clk_domain=system.clk_domain -cpu_id=-1 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=65536 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.l2bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=65536 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=16384 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.icache_port -mem_side=system.l2bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=16384 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=tests/test-progs/hello/bin/alpha/linux/hello -cwd= -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable= -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.l2bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.l2bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.l2bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=262144 -system=system -tags=system.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.l2bus.master[0] -mem_side=system.membus.slave[0] - -[system.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 - -[system.mem_ctrl] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=0:536870911:0:0:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=6000 -tXPDLL=0 -tXS=270000 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[0] - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.mem_ctrl.port -slave=system.l2cache.mem_side system.system_port - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/simerr --- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/simerr Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,3 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/simout --- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/simout Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,16 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:19:46 -gem5 executing on e108600-lin, pid 28074 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level - -Global frequency set at 1000000000000 ticks per second -Beginning simulation! -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Hello world! -Exiting @ tick 64758000 because target called exit() diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt --- a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,745 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000065 # Number of seconds simulated -sim_ticks 64758000 # Number of ticks simulated -final_tick 64758000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 610635 # Simulator instruction rate (inst/s) -host_op_rate 610062 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6117087273 # Simulator tick rate (ticks/s) -host_mem_usage 638532 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -sim_insts 6453 # Number of instructions simulated -sim_ops 6453 # Number of ops (including micro ops) simulated -system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states -system.mem_ctrl.bytes_read::cpu.inst 17792 # Number of bytes read from this memory -system.mem_ctrl.bytes_read::cpu.data 10752 # Number of bytes read from this memory -system.mem_ctrl.bytes_read::total 28544 # Number of bytes read from this memory -system.mem_ctrl.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory -system.mem_ctrl.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory -system.mem_ctrl.num_reads::cpu.inst 278 # Number of read requests responded to by this memory -system.mem_ctrl.num_reads::cpu.data 168 # Number of read requests responded to by this memory -system.mem_ctrl.num_reads::total 446 # Number of read requests responded to by this memory -system.mem_ctrl.bw_read::cpu.inst 274745977 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::cpu.data 166033540 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_read::total 440779518 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::cpu.inst 274745977 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_inst_read::total 274745977 # Instruction read bandwidth from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.inst 274745977 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::cpu.data 166033540 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.bw_total::total 440779518 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrl.readReqs 446 # Number of read requests accepted -system.mem_ctrl.writeReqs 0 # Number of write requests accepted -system.mem_ctrl.readBursts 446 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrl.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrl.bytesReadDRAM 28544 # Total number of bytes read from DRAM -system.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue -system.mem_ctrl.bytesWritten 0 # Total number of bytes written to DRAM -system.mem_ctrl.bytesReadSys 28544 # Total read bytes from the system interface side -system.mem_ctrl.bytesWrittenSys 0 # Total written bytes from the system interface side -system.mem_ctrl.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrl.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrl.perBankRdBursts::0 62 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::1 26 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::2 24 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::3 43 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::4 40 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::5 17 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::6 1 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::7 3 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::8 0 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::9 1 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::10 19 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::11 23 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::12 14 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::13 116 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::14 45 # Per bank write bursts -system.mem_ctrl.perBankRdBursts::15 12 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::9 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts -system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts -system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrl.totGap 64501000 # Total gap between requests -system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrl.readPktSize::6 446 # Read request sizes (log2) -system.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::1 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::2 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::3 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) -system.mem_ctrl.rdQLenPdf::0 446 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrl.bytesPerActivate::samples 105 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::mean 264.533333 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::gmean 181.831163 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::stdev 249.307389 # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::0-127 27 25.71% 25.71% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::128-255 40 38.10% 63.81% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::256-383 10 9.52% 73.33% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::384-511 9 8.57% 81.90% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::512-639 7 6.67% 88.57% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::640-767 6 5.71% 94.29% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::768-895 1 0.95% 95.24% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::1024-1151 5 4.76% 100.00% # Bytes accessed per row activation -system.mem_ctrl.bytesPerActivate::total 105 # Bytes accessed per row activation -system.mem_ctrl.totQLat 6134000 # Total ticks spent queuing -system.mem_ctrl.totMemAccLat 14496500 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrl.totBusLat 2230000 # Total ticks spent in databus transfers -system.mem_ctrl.avgQLat 13753.36 # Average queueing delay per DRAM burst -system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.mem_ctrl.avgMemAccLat 32503.36 # Average memory access latency per DRAM burst -system.mem_ctrl.avgRdBW 440.78 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.mem_ctrl.avgRdBWSys 440.78 # Average system read bandwidth in MiByte/s -system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrl.busUtil 3.44 # Data bus utilization in percentage -system.mem_ctrl.busUtilRead 3.44 # Data bus utilization in percentage for reads -system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing -system.mem_ctrl.readRowHits 337 # Number of row buffer hits during reads -system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes -system.mem_ctrl.readRowHitRate 75.56 # Row buffer hit rate for reads -system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes -system.mem_ctrl.avgGap 144621.08 # Average gap between requests -system.mem_ctrl.pageHitRate 75.56 # Row buffer hit rate, read and write combined -system.mem_ctrl_0.actEnergy 314160 # Energy for activate commands per rank (pJ) -system.mem_ctrl_0.preEnergy 163185 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_0.readEnergy 1542240 # Energy for read commands per rank (pJ) -system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrl_0.refreshEnergy 4917120.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_0.actBackEnergy 3812160 # Energy for active background per rank (pJ) -system.mem_ctrl_0.preBackEnergy 131040 # Energy for precharge background per rank (pJ) -system.mem_ctrl_0.actPowerDownEnergy 22575420 # Energy for active power-down per rank (pJ) -system.mem_ctrl_0.prePowerDownEnergy 2515200 # Energy for precharge power-down per rank (pJ) -system.mem_ctrl_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrl_0.totalEnergy 35970525 # Total energy per rank (pJ) -system.mem_ctrl_0.averagePower 555.454282 # Core power per rank (mW) -system.mem_ctrl_0.totalIdleTime 55623250 # Total Idle time Per DRAM Rank -system.mem_ctrl_0.memoryStateTime::IDLE 77000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::REF 2080000 # Time in different power states -system.mem_ctrl_0.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrl_0.memoryStateTime::PRE_PDN 6549500 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT 6531250 # Time in different power states -system.mem_ctrl_0.memoryStateTime::ACT_PDN 49520250 # Time in different power states -system.mem_ctrl_1.actEnergy 464100 # Energy for activate commands per rank (pJ) -system.mem_ctrl_1.preEnergy 235290 # Energy for precharge commands per rank (pJ) -system.mem_ctrl_1.readEnergy 1642200 # Energy for read commands per rank (pJ) -system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrl_1.refreshEnergy 4917120.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrl_1.actBackEnergy 4174680 # Energy for active background per rank (pJ) -system.mem_ctrl_1.preBackEnergy 251520 # Energy for precharge background per rank (pJ) -system.mem_ctrl_1.actPowerDownEnergy 24338430 # Energy for active power-down per rank (pJ) -system.mem_ctrl_1.prePowerDownEnergy 604800 # Energy for precharge power-down per rank (pJ) -system.mem_ctrl_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrl_1.totalEnergy 36628140 # Total energy per rank (pJ) -system.mem_ctrl_1.averagePower 565.609126 # Core power per rank (mW) -system.mem_ctrl_1.totalIdleTime 54728750 # Total Idle time Per DRAM Rank -system.mem_ctrl_1.memoryStateTime::IDLE 283000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::REF 2080000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrl_1.memoryStateTime::PRE_PDN 1573250 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT 7457000 # Time in different power states -system.mem_ctrl_1.memoryStateTime::ACT_PDN 53364750 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1190 # DTB read hits -system.cpu.dtb.read_misses 7 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 1197 # DTB read accesses -system.cpu.dtb.write_hits 865 # DTB write hits -system.cpu.dtb.write_misses 3 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 868 # DTB write accesses -system.cpu.dtb.data_hits 2055 # DTB hits -system.cpu.dtb.data_misses 10 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 2065 # DTB accesses -system.cpu.itb.fetch_hits 6464 # ITB hits -system.cpu.itb.fetch_misses 17 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 6481 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 64758000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 64758 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 6453 # Number of instructions committed -system.cpu.committedOps 6453 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 6380 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses -system.cpu.num_func_calls 251 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 759 # number of instructions that are conditional controls -system.cpu.num_int_insts 6380 # number of integer instructions -system.cpu.num_fp_insts 10 # number of float instructions -system.cpu.num_int_register_reads 8392 # number of times the integer registers were read -system.cpu.num_int_register_writes 4621 # number of times the integer registers were written -system.cpu.num_fp_register_reads 8 # number of times the floating registers were read -system.cpu.num_fp_register_writes 2 # number of times the floating registers were written -system.cpu.num_mem_refs 2065 # number of memory refs -system.cpu.num_load_insts 1197 # Number of load instructions -system.cpu.num_store_insts 868 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 64758 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 1060 # Number of branches fetched -system.cpu.op_class::No_OpClass 19 0.29% 0.29% # Class of executed instruction -system.cpu.op_class::IntAlu 4376 67.71% 68.00% # Class of executed instruction -system.cpu.op_class::IntMult 1 0.02% 68.02% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 68.02% # Class of executed instruction -system.cpu.op_class::FloatAdd 2 0.03% 68.05% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.05% # Class of executed instruction -system.cpu.op_class::MemRead 1196 18.51% 86.55% # Class of executed instruction -system.cpu.op_class::MemWrite 861 13.32% 99.88% # Class of executed instruction -system.cpu.op_class::FloatMemRead 1 0.02% 99.89% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 7 0.11% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 6463 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 104.399751 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1887 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.232143 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 104.399751 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.101953 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.101953 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.164062 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4278 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4278 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1095 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1095 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1887 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1887 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1887 # number of overall hits -system.cpu.dcache.overall_hits::total 1887 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 95 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 95 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 73 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 168 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses -system.cpu.dcache.overall_misses::total 168 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10261000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10261000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 7802000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 7802000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 18063000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 18063000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 18063000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 18063000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1190 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1190 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2055 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2055 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2055 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2055 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.079832 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.079832 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084393 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.084393 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.081752 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.081752 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.081752 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.081752 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 108010.526316 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 108010.526316 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 106876.712329 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 106876.712329 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 107517.857143 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 107517.857143 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 107517.857143 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 107517.857143 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10071000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10071000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7656000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7656000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17727000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 17727000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17727000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 17727000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.079832 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.079832 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081752 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.081752 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081752 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.081752 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 106010.526316 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 106010.526316 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 104876.712329 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 104876.712329 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 105517.857143 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 105517.857143 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 105517.857143 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 105517.857143 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 62 # number of replacements -system.cpu.icache.tags.tagsinuse 113.445692 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 6183 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 281 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 22.003559 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 113.445692 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.443147 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.443147 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 219 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.855469 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 13209 # Number of tag accesses -system.cpu.icache.tags.data_accesses 13209 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 6183 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 6183 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 6183 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 6183 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 6183 # number of overall hits -system.cpu.icache.overall_hits::total 6183 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 281 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 281 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 281 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 281 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 281 # number of overall misses -system.cpu.icache.overall_misses::total 281 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 30557000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 30557000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 30557000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 30557000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 30557000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 30557000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 6464 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 6464 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 6464 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 6464 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 6464 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 6464 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043472 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.043472 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.043472 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.043472 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.043472 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.043472 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 108743.772242 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 108743.772242 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 108743.772242 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 108743.772242 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 108743.772242 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 108743.772242 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 281 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 281 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 281 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 281 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 281 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 281 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29995000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 29995000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29995000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 29995000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29995000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 29995000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043472 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.043472 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.043472 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 106743.772242 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 106743.772242 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 106743.772242 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 106743.772242 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 106743.772242 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 106743.772242 # average overall mshr miss latency -system.l2bus.snoop_filter.tot_requests 511 # Total number of requests made to the snoop filter. -system.l2bus.snoop_filter.hit_single_requests 63 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.l2bus.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states -system.l2bus.trans_dist::ReadResp 376 # Transaction distribution -system.l2bus.trans_dist::CleanEvict 62 # Transaction distribution -system.l2bus.trans_dist::ReadExReq 73 # Transaction distribution -system.l2bus.trans_dist::ReadExResp 73 # Transaction distribution -system.l2bus.trans_dist::ReadSharedReq 376 # Transaction distribution -system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 624 # Packet count per connected master and slave (bytes) -system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 336 # Packet count per connected master and slave (bytes) -system.l2bus.pkt_count::total 960 # Packet count per connected master and slave (bytes) -system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side 17984 # Cumulative packet size per connected master and slave (bytes) -system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 10752 # Cumulative packet size per connected master and slave (bytes) -system.l2bus.pkt_size::total 28736 # Cumulative packet size per connected master and slave (bytes) -system.l2bus.snoops 0 # Total snoops (count) -system.l2bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.l2bus.snoop_fanout::samples 449 # Request fanout histogram -system.l2bus.snoop_fanout::mean 0.002227 # Request fanout histogram -system.l2bus.snoop_fanout::stdev 0.047193 # Request fanout histogram -system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.l2bus.snoop_fanout::0 448 99.78% 99.78% # Request fanout histogram -system.l2bus.snoop_fanout::1 1 0.22% 100.00% # Request fanout histogram -system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram -system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram -system.l2bus.snoop_fanout::total 449 # Request fanout histogram -system.l2bus.reqLayer0.occupancy 511000 # Layer occupancy (ticks) -system.l2bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.l2bus.respLayer0.occupancy 843000 # Layer occupancy (ticks) -system.l2bus.respLayer0.utilization 1.3 # Layer utilization (%) -system.l2bus.respLayer1.occupancy 504000 # Layer occupancy (ticks) -system.l2bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states -system.l2cache.tags.replacements 0 # number of replacements -system.l2cache.tags.tagsinuse 232.606847 # Cycle average of tags in use -system.l2cache.tags.total_refs 65 # Total number of references to valid blocks. -system.l2cache.tags.sampled_refs 446 # Sample count of references to valid blocks. -system.l2cache.tags.avg_refs 0.145740 # Average number of references to valid blocks. -system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2cache.tags.occ_blocks::cpu.inst 128.152617 # Average occupied blocks per requestor -system.l2cache.tags.occ_blocks::cpu.data 104.454231 # Average occupied blocks per requestor -system.l2cache.tags.occ_percent::cpu.inst 0.031287 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::cpu.data 0.025502 # Average percentage of cache occupancy -system.l2cache.tags.occ_percent::total 0.056789 # Average percentage of cache occupancy -system.l2cache.tags.occ_task_id_blocks::1024 446 # Occupied blocks per task id -system.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id -system.l2cache.tags.age_task_id_blocks_1024::1 384 # Occupied blocks per task id -system.l2cache.tags.occ_task_id_percent::1024 0.108887 # Percentage of cache occupancy per task id -system.l2cache.tags.tag_accesses 4534 # Number of tag accesses -system.l2cache.tags.data_accesses 4534 # Number of data accesses -system.l2cache.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states -system.l2cache.ReadSharedReq_hits::cpu.inst 3 # number of ReadSharedReq hits -system.l2cache.ReadSharedReq_hits::total 3 # number of ReadSharedReq hits -system.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits -system.l2cache.demand_hits::total 3 # number of demand (read+write) hits -system.l2cache.overall_hits::cpu.inst 3 # number of overall hits -system.l2cache.overall_hits::total 3 # number of overall hits -system.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses -system.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses -system.l2cache.ReadSharedReq_misses::cpu.inst 278 # number of ReadSharedReq misses -system.l2cache.ReadSharedReq_misses::cpu.data 95 # number of ReadSharedReq misses -system.l2cache.ReadSharedReq_misses::total 373 # number of ReadSharedReq misses -system.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses -system.l2cache.demand_misses::cpu.data 168 # number of demand (read+write) misses -system.l2cache.demand_misses::total 446 # number of demand (read+write) misses -system.l2cache.overall_misses::cpu.inst 278 # number of overall misses -system.l2cache.overall_misses::cpu.data 168 # number of overall misses -system.l2cache.overall_misses::total 446 # number of overall misses -system.l2cache.ReadExReq_miss_latency::cpu.data 7437000 # number of ReadExReq miss cycles -system.l2cache.ReadExReq_miss_latency::total 7437000 # number of ReadExReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.inst 29087000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::cpu.data 9786000 # number of ReadSharedReq miss cycles -system.l2cache.ReadSharedReq_miss_latency::total 38873000 # number of ReadSharedReq miss cycles -system.l2cache.demand_miss_latency::cpu.inst 29087000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::cpu.data 17223000 # number of demand (read+write) miss cycles -system.l2cache.demand_miss_latency::total 46310000 # number of demand (read+write) miss cycles -system.l2cache.overall_miss_latency::cpu.inst 29087000 # number of overall miss cycles -system.l2cache.overall_miss_latency::cpu.data 17223000 # number of overall miss cycles -system.l2cache.overall_miss_latency::total 46310000 # number of overall miss cycles -system.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) -system.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) -system.l2cache.ReadSharedReq_accesses::cpu.inst 281 # number of ReadSharedReq accesses(hits+misses) -system.l2cache.ReadSharedReq_accesses::cpu.data 95 # number of ReadSharedReq accesses(hits+misses) -system.l2cache.ReadSharedReq_accesses::total 376 # number of ReadSharedReq accesses(hits+misses) -system.l2cache.demand_accesses::cpu.inst 281 # number of demand (read+write) accesses -system.l2cache.demand_accesses::cpu.data 168 # number of demand (read+write) accesses -system.l2cache.demand_accesses::total 449 # number of demand (read+write) accesses -system.l2cache.overall_accesses::cpu.inst 281 # number of overall (read+write) accesses -system.l2cache.overall_accesses::cpu.data 168 # number of overall (read+write) accesses -system.l2cache.overall_accesses::total 449 # number of overall (read+write) accesses -system.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.l2cache.ReadSharedReq_miss_rate::cpu.inst 0.989324 # miss rate for ReadSharedReq accesses -system.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses -system.l2cache.ReadSharedReq_miss_rate::total 0.992021 # miss rate for ReadSharedReq accesses -system.l2cache.demand_miss_rate::cpu.inst 0.989324 # miss rate for demand accesses -system.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.l2cache.demand_miss_rate::total 0.993318 # miss rate for demand accesses -system.l2cache.overall_miss_rate::cpu.inst 0.989324 # miss rate for overall accesses -system.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.l2cache.overall_miss_rate::total 0.993318 # miss rate for overall accesses -system.l2cache.ReadExReq_avg_miss_latency::cpu.data 101876.712329 # average ReadExReq miss latency -system.l2cache.ReadExReq_avg_miss_latency::total 101876.712329 # average ReadExReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 104629.496403 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 103010.526316 # average ReadSharedReq miss latency -system.l2cache.ReadSharedReq_avg_miss_latency::total 104217.158177 # average ReadSharedReq miss latency -system.l2cache.demand_avg_miss_latency::cpu.inst 104629.496403 # average overall miss latency -system.l2cache.demand_avg_miss_latency::cpu.data 102517.857143 # average overall miss latency -system.l2cache.demand_avg_miss_latency::total 103834.080717 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.inst 104629.496403 # average overall miss latency -system.l2cache.overall_avg_miss_latency::cpu.data 102517.857143 # average overall miss latency -system.l2cache.overall_avg_miss_latency::total 103834.080717 # average overall miss latency -system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses -system.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses -system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 278 # number of ReadSharedReq MSHR misses -system.l2cache.ReadSharedReq_mshr_misses::cpu.data 95 # number of ReadSharedReq MSHR misses -system.l2cache.ReadSharedReq_mshr_misses::total 373 # number of ReadSharedReq MSHR misses -system.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses -system.l2cache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses -system.l2cache.demand_mshr_misses::total 446 # number of demand (read+write) MSHR misses -system.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses -system.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses -system.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses -system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5977000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadExReq_mshr_miss_latency::total 5977000 # number of ReadExReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 23527000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7886000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.ReadSharedReq_mshr_miss_latency::total 31413000 # number of ReadSharedReq MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.inst 23527000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::cpu.data 13863000 # number of demand (read+write) MSHR miss cycles -system.l2cache.demand_mshr_miss_latency::total 37390000 # number of demand (read+write) MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.inst 23527000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::cpu.data 13863000 # number of overall MSHR miss cycles -system.l2cache.overall_mshr_miss_latency::total 37390000 # number of overall MSHR miss cycles -system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.989324 # mshr miss rate for ReadSharedReq accesses -system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses -system.l2cache.ReadSharedReq_mshr_miss_rate::total 0.992021 # mshr miss rate for ReadSharedReq accesses -system.l2cache.demand_mshr_miss_rate::cpu.inst 0.989324 # mshr miss rate for demand accesses -system.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.l2cache.demand_mshr_miss_rate::total 0.993318 # mshr miss rate for demand accesses -system.l2cache.overall_mshr_miss_rate::cpu.inst 0.989324 # mshr miss rate for overall accesses -system.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.l2cache.overall_mshr_miss_rate::total 0.993318 # mshr miss rate for overall accesses -system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81876.712329 # average ReadExReq mshr miss latency -system.l2cache.ReadExReq_avg_mshr_miss_latency::total 81876.712329 # average ReadExReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 84629.496403 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 83010.526316 # average ReadSharedReq mshr miss latency -system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 84217.158177 # average ReadSharedReq mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 84629.496403 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::cpu.data 82517.857143 # average overall mshr miss latency -system.l2cache.demand_avg_mshr_miss_latency::total 83834.080717 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 84629.496403 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::cpu.data 82517.857143 # average overall mshr miss latency -system.l2cache.overall_avg_mshr_miss_latency::total 83834.080717 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 446 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 373 # Transaction distribution -system.membus.trans_dist::ReadExReq 73 # Transaction distribution -system.membus.trans_dist::ReadExResp 73 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 373 # Transaction distribution -system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 892 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 28544 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 446 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 446 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 446 # Request fanout histogram -system.membus.reqLayer0.occupancy 446000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer0.occupancy 2377500 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 3.7 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini --- a/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,203 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=atomic -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=AtomicSimpleCPU -children=dtb interrupts isa itb tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -fastmem=false -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -simulate_data_stalls=false -simulate_inst_stalls=false -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -width=1 -workload=system.cpu.workload -dcache_port=system.membus.slave[2] -icache_port=system.membus.slave[1] - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ALPHA/tests/opt/quick/se/30.eon/alpha/tru64/simple-atomic -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/eon -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=Null -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.icache_port system.cpu.dcache_port - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=0:134217727 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/simerr --- a/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/simerr Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,52 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -getting pixel output filename pixels_out.cook -opening control file chair.control.cook -opening camera file chair.camera -opening surfaces file chair.surfaces -reading data -processing 8parts -Grid measure is 6 by 3.0001 by 6 -cell dimension is 0.863065 -Creating grid for list of length 21 -Grid size = 7 by 4 by 7 -Total occupancy = 236 -reading control stream -reading camera stream -Writing to chair.cook.ppm -calculating 15 by 15 image with 196 samples -col 0. . . -col 1. . . -col 2. . . -col 3. . . -col 4. . . -col 5. . . -col 6. . . -col 7. . . -col 8. . . -col 9. . . -col 10. . . -col 11. . . -col 12. . . -col 13. . . -col 14. . . -Writing to chair.cook.ppm -0 8 14 -1 8 14 -2 8 14 -3 8 14 -4 8 14 -5 8 14 -6 8 14 -7 8 14 -8 8 14 -9 8 14 -10 8 14 -11 8 14 -12 8 14 -13 8 14 -14 8 14 -warn: ignoring syscall sigprocmask(1, ...) diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/simout --- a/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/simout Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,17 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/se/30.eon/alpha/tru64/simple-atomic/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/se/30.eon/alpha/tru64/simple-atomic/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 21 2016 14:09:27 -gem5 executing on e108600-lin, pid 4289 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eon/alpha/tru64/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/30.eon/alpha/tru64/simple-atomic - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Eon, Version 1.1 -info: Increasing stack size by one page. -OO-style eon Time= 0.183333 -Exiting @ tick 199332411500 because target called exit() diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt --- a/tests/quick/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,167 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.199332 # Number of seconds simulated -sim_ticks 199332411500 # Number of ticks simulated -final_tick 199332411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2875345 # Simulator instruction rate (inst/s) -host_op_rate 2875345 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1437672996 # Simulator tick rate (ticks/s) -host_mem_usage 248448 # Number of bytes of host memory used -host_seconds 138.65 # Real time elapsed on the host -sim_insts 398664595 # Number of instructions simulated -sim_ops 398664595 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 199332411500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 1594658604 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 662449271 # Number of bytes read from this memory -system.physmem.bytes_read::total 2257107875 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1594658604 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1594658604 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 492356798 # Number of bytes written to this memory -system.physmem.bytes_written::total 492356798 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 398664651 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 94754489 # Number of read requests responded to by this memory -system.physmem.num_reads::total 493419140 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 73520729 # Number of write requests responded to by this memory -system.physmem.num_writes::total 73520729 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7999996548 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3323339471 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 11323336020 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7999996548 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7999996548 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 2470028804 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2470028804 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7999996548 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5793368275 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 13793364824 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 199332411500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 94754489 # DTB read hits -system.cpu.dtb.read_misses 21 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 94754510 # DTB read accesses -system.cpu.dtb.write_hits 73520729 # DTB write hits -system.cpu.dtb.write_misses 35 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 73520764 # DTB write accesses -system.cpu.dtb.data_hits 168275218 # DTB hits -system.cpu.dtb.data_misses 56 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 168275274 # DTB accesses -system.cpu.itb.fetch_hits 398664651 # ITB hits -system.cpu.itb.fetch_misses 173 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 398664824 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 199332411500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 398664824 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 398664595 # Number of instructions committed -system.cpu.committedOps 398664595 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 316365907 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 155295119 # Number of float alu accesses -system.cpu.num_func_calls 16015498 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 25997787 # number of instructions that are conditional controls -system.cpu.num_int_insts 316365907 # number of integer instructions -system.cpu.num_fp_insts 155295119 # number of float instructions -system.cpu.num_int_register_reads 372938760 # number of times the integer registers were read -system.cpu.num_int_register_writes 159335860 # number of times the integer registers were written -system.cpu.num_fp_register_reads 151776196 # number of times the floating registers were read -system.cpu.num_fp_register_writes 100196481 # number of times the floating registers were written -system.cpu.num_mem_refs 168275274 # number of memory refs -system.cpu.num_load_insts 94754510 # Number of load instructions -system.cpu.num_store_insts 73520764 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 398664824 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 44587532 # Number of branches fetched -system.cpu.op_class::No_OpClass 23123356 5.80% 5.80% # Class of executed instruction -system.cpu.op_class::IntAlu 141652555 35.53% 41.33% # Class of executed instruction -system.cpu.op_class::IntMult 2124322 0.53% 41.86% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 41.86% # Class of executed instruction -system.cpu.op_class::FloatAdd 35620060 8.93% 50.80% # Class of executed instruction -system.cpu.op_class::FloatCmp 7072549 1.77% 52.57% # Class of executed instruction -system.cpu.op_class::FloatCvt 2735231 0.69% 53.26% # Class of executed instruction -system.cpu.op_class::FloatMult 16498021 4.14% 57.40% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 57.40% # Class of executed instruction -system.cpu.op_class::FloatDiv 1563283 0.39% 57.79% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::MemRead 46072315 11.56% 69.35% # Class of executed instruction -system.cpu.op_class::MemWrite 30396984 7.62% 76.97% # Class of executed instruction -system.cpu.op_class::FloatMemRead 48682195 12.21% 89.18% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 43123780 10.82% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 398664651 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 199332411500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 493419140 # Transaction distribution -system.membus.trans_dist::ReadResp 493419140 # Transaction distribution -system.membus.trans_dist::WriteReq 73520729 # Transaction distribution -system.membus.trans_dist::WriteResp 73520729 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 797329302 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 336550436 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1133879738 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1594658604 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1154806069 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 2749464673 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 566939869 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 566939869 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 566939869 # Request fanout histogram - ----------- End Simulation Statistics ---------- diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini --- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,203 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=atomic -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=AtomicSimpleCPU -children=dtb interrupts isa itb tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -fastmem=false -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -simulate_data_stalls=false -simulate_inst_stalls=false -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -width=1 -workload=system.cpu.workload -dcache_port=system.membus.slave[2] -icache_port=system.membus.slave[1] - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=vortex lendian.raw -cwd=build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-atomic -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/vortex -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=Null -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.icache_port system.cpu.dcache_port - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=0:134217727 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/simerr --- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/simerr Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,6 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(1, ...) diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/simout --- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/simout Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,14 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-atomic/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-atomic/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 21 2016 14:09:27 -gem5 executing on e108600-lin, pid 4293 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/50.vortex/alpha/tru64/simple-atomic - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Exiting @ tick 44221003000 because target called exit() diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.msg --- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.msg Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,158 +0,0 @@ - - SYSTEM TYPE... - __ZTC__ := False - __UNIX__ := True - __RISC__ := True - SPEC_CPU2000_LP64 := True - __MAC__ := False - __BCC__ := False - __BORLANDC__ := False - __GUI__ := False - __WTC__ := False - __HP__ := False - - CODE OPTIONS... - __MACROIZE_HM__ := True - __MACROIZE_MEM__ := True - ENV01 := True - USE_HPP_STYPE_HDRS := False - USE_H_STYPE_HDRS := False - - CODE INCLUSION PARAMETERS... - INCLUDE_ALL_CODE := False - INCLUDE_DELETE_CODE := True - __SWAP_GRP_POS__ := True - __INCLUDE_MTRX__ := False - __BAD_CODE__ := False - API_INCLUDE := False - BE_CAREFUL := False - OLDWAY := False - NOTUSED := False - - SYSTEM PARAMETERS... - EXT_ENUM := 999999999L - CHUNK_CONSTANT := 55555555 - CORE_CONSTANT := 55555555 - CORE_LIMIT := 20971520 - CorePage_Size := 384000 - ALIGN_BYTES := True - CORE_BLOCK_ALIGN := 8 - FAR_MEM := False - - MEMORY MANAGEMENT PARAMETERS... - SYSTEM_ALLOC := True - SYSTEM_FREESTORE := True - __NO_DISKCACHE__ := False - __FREEZE_VCHUNKS__ := True - __FREEZE_GRP_PACKETS__ := True - __MINIMIZE_TREE_CACHE__:= True - - SYSTEM STD PARAMETERS... - __STDOUT__ := False - NULL := 0 - LPTR := False - False_Status := 1 - True_Status := 0 - LARGE := True - TWOBYTE_BOOL := False - __NOSTR__ := False - - MEMORY VALIDATION PARAMETERS... - CORE_CRC_CHECK := False - VALIDATE_MEM_CHUNKS := False - - SYSTEM DEBUG OPTIONS... - DEBUG := False - MCSTAT := False - TRACKBACK := False - FLUSH_FILES := False - DEBUG_CORE0 := False - DEBUG_RISC := False - __TREE_BUG__ := False - __TRACK_FILE_READS__ := False - PAGE_SPACE := False - LEAVE_NO_TRACE := True - NULL_TRACE_STRS := False - - TIME PARAMETERS... - CLOCK_IS_LONG := False - __DISPLAY_TIME__ := False - __TREE_TIME__ := False - __DISPLAY_ERRORS__ := False - - API MACROS... - __BMT01__ := True - OPTIMIZE := True - - END OF DEFINES. - - - - ... IMPLODE MEMORY ... - - SWAP to DiskCache := False - - FREEZE_GRP_PACKETS:= True - - QueBug := 1000 - - sizeof(boolean) = 4 - sizeof(sizetype) = 4 - sizeof(chunkstruc) = 32 - - sizeof(shorttype ) = 2 - sizeof(idtype ) = 2 - sizeof(sizetype ) = 4 - sizeof(indextype ) = 4 - sizeof(numtype ) = 4 - sizeof(handletype) = 4 - sizeof(tokentype ) = 8 - - sizeof(short ) = 2 - sizeof(int ) = 4 - - sizeof(lt64 ) = 4 - sizeof(farlongtype) = 4 - sizeof(long ) = 8 - sizeof(longaddr ) = 8 - - sizeof(float ) = 4 - sizeof(double ) = 8 - - sizeof(addrtype ) = 8 - sizeof(char * ) = 8 - ALLOC CORE_1 :: 16 - BHOOLE NATH - - OPEN File ./input/lendian.rnv - *Status = 0 - DB HDR restored from FileVbn[ 0] - DB BlkDirOffset : @ 2030c0 - DB BlkDirChunk : Chunk[ 10] AT Vbn[3146] - DB BlkTknChunk : Chunk[ 11] AT Vbn[3147] - DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148] - DB Handle Chunk's StackPtr = 20797 - - DB[ 1] LOADED; Handles= 20797 - KERNEL in CORE[ 1] Restored @ 4005c800 - - OPEN File ./input/lendian.wnv - *Status = 0 - DB HDR restored from FileVbn[ 0] - DB BlkDirOffset : @ 21c40 - DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81] - DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82] - DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83] - DB Handle Chunk's StackPtr = 17 - - DB[ 2] LOADED; Handles= 17 - VORTEx_Status == -8 || fffffff8 - - BE HERE NOW !!! - - - - ... VORTEx ON LINE ... - - - ... END OF SESSION ... diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.out --- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.out Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,258 +0,0 @@ - CREATE Db Header and Db Primal ... - NEW DB [ 3] Created. - -VORTEX INPUT PARAMETERS:: - MESSAGE FileName: smred.msg - OUTPUT FileName: smred.out - DISK CACHE FileName: NULL - PART DB FileName: parts.db - DRAW DB FileName: draw.db - PERSON DB FileName: emp.db - PERSONS Data FileName: ./input/persons.250 - PARTS Count : 100 - OUTER Loops : 1 - INNER Loops : 1 - LOOKUP Parts : 25 - DELETE Parts : 10 - STUFF Parts : 10 - DEPTH Traverse: 5 - % DECREASE Parts : 0 - % INCREASE LookUps : 0 - % INCREASE Deletes : 0 - % INCREASE Stuffs : 0 - FREEZE_PACKETS : 1 - ALLOC_CHUNKS : 10000 - EXTEND_CHUNKS : 5000 - DELETE Draw objects : True - DELETE Part objects : False - QUE_BUG : 1000 - VOID_BOUNDARY : 67108864 - VOID_RESERVE : 1048576 - - COMMIT_DBS : False - - - - BMT TEST :: files... - EdbName := PartLib - EdbFileName := parts.db - DrwName := DrawLib - DrwFileName := draw.db - EmpName := PersonLib - EmpFileName := emp.db - - Swap to DiskCache := False - Freeze the cache := True - - - BMT TEST :: parms... - DeBug modulo := 1000 - Create Parts count:= 100 - Outer Loops := 1 - Inner Loops := 1 - Look Ups := 25 - Delete Parts := 10 - Stuff Parts := 10 - Traverse Limit := 5 - Delete Draws := True - Delete Parts := False - Delete ALL Parts := after every Outer Loop - - INITIALIZE LIBRARY :: - - INITIALIZE SCHEMA :: - Primal_CreateDb Accessed !!! - CREATE Db Header and Db Primal ... - NEW DB [ 4] Created. - PartLibCreate:: Db[ 4]; VpartsDir= 1 - - Part Count= 1 - - Initialize the Class maps - LIST HEADS loaded ... DbListHead_Class = 207 - DbListNode_Class = 206 - -...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated. - - -...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated. - - Primal_CreateDb Accessed !!! - CREATE Db Header and Db Primal ... - NEW DB [ 5] Created. - DrawLibCreate:: Db[ 5]; VpartsDir= 1 - - Initialize the Class maps of this schema. - Primal_CreateDb Accessed !!! - CREATE Db Header and Db Primal ... - NEW DB [ 6] Created. - - ***NOTE*** Persons Library Extended! - - Create <131072> Persons. - ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ; - - LAST Person Read:: - ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ; - - BUILD for class:: - - if (link[1].length >= 5) :: - - Build Query2 for
class:: - - if (State == CA || State == T*) - - Build Query1 for class:: - - if (LastName >= H* && LastName <= P* && Query0(Residence)) :: - - BUILD for class:: - - if (Id >= 3000 - && (Id >= 3000 && Id <= 3001) - && Id >= 3002) - - BUILD for class:: - - if (Nam == Pre* - || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post - || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post) - && Id <= 7) - SEED := 1008; Swap = False; RgnEntries = 135 - - OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10. - - Create 100 New Parts - Create Part 1. Token[ 4: 2]. - - < 100> Parts Created. CurrentId= 100 - - Connect each instantiated Part TO 3 unique Parts - Connect Part 1. Token[ 4: 2] - Connect Part 25. Token[ 4: 26] FromList= 26. - Connect Part 12. Token[ 4: 13] FromList= 13. - Connect Part 59. Token[ 4: 60] FromList= 60. - - SET entries:: - 1. [ 5: 5] := <1 >; @[: 6] - Iteration count = 100 - - SET entries:: - 1. [ 5: 39] := <14 >; - Iteration count = 12 - - SET entries:: - 1. [ 5: 23] := <8 >; @[: 24] - Iteration count = 12 - - LIST entries:: - 1. [ 5: 23] - Iteration count = 12 - - SET entries:: - Iteration count = 250 - - COMMIT All Image copies:: Release=; Max Parts= 100 - < 100> Part images' Committed. - < 0> are Named. - < 50> Point images' Committed. - < 81> Person images' Committed. - - COMMIT Parts(* 100) - - Commit TestObj_Class in DB. - ItNum 0. Token[ 0: 0]. TestObj Committed. - < 0> TestObj images' Committed. - - Commit CartesianPoint_Class in DB. - ItNum 0. Token[ 0: 0]. CartesianPoint Committed. - < 0> CartesianPoint images' Committed. - - BEGIN Inner Loop Sequence::. - - INNER LOOP [ 1: 1] : - - LOOK UP 25 Random Parts and Export each Part. - - LookUp for 26 parts; Asserts = 8 - Asserts = 2; NULL Asserts = 3. - Asserts = 0; NULL Asserts = 5. - Asserts = 0; NULL Asserts = 0. - Asserts = 0; NULL Asserts = 5. - Asserts = 60; NULL Asserts = 0. - - DELETE 10 Random Parts. - - PartDelete :: Token[ 4: 91]. - PartDisconnect:: Token[ 4: 91] id:= 90 for each link. - DisConnect link [ 0]:= 50; PartToken[ 51: 51]. - DisConnect link [ 1]:= 17; PartToken[ 18: 18]. - DisConnect link [ 2]:= 72; PartToken[ 73: 73]. - DeleteFromList:: Vchunk[ 4: 91]. (* 1) - DisConnect FromList[ 0]:= 56; Token[ 57: 57]. - Vlists[ 89] := 100; - - Delete for 11 parts; - - Traverse Count= 0 - - TRAVERSE PartId[ 6] and all Connections to 5 Levels - SEED In Traverse Part [ 4: 65] @ Level = 4. - - Traverse Count= 357 - Traverse Asserts = 5. True Tests = 1 - < 5> DrawObj objects DELETED. - < 2> are Named. - < 2> Point objects DELETED. - - CREATE 10 Additional Parts - - Create 10 New Parts - Create Part 101. Token[ 4: 102]. - - < 10> Parts Created. CurrentId= 110 - - Connect each instantiated Part TO 3 unique Parts - - COMMIT All Image copies:: Release=; Max Parts= 110 - < 81> Part images' Committed. - < 0> are Named. - < 38> Point images' Committed. - < 31> Person images' Committed. - - COMMIT Parts(* 100) - - Commit TestObj_Class in DB. - ItNum 0. Token[ 3: 4]. TestObj Committed. - < 15> TestObj images' Committed. - - Commit CartesianPoint_Class in DB. - ItNum 0. Token[ 3: 3]. CartesianPoint Committed. - < 16> CartesianPoint images' Committed. - - DELETE All TestObj objects; - - Delete TestObj_Class in DB. - ItNum 0. Token[ 3: 4]. TestObj Deleted. - < 15> TestObj objects Deleted. - - Commit CartesianPoint_Class in DB. - ItNum 0. Token[ 3: 3]. CartesianPoint Deleted. - < 16> CartesianPoint objects Deleted. - - DELETE TestObj and Point objects... - - END INNER LOOP [ 1: 1]. - - DELETE All TestObj objects; - - Delete TestObj_Class in DB. - < 0> TestObj objects Deleted. - - Commit CartesianPoint_Class in DB. - < 0> CartesianPoint objects Deleted. - - DELETE TestObj and Point objects... - STATUS= -201 -V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1! diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt --- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,167 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.044221 # Number of seconds simulated -sim_ticks 44221003000 # Number of ticks simulated -final_tick 44221003000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2866684 # Simulator instruction rate (inst/s) -host_op_rate 2866683 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1434985124 # Simulator tick rate (ticks/s) -host_mem_usage 250568 # Number of bytes of host memory used -host_seconds 30.82 # Real time elapsed on the host -sim_insts 88340673 # Number of instructions simulated -sim_ops 88340673 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 44221003000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 353752292 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 126702647 # Number of bytes read from this memory -system.physmem.bytes_read::total 480454939 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 353752292 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 353752292 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 91652896 # Number of bytes written to this memory -system.physmem.bytes_written::total 91652896 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 88438073 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 20276638 # Number of read requests responded to by this memory -system.physmem.num_reads::total 108714711 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 14613377 # Number of write requests responded to by this memory -system.physmem.num_writes::total 14613377 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7999644241 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2865214229 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10864858470 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7999644241 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7999644241 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 2072610067 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2072610067 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7999644241 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4937824296 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 12937468537 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 44221003000 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20276638 # DTB read hits -system.cpu.dtb.read_misses 90148 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 20366786 # DTB read accesses -system.cpu.dtb.write_hits 14613377 # DTB write hits -system.cpu.dtb.write_misses 7252 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14620629 # DTB write accesses -system.cpu.dtb.data_hits 34890015 # DTB hits -system.cpu.dtb.data_misses 97400 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 34987415 # DTB accesses -system.cpu.itb.fetch_hits 88438073 # ITB hits -system.cpu.itb.fetch_misses 3934 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 88442007 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 44221003000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 88442007 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 88340673 # Number of instructions committed -system.cpu.committedOps 88340673 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 78039444 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 267757 # Number of float alu accesses -system.cpu.num_func_calls 3321606 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 8920848 # number of instructions that are conditional controls -system.cpu.num_int_insts 78039444 # number of integer instructions -system.cpu.num_fp_insts 267757 # number of float instructions -system.cpu.num_int_register_reads 105931758 # number of times the integer registers were read -system.cpu.num_int_register_writes 52319251 # number of times the integer registers were written -system.cpu.num_fp_register_reads 229023 # number of times the floating registers were read -system.cpu.num_fp_register_writes 227630 # number of times the floating registers were written -system.cpu.num_mem_refs 34987415 # number of memory refs -system.cpu.num_load_insts 20366786 # Number of load instructions -system.cpu.num_store_insts 14620629 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 88442007 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 13754477 # Number of branches fetched -system.cpu.op_class::No_OpClass 8748916 9.89% 9.89% # Class of executed instruction -system.cpu.op_class::IntAlu 44394799 50.20% 60.09% # Class of executed instruction -system.cpu.op_class::IntMult 41101 0.05% 60.14% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 60.14% # Class of executed instruction -system.cpu.op_class::FloatAdd 114304 0.13% 60.27% # Class of executed instruction -system.cpu.op_class::FloatCmp 84 0.00% 60.27% # Class of executed instruction -system.cpu.op_class::FloatCvt 113640 0.13% 60.40% # Class of executed instruction -system.cpu.op_class::FloatMult 50 0.00% 60.40% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 60.40% # Class of executed instruction -system.cpu.op_class::FloatDiv 37764 0.04% 60.44% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::MemRead 20366476 23.03% 83.47% # Class of executed instruction -system.cpu.op_class::MemWrite 14619024 16.53% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 310 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 1605 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 88438073 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 44221003000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 108714711 # Transaction distribution -system.membus.trans_dist::ReadResp 108714711 # Transaction distribution -system.membus.trans_dist::WriteReq 14613377 # Transaction distribution -system.membus.trans_dist::WriteResp 14613377 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 176876146 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 69780030 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 246656176 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 353752292 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 218355543 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 572107835 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 123328088 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 123328088 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 123328088 # Request fanout histogram - ----------- End Simulation Statistics ---------- diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini --- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,366 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=vortex lendian.raw -cwd=build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-timing -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/vortex -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=Null -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=0:134217727 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/simerr --- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/simerr Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,6 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(1, ...) diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/simout --- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/simout Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,14 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 21 2016 14:09:27 -gem5 executing on e108600-lin, pid 4294 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/50.vortex/alpha/tru64/simple-timing - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Exiting @ tick 134741611500 because target called exit() diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/smred.msg --- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/smred.msg Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,158 +0,0 @@ - - SYSTEM TYPE... - __ZTC__ := False - __UNIX__ := True - __RISC__ := True - SPEC_CPU2000_LP64 := True - __MAC__ := False - __BCC__ := False - __BORLANDC__ := False - __GUI__ := False - __WTC__ := False - __HP__ := False - - CODE OPTIONS... - __MACROIZE_HM__ := True - __MACROIZE_MEM__ := True - ENV01 := True - USE_HPP_STYPE_HDRS := False - USE_H_STYPE_HDRS := False - - CODE INCLUSION PARAMETERS... - INCLUDE_ALL_CODE := False - INCLUDE_DELETE_CODE := True - __SWAP_GRP_POS__ := True - __INCLUDE_MTRX__ := False - __BAD_CODE__ := False - API_INCLUDE := False - BE_CAREFUL := False - OLDWAY := False - NOTUSED := False - - SYSTEM PARAMETERS... - EXT_ENUM := 999999999L - CHUNK_CONSTANT := 55555555 - CORE_CONSTANT := 55555555 - CORE_LIMIT := 20971520 - CorePage_Size := 384000 - ALIGN_BYTES := True - CORE_BLOCK_ALIGN := 8 - FAR_MEM := False - - MEMORY MANAGEMENT PARAMETERS... - SYSTEM_ALLOC := True - SYSTEM_FREESTORE := True - __NO_DISKCACHE__ := False - __FREEZE_VCHUNKS__ := True - __FREEZE_GRP_PACKETS__ := True - __MINIMIZE_TREE_CACHE__:= True - - SYSTEM STD PARAMETERS... - __STDOUT__ := False - NULL := 0 - LPTR := False - False_Status := 1 - True_Status := 0 - LARGE := True - TWOBYTE_BOOL := False - __NOSTR__ := False - - MEMORY VALIDATION PARAMETERS... - CORE_CRC_CHECK := False - VALIDATE_MEM_CHUNKS := False - - SYSTEM DEBUG OPTIONS... - DEBUG := False - MCSTAT := False - TRACKBACK := False - FLUSH_FILES := False - DEBUG_CORE0 := False - DEBUG_RISC := False - __TREE_BUG__ := False - __TRACK_FILE_READS__ := False - PAGE_SPACE := False - LEAVE_NO_TRACE := True - NULL_TRACE_STRS := False - - TIME PARAMETERS... - CLOCK_IS_LONG := False - __DISPLAY_TIME__ := False - __TREE_TIME__ := False - __DISPLAY_ERRORS__ := False - - API MACROS... - __BMT01__ := True - OPTIMIZE := True - - END OF DEFINES. - - - - ... IMPLODE MEMORY ... - - SWAP to DiskCache := False - - FREEZE_GRP_PACKETS:= True - - QueBug := 1000 - - sizeof(boolean) = 4 - sizeof(sizetype) = 4 - sizeof(chunkstruc) = 32 - - sizeof(shorttype ) = 2 - sizeof(idtype ) = 2 - sizeof(sizetype ) = 4 - sizeof(indextype ) = 4 - sizeof(numtype ) = 4 - sizeof(handletype) = 4 - sizeof(tokentype ) = 8 - - sizeof(short ) = 2 - sizeof(int ) = 4 - - sizeof(lt64 ) = 4 - sizeof(farlongtype) = 4 - sizeof(long ) = 8 - sizeof(longaddr ) = 8 - - sizeof(float ) = 4 - sizeof(double ) = 8 - - sizeof(addrtype ) = 8 - sizeof(char * ) = 8 - ALLOC CORE_1 :: 16 - BHOOLE NATH - - OPEN File ./input/lendian.rnv - *Status = 0 - DB HDR restored from FileVbn[ 0] - DB BlkDirOffset : @ 2030c0 - DB BlkDirChunk : Chunk[ 10] AT Vbn[3146] - DB BlkTknChunk : Chunk[ 11] AT Vbn[3147] - DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148] - DB Handle Chunk's StackPtr = 20797 - - DB[ 1] LOADED; Handles= 20797 - KERNEL in CORE[ 1] Restored @ 4005c800 - - OPEN File ./input/lendian.wnv - *Status = 0 - DB HDR restored from FileVbn[ 0] - DB BlkDirOffset : @ 21c40 - DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81] - DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82] - DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83] - DB Handle Chunk's StackPtr = 17 - - DB[ 2] LOADED; Handles= 17 - VORTEx_Status == -8 || fffffff8 - - BE HERE NOW !!! - - - - ... VORTEx ON LINE ... - - - ... END OF SESSION ... diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/smred.out --- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/smred.out Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,258 +0,0 @@ - CREATE Db Header and Db Primal ... - NEW DB [ 3] Created. - -VORTEX INPUT PARAMETERS:: - MESSAGE FileName: smred.msg - OUTPUT FileName: smred.out - DISK CACHE FileName: NULL - PART DB FileName: parts.db - DRAW DB FileName: draw.db - PERSON DB FileName: emp.db - PERSONS Data FileName: ./input/persons.250 - PARTS Count : 100 - OUTER Loops : 1 - INNER Loops : 1 - LOOKUP Parts : 25 - DELETE Parts : 10 - STUFF Parts : 10 - DEPTH Traverse: 5 - % DECREASE Parts : 0 - % INCREASE LookUps : 0 - % INCREASE Deletes : 0 - % INCREASE Stuffs : 0 - FREEZE_PACKETS : 1 - ALLOC_CHUNKS : 10000 - EXTEND_CHUNKS : 5000 - DELETE Draw objects : True - DELETE Part objects : False - QUE_BUG : 1000 - VOID_BOUNDARY : 67108864 - VOID_RESERVE : 1048576 - - COMMIT_DBS : False - - - - BMT TEST :: files... - EdbName := PartLib - EdbFileName := parts.db - DrwName := DrawLib - DrwFileName := draw.db - EmpName := PersonLib - EmpFileName := emp.db - - Swap to DiskCache := False - Freeze the cache := True - - - BMT TEST :: parms... - DeBug modulo := 1000 - Create Parts count:= 100 - Outer Loops := 1 - Inner Loops := 1 - Look Ups := 25 - Delete Parts := 10 - Stuff Parts := 10 - Traverse Limit := 5 - Delete Draws := True - Delete Parts := False - Delete ALL Parts := after every Outer Loop - - INITIALIZE LIBRARY :: - - INITIALIZE SCHEMA :: - Primal_CreateDb Accessed !!! - CREATE Db Header and Db Primal ... - NEW DB [ 4] Created. - PartLibCreate:: Db[ 4]; VpartsDir= 1 - - Part Count= 1 - - Initialize the Class maps - LIST HEADS loaded ... DbListHead_Class = 207 - DbListNode_Class = 206 - -...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated. - - -...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated. - - Primal_CreateDb Accessed !!! - CREATE Db Header and Db Primal ... - NEW DB [ 5] Created. - DrawLibCreate:: Db[ 5]; VpartsDir= 1 - - Initialize the Class maps of this schema. - Primal_CreateDb Accessed !!! - CREATE Db Header and Db Primal ... - NEW DB [ 6] Created. - - ***NOTE*** Persons Library Extended! - - Create <131072> Persons. - ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ; - - LAST Person Read:: - ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ; - - BUILD for class:: - - if (link[1].length >= 5) :: - - Build Query2 for
class:: - - if (State == CA || State == T*) - - Build Query1 for class:: - - if (LastName >= H* && LastName <= P* && Query0(Residence)) :: - - BUILD for class:: - - if (Id >= 3000 - && (Id >= 3000 && Id <= 3001) - && Id >= 3002) - - BUILD for class:: - - if (Nam == Pre* - || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post - || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post) - && Id <= 7) - SEED := 1008; Swap = False; RgnEntries = 135 - - OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10. - - Create 100 New Parts - Create Part 1. Token[ 4: 2]. - - < 100> Parts Created. CurrentId= 100 - - Connect each instantiated Part TO 3 unique Parts - Connect Part 1. Token[ 4: 2] - Connect Part 25. Token[ 4: 26] FromList= 26. - Connect Part 12. Token[ 4: 13] FromList= 13. - Connect Part 59. Token[ 4: 60] FromList= 60. - - SET entries:: - 1. [ 5: 5] := <1 >; @[: 6] - Iteration count = 100 - - SET entries:: - 1. [ 5: 39] := <14 >; - Iteration count = 12 - - SET entries:: - 1. [ 5: 23] := <8 >; @[: 24] - Iteration count = 12 - - LIST entries:: - 1. [ 5: 23] - Iteration count = 12 - - SET entries:: - Iteration count = 250 - - COMMIT All Image copies:: Release=; Max Parts= 100 - < 100> Part images' Committed. - < 0> are Named. - < 50> Point images' Committed. - < 81> Person images' Committed. - - COMMIT Parts(* 100) - - Commit TestObj_Class in DB. - ItNum 0. Token[ 0: 0]. TestObj Committed. - < 0> TestObj images' Committed. - - Commit CartesianPoint_Class in DB. - ItNum 0. Token[ 0: 0]. CartesianPoint Committed. - < 0> CartesianPoint images' Committed. - - BEGIN Inner Loop Sequence::. - - INNER LOOP [ 1: 1] : - - LOOK UP 25 Random Parts and Export each Part. - - LookUp for 26 parts; Asserts = 8 - Asserts = 2; NULL Asserts = 3. - Asserts = 0; NULL Asserts = 5. - Asserts = 0; NULL Asserts = 0. - Asserts = 0; NULL Asserts = 5. - Asserts = 60; NULL Asserts = 0. - - DELETE 10 Random Parts. - - PartDelete :: Token[ 4: 91]. - PartDisconnect:: Token[ 4: 91] id:= 90 for each link. - DisConnect link [ 0]:= 50; PartToken[ 51: 51]. - DisConnect link [ 1]:= 17; PartToken[ 18: 18]. - DisConnect link [ 2]:= 72; PartToken[ 73: 73]. - DeleteFromList:: Vchunk[ 4: 91]. (* 1) - DisConnect FromList[ 0]:= 56; Token[ 57: 57]. - Vlists[ 89] := 100; - - Delete for 11 parts; - - Traverse Count= 0 - - TRAVERSE PartId[ 6] and all Connections to 5 Levels - SEED In Traverse Part [ 4: 65] @ Level = 4. - - Traverse Count= 357 - Traverse Asserts = 5. True Tests = 1 - < 5> DrawObj objects DELETED. - < 2> are Named. - < 2> Point objects DELETED. - - CREATE 10 Additional Parts - - Create 10 New Parts - Create Part 101. Token[ 4: 102]. - - < 10> Parts Created. CurrentId= 110 - - Connect each instantiated Part TO 3 unique Parts - - COMMIT All Image copies:: Release=; Max Parts= 110 - < 81> Part images' Committed. - < 0> are Named. - < 38> Point images' Committed. - < 31> Person images' Committed. - - COMMIT Parts(* 100) - - Commit TestObj_Class in DB. - ItNum 0. Token[ 3: 4]. TestObj Committed. - < 15> TestObj images' Committed. - - Commit CartesianPoint_Class in DB. - ItNum 0. Token[ 3: 3]. CartesianPoint Committed. - < 16> CartesianPoint images' Committed. - - DELETE All TestObj objects; - - Delete TestObj_Class in DB. - ItNum 0. Token[ 3: 4]. TestObj Deleted. - < 15> TestObj objects Deleted. - - Commit CartesianPoint_Class in DB. - ItNum 0. Token[ 3: 3]. CartesianPoint Deleted. - < 16> CartesianPoint objects Deleted. - - DELETE TestObj and Point objects... - - END INNER LOOP [ 1: 1]. - - DELETE All TestObj objects; - - Delete TestObj_Class in DB. - < 0> TestObj objects Deleted. - - Commit CartesianPoint_Class in DB. - < 0> CartesianPoint objects Deleted. - - DELETE TestObj and Point objects... - STATUS= -201 -V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1! diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt --- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,569 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.134921 # Number of seconds simulated -sim_ticks 134921160500 # Number of ticks simulated -final_tick 134921160500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1865262 # Simulator instruction rate (inst/s) -host_op_rate 1865262 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2848781352 # Simulator tick rate (ticks/s) -host_mem_usage 261840 # Number of bytes of host memory used -host_seconds 47.36 # Real time elapsed on the host -sim_insts 88340673 # Number of instructions simulated -sim_ops 88340673 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 134921160500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 369920 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10155520 # Number of bytes read from this memory -system.physmem.bytes_read::total 10525440 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 369920 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 369920 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7371264 # Number of bytes written to this memory -system.physmem.bytes_written::total 7371264 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 5780 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158680 # Number of read requests responded to by this memory -system.physmem.num_reads::total 164460 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115176 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115176 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2741749 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 75270031 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 78011781 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2741749 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2741749 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 54633862 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 54633862 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 54633862 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2741749 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 75270031 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 132645642 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 134921160500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20276638 # DTB read hits -system.cpu.dtb.read_misses 90148 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 20366786 # DTB read accesses -system.cpu.dtb.write_hits 14613377 # DTB write hits -system.cpu.dtb.write_misses 7252 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14620629 # DTB write accesses -system.cpu.dtb.data_hits 34890015 # DTB hits -system.cpu.dtb.data_misses 97400 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 34987415 # DTB accesses -system.cpu.itb.fetch_hits 88438074 # ITB hits -system.cpu.itb.fetch_misses 3934 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 88442008 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 134921160500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 269842321 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 88340673 # Number of instructions committed -system.cpu.committedOps 88340673 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 78039444 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 267757 # Number of float alu accesses -system.cpu.num_func_calls 3321606 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 8920848 # number of instructions that are conditional controls -system.cpu.num_int_insts 78039444 # number of integer instructions -system.cpu.num_fp_insts 267757 # number of float instructions -system.cpu.num_int_register_reads 105931758 # number of times the integer registers were read -system.cpu.num_int_register_writes 52319251 # number of times the integer registers were written -system.cpu.num_fp_register_reads 229023 # number of times the floating registers were read -system.cpu.num_fp_register_writes 227630 # number of times the floating registers were written -system.cpu.num_mem_refs 34987415 # number of memory refs -system.cpu.num_load_insts 20366786 # Number of load instructions -system.cpu.num_store_insts 14620629 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 269842321 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 13754477 # Number of branches fetched -system.cpu.op_class::No_OpClass 8748916 9.89% 9.89% # Class of executed instruction -system.cpu.op_class::IntAlu 44394799 50.20% 60.09% # Class of executed instruction -system.cpu.op_class::IntMult 41101 0.05% 60.14% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 60.14% # Class of executed instruction -system.cpu.op_class::FloatAdd 114304 0.13% 60.27% # Class of executed instruction -system.cpu.op_class::FloatCmp 84 0.00% 60.27% # Class of executed instruction -system.cpu.op_class::FloatCvt 113640 0.13% 60.40% # Class of executed instruction -system.cpu.op_class::FloatMult 50 0.00% 60.40% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 60.40% # Class of executed instruction -system.cpu.op_class::FloatDiv 37764 0.04% 60.44% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.44% # Class of executed instruction -system.cpu.op_class::MemRead 20366476 23.03% 83.47% # Class of executed instruction -system.cpu.op_class::MemWrite 14619024 16.53% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 310 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 1605 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 88438073 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 134921160500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 200248 # number of replacements -system.cpu.dcache.tags.tagsinuse 4078.334496 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 34685671 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 204344 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 169.741568 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 990170500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4078.334496 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.995687 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.995687 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 445 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3604 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 69984374 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 69984374 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 134921160500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 20215872 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20215872 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 14469799 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 14469799 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 34685671 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34685671 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34685671 # number of overall hits -system.cpu.dcache.overall_hits::total 34685671 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 60766 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 60766 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 143578 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 143578 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 204344 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 204344 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 204344 # number of overall misses -system.cpu.dcache.overall_misses::total 204344 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2178421500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2178421500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8412226500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8412226500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 10590648000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 10590648000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 10590648000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 10590648000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 34890015 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002997 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002997 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009825 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.009825 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.005857 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.005857 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.005857 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.005857 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35849.348320 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 35849.348320 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 58589.940659 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 58589.940659 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 51827.545707 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 51827.545707 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 51827.545707 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 51827.545707 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 167988 # number of writebacks -system.cpu.dcache.writebacks::total 167988 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60766 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 60766 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143578 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143578 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 204344 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 204344 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 204344 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 204344 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2117655500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2117655500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8268648500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8268648500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10386304000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10386304000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10386304000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10386304000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009825 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34849.348320 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34849.348320 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 57589.940659 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 57589.940659 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50827.545707 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 50827.545707 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50827.545707 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 50827.545707 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 134921160500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 74391 # number of replacements -system.cpu.icache.tags.tagsinuse 1870.340281 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 88361638 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 76436 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1156.021220 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1870.340281 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.913252 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.913252 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 2045 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 110 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 191 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1708 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.998535 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 176952584 # Number of tag accesses -system.cpu.icache.tags.data_accesses 176952584 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 134921160500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 88361638 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 88361638 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 88361638 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 88361638 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 88361638 # number of overall hits -system.cpu.icache.overall_hits::total 88361638 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 76436 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 76436 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 76436 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 76436 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 76436 # number of overall misses -system.cpu.icache.overall_misses::total 76436 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1283204500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1283204500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1283204500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1283204500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1283204500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1283204500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 88438074 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 88438074 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 88438074 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 88438074 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 88438074 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 88438074 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000864 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000864 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000864 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000864 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000864 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000864 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16787.959862 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16787.959862 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16787.959862 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16787.959862 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16787.959862 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16787.959862 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 74391 # number of writebacks -system.cpu.icache.writebacks::total 74391 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 76436 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 76436 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 76436 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 76436 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 76436 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 76436 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1206768500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1206768500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1206768500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1206768500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1206768500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1206768500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000864 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000864 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000864 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15787.959862 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15787.959862 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15787.959862 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 15787.959862 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15787.959862 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 15787.959862 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 134921160500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 133742 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31970.307618 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 388803 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 166510 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.335013 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 30559527000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 658.522624 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1588.260241 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 29723.524754 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.020097 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.048470 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.907090 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.975656 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 655 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 7663 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 24220 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 111 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4609862 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4609862 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 134921160500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 167988 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 167988 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 74391 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 74391 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 12665 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 12665 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 70656 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 70656 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 32999 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 32999 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 70656 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 45664 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 116320 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 70656 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 45664 # number of overall hits -system.cpu.l2cache.overall_hits::total 116320 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 130913 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 130913 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 5780 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 5780 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 27767 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 27767 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 5780 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 158680 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 164460 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 5780 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 158680 # number of overall misses -system.cpu.l2cache.overall_misses::total 164460 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7920287500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 7920287500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 349972000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 349972000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1679964000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 1679964000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 349972000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9600251500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 9950223500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 349972000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9600251500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 9950223500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 167988 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 167988 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 74391 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 74391 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 143578 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 143578 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 76436 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 76436 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 60766 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 60766 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 76436 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 204344 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 280780 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 76436 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 204344 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 280780 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911790 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.911790 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.075619 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.075619 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.456950 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.456950 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.075619 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.776534 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.585725 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.075619 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.776534 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.585725 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.389572 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.389572 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60548.788927 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60548.788927 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60502.178845 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60502.178845 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60548.788927 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500.702672 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 60502.392679 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60548.788927 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500.702672 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 60502.392679 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 115177 # number of writebacks -system.cpu.l2cache.writebacks::total 115177 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 106 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 106 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130913 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 130913 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 5780 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 5780 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 27767 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 27767 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 5780 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 158680 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 164460 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 5780 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 158680 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 164460 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6611157500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6611157500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 292172000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 292172000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1402294000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1402294000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 292172000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8013451500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8305623500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 292172000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8013451500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8305623500 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911790 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911790 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.075619 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.075619 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.456950 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.456950 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.075619 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.776534 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.585725 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.075619 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.776534 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.585725 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.389572 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.389572 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50548.788927 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50548.788927 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50502.178845 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50502.178845 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50548.788927 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500.702672 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50502.392679 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50548.788927 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500.702672 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50502.392679 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 555419 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 274639 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 4055 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4055 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 134921160500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 137202 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 283165 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 74391 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 50825 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143578 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143578 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 76436 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 60766 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 227263 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 608936 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 836199 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9652928 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23829248 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 33482176 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 133742 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 7371328 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 414522 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.009782 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.098421 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 410467 99.02% 99.02% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4055 0.98% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 414522 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 520088500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 114654000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 306516000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 294252 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 129792 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 134921160500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 33547 # Transaction distribution -system.membus.trans_dist::WritebackDirty 115176 # Transaction distribution -system.membus.trans_dist::CleanEvict 14616 # Transaction distribution -system.membus.trans_dist::ReadExReq 130913 # Transaction distribution -system.membus.trans_dist::ReadExResp 130913 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 33547 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 458712 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 458712 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17896704 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17896704 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 164460 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 164460 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 164460 # Request fanout histogram -system.membus.reqLayer0.occupancy 755151000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 822300000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.6 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/config.ini --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/config.ini Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,1381 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000 -time_sync_spin_threshold=100000 - -[system] -type=System -children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges=0:268435455:0:0:0:0 -memories=system.mem_ctrls -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.sys_port_proxy.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=RubyTester -check_flush=false -checks_to_complete=100 -clk_domain=system.clk_domain -deadlock_threshold=50000 -default_p_state=UNDEFINED -eventq_index=0 -num_cpus=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -system=system -wakeup_frequency=10 -cpuInstDataPort=system.ruby.l1_cntrl0.sequencer.slave[0] - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000 - -[system.mem_ctrls] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -page_policy=open_adaptive -power_model=Null -range=0:268435455:5:19:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10 -static_frontend_latency=10 -tBURST=5 -tCCD_L=0 -tCK=1 -tCL=14 -tCS=3 -tRAS=35 -tRCD=14 -tREFI=7800 -tRFC=260 -tRP=14 -tRRD=6 -tRRD_L=0 -tRTP=8 -tRTW=3 -tWR=15 -tWTR=8 -tXAW=30 -tXP=6 -tXPDLL=0 -tXS=270 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.ruby.dir_cntrl0.memory - -[system.ruby] -type=RubySystem -children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network -access_backing_store=false -all_instructions=false -block_size_bytes=64 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hot_lines=false -memory_size_bits=48 -num_of_sequencers=1 -number_of_virtual_networks=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -phys_mem=Null -power_model=Null -randomization=true - -[system.ruby.clk_domain] -type=SrcClockDomain -clock=1 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.ruby.dir_cntrl0] -type=Directory_Controller -children=directory requestToDir responseFromDir responseFromMemory responseToDir -buffer_size=0 -clk_domain=system.ruby.clk_domain -cluster_id=0 -default_p_state=UNDEFINED -directory=system.ruby.dir_cntrl0.directory -directory_latency=6 -eventq_index=0 -number_of_TBEs=256 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -recycle_latency=10 -requestToDir=system.ruby.dir_cntrl0.requestToDir -responseFromDir=system.ruby.dir_cntrl0.responseFromDir -responseFromMemory=system.ruby.dir_cntrl0.responseFromMemory -responseToDir=system.ruby.dir_cntrl0.responseToDir -ruby_system=system.ruby -system=system -to_mem_ctrl_latency=1 -transitions_per_cycle=32 -version=0 -memory=system.mem_ctrls.port - -[system.ruby.dir_cntrl0.directory] -type=RubyDirectoryMemory -eventq_index=0 -numa_high_bit=5 -size=268435456 -version=0 - -[system.ruby.dir_cntrl0.requestToDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[5] - -[system.ruby.dir_cntrl0.responseFromDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[6] - -[system.ruby.dir_cntrl0.responseFromMemory] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false - -[system.ruby.dir_cntrl0.responseToDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[6] - -[system.ruby.l1_cntrl0] -type=L1Cache_Controller -children=L1Dcache L1Icache mandatoryQueue optionalQueue prefetcher requestFromL1Cache requestToL1Cache responseFromL1Cache responseToL1Cache sequencer unblockFromL1Cache -L1Dcache=system.ruby.l1_cntrl0.L1Dcache -L1Icache=system.ruby.l1_cntrl0.L1Icache -buffer_size=0 -clk_domain=system.ruby.clk_domain -cluster_id=0 -default_p_state=UNDEFINED -enable_prefetch=false -eventq_index=0 -l1_request_latency=2 -l1_response_latency=2 -l2_select_num_bits=0 -mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue -number_of_TBEs=256 -optionalQueue=system.ruby.l1_cntrl0.optionalQueue -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -prefetcher=system.ruby.l1_cntrl0.prefetcher -recycle_latency=10 -requestFromL1Cache=system.ruby.l1_cntrl0.requestFromL1Cache -requestToL1Cache=system.ruby.l1_cntrl0.requestToL1Cache -responseFromL1Cache=system.ruby.l1_cntrl0.responseFromL1Cache -responseToL1Cache=system.ruby.l1_cntrl0.responseToL1Cache -ruby_system=system.ruby -send_evictions=false -sequencer=system.ruby.l1_cntrl0.sequencer -system=system -to_l2_latency=1 -transitions_per_cycle=32 -unblockFromL1Cache=system.ruby.l1_cntrl0.unblockFromL1Cache -version=0 - -[system.ruby.l1_cntrl0.L1Dcache] -type=RubyCache -children=replacement_policy -assoc=2 -block_size=0 -dataAccessLatency=1 -dataArrayBanks=1 -eventq_index=0 -is_icache=false -replacement_policy=system.ruby.l1_cntrl0.L1Dcache.replacement_policy -resourceStalls=false -ruby_system=system.ruby -size=256 -start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 - -[system.ruby.l1_cntrl0.L1Dcache.replacement_policy] -type=PseudoLRUReplacementPolicy -assoc=2 -block_size=64 -eventq_index=0 -size=256 - -[system.ruby.l1_cntrl0.L1Icache] -type=RubyCache -children=replacement_policy -assoc=2 -block_size=0 -dataAccessLatency=1 -dataArrayBanks=1 -eventq_index=0 -is_icache=true -replacement_policy=system.ruby.l1_cntrl0.L1Icache.replacement_policy -resourceStalls=false -ruby_system=system.ruby -size=256 -start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 - -[system.ruby.l1_cntrl0.L1Icache.replacement_policy] -type=PseudoLRUReplacementPolicy -assoc=2 -block_size=64 -eventq_index=0 -size=256 - -[system.ruby.l1_cntrl0.mandatoryQueue] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false - -[system.ruby.l1_cntrl0.optionalQueue] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false - -[system.ruby.l1_cntrl0.prefetcher] -type=Prefetcher -cross_page=false -eventq_index=0 -nonunit_filter=8 -num_startup_pfs=1 -num_streams=4 -pf_per_stream=1 -sys=system -train_misses=4 -unit_filter=8 - -[system.ruby.l1_cntrl0.requestFromL1Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[0] - -[system.ruby.l1_cntrl0.requestToL1Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[0] - -[system.ruby.l1_cntrl0.responseFromL1Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[1] - -[system.ruby.l1_cntrl0.responseToL1Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[1] - -[system.ruby.l1_cntrl0.sequencer] -type=RubySequencer -clk_domain=system.ruby.clk_domain -coreid=99 -dcache=system.ruby.l1_cntrl0.L1Dcache -dcache_hit_latency=1 -deadlock_threshold=500000 -default_p_state=UNDEFINED -eventq_index=0 -garnet_standalone=false -icache=system.ruby.l1_cntrl0.L1Icache -icache_hit_latency=1 -is_cpu_sequencer=true -max_outstanding_requests=16 -no_retry_on_stall=true -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -ruby_system=system.ruby -support_data_reqs=true -support_inst_reqs=true -system=system -using_ruby_tester=true -version=0 -slave=system.cpu.cpuInstDataPort[0] - -[system.ruby.l1_cntrl0.unblockFromL1Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[2] - -[system.ruby.l2_cntrl0] -type=L2Cache_Controller -children=DirRequestFromL2Cache L1RequestFromL2Cache L1RequestToL2Cache L2cache responseFromL2Cache responseToL2Cache unblockToL2Cache -DirRequestFromL2Cache=system.ruby.l2_cntrl0.DirRequestFromL2Cache -L1RequestFromL2Cache=system.ruby.l2_cntrl0.L1RequestFromL2Cache -L1RequestToL2Cache=system.ruby.l2_cntrl0.L1RequestToL2Cache -L2cache=system.ruby.l2_cntrl0.L2cache -buffer_size=0 -clk_domain=system.ruby.clk_domain -cluster_id=0 -default_p_state=UNDEFINED -eventq_index=0 -l2_request_latency=2 -l2_response_latency=2 -number_of_TBEs=256 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -recycle_latency=10 -responseFromL2Cache=system.ruby.l2_cntrl0.responseFromL2Cache -responseToL2Cache=system.ruby.l2_cntrl0.responseToL2Cache -ruby_system=system.ruby -system=system -to_l1_latency=1 -transitions_per_cycle=32 -unblockToL2Cache=system.ruby.l2_cntrl0.unblockToL2Cache -version=0 - -[system.ruby.l2_cntrl0.DirRequestFromL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[3] - -[system.ruby.l2_cntrl0.L1RequestFromL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[4] - -[system.ruby.l2_cntrl0.L1RequestToL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[3] - -[system.ruby.l2_cntrl0.L2cache] -type=RubyCache -children=replacement_policy -assoc=2 -block_size=0 -dataAccessLatency=1 -dataArrayBanks=1 -eventq_index=0 -is_icache=false -replacement_policy=system.ruby.l2_cntrl0.L2cache.replacement_policy -resourceStalls=false -ruby_system=system.ruby -size=512 -start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 - -[system.ruby.l2_cntrl0.L2cache.replacement_policy] -type=PseudoLRUReplacementPolicy -assoc=2 -block_size=64 -eventq_index=0 -size=512 - -[system.ruby.l2_cntrl0.responseFromL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[5] - -[system.ruby.l2_cntrl0.responseToL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[4] - -[system.ruby.l2_cntrl0.unblockToL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[2] - -[system.ruby.memctrl_clk_domain] -type=DerivedClockDomain -clk_divider=3 -clk_domain=system.ruby.clk_domain -eventq_index=0 - -[system.ruby.network] -type=SimpleNetwork -children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 routers0 routers1 routers2 routers3 -adaptive_routing=false -buffer_size=0 -clk_domain=system.ruby.clk_domain -control_msg_size=8 -default_p_state=UNDEFINED -endpoint_bandwidth=1000 -eventq_index=0 -ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2 -int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 -int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4 system.ruby.network.int_links5 -netifs= -number_of_virtual_networks=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 system.ruby.network.routers3 -ruby_system=system.ruby -topology=Crossbar -master=system.ruby.l1_cntrl0.requestToL1Cache.slave system.ruby.l1_cntrl0.responseToL1Cache.slave system.ruby.l2_cntrl0.unblockToL2Cache.slave system.ruby.l2_cntrl0.L1RequestToL2Cache.slave system.ruby.l2_cntrl0.responseToL2Cache.slave system.ruby.dir_cntrl0.requestToDir.slave system.ruby.dir_cntrl0.responseToDir.slave -slave=system.ruby.l1_cntrl0.requestFromL1Cache.master system.ruby.l1_cntrl0.responseFromL1Cache.master system.ruby.l1_cntrl0.unblockFromL1Cache.master system.ruby.l2_cntrl0.DirRequestFromL2Cache.master system.ruby.l2_cntrl0.L1RequestFromL2Cache.master system.ruby.l2_cntrl0.responseFromL2Cache.master system.ruby.dir_cntrl0.responseFromDir.master - -[system.ruby.network.ext_links0] -type=SimpleExtLink -bandwidth_factor=16 -eventq_index=0 -ext_node=system.ruby.l1_cntrl0 -int_node=system.ruby.network.routers0 -latency=1 -link_id=0 -weight=1 - -[system.ruby.network.ext_links1] -type=SimpleExtLink -bandwidth_factor=16 -eventq_index=0 -ext_node=system.ruby.l2_cntrl0 -int_node=system.ruby.network.routers1 -latency=1 -link_id=1 -weight=1 - -[system.ruby.network.ext_links2] -type=SimpleExtLink -bandwidth_factor=16 -eventq_index=0 -ext_node=system.ruby.dir_cntrl0 -int_node=system.ruby.network.routers2 -latency=1 -link_id=2 -weight=1 - -[system.ruby.network.int_link_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers15] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers16] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers17] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers18] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers19] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers20] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers21] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers22] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers23] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers24] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers25] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers26] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers27] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers28] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers29] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers30] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers31] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers32] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers33] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers34] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers35] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_links0] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers3 -eventq_index=0 -latency=1 -link_id=3 -src_node=system.ruby.network.routers0 -src_outport= -weight=1 - -[system.ruby.network.int_links1] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers3 -eventq_index=0 -latency=1 -link_id=4 -src_node=system.ruby.network.routers1 -src_outport= -weight=1 - -[system.ruby.network.int_links2] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers3 -eventq_index=0 -latency=1 -link_id=5 -src_node=system.ruby.network.routers2 -src_outport= -weight=1 - -[system.ruby.network.int_links3] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers0 -eventq_index=0 -latency=1 -link_id=6 -src_node=system.ruby.network.routers3 -src_outport= -weight=1 - -[system.ruby.network.int_links4] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers1 -eventq_index=0 -latency=1 -link_id=7 -src_node=system.ruby.network.routers3 -src_outport= -weight=1 - -[system.ruby.network.int_links5] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers2 -eventq_index=0 -latency=1 -link_id=8 -src_node=system.ruby.network.routers3 -src_outport= -weight=1 - -[system.ruby.network.routers0] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 -power_model=Null -router_id=0 -virt_nets=3 - -[system.ruby.network.routers0.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 -power_model=Null -router_id=1 -virt_nets=3 - -[system.ruby.network.routers1.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 -power_model=Null -router_id=2 -virt_nets=3 - -[system.ruby.network.routers2.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers3.port_buffers00 system.ruby.network.routers3.port_buffers01 system.ruby.network.routers3.port_buffers02 system.ruby.network.routers3.port_buffers03 system.ruby.network.routers3.port_buffers04 system.ruby.network.routers3.port_buffers05 system.ruby.network.routers3.port_buffers06 system.ruby.network.routers3.port_buffers07 system.ruby.network.routers3.port_buffers08 system.ruby.network.routers3.port_buffers09 system.ruby.network.routers3.port_buffers10 system.ruby.network.routers3.port_buffers11 system.ruby.network.routers3.port_buffers12 system.ruby.network.routers3.port_buffers13 system.ruby.network.routers3.port_buffers14 system.ruby.network.routers3.port_buffers15 system.ruby.network.routers3.port_buffers16 system.ruby.network.routers3.port_buffers17 -power_model=Null -router_id=3 -virt_nets=3 - -[system.ruby.network.routers3.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers15] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers16] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers17] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.sys_port_proxy] -type=RubyPortProxy -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_cpu_sequencer=true -no_retry_on_stall=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -ruby_system=system.ruby -support_data_reqs=true -support_inst_reqs=true -system=system -using_ruby_tester=false -version=0 -slave=system.system_port - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simerr --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simerr Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,8 +0,0 @@ -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) -warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simout --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simout Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,13 +0,0 @@ -Redirecting stdout to build/ALPHA_MESI_Two_Level/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_Two_Level/simout -Redirecting stderr to build/ALPHA_MESI_Two_Level/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_Two_Level/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 13 2016 20:28:06 -gem5 started Oct 13 2016 20:28:31 -gem5 executing on e108600-lin, pid 8234 -command line: /work/curdun01/gem5-external.hg/build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_Two_Level -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_Two_Level - -Global frequency set at 1000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 44021 because Ruby Tester completed diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,675 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000044 # Number of seconds simulated -sim_ticks 44021 # Number of ticks simulated -final_tick 44021 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 728057 # Simulator tick rate (ticks/s) -host_mem_usage 409368 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 44021 # Cumulative time (in ticks) in various power states -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 55424 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 55424 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 49920 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 49920 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 866 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 866 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 780 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 780 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 1259035460 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 1259035460 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 1134004225 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 1134004225 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 2393039686 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 2393039686 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 866 # Number of read requests accepted -system.mem_ctrls.writeReqs 780 # Number of write requests accepted -system.mem_ctrls.readBursts 866 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 780 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 45760 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 9664 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 40640 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 55424 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 49920 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 151 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 116 # Number of DRAM write bursts merged with an existing one -system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 210 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 228 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 223 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 54 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::9 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 184 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 198 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 203 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 50 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts -system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 44002 # Total gap between requests -system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 866 # Read request sizes (log2) -system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 780 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 430 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 284 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::2 1 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 7 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 29 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 41 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 41 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 48 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 41 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 39 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 39 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 39 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 39 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 93 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 915.268817 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 819.587468 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 267.362608 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 2 2.15% 2.15% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 5 5.38% 7.53% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 1 1.08% 8.60% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 3 3.23% 11.83% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 3 3.23% 15.05% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 4 4.30% 19.35% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 75 80.65% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 93 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 39 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 17.897436 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 17.675839 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 3.385689 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::14-15 5 12.82% 12.82% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-17 14 35.90% 48.72% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::18-19 15 38.46% 87.18% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::20-21 3 7.69% 94.87% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::22-23 1 2.56% 97.44% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::36-37 1 2.56% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 39 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 39 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.282051 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.268709 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 0.686284 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 33 84.62% 84.62% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 1 2.56% 87.18% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 5 12.82% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 39 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 12989 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 26574 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 3575 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 18.17 # Average queueing delay per DRAM burst -system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 37.17 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 1039.50 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 923.20 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 1259.04 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 1134.00 # Average system write bandwidth in MiByte/s -system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 15.33 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 8.12 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 7.21 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 1.66 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 25.56 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 627 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 627 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 87.69 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 94.43 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 26.73 # Average gap between requests -system.mem_ctrls.pageHitRate 90.94 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 685440 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 359352 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 8168160 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 5303520 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 3073200.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 8952648 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 72576 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.actPowerDownEnergy 11032464 # Energy for active power-down per rank (pJ) -system.mem_ctrls_0.prePowerDownEnergy 1920 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrls_0.totalEnergy 37649280 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 855.257264 # Core power per rank (mW) -system.mem_ctrls_0.totalIdleTime 24199 # Total Idle time Per DRAM Rank -system.mem_ctrls_0.memoryStateTime::IDLE 49 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 1300 # Time in different power states -system.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::PRE_PDN 5 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 18473 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 24194 # Time in different power states -system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 224352 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 3002880 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) -system.mem_ctrls_1.prePowerDownEnergy 2889984 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_1.selfRefreshEnergy 6763920 # Energy for self refresh per rank (pJ) -system.mem_ctrls_1.totalEnergy 14110416 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 320.538289 # Core power per rank (mW) -system.mem_ctrls_1.totalIdleTime 7526 # Total Idle time Per DRAM Rank -system.mem_ctrls_1.memoryStateTime::IDLE 7786 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 526 # Time in different power states -system.mem_ctrls_1.memoryStateTime::SREF 28183 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 7526 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 44021 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::UNDEFINED 44021 # Cumulative time (in ticks) in various power states -system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.pwrStateResidencyTicks::UNDEFINED 44021 # Cumulative time (in ticks) in various power states -system.ruby.delayHist::bucket_size 4 # delay histogram for all message -system.ruby.delayHist::max_bucket 39 # delay histogram for all message -system.ruby.delayHist::samples 6525 # delay histogram for all message -system.ruby.delayHist::mean 2.632031 # delay histogram for all message -system.ruby.delayHist::stdev 5.481611 # delay histogram for all message -system.ruby.delayHist | 5040 77.24% 77.24% | 61 0.93% 78.18% | 1056 16.18% 94.36% | 7 0.11% 94.47% | 285 4.37% 98.84% | 1 0.02% 98.85% | 1 0.02% 98.87% | 70 1.07% 99.94% | 0 0.00% 99.94% | 4 0.06% 100.00% # delay histogram for all message -system.ruby.delayHist::total 6525 # delay histogram for all message -system.ruby.outstanding_req_hist_seqr::bucket_size 2 -system.ruby.outstanding_req_hist_seqr::max_bucket 19 -system.ruby.outstanding_req_hist_seqr::samples 1019 -system.ruby.outstanding_req_hist_seqr::mean 15.664377 -system.ruby.outstanding_req_hist_seqr::gmean 15.560778 -system.ruby.outstanding_req_hist_seqr::stdev 1.199712 -system.ruby.outstanding_req_hist_seqr | 1 0.10% 0.10% | 2 0.20% 0.29% | 2 0.20% 0.49% | 2 0.20% 0.69% | 4 0.39% 1.08% | 2 0.20% 1.28% | 5 0.49% 1.77% | 199 19.53% 21.30% | 802 78.70% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist_seqr::total 1019 -system.ruby.latency_hist_seqr::bucket_size 128 -system.ruby.latency_hist_seqr::max_bucket 1279 -system.ruby.latency_hist_seqr::samples 1004 -system.ruby.latency_hist_seqr::mean 684.454183 -system.ruby.latency_hist_seqr::gmean 346.202279 -system.ruby.latency_hist_seqr::stdev 321.934539 -system.ruby.latency_hist_seqr | 155 15.44% 15.44% | 28 2.79% 18.23% | 4 0.40% 18.63% | 3 0.30% 18.92% | 6 0.60% 19.52% | 263 26.20% 45.72% | 367 36.55% 82.27% | 113 11.25% 93.53% | 53 5.28% 98.80% | 12 1.20% 100.00% -system.ruby.latency_hist_seqr::total 1004 -system.ruby.hit_latency_hist_seqr::bucket_size 1 -system.ruby.hit_latency_hist_seqr::max_bucket 9 -system.ruby.hit_latency_hist_seqr::samples 101 -system.ruby.hit_latency_hist_seqr::mean 1 -system.ruby.hit_latency_hist_seqr::gmean 1 -system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 101 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist_seqr::total 101 -system.ruby.miss_latency_hist_seqr::bucket_size 128 -system.ruby.miss_latency_hist_seqr::max_bucket 1279 -system.ruby.miss_latency_hist_seqr::samples 903 -system.ruby.miss_latency_hist_seqr::mean 760.898117 -system.ruby.miss_latency_hist_seqr::gmean 665.813242 -system.ruby.miss_latency_hist_seqr::stdev 238.941361 -system.ruby.miss_latency_hist_seqr | 54 5.98% 5.98% | 28 3.10% 9.08% | 4 0.44% 9.52% | 3 0.33% 9.86% | 6 0.66% 10.52% | 263 29.13% 39.65% | 367 40.64% 80.29% | 113 12.51% 92.80% | 53 5.87% 98.67% | 12 1.33% 100.00% -system.ruby.miss_latency_hist_seqr::total 903 -system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 44021 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.L1Dcache.demand_hits 101 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 855 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 956 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Icache.demand_misses 50 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Icache.demand_accesses 50 # Number of cache demand accesses -system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed -system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching -system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made -system.ruby.l1_cntrl0.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted -system.ruby.l1_cntrl0.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped -system.ruby.l1_cntrl0.prefetcher.hits 0 # number of prefetched blocks accessed -system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched -system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages -system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 44021 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 4 # Number of times a store aliased with a pending load -system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 86 # Number of times a store aliased with a pending store -system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 8 # Number of times a load aliased with a pending store -system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 44021 # Cumulative time (in ticks) in various power states -system.ruby.l2_cntrl0.L2cache.demand_hits 39 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 866 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 905 # Number of cache demand accesses -system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 44021 # Cumulative time (in ticks) in various power states -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 44021 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.percent_links_utilized 11.308239 -system.ruby.network.routers0.msg_count.Control::0 905 -system.ruby.network.routers0.msg_count.Request_Control::2 268 -system.ruby.network.routers0.msg_count.Response_Data::1 902 -system.ruby.network.routers0.msg_count.Response_Control::1 853 -system.ruby.network.routers0.msg_count.Response_Control::2 852 -system.ruby.network.routers0.msg_count.Writeback_Data::0 769 -system.ruby.network.routers0.msg_count.Writeback_Data::1 218 -system.ruby.network.routers0.msg_count.Writeback_Control::0 33 -system.ruby.network.routers0.msg_bytes.Control::0 7240 -system.ruby.network.routers0.msg_bytes.Request_Control::2 2144 -system.ruby.network.routers0.msg_bytes.Response_Data::1 64944 -system.ruby.network.routers0.msg_bytes.Response_Control::1 6824 -system.ruby.network.routers0.msg_bytes.Response_Control::2 6816 -system.ruby.network.routers0.msg_bytes.Writeback_Data::0 55368 -system.ruby.network.routers0.msg_bytes.Writeback_Data::1 15696 -system.ruby.network.routers0.msg_bytes.Writeback_Control::0 264 -system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 44021 # Cumulative time (in ticks) in various power states -system.ruby.network.routers1.percent_links_utilized 20.738398 -system.ruby.network.routers1.msg_count.Control::0 1771 -system.ruby.network.routers1.msg_count.Request_Control::2 268 -system.ruby.network.routers1.msg_count.Response_Data::1 2546 -system.ruby.network.routers1.msg_count.Response_Control::1 1796 -system.ruby.network.routers1.msg_count.Response_Control::2 852 -system.ruby.network.routers1.msg_count.Writeback_Data::0 769 -system.ruby.network.routers1.msg_count.Writeback_Data::1 218 -system.ruby.network.routers1.msg_count.Writeback_Control::0 33 -system.ruby.network.routers1.msg_bytes.Control::0 14168 -system.ruby.network.routers1.msg_bytes.Request_Control::2 2144 -system.ruby.network.routers1.msg_bytes.Response_Data::1 183312 -system.ruby.network.routers1.msg_bytes.Response_Control::1 14368 -system.ruby.network.routers1.msg_bytes.Response_Control::2 6816 -system.ruby.network.routers1.msg_bytes.Writeback_Data::0 55368 -system.ruby.network.routers1.msg_bytes.Writeback_Data::1 15696 -system.ruby.network.routers1.msg_bytes.Writeback_Control::0 264 -system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 44021 # Cumulative time (in ticks) in various power states -system.ruby.network.routers2.percent_links_utilized 9.432430 -system.ruby.network.routers2.msg_count.Control::0 866 -system.ruby.network.routers2.msg_count.Response_Data::1 1645 -system.ruby.network.routers2.msg_count.Response_Control::1 943 -system.ruby.network.routers2.msg_bytes.Control::0 6928 -system.ruby.network.routers2.msg_bytes.Response_Data::1 118440 -system.ruby.network.routers2.msg_bytes.Response_Control::1 7544 -system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 44021 # Cumulative time (in ticks) in various power states -system.ruby.network.routers3.percent_links_utilized 13.825598 -system.ruby.network.routers3.msg_count.Control::0 1771 -system.ruby.network.routers3.msg_count.Request_Control::2 268 -system.ruby.network.routers3.msg_count.Response_Data::1 2546 -system.ruby.network.routers3.msg_count.Response_Control::1 1796 -system.ruby.network.routers3.msg_count.Response_Control::2 852 -system.ruby.network.routers3.msg_count.Writeback_Data::0 769 -system.ruby.network.routers3.msg_count.Writeback_Data::1 218 -system.ruby.network.routers3.msg_count.Writeback_Control::0 33 -system.ruby.network.routers3.msg_bytes.Control::0 14168 -system.ruby.network.routers3.msg_bytes.Request_Control::2 2144 -system.ruby.network.routers3.msg_bytes.Response_Data::1 183312 -system.ruby.network.routers3.msg_bytes.Response_Control::1 14368 -system.ruby.network.routers3.msg_bytes.Response_Control::2 6816 -system.ruby.network.routers3.msg_bytes.Writeback_Data::0 55368 -system.ruby.network.routers3.msg_bytes.Writeback_Data::1 15696 -system.ruby.network.routers3.msg_bytes.Writeback_Control::0 264 -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 44021 # Cumulative time (in ticks) in various power states -system.ruby.network.msg_count.Control 5313 -system.ruby.network.msg_count.Request_Control 804 -system.ruby.network.msg_count.Response_Data 7639 -system.ruby.network.msg_count.Response_Control 7944 -system.ruby.network.msg_count.Writeback_Data 2961 -system.ruby.network.msg_count.Writeback_Control 99 -system.ruby.network.msg_byte.Control 42504 -system.ruby.network.msg_byte.Request_Control 6432 -system.ruby.network.msg_byte.Response_Data 550008 -system.ruby.network.msg_byte.Response_Control 63552 -system.ruby.network.msg_byte.Writeback_Data 213192 -system.ruby.network.msg_byte.Writeback_Control 792 -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 44021 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.throttle0.link_utilization 10.437064 -system.ruby.network.routers0.throttle0.msg_count.Request_Control::2 268 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 902 -system.ruby.network.routers0.throttle0.msg_count.Response_Control::1 803 -system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::2 2144 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1 64944 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1 6424 -system.ruby.network.routers0.throttle1.link_utilization 12.179414 -system.ruby.network.routers0.throttle1.msg_count.Control::0 905 -system.ruby.network.routers0.throttle1.msg_count.Response_Control::1 50 -system.ruby.network.routers0.throttle1.msg_count.Response_Control::2 852 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::0 769 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::1 218 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 33 -system.ruby.network.routers0.throttle1.msg_bytes.Control::0 7240 -system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::1 400 -system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2 6816 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0 55368 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1 15696 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 264 -system.ruby.network.routers1.throttle0.link_utilization 21.989505 -system.ruby.network.routers1.throttle0.msg_count.Control::0 905 -system.ruby.network.routers1.throttle0.msg_count.Response_Data::1 864 -system.ruby.network.routers1.throttle0.msg_count.Response_Control::1 911 -system.ruby.network.routers1.throttle0.msg_count.Response_Control::2 852 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::0 769 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::1 218 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0 33 -system.ruby.network.routers1.throttle0.msg_bytes.Control::0 7240 -system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::1 62208 -system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::1 7288 -system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::2 6816 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::0 55368 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::1 15696 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 264 -system.ruby.network.routers1.throttle1.link_utilization 19.487290 -system.ruby.network.routers1.throttle1.msg_count.Control::0 866 -system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 268 -system.ruby.network.routers1.throttle1.msg_count.Response_Data::1 1682 -system.ruby.network.routers1.throttle1.msg_count.Response_Control::1 885 -system.ruby.network.routers1.throttle1.msg_bytes.Control::0 6928 -system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2 2144 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1 121104 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1 7080 -system.ruby.network.routers2.throttle0.link_utilization 9.050226 -system.ruby.network.routers2.throttle0.msg_count.Control::0 866 -system.ruby.network.routers2.throttle0.msg_count.Response_Data::1 780 -system.ruby.network.routers2.throttle0.msg_count.Response_Control::1 82 -system.ruby.network.routers2.throttle0.msg_bytes.Control::0 6928 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1 56160 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1 656 -system.ruby.network.routers2.throttle1.link_utilization 9.814634 -system.ruby.network.routers2.throttle1.msg_count.Response_Data::1 865 -system.ruby.network.routers2.throttle1.msg_count.Response_Control::1 861 -system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1 62280 -system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1 6888 -system.ruby.network.routers3.throttle0.link_utilization 10.437064 -system.ruby.network.routers3.throttle0.msg_count.Request_Control::2 268 -system.ruby.network.routers3.throttle0.msg_count.Response_Data::1 902 -system.ruby.network.routers3.throttle0.msg_count.Response_Control::1 803 -system.ruby.network.routers3.throttle0.msg_bytes.Request_Control::2 2144 -system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1 64944 -system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1 6424 -system.ruby.network.routers3.throttle1.link_utilization 21.989505 -system.ruby.network.routers3.throttle1.msg_count.Control::0 905 -system.ruby.network.routers3.throttle1.msg_count.Response_Data::1 864 -system.ruby.network.routers3.throttle1.msg_count.Response_Control::1 911 -system.ruby.network.routers3.throttle1.msg_count.Response_Control::2 852 -system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::0 769 -system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::1 218 -system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::0 33 -system.ruby.network.routers3.throttle1.msg_bytes.Control::0 7240 -system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::1 62208 -system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::1 7288 -system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::2 6816 -system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::0 55368 -system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::1 15696 -system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 264 -system.ruby.network.routers3.throttle2.link_utilization 9.050226 -system.ruby.network.routers3.throttle2.msg_count.Control::0 866 -system.ruby.network.routers3.throttle2.msg_count.Response_Data::1 780 -system.ruby.network.routers3.throttle2.msg_count.Response_Control::1 82 -system.ruby.network.routers3.throttle2.msg_bytes.Control::0 6928 -system.ruby.network.routers3.throttle2.msg_bytes.Response_Data::1 56160 -system.ruby.network.routers3.throttle2.msg_bytes.Response_Control::1 656 -system.ruby.delayVCHist.vnet_0::bucket_size 4 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::max_bucket 39 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::samples 2559 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::mean 5.696757 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::stdev 7.319490 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0 | 1396 54.55% 54.55% | 8 0.31% 54.87% | 792 30.95% 85.81% | 2 0.08% 85.89% | 285 11.14% 97.03% | 1 0.04% 97.07% | 1 0.04% 97.11% | 70 2.74% 99.84% | 0 0.00% 99.84% | 4 0.16% 100.00% # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::total 2559 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_1::bucket_size 2 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::max_bucket 19 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::samples 3698 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::mean 0.702001 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::stdev 2.286109 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1 | 3361 90.89% 90.89% | 15 0.41% 91.29% | 10 0.27% 91.56% | 43 1.16% 92.73% | 218 5.90% 98.62% | 46 1.24% 99.86% | 3 0.08% 99.95% | 2 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::total 3698 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::samples 268 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2 | 268 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::total 268 # delay histogram for vnet_2 -system.ruby.LD.latency_hist_seqr::bucket_size 128 -system.ruby.LD.latency_hist_seqr::max_bucket 1279 -system.ruby.LD.latency_hist_seqr::samples 50 -system.ruby.LD.latency_hist_seqr::mean 631.160000 -system.ruby.LD.latency_hist_seqr::gmean 197.121649 -system.ruby.LD.latency_hist_seqr::stdev 346.030868 -system.ruby.LD.latency_hist_seqr | 11 22.00% 22.00% | 0 0.00% 22.00% | 0 0.00% 22.00% | 0 0.00% 22.00% | 1 2.00% 24.00% | 12 24.00% 48.00% | 21 42.00% 90.00% | 5 10.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist_seqr::total 50 -system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 -system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 -system.ruby.LD.hit_latency_hist_seqr::samples 10 -system.ruby.LD.hit_latency_hist_seqr::mean 1 -system.ruby.LD.hit_latency_hist_seqr::gmean 1 -system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist_seqr::total 10 -system.ruby.LD.miss_latency_hist_seqr::bucket_size 128 -system.ruby.LD.miss_latency_hist_seqr::max_bucket 1279 -system.ruby.LD.miss_latency_hist_seqr::samples 40 -system.ruby.LD.miss_latency_hist_seqr::mean 788.700000 -system.ruby.LD.miss_latency_hist_seqr::gmean 738.614626 -system.ruby.LD.miss_latency_hist_seqr::stdev 152.194242 -system.ruby.LD.miss_latency_hist_seqr | 1 2.50% 2.50% | 0 0.00% 2.50% | 0 0.00% 2.50% | 0 0.00% 2.50% | 1 2.50% 5.00% | 12 30.00% 35.00% | 21 52.50% 87.50% | 5 12.50% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist_seqr::total 40 -system.ruby.ST.latency_hist_seqr::bucket_size 128 -system.ruby.ST.latency_hist_seqr::max_bucket 1279 -system.ruby.ST.latency_hist_seqr::samples 904 -system.ruby.ST.latency_hist_seqr::mean 719.136062 -system.ruby.ST.latency_hist_seqr::gmean 383.374715 -system.ruby.ST.latency_hist_seqr::stdev 298.133155 -system.ruby.ST.latency_hist_seqr | 114 12.61% 12.61% | 8 0.88% 13.50% | 4 0.44% 13.94% | 3 0.33% 14.27% | 5 0.55% 14.82% | 251 27.77% 42.59% | 346 38.27% 80.86% | 108 11.95% 92.81% | 53 5.86% 98.67% | 12 1.33% 100.00% -system.ruby.ST.latency_hist_seqr::total 904 -system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 -system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 -system.ruby.ST.hit_latency_hist_seqr::samples 91 -system.ruby.ST.hit_latency_hist_seqr::mean 1 -system.ruby.ST.hit_latency_hist_seqr::gmean 1 -system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 91 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist_seqr::total 91 -system.ruby.ST.miss_latency_hist_seqr::bucket_size 128 -system.ruby.ST.miss_latency_hist_seqr::max_bucket 1279 -system.ruby.ST.miss_latency_hist_seqr::samples 813 -system.ruby.ST.miss_latency_hist_seqr::mean 799.517835 -system.ruby.ST.miss_latency_hist_seqr::gmean 746.124556 -system.ruby.ST.miss_latency_hist_seqr::stdev 185.954617 -system.ruby.ST.miss_latency_hist_seqr | 23 2.83% 2.83% | 8 0.98% 3.81% | 4 0.49% 4.31% | 3 0.37% 4.67% | 5 0.62% 5.29% | 251 30.87% 36.16% | 346 42.56% 78.72% | 108 13.28% 92.00% | 53 6.52% 98.52% | 12 1.48% 100.00% -system.ruby.ST.miss_latency_hist_seqr::total 813 -system.ruby.IFETCH.latency_hist_seqr::bucket_size 32 -system.ruby.IFETCH.latency_hist_seqr::max_bucket 319 -system.ruby.IFETCH.latency_hist_seqr::samples 50 -system.ruby.IFETCH.latency_hist_seqr::mean 110.700000 -system.ruby.IFETCH.latency_hist_seqr::gmean 96.182985 -system.ruby.IFETCH.latency_hist_seqr::stdev 52.466607 -system.ruby.IFETCH.latency_hist_seqr | 1 2.00% 2.00% | 9 18.00% 20.00% | 11 22.00% 42.00% | 9 18.00% 60.00% | 13 26.00% 86.00% | 5 10.00% 96.00% | 0 0.00% 96.00% | 2 4.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist_seqr::total 50 -system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 32 -system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 319 -system.ruby.IFETCH.miss_latency_hist_seqr::samples 50 -system.ruby.IFETCH.miss_latency_hist_seqr::mean 110.700000 -system.ruby.IFETCH.miss_latency_hist_seqr::gmean 96.182985 -system.ruby.IFETCH.miss_latency_hist_seqr::stdev 52.466607 -system.ruby.IFETCH.miss_latency_hist_seqr | 1 2.00% 2.00% | 9 18.00% 20.00% | 11 22.00% 42.00% | 9 18.00% 60.00% | 13 26.00% 86.00% | 5 10.00% 96.00% | 0 0.00% 96.00% | 2 4.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.miss_latency_hist_seqr::total 50 -system.ruby.Directory_Controller.Fetch 866 0.00% 0.00% -system.ruby.Directory_Controller.Data 780 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 865 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 779 0.00% 0.00% -system.ruby.Directory_Controller.CleanReplacement 82 0.00% 0.00% -system.ruby.Directory_Controller.I.Fetch 866 0.00% 0.00% -system.ruby.Directory_Controller.M.Data 780 0.00% 0.00% -system.ruby.Directory_Controller.M.CleanReplacement 82 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 865 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 779 0.00% 0.00% -system.ruby.L1Cache_Controller.Load 51 0.00% 0.00% -system.ruby.L1Cache_Controller.Ifetch 55 0.00% 0.00% -system.ruby.L1Cache_Controller.Store 905 0.00% 0.00% -system.ruby.L1Cache_Controller.Inv 268 0.00% 0.00% -system.ruby.L1Cache_Controller.L1_Replacement 11918 0.00% 0.00% -system.ruby.L1Cache_Controller.Data_Exclusive 39 0.00% 0.00% -system.ruby.L1Cache_Controller.Data_all_Acks 863 0.00% 0.00% -system.ruby.L1Cache_Controller.Ack_all 1 0.00% 0.00% -system.ruby.L1Cache_Controller.WB_Ack 802 0.00% 0.00% -system.ruby.L1Cache_Controller.NP.Load 41 0.00% 0.00% -system.ruby.L1Cache_Controller.NP.Ifetch 50 0.00% 0.00% -system.ruby.L1Cache_Controller.NP.Store 813 0.00% 0.00% -system.ruby.L1Cache_Controller.I.L1_Replacement 92 0.00% 0.00% -system.ruby.L1Cache_Controller.S.Store 1 0.00% 0.00% -system.ruby.L1Cache_Controller.S.Inv 37 0.00% 0.00% -system.ruby.L1Cache_Controller.S.L1_Replacement 5 0.00% 0.00% -system.ruby.L1Cache_Controller.E.Inv 6 0.00% 0.00% -system.ruby.L1Cache_Controller.E.L1_Replacement 33 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Load 10 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Store 91 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Inv 43 0.00% 0.00% -system.ruby.L1Cache_Controller.M.L1_Replacement 769 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Inv 7 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.L1_Replacement 452 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Data_Exclusive 39 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Data_all_Acks 44 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.L1_Replacement 10567 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.Data_all_Acks 812 0.00% 0.00% -system.ruby.L1Cache_Controller.SM.Ack_all 1 0.00% 0.00% -system.ruby.L1Cache_Controller.IS_I.Data_all_Acks 7 0.00% 0.00% -system.ruby.L1Cache_Controller.M_I.Ifetch 5 0.00% 0.00% -system.ruby.L1Cache_Controller.M_I.Inv 175 0.00% 0.00% -system.ruby.L1Cache_Controller.M_I.WB_Ack 627 0.00% 0.00% -system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack 175 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GET_INSTR 50 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETS 41 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETX 813 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_UPGRADE 1 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTX 627 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTX_old 314 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement 568 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement_clean 551 0.00% 0.00% -system.ruby.L2Cache_Controller.Mem_Data 864 0.00% 0.00% -system.ruby.L2Cache_Controller.Mem_Ack 861 0.00% 0.00% -system.ruby.L2Cache_Controller.WB_Data 212 0.00% 0.00% -system.ruby.L2Cache_Controller.WB_Data_clean 6 0.00% 0.00% -system.ruby.L2Cache_Controller.Ack_all 50 0.00% 0.00% -system.ruby.L2Cache_Controller.Exclusive_Unblock 852 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GET_INSTR 44 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETS 39 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETX 783 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_PUTX_old 163 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GETS 1 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GETX 4 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_UPGRADE 1 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 44 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GET_INSTR 6 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETS 1 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETX 26 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement 568 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement_clean 26 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_PUTX 627 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 224 0.00% 0.00% -system.ruby.L2Cache_Controller.M_I.L1_PUTX_old 12 0.00% 0.00% -system.ruby.L2Cache_Controller.M_I.Mem_Ack 861 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.L1_PUTX_old 139 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.WB_Data 212 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.WB_Data_clean 6 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.Ack_all 6 0.00% 0.00% -system.ruby.L2Cache_Controller.I_I.Ack_all 44 0.00% 0.00% -system.ruby.L2Cache_Controller.ISS.L2_Replacement_clean 3 0.00% 0.00% -system.ruby.L2Cache_Controller.ISS.Mem_Data 38 0.00% 0.00% -system.ruby.L2Cache_Controller.IS.L2_Replacement_clean 96 0.00% 0.00% -system.ruby.L2Cache_Controller.IS.Mem_Data 44 0.00% 0.00% -system.ruby.L2Cache_Controller.IM.L2_Replacement_clean 132 0.00% 0.00% -system.ruby.L2Cache_Controller.IM.Mem_Data 782 0.00% 0.00% -system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 5 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.L2_Replacement_clean 26 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 847 0.00% 0.00% - ----------- End Simulation Statistics ---------- diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,1373 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000 -time_sync_spin_threshold=100000 - -[system] -type=System -children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges=0:268435455:0:0:0:0 -memories=system.mem_ctrls -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.sys_port_proxy.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=RubyTester -check_flush=false -checks_to_complete=100 -clk_domain=system.clk_domain -deadlock_threshold=50000 -default_p_state=UNDEFINED -eventq_index=0 -num_cpus=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -system=system -wakeup_frequency=10 -cpuInstDataPort=system.ruby.l1_cntrl0.sequencer.slave[0] - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000 - -[system.mem_ctrls] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -page_policy=open_adaptive -power_model=Null -range=0:268435455:5:19:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10 -static_frontend_latency=10 -tBURST=5 -tCCD_L=0 -tCK=1 -tCL=14 -tCS=3 -tRAS=35 -tRCD=14 -tREFI=7800 -tRFC=260 -tRP=14 -tRRD=6 -tRRD_L=0 -tRTP=8 -tRTW=3 -tWR=15 -tWTR=8 -tXAW=30 -tXP=6 -tXPDLL=0 -tXS=270 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.ruby.dir_cntrl0.memory - -[system.ruby] -type=RubySystem -children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network -access_backing_store=false -all_instructions=false -block_size_bytes=64 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hot_lines=false -memory_size_bits=48 -num_of_sequencers=1 -number_of_virtual_networks=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -phys_mem=Null -power_model=Null -randomization=true - -[system.ruby.clk_domain] -type=SrcClockDomain -clock=1 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.ruby.dir_cntrl0] -type=Directory_Controller -children=directory forwardFromDir requestToDir responseFromDir responseFromMemory responseToDir -buffer_size=0 -clk_domain=system.ruby.clk_domain -cluster_id=0 -default_p_state=UNDEFINED -directory=system.ruby.dir_cntrl0.directory -directory_latency=6 -eventq_index=0 -forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir -number_of_TBEs=256 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -recycle_latency=10 -requestToDir=system.ruby.dir_cntrl0.requestToDir -responseFromDir=system.ruby.dir_cntrl0.responseFromDir -responseFromMemory=system.ruby.dir_cntrl0.responseFromMemory -responseToDir=system.ruby.dir_cntrl0.responseToDir -ruby_system=system.ruby -system=system -to_memory_controller_latency=1 -transitions_per_cycle=32 -version=0 -memory=system.mem_ctrls.port - -[system.ruby.dir_cntrl0.directory] -type=RubyDirectoryMemory -eventq_index=0 -numa_high_bit=5 -size=268435456 -version=0 - -[system.ruby.dir_cntrl0.forwardFromDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[6] - -[system.ruby.dir_cntrl0.requestToDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[5] - -[system.ruby.dir_cntrl0.responseFromDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[5] - -[system.ruby.dir_cntrl0.responseFromMemory] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false - -[system.ruby.dir_cntrl0.responseToDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[6] - -[system.ruby.l1_cntrl0] -type=L1Cache_Controller -children=L1Dcache L1Icache mandatoryQueue requestFromL1Cache requestToL1Cache responseFromL1Cache responseToL1Cache sequencer triggerQueue -L1Dcache=system.ruby.l1_cntrl0.L1Dcache -L1Icache=system.ruby.l1_cntrl0.L1Icache -buffer_size=0 -clk_domain=system.ruby.clk_domain -cluster_id=0 -default_p_state=UNDEFINED -eventq_index=0 -l2_select_num_bits=0 -mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue -number_of_TBEs=256 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -recycle_latency=10 -requestFromL1Cache=system.ruby.l1_cntrl0.requestFromL1Cache -requestToL1Cache=system.ruby.l1_cntrl0.requestToL1Cache -request_latency=2 -responseFromL1Cache=system.ruby.l1_cntrl0.responseFromL1Cache -responseToL1Cache=system.ruby.l1_cntrl0.responseToL1Cache -ruby_system=system.ruby -send_evictions=false -sequencer=system.ruby.l1_cntrl0.sequencer -system=system -transitions_per_cycle=32 -triggerQueue=system.ruby.l1_cntrl0.triggerQueue -use_timeout_latency=50 -version=0 - -[system.ruby.l1_cntrl0.L1Dcache] -type=RubyCache -children=replacement_policy -assoc=2 -block_size=0 -dataAccessLatency=1 -dataArrayBanks=1 -eventq_index=0 -is_icache=false -replacement_policy=system.ruby.l1_cntrl0.L1Dcache.replacement_policy -resourceStalls=false -ruby_system=system.ruby -size=256 -start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 - -[system.ruby.l1_cntrl0.L1Dcache.replacement_policy] -type=PseudoLRUReplacementPolicy -assoc=2 -block_size=64 -eventq_index=0 -size=256 - -[system.ruby.l1_cntrl0.L1Icache] -type=RubyCache -children=replacement_policy -assoc=2 -block_size=0 -dataAccessLatency=1 -dataArrayBanks=1 -eventq_index=0 -is_icache=true -replacement_policy=system.ruby.l1_cntrl0.L1Icache.replacement_policy -resourceStalls=false -ruby_system=system.ruby -size=256 -start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 - -[system.ruby.l1_cntrl0.L1Icache.replacement_policy] -type=PseudoLRUReplacementPolicy -assoc=2 -block_size=64 -eventq_index=0 -size=256 - -[system.ruby.l1_cntrl0.mandatoryQueue] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false - -[system.ruby.l1_cntrl0.requestFromL1Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[0] - -[system.ruby.l1_cntrl0.requestToL1Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[0] - -[system.ruby.l1_cntrl0.responseFromL1Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[1] - -[system.ruby.l1_cntrl0.responseToL1Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[1] - -[system.ruby.l1_cntrl0.sequencer] -type=RubySequencer -clk_domain=system.ruby.clk_domain -coreid=99 -dcache=system.ruby.l1_cntrl0.L1Dcache -dcache_hit_latency=1 -deadlock_threshold=500000 -default_p_state=UNDEFINED -eventq_index=0 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-L1RequestToL2Cache=system.ruby.l2_cntrl0.L1RequestToL2Cache -L2cache=system.ruby.l2_cntrl0.L2cache -buffer_size=0 -clk_domain=system.ruby.clk_domain -cluster_id=0 -default_p_state=UNDEFINED -eventq_index=0 -number_of_TBEs=256 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -recycle_latency=10 -request_latency=2 -responseFromL2Cache=system.ruby.l2_cntrl0.responseFromL2Cache -responseToL2Cache=system.ruby.l2_cntrl0.responseToL2Cache -response_latency=2 -ruby_system=system.ruby -system=system -transitions_per_cycle=32 -triggerQueue=system.ruby.l2_cntrl0.triggerQueue -version=0 - -[system.ruby.l2_cntrl0.GlobalRequestFromL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[2] - -[system.ruby.l2_cntrl0.GlobalRequestToL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[2] - -[system.ruby.l2_cntrl0.L1RequestFromL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[3] - -[system.ruby.l2_cntrl0.L1RequestToL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[3] - -[system.ruby.l2_cntrl0.L2cache] -type=RubyCache -children=replacement_policy -assoc=2 -block_size=0 -dataAccessLatency=1 -dataArrayBanks=1 -eventq_index=0 -is_icache=false -replacement_policy=system.ruby.l2_cntrl0.L2cache.replacement_policy -resourceStalls=false -ruby_system=system.ruby -size=512 -start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 - -[system.ruby.l2_cntrl0.L2cache.replacement_policy] -type=PseudoLRUReplacementPolicy -assoc=2 -block_size=64 -eventq_index=0 -size=512 - -[system.ruby.l2_cntrl0.responseFromL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[4] - -[system.ruby.l2_cntrl0.responseToL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[4] - -[system.ruby.l2_cntrl0.triggerQueue] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.memctrl_clk_domain] -type=DerivedClockDomain -clk_divider=3 -clk_domain=system.ruby.clk_domain -eventq_index=0 - -[system.ruby.network] -type=SimpleNetwork -children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 routers0 routers1 routers2 routers3 -adaptive_routing=false -buffer_size=0 -clk_domain=system.ruby.clk_domain -control_msg_size=8 -default_p_state=UNDEFINED -endpoint_bandwidth=1000 -eventq_index=0 -ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2 -int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 -int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4 system.ruby.network.int_links5 -netifs= -number_of_virtual_networks=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 system.ruby.network.routers3 -ruby_system=system.ruby -topology=Crossbar -master=system.ruby.l1_cntrl0.requestToL1Cache.slave system.ruby.l1_cntrl0.responseToL1Cache.slave system.ruby.l2_cntrl0.GlobalRequestToL2Cache.slave system.ruby.l2_cntrl0.L1RequestToL2Cache.slave system.ruby.l2_cntrl0.responseToL2Cache.slave system.ruby.dir_cntrl0.requestToDir.slave system.ruby.dir_cntrl0.responseToDir.slave -slave=system.ruby.l1_cntrl0.requestFromL1Cache.master system.ruby.l1_cntrl0.responseFromL1Cache.master system.ruby.l2_cntrl0.GlobalRequestFromL2Cache.master system.ruby.l2_cntrl0.L1RequestFromL2Cache.master system.ruby.l2_cntrl0.responseFromL2Cache.master system.ruby.dir_cntrl0.responseFromDir.master system.ruby.dir_cntrl0.forwardFromDir.master - -[system.ruby.network.ext_links0] -type=SimpleExtLink -bandwidth_factor=16 -eventq_index=0 -ext_node=system.ruby.l1_cntrl0 -int_node=system.ruby.network.routers0 -latency=1 -link_id=0 -weight=1 - -[system.ruby.network.ext_links1] -type=SimpleExtLink -bandwidth_factor=16 -eventq_index=0 -ext_node=system.ruby.l2_cntrl0 -int_node=system.ruby.network.routers1 -latency=1 -link_id=1 -weight=1 - -[system.ruby.network.ext_links2] -type=SimpleExtLink -bandwidth_factor=16 -eventq_index=0 -ext_node=system.ruby.dir_cntrl0 -int_node=system.ruby.network.routers2 -latency=1 -link_id=2 -weight=1 - -[system.ruby.network.int_link_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers15] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers16] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers17] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers18] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers19] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers20] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers21] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers22] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers23] -type=MessageBuffer -buffer_size=0 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-[system.ruby.network.int_link_buffers31] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers32] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers33] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers34] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers35] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_links0] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers3 -eventq_index=0 -latency=1 -link_id=3 -src_node=system.ruby.network.routers0 -src_outport= -weight=1 - -[system.ruby.network.int_links1] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers3 -eventq_index=0 -latency=1 -link_id=4 -src_node=system.ruby.network.routers1 -src_outport= -weight=1 - -[system.ruby.network.int_links2] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers3 -eventq_index=0 -latency=1 -link_id=5 -src_node=system.ruby.network.routers2 -src_outport= -weight=1 - -[system.ruby.network.int_links3] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers0 -eventq_index=0 -latency=1 -link_id=6 -src_node=system.ruby.network.routers3 -src_outport= -weight=1 - -[system.ruby.network.int_links4] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers1 -eventq_index=0 -latency=1 -link_id=7 -src_node=system.ruby.network.routers3 -src_outport= -weight=1 - -[system.ruby.network.int_links5] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers2 -eventq_index=0 -latency=1 -link_id=8 -src_node=system.ruby.network.routers3 -src_outport= -weight=1 - -[system.ruby.network.routers0] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 -power_model=Null -router_id=0 -virt_nets=3 - -[system.ruby.network.routers0.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 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-default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 -power_model=Null -router_id=1 -virt_nets=3 - -[system.ruby.network.routers1.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 -power_model=Null -router_id=2 -virt_nets=3 - -[system.ruby.network.routers2.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers3.port_buffers00 system.ruby.network.routers3.port_buffers01 system.ruby.network.routers3.port_buffers02 system.ruby.network.routers3.port_buffers03 system.ruby.network.routers3.port_buffers04 system.ruby.network.routers3.port_buffers05 system.ruby.network.routers3.port_buffers06 system.ruby.network.routers3.port_buffers07 system.ruby.network.routers3.port_buffers08 system.ruby.network.routers3.port_buffers09 system.ruby.network.routers3.port_buffers10 system.ruby.network.routers3.port_buffers11 system.ruby.network.routers3.port_buffers12 system.ruby.network.routers3.port_buffers13 system.ruby.network.routers3.port_buffers14 system.ruby.network.routers3.port_buffers15 system.ruby.network.routers3.port_buffers16 system.ruby.network.routers3.port_buffers17 -power_model=Null -router_id=3 -virt_nets=3 - -[system.ruby.network.routers3.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers15] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers16] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers17] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.sys_port_proxy] -type=RubyPortProxy -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_cpu_sequencer=true -no_retry_on_stall=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -ruby_system=system.ruby -support_data_reqs=true -support_inst_reqs=true -system=system -using_ruby_tester=false -version=0 -slave=system.system_port - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,8 +0,0 @@ -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) -warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,13 +0,0 @@ -Redirecting stdout to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout -Redirecting stderr to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 13 2016 20:30:58 -gem5 started Oct 13 2016 20:31:25 -gem5 executing on e108600-lin, pid 17788 -command line: /work/curdun01/gem5-external.hg/build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory - -Global frequency set at 1000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 57351 because Ruby Tester completed diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,649 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000057 # Number of seconds simulated -sim_ticks 57351 # Number of ticks simulated -final_tick 57351 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 527309 # Simulator tick rate (ticks/s) -host_mem_usage 410220 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 57351 # Cumulative time (in ticks) in various power states -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 56384 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 56384 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 50624 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 50624 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 881 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 881 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 791 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 791 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 983138916 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 983138916 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 882704748 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 882704748 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 1865843664 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 1865843664 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 881 # Number of read requests accepted -system.mem_ctrls.writeReqs 791 # Number of write requests accepted -system.mem_ctrls.readBursts 881 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 791 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 48256 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 8128 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 42816 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 56384 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 50624 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 127 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 95 # Number of DRAM write bursts merged with an existing one -system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 222 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 247 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 228 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 57 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::9 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 195 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 221 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 201 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 52 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts -system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 57270 # Total gap between requests -system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 881 # Read request sizes (log2) -system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 791 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 553 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 198 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::2 3 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 25 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 26 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 31 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 45 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 43 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 39 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 39 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 39 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 42 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 39 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 38 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 39 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 38 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 38 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 38 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 103 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 877.359223 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 782.793653 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 281.638652 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 2 1.94% 1.94% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 4 3.88% 5.83% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 6 5.83% 11.65% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 6 5.83% 17.48% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 4 3.88% 21.36% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 3 2.91% 24.27% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 2 1.94% 26.21% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 76 73.79% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 103 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 38 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 19.447368 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 19.196443 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 3.599530 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::14-15 1 2.63% 2.63% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-17 9 23.68% 26.32% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::18-19 10 26.32% 52.63% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::20-21 13 34.21% 86.84% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::22-23 3 7.89% 94.74% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::24-25 1 2.63% 97.37% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::36-37 1 2.63% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 38 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 38 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 17.605263 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 17.559134 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 1.284828 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 13 34.21% 34.21% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 1 2.63% 36.84% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 13 34.21% 71.05% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 10 26.32% 97.37% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::20 1 2.63% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 38 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 10814 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 25140 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 3770 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 14.34 # Average queueing delay per DRAM burst -system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 33.34 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 841.42 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 746.56 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 983.14 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 882.70 # Average system write bandwidth in MiByte/s -system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 12.41 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 6.57 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 5.83 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 1.47 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 24.63 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 656 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 661 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 87.00 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 94.97 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 34.25 # Average gap between requests -system.mem_ctrls.pageHitRate 90.83 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 756840 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 397992 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 8613696 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 5587488 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 4302480.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 11006472 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 91776 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.actPowerDownEnergy 15034776 # Energy for active power-down per rank (pJ) -system.mem_ctrls_0.prePowerDownEnergy 1536 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrls_0.totalEnergy 45793056 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 798.470053 # Core power per rank (mW) -system.mem_ctrls_0.totalIdleTime 32938 # Total Idle time Per DRAM Rank -system.mem_ctrls_0.memoryStateTime::IDLE 43 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 1820 # Time in different power states -system.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::PRE_PDN 4 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 22513 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 32971 # Time in different power states -system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 224352 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 3002880 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) -system.mem_ctrls_1.prePowerDownEnergy 2889984 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_1.selfRefreshEnergy 9963120 # Energy for self refresh per rank (pJ) -system.mem_ctrls_1.totalEnergy 17309616 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 301.818905 # Core power per rank (mW) -system.mem_ctrls_1.totalIdleTime 7526 # Total Idle time Per DRAM Rank -system.mem_ctrls_1.memoryStateTime::IDLE 7786 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 526 # Time in different power states -system.mem_ctrls_1.memoryStateTime::SREF 41513 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 7526 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 57351 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::UNDEFINED 57351 # Cumulative time (in ticks) in various power states -system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.pwrStateResidencyTicks::UNDEFINED 57351 # Cumulative time (in ticks) in various power states -system.ruby.outstanding_req_hist_seqr::bucket_size 2 -system.ruby.outstanding_req_hist_seqr::max_bucket 19 -system.ruby.outstanding_req_hist_seqr::samples 1014 -system.ruby.outstanding_req_hist_seqr::mean 15.673570 -system.ruby.outstanding_req_hist_seqr::gmean 15.569970 -system.ruby.outstanding_req_hist_seqr::stdev 1.195975 -system.ruby.outstanding_req_hist_seqr | 1 0.10% 0.10% | 2 0.20% 0.30% | 2 0.20% 0.49% | 2 0.20% 0.69% | 4 0.39% 1.08% | 2 0.20% 1.28% | 3 0.30% 1.58% | 194 19.13% 20.71% | 804 79.29% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist_seqr::total 1014 -system.ruby.latency_hist_seqr::bucket_size 256 -system.ruby.latency_hist_seqr::max_bucket 2559 -system.ruby.latency_hist_seqr::samples 999 -system.ruby.latency_hist_seqr::mean 900.097097 -system.ruby.latency_hist_seqr::gmean 478.512857 -system.ruby.latency_hist_seqr::stdev 377.349343 -system.ruby.latency_hist_seqr | 145 14.51% 14.51% | 9 0.90% 15.42% | 4 0.40% 15.82% | 380 38.04% 53.85% | 412 41.24% 95.10% | 49 4.90% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist_seqr::total 999 -system.ruby.hit_latency_hist_seqr::bucket_size 1 -system.ruby.hit_latency_hist_seqr::max_bucket 9 -system.ruby.hit_latency_hist_seqr::samples 90 -system.ruby.hit_latency_hist_seqr::mean 1 -system.ruby.hit_latency_hist_seqr::gmean 1 -system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 90 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist_seqr::total 90 -system.ruby.miss_latency_hist_seqr::bucket_size 256 -system.ruby.miss_latency_hist_seqr::max_bucket 2559 -system.ruby.miss_latency_hist_seqr::samples 909 -system.ruby.miss_latency_hist_seqr::mean 989.116612 -system.ruby.miss_latency_hist_seqr::gmean 881.514808 -system.ruby.miss_latency_hist_seqr::stdev 261.625282 -system.ruby.miss_latency_hist_seqr | 55 6.05% 6.05% | 9 0.99% 7.04% | 4 0.44% 7.48% | 380 41.80% 49.28% | 412 45.32% 94.61% | 49 5.39% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist_seqr::total 909 -system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 57351 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.L1Dcache.demand_hits 88 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 859 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 947 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Icache.demand_hits 2 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Icache.demand_misses 50 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Icache.demand_accesses 52 # Number of cache demand accesses -system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 57351 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 2 # Number of times a store aliased with a pending load -system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 89 # Number of times a store aliased with a pending store -system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 5 # Number of times a load aliased with a pending store -system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 57351 # Cumulative time (in ticks) in various power states -system.ruby.l2_cntrl0.L2cache.demand_hits 28 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 881 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 909 # Number of cache demand accesses -system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 57351 # Cumulative time (in ticks) in various power states -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 57351 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.percent_links_utilized 8.691653 -system.ruby.network.routers0.msg_count.Request_Control::0 909 -system.ruby.network.routers0.msg_count.Response_Data::2 881 -system.ruby.network.routers0.msg_count.ResponseL2hit_Data::2 28 -system.ruby.network.routers0.msg_count.Writeback_Data::2 904 -system.ruby.network.routers0.msg_count.Writeback_Control::0 1808 -system.ruby.network.routers0.msg_count.Unblock_Control::2 908 -system.ruby.network.routers0.msg_bytes.Request_Control::0 7272 -system.ruby.network.routers0.msg_bytes.Response_Data::2 63432 -system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2 2016 -system.ruby.network.routers0.msg_bytes.Writeback_Data::2 65088 -system.ruby.network.routers0.msg_bytes.Writeback_Control::0 14464 -system.ruby.network.routers0.msg_bytes.Unblock_Control::2 7264 -system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 57351 # Cumulative time (in ticks) in various power states -system.ruby.network.routers1.percent_links_utilized 16.709822 -system.ruby.network.routers1.msg_count.Request_Control::0 909 -system.ruby.network.routers1.msg_count.Request_Control::1 881 -system.ruby.network.routers1.msg_count.Response_Data::2 1762 -system.ruby.network.routers1.msg_count.ResponseL2hit_Data::2 28 -system.ruby.network.routers1.msg_count.Writeback_Data::2 1695 -system.ruby.network.routers1.msg_count.Writeback_Control::0 1808 -system.ruby.network.routers1.msg_count.Writeback_Control::1 1582 -system.ruby.network.routers1.msg_count.Unblock_Control::2 1788 -system.ruby.network.routers1.msg_bytes.Request_Control::0 7272 -system.ruby.network.routers1.msg_bytes.Request_Control::1 7048 -system.ruby.network.routers1.msg_bytes.Response_Data::2 126864 -system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::2 2016 -system.ruby.network.routers1.msg_bytes.Writeback_Data::2 122040 -system.ruby.network.routers1.msg_bytes.Writeback_Control::0 14464 -system.ruby.network.routers1.msg_bytes.Writeback_Control::1 12656 -system.ruby.network.routers1.msg_bytes.Unblock_Control::2 14304 -system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 57351 # Cumulative time (in ticks) in various power states -system.ruby.network.routers2.percent_links_utilized 8.016861 -system.ruby.network.routers2.msg_count.Request_Control::1 881 -system.ruby.network.routers2.msg_count.Response_Data::2 881 -system.ruby.network.routers2.msg_count.Writeback_Data::2 791 -system.ruby.network.routers2.msg_count.Writeback_Control::1 1582 -system.ruby.network.routers2.msg_count.Unblock_Control::2 880 -system.ruby.network.routers2.msg_bytes.Request_Control::1 7048 -system.ruby.network.routers2.msg_bytes.Response_Data::2 63432 -system.ruby.network.routers2.msg_bytes.Writeback_Data::2 56952 -system.ruby.network.routers2.msg_bytes.Writeback_Control::1 12656 -system.ruby.network.routers2.msg_bytes.Unblock_Control::2 7040 -system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 57351 # Cumulative time (in ticks) in various power states -system.ruby.network.routers3.percent_links_utilized 11.139881 -system.ruby.network.routers3.msg_count.Request_Control::0 909 -system.ruby.network.routers3.msg_count.Request_Control::1 881 -system.ruby.network.routers3.msg_count.Response_Data::2 1762 -system.ruby.network.routers3.msg_count.ResponseL2hit_Data::2 28 -system.ruby.network.routers3.msg_count.Writeback_Data::2 1695 -system.ruby.network.routers3.msg_count.Writeback_Control::0 1808 -system.ruby.network.routers3.msg_count.Writeback_Control::1 1582 -system.ruby.network.routers3.msg_count.Unblock_Control::2 1788 -system.ruby.network.routers3.msg_bytes.Request_Control::0 7272 -system.ruby.network.routers3.msg_bytes.Request_Control::1 7048 -system.ruby.network.routers3.msg_bytes.Response_Data::2 126864 -system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::2 2016 -system.ruby.network.routers3.msg_bytes.Writeback_Data::2 122040 -system.ruby.network.routers3.msg_bytes.Writeback_Control::0 14464 -system.ruby.network.routers3.msg_bytes.Writeback_Control::1 12656 -system.ruby.network.routers3.msg_bytes.Unblock_Control::2 14304 -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 57351 # Cumulative time (in ticks) in various power states -system.ruby.network.msg_count.Request_Control 5370 -system.ruby.network.msg_count.Response_Data 5286 -system.ruby.network.msg_count.ResponseL2hit_Data 84 -system.ruby.network.msg_count.Writeback_Data 5085 -system.ruby.network.msg_count.Writeback_Control 10170 -system.ruby.network.msg_count.Unblock_Control 5364 -system.ruby.network.msg_byte.Request_Control 42960 -system.ruby.network.msg_byte.Response_Data 380592 -system.ruby.network.msg_byte.ResponseL2hit_Data 6048 -system.ruby.network.msg_byte.Writeback_Data 366120 -system.ruby.network.msg_byte.Writeback_Control 81360 -system.ruby.network.msg_byte.Unblock_Control 42912 -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 57351 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.throttle0.link_utilization 7.917909 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 881 -system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2 28 -system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::0 904 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::2 63432 -system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::2 2016 -system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::0 7232 -system.ruby.network.routers0.throttle1.link_utilization 9.465397 -system.ruby.network.routers0.throttle1.msg_count.Request_Control::0 909 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::2 904 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 904 -system.ruby.network.routers0.throttle1.msg_count.Unblock_Control::2 908 -system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::0 7272 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::2 65088 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 7232 -system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::2 7264 -system.ruby.network.routers1.throttle0.link_utilization 17.067706 -system.ruby.network.routers1.throttle0.msg_count.Request_Control::0 909 -system.ruby.network.routers1.throttle0.msg_count.Response_Data::2 881 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::2 904 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0 904 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::1 791 -system.ruby.network.routers1.throttle0.msg_count.Unblock_Control::2 908 -system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::0 7272 -system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::2 63432 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::2 65088 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 7232 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::1 6328 -system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::2 7264 -system.ruby.network.routers1.throttle1.link_utilization 16.351938 -system.ruby.network.routers1.throttle1.msg_count.Request_Control::1 881 -system.ruby.network.routers1.throttle1.msg_count.Response_Data::2 881 -system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::2 28 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::2 791 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::0 904 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::1 791 -system.ruby.network.routers1.throttle1.msg_count.Unblock_Control::2 880 -system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::1 7048 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::2 63432 -system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::2 2016 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::2 56952 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::0 7232 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::1 6328 -system.ruby.network.routers1.throttle1.msg_bytes.Unblock_Control::2 7040 -system.ruby.network.routers2.throttle0.link_utilization 8.431414 -system.ruby.network.routers2.throttle0.msg_count.Request_Control::1 881 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::2 791 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::1 791 -system.ruby.network.routers2.throttle0.msg_count.Unblock_Control::2 880 -system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::1 7048 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::2 56952 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::1 6328 -system.ruby.network.routers2.throttle0.msg_bytes.Unblock_Control::2 7040 -system.ruby.network.routers2.throttle1.link_utilization 7.602309 -system.ruby.network.routers2.throttle1.msg_count.Response_Data::2 881 -system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::1 791 -system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::2 63432 -system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::1 6328 -system.ruby.network.routers3.throttle0.link_utilization 7.920524 -system.ruby.network.routers3.throttle0.msg_count.Response_Data::2 881 -system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::2 28 -system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::0 904 -system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::2 63432 -system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::2 2016 -system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::0 7232 -system.ruby.network.routers3.throttle1.link_utilization 17.067706 -system.ruby.network.routers3.throttle1.msg_count.Request_Control::0 909 -system.ruby.network.routers3.throttle1.msg_count.Response_Data::2 881 -system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::2 904 -system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::0 904 -system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::1 791 -system.ruby.network.routers3.throttle1.msg_count.Unblock_Control::2 908 -system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::0 7272 -system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::2 63432 -system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::2 65088 -system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 7232 -system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::1 6328 -system.ruby.network.routers3.throttle1.msg_bytes.Unblock_Control::2 7264 -system.ruby.network.routers3.throttle2.link_utilization 8.431414 -system.ruby.network.routers3.throttle2.msg_count.Request_Control::1 881 -system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::2 791 -system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::1 791 -system.ruby.network.routers3.throttle2.msg_count.Unblock_Control::2 880 -system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::1 7048 -system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::2 56952 -system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::1 6328 -system.ruby.network.routers3.throttle2.msg_bytes.Unblock_Control::2 7040 -system.ruby.LD.latency_hist_seqr::bucket_size 256 -system.ruby.LD.latency_hist_seqr::max_bucket 2559 -system.ruby.LD.latency_hist_seqr::samples 48 -system.ruby.LD.latency_hist_seqr::mean 885.875000 -system.ruby.LD.latency_hist_seqr::gmean 375.211617 -system.ruby.LD.latency_hist_seqr::stdev 381.714030 -system.ruby.LD.latency_hist_seqr | 7 14.58% 14.58% | 0 0.00% 14.58% | 0 0.00% 14.58% | 21 43.75% 58.33% | 18 37.50% 95.83% | 2 4.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist_seqr::total 48 -system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 -system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 -system.ruby.LD.hit_latency_hist_seqr::samples 7 -system.ruby.LD.hit_latency_hist_seqr::mean 1 -system.ruby.LD.hit_latency_hist_seqr::gmean 1 -system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 7 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist_seqr::total 7 -system.ruby.LD.miss_latency_hist_seqr::bucket_size 256 -system.ruby.LD.miss_latency_hist_seqr::max_bucket 2559 -system.ruby.LD.miss_latency_hist_seqr::samples 41 -system.ruby.LD.miss_latency_hist_seqr::mean 1036.951220 -system.ruby.LD.miss_latency_hist_seqr::gmean 1032.254678 -system.ruby.LD.miss_latency_hist_seqr::stdev 103.845065 -system.ruby.LD.miss_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 21 51.22% 51.22% | 18 43.90% 95.12% | 2 4.88% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist_seqr::total 41 -system.ruby.ST.latency_hist_seqr::bucket_size 256 -system.ruby.ST.latency_hist_seqr::max_bucket 2559 -system.ruby.ST.latency_hist_seqr::samples 899 -system.ruby.ST.latency_hist_seqr::mean 947.919911 -system.ruby.ST.latency_hist_seqr::gmean 545.272647 -system.ruby.ST.latency_hist_seqr::stdev 331.026961 -system.ruby.ST.latency_hist_seqr | 89 9.90% 9.90% | 6 0.67% 10.57% | 4 0.44% 11.01% | 359 39.93% 50.95% | 394 43.83% 94.77% | 47 5.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist_seqr::total 899 -system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 -system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 -system.ruby.ST.hit_latency_hist_seqr::samples 81 -system.ruby.ST.hit_latency_hist_seqr::mean 1 -system.ruby.ST.hit_latency_hist_seqr::gmean 1 -system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 81 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist_seqr::total 81 -system.ruby.ST.miss_latency_hist_seqr::bucket_size 256 -system.ruby.ST.miss_latency_hist_seqr::max_bucket 2559 -system.ruby.ST.miss_latency_hist_seqr::samples 818 -system.ruby.ST.miss_latency_hist_seqr::mean 1041.685819 -system.ruby.ST.miss_latency_hist_seqr::gmean 1017.650590 -system.ruby.ST.miss_latency_hist_seqr::stdev 150.806361 -system.ruby.ST.miss_latency_hist_seqr | 8 0.98% 0.98% | 6 0.73% 1.71% | 4 0.49% 2.20% | 359 43.89% 46.09% | 394 48.17% 94.25% | 47 5.75% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist_seqr::total 818 -system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 -system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.latency_hist_seqr::samples 52 -system.ruby.IFETCH.latency_hist_seqr::mean 86.442308 -system.ruby.IFETCH.latency_hist_seqr::gmean 62.630120 -system.ruby.IFETCH.latency_hist_seqr::stdev 84.743769 -system.ruby.IFETCH.latency_hist_seqr | 17 32.69% 32.69% | 31 59.62% 92.31% | 1 1.92% 94.23% | 0 0.00% 94.23% | 0 0.00% 94.23% | 2 3.85% 98.08% | 0 0.00% 98.08% | 1 1.92% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist_seqr::total 52 -system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 -system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 -system.ruby.IFETCH.hit_latency_hist_seqr::samples 2 -system.ruby.IFETCH.hit_latency_hist_seqr::mean 1 -system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 -system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist_seqr::total 2 -system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 -system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.miss_latency_hist_seqr::samples 50 -system.ruby.IFETCH.miss_latency_hist_seqr::mean 89.860000 -system.ruby.IFETCH.miss_latency_hist_seqr::gmean 73.901725 -system.ruby.IFETCH.miss_latency_hist_seqr::stdev 84.644758 -system.ruby.IFETCH.miss_latency_hist_seqr | 15 30.00% 30.00% | 31 62.00% 92.00% | 1 2.00% 94.00% | 0 0.00% 94.00% | 0 0.00% 94.00% | 2 4.00% 98.00% | 0 0.00% 98.00% | 1 2.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.miss_latency_hist_seqr::total 50 -system.ruby.Directory_Controller.GETX 796 0.00% 0.00% -system.ruby.Directory_Controller.GETS 85 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 791 0.00% 0.00% -system.ruby.Directory_Controller.Unblock 81 0.00% 0.00% -system.ruby.Directory_Controller.Last_Unblock 3 0.00% 0.00% -system.ruby.Directory_Controller.Exclusive_Unblock 796 0.00% 0.00% -system.ruby.Directory_Controller.Dirty_Writeback 791 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 881 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 791 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 735 0.00% 0.00% -system.ruby.Directory_Controller.I.GETS 82 0.00% 0.00% -system.ruby.Directory_Controller.I.Memory_Ack 791 0.00% 0.00% -system.ruby.Directory_Controller.S.GETX 61 0.00% 0.00% -system.ruby.Directory_Controller.S.GETS 3 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 791 0.00% 0.00% -system.ruby.Directory_Controller.IS.Unblock 81 0.00% 0.00% -system.ruby.Directory_Controller.IS.Memory_Data 82 0.00% 0.00% -system.ruby.Directory_Controller.SS.Last_Unblock 3 0.00% 0.00% -system.ruby.Directory_Controller.SS.Memory_Data 3 0.00% 0.00% -system.ruby.Directory_Controller.MM.Exclusive_Unblock 796 0.00% 0.00% -system.ruby.Directory_Controller.MM.Memory_Data 796 0.00% 0.00% -system.ruby.Directory_Controller.MI.Dirty_Writeback 791 0.00% 0.00% -system.ruby.L1Cache_Controller.Load 48 0.00% 0.00% -system.ruby.L1Cache_Controller.Ifetch 64 0.00% 0.00% -system.ruby.L1Cache_Controller.Store 905 0.00% 0.00% -system.ruby.L1Cache_Controller.L1_Replacement 84079 0.00% 0.00% -system.ruby.L1Cache_Controller.Data 85 0.00% 0.00% -system.ruby.L1Cache_Controller.Exclusive_Data 824 0.00% 0.00% -system.ruby.L1Cache_Controller.Writeback_Ack_Data 904 0.00% 0.00% -system.ruby.L1Cache_Controller.All_acks 818 0.00% 0.00% -system.ruby.L1Cache_Controller.Use_Timeout 823 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Load 41 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Ifetch 50 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Store 818 0.00% 0.00% -system.ruby.L1Cache_Controller.S.Ifetch 2 0.00% 0.00% -system.ruby.L1Cache_Controller.S.L1_Replacement 82 0.00% 0.00% -system.ruby.L1Cache_Controller.M.L1_Replacement 5 0.00% 0.00% -system.ruby.L1Cache_Controller.M_W.Use_Timeout 6 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.Load 7 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.Store 70 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.L1_Replacement 817 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_W.Store 11 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_W.L1_Replacement 31468 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_W.Use_Timeout 817 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.L1_Replacement 48874 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.Exclusive_Data 818 0.00% 0.00% -system.ruby.L1Cache_Controller.OM.L1_Replacement 674 0.00% 0.00% -system.ruby.L1Cache_Controller.OM.All_acks 818 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.L1_Replacement 2159 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Data 85 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Exclusive_Data 6 0.00% 0.00% -system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data 82 0.00% 0.00% -system.ruby.L1Cache_Controller.MI.Ifetch 12 0.00% 0.00% -system.ruby.L1Cache_Controller.MI.Store 6 0.00% 0.00% -system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data 822 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETS 91 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETX 818 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTX 822 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTS_only 82 0.00% 0.00% -system.ruby.L2Cache_Controller.All_Acks 796 0.00% 0.00% -system.ruby.L2Cache_Controller.Data 881 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_WBCLEANDATA 82 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_WBDIRTYDATA 822 0.00% 0.00% -system.ruby.L2Cache_Controller.Writeback_Ack 791 0.00% 0.00% -system.ruby.L2Cache_Controller.Unblock 84 0.00% 0.00% -system.ruby.L2Cache_Controller.Exclusive_Unblock 824 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement 873 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETS 85 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETX 796 0.00% 0.00% -system.ruby.L2Cache_Controller.ILS.L1_PUTS_only 82 0.00% 0.00% -system.ruby.L2Cache_Controller.ILX.L1_PUTX 822 0.00% 0.00% -system.ruby.L2Cache_Controller.S.L2_Replacement 82 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETS 6 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETX 22 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement 791 0.00% 0.00% -system.ruby.L2Cache_Controller.IW.L1_WBCLEANDATA 82 0.00% 0.00% -system.ruby.L2Cache_Controller.ILXW.L1_WBDIRTYDATA 822 0.00% 0.00% -system.ruby.L2Cache_Controller.IGS.Data 85 0.00% 0.00% -system.ruby.L2Cache_Controller.IGS.Unblock 84 0.00% 0.00% -system.ruby.L2Cache_Controller.IGM.Data 796 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMO.All_Acks 796 0.00% 0.00% -system.ruby.L2Cache_Controller.IGMO.Exclusive_Unblock 796 0.00% 0.00% -system.ruby.L2Cache_Controller.MM.Exclusive_Unblock 22 0.00% 0.00% -system.ruby.L2Cache_Controller.OO.Exclusive_Unblock 6 0.00% 0.00% -system.ruby.L2Cache_Controller.MI.Writeback_Ack 791 0.00% 0.00% - ----------- End Simulation Statistics ---------- diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,2063 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000 -time_sync_spin_threshold=100000 - -[system] -type=System -children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges=0:268435455:0:0:0:0 -memories=system.mem_ctrls -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.sys_port_proxy.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=RubyTester -check_flush=false -checks_to_complete=100 -clk_domain=system.clk_domain -deadlock_threshold=50000 -default_p_state=UNDEFINED -eventq_index=0 -num_cpus=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -system=system -wakeup_frequency=10 -cpuInstDataPort=system.ruby.l1_cntrl0.sequencer.slave[0] - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000 - -[system.mem_ctrls] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -page_policy=open_adaptive -power_model=Null -range=0:268435455:5:19:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10 -static_frontend_latency=10 -tBURST=5 -tCCD_L=0 -tCK=1 -tCL=14 -tCS=3 -tRAS=35 -tRCD=14 -tREFI=7800 -tRFC=260 -tRP=14 -tRRD=6 -tRRD_L=0 -tRTP=8 -tRTW=3 -tWR=15 -tWTR=8 -tXAW=30 -tXP=6 -tXPDLL=0 -tXS=270 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.ruby.dir_cntrl0.memory - -[system.ruby] -type=RubySystem -children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network -access_backing_store=false -all_instructions=false -block_size_bytes=64 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hot_lines=false -memory_size_bits=48 -num_of_sequencers=1 -number_of_virtual_networks=6 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -phys_mem=Null -power_model=Null -randomization=true - -[system.ruby.clk_domain] -type=SrcClockDomain -clock=1 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.ruby.dir_cntrl0] -type=Directory_Controller -children=directory dmaRequestToDir dmaResponseFromDir persistentFromDir persistentToDir requestFromDir requestToDir responseFromDir responseFromMemory responseToDir -buffer_size=0 -clk_domain=system.ruby.clk_domain -cluster_id=0 -default_p_state=UNDEFINED -directory=system.ruby.dir_cntrl0.directory -directory_latency=5 -distributed_persistent=true -dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir -dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir -eventq_index=0 -fixed_timeout_latency=100 -l2_select_num_bits=0 -number_of_TBEs=256 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -persistentFromDir=system.ruby.dir_cntrl0.persistentFromDir -persistentToDir=system.ruby.dir_cntrl0.persistentToDir -power_model=Null -recycle_latency=10 -reissue_wakeup_latency=10 -requestFromDir=system.ruby.dir_cntrl0.requestFromDir -requestToDir=system.ruby.dir_cntrl0.requestToDir -responseFromDir=system.ruby.dir_cntrl0.responseFromDir -responseFromMemory=system.ruby.dir_cntrl0.responseFromMemory -responseToDir=system.ruby.dir_cntrl0.responseToDir -ruby_system=system.ruby -system=system -to_memory_controller_latency=1 -transitions_per_cycle=32 -version=0 -memory=system.mem_ctrls.port - -[system.ruby.dir_cntrl0.directory] -type=RubyDirectoryMemory -eventq_index=0 -numa_high_bit=5 -size=268435456 -version=0 - -[system.ruby.dir_cntrl0.dmaRequestToDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -slave=system.ruby.network.master[10] - -[system.ruby.dir_cntrl0.dmaResponseFromDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -master=system.ruby.network.slave[9] - -[system.ruby.dir_cntrl0.persistentFromDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -master=system.ruby.network.slave[8] - -[system.ruby.dir_cntrl0.persistentToDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -slave=system.ruby.network.master[9] - -[system.ruby.dir_cntrl0.requestFromDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[6] - -[system.ruby.dir_cntrl0.requestToDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[7] - -[system.ruby.dir_cntrl0.responseFromDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[7] - -[system.ruby.dir_cntrl0.responseFromMemory] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false - -[system.ruby.dir_cntrl0.responseToDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[8] - -[system.ruby.l1_cntrl0] -type=L1Cache_Controller -children=L1Dcache L1Icache mandatoryQueue persistentFromL1Cache persistentToL1Cache requestFromL1Cache requestToL1Cache responseFromL1Cache responseToL1Cache sequencer -L1Dcache=system.ruby.l1_cntrl0.L1Dcache -L1Icache=system.ruby.l1_cntrl0.L1Icache -N_tokens=2 -buffer_size=0 -clk_domain=system.ruby.clk_domain -cluster_id=0 -default_p_state=UNDEFINED -dynamic_timeout_enabled=true -eventq_index=0 -fixed_timeout_latency=300 -l1_request_latency=2 -l1_response_latency=2 -l2_select_num_bits=0 -mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue -no_mig_atomic=true -number_of_TBEs=256 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -persistentFromL1Cache=system.ruby.l1_cntrl0.persistentFromL1Cache -persistentToL1Cache=system.ruby.l1_cntrl0.persistentToL1Cache -power_model=Null -recycle_latency=10 -reissue_wakeup_latency=10 -requestFromL1Cache=system.ruby.l1_cntrl0.requestFromL1Cache -requestToL1Cache=system.ruby.l1_cntrl0.requestToL1Cache -responseFromL1Cache=system.ruby.l1_cntrl0.responseFromL1Cache -responseToL1Cache=system.ruby.l1_cntrl0.responseToL1Cache -retry_threshold=1 -ruby_system=system.ruby -send_evictions=false -sequencer=system.ruby.l1_cntrl0.sequencer -system=system -transitions_per_cycle=32 -use_timeout_latency=50 -version=0 - -[system.ruby.l1_cntrl0.L1Dcache] -type=RubyCache -children=replacement_policy -assoc=2 -block_size=0 -dataAccessLatency=1 -dataArrayBanks=1 -eventq_index=0 -is_icache=false -replacement_policy=system.ruby.l1_cntrl0.L1Dcache.replacement_policy -resourceStalls=false -ruby_system=system.ruby -size=256 -start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 - -[system.ruby.l1_cntrl0.L1Dcache.replacement_policy] -type=PseudoLRUReplacementPolicy -assoc=2 -block_size=64 -eventq_index=0 -size=256 - -[system.ruby.l1_cntrl0.L1Icache] -type=RubyCache -children=replacement_policy -assoc=2 -block_size=0 -dataAccessLatency=1 -dataArrayBanks=1 -eventq_index=0 -is_icache=false -replacement_policy=system.ruby.l1_cntrl0.L1Icache.replacement_policy -resourceStalls=false -ruby_system=system.ruby -size=256 -start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 - -[system.ruby.l1_cntrl0.L1Icache.replacement_policy] -type=PseudoLRUReplacementPolicy -assoc=2 -block_size=64 -eventq_index=0 -size=256 - -[system.ruby.l1_cntrl0.mandatoryQueue] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false - -[system.ruby.l1_cntrl0.persistentFromL1Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -master=system.ruby.network.slave[2] - -[system.ruby.l1_cntrl0.persistentToL1Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -slave=system.ruby.network.master[2] - -[system.ruby.l1_cntrl0.requestFromL1Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[0] - -[system.ruby.l1_cntrl0.requestToL1Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[0] - -[system.ruby.l1_cntrl0.responseFromL1Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[1] - -[system.ruby.l1_cntrl0.responseToL1Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[1] - -[system.ruby.l1_cntrl0.sequencer] -type=RubySequencer -clk_domain=system.ruby.clk_domain -coreid=99 -dcache=system.ruby.l1_cntrl0.L1Dcache -dcache_hit_latency=1 -deadlock_threshold=500000 -default_p_state=UNDEFINED -eventq_index=0 -garnet_standalone=false -icache=system.ruby.l1_cntrl0.L1Icache -icache_hit_latency=1 -is_cpu_sequencer=true -max_outstanding_requests=16 -no_retry_on_stall=true -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -ruby_system=system.ruby -support_data_reqs=true -support_inst_reqs=true -system=system -using_ruby_tester=true -version=0 -slave=system.cpu.cpuInstDataPort[0] - -[system.ruby.l2_cntrl0] -type=L2Cache_Controller -children=GlobalRequestFromL2Cache GlobalRequestToL2Cache L1RequestFromL2Cache L1RequestToL2Cache L2cache persistentToL2Cache responseFromL2Cache responseToL2Cache -GlobalRequestFromL2Cache=system.ruby.l2_cntrl0.GlobalRequestFromL2Cache -GlobalRequestToL2Cache=system.ruby.l2_cntrl0.GlobalRequestToL2Cache -L1RequestFromL2Cache=system.ruby.l2_cntrl0.L1RequestFromL2Cache -L1RequestToL2Cache=system.ruby.l2_cntrl0.L1RequestToL2Cache -L2cache=system.ruby.l2_cntrl0.L2cache -N_tokens=2 -buffer_size=0 -clk_domain=system.ruby.clk_domain -cluster_id=0 -default_p_state=UNDEFINED -eventq_index=0 -filtering_enabled=true -l2_request_latency=5 -l2_response_latency=5 -number_of_TBEs=256 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -persistentToL2Cache=system.ruby.l2_cntrl0.persistentToL2Cache -power_model=Null -recycle_latency=10 -responseFromL2Cache=system.ruby.l2_cntrl0.responseFromL2Cache -responseToL2Cache=system.ruby.l2_cntrl0.responseToL2Cache -ruby_system=system.ruby -system=system -transitions_per_cycle=32 -version=0 - -[system.ruby.l2_cntrl0.GlobalRequestFromL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[3] - -[system.ruby.l2_cntrl0.GlobalRequestToL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[3] - -[system.ruby.l2_cntrl0.L1RequestFromL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[4] - -[system.ruby.l2_cntrl0.L1RequestToL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[4] - -[system.ruby.l2_cntrl0.L2cache] -type=RubyCache -children=replacement_policy -assoc=2 -block_size=0 -dataAccessLatency=1 -dataArrayBanks=1 -eventq_index=0 -is_icache=false -replacement_policy=system.ruby.l2_cntrl0.L2cache.replacement_policy -resourceStalls=false -ruby_system=system.ruby -size=512 -start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 - -[system.ruby.l2_cntrl0.L2cache.replacement_policy] -type=PseudoLRUReplacementPolicy -assoc=2 -block_size=64 -eventq_index=0 -size=512 - -[system.ruby.l2_cntrl0.persistentToL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -slave=system.ruby.network.master[6] - -[system.ruby.l2_cntrl0.responseFromL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[5] - -[system.ruby.l2_cntrl0.responseToL2Cache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[5] - -[system.ruby.memctrl_clk_domain] -type=DerivedClockDomain -clk_divider=3 -clk_domain=system.ruby.clk_domain -eventq_index=0 - -[system.ruby.network] -type=SimpleNetwork -children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_link_buffers40 int_link_buffers41 int_link_buffers42 int_link_buffers43 int_link_buffers44 int_link_buffers45 int_link_buffers46 int_link_buffers47 int_link_buffers48 int_link_buffers49 int_link_buffers50 int_link_buffers51 int_link_buffers52 int_link_buffers53 int_link_buffers54 int_link_buffers55 int_link_buffers56 int_link_buffers57 int_link_buffers58 int_link_buffers59 int_link_buffers60 int_link_buffers61 int_link_buffers62 int_link_buffers63 int_link_buffers64 int_link_buffers65 int_link_buffers66 int_link_buffers67 int_link_buffers68 int_link_buffers69 int_link_buffers70 int_link_buffers71 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 routers0 routers1 routers2 routers3 -adaptive_routing=false -buffer_size=0 -clk_domain=system.ruby.clk_domain -control_msg_size=8 -default_p_state=UNDEFINED -endpoint_bandwidth=1000 -eventq_index=0 -ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2 -int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 system.ruby.network.int_link_buffers40 system.ruby.network.int_link_buffers41 system.ruby.network.int_link_buffers42 system.ruby.network.int_link_buffers43 system.ruby.network.int_link_buffers44 system.ruby.network.int_link_buffers45 system.ruby.network.int_link_buffers46 system.ruby.network.int_link_buffers47 system.ruby.network.int_link_buffers48 system.ruby.network.int_link_buffers49 system.ruby.network.int_link_buffers50 system.ruby.network.int_link_buffers51 system.ruby.network.int_link_buffers52 system.ruby.network.int_link_buffers53 system.ruby.network.int_link_buffers54 system.ruby.network.int_link_buffers55 system.ruby.network.int_link_buffers56 system.ruby.network.int_link_buffers57 system.ruby.network.int_link_buffers58 system.ruby.network.int_link_buffers59 system.ruby.network.int_link_buffers60 system.ruby.network.int_link_buffers61 system.ruby.network.int_link_buffers62 system.ruby.network.int_link_buffers63 system.ruby.network.int_link_buffers64 system.ruby.network.int_link_buffers65 system.ruby.network.int_link_buffers66 system.ruby.network.int_link_buffers67 system.ruby.network.int_link_buffers68 system.ruby.network.int_link_buffers69 system.ruby.network.int_link_buffers70 system.ruby.network.int_link_buffers71 -int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4 system.ruby.network.int_links5 -netifs= -number_of_virtual_networks=6 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 system.ruby.network.routers3 -ruby_system=system.ruby -topology=Crossbar -master=system.ruby.l1_cntrl0.requestToL1Cache.slave system.ruby.l1_cntrl0.responseToL1Cache.slave system.ruby.l1_cntrl0.persistentToL1Cache.slave system.ruby.l2_cntrl0.GlobalRequestToL2Cache.slave system.ruby.l2_cntrl0.L1RequestToL2Cache.slave system.ruby.l2_cntrl0.responseToL2Cache.slave system.ruby.l2_cntrl0.persistentToL2Cache.slave system.ruby.dir_cntrl0.requestToDir.slave system.ruby.dir_cntrl0.responseToDir.slave system.ruby.dir_cntrl0.persistentToDir.slave system.ruby.dir_cntrl0.dmaRequestToDir.slave -slave=system.ruby.l1_cntrl0.requestFromL1Cache.master system.ruby.l1_cntrl0.responseFromL1Cache.master system.ruby.l1_cntrl0.persistentFromL1Cache.master system.ruby.l2_cntrl0.GlobalRequestFromL2Cache.master system.ruby.l2_cntrl0.L1RequestFromL2Cache.master system.ruby.l2_cntrl0.responseFromL2Cache.master system.ruby.dir_cntrl0.requestFromDir.master system.ruby.dir_cntrl0.responseFromDir.master system.ruby.dir_cntrl0.persistentFromDir.master system.ruby.dir_cntrl0.dmaResponseFromDir.master - -[system.ruby.network.ext_links0] -type=SimpleExtLink -bandwidth_factor=16 -eventq_index=0 -ext_node=system.ruby.l1_cntrl0 -int_node=system.ruby.network.routers0 -latency=1 -link_id=0 -weight=1 - -[system.ruby.network.ext_links1] -type=SimpleExtLink -bandwidth_factor=16 -eventq_index=0 -ext_node=system.ruby.l2_cntrl0 -int_node=system.ruby.network.routers1 -latency=1 -link_id=1 -weight=1 - -[system.ruby.network.ext_links2] -type=SimpleExtLink -bandwidth_factor=16 -eventq_index=0 -ext_node=system.ruby.dir_cntrl0 -int_node=system.ruby.network.routers2 -latency=1 -link_id=2 -weight=1 - -[system.ruby.network.int_link_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - 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-randomization=false - -[system.ruby.network.routers2.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers15] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers16] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers17] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers18] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers19] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers20] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers21] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers22] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers23] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23 port_buffers24 port_buffers25 port_buffers26 port_buffers27 port_buffers28 port_buffers29 port_buffers30 port_buffers31 port_buffers32 port_buffers33 port_buffers34 port_buffers35 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers3.port_buffers00 system.ruby.network.routers3.port_buffers01 system.ruby.network.routers3.port_buffers02 system.ruby.network.routers3.port_buffers03 system.ruby.network.routers3.port_buffers04 system.ruby.network.routers3.port_buffers05 system.ruby.network.routers3.port_buffers06 system.ruby.network.routers3.port_buffers07 system.ruby.network.routers3.port_buffers08 system.ruby.network.routers3.port_buffers09 system.ruby.network.routers3.port_buffers10 system.ruby.network.routers3.port_buffers11 system.ruby.network.routers3.port_buffers12 system.ruby.network.routers3.port_buffers13 system.ruby.network.routers3.port_buffers14 system.ruby.network.routers3.port_buffers15 system.ruby.network.routers3.port_buffers16 system.ruby.network.routers3.port_buffers17 system.ruby.network.routers3.port_buffers18 system.ruby.network.routers3.port_buffers19 system.ruby.network.routers3.port_buffers20 system.ruby.network.routers3.port_buffers21 system.ruby.network.routers3.port_buffers22 system.ruby.network.routers3.port_buffers23 system.ruby.network.routers3.port_buffers24 system.ruby.network.routers3.port_buffers25 system.ruby.network.routers3.port_buffers26 system.ruby.network.routers3.port_buffers27 system.ruby.network.routers3.port_buffers28 system.ruby.network.routers3.port_buffers29 system.ruby.network.routers3.port_buffers30 system.ruby.network.routers3.port_buffers31 system.ruby.network.routers3.port_buffers32 system.ruby.network.routers3.port_buffers33 system.ruby.network.routers3.port_buffers34 system.ruby.network.routers3.port_buffers35 -power_model=Null -router_id=3 -virt_nets=6 - -[system.ruby.network.routers3.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers15] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers16] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers17] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers18] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers19] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers20] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers21] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers22] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers23] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers24] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers25] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers26] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers27] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers28] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers29] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers30] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers31] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers32] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers33] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers34] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers3.port_buffers35] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.sys_port_proxy] -type=RubyPortProxy -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_cpu_sequencer=true -no_retry_on_stall=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -ruby_system=system.ruby -support_data_reqs=true -support_inst_reqs=true -system=system -using_ruby_tester=false -version=0 -slave=system.system_port - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,8 +0,0 @@ -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) -warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,13 +0,0 @@ -Redirecting stdout to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout -Redirecting stderr to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 13 2016 20:33:48 -gem5 started Oct 13 2016 20:34:17 -gem5 executing on e108600-lin, pid 27528 -command line: /work/curdun01/gem5-external.hg/build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token - -Global frequency set at 1000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 53801 because Ruby Tester completed diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,711 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000054 # Number of seconds simulated -sim_ticks 53801 # Number of ticks simulated -final_tick 53801 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 784976 # Simulator tick rate (ticks/s) -host_mem_usage 409916 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 53801 # Cumulative time (in ticks) in various power states -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 52672 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 52672 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 47552 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 47552 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 823 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 823 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 743 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 743 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 979015260 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 979015260 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 883849743 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 883849743 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 1862865003 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 1862865003 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 824 # Number of read requests accepted -system.mem_ctrls.writeReqs 743 # Number of write requests accepted -system.mem_ctrls.readBursts 824 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 743 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 43776 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 8960 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 40320 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 52736 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 47552 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 140 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 90 # Number of DRAM write bursts merged with an existing one -system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 217 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 193 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 224 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 50 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::9 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 196 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 186 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 201 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 47 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts -system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 53772 # Total gap between requests -system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 824 # Read request sizes (log2) -system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 743 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 527 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 156 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::2 1 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 4 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 4 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 20 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 43 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 44 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 41 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 41 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 39 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 41 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 41 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 45 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 39 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 39 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 39 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 39 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 39 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 90 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 916.622222 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 830.573922 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 254.887972 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 1 1.11% 1.11% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 5 5.56% 6.67% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 1 1.11% 7.78% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 2 2.22% 10.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 3 3.33% 13.33% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 4 4.44% 17.78% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 4 4.44% 22.22% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 70 77.78% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 90 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 39 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 17.282051 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 16.989006 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 3.886202 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::12-13 1 2.56% 2.56% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::14-15 8 20.51% 23.08% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-17 18 46.15% 69.23% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::18-19 8 20.51% 89.74% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::20-21 2 5.13% 94.87% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::22-23 1 2.56% 97.44% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::38-39 1 2.56% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 39 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 39 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.153846 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.145622 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 0.539906 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 36 92.31% 92.31% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 3 7.69% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 39 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 11889 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 24885 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 3420 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 17.38 # Average queueing delay per DRAM burst -system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 36.38 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 813.67 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 749.43 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 980.20 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 883.85 # Average system write bandwidth in MiByte/s -system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 12.21 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 6.36 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 5.85 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 1.38 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 25.30 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 599 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 622 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 87.57 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 95.25 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 34.32 # Average gap between requests -system.mem_ctrls.pageHitRate 91.32 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 664020 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 347760 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 7814016 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 5261760 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 3687840.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 10048872 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 77568 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.actPowerDownEnergy 14391360 # Energy for active power-down per rank (pJ) -system.mem_ctrls_0.prePowerDownEnergy 768 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrls_0.totalEnergy 42293964 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 786.118548 # Core power per rank (mW) -system.mem_ctrls_0.totalIdleTime 31562 # Total Idle time Per DRAM Rank -system.mem_ctrls_0.memoryStateTime::IDLE 34 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 1560 # Time in different power states -system.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::PRE_PDN 2 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 20645 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 31560 # Time in different power states -system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 224352 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 3002880 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) -system.mem_ctrls_1.prePowerDownEnergy 2889984 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_1.selfRefreshEnergy 9111120 # Energy for self refresh per rank (pJ) -system.mem_ctrls_1.totalEnergy 16457616 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 305.897957 # Core power per rank (mW) -system.mem_ctrls_1.totalIdleTime 7526 # Total Idle time Per DRAM Rank -system.mem_ctrls_1.memoryStateTime::IDLE 7786 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 526 # Time in different power states -system.mem_ctrls_1.memoryStateTime::SREF 37963 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 7526 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 53801 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::UNDEFINED 53801 # Cumulative time (in ticks) in various power states -system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.pwrStateResidencyTicks::UNDEFINED 53801 # Cumulative time (in ticks) in various power states -system.ruby.outstanding_req_hist_seqr::bucket_size 2 -system.ruby.outstanding_req_hist_seqr::max_bucket 19 -system.ruby.outstanding_req_hist_seqr::samples 973 -system.ruby.outstanding_req_hist_seqr::mean 15.744090 -system.ruby.outstanding_req_hist_seqr::gmean 15.636746 -system.ruby.outstanding_req_hist_seqr::stdev 1.206668 -system.ruby.outstanding_req_hist_seqr | 1 0.10% 0.10% | 2 0.21% 0.31% | 2 0.21% 0.51% | 2 0.21% 0.72% | 4 0.41% 1.13% | 2 0.21% 1.34% | 3 0.31% 1.64% | 112 11.51% 13.16% | 845 86.84% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist_seqr::total 973 -system.ruby.latency_hist_seqr::bucket_size 256 -system.ruby.latency_hist_seqr::max_bucket 2559 -system.ruby.latency_hist_seqr::samples 958 -system.ruby.latency_hist_seqr::mean 879.328810 -system.ruby.latency_hist_seqr::gmean 422.320646 -system.ruby.latency_hist_seqr::stdev 422.809847 -system.ruby.latency_hist_seqr | 182 19.00% 19.00% | 6 0.63% 19.62% | 4 0.42% 20.04% | 214 22.34% 42.38% | 516 53.86% 96.24% | 36 3.76% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist_seqr::total 958 -system.ruby.hit_latency_hist_seqr::bucket_size 256 -system.ruby.hit_latency_hist_seqr::max_bucket 2559 -system.ruby.hit_latency_hist_seqr::samples 136 -system.ruby.hit_latency_hist_seqr::mean 190.117647 -system.ruby.hit_latency_hist_seqr::gmean 5.669159 -system.ruby.hit_latency_hist_seqr::stdev 399.173351 -system.ruby.hit_latency_hist_seqr | 112 82.35% 82.35% | 0 0.00% 82.35% | 0 0.00% 82.35% | 10 7.35% 89.71% | 13 9.56% 99.26% | 1 0.74% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist_seqr::total 136 -system.ruby.miss_latency_hist_seqr::bucket_size 256 -system.ruby.miss_latency_hist_seqr::max_bucket 2559 -system.ruby.miss_latency_hist_seqr::samples 822 -system.ruby.miss_latency_hist_seqr::mean 993.358881 -system.ruby.miss_latency_hist_seqr::gmean 861.758158 -system.ruby.miss_latency_hist_seqr::stdev 300.791358 -system.ruby.miss_latency_hist_seqr | 70 8.52% 8.52% | 6 0.73% 9.25% | 4 0.49% 9.73% | 204 24.82% 34.55% | 503 61.19% 95.74% | 35 4.26% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist_seqr::total 822 -system.ruby.Directory.incomplete_times_seqr 822 -system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 53801 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.L1Dcache.demand_hits 92 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 820 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 912 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Icache.demand_misses 48 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Icache.demand_accesses 48 # Number of cache demand accesses -system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 53801 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 4 # Number of times a store aliased with a pending load -system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 91 # Number of times a store aliased with a pending store -system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 7 # Number of times a load aliased with a pending store -system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 53801 # Cumulative time (in ticks) in various power states -system.ruby.l2_cntrl0.L2cache.demand_hits 43 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 825 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 868 # Number of cache demand accesses -system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 53801 # Cumulative time (in ticks) in various power states -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 53801 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.percent_links_utilized 7.774948 -system.ruby.network.routers0.msg_count.Request_Control::1 868 -system.ruby.network.routers0.msg_count.Response_Data::4 823 -system.ruby.network.routers0.msg_count.ResponseL2hit_Data::4 44 -system.ruby.network.routers0.msg_count.Writeback_Data::4 888 -system.ruby.network.routers0.msg_count.Persistent_Control::3 76 -system.ruby.network.routers0.msg_bytes.Request_Control::1 6944 -system.ruby.network.routers0.msg_bytes.Response_Data::4 59256 -system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::4 3168 -system.ruby.network.routers0.msg_bytes.Writeback_Data::4 63936 -system.ruby.network.routers0.msg_bytes.Persistent_Control::3 608 -system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 53801 # Cumulative time (in ticks) in various power states -system.ruby.network.routers1.percent_links_utilized 7.735451 -system.ruby.network.routers1.msg_count.Request_Control::1 868 -system.ruby.network.routers1.msg_count.Request_Control::2 825 -system.ruby.network.routers1.msg_count.ResponseL2hit_Data::4 44 -system.ruby.network.routers1.msg_count.Writeback_Data::4 1605 -system.ruby.network.routers1.msg_count.Writeback_Control::4 75 -system.ruby.network.routers1.msg_count.Persistent_Control::3 38 -system.ruby.network.routers1.msg_bytes.Request_Control::1 6944 -system.ruby.network.routers1.msg_bytes.Request_Control::2 6600 -system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::4 3168 -system.ruby.network.routers1.msg_bytes.Writeback_Data::4 115560 -system.ruby.network.routers1.msg_bytes.Writeback_Control::4 600 -system.ruby.network.routers1.msg_bytes.Persistent_Control::3 304 -system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 53801 # Cumulative time (in ticks) in various power states -system.ruby.network.routers2.percent_links_utilized 6.985000 -system.ruby.network.routers2.msg_count.Request_Control::2 825 -system.ruby.network.routers2.msg_count.Response_Data::4 823 -system.ruby.network.routers2.msg_count.Writeback_Data::4 743 -system.ruby.network.routers2.msg_count.Writeback_Control::4 75 -system.ruby.network.routers2.msg_count.Persistent_Control::3 38 -system.ruby.network.routers2.msg_bytes.Request_Control::2 6600 -system.ruby.network.routers2.msg_bytes.Response_Data::4 59256 -system.ruby.network.routers2.msg_bytes.Writeback_Data::4 53496 -system.ruby.network.routers2.msg_bytes.Writeback_Control::4 600 -system.ruby.network.routers2.msg_bytes.Persistent_Control::3 304 -system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 53801 # Cumulative time (in ticks) in various power states -system.ruby.network.routers3.percent_links_utilized 7.498621 -system.ruby.network.routers3.msg_count.Request_Control::1 868 -system.ruby.network.routers3.msg_count.Request_Control::2 825 -system.ruby.network.routers3.msg_count.Response_Data::4 823 -system.ruby.network.routers3.msg_count.ResponseL2hit_Data::4 44 -system.ruby.network.routers3.msg_count.Writeback_Data::4 1618 -system.ruby.network.routers3.msg_count.Writeback_Control::4 75 -system.ruby.network.routers3.msg_count.Persistent_Control::3 76 -system.ruby.network.routers3.msg_bytes.Request_Control::1 6944 -system.ruby.network.routers3.msg_bytes.Request_Control::2 6600 -system.ruby.network.routers3.msg_bytes.Response_Data::4 59256 -system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::4 3168 -system.ruby.network.routers3.msg_bytes.Writeback_Data::4 116496 -system.ruby.network.routers3.msg_bytes.Writeback_Control::4 600 -system.ruby.network.routers3.msg_bytes.Persistent_Control::3 608 -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 53801 # Cumulative time (in ticks) in various power states -system.ruby.network.msg_count.Request_Control 5079 -system.ruby.network.msg_count.Response_Data 2469 -system.ruby.network.msg_count.ResponseL2hit_Data 132 -system.ruby.network.msg_count.Writeback_Data 4854 -system.ruby.network.msg_count.Writeback_Control 225 -system.ruby.network.msg_count.Persistent_Control 228 -system.ruby.network.msg_byte.Request_Control 40632 -system.ruby.network.msg_byte.Response_Data 177768 -system.ruby.network.msg_byte.ResponseL2hit_Data 9504 -system.ruby.network.msg_byte.Writeback_Data 349488 -system.ruby.network.msg_byte.Writeback_Control 1800 -system.ruby.network.msg_byte.Persistent_Control 1824 -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 53801 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.throttle0.link_utilization 7.389268 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 823 -system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4 44 -system.ruby.network.routers0.throttle0.msg_count.Writeback_Data::4 13 -system.ruby.network.routers0.throttle0.msg_count.Persistent_Control::3 38 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 59256 -system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::4 3168 -system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Data::4 936 -system.ruby.network.routers0.throttle0.msg_bytes.Persistent_Control::3 304 -system.ruby.network.routers0.throttle1.link_utilization 8.160629 -system.ruby.network.routers0.throttle1.msg_count.Request_Control::1 868 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::4 875 -system.ruby.network.routers0.throttle1.msg_count.Persistent_Control::3 38 -system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::1 6944 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::4 63000 -system.ruby.network.routers0.throttle1.msg_bytes.Persistent_Control::3 304 -system.ruby.network.routers1.throttle0.link_utilization 8.051895 -system.ruby.network.routers1.throttle0.msg_count.Request_Control::1 868 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::4 862 -system.ruby.network.routers1.throttle0.msg_count.Persistent_Control::3 38 -system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::1 6944 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::4 62064 -system.ruby.network.routers1.throttle0.msg_bytes.Persistent_Control::3 304 -system.ruby.network.routers1.throttle1.link_utilization 7.419007 -system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 825 -system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::4 44 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::4 743 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::4 75 -system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2 6600 -system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::4 3168 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::4 53496 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::4 600 -system.ruby.network.routers2.throttle0.link_utilization 7.086300 -system.ruby.network.routers2.throttle0.msg_count.Request_Control::2 825 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::4 743 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::4 75 -system.ruby.network.routers2.throttle0.msg_count.Persistent_Control::3 38 -system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::2 6600 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::4 53496 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::4 600 -system.ruby.network.routers2.throttle0.msg_bytes.Persistent_Control::3 304 -system.ruby.network.routers2.throttle1.link_utilization 6.883701 -system.ruby.network.routers2.throttle1.msg_count.Response_Data::4 823 -system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::4 59256 -system.ruby.network.routers3.throttle0.link_utilization 7.357670 -system.ruby.network.routers3.throttle0.msg_count.Response_Data::4 823 -system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::4 44 -system.ruby.network.routers3.throttle0.msg_count.Writeback_Data::4 13 -system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::4 59256 -system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::4 3168 -system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Data::4 936 -system.ruby.network.routers3.throttle1.link_utilization 8.051895 -system.ruby.network.routers3.throttle1.msg_count.Request_Control::1 868 -system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::4 862 -system.ruby.network.routers3.throttle1.msg_count.Persistent_Control::3 38 -system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::1 6944 -system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::4 62064 -system.ruby.network.routers3.throttle1.msg_bytes.Persistent_Control::3 304 -system.ruby.network.routers3.throttle2.link_utilization 7.086300 -system.ruby.network.routers3.throttle2.msg_count.Request_Control::2 825 -system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::4 743 -system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::4 75 -system.ruby.network.routers3.throttle2.msg_count.Persistent_Control::3 38 -system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::2 6600 -system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::4 53496 -system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::4 600 -system.ruby.network.routers3.throttle2.msg_bytes.Persistent_Control::3 304 -system.ruby.LD.latency_hist_seqr::bucket_size 256 -system.ruby.LD.latency_hist_seqr::max_bucket 2559 -system.ruby.LD.latency_hist_seqr::samples 53 -system.ruby.LD.latency_hist_seqr::mean 911.113208 -system.ruby.LD.latency_hist_seqr::gmean 398.266031 -system.ruby.LD.latency_hist_seqr::stdev 447.197842 -system.ruby.LD.latency_hist_seqr | 10 18.87% 18.87% | 0 0.00% 18.87% | 0 0.00% 18.87% | 10 18.87% 37.74% | 28 52.83% 90.57% | 5 9.43% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist_seqr::total 53 -system.ruby.LD.hit_latency_hist_seqr::bucket_size 256 -system.ruby.LD.hit_latency_hist_seqr::max_bucket 2559 -system.ruby.LD.hit_latency_hist_seqr::samples 9 -system.ruby.LD.hit_latency_hist_seqr::mean 152 -system.ruby.LD.hit_latency_hist_seqr::gmean 4.500121 -system.ruby.LD.hit_latency_hist_seqr::stdev 435.863798 -system.ruby.LD.hit_latency_hist_seqr | 8 88.89% 88.89% | 0 0.00% 88.89% | 0 0.00% 88.89% | 0 0.00% 88.89% | 0 0.00% 88.89% | 1 11.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist_seqr::total 9 -system.ruby.LD.miss_latency_hist_seqr::bucket_size 256 -system.ruby.LD.miss_latency_hist_seqr::max_bucket 2559 -system.ruby.LD.miss_latency_hist_seqr::samples 44 -system.ruby.LD.miss_latency_hist_seqr::mean 1066.386364 -system.ruby.LD.miss_latency_hist_seqr::gmean 996.352114 -system.ruby.LD.miss_latency_hist_seqr::stdev 247.421326 -system.ruby.LD.miss_latency_hist_seqr | 2 4.55% 4.55% | 0 0.00% 4.55% | 0 0.00% 4.55% | 10 22.73% 27.27% | 28 63.64% 90.91% | 4 9.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist_seqr::total 44 -system.ruby.ST.latency_hist_seqr::bucket_size 256 -system.ruby.ST.latency_hist_seqr::max_bucket 2559 -system.ruby.ST.latency_hist_seqr::samples 858 -system.ruby.ST.latency_hist_seqr::mean 921.592075 -system.ruby.ST.latency_hist_seqr::gmean 471.652464 -system.ruby.ST.latency_hist_seqr::stdev 386.984382 -system.ruby.ST.latency_hist_seqr | 126 14.69% 14.69% | 5 0.58% 15.27% | 4 0.47% 15.73% | 204 23.78% 39.51% | 488 56.88% 96.39% | 31 3.61% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist_seqr::total 858 -system.ruby.ST.hit_latency_hist_seqr::bucket_size 128 -system.ruby.ST.hit_latency_hist_seqr::max_bucket 1279 -system.ruby.ST.hit_latency_hist_seqr::samples 120 -system.ruby.ST.hit_latency_hist_seqr::mean 202.641667 -system.ruby.ST.hit_latency_hist_seqr::gmean 5.297334 -system.ruby.ST.hit_latency_hist_seqr::stdev 407.564189 -system.ruby.ST.hit_latency_hist_seqr | 97 80.83% 80.83% | 0 0.00% 80.83% | 0 0.00% 80.83% | 0 0.00% 80.83% | 0 0.00% 80.83% | 0 0.00% 80.83% | 0 0.00% 80.83% | 10 8.33% 89.17% | 12 10.00% 99.17% | 1 0.83% 100.00% -system.ruby.ST.hit_latency_hist_seqr::total 120 -system.ruby.ST.miss_latency_hist_seqr::bucket_size 256 -system.ruby.ST.miss_latency_hist_seqr::max_bucket 2559 -system.ruby.ST.miss_latency_hist_seqr::samples 738 -system.ruby.ST.miss_latency_hist_seqr::mean 1038.494580 -system.ruby.ST.miss_latency_hist_seqr::gmean 978.643470 -system.ruby.ST.miss_latency_hist_seqr::stdev 222.427518 -system.ruby.ST.miss_latency_hist_seqr | 29 3.93% 3.93% | 5 0.68% 4.61% | 4 0.54% 5.15% | 194 26.29% 31.44% | 475 64.36% 95.80% | 31 4.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist_seqr::total 738 -system.ruby.IFETCH.latency_hist_seqr::bucket_size 32 -system.ruby.IFETCH.latency_hist_seqr::max_bucket 319 -system.ruby.IFETCH.latency_hist_seqr::samples 47 -system.ruby.IFETCH.latency_hist_seqr::mean 71.957447 -system.ruby.IFETCH.latency_hist_seqr::gmean 60.044920 -system.ruby.IFETCH.latency_hist_seqr::stdev 50.481575 -system.ruby.IFETCH.latency_hist_seqr | 7 14.89% 14.89% | 14 29.79% 44.68% | 21 44.68% 89.36% | 0 0.00% 89.36% | 1 2.13% 91.49% | 2 4.26% 95.74% | 1 2.13% 97.87% | 0 0.00% 97.87% | 1 2.13% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist_seqr::total 47 -system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 4 -system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 39 -system.ruby.IFETCH.hit_latency_hist_seqr::samples 7 -system.ruby.IFETCH.hit_latency_hist_seqr::mean 24.428571 -system.ruby.IFETCH.hit_latency_hist_seqr::gmean 24.407244 -system.ruby.IFETCH.hit_latency_hist_seqr::stdev 1.133893 -system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 7 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist_seqr::total 7 -system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 32 -system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 319 -system.ruby.IFETCH.miss_latency_hist_seqr::samples 40 -system.ruby.IFETCH.miss_latency_hist_seqr::mean 80.275000 -system.ruby.IFETCH.miss_latency_hist_seqr::gmean 70.290048 -system.ruby.IFETCH.miss_latency_hist_seqr::stdev 50.290942 -system.ruby.IFETCH.miss_latency_hist_seqr | 0 0.00% 0.00% | 14 35.00% 35.00% | 21 52.50% 87.50% | 0 0.00% 87.50% | 1 2.50% 90.00% | 2 5.00% 95.00% | 1 2.50% 97.50% | 0 0.00% 97.50% | 1 2.50% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.miss_latency_hist_seqr::total 40 -system.ruby.L1Cache.hit_mach_latency_hist_seqr::bucket_size 1 -system.ruby.L1Cache.hit_mach_latency_hist_seqr::max_bucket 9 -system.ruby.L1Cache.hit_mach_latency_hist_seqr::samples 92 -system.ruby.L1Cache.hit_mach_latency_hist_seqr::mean 1 -system.ruby.L1Cache.hit_mach_latency_hist_seqr::gmean 1 -system.ruby.L1Cache.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 92 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.hit_mach_latency_hist_seqr::total 92 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::bucket_size 256 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::max_bucket 2559 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::samples 44 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::mean 585.545455 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::gmean 213.332787 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::stdev 513.546966 -system.ruby.L2Cache.hit_mach_latency_hist_seqr | 20 45.45% 45.45% | 0 0.00% 45.45% | 0 0.00% 45.45% | 10 22.73% 68.18% | 13 29.55% 97.73% | 1 2.27% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L2Cache.hit_mach_latency_hist_seqr::total 44 -system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 256 -system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 2559 -system.ruby.Directory.miss_mach_latency_hist_seqr::samples 822 -system.ruby.Directory.miss_mach_latency_hist_seqr::mean 993.358881 -system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 861.758158 -system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 300.791358 -system.ruby.Directory.miss_mach_latency_hist_seqr | 70 8.52% 8.52% | 6 0.73% 9.25% | 4 0.49% 9.73% | 204 24.82% 34.55% | 503 61.19% 95.74% | 35 4.26% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_mach_latency_hist_seqr::total 822 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::samples 6 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::mean 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 6 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::total 6 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 256 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 2559 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::samples 3 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::mean 454 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::gmean 91.132360 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::stdev 744.781847 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr | 2 66.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::total 3 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 256 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 2559 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 44 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 1066.386364 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 996.352114 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 247.421326 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 2 4.55% 4.55% | 0 0.00% 4.55% | 0 0.00% 4.55% | 10 22.73% 27.27% | 28 63.64% 90.91% | 4 9.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 44 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::samples 86 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::mean 1 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 86 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::total 86 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 128 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 1279 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::samples 34 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::mean 712.676471 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::gmean 359.332613 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::stdev 474.361052 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr | 11 32.35% 32.35% | 0 0.00% 32.35% | 0 0.00% 32.35% | 0 0.00% 32.35% | 0 0.00% 32.35% | 0 0.00% 32.35% | 0 0.00% 32.35% | 10 29.41% 61.76% | 12 35.29% 97.06% | 1 2.94% 100.00% -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::total 34 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 256 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 2559 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 738 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 1038.494580 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 978.643470 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 222.427518 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 29 3.93% 3.93% | 5 0.68% 4.61% | 4 0.54% 5.15% | 194 26.29% 31.44% | 475 64.36% 95.80% | 31 4.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 738 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 4 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 39 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::samples 7 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::mean 24.428571 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::gmean 24.407244 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::stdev 1.133893 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 7 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::total 7 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 40 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 80.275000 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 70.290048 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 50.290942 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 14 35.00% 35.00% | 21 52.50% 87.50% | 0 0.00% 87.50% | 1 2.50% 90.00% | 2 5.00% 95.00% | 1 2.50% 97.50% | 0 0.00% 97.50% | 1 2.50% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 40 -system.ruby.Directory_Controller.GETX 740 0.00% 0.00% -system.ruby.Directory_Controller.GETS 85 0.00% 0.00% -system.ruby.Directory_Controller.Lockdown 19 0.00% 0.00% -system.ruby.Directory_Controller.Unlockdown 19 0.00% 0.00% -system.ruby.Directory_Controller.Data_Owner 2 0.00% 0.00% -system.ruby.Directory_Controller.Data_All_Tokens 741 0.00% 0.00% -system.ruby.Directory_Controller.Ack_Owner_All_Tokens 73 0.00% 0.00% -system.ruby.Directory_Controller.Ack_All_Tokens 2 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 823 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 743 0.00% 0.00% -system.ruby.Directory_Controller.O.GETX 739 0.00% 0.00% -system.ruby.Directory_Controller.O.GETS 85 0.00% 0.00% -system.ruby.Directory_Controller.O.Ack_All_Tokens 2 0.00% 0.00% -system.ruby.Directory_Controller.NO.GETX 1 0.00% 0.00% -system.ruby.Directory_Controller.NO.Lockdown 4 0.00% 0.00% -system.ruby.Directory_Controller.NO.Data_Owner 2 0.00% 0.00% -system.ruby.Directory_Controller.NO.Data_All_Tokens 741 0.00% 0.00% -system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens 73 0.00% 0.00% -system.ruby.Directory_Controller.L.Unlockdown 19 0.00% 0.00% -system.ruby.Directory_Controller.O_W.Memory_Ack 743 0.00% 0.00% -system.ruby.Directory_Controller.L_NO_W.Memory_Data 15 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.Lockdown 15 0.00% 0.00% -system.ruby.Directory_Controller.NO_W.Memory_Data 808 0.00% 0.00% -system.ruby.L1Cache_Controller.Load 53 0.00% 0.00% -system.ruby.L1Cache_Controller.Ifetch 48 0.00% 0.00% -system.ruby.L1Cache_Controller.Store 859 0.00% 0.00% -system.ruby.L1Cache_Controller.L1_Replacement 23142 0.00% 0.00% -system.ruby.L1Cache_Controller.Data_Shared 10 0.00% 0.00% -system.ruby.L1Cache_Controller.Data_All_Tokens 869 0.00% 0.00% -system.ruby.L1Cache_Controller.Own_Lock_or_Unlock 38 0.00% 0.00% -system.ruby.L1Cache_Controller.Request_Timeout 35 0.00% 0.00% -system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers 855 0.00% 0.00% -system.ruby.L1Cache_Controller.NP.Load 47 0.00% 0.00% -system.ruby.L1Cache_Controller.NP.Ifetch 48 0.00% 0.00% -system.ruby.L1Cache_Controller.NP.Store 772 0.00% 0.00% -system.ruby.L1Cache_Controller.NP.Data_All_Tokens 13 0.00% 0.00% -system.ruby.L1Cache_Controller.NP.Own_Lock_or_Unlock 14 0.00% 0.00% -system.ruby.L1Cache_Controller.S.Load 1 0.00% 0.00% -system.ruby.L1Cache_Controller.S.Store 1 0.00% 0.00% -system.ruby.L1Cache_Controller.S.L1_Replacement 9 0.00% 0.00% -system.ruby.L1Cache_Controller.M.L1_Replacement 82 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock 3 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.Load 4 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.Store 69 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.L1_Replacement 771 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.Own_Lock_or_Unlock 2 0.00% 0.00% -system.ruby.L1Cache_Controller.M_W.L1_Replacement 624 0.00% 0.00% -system.ruby.L1Cache_Controller.M_W.Own_Lock_or_Unlock 1 0.00% 0.00% -system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers 83 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_W.Load 1 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_W.Store 17 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_W.L1_Replacement 10842 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_W.Own_Lock_or_Unlock 1 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_W.Use_TimeoutNoStarvers 772 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.L1_Replacement 10272 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.Data_All_Tokens 771 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.Own_Lock_or_Unlock 12 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.Request_Timeout 25 0.00% 0.00% -system.ruby.L1Cache_Controller.SM.Data_All_Tokens 1 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.L1_Replacement 542 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Data_Shared 10 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Data_All_Tokens 84 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Own_Lock_or_Unlock 5 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Request_Timeout 10 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETS 95 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETX 773 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement 805 0.00% 0.00% -system.ruby.L2Cache_Controller.Writeback_Shared_Data 2 0.00% 0.00% -system.ruby.L2Cache_Controller.Writeback_All_Tokens 860 0.00% 0.00% -system.ruby.L2Cache_Controller.Persistent_GETX 13 0.00% 0.00% -system.ruby.L2Cache_Controller.Persistent_GETS 6 0.00% 0.00% -system.ruby.L2Cache_Controller.Own_Lock_or_Unlock 19 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETS 85 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETX 739 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.Writeback_Shared_Data 2 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.Writeback_All_Tokens 807 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.Own_Lock_or_Unlock 19 0.00% 0.00% -system.ruby.L2Cache_Controller.I.Writeback_All_Tokens 33 0.00% 0.00% -system.ruby.L2Cache_Controller.S.L2_Replacement 2 0.00% 0.00% -system.ruby.L2Cache_Controller.O.L1_GETX 1 0.00% 0.00% -system.ruby.L2Cache_Controller.O.L2_Replacement 2 0.00% 0.00% -system.ruby.L2Cache_Controller.O.Writeback_All_Tokens 7 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETS 10 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETX 33 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement 801 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.Writeback_All_Tokens 13 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.Persistent_GETX 13 0.00% 0.00% -system.ruby.L2Cache_Controller.I_L.Persistent_GETS 6 0.00% 0.00% - ----------- End Simulation Statistics ---------- diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,1439 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000 -time_sync_spin_threshold=100000 - -[system] -type=System -children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges=0:268435455:0:0:0:0 -memories=system.mem_ctrls -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.sys_port_proxy.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=RubyTester -check_flush=true -checks_to_complete=100 -clk_domain=system.clk_domain -deadlock_threshold=50000 -default_p_state=UNDEFINED -eventq_index=0 -num_cpus=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -system=system -wakeup_frequency=10 -cpuInstDataPort=system.ruby.l1_cntrl0.sequencer.slave[0] - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000 - -[system.mem_ctrls] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -page_policy=open_adaptive -power_model=Null -range=0:268435455:5:19:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10 -static_frontend_latency=10 -tBURST=5 -tCCD_L=0 -tCK=1 -tCL=14 -tCS=3 -tRAS=35 -tRCD=14 -tREFI=7800 -tRFC=260 -tRP=14 -tRRD=6 -tRRD_L=0 -tRTP=8 -tRTW=3 -tWR=15 -tWTR=8 -tXAW=30 -tXP=6 -tXPDLL=0 -tXS=270 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.ruby.dir_cntrl0.memory - -[system.ruby] -type=RubySystem -children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network -access_backing_store=false -all_instructions=false -block_size_bytes=64 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hot_lines=false -memory_size_bits=48 -num_of_sequencers=1 -number_of_virtual_networks=6 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -phys_mem=Null -power_model=Null -randomization=true - -[system.ruby.clk_domain] -type=SrcClockDomain -clock=1 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.ruby.dir_cntrl0] -type=Directory_Controller -children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir probeFilter requestToDir responseFromDir responseFromMemory responseToDir triggerQueue unblockToDir -buffer_size=0 -clk_domain=system.ruby.clk_domain -cluster_id=0 -default_p_state=UNDEFINED -directory=system.ruby.dir_cntrl0.directory -dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir -dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir -eventq_index=0 -forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir -from_memory_controller_latency=2 -full_bit_dir_enabled=false -number_of_TBEs=256 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -probeFilter=system.ruby.dir_cntrl0.probeFilter -probe_filter_enabled=false -recycle_latency=10 -requestToDir=system.ruby.dir_cntrl0.requestToDir -responseFromDir=system.ruby.dir_cntrl0.responseFromDir -responseFromMemory=system.ruby.dir_cntrl0.responseFromMemory -responseToDir=system.ruby.dir_cntrl0.responseToDir -ruby_system=system.ruby -system=system -to_memory_controller_latency=1 -transitions_per_cycle=32 -triggerQueue=system.ruby.dir_cntrl0.triggerQueue -unblockToDir=system.ruby.dir_cntrl0.unblockToDir -version=0 -memory=system.mem_ctrls.port - -[system.ruby.dir_cntrl0.directory] -type=RubyDirectoryMemory -eventq_index=0 -numa_high_bit=5 -size=268435456 -version=0 - -[system.ruby.dir_cntrl0.dmaRequestToDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -slave=system.ruby.network.master[5] - -[system.ruby.dir_cntrl0.dmaResponseFromDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -master=system.ruby.network.slave[5] - -[system.ruby.dir_cntrl0.forwardFromDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[3] - -[system.ruby.dir_cntrl0.probeFilter] -type=RubyCache -children=replacement_policy -assoc=4 -block_size=0 -dataAccessLatency=1 -dataArrayBanks=1 -eventq_index=0 -is_icache=false -replacement_policy=system.ruby.dir_cntrl0.probeFilter.replacement_policy -resourceStalls=false -ruby_system=system.ruby -size=1024 -start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 - -[system.ruby.dir_cntrl0.probeFilter.replacement_policy] -type=PseudoLRUReplacementPolicy -assoc=4 -block_size=64 -eventq_index=0 -size=1024 - -[system.ruby.dir_cntrl0.requestToDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[4] - -[system.ruby.dir_cntrl0.responseFromDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[4] - -[system.ruby.dir_cntrl0.responseFromMemory] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false - -[system.ruby.dir_cntrl0.responseToDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[3] - -[system.ruby.dir_cntrl0.triggerQueue] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.dir_cntrl0.unblockToDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[2] - -[system.ruby.l1_cntrl0] -type=L1Cache_Controller -children=L1Dcache L1Icache L2cache forwardToCache mandatoryQueue requestFromCache responseFromCache responseToCache sequencer triggerQueue unblockFromCache -L1Dcache=system.ruby.l1_cntrl0.L1Dcache -L1Icache=system.ruby.l1_cntrl0.L1Icache -L2cache=system.ruby.l1_cntrl0.L2cache -buffer_size=0 -cache_response_latency=10 -clk_domain=system.ruby.clk_domain -cluster_id=0 -default_p_state=UNDEFINED -eventq_index=0 -forwardToCache=system.ruby.l1_cntrl0.forwardToCache -issue_latency=2 -l2_cache_hit_latency=10 -mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue -no_mig_atomic=true -number_of_TBEs=256 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -recycle_latency=10 -requestFromCache=system.ruby.l1_cntrl0.requestFromCache -responseFromCache=system.ruby.l1_cntrl0.responseFromCache -responseToCache=system.ruby.l1_cntrl0.responseToCache -ruby_system=system.ruby -send_evictions=false -sequencer=system.ruby.l1_cntrl0.sequencer -system=system -transitions_per_cycle=32 -triggerQueue=system.ruby.l1_cntrl0.triggerQueue -unblockFromCache=system.ruby.l1_cntrl0.unblockFromCache -version=0 - -[system.ruby.l1_cntrl0.L1Dcache] -type=RubyCache -children=replacement_policy -assoc=2 -block_size=0 -dataAccessLatency=1 -dataArrayBanks=1 -eventq_index=0 -is_icache=false -replacement_policy=system.ruby.l1_cntrl0.L1Dcache.replacement_policy -resourceStalls=false -ruby_system=system.ruby -size=256 -start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 - -[system.ruby.l1_cntrl0.L1Dcache.replacement_policy] -type=PseudoLRUReplacementPolicy -assoc=2 -block_size=64 -eventq_index=0 -size=256 - -[system.ruby.l1_cntrl0.L1Icache] -type=RubyCache -children=replacement_policy -assoc=2 -block_size=0 -dataAccessLatency=1 -dataArrayBanks=1 -eventq_index=0 -is_icache=true -replacement_policy=system.ruby.l1_cntrl0.L1Icache.replacement_policy -resourceStalls=false -ruby_system=system.ruby -size=256 -start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 - -[system.ruby.l1_cntrl0.L1Icache.replacement_policy] -type=PseudoLRUReplacementPolicy -assoc=2 -block_size=64 -eventq_index=0 -size=256 - -[system.ruby.l1_cntrl0.L2cache] -type=RubyCache -children=replacement_policy -assoc=2 -block_size=0 -dataAccessLatency=1 -dataArrayBanks=1 -eventq_index=0 -is_icache=false -replacement_policy=system.ruby.l1_cntrl0.L2cache.replacement_policy -resourceStalls=false -ruby_system=system.ruby -size=512 -start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 - -[system.ruby.l1_cntrl0.L2cache.replacement_policy] -type=PseudoLRUReplacementPolicy -assoc=2 -block_size=64 -eventq_index=0 -size=512 - -[system.ruby.l1_cntrl0.forwardToCache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[0] - -[system.ruby.l1_cntrl0.mandatoryQueue] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false - -[system.ruby.l1_cntrl0.requestFromCache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[0] - -[system.ruby.l1_cntrl0.responseFromCache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[1] - -[system.ruby.l1_cntrl0.responseToCache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -slave=system.ruby.network.master[1] - -[system.ruby.l1_cntrl0.sequencer] -type=RubySequencer -clk_domain=system.ruby.clk_domain -coreid=99 -dcache=system.ruby.l1_cntrl0.L1Dcache -dcache_hit_latency=1 -deadlock_threshold=500000 -default_p_state=UNDEFINED -eventq_index=0 -garnet_standalone=false -icache=system.ruby.l1_cntrl0.L1Icache -icache_hit_latency=1 -is_cpu_sequencer=true -max_outstanding_requests=16 -no_retry_on_stall=true -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -ruby_system=system.ruby -support_data_reqs=true -support_inst_reqs=true -system=system -using_ruby_tester=true -version=0 -slave=system.cpu.cpuInstDataPort[0] - -[system.ruby.l1_cntrl0.triggerQueue] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false - -[system.ruby.l1_cntrl0.unblockFromCache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[2] - -[system.ruby.memctrl_clk_domain] -type=DerivedClockDomain -clk_divider=3 -clk_domain=system.ruby.clk_domain -eventq_index=0 - -[system.ruby.network] -type=SimpleNetwork -children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_link_buffers40 int_link_buffers41 int_link_buffers42 int_link_buffers43 int_link_buffers44 int_link_buffers45 int_link_buffers46 int_link_buffers47 int_links0 int_links1 int_links2 int_links3 routers0 routers1 routers2 -adaptive_routing=false -buffer_size=0 -clk_domain=system.ruby.clk_domain -control_msg_size=8 -default_p_state=UNDEFINED -endpoint_bandwidth=1000 -eventq_index=0 -ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 -int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 system.ruby.network.int_link_buffers40 system.ruby.network.int_link_buffers41 system.ruby.network.int_link_buffers42 system.ruby.network.int_link_buffers43 system.ruby.network.int_link_buffers44 system.ruby.network.int_link_buffers45 system.ruby.network.int_link_buffers46 system.ruby.network.int_link_buffers47 -int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 -netifs= -number_of_virtual_networks=6 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 -ruby_system=system.ruby -topology=Crossbar -master=system.ruby.l1_cntrl0.forwardToCache.slave system.ruby.l1_cntrl0.responseToCache.slave system.ruby.dir_cntrl0.unblockToDir.slave system.ruby.dir_cntrl0.responseToDir.slave system.ruby.dir_cntrl0.requestToDir.slave system.ruby.dir_cntrl0.dmaRequestToDir.slave -slave=system.ruby.l1_cntrl0.requestFromCache.master system.ruby.l1_cntrl0.responseFromCache.master system.ruby.l1_cntrl0.unblockFromCache.master system.ruby.dir_cntrl0.forwardFromDir.master system.ruby.dir_cntrl0.responseFromDir.master system.ruby.dir_cntrl0.dmaResponseFromDir.master - -[system.ruby.network.ext_links0] -type=SimpleExtLink -bandwidth_factor=16 -eventq_index=0 -ext_node=system.ruby.l1_cntrl0 -int_node=system.ruby.network.routers0 -latency=1 -link_id=0 -weight=1 - -[system.ruby.network.ext_links1] -type=SimpleExtLink -bandwidth_factor=16 -eventq_index=0 -ext_node=system.ruby.dir_cntrl0 -int_node=system.ruby.network.routers1 -latency=1 -link_id=1 -weight=1 - -[system.ruby.network.int_link_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers15] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers16] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers17] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers18] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers19] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers20] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers21] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers22] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers23] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers24] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers25] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers26] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers27] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers28] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers29] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers30] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers31] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers32] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers33] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers34] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers35] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers36] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers37] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers38] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers39] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers40] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers41] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers42] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers43] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers44] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers45] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers46] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers47] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_links0] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers2 -eventq_index=0 -latency=1 -link_id=2 -src_node=system.ruby.network.routers0 -src_outport= -weight=1 - -[system.ruby.network.int_links1] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers2 -eventq_index=0 -latency=1 -link_id=3 -src_node=system.ruby.network.routers1 -src_outport= -weight=1 - -[system.ruby.network.int_links2] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers0 -eventq_index=0 -latency=1 -link_id=4 -src_node=system.ruby.network.routers2 -src_outport= -weight=1 - -[system.ruby.network.int_links3] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers1 -eventq_index=0 -latency=1 -link_id=5 -src_node=system.ruby.network.routers2 -src_outport= -weight=1 - -[system.ruby.network.routers0] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 system.ruby.network.routers0.port_buffers12 system.ruby.network.routers0.port_buffers13 system.ruby.network.routers0.port_buffers14 system.ruby.network.routers0.port_buffers15 system.ruby.network.routers0.port_buffers16 system.ruby.network.routers0.port_buffers17 -power_model=Null -router_id=0 -virt_nets=6 - -[system.ruby.network.routers0.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers15] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers16] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers17] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 system.ruby.network.routers1.port_buffers12 system.ruby.network.routers1.port_buffers13 system.ruby.network.routers1.port_buffers14 system.ruby.network.routers1.port_buffers15 system.ruby.network.routers1.port_buffers16 system.ruby.network.routers1.port_buffers17 -power_model=Null -router_id=1 -virt_nets=6 - -[system.ruby.network.routers1.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers15] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers16] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers17] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19 system.ruby.network.routers2.port_buffers20 system.ruby.network.routers2.port_buffers21 system.ruby.network.routers2.port_buffers22 system.ruby.network.routers2.port_buffers23 -power_model=Null -router_id=2 -virt_nets=6 - -[system.ruby.network.routers2.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers15] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers16] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers17] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers18] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers19] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers20] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers21] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers22] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers23] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.sys_port_proxy] -type=RubyPortProxy -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_cpu_sequencer=true -no_retry_on_stall=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -ruby_system=system.ruby -support_data_reqs=true -support_inst_reqs=true -system=system -using_ruby_tester=false -version=0 -slave=system.system_port - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,8 +0,0 @@ -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) -warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,13 +0,0 @@ -Redirecting stdout to build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer/simout -Redirecting stderr to build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 13 2016 20:24:36 -gem5 started Oct 13 2016 20:24:58 -gem5 executing on e108600-lin, pid 38873 -command line: /work/curdun01/gem5-external.hg/build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer - -Global frequency set at 1000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 31071 because Ruby Tester completed diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,699 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000031 # Number of seconds simulated -sim_ticks 31071 # Number of ticks simulated -final_tick 31071 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 307258 # Simulator tick rate (ticks/s) -host_mem_usage 409592 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 31071 # Cumulative time (in ticks) in various power states -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 55104 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 55104 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 50048 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 50048 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 861 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 861 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 782 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 782 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 1773486531 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 1773486531 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 1610762447 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 1610762447 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 3384248978 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 3384248978 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 862 # Number of read requests accepted -system.mem_ctrls.writeReqs 782 # Number of write requests accepted -system.mem_ctrls.readBursts 862 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 782 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 45632 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 9536 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 41024 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 55168 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 50048 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 149 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 111 # Number of DRAM write bursts merged with an existing one -system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 191 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 231 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 240 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 51 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::9 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 172 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 202 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 220 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 47 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts -system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 31040 # Total gap between requests -system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 862 # Read request sizes (log2) -system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 782 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 405 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 288 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::2 19 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::3 1 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 22 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 40 # What write queue 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-system.mem_ctrls.wrQLenPdf::30 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 90 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 943.644444 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 882.472849 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 228.764454 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 5 5.56% 5.56% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 1 1.11% 6.67% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 1 1.11% 7.78% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 3 3.33% 11.11% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 2 2.22% 13.33% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 78 86.67% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 90 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 40 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 17.425000 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 17.142863 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 3.754570 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::12-13 1 2.50% 2.50% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::14-15 10 25.00% 27.50% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-17 16 40.00% 67.50% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::18-19 6 15.00% 82.50% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::20-21 5 12.50% 95.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::22-23 1 2.50% 97.50% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::36-37 1 2.50% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 40 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 40 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.025000 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.024268 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 0.158114 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 39 97.50% 97.50% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 1 2.50% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 40 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 12133 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 25680 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 3565 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 17.02 # Average queueing delay per DRAM burst -system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 36.02 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 1468.64 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 1320.33 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 1775.55 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 1610.76 # Average system write bandwidth in MiByte/s -system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 21.79 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 11.47 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 10.32 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 1.76 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 25.13 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 625 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 635 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 87.66 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 94.63 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 18.88 # Average gap between requests -system.mem_ctrls.pageHitRate 91.04 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 671160 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 347760 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 8145312 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 5353632 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 8199792 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 36480 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.actPowerDownEnergy 5925264 # Energy for active power-down per rank (pJ) -system.mem_ctrls_0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrls_0.totalEnergy 30523320 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 982.373274 # Core power per rank (mW) -system.mem_ctrls_0.totalIdleTime 12994 # Total Idle time Per DRAM Rank -system.mem_ctrls_0.memoryStateTime::IDLE 11 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 780 # Time in different power states -system.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 17286 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 12994 # Time in different power states -system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 224352 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 3002880 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) -system.mem_ctrls_1.prePowerDownEnergy 2889984 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_1.selfRefreshEnergy 3655920 # Energy for self refresh per rank (pJ) -system.mem_ctrls_1.totalEnergy 11002416 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 354.105629 # Core power per rank (mW) -system.mem_ctrls_1.totalIdleTime 7526 # Total Idle time Per DRAM Rank -system.mem_ctrls_1.memoryStateTime::IDLE 7786 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 526 # Time in different power states -system.mem_ctrls_1.memoryStateTime::SREF 15233 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 7526 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 31071 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::UNDEFINED 31071 # Cumulative time (in ticks) in various power states -system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.pwrStateResidencyTicks::UNDEFINED 31071 # Cumulative time (in ticks) in various power states -system.ruby.outstanding_req_hist_seqr::bucket_size 2 -system.ruby.outstanding_req_hist_seqr::max_bucket 19 -system.ruby.outstanding_req_hist_seqr::samples 1010 -system.ruby.outstanding_req_hist_seqr::mean 15.556436 -system.ruby.outstanding_req_hist_seqr::gmean 15.445317 -system.ruby.outstanding_req_hist_seqr::stdev 1.273066 -system.ruby.outstanding_req_hist_seqr | 1 0.10% 0.10% | 2 0.20% 0.30% | 2 0.20% 0.50% | 3 0.30% 0.79% | 3 0.30% 1.09% | 6 0.59% 1.68% | 3 0.30% 1.98% | 272 26.93% 28.91% | 718 71.09% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist_seqr::total 1010 -system.ruby.latency_hist_seqr::bucket_size 128 -system.ruby.latency_hist_seqr::max_bucket 1279 -system.ruby.latency_hist_seqr::samples 995 -system.ruby.latency_hist_seqr::mean 482.717588 -system.ruby.latency_hist_seqr::gmean 245.065735 -system.ruby.latency_hist_seqr::stdev 262.743362 -system.ruby.latency_hist_seqr | 233 23.42% 23.42% | 9 0.90% 24.32% | 5 0.50% 24.82% | 58 5.83% 30.65% | 397 39.90% 70.55% | 236 23.72% 94.27% | 55 5.53% 99.80% | 2 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist_seqr::total 995 -system.ruby.hit_latency_hist_seqr::bucket_size 128 -system.ruby.hit_latency_hist_seqr::max_bucket 1279 -system.ruby.hit_latency_hist_seqr::samples 135 -system.ruby.hit_latency_hist_seqr::mean 110.851852 -system.ruby.hit_latency_hist_seqr::gmean 6.261385 -system.ruby.hit_latency_hist_seqr::stdev 224.829770 -system.ruby.hit_latency_hist_seqr | 111 82.22% 82.22% | 0 0.00% 82.22% | 0 0.00% 82.22% | 3 2.22% 84.44% | 17 12.59% 97.04% | 3 2.22% 99.26% | 0 0.00% 99.26% | 1 0.74% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist_seqr::total 135 -system.ruby.miss_latency_hist_seqr::bucket_size 128 -system.ruby.miss_latency_hist_seqr::max_bucket 1279 -system.ruby.miss_latency_hist_seqr::samples 860 -system.ruby.miss_latency_hist_seqr::mean 541.091860 -system.ruby.miss_latency_hist_seqr::gmean 435.798434 -system.ruby.miss_latency_hist_seqr::stdev 216.457686 -system.ruby.miss_latency_hist_seqr | 122 14.19% 14.19% | 9 1.05% 15.23% | 5 0.58% 15.81% | 55 6.40% 22.21% | 380 44.19% 66.40% | 233 27.09% 93.49% | 55 6.40% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist_seqr::total 860 -system.ruby.Directory.incomplete_times_seqr 860 -system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits -system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses -system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses -system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 31071 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.L1Dcache.demand_hits 79 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 852 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 931 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Icache.demand_misses 63 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Icache.demand_accesses 63 # Number of cache demand accesses -system.ruby.l1_cntrl0.L2cache.demand_hits 54 # Number of cache demand hits -system.ruby.l1_cntrl0.L2cache.demand_misses 861 # Number of cache demand misses -system.ruby.l1_cntrl0.L2cache.demand_accesses 915 # Number of cache demand accesses -system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 31071 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 3 # Number of times a store aliased with a pending load -system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 84 # Number of times a store aliased with a pending store -system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 7 # Number of times a load aliased with a pending store -system.ruby.l1_cntrl0.sequencer.load_waiting_on_load 1 # Number of times a load aliased with a pending load -system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 31071 # Cumulative time (in ticks) in various power states -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 31071 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.percent_links_utilized 14.722732 -system.ruby.network.routers0.msg_count.Request_Control::2 863 -system.ruby.network.routers0.msg_count.Response_Data::4 861 -system.ruby.network.routers0.msg_count.Writeback_Data::5 783 -system.ruby.network.routers0.msg_count.Writeback_Control::2 855 -system.ruby.network.routers0.msg_count.Writeback_Control::3 856 -system.ruby.network.routers0.msg_count.Writeback_Control::5 71 -system.ruby.network.routers0.msg_count.Unblock_Control::5 859 -system.ruby.network.routers0.msg_bytes.Request_Control::2 6904 -system.ruby.network.routers0.msg_bytes.Response_Data::4 61992 -system.ruby.network.routers0.msg_bytes.Writeback_Data::5 56376 -system.ruby.network.routers0.msg_bytes.Writeback_Control::2 6840 -system.ruby.network.routers0.msg_bytes.Writeback_Control::3 6848 -system.ruby.network.routers0.msg_bytes.Writeback_Control::5 568 -system.ruby.network.routers0.msg_bytes.Unblock_Control::5 6872 -system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 31071 # Cumulative time (in ticks) in various power states -system.ruby.network.routers1.percent_links_utilized 14.717100 -system.ruby.network.routers1.msg_count.Request_Control::2 863 -system.ruby.network.routers1.msg_count.Response_Data::4 861 -system.ruby.network.routers1.msg_count.Writeback_Data::5 782 -system.ruby.network.routers1.msg_count.Writeback_Control::2 855 -system.ruby.network.routers1.msg_count.Writeback_Control::3 856 -system.ruby.network.routers1.msg_count.Writeback_Control::5 71 -system.ruby.network.routers1.msg_count.Unblock_Control::5 859 -system.ruby.network.routers1.msg_bytes.Request_Control::2 6904 -system.ruby.network.routers1.msg_bytes.Response_Data::4 61992 -system.ruby.network.routers1.msg_bytes.Writeback_Data::5 56304 -system.ruby.network.routers1.msg_bytes.Writeback_Control::2 6840 -system.ruby.network.routers1.msg_bytes.Writeback_Control::3 6848 -system.ruby.network.routers1.msg_bytes.Writeback_Control::5 568 -system.ruby.network.routers1.msg_bytes.Unblock_Control::5 6872 -system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 31071 # Cumulative time (in ticks) in various power states -system.ruby.network.routers2.percent_links_utilized 14.720318 -system.ruby.network.routers2.msg_count.Request_Control::2 863 -system.ruby.network.routers2.msg_count.Response_Data::4 861 -system.ruby.network.routers2.msg_count.Writeback_Data::5 783 -system.ruby.network.routers2.msg_count.Writeback_Control::2 855 -system.ruby.network.routers2.msg_count.Writeback_Control::3 856 -system.ruby.network.routers2.msg_count.Writeback_Control::5 71 -system.ruby.network.routers2.msg_count.Unblock_Control::5 859 -system.ruby.network.routers2.msg_bytes.Request_Control::2 6904 -system.ruby.network.routers2.msg_bytes.Response_Data::4 61992 -system.ruby.network.routers2.msg_bytes.Writeback_Data::5 56376 -system.ruby.network.routers2.msg_bytes.Writeback_Control::2 6840 -system.ruby.network.routers2.msg_bytes.Writeback_Control::3 6848 -system.ruby.network.routers2.msg_bytes.Writeback_Control::5 568 -system.ruby.network.routers2.msg_bytes.Unblock_Control::5 6872 -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 31071 # Cumulative time (in ticks) in various power states -system.ruby.network.msg_count.Request_Control 2589 -system.ruby.network.msg_count.Response_Data 2583 -system.ruby.network.msg_count.Writeback_Data 2348 -system.ruby.network.msg_count.Writeback_Control 5346 -system.ruby.network.msg_count.Unblock_Control 2577 -system.ruby.network.msg_byte.Request_Control 20712 -system.ruby.network.msg_byte.Response_Data 185976 -system.ruby.network.msg_byte.Writeback_Data 169056 -system.ruby.network.msg_byte.Writeback_Control 42768 -system.ruby.network.msg_byte.Unblock_Control 20616 -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 31071 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.throttle0.link_utilization 13.845708 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 861 -system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 856 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 61992 -system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 6848 -system.ruby.network.routers0.throttle1.link_utilization 15.599755 -system.ruby.network.routers0.throttle1.msg_count.Request_Control::2 863 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::5 783 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::2 855 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::5 71 -system.ruby.network.routers0.throttle1.msg_count.Unblock_Control::5 859 -system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::2 6904 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::5 56376 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::2 6840 -system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::5 568 -system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::5 6872 -system.ruby.network.routers1.throttle0.link_utilization 15.586882 -system.ruby.network.routers1.throttle0.msg_count.Request_Control::2 863 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::5 782 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::2 855 -system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::5 71 -system.ruby.network.routers1.throttle0.msg_count.Unblock_Control::5 859 -system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::2 6904 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::5 56304 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::2 6840 -system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::5 568 -system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::5 6872 -system.ruby.network.routers1.throttle1.link_utilization 13.847317 -system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 861 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 856 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 61992 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 6848 -system.ruby.network.routers2.throttle0.link_utilization 13.847317 -system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 861 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 856 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 61992 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 6848 -system.ruby.network.routers2.throttle1.link_utilization 15.593319 -system.ruby.network.routers2.throttle1.msg_count.Request_Control::2 863 -system.ruby.network.routers2.throttle1.msg_count.Writeback_Data::5 783 -system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::2 855 -system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::5 71 -system.ruby.network.routers2.throttle1.msg_count.Unblock_Control::5 859 -system.ruby.network.routers2.throttle1.msg_bytes.Request_Control::2 6904 -system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Data::5 56376 -system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::2 6840 -system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::5 568 -system.ruby.network.routers2.throttle1.msg_bytes.Unblock_Control::5 6872 -system.ruby.LD.latency_hist_seqr::bucket_size 128 -system.ruby.LD.latency_hist_seqr::max_bucket 1279 -system.ruby.LD.latency_hist_seqr::samples 37 -system.ruby.LD.latency_hist_seqr::mean 484.027027 -system.ruby.LD.latency_hist_seqr::gmean 206.042037 -system.ruby.LD.latency_hist_seqr::stdev 286.676016 -system.ruby.LD.latency_hist_seqr | 10 27.03% 27.03% | 0 0.00% 27.03% | 0 0.00% 27.03% | 0 0.00% 27.03% | 12 32.43% 59.46% | 13 35.14% 94.59% | 2 5.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist_seqr::total 37 -system.ruby.LD.hit_latency_hist_seqr::bucket_size 64 -system.ruby.LD.hit_latency_hist_seqr::max_bucket 639 -system.ruby.LD.hit_latency_hist_seqr::samples 6 -system.ruby.LD.hit_latency_hist_seqr::mean 104 -system.ruby.LD.hit_latency_hist_seqr::gmean 4.461922 -system.ruby.LD.hit_latency_hist_seqr::stdev 246.465413 -system.ruby.LD.hit_latency_hist_seqr | 5 83.33% 83.33% | 0 0.00% 83.33% | 0 0.00% 83.33% | 0 0.00% 83.33% | 0 0.00% 83.33% | 0 0.00% 83.33% | 0 0.00% 83.33% | 0 0.00% 83.33% | 0 0.00% 83.33% | 1 16.67% 100.00% -system.ruby.LD.hit_latency_hist_seqr::total 6 -system.ruby.LD.miss_latency_hist_seqr::bucket_size 128 -system.ruby.LD.miss_latency_hist_seqr::max_bucket 1279 -system.ruby.LD.miss_latency_hist_seqr::samples 31 -system.ruby.LD.miss_latency_hist_seqr::mean 557.580645 -system.ruby.LD.miss_latency_hist_seqr::gmean 432.617733 -system.ruby.LD.miss_latency_hist_seqr::stdev 232.424149 -system.ruby.LD.miss_latency_hist_seqr | 5 16.13% 16.13% | 0 0.00% 16.13% | 0 0.00% 16.13% | 0 0.00% 16.13% | 11 35.48% 51.61% | 13 41.94% 93.55% | 2 6.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist_seqr::total 31 -system.ruby.ST.latency_hist_seqr::bucket_size 128 -system.ruby.ST.latency_hist_seqr::max_bucket 1279 -system.ruby.ST.latency_hist_seqr::samples 893 -system.ruby.ST.latency_hist_seqr::mean 513.324748 -system.ruby.ST.latency_hist_seqr::gmean 281.060775 -system.ruby.ST.latency_hist_seqr::stdev 242.626948 -system.ruby.ST.latency_hist_seqr | 160 17.92% 17.92% | 8 0.90% 18.81% | 5 0.56% 19.37% | 58 6.49% 25.87% | 385 43.11% 68.98% | 223 24.97% 93.95% | 53 5.94% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist_seqr::total 893 -system.ruby.ST.hit_latency_hist_seqr::bucket_size 128 -system.ruby.ST.hit_latency_hist_seqr::max_bucket 1279 -system.ruby.ST.hit_latency_hist_seqr::samples 116 -system.ruby.ST.hit_latency_hist_seqr::mean 114.353448 -system.ruby.ST.hit_latency_hist_seqr::gmean 5.688161 -system.ruby.ST.hit_latency_hist_seqr::stdev 222.966921 -system.ruby.ST.hit_latency_hist_seqr | 94 81.03% 81.03% | 0 0.00% 81.03% | 0 0.00% 81.03% | 3 2.59% 83.62% | 16 13.79% 97.41% | 3 2.59% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist_seqr::total 116 -system.ruby.ST.miss_latency_hist_seqr::bucket_size 128 -system.ruby.ST.miss_latency_hist_seqr::max_bucket 1279 -system.ruby.ST.miss_latency_hist_seqr::samples 777 -system.ruby.ST.miss_latency_hist_seqr::mean 572.888031 -system.ruby.ST.miss_latency_hist_seqr::gmean 503.124564 -system.ruby.ST.miss_latency_hist_seqr::stdev 181.530163 -system.ruby.ST.miss_latency_hist_seqr | 66 8.49% 8.49% | 8 1.03% 9.52% | 5 0.64% 10.17% | 55 7.08% 17.25% | 369 47.49% 64.74% | 220 28.31% 93.05% | 53 6.82% 99.87% | 1 0.13% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist_seqr::total 777 -system.ruby.IFETCH.latency_hist_seqr::bucket_size 32 -system.ruby.IFETCH.latency_hist_seqr::max_bucket 319 -system.ruby.IFETCH.latency_hist_seqr::samples 63 -system.ruby.IFETCH.latency_hist_seqr::mean 48.269841 -system.ruby.IFETCH.latency_hist_seqr::gmean 39.118214 -system.ruby.IFETCH.latency_hist_seqr::stdev 28.730790 -system.ruby.IFETCH.latency_hist_seqr | 25 39.68% 39.68% | 19 30.16% 69.84% | 18 28.57% 98.41% | 0 0.00% 98.41% | 0 0.00% 98.41% | 1 1.59% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist_seqr::total 63 -system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 2 -system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 19 -system.ruby.IFETCH.hit_latency_hist_seqr::samples 11 -system.ruby.IFETCH.hit_latency_hist_seqr::mean 11 -system.ruby.IFETCH.hit_latency_hist_seqr::gmean 11.000000 -system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 11 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist_seqr::total 11 -system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 32 -system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 319 -system.ruby.IFETCH.miss_latency_hist_seqr::samples 52 -system.ruby.IFETCH.miss_latency_hist_seqr::mean 56.153846 -system.ruby.IFETCH.miss_latency_hist_seqr::gmean 51.160387 -system.ruby.IFETCH.miss_latency_hist_seqr::stdev 25.308593 -system.ruby.IFETCH.miss_latency_hist_seqr | 14 26.92% 26.92% | 19 36.54% 63.46% | 18 34.62% 98.08% | 0 0.00% 98.08% | 0 0.00% 98.08% | 1 1.92% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.miss_latency_hist_seqr::total 52 -system.ruby.FLUSH.latency_hist_seqr::bucket_size 128 -system.ruby.FLUSH.latency_hist_seqr::max_bucket 1279 -system.ruby.FLUSH.latency_hist_seqr::samples 2 -system.ruby.FLUSH.latency_hist_seqr::mean 477.500000 -system.ruby.FLUSH.latency_hist_seqr::gmean 204.484718 -system.ruby.FLUSH.latency_hist_seqr::stdev 610.233152 -system.ruby.FLUSH.latency_hist_seqr | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.FLUSH.latency_hist_seqr::total 2 -system.ruby.FLUSH.hit_latency_hist_seqr::bucket_size 128 -system.ruby.FLUSH.hit_latency_hist_seqr::max_bucket 1279 -system.ruby.FLUSH.hit_latency_hist_seqr::samples 2 -system.ruby.FLUSH.hit_latency_hist_seqr::mean 477.500000 -system.ruby.FLUSH.hit_latency_hist_seqr::gmean 204.484718 -system.ruby.FLUSH.hit_latency_hist_seqr::stdev 610.233152 -system.ruby.FLUSH.hit_latency_hist_seqr | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.FLUSH.hit_latency_hist_seqr::total 2 -system.ruby.L1Cache.hit_mach_latency_hist_seqr::bucket_size 128 -system.ruby.L1Cache.hit_mach_latency_hist_seqr::max_bucket 1279 -system.ruby.L1Cache.hit_mach_latency_hist_seqr::samples 81 -system.ruby.L1Cache.hit_mach_latency_hist_seqr::mean 12.765432 -system.ruby.L1Cache.hit_mach_latency_hist_seqr::gmean 1.140390 -system.ruby.L1Cache.hit_mach_latency_hist_seqr::stdev 100.950269 -system.ruby.L1Cache.hit_mach_latency_hist_seqr | 80 98.77% 98.77% | 0 0.00% 98.77% | 0 0.00% 98.77% | 0 0.00% 98.77% | 0 0.00% 98.77% | 0 0.00% 98.77% | 0 0.00% 98.77% | 1 1.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L1Cache.hit_mach_latency_hist_seqr::total 81 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::bucket_size 128 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::max_bucket 1279 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::samples 54 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::mean 257.981481 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::gmean 80.555654 -system.ruby.L2Cache.hit_mach_latency_hist_seqr::stdev 275.063320 -system.ruby.L2Cache.hit_mach_latency_hist_seqr | 31 57.41% 57.41% | 0 0.00% 57.41% | 0 0.00% 57.41% | 3 5.56% 62.96% | 17 31.48% 94.44% | 3 5.56% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.L2Cache.hit_mach_latency_hist_seqr::total 54 -system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 128 -system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 1279 -system.ruby.Directory.miss_mach_latency_hist_seqr::samples 860 -system.ruby.Directory.miss_mach_latency_hist_seqr::mean 541.091860 -system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 435.798434 -system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 216.457686 -system.ruby.Directory.miss_mach_latency_hist_seqr | 122 14.19% 14.19% | 9 1.05% 15.23% | 5 0.58% 15.81% | 55 6.40% 22.21% | 380 44.19% 66.40% | 233 27.09% 93.49% | 55 6.40% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_mach_latency_hist_seqr::total 860 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::samples 4 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::mean 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1 -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 4 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::total 4 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 64 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 639 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::samples 2 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::mean 310 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::gmean 88.831301 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::stdev 420.021428 -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% -system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::total 2 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 128 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 1279 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 31 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 557.580645 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 432.617733 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 232.424149 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 5 16.13% 16.13% | 0 0.00% 16.13% | 0 0.00% 16.13% | 0 0.00% 16.13% | 11 35.48% 51.61% | 13 41.94% 93.55% | 2 6.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 31 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::samples 75 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::mean 1 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1 -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 75 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::total 75 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 128 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 1279 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::samples 41 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::mean 321.707317 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::gmean 136.778519 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::stdev 273.433835 -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr | 19 46.34% 46.34% | 0 0.00% 46.34% | 0 0.00% 46.34% | 3 7.32% 53.66% | 16 39.02% 92.68% | 3 7.32% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::total 41 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 128 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 1279 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 777 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 572.888031 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 503.124564 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 181.530163 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 66 8.49% 8.49% | 8 1.03% 9.52% | 5 0.64% 10.17% | 55 7.08% 17.25% | 369 47.49% 64.74% | 220 28.31% 93.05% | 53 6.82% 99.87% | 1 0.13% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 777 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 2 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 19 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::samples 11 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::mean 11 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::gmean 11.000000 -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 11 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::total 11 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 52 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 56.153846 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 51.160387 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 25.308593 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 14 26.92% 26.92% | 19 36.54% 63.46% | 18 34.62% 98.08% | 0 0.00% 98.08% | 0 0.00% 98.08% | 1 1.92% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 52 -system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 128 -system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 1279 -system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist_seqr::samples 2 -system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist_seqr::mean 477.500000 -system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist_seqr::gmean 204.484718 -system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist_seqr::stdev 610.233152 -system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist_seqr | 1 50.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.FLUSH.L1Cache.hit_type_mach_latency_hist_seqr::total 2 -system.ruby.Directory_Controller.GETX 778 0.00% 0.00% -system.ruby.Directory_Controller.GETS 84 0.00% 0.00% -system.ruby.Directory_Controller.PUT 1099 0.00% 0.00% -system.ruby.Directory_Controller.UnblockM 859 0.00% 0.00% -system.ruby.Directory_Controller.Writeback_Exclusive_Clean 71 0.00% 0.00% -system.ruby.Directory_Controller.Writeback_Exclusive_Dirty 782 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 861 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 782 0.00% 0.00% -system.ruby.Directory_Controller.GETF 2 0.00% 0.00% -system.ruby.Directory_Controller.PUTF 2 0.00% 0.00% -system.ruby.Directory_Controller.NO.PUT 853 0.00% 0.00% -system.ruby.Directory_Controller.NO.GETF 1 0.00% 0.00% -system.ruby.Directory_Controller.E.GETX 778 0.00% 0.00% -system.ruby.Directory_Controller.E.GETS 83 0.00% 0.00% -system.ruby.Directory_Controller.E.GETF 1 0.00% 0.00% -system.ruby.Directory_Controller.NO_B.PUT 246 0.00% 0.00% -system.ruby.Directory_Controller.NO_B.UnblockM 859 0.00% 0.00% -system.ruby.Directory_Controller.NO_B_W.Memory_Data 860 0.00% 0.00% -system.ruby.Directory_Controller.WB.GETS 1 0.00% 0.00% -system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean 71 0.00% 0.00% -system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty 782 0.00% 0.00% -system.ruby.Directory_Controller.WB_E_W.Memory_Ack 782 0.00% 0.00% -system.ruby.Directory_Controller.NO_F.PUTF 2 0.00% 0.00% -system.ruby.Directory_Controller.NO_F_W.Memory_Data 1 0.00% 0.00% -system.ruby.L1Cache_Controller.Load 39 0.00% 0.00% -system.ruby.L1Cache_Controller.Ifetch 64 0.00% 0.00% -system.ruby.L1Cache_Controller.Store 934 0.00% 0.00% -system.ruby.L1Cache_Controller.L2_Replacement 853 0.00% 0.00% -system.ruby.L1Cache_Controller.L1_to_L2 18403 0.00% 0.00% -system.ruby.L1Cache_Controller.Trigger_L2_to_L1D 44 0.00% 0.00% -system.ruby.L1Cache_Controller.Trigger_L2_to_L1I 11 0.00% 0.00% -system.ruby.L1Cache_Controller.Complete_L2_to_L1 55 0.00% 0.00% -system.ruby.L1Cache_Controller.Exclusive_Data 861 0.00% 0.00% -system.ruby.L1Cache_Controller.Writeback_Ack 855 0.00% 0.00% -system.ruby.L1Cache_Controller.All_acks_no_sharers 861 0.00% 0.00% -system.ruby.L1Cache_Controller.Flush_line 2 0.00% 0.00% -system.ruby.L1Cache_Controller.Block_Ack 1 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Load 31 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Ifetch 52 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Store 778 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Flush_line 1 0.00% 0.00% -system.ruby.L1Cache_Controller.M.L2_Replacement 71 0.00% 0.00% -system.ruby.L1Cache_Controller.M.L1_to_L2 81 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1D 10 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.Load 4 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.Store 75 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.L2_Replacement 782 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.L1_to_L2 829 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1D 34 0.00% 0.00% -system.ruby.L1Cache_Controller.MM.Trigger_L2_to_L1I 11 0.00% 0.00% -system.ruby.L1Cache_Controller.MR.Store 10 0.00% 0.00% -system.ruby.L1Cache_Controller.MR.L1_to_L2 114 0.00% 0.00% -system.ruby.L1Cache_Controller.MMR.Load 2 0.00% 0.00% -system.ruby.L1Cache_Controller.MMR.Ifetch 11 0.00% 0.00% -system.ruby.L1Cache_Controller.MMR.Store 31 0.00% 0.00% -system.ruby.L1Cache_Controller.MMR.L1_to_L2 14 0.00% 0.00% -system.ruby.L1Cache_Controller.MMR.Flush_line 1 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.L1_to_L2 10904 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.Exclusive_Data 777 0.00% 0.00% -system.ruby.L1Cache_Controller.M_W.L1_to_L2 223 0.00% 0.00% -system.ruby.L1Cache_Controller.M_W.All_acks_no_sharers 83 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_W.L1_to_L2 5430 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_W.All_acks_no_sharers 777 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.L1_to_L2 455 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Exclusive_Data 83 0.00% 0.00% -system.ruby.L1Cache_Controller.MI.Ifetch 1 0.00% 0.00% -system.ruby.L1Cache_Controller.MI.Store 1 0.00% 0.00% -system.ruby.L1Cache_Controller.MI.Writeback_Ack 853 0.00% 0.00% -system.ruby.L1Cache_Controller.MT.Store 9 0.00% 0.00% -system.ruby.L1Cache_Controller.MT.L1_to_L2 130 0.00% 0.00% -system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1 10 0.00% 0.00% -system.ruby.L1Cache_Controller.MMT.Load 2 0.00% 0.00% -system.ruby.L1Cache_Controller.MMT.Store 30 0.00% 0.00% -system.ruby.L1Cache_Controller.MMT.L1_to_L2 223 0.00% 0.00% -system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1 45 0.00% 0.00% -system.ruby.L1Cache_Controller.MI_F.Writeback_Ack 2 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_F.Block_Ack 1 0.00% 0.00% -system.ruby.L1Cache_Controller.IM_F.Exclusive_Data 1 0.00% 0.00% -system.ruby.L1Cache_Controller.MM_WF.All_acks_no_sharers 1 0.00% 0.00% - ----------- End Simulation Statistics ---------- diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,1191 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000 -time_sync_spin_threshold=100000 - -[system] -type=System -children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges=0:268435455:0:0:0:0 -memories=system.mem_ctrls -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.sys_port_proxy.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=RubyTester -check_flush=false -checks_to_complete=100 -clk_domain=system.clk_domain -deadlock_threshold=50000 -default_p_state=UNDEFINED -eventq_index=0 -num_cpus=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -system=system -wakeup_frequency=10 -cpuInstDataPort=system.ruby.l1_cntrl0.sequencer.slave[0] - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000 - -[system.mem_ctrls] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -page_policy=open_adaptive -power_model=Null -range=0:268435455:5:19:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10 -static_frontend_latency=10 -tBURST=5 -tCCD_L=0 -tCK=1 -tCL=14 -tCS=3 -tRAS=35 -tRCD=14 -tREFI=7800 -tRFC=260 -tRP=14 -tRRD=6 -tRRD_L=0 -tRTP=8 -tRTW=3 -tWR=15 -tWTR=8 -tXAW=30 -tXP=6 -tXPDLL=0 -tXS=270 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.ruby.dir_cntrl0.memory - -[system.ruby] -type=RubySystem -children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network -access_backing_store=false -all_instructions=false -block_size_bytes=64 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hot_lines=false -memory_size_bits=48 -num_of_sequencers=1 -number_of_virtual_networks=5 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -phys_mem=Null -power_model=Null -randomization=true - -[system.ruby.clk_domain] -type=SrcClockDomain -clock=1 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.ruby.dir_cntrl0] -type=Directory_Controller -children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir requestToDir responseFromDir responseFromMemory -buffer_size=0 -clk_domain=system.ruby.clk_domain -cluster_id=0 -default_p_state=UNDEFINED -directory=system.ruby.dir_cntrl0.directory -directory_latency=12 -dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir -dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir -eventq_index=0 -forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir -number_of_TBEs=256 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -recycle_latency=10 -requestToDir=system.ruby.dir_cntrl0.requestToDir -responseFromDir=system.ruby.dir_cntrl0.responseFromDir -responseFromMemory=system.ruby.dir_cntrl0.responseFromMemory -ruby_system=system.ruby -system=system -to_memory_controller_latency=1 -transitions_per_cycle=32 -version=0 -memory=system.mem_ctrls.port - -[system.ruby.dir_cntrl0.directory] -type=RubyDirectoryMemory -eventq_index=0 -numa_high_bit=5 -size=268435456 -version=0 - -[system.ruby.dir_cntrl0.dmaRequestToDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -slave=system.ruby.network.master[3] - -[system.ruby.dir_cntrl0.dmaResponseFromDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -master=system.ruby.network.slave[3] - -[system.ruby.dir_cntrl0.forwardFromDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[4] - -[system.ruby.dir_cntrl0.requestToDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -slave=system.ruby.network.master[2] - -[system.ruby.dir_cntrl0.responseFromDir] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false -master=system.ruby.network.slave[2] - -[system.ruby.dir_cntrl0.responseFromMemory] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false - -[system.ruby.l1_cntrl0] -type=L1Cache_Controller -children=cacheMemory forwardToCache mandatoryQueue requestFromCache responseFromCache responseToCache sequencer -buffer_size=0 -cacheMemory=system.ruby.l1_cntrl0.cacheMemory -cache_response_latency=12 -clk_domain=system.ruby.clk_domain -cluster_id=0 -default_p_state=UNDEFINED -eventq_index=0 -forwardToCache=system.ruby.l1_cntrl0.forwardToCache -issue_latency=2 -mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue -number_of_TBEs=256 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -recycle_latency=10 -requestFromCache=system.ruby.l1_cntrl0.requestFromCache -responseFromCache=system.ruby.l1_cntrl0.responseFromCache -responseToCache=system.ruby.l1_cntrl0.responseToCache -ruby_system=system.ruby -send_evictions=false -sequencer=system.ruby.l1_cntrl0.sequencer -system=system -transitions_per_cycle=32 -version=0 - -[system.ruby.l1_cntrl0.cacheMemory] -type=RubyCache -children=replacement_policy -assoc=2 -block_size=0 -dataAccessLatency=1 -dataArrayBanks=1 -eventq_index=0 -is_icache=false -replacement_policy=system.ruby.l1_cntrl0.cacheMemory.replacement_policy -resourceStalls=false -ruby_system=system.ruby -size=256 -start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 - -[system.ruby.l1_cntrl0.cacheMemory.replacement_policy] -type=PseudoLRUReplacementPolicy -assoc=2 -block_size=64 -eventq_index=0 -size=256 - -[system.ruby.l1_cntrl0.forwardToCache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -slave=system.ruby.network.master[0] - -[system.ruby.l1_cntrl0.mandatoryQueue] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=false -randomization=false - -[system.ruby.l1_cntrl0.requestFromCache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -master=system.ruby.network.slave[0] - -[system.ruby.l1_cntrl0.responseFromCache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -master=system.ruby.network.slave[1] - -[system.ruby.l1_cntrl0.responseToCache] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false -slave=system.ruby.network.master[1] - -[system.ruby.l1_cntrl0.sequencer] -type=RubySequencer -clk_domain=system.ruby.clk_domain -coreid=99 -dcache=system.ruby.l1_cntrl0.cacheMemory -dcache_hit_latency=1 -deadlock_threshold=500000 -default_p_state=UNDEFINED -eventq_index=0 -garnet_standalone=false -icache=system.ruby.l1_cntrl0.cacheMemory -icache_hit_latency=1 -is_cpu_sequencer=true -max_outstanding_requests=16 -no_retry_on_stall=true -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -ruby_system=system.ruby -support_data_reqs=true -support_inst_reqs=true -system=system -using_ruby_tester=true -version=0 -slave=system.cpu.cpuInstDataPort[0] - -[system.ruby.memctrl_clk_domain] -type=DerivedClockDomain -clk_divider=3 -clk_domain=system.ruby.clk_domain -eventq_index=0 - -[system.ruby.network] -type=SimpleNetwork -children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_links0 int_links1 int_links2 int_links3 routers0 routers1 routers2 -adaptive_routing=false -buffer_size=0 -clk_domain=system.ruby.clk_domain -control_msg_size=8 -default_p_state=UNDEFINED -endpoint_bandwidth=1000 -eventq_index=0 -ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 -int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 -int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 -netifs= -number_of_virtual_networks=5 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 -ruby_system=system.ruby -topology=Crossbar -master=system.ruby.l1_cntrl0.forwardToCache.slave system.ruby.l1_cntrl0.responseToCache.slave system.ruby.dir_cntrl0.requestToDir.slave system.ruby.dir_cntrl0.dmaRequestToDir.slave -slave=system.ruby.l1_cntrl0.requestFromCache.master system.ruby.l1_cntrl0.responseFromCache.master system.ruby.dir_cntrl0.responseFromDir.master system.ruby.dir_cntrl0.dmaResponseFromDir.master system.ruby.dir_cntrl0.forwardFromDir.master - -[system.ruby.network.ext_links0] -type=SimpleExtLink -bandwidth_factor=16 -eventq_index=0 -ext_node=system.ruby.l1_cntrl0 -int_node=system.ruby.network.routers0 -latency=1 -link_id=0 -weight=1 - -[system.ruby.network.ext_links1] -type=SimpleExtLink -bandwidth_factor=16 -eventq_index=0 -ext_node=system.ruby.dir_cntrl0 -int_node=system.ruby.network.routers1 -latency=1 -link_id=1 -weight=1 - -[system.ruby.network.int_link_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers15] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers16] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers17] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers18] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - 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-[system.ruby.network.int_link_buffers34] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers35] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers36] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers37] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers38] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_link_buffers39] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.int_links0] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers2 -eventq_index=0 -latency=1 -link_id=2 -src_node=system.ruby.network.routers0 -src_outport= -weight=1 - -[system.ruby.network.int_links1] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers2 -eventq_index=0 -latency=1 -link_id=3 -src_node=system.ruby.network.routers1 -src_outport= -weight=1 - -[system.ruby.network.int_links2] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers0 -eventq_index=0 -latency=1 -link_id=4 -src_node=system.ruby.network.routers2 -src_outport= -weight=1 - -[system.ruby.network.int_links3] -type=SimpleIntLink -bandwidth_factor=16 -dst_inport= -dst_node=system.ruby.network.routers1 -eventq_index=0 -latency=1 -link_id=5 -src_node=system.ruby.network.routers2 -src_outport= -weight=1 - -[system.ruby.network.routers0] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 system.ruby.network.routers0.port_buffers12 system.ruby.network.routers0.port_buffers13 system.ruby.network.routers0.port_buffers14 -power_model=Null -router_id=0 -virt_nets=5 - -[system.ruby.network.routers0.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers0.port_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 system.ruby.network.routers1.port_buffers12 system.ruby.network.routers1.port_buffers13 system.ruby.network.routers1.port_buffers14 -power_model=Null -router_id=1 -virt_nets=5 - -[system.ruby.network.routers1.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers1.port_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2] -type=Switch -children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 -clk_domain=system.ruby.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19 -power_model=Null -router_id=2 -virt_nets=5 - -[system.ruby.network.routers2.port_buffers00] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers01] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers02] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers03] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers04] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers05] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers06] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers07] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers08] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers09] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers10] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers11] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers12] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers13] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers14] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers15] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers16] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers17] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers18] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.ruby.network.routers2.port_buffers19] -type=MessageBuffer -buffer_size=0 -eventq_index=0 -ordered=true -randomization=false - -[system.sys_port_proxy] -type=RubyPortProxy -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_cpu_sequencer=true -no_retry_on_stall=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000 -p_state_clk_gate_min=1 -power_model=Null -ruby_system=system.ruby -support_data_reqs=true -support_inst_reqs=true -system=system -using_ruby_tester=false -version=0 -slave=system.system_port - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,8 +0,0 @@ -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: rounding error > tolerance - 1.250000 rounded to 1 -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) -warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,13 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:19:45 -gem5 executing on e108600-lin, pid 28072 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/60.rubytest/alpha/linux/rubytest-ruby - -Global frequency set at 1000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 39431 because Ruby Tester completed diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,539 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000039 # Number of seconds simulated -sim_ticks 39431 # Number of ticks simulated -final_tick 39431 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 979592 # Simulator tick rate (ticks/s) -host_mem_usage 407616 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 39431 # Cumulative time (in ticks) in various power states -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 60224 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 60224 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 60032 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 60032 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 941 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 941 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 938 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 938 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 1527326215 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 1527326215 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 1522456950 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 1522456950 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 3049783166 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 3049783166 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 941 # Number of read requests accepted -system.mem_ctrls.writeReqs 938 # Number of write requests accepted -system.mem_ctrls.readBursts 941 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 938 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 50560 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 9664 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 49728 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 60224 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 60032 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 151 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 134 # Number of DRAM write bursts merged with an existing one -system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 259 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 247 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 238 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 46 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::9 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 258 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 243 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 232 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 44 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts -system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 39357 # Total gap between requests -system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 941 # Read request sizes (log2) -system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 938 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 461 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 328 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::2 1 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 2 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 36 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 47 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 48 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 49 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 49 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 52 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 49 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 49 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 49 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 51 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 67 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 48 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 48 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 48 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 48 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 48 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 108 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 925.629630 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 827.187599 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 260.509945 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 4 3.70% 3.70% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 3 2.78% 6.48% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 2 1.85% 8.33% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 2 1.85% 10.19% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 1 0.93% 11.11% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 1 0.93% 12.04% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 1 0.93% 12.96% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 3 2.78% 15.74% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 91 84.26% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 108 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 48 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 16.229167 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 16.080832 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 2.837736 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::14-15 10 20.83% 20.83% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-17 37 77.08% 97.92% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::34-35 1 2.08% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 48 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 48 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.187500 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.181743 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 0.445127 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 40 83.33% 83.33% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 7 14.58% 97.92% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 1 2.08% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 48 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 14435 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 29445 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 3950 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 18.27 # Average queueing delay per DRAM burst -system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 37.27 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 1282.24 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 1261.14 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 1527.33 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 1522.46 # Average system write bandwidth in MiByte/s -system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 19.87 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 10.02 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 9.85 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 1.68 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 25.86 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 690 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 766 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 87.34 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 95.27 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 20.95 # Average gap between requests -system.mem_ctrls.pageHitRate 91.34 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 792540 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 417312 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 9024960 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 6489504 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 3073200.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 9767064 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 64896 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.actPowerDownEnergy 8135040 # Energy for active power-down per rank (pJ) -system.mem_ctrls_0.prePowerDownEnergy 1152 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrls_0.totalEnergy 37765668 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 957.765920 # Core power per rank (mW) -system.mem_ctrls_0.totalIdleTime 17819 # Total Idle time Per DRAM Rank -system.mem_ctrls_0.memoryStateTime::IDLE 29 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 1300 # Time in different power states -system.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::PRE_PDN 3 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 20259 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 17840 # Time in different power states -system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 224352 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 3002880 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) -system.mem_ctrls_1.prePowerDownEnergy 2889984 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_1.selfRefreshEnergy 5662320 # Energy for self refresh per rank (pJ) -system.mem_ctrls_1.totalEnergy 13008816 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 329.913418 # Core power per rank (mW) -system.mem_ctrls_1.totalIdleTime 7526 # Total Idle time Per DRAM Rank -system.mem_ctrls_1.memoryStateTime::IDLE 7786 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 526 # Time in different power states -system.mem_ctrls_1.memoryStateTime::SREF 23593 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 7526 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 39431 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::UNDEFINED 39431 # Cumulative time (in ticks) in various power states -system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.pwrStateResidencyTicks::UNDEFINED 39431 # Cumulative time (in ticks) in various power states -system.ruby.delayHist::bucket_size 1 # delay histogram for all message -system.ruby.delayHist::max_bucket 9 # delay histogram for all message -system.ruby.delayHist::samples 1878 # delay histogram for all message -system.ruby.delayHist::mean 0.221512 # delay histogram for all message -system.ruby.delayHist::stdev 1.129790 # delay histogram for all message -system.ruby.delayHist | 1808 96.27% 96.27% | 0 0.00% 96.27% | 1 0.05% 96.33% | 0 0.00% 96.33% | 0 0.00% 96.33% | 0 0.00% 96.33% | 69 3.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 1878 # delay histogram for all message -system.ruby.outstanding_req_hist_seqr::bucket_size 2 -system.ruby.outstanding_req_hist_seqr::max_bucket 19 -system.ruby.outstanding_req_hist_seqr::samples 997 -system.ruby.outstanding_req_hist_seqr::mean 15.607823 -system.ruby.outstanding_req_hist_seqr::gmean 15.499600 -system.ruby.outstanding_req_hist_seqr::stdev 1.240894 -system.ruby.outstanding_req_hist_seqr | 1 0.10% 0.10% | 2 0.20% 0.30% | 2 0.20% 0.50% | 2 0.20% 0.70% | 4 0.40% 1.10% | 2 0.20% 1.30% | 4 0.40% 1.71% | 227 22.77% 24.47% | 753 75.53% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist_seqr::total 997 -system.ruby.latency_hist_seqr::bucket_size 128 -system.ruby.latency_hist_seqr::max_bucket 1279 -system.ruby.latency_hist_seqr::samples 982 -system.ruby.latency_hist_seqr::mean 622.683299 -system.ruby.latency_hist_seqr::gmean 611.609969 -system.ruby.latency_hist_seqr::stdev 106.877832 -system.ruby.latency_hist_seqr | 2 0.20% 0.20% | 7 0.71% 0.92% | 6 0.61% 1.53% | 88 8.96% 10.49% | 458 46.64% 57.13% | 355 36.15% 93.28% | 33 3.36% 96.64% | 33 3.36% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist_seqr::total 982 -system.ruby.hit_latency_hist_seqr::bucket_size 128 -system.ruby.hit_latency_hist_seqr::max_bucket 1279 -system.ruby.hit_latency_hist_seqr::samples 42 -system.ruby.hit_latency_hist_seqr::mean 524.214286 -system.ruby.hit_latency_hist_seqr::gmean 519.360085 -system.ruby.hit_latency_hist_seqr::stdev 71.299963 -system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 17 40.48% 40.48% | 24 57.14% 97.62% | 1 2.38% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist_seqr::total 42 -system.ruby.miss_latency_hist_seqr::bucket_size 128 -system.ruby.miss_latency_hist_seqr::max_bucket 1279 -system.ruby.miss_latency_hist_seqr::samples 940 -system.ruby.miss_latency_hist_seqr::mean 627.082979 -system.ruby.miss_latency_hist_seqr::gmean 616.094261 -system.ruby.miss_latency_hist_seqr::stdev 106.107284 -system.ruby.miss_latency_hist_seqr | 2 0.21% 0.21% | 7 0.74% 0.96% | 6 0.64% 1.60% | 71 7.55% 9.15% | 434 46.17% 55.32% | 354 37.66% 92.98% | 33 3.51% 96.49% | 33 3.51% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist_seqr::total 940 -system.ruby.Directory.incomplete_times_seqr 940 -system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 39431 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.cacheMemory.demand_hits 42 # Number of cache demand hits -system.ruby.l1_cntrl0.cacheMemory.demand_misses 941 # Number of cache demand misses -system.ruby.l1_cntrl0.cacheMemory.demand_accesses 983 # Number of cache demand accesses -system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 39431 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 14 # Number of times a store aliased with a pending load -system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 141 # Number of times a store aliased with a pending store -system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 15 # Number of times a load aliased with a pending store -system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 39431 # Cumulative time (in ticks) in various power states -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 39431 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.percent_links_utilized 11.905607 -system.ruby.network.routers0.msg_count.Control::2 941 -system.ruby.network.routers0.msg_count.Data::2 938 -system.ruby.network.routers0.msg_count.Response_Data::4 940 -system.ruby.network.routers0.msg_count.Writeback_Control::3 938 -system.ruby.network.routers0.msg_bytes.Control::2 7528 -system.ruby.network.routers0.msg_bytes.Data::2 67536 -system.ruby.network.routers0.msg_bytes.Response_Data::4 67680 -system.ruby.network.routers0.msg_bytes.Writeback_Control::3 7504 -system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 39431 # Cumulative time (in ticks) in various power states -system.ruby.network.routers1.percent_links_utilized 11.910045 -system.ruby.network.routers1.msg_count.Control::2 941 -system.ruby.network.routers1.msg_count.Data::2 938 -system.ruby.network.routers1.msg_count.Response_Data::4 941 -system.ruby.network.routers1.msg_count.Writeback_Control::3 938 -system.ruby.network.routers1.msg_bytes.Control::2 7528 -system.ruby.network.routers1.msg_bytes.Data::2 67536 -system.ruby.network.routers1.msg_bytes.Response_Data::4 67752 -system.ruby.network.routers1.msg_bytes.Writeback_Control::3 7504 -system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 39431 # Cumulative time (in ticks) in various power states -system.ruby.network.routers2.percent_links_utilized 11.907509 -system.ruby.network.routers2.msg_count.Control::2 941 -system.ruby.network.routers2.msg_count.Data::2 938 -system.ruby.network.routers2.msg_count.Response_Data::4 940 -system.ruby.network.routers2.msg_count.Writeback_Control::3 938 -system.ruby.network.routers2.msg_bytes.Control::2 7528 -system.ruby.network.routers2.msg_bytes.Data::2 67536 -system.ruby.network.routers2.msg_bytes.Response_Data::4 67680 -system.ruby.network.routers2.msg_bytes.Writeback_Control::3 7504 -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 39431 # Cumulative time (in ticks) in various power states -system.ruby.network.msg_count.Control 2823 -system.ruby.network.msg_count.Data 2814 -system.ruby.network.msg_count.Response_Data 2821 -system.ruby.network.msg_count.Writeback_Control 2814 -system.ruby.network.msg_byte.Control 22584 -system.ruby.network.msg_byte.Data 202608 -system.ruby.network.msg_byte.Response_Data 203112 -system.ruby.network.msg_byte.Writeback_Control 22512 -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 39431 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.throttle0.link_utilization 11.913215 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 940 -system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 938 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 67680 -system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 7504 -system.ruby.network.routers0.throttle1.link_utilization 11.897999 -system.ruby.network.routers0.throttle1.msg_count.Control::2 941 -system.ruby.network.routers0.throttle1.msg_count.Data::2 938 -system.ruby.network.routers0.throttle1.msg_bytes.Control::2 7528 -system.ruby.network.routers0.throttle1.msg_bytes.Data::2 67536 -system.ruby.network.routers1.throttle0.link_utilization 11.897999 -system.ruby.network.routers1.throttle0.msg_count.Control::2 941 -system.ruby.network.routers1.throttle0.msg_count.Data::2 938 -system.ruby.network.routers1.throttle0.msg_bytes.Control::2 7528 -system.ruby.network.routers1.throttle0.msg_bytes.Data::2 67536 -system.ruby.network.routers1.throttle1.link_utilization 11.922092 -system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 941 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 938 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 67752 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 7504 -system.ruby.network.routers2.throttle0.link_utilization 11.917020 -system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 940 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 938 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 67680 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 7504 -system.ruby.network.routers2.throttle1.link_utilization 11.897999 -system.ruby.network.routers2.throttle1.msg_count.Control::2 941 -system.ruby.network.routers2.throttle1.msg_count.Data::2 938 -system.ruby.network.routers2.throttle1.msg_bytes.Control::2 7528 -system.ruby.network.routers2.throttle1.msg_bytes.Data::2 67536 -system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::samples 940 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1 | 940 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::total 940 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::samples 938 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::mean 0.443497 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::stdev 1.567923 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2 | 868 92.54% 92.54% | 0 0.00% 92.54% | 1 0.11% 92.64% | 0 0.00% 92.64% | 0 0.00% 92.64% | 0 0.00% 92.64% | 69 7.36% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::total 938 # delay histogram for vnet_2 -system.ruby.LD.latency_hist_seqr::bucket_size 128 -system.ruby.LD.latency_hist_seqr::max_bucket 1279 -system.ruby.LD.latency_hist_seqr::samples 51 -system.ruby.LD.latency_hist_seqr::mean 632.509804 -system.ruby.LD.latency_hist_seqr::gmean 625.135320 -system.ruby.LD.latency_hist_seqr::stdev 99.959466 -system.ruby.LD.latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 6 11.76% 11.76% | 20 39.22% 50.98% | 21 41.18% 92.16% | 2 3.92% 96.08% | 2 3.92% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist_seqr::total 51 -system.ruby.LD.hit_latency_hist_seqr::bucket_size 64 -system.ruby.LD.hit_latency_hist_seqr::max_bucket 639 -system.ruby.LD.hit_latency_hist_seqr::samples 2 -system.ruby.LD.hit_latency_hist_seqr::mean 576 -system.ruby.LD.hit_latency_hist_seqr::gmean 575.579708 -system.ruby.LD.hit_latency_hist_seqr::stdev 31.112698 -system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% -system.ruby.LD.hit_latency_hist_seqr::total 2 -system.ruby.LD.miss_latency_hist_seqr::bucket_size 128 -system.ruby.LD.miss_latency_hist_seqr::max_bucket 1279 -system.ruby.LD.miss_latency_hist_seqr::samples 49 -system.ruby.LD.miss_latency_hist_seqr::mean 634.816327 -system.ruby.LD.miss_latency_hist_seqr::gmean 627.246231 -system.ruby.LD.miss_latency_hist_seqr::stdev 101.240159 -system.ruby.LD.miss_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 6 12.24% 12.24% | 18 36.73% 48.98% | 21 42.86% 91.84% | 2 4.08% 95.92% | 2 4.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist_seqr::total 49 -system.ruby.ST.latency_hist_seqr::bucket_size 128 -system.ruby.ST.latency_hist_seqr::max_bucket 1279 -system.ruby.ST.latency_hist_seqr::samples 882 -system.ruby.ST.latency_hist_seqr::mean 621.007937 -system.ruby.ST.latency_hist_seqr::gmean 609.588661 -system.ruby.ST.latency_hist_seqr::stdev 107.265659 -system.ruby.ST.latency_hist_seqr | 2 0.23% 0.23% | 7 0.79% 1.02% | 6 0.68% 1.70% | 78 8.84% 10.54% | 414 46.94% 57.48% | 318 36.05% 93.54% | 29 3.29% 96.83% | 28 3.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist_seqr::total 882 -system.ruby.ST.hit_latency_hist_seqr::bucket_size 128 -system.ruby.ST.hit_latency_hist_seqr::max_bucket 1279 -system.ruby.ST.hit_latency_hist_seqr::samples 38 -system.ruby.ST.hit_latency_hist_seqr::mean 517.263158 -system.ruby.ST.hit_latency_hist_seqr::gmean 512.460135 -system.ruby.ST.hit_latency_hist_seqr::stdev 71.032419 -system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 17 44.74% 44.74% | 20 52.63% 97.37% | 1 2.63% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist_seqr::total 38 -system.ruby.ST.miss_latency_hist_seqr::bucket_size 128 -system.ruby.ST.miss_latency_hist_seqr::max_bucket 1279 -system.ruby.ST.miss_latency_hist_seqr::samples 844 -system.ruby.ST.miss_latency_hist_seqr::mean 625.678910 -system.ruby.ST.miss_latency_hist_seqr::gmean 614.370879 -system.ruby.ST.miss_latency_hist_seqr::stdev 106.283167 -system.ruby.ST.miss_latency_hist_seqr | 2 0.24% 0.24% | 7 0.83% 1.07% | 6 0.71% 1.78% | 61 7.23% 9.00% | 394 46.68% 55.69% | 317 37.56% 93.25% | 29 3.44% 96.68% | 28 3.32% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist_seqr::total 844 -system.ruby.IFETCH.latency_hist_seqr::bucket_size 128 -system.ruby.IFETCH.latency_hist_seqr::max_bucket 1279 -system.ruby.IFETCH.latency_hist_seqr::samples 49 -system.ruby.IFETCH.latency_hist_seqr::mean 642.612245 -system.ruby.IFETCH.latency_hist_seqr::gmean 634.549482 -system.ruby.IFETCH.latency_hist_seqr::stdev 106.327289 -system.ruby.IFETCH.latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 4 8.16% 8.16% | 24 48.98% 57.14% | 16 32.65% 89.80% | 2 4.08% 93.88% | 3 6.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist_seqr::total 49 -system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 64 -system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.hit_latency_hist_seqr::samples 2 -system.ruby.IFETCH.hit_latency_hist_seqr::mean 604.500000 -system.ruby.IFETCH.hit_latency_hist_seqr::gmean 604.216848 -system.ruby.IFETCH.hit_latency_hist_seqr::stdev 26.162951 -system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 100.00% 100.00% -system.ruby.IFETCH.hit_latency_hist_seqr::total 2 -system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 128 -system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 1279 -system.ruby.IFETCH.miss_latency_hist_seqr::samples 47 -system.ruby.IFETCH.miss_latency_hist_seqr::mean 644.234043 -system.ruby.IFETCH.miss_latency_hist_seqr::gmean 635.873481 -system.ruby.IFETCH.miss_latency_hist_seqr::stdev 108.241922 -system.ruby.IFETCH.miss_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 4 8.51% 8.51% | 22 46.81% 55.32% | 16 34.04% 89.36% | 2 4.26% 93.62% | 3 6.38% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.miss_latency_hist_seqr::total 47 -system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 128 -system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 1279 -system.ruby.Directory.miss_mach_latency_hist_seqr::samples 940 -system.ruby.Directory.miss_mach_latency_hist_seqr::mean 627.082979 -system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 616.094261 -system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 106.107284 -system.ruby.Directory.miss_mach_latency_hist_seqr | 2 0.21% 0.21% | 7 0.74% 0.96% | 6 0.64% 1.60% | 71 7.55% 9.15% | 434 46.17% 55.32% | 354 37.66% 92.98% | 33 3.51% 96.49% | 33 3.51% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Directory.miss_mach_latency_hist_seqr::total 940 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 128 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 1279 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 49 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 634.816327 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 627.246231 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 101.240159 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 6 12.24% 12.24% | 18 36.73% 48.98% | 21 42.86% 91.84% | 2 4.08% 95.92% | 2 4.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 49 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 128 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 1279 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 844 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 625.678910 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 614.370879 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 106.283167 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 2 0.24% 0.24% | 7 0.83% 1.07% | 6 0.71% 1.78% | 61 7.23% 9.00% | 394 46.68% 55.69% | 317 37.56% 93.25% | 29 3.44% 96.68% | 28 3.32% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 844 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 128 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 1279 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 47 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 644.234043 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 635.873481 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 108.241922 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 4 8.51% 8.51% | 22 46.81% 55.32% | 16 34.04% 89.36% | 2 4.26% 93.62% | 3 6.38% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 47 -system.ruby.Directory_Controller.GETX 941 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 938 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 941 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 938 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 941 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 938 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 941 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 938 0.00% 0.00% -system.ruby.L1Cache_Controller.Load 51 0.00% 0.00% -system.ruby.L1Cache_Controller.Ifetch 49 0.00% 0.00% -system.ruby.L1Cache_Controller.Store 883 0.00% 0.00% -system.ruby.L1Cache_Controller.Data 940 0.00% 0.00% -system.ruby.L1Cache_Controller.Replacement 938 0.00% 0.00% -system.ruby.L1Cache_Controller.Writeback_Ack 938 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Load 49 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Ifetch 47 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Store 845 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Load 2 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Ifetch 2 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Store 38 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Replacement 938 0.00% 0.00% -system.ruby.L1Cache_Controller.MI.Writeback_Ack 938 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Data 96 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.Data 844 0.00% 0.00% - ----------- End Simulation Statistics ---------- diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,203 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=atomic -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=AtomicSimpleCPU -children=dtb interrupts isa itb tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -fastmem=false -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -simulate_data_stalls=false -simulate_inst_stalls=false -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -width=1 -workload=system.cpu.workload -dcache_port=system.membus.slave[2] -icache_port=system.membus.slave[1] - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=twolf smred -cwd=build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-atomic -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/twolf -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=Null -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.icache_port system.cpu.dcache_port - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=0:134217727 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/simerr --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/simerr Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,6 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(1, ...) diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/simout --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/simout Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,29 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-atomic/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-atomic/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 21 2016 14:09:28 -gem5 executing on e108600-lin, pid 4296 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/70.twolf/alpha/tru64/simple-atomic - -Couldn't unlink build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-atomic/smred.sav -Couldn't unlink build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-atomic/smred.sv2 -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. - -TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 -Standard Cell Placement and Global Routing Program -Authors: Carl Sechen, Bill Swartz - Yale University - 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 - 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 - 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 - 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 - 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 - 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 -106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 45951567500 because target called exit() diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.out --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.out Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,276 +0,0 @@ - -TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 -Standard Cell Placement and Global Routing Program -Authors: Carl Sechen, Bill Swartz - Yale University - - -NOTE: Restart file .rs2 not used - -TimberWolf will perform a global route step -rowSep: 1.000000 -feedThruWidth: 4 - -****************** -BLOCK DATA -block:1 desire:85 -block:2 desire:85 -Total Desired Length: 170 -total cell length: 168 -total block length: 168 -block x-span:84 block y-span:78 -implicit feed thru range: -84 -Using default value of bin.penalty.control:1.000000 -numBins automatically set to:5 -binWidth = average_cell_width + 0 sigma= 17 -average_cell_width is:16 -standard deviation of cell length is:23.6305 -TimberWolfSC starting from the beginning - - - -THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645 -The number of nets with 1 pin is 4 -The number of nets with 2 pin is 9 -The number of nets with 3 pin is 0 -The number of nets with 4 pin is 2 -The number of nets with 5 pin is 0 -The number of nets with 6 pin is 0 -The number of nets with 7 pin is 0 -The number of nets with 8 pin is 0 -The number of nets with 9 pin is 0 -The number of nets with 10 pin or more is 0 - -New Cost Function: Initial Horizontal Cost:242 -New Cost Function: FEEDS:0 MISSING_ROWS:-46 - -bdxlen:86 bdylen:78 -l:0 t:78 r:86 b:0 - - - -THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645 - - - -THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44 - -The rand generator seed was at utemp() : 1 - - - tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000 - tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000 - tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000 - tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000 - - I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs - 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40 - 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46 - 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.3 0.0 0 46 - 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48 - 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46 - 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52 - 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50 - 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48 - 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48 - 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48 - 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50 - 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44 - 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50 - 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50 - 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46 - 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52 - 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50 - 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48 - 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48 - 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52 - 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52 - 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50 - 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48 - 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42 - 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52 - 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52 - 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50 - 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48 - 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50 - 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46 - 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48 - 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48 - 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52 - 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48 - 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48 - 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50 - 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52 - 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52 - 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48 - 40 251 8 741 104 159 0.0 0.8 0.5 36.3 47.5 0.0 0 48 - 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50 - 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50 - 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48 - 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52 - 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50 - 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52 - 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52 - 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48 - 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52 - 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52 - 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52 - 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46 - 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44 - 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50 - 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52 - 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48 - 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52 - 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50 - 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50 - 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52 - 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48 - 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48 - 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52 - 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52 - 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50 - 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52 - 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52 - 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52 - 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52 - 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52 - 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52 - 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52 - 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52 - 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52 - 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52 - 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52 - 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52 - 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50 - 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52 - 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52 - 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52 - 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50 - 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50 - 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52 - 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52 - 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52 - 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52 - 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52 - 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52 - 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52 - 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52 - 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52 - 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52 - 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52 - 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52 - 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52 - 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52 - 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52 - 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52 -100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52 -101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52 -102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52 -103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52 -104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52 -105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52 -106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52 -107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52 -108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52 -109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52 -110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52 -111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52 -112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52 -113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52 -114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52 -115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52 -116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52 -117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52 -118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52 -119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52 -120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52 -121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8 - -Initial Wiring Cost: 645 Final Wiring Cost: 732 -############## Percent Wire Cost Reduction: -13 - - -Initial Wire Length: 645 Final Wire Length: 732 -************** Percent Wire Length Reduction: -13 - - -Initial Horiz. Wire: 216 Final Horiz. Wire: 147 -$$$$$$$$$$$ Percent H-Wire Length Reduction: 32 - - -Initial Vert. Wire: 429 Final Vert. Wire: 585 -@@@@@@@@@@@ Percent V-Wire Length Reduction: -36 - -Before Feeds are Added: -BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET - 1 82 -20 - 2 86 -16 - -LONGEST Block is:2 Its length is:86 -BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET - 1 86 -16 - 2 86 -16 - -LONGEST Block is:1 Its length is:86 -Added: 1 feed-through cells - -Removed the cell overlaps --- Will do neighbor interchanges only now - -TOTAL INTERCONNECT LENGTH: 994 -OVERLAP PENALTY: 0 - -initialRowControl: 1.650 -finalRowControl: 0.300 -iter T Wire accept - 122 0.001 976 16% - 123 0.001 971 0% - 124 0.001 971 0% -Total Feed-Alignment Movement (Pass 1): 0 -Total Feed-Alignment Movement (Pass 2): 0 -Total Feed-Alignment Movement (Pass 3): 0 -Total Feed-Alignment Movement (Pass 4): 0 -Total Feed-Alignment Movement (Pass 5): 0 -Total Feed-Alignment Movement (Pass 6): 0 -Total Feed-Alignment Movement (Pass 7): 0 -Total Feed-Alignment Movement (Pass 8): 0 - -The rand generator seed was at globroute() : 987654321 - - -Total Number of Net Segments: 9 -Number of Switchable Net Segments: 0 - -Number of channels: 3 - - - -THIS IS THE ORIGINAL NUMBER OF TRACKS: 5 - - -no. of accepted flips: 0 -no. of attempted flips: 0 -THIS IS THE NUMBER OF TRACKS: 5 - - - -FINAL NUMBER OF ROUTING TRACKS: 5 - -MAX OF CHANNEL: 1 is: 0 -MAX OF CHANNEL: 2 is: 4 -MAX OF CHANNEL: 3 is: 1 -FINAL TOTAL INTERCONNECT LENGTH: 978 -FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978 -MAX NUMBER OF ATTEMPTED FLIPS PER T: 55 - - -cost_scale_factor:3.90616 - -Number of Feed Thrus: 0 -Number of Implicit Feed Thrus: 0 - -Statistics: -Number of Standard Cells: 10 -Number of Pads: 0 -Number of Nets: 15 -Number of Pins: 46 -Usage statistics not available diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pin --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pin Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,17 +0,0 @@ -$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0 -$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0 -B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0 -B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0 -B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0 -B7 3 ACOUNT_1 01#Z 17 26 2 -1 0 -B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0 -B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0 -B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0 -$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0 -$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0 -$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0 -$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0 -$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0 -$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0 -$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0 -$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0 diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl1 --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl1 Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,11 +0,0 @@ -$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1 -$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1 -$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1 -ACOUNT_1 14 0 18 26 2 1 -twfeed1 18 0 22 26 0 1 -$COUNT_1/$FJK3_1 22 0 86 26 0 1 -$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2 -$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2 -$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2 -$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2 -$COUNT_1/$FJK3_2 22 52 86 78 0 2 diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl2 --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl2 Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,2 +0,0 @@ -1 0 0 86 26 0 0 -2 0 52 86 78 0 0 diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.sav --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.sav Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,18 +0,0 @@ -0.009592 -121 -0 -1 -0.000000 -0.500000 -3.906156 -1 -1 1 2 37 13 -2 2 0 34 65 -3 2 2 63 65 -4 1 0 59 13 -5 1 2 32 13 -6 2 0 23 65 -7 1 2 12 13 -8 2 0 6 65 -9 1 0 70 13 -10 2 0 70 65 diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.sv2 --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.sv2 Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,19 +0,0 @@ -0.001000 -123 -0 -2 -0.000000 -0.500000 -3.906156 -1 -1 1 2 16 13 -2 2 2 19 65 -3 2 2 14 65 -4 1 0 11 13 -5 1 2 6 13 -6 2 0 3 65 -7 1 0 2 13 -8 2 2 9 65 -9 1 0 50 13 -10 2 0 54 65 -11 1 0 84 13 diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.twf --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.twf Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,29 +0,0 @@ -net 1 -segment channel 2 - pin1 1 pin2 7 0 0 -net 2 -segment channel 3 -pin1 41 pin2 42 0 0 -segment channel 2 -pin1 12 pin2 3 0 0 -net 3 -segment channel 2 -pin1 35 pin2 36 0 0 -segment channel 2 -pin1 19 pin2 35 0 0 -net 4 -segment channel 2 - pin1 5 pin2 38 0 0 -net 5 -net 7 -segment channel 2 - pin1 14 pin2 43 0 0 -net 8 -segment channel 2 - pin1 23 pin2 17 0 0 -net 9 -net 11 -segment channel 2 - pin1 25 pin2 31 0 0 -net 14 -net 15 diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,167 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.045952 # Number of seconds simulated -sim_ticks 45951567500 # Number of ticks simulated -final_tick 45951567500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3055578 # Simulator instruction rate (inst/s) -host_op_rate 3055577 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1527789176 # Simulator tick rate (ticks/s) -host_mem_usage 246136 # Number of bytes of host memory used -host_seconds 30.08 # Real time elapsed on the host -sim_insts 91903056 # Number of instructions simulated -sim_ops 91903056 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 45951567500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 367612356 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 108337521 # Number of bytes read from this memory -system.physmem.bytes_read::total 475949877 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 367612356 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 367612356 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 30920974 # Number of bytes written to this memory -system.physmem.bytes_written::total 30920974 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 91903089 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 19996198 # Number of read requests responded to by this memory -system.physmem.num_reads::total 111899287 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 6501103 # Number of write requests responded to by this memory -system.physmem.num_writes::total 6501103 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7999995996 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2357645819 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10357641815 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7999995996 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7999995996 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 672903574 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 672903574 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7999995996 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3030549393 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 11030545389 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 45951567500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 19996198 # DTB read hits -system.cpu.dtb.read_misses 10 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 19996208 # DTB read accesses -system.cpu.dtb.write_hits 6501103 # DTB write hits -system.cpu.dtb.write_misses 23 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 6501126 # DTB write accesses -system.cpu.dtb.data_hits 26497301 # DTB hits -system.cpu.dtb.data_misses 33 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 26497334 # DTB accesses -system.cpu.itb.fetch_hits 91903089 # ITB hits -system.cpu.itb.fetch_misses 47 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 91903136 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 45951567500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 91903136 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 91903056 # Number of instructions committed -system.cpu.committedOps 91903056 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 79581109 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 6862064 # Number of float alu accesses -system.cpu.num_func_calls 2059216 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7465012 # number of instructions that are conditional controls -system.cpu.num_int_insts 79581109 # number of integer instructions -system.cpu.num_fp_insts 6862064 # number of float instructions -system.cpu.num_int_register_reads 115028592 # number of times the integer registers were read -system.cpu.num_int_register_writes 62575473 # number of times the integer registers were written -system.cpu.num_fp_register_reads 6071661 # number of times the floating registers were read -system.cpu.num_fp_register_writes 5851888 # number of times the floating registers were written -system.cpu.num_mem_refs 26497334 # number of memory refs -system.cpu.num_load_insts 19996208 # Number of load instructions -system.cpu.num_store_insts 6501126 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 91903136 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 10240685 # Number of branches fetched -system.cpu.op_class::No_OpClass 7723353 8.40% 8.40% # Class of executed instruction -system.cpu.op_class::IntAlu 51001454 55.49% 63.90% # Class of executed instruction -system.cpu.op_class::IntMult 458252 0.50% 64.40% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 64.40% # Class of executed instruction -system.cpu.op_class::FloatAdd 2732553 2.97% 67.37% # Class of executed instruction -system.cpu.op_class::FloatCmp 104605 0.11% 67.48% # Class of executed instruction -system.cpu.op_class::FloatCvt 2333953 2.54% 70.02% # Class of executed instruction -system.cpu.op_class::FloatMult 296445 0.32% 70.35% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::FloatDiv 754822 0.82% 71.17% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::FloatSqrt 318 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::MemRead 19433628 21.15% 92.31% # Class of executed instruction -system.cpu.op_class::MemWrite 6424338 6.99% 99.30% # Class of executed instruction -system.cpu.op_class::FloatMemRead 562580 0.61% 99.92% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 76788 0.08% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 91903089 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 45951567500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 111899287 # Transaction distribution -system.membus.trans_dist::ReadResp 111899287 # Transaction distribution -system.membus.trans_dist::WriteReq 6501103 # Transaction distribution -system.membus.trans_dist::WriteResp 6501103 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 183806178 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 52994602 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 236800780 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 367612356 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 139258495 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 506870851 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 118400390 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 118400390 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 118400390 # Request fanout histogram - ----------- End Simulation Statistics ---------- diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,366 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=twolf smred -cwd=build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-timing -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/twolf -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=Null -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=0:134217727 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/simerr --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/simerr Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,6 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(1, ...) diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/simout --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/simout Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,29 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 21 2016 14:09:28 -gem5 executing on e108600-lin, pid 4297 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/70.twolf/alpha/tru64/simple-timing - -Couldn't unlink build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-timing/smred.sav -Couldn't unlink build/ALPHA/tests/opt/quick/se/70.twolf/alpha/tru64/simple-timing/smred.sv2 -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. - -TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 -Standard Cell Placement and Global Routing Program -Authors: Carl Sechen, Bill Swartz - Yale University - 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 - 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 - 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 - 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 - 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 - 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 -106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 118762761500 because target called exit() diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.out --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.out Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,276 +0,0 @@ - -TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 -Standard Cell Placement and Global Routing Program -Authors: Carl Sechen, Bill Swartz - Yale University - - -NOTE: Restart file .rs2 not used - -TimberWolf will perform a global route step -rowSep: 1.000000 -feedThruWidth: 4 - -****************** -BLOCK DATA -block:1 desire:85 -block:2 desire:85 -Total Desired Length: 170 -total cell length: 168 -total block length: 168 -block x-span:84 block y-span:78 -implicit feed thru range: -84 -Using default value of bin.penalty.control:1.000000 -numBins automatically set to:5 -binWidth = average_cell_width + 0 sigma= 17 -average_cell_width is:16 -standard deviation of cell length is:23.6305 -TimberWolfSC starting from the beginning - - - -THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645 -The number of nets with 1 pin is 4 -The number of nets with 2 pin is 9 -The number of nets with 3 pin is 0 -The number of nets with 4 pin is 2 -The number of nets with 5 pin is 0 -The number of nets with 6 pin is 0 -The number of nets with 7 pin is 0 -The number of nets with 8 pin is 0 -The number of nets with 9 pin is 0 -The number of nets with 10 pin or more is 0 - -New Cost Function: Initial Horizontal Cost:242 -New Cost Function: FEEDS:0 MISSING_ROWS:-46 - -bdxlen:86 bdylen:78 -l:0 t:78 r:86 b:0 - - - -THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645 - - - -THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44 - -The rand generator seed was at utemp() : 1 - - - tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000 - tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000 - tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000 - tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000 - - I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs - 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40 - 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46 - 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.3 0.0 0 46 - 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48 - 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46 - 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52 - 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50 - 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48 - 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48 - 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48 - 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50 - 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44 - 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50 - 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50 - 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46 - 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52 - 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50 - 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48 - 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48 - 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52 - 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52 - 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50 - 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48 - 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42 - 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52 - 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52 - 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50 - 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48 - 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50 - 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46 - 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48 - 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48 - 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52 - 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48 - 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48 - 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50 - 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52 - 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52 - 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48 - 40 251 8 741 104 159 0.0 0.8 0.5 36.3 47.5 0.0 0 48 - 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50 - 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50 - 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48 - 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52 - 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50 - 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52 - 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52 - 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48 - 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52 - 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52 - 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52 - 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46 - 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44 - 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50 - 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52 - 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48 - 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52 - 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50 - 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50 - 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52 - 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48 - 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48 - 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52 - 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52 - 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50 - 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52 - 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52 - 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52 - 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52 - 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52 - 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52 - 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52 - 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52 - 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52 - 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52 - 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52 - 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52 - 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50 - 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52 - 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52 - 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52 - 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50 - 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50 - 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52 - 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52 - 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52 - 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52 - 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52 - 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52 - 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52 - 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52 - 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52 - 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52 - 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52 - 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52 - 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52 - 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52 - 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52 - 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52 -100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52 -101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52 -102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52 -103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52 -104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52 -105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52 -106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52 -107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52 -108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52 -109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52 -110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52 -111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52 -112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52 -113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52 -114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52 -115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52 -116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52 -117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52 -118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52 -119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52 -120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52 -121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8 - -Initial Wiring Cost: 645 Final Wiring Cost: 732 -############## Percent Wire Cost Reduction: -13 - - -Initial Wire Length: 645 Final Wire Length: 732 -************** Percent Wire Length Reduction: -13 - - -Initial Horiz. Wire: 216 Final Horiz. Wire: 147 -$$$$$$$$$$$ Percent H-Wire Length Reduction: 32 - - -Initial Vert. Wire: 429 Final Vert. Wire: 585 -@@@@@@@@@@@ Percent V-Wire Length Reduction: -36 - -Before Feeds are Added: -BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET - 1 82 -20 - 2 86 -16 - -LONGEST Block is:2 Its length is:86 -BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET - 1 86 -16 - 2 86 -16 - -LONGEST Block is:1 Its length is:86 -Added: 1 feed-through cells - -Removed the cell overlaps --- Will do neighbor interchanges only now - -TOTAL INTERCONNECT LENGTH: 994 -OVERLAP PENALTY: 0 - -initialRowControl: 1.650 -finalRowControl: 0.300 -iter T Wire accept - 122 0.001 976 16% - 123 0.001 971 0% - 124 0.001 971 0% -Total Feed-Alignment Movement (Pass 1): 0 -Total Feed-Alignment Movement (Pass 2): 0 -Total Feed-Alignment Movement (Pass 3): 0 -Total Feed-Alignment Movement (Pass 4): 0 -Total Feed-Alignment Movement (Pass 5): 0 -Total Feed-Alignment Movement (Pass 6): 0 -Total Feed-Alignment Movement (Pass 7): 0 -Total Feed-Alignment Movement (Pass 8): 0 - -The rand generator seed was at globroute() : 987654321 - - -Total Number of Net Segments: 9 -Number of Switchable Net Segments: 0 - -Number of channels: 3 - - - -THIS IS THE ORIGINAL NUMBER OF TRACKS: 5 - - -no. of accepted flips: 0 -no. of attempted flips: 0 -THIS IS THE NUMBER OF TRACKS: 5 - - - -FINAL NUMBER OF ROUTING TRACKS: 5 - -MAX OF CHANNEL: 1 is: 0 -MAX OF CHANNEL: 2 is: 4 -MAX OF CHANNEL: 3 is: 1 -FINAL TOTAL INTERCONNECT LENGTH: 978 -FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978 -MAX NUMBER OF ATTEMPTED FLIPS PER T: 55 - - -cost_scale_factor:3.90616 - -Number of Feed Thrus: 0 -Number of Implicit Feed Thrus: 0 - -Statistics: -Number of Standard Cells: 10 -Number of Pads: 0 -Number of Nets: 15 -Number of Pins: 46 -Usage statistics not available diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pin --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pin Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,17 +0,0 @@ -$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0 -$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0 -B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0 -B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0 -B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0 -B7 3 ACOUNT_1 01#Z 17 26 2 -1 0 -B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0 -B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0 -B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0 -$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0 -$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0 -$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0 -$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0 -$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0 -$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0 -$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0 -$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0 diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pl1 --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pl1 Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,11 +0,0 @@ -$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1 -$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1 -$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1 -ACOUNT_1 14 0 18 26 2 1 -twfeed1 18 0 22 26 0 1 -$COUNT_1/$FJK3_1 22 0 86 26 0 1 -$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2 -$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2 -$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2 -$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2 -$COUNT_1/$FJK3_2 22 52 86 78 0 2 diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pl2 --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pl2 Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,2 +0,0 @@ -1 0 0 86 26 0 0 -2 0 52 86 78 0 0 diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.sav --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.sav Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,18 +0,0 @@ -0.009592 -121 -0 -1 -0.000000 -0.500000 -3.906156 -1 -1 1 2 37 13 -2 2 0 34 65 -3 2 2 63 65 -4 1 0 59 13 -5 1 2 32 13 -6 2 0 23 65 -7 1 2 12 13 -8 2 0 6 65 -9 1 0 70 13 -10 2 0 70 65 diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.sv2 --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.sv2 Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,19 +0,0 @@ -0.001000 -123 -0 -2 -0.000000 -0.500000 -3.906156 -1 -1 1 2 16 13 -2 2 2 19 65 -3 2 2 14 65 -4 1 0 11 13 -5 1 2 6 13 -6 2 0 3 65 -7 1 0 2 13 -8 2 2 9 65 -9 1 0 50 13 -10 2 0 54 65 -11 1 0 84 13 diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.twf --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/smred.twf Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,29 +0,0 @@ -net 1 -segment channel 2 - pin1 1 pin2 7 0 0 -net 2 -segment channel 3 -pin1 41 pin2 42 0 0 -segment channel 2 -pin1 12 pin2 3 0 0 -net 3 -segment channel 2 -pin1 35 pin2 36 0 0 -segment channel 2 -pin1 19 pin2 35 0 0 -net 4 -segment channel 2 - pin1 5 pin2 38 0 0 -net 5 -net 7 -segment channel 2 - pin1 14 pin2 43 0 0 -net 8 -segment channel 2 - pin1 23 pin2 17 0 0 -net 9 -net 11 -segment channel 2 - pin1 25 pin2 31 0 0 -net 14 -net 15 diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,555 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.118768 # Number of seconds simulated -sim_ticks 118767526500 # Number of ticks simulated -final_tick 118767526500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2099166 # Simulator instruction rate (inst/s) -host_op_rate 2099165 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2712778064 # Simulator tick rate (ticks/s) -host_mem_usage 256380 # Number of bytes of host memory used -host_seconds 43.78 # Real time elapsed on the host -sim_insts 91903056 # Number of instructions simulated -sim_ops 91903056 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 118767526500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 167744 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 137216 # Number of bytes read from this memory -system.physmem.bytes_read::total 304960 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 167744 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 167744 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2621 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory -system.physmem.num_reads::total 4765 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1412373 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1155333 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2567705 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1412373 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1412373 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1412373 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1155333 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2567705 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 118767526500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 19996198 # DTB read hits -system.cpu.dtb.read_misses 10 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 19996208 # DTB read accesses -system.cpu.dtb.write_hits 6501103 # DTB write hits -system.cpu.dtb.write_misses 23 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 6501126 # DTB write accesses -system.cpu.dtb.data_hits 26497301 # DTB hits -system.cpu.dtb.data_misses 33 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 26497334 # DTB accesses -system.cpu.itb.fetch_hits 91903090 # ITB hits -system.cpu.itb.fetch_misses 47 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 91903137 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 118767526500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 237535053 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 91903056 # Number of instructions committed -system.cpu.committedOps 91903056 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 79581109 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 6862064 # Number of float alu accesses -system.cpu.num_func_calls 2059216 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7465012 # number of instructions that are conditional controls -system.cpu.num_int_insts 79581109 # number of integer instructions -system.cpu.num_fp_insts 6862064 # number of float instructions -system.cpu.num_int_register_reads 115028592 # number of times the integer registers were read -system.cpu.num_int_register_writes 62575473 # number of times the integer registers were written -system.cpu.num_fp_register_reads 6071661 # number of times the floating registers were read -system.cpu.num_fp_register_writes 5851888 # number of times the floating registers were written -system.cpu.num_mem_refs 26497334 # number of memory refs -system.cpu.num_load_insts 19996208 # Number of load instructions -system.cpu.num_store_insts 6501126 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 237535053 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 10240685 # Number of branches fetched -system.cpu.op_class::No_OpClass 7723353 8.40% 8.40% # Class of executed instruction -system.cpu.op_class::IntAlu 51001454 55.49% 63.90% # Class of executed instruction -system.cpu.op_class::IntMult 458252 0.50% 64.40% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 64.40% # Class of executed instruction -system.cpu.op_class::FloatAdd 2732553 2.97% 67.37% # Class of executed instruction -system.cpu.op_class::FloatCmp 104605 0.11% 67.48% # Class of executed instruction -system.cpu.op_class::FloatCvt 2333953 2.54% 70.02% # Class of executed instruction -system.cpu.op_class::FloatMult 296445 0.32% 70.35% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 70.35% # Class of executed instruction -system.cpu.op_class::FloatDiv 754822 0.82% 71.17% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::FloatSqrt 318 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.17% # Class of executed instruction -system.cpu.op_class::MemRead 19433628 21.15% 92.31% # Class of executed instruction -system.cpu.op_class::MemWrite 6424338 6.99% 99.30% # Class of executed instruction -system.cpu.op_class::FloatMemRead 562580 0.61% 99.92% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 76788 0.08% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 91903089 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 118767526500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.tagsinuse 1441.932454 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26495078 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11918.613585 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1441.932454 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.352034 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.352034 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 2066 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 169 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 491 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1372 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.504395 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 52996825 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 52996825 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 118767526500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 19995723 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 19995723 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6499355 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6499355 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 26495078 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26495078 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26495078 # number of overall hits -system.cpu.dcache.overall_hits::total 26495078 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 475 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 475 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1748 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1748 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2223 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2223 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2223 # number of overall misses -system.cpu.dcache.overall_misses::total 2223 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 27278500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 27278500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 108825000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 108825000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 136103500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 136103500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 136103500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 136103500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 26497301 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 26497301 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 26497301 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000269 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000269 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000084 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000084 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000084 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000084 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 57428.421053 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 57428.421053 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62256.864989 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62256.864989 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61225.146199 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61225.146199 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61225.146199 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61225.146199 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 107 # number of writebacks -system.cpu.dcache.writebacks::total 107 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1748 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2223 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26803500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 26803500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 107077000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 107077000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 133880500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 133880500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 133880500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 133880500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000269 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # 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241766000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 241766000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 241766000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 241766000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 241766000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 91903090 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 91903090 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 91903090 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 91903090 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 91903090 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 91903090 # number of overall (read+write) accesses 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latency -system.cpu.icache.overall_avg_miss_latency::total 28409.635723 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 6681 # number of writebacks -system.cpu.icache.writebacks::total 6681 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 8510 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 8510 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 8510 # 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27409.635723 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 27409.635723 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 118767526500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3172.251150 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 12806 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 4765 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.687513 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1704.876553 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1467.374597 # Average occupied blocks per requestor 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-system.cpu.l2cache.tags.data_accesses 145333 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 118767526500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 107 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 107 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 6681 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 6681 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 5889 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 5889 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 53 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 53 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 5889 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 79 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 5968 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 5889 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 79 # number of overall hits -system.cpu.l2cache.overall_hits::total 5968 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 1722 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 1722 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2621 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 2621 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 422 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 422 # number of ReadSharedReq misses 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miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 132375000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 108274500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 240649500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 132375000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 108274500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 240649500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985126 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985126 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.307991 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.888421 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.443958 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.443958 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.580720 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.580720 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50505.532240 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50505.532240 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50503.554502 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50503.554502 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50505.532240 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50501.166045 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50503.567681 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50505.532240 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50501.166045 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50503.567681 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 17571 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 6838 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 118767526500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 8985 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 107 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 6681 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 50 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1748 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1748 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 8510 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 475 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23701 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4603 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 28304 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 972224 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149120 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 1121344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 10733 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 10733 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 10733 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 15573500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 12765000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3334500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 4765 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 118767526500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 3043 # Transaction distribution -system.membus.trans_dist::ReadExReq 1722 # Transaction distribution -system.membus.trans_dist::ReadExResp 1722 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3043 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9530 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 9530 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 304960 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 304960 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 4765 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 4765 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 4765 # Request fanout histogram -system.membus.reqLayer0.occupancy 4782000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 23825000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff -r 9c673b990d5d -r e1835e5846b9 tests/test-progs/hello/bin/alpha/linux/hello Binary file tests/test-progs/hello/bin/alpha/linux/hello has changed diff -r 9c673b990d5d -r e1835e5846b9 tests/test-progs/hello/bin/alpha/tru64/hello Binary file tests/test-progs/hello/bin/alpha/tru64/hello has changed diff -r 9c673b990d5d -r e1835e5846b9 util/regress --- a/util/regress Mon Oct 24 21:38:48 2016 +0100 +++ b/util/regress Mon Oct 24 21:40:04 2016 +0100 @@ -40,16 +40,12 @@ add_option('-v', '--verbose', action='store_true', default=False, help='echo commands before executing') add_option('--builds', - default='ALPHA,ALPHA_MOESI_hammer,' \ - 'ALPHA_MESI_Two_Level,' \ - 'ALPHA_MOESI_CMP_directory,' \ - 'ALPHA_MOESI_CMP_token,' \ + default='ARM,'\ 'MIPS,' \ 'NULL,' \ 'POWER,' \ 'SPARC,' \ 'X86,X86_MESI_Two_Level,' \ - 'ARM,' \ 'HSAIL_X86', help="comma-separated build targets to test (default: '%default')") add_option('--modes', diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,1097 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.022820 # Number of seconds simulated -sim_ticks 22819771500 # Number of ticks simulated -final_tick 22819771500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 390933 # Simulator instruction rate (inst/s) -host_op_rate 390933 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 112084385 # Simulator tick rate (ticks/s) -host_mem_usage 265424 # Number of bytes of host memory used -host_seconds 203.59 # Real time elapsed on the host -sim_insts 79591756 # Number of instructions simulated -sim_ops 79591756 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 414016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10170944 # Number of bytes read from this memory -system.physmem.bytes_read::total 10584960 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 414016 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 414016 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7372608 # Number of bytes written to this memory -system.physmem.bytes_written::total 7372608 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 6469 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158921 # Number of read requests responded to by this memory -system.physmem.num_reads::total 165390 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115197 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115197 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 18142864 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 445707530 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 463850394 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 18142864 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 18142864 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 323079835 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 323079835 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 323079835 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 18142864 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 445707530 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 786930228 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 165390 # Number of read requests accepted -system.physmem.writeReqs 115197 # Number of write requests accepted -system.physmem.readBursts 165390 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 115197 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10584512 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue -system.physmem.bytesWritten 7370752 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10584960 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7372608 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10310 # Per bank write bursts -system.physmem.perBankRdBursts::1 10353 # Per bank write bursts -system.physmem.perBankRdBursts::2 10221 # Per bank write bursts -system.physmem.perBankRdBursts::3 10036 # Per bank write bursts -system.physmem.perBankRdBursts::4 10349 # Per bank write bursts -system.physmem.perBankRdBursts::5 10326 # Per bank write bursts -system.physmem.perBankRdBursts::6 9802 # Per bank write bursts -system.physmem.perBankRdBursts::7 10209 # Per bank write bursts -system.physmem.perBankRdBursts::8 10557 # Per bank write bursts -system.physmem.perBankRdBursts::9 10617 # Per bank write bursts -system.physmem.perBankRdBursts::10 10516 # Per bank write bursts -system.physmem.perBankRdBursts::11 10223 # Per bank write bursts -system.physmem.perBankRdBursts::12 10279 # Per bank write bursts -system.physmem.perBankRdBursts::13 10557 # Per bank write bursts -system.physmem.perBankRdBursts::14 10475 # Per bank write bursts -system.physmem.perBankRdBursts::15 10553 # Per bank write bursts -system.physmem.perBankWrBursts::0 7167 # Per bank write bursts -system.physmem.perBankWrBursts::1 7277 # Per bank write bursts -system.physmem.perBankWrBursts::2 7300 # Per bank write bursts -system.physmem.perBankWrBursts::3 7008 # Per bank write bursts -system.physmem.perBankWrBursts::4 7142 # Per bank write bursts -system.physmem.perBankWrBursts::5 7300 # Per bank write bursts -system.physmem.perBankWrBursts::6 6892 # Per bank write bursts -system.physmem.perBankWrBursts::7 7158 # Per bank write bursts -system.physmem.perBankWrBursts::8 7240 # Per bank write bursts -system.physmem.perBankWrBursts::9 7069 # Per bank write bursts -system.physmem.perBankWrBursts::10 7202 # Per bank write bursts -system.physmem.perBankWrBursts::11 7121 # Per bank write bursts -system.physmem.perBankWrBursts::12 7069 # Per bank write bursts -system.physmem.perBankWrBursts::13 7390 # Per bank write bursts -system.physmem.perBankWrBursts::14 7350 # Per bank write bursts -system.physmem.perBankWrBursts::15 7483 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 22819740500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 165390 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 115197 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 51469 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 42313 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 37455 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 34126 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 585 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 604 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2061 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4086 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7552 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9529 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 9432 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7837 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8541 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 945 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 29 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 44648 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 402.130084 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 240.586732 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 367.720381 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13091 29.32% 29.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8315 18.62% 47.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5360 12.01% 59.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2692 6.03% 65.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2549 5.71% 71.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1575 3.53% 75.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1705 3.82% 79.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1125 2.52% 81.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8236 18.45% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 44648 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7096 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.304961 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 17.955367 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 317.126574 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 7095 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7096 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7096 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.229989 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.211978 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.816035 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6480 91.32% 91.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 18 0.25% 91.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 334 4.71% 96.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 161 2.27% 98.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 74 1.04% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 24 0.34% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 2 0.03% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7096 # Writes before turning the bus around for reads -system.physmem.totQLat 7131716500 # Total ticks spent queuing -system.physmem.totMemAccLat 10232647750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 826915000 # Total ticks spent in databus transfers -system.physmem.avgQLat 43122.43 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 61872.43 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 463.83 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 323.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 463.85 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 323.08 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 6.15 # Data bus utilization in percentage -system.physmem.busUtilRead 3.62 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 2.52 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.98 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.48 # Average write queue length when enqueuing -system.physmem.readRowHits 145971 # Number of row buffer hits during reads -system.physmem.writeRowHits 89923 # Number of row buffer hits during writes -system.physmem.readRowHitRate 88.26 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.06 # Row buffer hit rate for writes -system.physmem.avgGap 81328.57 # Average gap between requests -system.physmem.pageHitRate 84.07 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 153103020 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 81361005 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 582666840 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 298813680 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1398920640.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1820142240 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 87895200 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 2523555300 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 1884269760 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 2191410645 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 11023267740 # Total energy per rank (pJ) -system.physmem_0.averagePower 483.057740 # Core power per rank (mW) -system.physmem_0.totalIdleTime 18596850000 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 135529000 # Time in different power states -system.physmem_0.memoryStateTime::REF 594334000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 8155766000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 4906976500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 3493009750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 5534156250 # Time in different power states -system.physmem_1.actEnergy 165747960 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 88078155 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 598167780 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 302363280 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1429652640.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1911531480 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 82258560 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 2724848520 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 1880202720 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 2026371015 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 11210189940 # Total energy per rank (pJ) -system.physmem_1.averagePower 491.248979 # Core power per rank (mW) -system.physmem_1.totalIdleTime 18411251500 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 119903000 # Time in different power states -system.physmem_1.memoryStateTime::REF 607208000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 7539541250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 4896374750 # Time in different power states -system.physmem_1.memoryStateTime::ACT 3681289750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 5975454750 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 16458678 # Number of BP lookups -system.cpu.branchPred.condPredicted 10655092 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 320474 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8794743 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7227596 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 82.180866 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1974394 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3324 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 39317 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 31522 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 7795 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 2656 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22495361 # DTB read hits -system.cpu.dtb.read_misses 227004 # DTB read misses -system.cpu.dtb.read_acv 16 # DTB read access violations -system.cpu.dtb.read_accesses 22722365 # DTB read accesses -system.cpu.dtb.write_hits 15803250 # DTB write hits -system.cpu.dtb.write_misses 44602 # DTB write misses -system.cpu.dtb.write_acv 6 # DTB write access violations -system.cpu.dtb.write_accesses 15847852 # DTB write accesses -system.cpu.dtb.data_hits 38298611 # DTB hits -system.cpu.dtb.data_misses 271606 # DTB misses -system.cpu.dtb.data_acv 22 # DTB access violations -system.cpu.dtb.data_accesses 38570217 # DTB accesses -system.cpu.itb.fetch_hits 13713928 # ITB hits -system.cpu.itb.fetch_misses 29641 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 13743569 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 22819771500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 45639548 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15527632 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 104958165 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16458678 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9233512 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 28526394 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 879432 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 1335 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 4713 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 342280 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 91 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13713928 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 186437 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 44842161 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.340613 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.113400 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 25352844 56.54% 56.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1513864 3.38% 59.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1375551 3.07% 62.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1499198 3.34% 66.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4186922 9.34% 75.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1824752 4.07% 79.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 669001 1.49% 81.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1050081 2.34% 83.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7369948 16.44% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 44842161 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.360623 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.299720 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 14899514 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 10738608 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18272960 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 588305 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 342774 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3699945 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 98528 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 102994976 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 312859 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 342774 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 15240271 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 5029380 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 97820 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18506228 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5625688 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102003977 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 6871 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 88609 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 422499 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 5043111 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 61324692 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 123005722 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 122686459 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 319262 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 8777811 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5683 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5735 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2339310 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23131891 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16353716 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1249387 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 502474 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 90699211 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5558 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 88573949 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 67838 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11113012 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4439512 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 975 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 44842161 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.975238 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.240795 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 18402096 41.04% 41.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 5711089 12.74% 53.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5105714 11.39% 65.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4382501 9.77% 74.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4313150 9.62% 84.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2637224 5.88% 90.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1940283 4.33% 94.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1377321 3.07% 97.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 972783 2.17% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 44842161 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 241463 9.57% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1168317 46.29% 55.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1113838 44.13% 99.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 25 0.00% 99.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 417 0.02% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49366935 55.74% 55.74% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 43991 0.05% 55.78% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 121159 0.14% 55.92% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 93 0.00% 55.92% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 120693 0.14% 56.06% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 63 0.00% 56.06% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 56.06% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 39087 0.04% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.10% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 22887385 25.84% 81.94% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 15970151 18.03% 99.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 459 0.00% 99.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 23933 0.03% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 88573949 # Type of FU issued -system.cpu.iq.rate 1.940728 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2524060 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.028497 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 223970516 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 101417859 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86818116 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 611441 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 420538 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 299902 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 90792080 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 305929 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1674439 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2855253 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5856 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 20836 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1740339 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3017 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 190756 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 342774 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1435868 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 3107979 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100192818 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 116708 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23131891 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16353716 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5558 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3773 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3106841 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 20836 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 111267 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 152585 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 263852 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 87883972 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22722991 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 689977 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9488049 # number of nop insts executed -system.cpu.iew.exec_refs 38571182 # number of memory reference insts executed -system.cpu.iew.exec_branches 15118040 # Number of branches executed -system.cpu.iew.exec_stores 15848191 # Number of stores executed -system.cpu.iew.exec_rate 1.925610 # Inst execution rate -system.cpu.iew.wb_sent 87519959 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87118018 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33843453 # num instructions producing a value -system.cpu.iew.wb_consumers 44250497 # num instructions consuming a value -system.cpu.iew.wb_rate 1.908827 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.764815 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 8632074 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 223532 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 43575084 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.027321 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.870724 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 22117259 50.76% 50.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 6277727 14.41% 65.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 2900957 6.66% 71.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 1737731 3.99% 75.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1677521 3.85% 79.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1124025 2.58% 82.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1202727 2.76% 85.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 795829 1.83% 86.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5741308 13.18% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 43575084 # Number of insts commited each cycle -system.cpu.commit.committedInsts 88340672 # Number of instructions committed -system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 34890015 # Number of memory references committed -system.cpu.commit.loads 20276638 # Number of loads committed -system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 13754477 # Number of branches committed -system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions. -system.cpu.commit.int_insts 77942044 # Number of committed integer instructions. -system.cpu.commit.function_calls 1661057 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 8748916 9.90% 9.90% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 44394798 50.25% 60.16% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 41101 0.05% 60.20% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 60.20% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 114304 0.13% 60.33% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 84 0.00% 60.33% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 113640 0.13% 60.46% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 50 0.00% 60.46% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 60.46% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 37764 0.04% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 60.51% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 20276331 22.95% 83.46% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 14611772 16.54% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemRead 307 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemWrite 1605 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 88340672 # Class of committed instruction -system.cpu.commit.bw_lim_events 5741308 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 133489180 # The number of ROB reads -system.cpu.rob.rob_writes 195215826 # The number of ROB writes -system.cpu.timesIdled 45373 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 797387 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 79591756 # Number of Instructions Simulated -system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.573421 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.573421 # CPI: Total CPI of All Threads -system.cpu.ipc 1.743921 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.743921 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 116327818 # number of integer regfile reads -system.cpu.int_regfile_writes 57658172 # number of integer regfile writes -system.cpu.fp_regfile_reads 255578 # number of floating regfile reads -system.cpu.fp_regfile_writes 240399 # number of floating regfile writes -system.cpu.misc_regfile_reads 38260 # number of misc regfile reads -system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 201413 # number of replacements -system.cpu.dcache.tags.tagsinuse 4069.948439 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 33978122 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 205509 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 165.336418 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 244590500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4069.948439 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993640 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993640 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2488 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 1533 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 70808789 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 70808789 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 20418812 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20418812 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13559258 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13559258 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 52 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 52 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 33978070 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 33978070 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 33978070 # number of overall hits -system.cpu.dcache.overall_hits::total 33978070 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 269399 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 269399 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1054119 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1054119 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1323518 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1323518 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1323518 # number of overall misses -system.cpu.dcache.overall_misses::total 1323518 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 19371317500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 19371317500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 94432641988 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 94432641988 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 113803959488 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 113803959488 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 113803959488 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 113803959488 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20688211 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20688211 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 52 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 52 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 35301588 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 35301588 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 35301588 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 35301588 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.013022 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.013022 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.072134 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.072134 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037492 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037492 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037492 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037492 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71905.677081 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 71905.677081 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 89584.422620 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 89584.422620 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 85985.955225 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 85985.955225 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 85985.955225 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 85985.955225 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 7415690 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 299 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 82797 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 89.564719 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 149.500000 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 168510 # number of writebacks -system.cpu.dcache.writebacks::total 168510 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 207284 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 207284 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 910725 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 910725 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1118009 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1118009 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1118009 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1118009 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62115 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 62115 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143394 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143394 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 205509 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 205509 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 205509 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 205509 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3617431500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3617431500 # number of ReadReq MSHR miss cycles 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-system.cpu.dcache.demand_avg_mshr_miss_latency::total 91973.656691 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 91973.656691 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 91973.656691 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 90457 # number of replacements -system.cpu.icache.tags.tagsinuse 1914.919853 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 13608920 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 92505 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 147.115507 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 19216549500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 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-system.cpu.icache.overall_misses::total 105006 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2088801499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2088801499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2088801499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2088801499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2088801499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2088801499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13713926 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13713926 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13713926 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13713926 # number of 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# average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 19892.210912 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 19892.210912 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 19892.210912 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 683 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 42.687500 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 90457 # number of writebacks -system.cpu.icache.writebacks::total 90457 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 12500 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 12500 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 12500 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 12500 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 12500 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 12500 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 92506 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 92506 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 92506 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 92506 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 92506 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 92506 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1693618500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1693618500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1693618500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1693618500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1693618500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1693618500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006745 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006745 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006745 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006745 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006745 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006745 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18308.201630 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18308.201630 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18308.201630 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18308.201630 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18308.201630 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18308.201630 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 134872 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31840.102351 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 422133 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 167640 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.518092 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 5003072000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 716.868966 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1773.767441 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 29349.465945 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.021877 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.054131 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.895675 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.971683 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 200 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2733 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 28770 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1005 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 60 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4886720 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4886720 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 168510 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 168510 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 90457 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 90457 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 12581 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 12581 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 86036 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 86036 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 34007 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 34007 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 86036 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 46588 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 132624 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 86036 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 46588 # number of overall hits -system.cpu.l2cache.overall_hits::total 132624 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 130815 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 130815 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 6470 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 6470 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 28106 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 28106 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 6470 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 158921 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 165391 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 6470 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 158921 # number of overall misses -system.cpu.l2cache.overall_misses::total 165391 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14933033000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 14933033000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 647096000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 647096000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3162742000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 3162742000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 647096000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 18095775000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 18742871000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 647096000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 18095775000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 18742871000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 168510 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 168510 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 90457 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 90457 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 143396 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 143396 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 92506 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 92506 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 62113 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 62113 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 92506 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 205509 # number of demand (read+write) accesses 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-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.069941 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.773304 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.554975 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.069941 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.773304 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.554975 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 114153.827925 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 114153.827925 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 100014.837713 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 100014.837713 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 112529.068526 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 112529.068526 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 100014.837713 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 113866.480830 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 113324.612585 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 100014.837713 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 113866.480830 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 113324.612585 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 115198 # number of writebacks -system.cpu.l2cache.writebacks::total 115198 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 111 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 111 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130815 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 130815 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 6470 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 6470 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 28106 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 28106 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 6470 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 158921 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 165391 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 6470 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 158921 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 165391 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13624883000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13624883000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 582406000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 582406000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2881682000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2881682000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 582406000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16506565000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17088971000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 582406000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16506565000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17088971000 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.912264 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912264 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.069941 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.069941 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.452498 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.452498 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.069941 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.773304 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.554975 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.069941 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773304 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.554975 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 104153.827925 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 104153.827925 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 90016.383308 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 90016.383308 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 102529.068526 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 102529.068526 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 90016.383308 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 103866.480830 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 103324.673048 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 90016.383308 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 103866.480830 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 103324.673048 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 589885 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 291870 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 4237 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4237 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 154618 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 283708 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 90457 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 52577 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143396 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143396 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 92506 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 62113 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 275468 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 612431 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 887899 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11709568 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23937216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 35646784 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 134872 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 7372672 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 432887 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.009788 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.098448 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 428650 99.02% 99.02% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4237 0.98% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 432887 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 553909500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 2.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 138764985 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 308272981 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 296135 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 130745 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 22819771500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 34575 # Transaction distribution -system.membus.trans_dist::WritebackDirty 115197 # Transaction distribution -system.membus.trans_dist::CleanEvict 15548 # Transaction distribution -system.membus.trans_dist::ReadExReq 130815 # Transaction distribution -system.membus.trans_dist::ReadExResp 130815 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 34575 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 461525 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 461525 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17957568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17957568 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 165390 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 165390 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 165390 # Request fanout histogram -system.membus.reqLayer0.occupancy 779827500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 3.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 851966000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 3.7 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/config.ini --- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/config.ini Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,877 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=MinorCPU -children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload -branchPred=system.cpu.branchPred -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -decodeCycleInput=true -decodeInputBufferSize=3 -decodeInputWidth=2 -decodeToExecuteForwardDelay=1 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -enableIdling=true -eventq_index=0 -executeAllowEarlyMemoryIssue=true -executeBranchDelay=1 -executeCommitLimit=2 -executeCycleInput=true -executeFuncUnits=system.cpu.executeFuncUnits -executeInputBufferSize=7 -executeInputWidth=2 -executeIssueLimit=2 -executeLSQMaxStoreBufferStoresPerCycle=2 -executeLSQRequestsQueueSize=1 -executeLSQStoreBufferSize=5 -executeLSQTransfersQueueSize=2 -executeMaxAccessesInMemory=2 -executeMemoryCommitLimit=1 -executeMemoryIssueLimit=1 -executeMemoryWidth=0 -executeSetTraceTimeOnCommit=true -executeSetTraceTimeOnIssue=false -fetch1FetchLimit=1 -fetch1LineSnapWidth=0 -fetch1LineWidth=0 -fetch1ToFetch2BackwardDelay=1 -fetch1ToFetch2ForwardDelay=1 -fetch2CycleInput=true -fetch2InputBufferSize=2 -fetch2ToDecodeForwardDelay=1 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -threadPolicy=RoundRobin -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.branchPred] -type=TournamentBP -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -indirectHashGHR=true -indirectHashTargets=true -indirectPathLength=3 -indirectSets=256 -indirectTagSize=16 -indirectWays=2 -instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 -useIndirect=true - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.executeFuncUnits] -type=MinorFUPool -children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 -eventq_index=0 -funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 - -[system.cpu.executeFuncUnits.funcUnits0] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits0.timings - -[system.cpu.executeFuncUnits.funcUnits0.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntAlu - -[system.cpu.executeFuncUnits.funcUnits0.timings] -type=MinorFUTiming -children=opClasses -description=Int -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits1] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits1.timings - -[system.cpu.executeFuncUnits.funcUnits1.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntAlu - -[system.cpu.executeFuncUnits.funcUnits1.timings] -type=MinorFUTiming -children=opClasses -description=Int -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits2] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits2.timings - -[system.cpu.executeFuncUnits.funcUnits2.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntMult - -[system.cpu.executeFuncUnits.funcUnits2.timings] -type=MinorFUTiming -children=opClasses -description=Mul -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses -srcRegsRelativeLats=0 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits3] -type=MinorFU -children=opClasses -cantForwardFromFUIndices= -eventq_index=0 -issueLat=9 -opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses -opLat=9 -timings= - -[system.cpu.executeFuncUnits.funcUnits3.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntDiv - -[system.cpu.executeFuncUnits.funcUnits4] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses -opLat=6 -timings=system.cpu.executeFuncUnits.funcUnits4.timings - -[system.cpu.executeFuncUnits.funcUnits4.opClasses] -type=MinorOpClassSet -children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] -type=MinorOpClass -eventq_index=0 -opClass=FloatAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01] -type=MinorOpClass -eventq_index=0 -opClass=FloatCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02] -type=MinorOpClass -eventq_index=0 -opClass=FloatCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] -type=MinorOpClass -eventq_index=0 -opClass=FloatMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] -type=MinorOpClass -eventq_index=0 -opClass=FloatDiv - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] -type=MinorOpClass -eventq_index=0 -opClass=FloatSqrt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] -type=MinorOpClass -eventq_index=0 -opClass=SimdAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] -type=MinorOpClass -eventq_index=0 -opClass=SimdAddAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] -type=MinorOpClass -eventq_index=0 -opClass=SimdAlu - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] -type=MinorOpClass -eventq_index=0 -opClass=SimdCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] -type=MinorOpClass -eventq_index=0 -opClass=SimdCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] -type=MinorOpClass -eventq_index=0 -opClass=SimdMisc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] -type=MinorOpClass -eventq_index=0 -opClass=SimdMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] -type=MinorOpClass -eventq_index=0 -opClass=SimdMultAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] -type=MinorOpClass -eventq_index=0 -opClass=SimdShift - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] -type=MinorOpClass -eventq_index=0 -opClass=SimdShiftAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] -type=MinorOpClass -eventq_index=0 -opClass=SimdSqrt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatAlu - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatDiv - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMisc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMultAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatSqrt - -[system.cpu.executeFuncUnits.funcUnits4.timings] -type=MinorFUTiming -children=opClasses -description=FloatSimd -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits5] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses -opLat=1 -timings=system.cpu.executeFuncUnits.funcUnits5.timings - -[system.cpu.executeFuncUnits.funcUnits5.opClasses] -type=MinorOpClassSet -children=opClasses0 opClasses1 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 - -[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] -type=MinorOpClass -eventq_index=0 -opClass=MemRead - -[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] -type=MinorOpClass -eventq_index=0 -opClass=MemWrite - -[system.cpu.executeFuncUnits.funcUnits5.timings] -type=MinorFUTiming -children=opClasses -description=Mem -eventq_index=0 -extraAssumedLat=2 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses -srcRegsRelativeLats=1 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits6] -type=MinorFU -children=opClasses -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses -opLat=1 -timings= - -[system.cpu.executeFuncUnits.funcUnits6.opClasses] -type=MinorOpClassSet -children=opClasses0 opClasses1 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 - -[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] -type=MinorOpClass -eventq_index=0 -opClass=IprAccess - -[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] -type=MinorOpClass -eventq_index=0 -opClass=InstPrefetch - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=bzip2 input.source 1 -cwd=build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/minor-timing -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/bzip2 -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=0:134217727:0:0:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=6000 -tXPDLL=0 -tXS=270000 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/simerr --- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/simerr Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,7 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(1, ...) diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/simout --- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/simout Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,29 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/minor-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/minor-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:19:45 -gem5 executing on e108600-lin, pid 28067 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/60.bzip2/alpha/tru64/minor-timing - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -info: Increasing stack size by one page. -spec_init -Loading Input Data -Input data 1048576 bytes in length -Compressing Input Data, level 7 -Compressed data 198546 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 198677 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! -Exiting @ tick 1241902335500 because target called exit() diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt --- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,836 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 1.241902 # Number of seconds simulated -sim_ticks 1241902335500 # Number of ticks simulated -final_tick 1241902335500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 473348 # Simulator instruction rate (inst/s) -host_op_rate 473348 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 321867657 # Simulator tick rate (ticks/s) -host_mem_usage 255296 # Number of bytes of host memory used -host_seconds 3858.43 # Real time elapsed on the host -sim_insts 1826378509 # Number of instructions simulated -sim_ops 1826378509 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1241902335500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 61632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 126178240 # Number of bytes read from this memory -system.physmem.bytes_read::total 126239872 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61632 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61632 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 66092288 # Number of bytes written to this memory -system.physmem.bytes_written::total 66092288 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 963 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1971535 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1972498 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1032692 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1032692 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 49627 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 101600775 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 101650402 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 49627 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 49627 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 53218587 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 53218587 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 53218587 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 49627 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 101600775 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 154868990 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1972498 # Number of read requests accepted -system.physmem.writeReqs 1032692 # Number of write requests accepted -system.physmem.readBursts 1972498 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1032692 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 126161536 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 78336 # Total number of bytes read from write queue -system.physmem.bytesWritten 66090880 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 126239872 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 66092288 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1224 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 119357 # Per bank write bursts -system.physmem.perBankRdBursts::1 114729 # Per bank write bursts -system.physmem.perBankRdBursts::2 116715 # Per bank write bursts -system.physmem.perBankRdBursts::3 118322 # Per bank write bursts -system.physmem.perBankRdBursts::4 118352 # Per bank write bursts -system.physmem.perBankRdBursts::5 118237 # Per bank write bursts -system.physmem.perBankRdBursts::6 120696 # Per bank write bursts -system.physmem.perBankRdBursts::7 125562 # Per bank write bursts -system.physmem.perBankRdBursts::8 127868 # Per bank write bursts -system.physmem.perBankRdBursts::9 130858 # Per bank write bursts -system.physmem.perBankRdBursts::10 129451 # Per bank write bursts -system.physmem.perBankRdBursts::11 131187 # Per bank write bursts -system.physmem.perBankRdBursts::12 126743 # Per bank write bursts -system.physmem.perBankRdBursts::13 125956 # Per bank write bursts -system.physmem.perBankRdBursts::14 123338 # Per bank write bursts -system.physmem.perBankRdBursts::15 123903 # Per bank write bursts -system.physmem.perBankWrBursts::0 62004 # Per bank write bursts -system.physmem.perBankWrBursts::1 62324 # Per bank write bursts -system.physmem.perBankWrBursts::2 61320 # Per bank write bursts -system.physmem.perBankWrBursts::3 62012 # Per bank write bursts -system.physmem.perBankWrBursts::4 62437 # Per bank write bursts -system.physmem.perBankWrBursts::5 63989 # Per bank write bursts -system.physmem.perBankWrBursts::6 65066 # Per bank write bursts -system.physmem.perBankWrBursts::7 66492 # Per bank write bursts -system.physmem.perBankWrBursts::8 66230 # Per bank write bursts -system.physmem.perBankWrBursts::9 66701 # Per bank write bursts -system.physmem.perBankWrBursts::10 66337 # Per bank write bursts -system.physmem.perBankWrBursts::11 66707 # Per bank write bursts -system.physmem.perBankWrBursts::12 65162 # Per bank write bursts -system.physmem.perBankWrBursts::13 65226 # Per bank write bursts -system.physmem.perBankWrBursts::14 65630 # Per bank write bursts -system.physmem.perBankWrBursts::15 65033 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1241902212500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1972498 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1032692 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1834002 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 137262 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 28680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 29758 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 55879 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 61072 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 61319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 61406 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 61263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 61215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 61129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 61163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 61122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 61175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 61200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 61213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 61359 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 61719 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 61033 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 60943 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1848577 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.999494 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.158472 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 130.975371 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1464855 79.24% 79.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 267102 14.45% 93.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 48426 2.62% 96.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20608 1.11% 97.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 12613 0.68% 98.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7404 0.40% 98.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5582 0.30% 98.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4649 0.25% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 17338 0.94% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1848577 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 60747 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 32.448697 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 23.033030 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 139.766082 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 60580 99.73% 99.73% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 126 0.21% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1535 11 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-2047 5 0.01% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-2559 4 0.01% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2560-3071 4 0.01% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-3583 2 0.00% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3584-4095 3 0.00% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-4607 3 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4608-5119 3 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::6656-7167 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8704-9215 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::9216-9727 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::11776-12287 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12800-13311 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14848-15359 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 60747 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 60747 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.999523 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.968024 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.037878 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 30790 50.69% 50.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1097 1.81% 52.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 26995 44.44% 96.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1834 3.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 26 0.04% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 5 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 60747 # Writes before turning the bus around for reads -system.physmem.totQLat 58523135000 # Total ticks spent queuing -system.physmem.totMemAccLat 95484522500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9856370000 # Total ticks spent in databus transfers -system.physmem.avgQLat 29687.98 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 48437.98 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 101.59 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 53.22 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 101.65 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 53.22 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.21 # Data bus utilization in percentage -system.physmem.busUtilRead 0.79 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.42 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.33 # Average write queue length when enqueuing -system.physmem.readRowHits 727297 # Number of row buffer hits during reads -system.physmem.writeRowHits 428065 # Number of row buffer hits during writes -system.physmem.readRowHitRate 36.89 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 41.45 # Row buffer hit rate for writes -system.physmem.avgGap 413252.48 # Average gap between requests -system.physmem.pageHitRate 38.46 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6395269440 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3399162525 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 6797065800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 2639461680 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 75004519200.000015 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 46893448560 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2685169920 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 246120093660 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 85384513440 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 94763106600 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 570117979365 # Total energy per rank (pJ) -system.physmem_0.averagePower 459.068285 # Core power per rank (mW) -system.physmem_0.totalIdleTime 1131989083250 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 3611832250 # Time in different power states -system.physmem_0.memoryStateTime::REF 31797904000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 369900280750 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 222356311250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 74502708250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 539733299000 # Time in different power states -system.physmem_1.actEnergy 6803606040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3616187190 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 7277830560 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 2751075720 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 76383156720.000015 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 47598512910 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2658705600 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 254833635780 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 85755552000 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 89279622225 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 576994094775 # Total energy per rank (pJ) -system.physmem_1.averagePower 464.605041 # Core power per rank (mW) -system.physmem_1.totalIdleTime 1130512338500 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 3468880500 # Time in different power states -system.physmem_1.memoryStateTime::REF 32377406000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 348347909000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 223320346000 # Time in different power states -system.physmem_1.memoryStateTime::ACT 75543655250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 558844138750 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1241902335500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 246965199 # Number of BP lookups -system.cpu.branchPred.condPredicted 186917374 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15586746 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 168139701 # Number of BTB lookups -system.cpu.branchPred.BTBHits 165606683 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.493504 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18556232 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 106082 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 314 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 63 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 251 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 101 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 453404968 # DTB read hits -system.cpu.dtb.read_misses 5001226 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 458406194 # DTB read accesses -system.cpu.dtb.write_hits 161377184 # DTB write hits -system.cpu.dtb.write_misses 1709229 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 163086413 # DTB write accesses -system.cpu.dtb.data_hits 614782152 # DTB hits -system.cpu.dtb.data_misses 6710455 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 621492607 # DTB accesses -system.cpu.itb.fetch_hits 600133421 # ITB hits -system.cpu.itb.fetch_misses 19 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 600133440 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 1241902335500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 2483804671 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 1826378509 # Number of instructions committed -system.cpu.committedOps 1826378509 # Number of ops (including micro ops) committed -system.cpu.discardedOps 55133015 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.359962 # CPI: cycles per instruction -system.cpu.ipc 0.735315 # IPC: instructions per cycle -system.cpu.op_class_0::No_OpClass 83736345 4.58% 4.58% # Class of committed instruction -system.cpu.op_class_0::IntAlu 1129914150 61.87% 66.45% # Class of committed instruction -system.cpu.op_class_0::IntMult 75 0.00% 66.45% # Class of committed instruction -system.cpu.op_class_0::IntDiv 0 0.00% 66.45% # Class of committed instruction -system.cpu.op_class_0::FloatAdd 805244 0.04% 66.50% # Class of committed instruction -system.cpu.op_class_0::FloatCmp 13 0.00% 66.50% # Class of committed instruction -system.cpu.op_class_0::FloatCvt 100 0.00% 66.50% # Class of committed instruction -system.cpu.op_class_0::FloatMult 11 0.00% 66.50% # Class of committed instruction -system.cpu.op_class_0::FloatMultAcc 0 0.00% 66.50% # Class of committed instruction -system.cpu.op_class_0::FloatDiv 24 0.00% 66.50% # Class of committed instruction -system.cpu.op_class_0::FloatMisc 0 0.00% 66.50% # Class of committed instruction -system.cpu.op_class_0::FloatSqrt 0 0.00% 66.50% # Class of committed instruction -system.cpu.op_class_0::SimdAdd 0 0.00% 66.50% # Class of committed instruction -system.cpu.op_class_0::SimdAddAcc 0 0.00% 66.50% # Class of committed instruction -system.cpu.op_class_0::SimdAlu 0 0.00% 66.50% # Class of committed instruction -system.cpu.op_class_0::SimdCmp 0 0.00% 66.50% # Class of committed instruction -system.cpu.op_class_0::SimdCvt 0 0.00% 66.50% # Class of committed instruction -system.cpu.op_class_0::SimdMisc 0 0.00% 66.50% # Class of committed instruction -system.cpu.op_class_0::SimdMult 0 0.00% 66.50% # Class of committed instruction -system.cpu.op_class_0::SimdMultAcc 0 0.00% 66.50% # Class of committed instruction -system.cpu.op_class_0::SimdShift 0 0.00% 66.50% # Class of committed instruction -system.cpu.op_class_0::SimdShiftAcc 0 0.00% 66.50% # Class of committed instruction -system.cpu.op_class_0::SimdSqrt 0 0.00% 66.50% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAdd 0 0.00% 66.50% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAlu 0 0.00% 66.50% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCmp 0 0.00% 66.50% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCvt 0 0.00% 66.50% # Class of committed instruction -system.cpu.op_class_0::SimdFloatDiv 0 0.00% 66.50% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMisc 0 0.00% 66.50% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMult 0 0.00% 66.50% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 66.50% # Class of committed instruction -system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 66.50% # Class of committed instruction -system.cpu.op_class_0::MemRead 449492662 24.61% 91.11% # Class of committed instruction -system.cpu.op_class_0::MemWrite 162429751 8.89% 100.00% # Class of committed instruction -system.cpu.op_class_0::FloatMemRead 79 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::FloatMemWrite 55 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 1826378509 # Class of committed instruction -system.cpu.tickCycles 2082494897 # Number of cycles that the object actually ticked -system.cpu.idleCycles 401309774 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1241902335500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 9121955 # number of replacements -system.cpu.dcache.tags.tagsinuse 4080.932596 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 602775567 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9126051 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 66.049989 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 17009517500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4080.932596 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.996321 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.996321 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1466 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2515 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 72 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1233653477 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1233653477 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1241902335500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 444296125 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 444296125 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 158479442 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 158479442 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 602775567 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 602775567 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 602775567 # number of overall hits -system.cpu.dcache.overall_hits::total 602775567 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7239086 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7239086 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2249060 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2249060 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 9488146 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9488146 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9488146 # number of overall misses -system.cpu.dcache.overall_misses::total 9488146 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 201399177000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 201399177000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 119572112000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 119572112000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 320971289000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 320971289000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 320971289000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 320971289000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 451535211 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 451535211 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 612263713 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 612263713 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 612263713 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 612263713 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016032 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.016032 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013993 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.013993 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.015497 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.015497 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.015497 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.015497 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27821.078103 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 27821.078103 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53165.372200 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 53165.372200 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 33828.662523 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 33828.662523 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 33828.662523 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 33828.662523 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 3671979 # number of writebacks -system.cpu.dcache.writebacks::total 3671979 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 365 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 365 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 361730 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 361730 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 362095 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 362095 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 362095 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 362095 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7238721 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7238721 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1887330 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1887330 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9126051 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9126051 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9126051 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9126051 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 194152625000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 194152625000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 91149337000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 91149337000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 285301962000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 285301962000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 285301962000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 285301962000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016031 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016031 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011742 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011742 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014905 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014905 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014905 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.014905 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 26821.399112 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26821.399112 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48295.389254 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48295.389254 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31262.367699 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 31262.367699 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31262.367699 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 31262.367699 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1241902335500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 3 # number of replacements -system.cpu.icache.tags.tagsinuse 754.212981 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 600132458 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 963 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 623190.506750 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 754.212981 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.368268 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.368268 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 960 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 879 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.468750 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1200267805 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1200267805 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1241902335500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 600132458 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 600132458 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 600132458 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 600132458 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 600132458 # number of overall hits -system.cpu.icache.overall_hits::total 600132458 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 963 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 963 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 963 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 963 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 963 # number of overall misses -system.cpu.icache.overall_misses::total 963 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 93461000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 93461000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 93461000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 93461000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 93461000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 93461000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 600133421 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 600133421 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 600133421 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 600133421 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 600133421 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 600133421 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 97051.921080 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 97051.921080 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 97051.921080 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 97051.921080 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 97051.921080 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 97051.921080 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 3 # number of writebacks -system.cpu.icache.writebacks::total 3 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 963 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 963 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 963 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 963 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 963 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 963 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 92498000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 92498000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 92498000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 92498000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 92498000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 92498000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 96051.921080 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 96051.921080 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 96051.921080 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 96051.921080 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 96051.921080 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 96051.921080 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1241902335500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 1940051 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31462.306469 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 16275911 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1972819 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 8.250078 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 89697966000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 7.975185 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 42.025867 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31412.305417 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000243 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001283 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.958627 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.960153 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 928 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2816 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7096 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 21807 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 147964595 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 147964595 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1241902335500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 3671979 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 3671979 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 3 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 3 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1095271 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1095271 # number of ReadExReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6059245 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 6059245 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.data 7154516 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7154516 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 7154516 # number of overall hits -system.cpu.l2cache.overall_hits::total 7154516 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 792059 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 792059 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 963 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 963 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1179476 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 1179476 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 963 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1971535 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1972498 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 963 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1971535 # number of overall misses -system.cpu.l2cache.overall_misses::total 1972498 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 76750433500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 76750433500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 91051000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 91051000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 119656496500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 119656496500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 91051000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 196406930000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 196497981000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 91051000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 196406930000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 196497981000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 3671979 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 3671979 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 3 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 3 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1887330 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1887330 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 963 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 963 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7238721 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 7238721 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 963 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9126051 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9127014 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 963 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9126051 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9127014 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.419672 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.419672 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.162940 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.162940 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.216034 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.216116 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.216034 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.216116 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96899.894452 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 96899.894452 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 94549.325026 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 94549.325026 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 101448.860765 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 101448.860765 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 94549.325026 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 99621.325515 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 99618.849297 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 94549.325026 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 99621.325515 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 99618.849297 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 1032692 # number of writebacks -system.cpu.l2cache.writebacks::total 1032692 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 242 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 242 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 792059 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 792059 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 963 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 963 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1179476 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1179476 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 963 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1971535 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1972498 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 963 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1971535 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1972498 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 68829843500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 68829843500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 81421000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 81421000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 107861736500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 107861736500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 81421000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 176691580000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 176773001000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 81421000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 176691580000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 176773001000 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.419672 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.419672 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.162940 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.162940 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216034 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.216116 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216034 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.216116 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86899.894452 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86899.894452 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 84549.325026 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 84549.325026 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 91448.860765 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 91448.860765 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 84549.325026 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 89621.325515 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 89618.849297 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 84549.325026 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 89621.325515 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 89618.849297 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 18248972 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 9121958 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1442 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1442 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1241902335500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 7239684 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 4704671 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 3 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6357335 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1887330 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1887330 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 963 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7238721 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1929 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27374057 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27375986 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61824 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 819073920 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 819135744 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1940051 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 66092288 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 11067065 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000130 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.011414 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 11065623 99.99% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1442 0.01% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 11067065 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12796468000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1444500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13689076500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 3911349 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 1938851 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1241902335500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1180439 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1032692 # Transaction distribution -system.membus.trans_dist::CleanEvict 906159 # Transaction distribution -system.membus.trans_dist::ReadExReq 792059 # Transaction distribution -system.membus.trans_dist::ReadExResp 792059 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1180439 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5883847 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5883847 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 192332160 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 192332160 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 1972498 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1972498 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 1972498 # Request fanout histogram -system.membus.reqLayer0.occupancy 8507556000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 10783034500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.9 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,825 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=DerivO3CPU -children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload -LFSTSize=1024 -LQEntries=32 -LSQCheckLoads=true -LSQDepCheckShift=4 -SQEntries=32 -SSITSize=1024 -activity=0 -backComSize=5 -branchPred=system.cpu.branchPred -cachePorts=200 -checker=Null -clk_domain=system.cpu_clk_domain -commitToDecodeDelay=1 -commitToFetchDelay=1 -commitToIEWDelay=1 -commitToRenameDelay=1 -commitWidth=8 -cpu_id=0 -decodeToFetchDelay=1 -decodeToRenameDelay=1 -decodeWidth=8 -default_p_state=UNDEFINED -dispatchWidth=8 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -fetchBufferSize=64 -fetchQueueSize=32 -fetchToDecodeDelay=1 -fetchTrapLatency=1 -fetchWidth=8 -forwardComSize=5 -fuPool=system.cpu.fuPool -function_trace=false -function_trace_start=0 -iewToCommitDelay=1 -iewToDecodeDelay=1 -iewToFetchDelay=1 -iewToRenameDelay=1 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -issueToExecuteDelay=1 -issueWidth=8 -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -needsTSO=false -numIQEntries=64 -numPhysCCRegs=0 -numPhysFloatRegs=256 -numPhysIntRegs=256 -numROBEntries=192 -numRobs=1 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -renameToDecodeDelay=1 -renameToFetchDelay=1 -renameToIEWDelay=2 -renameToROBDelay=1 -renameWidth=8 -simpoint_start_insts= -smtCommitPolicy=RoundRobin -smtFetchPolicy=SingleThread -smtIQPolicy=Partitioned -smtIQThreshold=100 -smtLSQPolicy=Partitioned -smtLSQThreshold=100 -smtNumFetchingThreads=1 -smtROBPolicy=Partitioned -smtROBThreshold=100 -socket_id=0 -squashWidth=8 -store_set_clear_period=250000 -switched_out=false -system=system -tracer=system.cpu.tracer -trapLatency=13 -wbWidth=8 -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.branchPred] -type=TournamentBP -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -indirectHashGHR=true -indirectHashTargets=true -indirectPathLength=3 -indirectSets=256 -indirectTagSize=16 -indirectWays=2 -instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 -useIndirect=true - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.fuPool] -type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 -eventq_index=0 - -[system.cpu.fuPool.FUList0] -type=FUDesc -children=opList -count=6 -eventq_index=0 -opList=system.cpu.fuPool.FUList0.opList - -[system.cpu.fuPool.FUList0.opList] -type=OpDesc -eventq_index=0 -opClass=IntAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList1] -type=FUDesc -children=opList0 opList1 -count=2 -eventq_index=0 -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -eventq_index=0 -opClass=IntMult -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -eventq_index=0 -opClass=IntDiv -opLat=20 -pipelined=false - -[system.cpu.fuPool.FUList2] -type=FUDesc -children=opList0 opList1 opList2 -count=4 -eventq_index=0 -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -eventq_index=0 -opClass=FloatAdd -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -eventq_index=0 -opClass=FloatCmp -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -eventq_index=0 -opClass=FloatCvt -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList3] -type=FUDesc -children=opList0 opList1 opList2 -count=2 -eventq_index=0 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -eventq_index=0 -opClass=FloatMult -opLat=4 -pipelined=true - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -eventq_index=0 -opClass=FloatDiv -opLat=12 -pipelined=false - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -eventq_index=0 -opClass=FloatSqrt -opLat=24 -pipelined=false - -[system.cpu.fuPool.FUList4] -type=FUDesc -children=opList -count=0 -eventq_index=0 -opList=system.cpu.fuPool.FUList4.opList - -[system.cpu.fuPool.FUList4.opList] -type=OpDesc -eventq_index=0 -opClass=MemRead -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5] -type=FUDesc -children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 -count=4 -eventq_index=0 -opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 - -[system.cpu.fuPool.FUList5.opList00] -type=OpDesc -eventq_index=0 -opClass=SimdAdd -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList01] -type=OpDesc -eventq_index=0 -opClass=SimdAddAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList02] -type=OpDesc -eventq_index=0 -opClass=SimdAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList03] -type=OpDesc -eventq_index=0 -opClass=SimdCmp -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList04] -type=OpDesc -eventq_index=0 -opClass=SimdCvt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList05] -type=OpDesc -eventq_index=0 -opClass=SimdMisc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList06] -type=OpDesc -eventq_index=0 -opClass=SimdMult -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList07] -type=OpDesc -eventq_index=0 -opClass=SimdMultAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList08] -type=OpDesc -eventq_index=0 -opClass=SimdShift -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList09] -type=OpDesc -eventq_index=0 -opClass=SimdShiftAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList10] -type=OpDesc -eventq_index=0 -opClass=SimdSqrt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList11] -type=OpDesc -eventq_index=0 -opClass=SimdFloatAdd -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList12] -type=OpDesc -eventq_index=0 -opClass=SimdFloatAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList13] -type=OpDesc -eventq_index=0 -opClass=SimdFloatCmp -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList14] -type=OpDesc -eventq_index=0 -opClass=SimdFloatCvt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList15] -type=OpDesc -eventq_index=0 -opClass=SimdFloatDiv -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList16] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMisc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList17] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMult -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList18] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMultAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList19] -type=OpDesc -eventq_index=0 -opClass=SimdFloatSqrt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList6] -type=FUDesc -children=opList -count=0 -eventq_index=0 -opList=system.cpu.fuPool.FUList6.opList - -[system.cpu.fuPool.FUList6.opList] -type=OpDesc -eventq_index=0 -opClass=MemWrite -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList7] -type=FUDesc -children=opList0 opList1 -count=4 -eventq_index=0 -opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -eventq_index=0 -opClass=MemRead -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList7.opList1] -type=OpDesc -eventq_index=0 -opClass=MemWrite -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList8] -type=FUDesc -children=opList -count=1 -eventq_index=0 -opList=system.cpu.fuPool.FUList8.opList - -[system.cpu.fuPool.FUList8.opList] -type=OpDesc -eventq_index=0 -opClass=IprAccess -opLat=3 -pipelined=false - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=bzip2 input.source 1 -cwd=build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/bzip2 -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=0:134217727:0:0:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=6000 -tXPDLL=0 -tXS=270000 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,7 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(1, ...) diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,29 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:19:44 -gem5 executing on e108600-lin, pid 28058 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/60.bzip2/alpha/tru64/o3-timing - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -info: Increasing stack size by one page. -spec_init -Loading Input Data -Input data 1048576 bytes in length -Compressing Input Data, level 7 -Compressed data 198546 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 198677 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! -Exiting @ tick 684199968000 because target called exit() diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,1119 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.684200 # Number of seconds simulated -sim_ticks 684199968000 # Number of ticks simulated -final_tick 684199968000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 295566 # Simulator instruction rate (inst/s) -host_op_rate 295566 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 116486932 # Simulator tick rate (ticks/s) -host_mem_usage 257340 # Number of bytes of host memory used -host_seconds 5873.62 # Real time elapsed on the host -sim_insts 1736043781 # Number of instructions simulated -sim_ops 1736043781 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 684199968000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 60736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 126674880 # Number of bytes read from this memory -system.physmem.bytes_read::total 126735616 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 60736 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 60736 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 66206592 # Number of bytes written to this memory -system.physmem.bytes_written::total 66206592 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 949 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1979295 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1980244 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1034478 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1034478 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 88769 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 185143066 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 185231836 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 88769 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 88769 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 96764974 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 96764974 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 96764974 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 88769 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 185143066 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 281996809 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1980244 # Number of read requests accepted -system.physmem.writeReqs 1034478 # Number of write requests accepted -system.physmem.readBursts 1980244 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1034478 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 126652288 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 83328 # Total number of bytes read from write queue -system.physmem.bytesWritten 66205120 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 126735616 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 66206592 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1302 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 119682 # Per bank write bursts -system.physmem.perBankRdBursts::1 115093 # Per bank write bursts -system.physmem.perBankRdBursts::2 117079 # Per bank write bursts -system.physmem.perBankRdBursts::3 118658 # Per bank write bursts -system.physmem.perBankRdBursts::4 118799 # Per bank write bursts -system.physmem.perBankRdBursts::5 118596 # Per bank write bursts -system.physmem.perBankRdBursts::6 121104 # Per bank write bursts -system.physmem.perBankRdBursts::7 126057 # Per bank write bursts -system.physmem.perBankRdBursts::8 128556 # Per bank write bursts -system.physmem.perBankRdBursts::9 131368 # Per bank write bursts -system.physmem.perBankRdBursts::10 130043 # Per bank write bursts -system.physmem.perBankRdBursts::11 131744 # Per bank write bursts -system.physmem.perBankRdBursts::12 127398 # Per bank write bursts -system.physmem.perBankRdBursts::13 126519 # Per bank write bursts -system.physmem.perBankRdBursts::14 123764 # Per bank write bursts -system.physmem.perBankRdBursts::15 124482 # Per bank write bursts -system.physmem.perBankWrBursts::0 62070 # Per bank write bursts -system.physmem.perBankWrBursts::1 62408 # Per bank write bursts -system.physmem.perBankWrBursts::2 61409 # Per bank write bursts -system.physmem.perBankWrBursts::3 62103 # Per bank write bursts -system.physmem.perBankWrBursts::4 62566 # Per bank write bursts -system.physmem.perBankWrBursts::5 64096 # Per bank write bursts -system.physmem.perBankWrBursts::6 65160 # Per bank write bursts -system.physmem.perBankWrBursts::7 66609 # Per bank write bursts -system.physmem.perBankWrBursts::8 66404 # Per bank write bursts -system.physmem.perBankWrBursts::9 66820 # Per bank write bursts -system.physmem.perBankWrBursts::10 66475 # Per bank write bursts -system.physmem.perBankWrBursts::11 66816 # Per bank write bursts -system.physmem.perBankWrBursts::12 65322 # Per bank write bursts -system.physmem.perBankWrBursts::13 65320 # Per bank write bursts -system.physmem.perBankWrBursts::14 65711 # Per bank write bursts -system.physmem.perBankWrBursts::15 65166 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 684199865500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1980244 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1034478 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1615224 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 253124 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 75634 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 34936 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 22 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 24649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 26003 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 51175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 58148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 60543 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 61668 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 61807 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 61824 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 61855 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 61800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 61827 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 61964 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 62700 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 64398 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 66372 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 62691 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 62546 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1786108 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 107.975625 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 82.936522 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 138.228671 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1386417 77.62% 77.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 276583 15.49% 93.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 52891 2.96% 96.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20920 1.17% 97.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 12358 0.69% 97.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 6524 0.37% 98.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5164 0.29% 98.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3751 0.21% 98.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 21500 1.20% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1786108 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 61165 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 32.352277 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 22.914892 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 140.448273 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 60991 99.72% 99.72% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 137 0.22% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1535 7 0.01% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-2047 4 0.01% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-2559 5 0.01% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2560-3071 4 0.01% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-3583 2 0.00% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3584-4095 3 0.00% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-4607 2 0.00% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4608-5119 4 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::6656-7167 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8704-9215 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::9216-9727 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::11776-12287 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12800-13311 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::15360-15871 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 61165 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 61165 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.912532 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.877578 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.101156 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 34708 56.74% 56.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1369 2.24% 58.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 21665 35.42% 94.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 2721 4.45% 98.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 576 0.94% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 109 0.18% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 15 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 61165 # Writes before turning the bus around for reads -system.physmem.totQLat 56581400750 # Total ticks spent queuing -system.physmem.totMemAccLat 93686563250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9894710000 # Total ticks spent in databus transfers -system.physmem.avgQLat 28591.74 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 47341.74 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 185.11 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 96.76 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 185.23 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 96.76 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.20 # Data bus utilization in percentage -system.physmem.busUtilRead 1.45 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.76 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.11 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.71 # Average write queue length when enqueuing -system.physmem.readRowHits 796002 # Number of row buffer hits during reads -system.physmem.writeRowHits 431282 # Number of row buffer hits during writes -system.physmem.readRowHitRate 40.22 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 41.69 # Row buffer hit rate for writes -system.physmem.avgGap 226952.89 # Average gap between requests -system.physmem.pageHitRate 40.73 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6177735060 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3283540260 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 6819185520 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 2643517620 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 44816475600.000008 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 37044798750 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1443275040 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 170396037690 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 31359460320 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 36616359660 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 340610162070 # Total energy per rank (pJ) -system.physmem_0.averagePower 497.822532 # Core power per rank (mW) -system.physmem_0.totalIdleTime 599184631500 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 1534958250 # Time in different power states -system.physmem_0.memoryStateTime::REF 18981984000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 143840379000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 81664935250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 64497738500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 373679973000 # Time in different power states -system.physmem_1.actEnergy 6575111760 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3494739600 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 7310460360 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 2756337480 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 45376412640.000008 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 37526229300 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1410684000 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 175219175340 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 30265452000 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 34407180735 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 344356241235 # Total energy per rank (pJ) -system.physmem_1.averagePower 503.297652 # Core power per rank (mW) -system.physmem_1.totalIdleTime 598199672750 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 1433387500 # Time in different power states -system.physmem_1.memoryStateTime::REF 19217296000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 135130926250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 78815070250 # Time in different power states -system.physmem_1.memoryStateTime::ACT 65349556500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 384253731500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 684199968000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 409436754 # Number of BP lookups -system.cpu.branchPred.condPredicted 318234486 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15963820 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 282367334 # Number of BTB lookups -system.cpu.branchPred.BTBHits 278623697 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.674196 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 26172484 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 47 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 12628 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 1002 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 11626 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 76 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 645003218 # DTB read hits -system.cpu.dtb.read_misses 12159343 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 657162561 # DTB read accesses -system.cpu.dtb.write_hits 218108239 # DTB write hits -system.cpu.dtb.write_misses 7507876 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 225616115 # DTB write accesses -system.cpu.dtb.data_hits 863111457 # DTB hits -system.cpu.dtb.data_misses 19667219 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 882778676 # DTB accesses -system.cpu.itb.fetch_hits 420694791 # ITB hits -system.cpu.itb.fetch_misses 37 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 420694828 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 684199968000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1368399937 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 431834940 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3410573803 # Number of instructions fetch has processed -system.cpu.fetch.Branches 409436754 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 304797183 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 913784247 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 45380414 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1708 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 42 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 420694791 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 8284167 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1368311169 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.492543 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.138689 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 743223403 54.32% 54.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 47685517 3.48% 57.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 24183643 1.77% 59.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 45097399 3.30% 62.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 142825430 10.44% 73.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 65953370 4.82% 78.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 43585313 3.19% 81.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 29408397 2.15% 83.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 226348697 16.54% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1368311169 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.299208 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.492381 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 353769261 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 432754726 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 524267891 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 34829792 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 22689499 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 62032551 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 750 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3256358950 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2045 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 22689499 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 372017301 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 224454621 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 9976 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 537214927 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 211924845 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3173979679 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1947204 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 21862090 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 161736150 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 34961727 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2371970000 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 4117940809 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 4117804241 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 136567 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 995767037 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 144 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 143 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 99713027 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 717292360 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 272467386 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 90468830 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 58360421 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2884387847 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 125 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2620166340 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1550282 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 1148344190 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 502911540 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 96 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1368311169 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.914891 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.143845 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 564702258 41.27% 41.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 169734991 12.40% 53.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 158008570 11.55% 65.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 149164272 10.90% 76.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 126054849 9.21% 85.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 84104604 6.15% 91.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 68048276 4.97% 96.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 34057471 2.49% 98.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 14435878 1.06% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1368311169 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 13157745 35.86% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 18955559 51.65% 87.51% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4574949 12.47% 99.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 21 0.00% 99.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 8342 0.02% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1716973131 65.53% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 113 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 895059 0.03% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 21 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 165 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 32 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 671606942 25.63% 91.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 230625627 8.80% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 214 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 65011 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2620166340 # Type of FU issued -system.cpu.iq.rate 1.914766 # Inst issue rate -system.cpu.iq.fu_busy_cnt 36696616 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014005 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6644950011 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 4031627633 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2518705843 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1940736 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1246935 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 885827 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2655894066 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 968890 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 69399237 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 272696697 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 372755 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 144718 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 111738884 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 276 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 6347426 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 22689499 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 153700665 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 24607409 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 3035418130 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 6594075 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 717292360 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 272467386 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 125 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 793020 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 24069505 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 144718 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10634250 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8701065 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 19335315 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2575033857 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 657162570 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 45132483 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 151030158 # number of nop insts executed -system.cpu.iew.exec_refs 882778753 # number of memory reference insts executed -system.cpu.iew.exec_branches 315511040 # Number of branches executed -system.cpu.iew.exec_stores 225616183 # Number of stores executed -system.cpu.iew.exec_rate 1.881785 # Inst execution rate -system.cpu.iew.wb_sent 2549403036 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2519591670 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1487461563 # num instructions producing a value -system.cpu.iew.wb_consumers 1918503373 # num instructions consuming a value -system.cpu.iew.wb_rate 1.841268 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.775324 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 998993468 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15963112 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1230277663 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.479162 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.528603 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 741569515 60.28% 60.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 159647987 12.98% 73.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 79500884 6.46% 79.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 52016561 4.23% 83.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 28471103 2.31% 86.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 19445294 1.58% 87.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19999560 1.63% 89.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 23041626 1.87% 91.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106585133 8.66% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1230277663 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1819780126 # Number of instructions committed -system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 605324165 # Number of memory references committed -system.cpu.commit.loads 444595663 # Number of loads committed -system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 214632552 # Number of branches committed -system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions. -system.cpu.commit.function_calls 16767440 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 83736345 4.60% 4.60% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 1129914149 62.09% 66.69% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 75 0.00% 66.69% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.69% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 805244 0.04% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 13 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 100 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 11 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 24 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.74% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 444595584 24.43% 91.17% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 160728448 8.83% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemRead 79 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemWrite 54 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 1819780126 # Class of committed instruction -system.cpu.commit.bw_lim_events 106585133 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3856686924 # The number of ROB reads -system.cpu.rob.rob_writes 5775715040 # The number of ROB writes -system.cpu.timesIdled 709 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 88768 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1736043781 # Number of Instructions Simulated -system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.788229 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.788229 # CPI: Total CPI of All Threads -system.cpu.ipc 1.268667 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.268667 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3463738117 # number of integer regfile reads -system.cpu.int_regfile_writes 2019389646 # number of integer regfile writes -system.cpu.fp_regfile_reads 39803 # number of floating regfile reads -system.cpu.fp_regfile_writes 598 # number of floating regfile writes -system.cpu.misc_regfile_reads 25 # number of misc regfile reads -system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 684199968000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 9207265 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.531672 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 712311191 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9211361 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 77.329636 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 5174346500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.531672 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997933 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997933 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 666 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2980 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 446 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1470218079 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1470218079 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 684199968000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 556814159 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 556814159 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 155497028 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 155497028 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 4 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 4 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 712311187 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 712311187 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 712311187 # number of overall hits -system.cpu.dcache.overall_hits::total 712311187 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 12960693 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 12960693 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5231474 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5231474 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 18192167 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 18192167 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 18192167 # number of overall misses -system.cpu.dcache.overall_misses::total 18192167 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 452018170000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 452018170000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 345871511780 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 345871511780 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 79500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 79500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 797889681780 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 797889681780 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 797889681780 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 797889681780 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 569774852 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 569774852 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 5 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 730503354 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 730503354 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 730503354 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 730503354 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022747 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.022747 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032549 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032549 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.200000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.200000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.024904 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.024904 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.024904 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.024904 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34876.080315 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34876.080315 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66113.587066 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 66113.587066 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 79500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 79500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 43858.968631 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 43858.968631 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 43858.968631 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 43858.968631 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 16718017 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 10716708 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1109373 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 69036 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.069789 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 155.233617 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 3713171 # number of writebacks -system.cpu.dcache.writebacks::total 3713171 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5628505 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 5628505 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3352302 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3352302 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 8980807 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 8980807 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 8980807 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 8980807 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7332188 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7332188 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1879172 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1879172 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9211360 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9211360 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9211360 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9211360 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 194855974500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 194855974500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 91510360097 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 91510360097 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 78500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 78500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 286366334597 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 286366334597 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 286366334597 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 286366334597 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.012869 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.012869 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011692 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011692 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.200000 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.200000 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012610 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.012610 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012610 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.012610 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 26575.419847 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26575.419847 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48697.170933 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48697.170933 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 78500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 78500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31088.388099 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 31088.388099 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31088.388099 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 31088.388099 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 684199968000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 753.632230 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 420693280 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 949 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 443301.664910 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 753.632230 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.367984 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.367984 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 948 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 882 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.462891 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 841390531 # Number of tag accesses -system.cpu.icache.tags.data_accesses 841390531 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 684199968000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 420693280 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 420693280 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 420693280 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 420693280 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 420693280 # number of overall hits -system.cpu.icache.overall_hits::total 420693280 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1511 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1511 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1511 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1511 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1511 # number of overall misses -system.cpu.icache.overall_misses::total 1511 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 138965499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 138965499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 138965499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 138965499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 138965499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 138965499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 420694791 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 420694791 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 420694791 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 420694791 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 420694791 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 420694791 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 91969.225017 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 91969.225017 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 91969.225017 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 91969.225017 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 91969.225017 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 91969.225017 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 347 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 115.666667 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 1 # number of writebacks -system.cpu.icache.writebacks::total 1 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 562 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 562 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 562 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 562 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 562 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 562 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 949 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 949 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 949 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 949 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 949 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 949 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 93919999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 93919999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 93919999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 93919999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 93919999 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 93919999 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 98967.332982 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 98967.332982 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 98967.332982 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 98967.332982 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 98967.332982 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 98967.332982 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 684199968000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 1947802 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32040.149631 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 16438766 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1980570 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 8.300018 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 28106474000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 8.660797 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.112733 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 32006.376101 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000264 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000766 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.976757 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.977788 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3407 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 643 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13986 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 14548 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 149337178 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 149337178 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 684199968000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 3713171 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 3713171 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1095576 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1095576 # number of ReadExReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6136490 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 6136490 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.data 7232066 # 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1980244 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 949 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1979295 # number of overall misses -system.cpu.l2cache.overall_misses::total 1980244 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 76631269000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 76631269000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 92491000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 92491000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 118466842500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 118466842500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 92491000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 195098111500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 195190602500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 92491000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 195098111500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 195190602500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 3713171 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 3713171 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1879188 # number of ReadExReq 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accesses -system.cpu.l2cache.overall_accesses::total 9212310 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.416995 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.416995 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.163073 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.163073 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.214875 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.214956 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.214875 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.214956 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 97792.362802 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 97792.362802 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 97461.538462 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 97461.538462 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 99078.804750 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 99078.804750 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 97461.538462 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 98569.496462 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 98568.965491 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 97461.538462 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 98569.496462 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 98568.965491 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 1034478 # number of writebacks -system.cpu.l2cache.writebacks::total 1034478 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 240 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 240 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 783612 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 783612 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 949 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 949 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1195683 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1195683 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 949 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1979295 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1980244 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 949 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1979295 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1980244 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 68795149000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 68795149000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 83001000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 83001000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 106510012500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 106510012500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 83001000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 175305161500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 175388162500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 83001000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 175305161500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 175388162500 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.416995 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.416995 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.163073 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.163073 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214875 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.214956 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214875 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.214956 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 87792.362802 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 87792.362802 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 87461.538462 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 87461.538462 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 89078.804750 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 89078.804750 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 87461.538462 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88569.496462 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88568.965491 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 87461.538462 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88569.496462 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 88568.965491 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 18419576 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 9207266 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1448 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1448 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 684199968000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 7333122 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 4747649 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6407418 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1879188 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1879188 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 949 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7332173 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1899 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27629987 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27631886 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 60800 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 827170048 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 827230848 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1947802 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 66206592 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 11160112 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000130 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.011390 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 11158664 99.99% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1448 0.01% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 11160112 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12922960000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1423500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13817041500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 3926838 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 1946594 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 684199968000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1196632 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1034478 # Transaction distribution -system.membus.trans_dist::CleanEvict 912116 # Transaction distribution -system.membus.trans_dist::ReadExReq 783612 # Transaction distribution -system.membus.trans_dist::ReadExResp 783612 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1196632 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5907082 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5907082 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 192942208 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 192942208 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 1980244 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1980244 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 1980244 # Request fanout histogram -system.membus.reqLayer0.occupancy 8533086500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 10770167500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.6 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,203 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=atomic -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=AtomicSimpleCPU -children=dtb interrupts isa itb tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -fastmem=false -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -simulate_data_stalls=false -simulate_inst_stalls=false -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -width=1 -workload=system.cpu.workload -dcache_port=system.membus.slave[2] -icache_port=system.membus.slave[1] - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=bzip2 input.source 1 -cwd=build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-atomic -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/bzip2 -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=Null -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.icache_port system.cpu.dcache_port - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=0:134217727 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simerr --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simerr Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,6 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(1, ...) diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,29 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-atomic/simout -Redirecting stderr to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-atomic/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 21 2016 14:09:29 -gem5 executing on e108600-lin, pid 4310 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/60.bzip2/alpha/tru64/simple-atomic - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -info: Increasing stack size by one page. -spec_init -Loading Input Data -Input data 1048576 bytes in length -Compressing Input Data, level 7 -Compressed data 198546 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 198677 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! -Exiting @ tick 913189263000 because target called exit() diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,167 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.913189 # Number of seconds simulated -sim_ticks 913189263000 # Number of ticks simulated -final_tick 913189263000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3052391 # Simulator instruction rate (inst/s) -host_op_rate 3052390 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1531729085 # Simulator tick rate (ticks/s) -host_mem_usage 242484 # Number of bytes of host memory used -host_seconds 596.18 # Real time elapsed on the host -sim_insts 1819780127 # Number of instructions simulated -sim_ops 1819780127 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 913189263000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 7305514036 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1974795935 # Number of bytes read from this memory -system.physmem.bytes_read::total 9280309971 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 7305514036 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 7305514036 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 827777307 # Number of bytes written to this memory -system.physmem.bytes_written::total 827777307 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1826378509 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 444595663 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2270974172 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 160728502 # Number of write requests responded to by this memory -system.physmem.num_writes::total 160728502 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7999999926 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2162526450 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10162526375 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7999999926 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7999999926 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 906468506 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 906468506 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7999999926 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3068994956 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 11068994882 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 913189263000 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 444595663 # DTB read hits -system.cpu.dtb.read_misses 4897078 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 449492741 # DTB read accesses -system.cpu.dtb.write_hits 160728502 # DTB write hits -system.cpu.dtb.write_misses 1701304 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 162429806 # DTB write accesses -system.cpu.dtb.data_hits 605324165 # DTB hits -system.cpu.dtb.data_misses 6598382 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 611922547 # DTB accesses -system.cpu.itb.fetch_hits 1826378509 # ITB hits -system.cpu.itb.fetch_misses 18 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 1826378527 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 913189263000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1826378527 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 1819780127 # Number of instructions committed -system.cpu.committedOps 1819780127 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1725565901 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 805526 # Number of float alu accesses -system.cpu.num_func_calls 33534877 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 164021647 # number of instructions that are conditional controls -system.cpu.num_int_insts 1725565901 # number of integer instructions -system.cpu.num_fp_insts 805526 # number of float instructions -system.cpu.num_int_register_reads 2347934659 # number of times the integer registers were read -system.cpu.num_int_register_writes 1376202618 # number of times the integer registers were written -system.cpu.num_fp_register_reads 357 # number of times the floating registers were read -system.cpu.num_fp_register_writes 345 # number of times the floating registers were written -system.cpu.num_mem_refs 611922547 # number of memory refs -system.cpu.num_load_insts 449492741 # Number of load instructions -system.cpu.num_store_insts 162429806 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1826378527 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 214632552 # Number of branches fetched -system.cpu.op_class::No_OpClass 83736345 4.58% 4.58% # Class of executed instruction -system.cpu.op_class::IntAlu 1129914150 61.87% 66.45% # Class of executed instruction -system.cpu.op_class::IntMult 75 0.00% 66.45% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 66.45% # Class of executed instruction -system.cpu.op_class::FloatAdd 805244 0.04% 66.50% # Class of executed instruction -system.cpu.op_class::FloatCmp 13 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::FloatCvt 100 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::FloatMult 11 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::FloatDiv 24 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::MemRead 449492662 24.61% 91.11% # Class of executed instruction -system.cpu.op_class::MemWrite 162429751 8.89% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 79 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 55 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1826378509 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 913189263000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 2270974172 # Transaction distribution -system.membus.trans_dist::ReadResp 2270974172 # Transaction distribution -system.membus.trans_dist::WriteReq 160728502 # Transaction distribution -system.membus.trans_dist::WriteResp 160728502 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 3652757018 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1210648330 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4863405348 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 7305514036 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 2802573242 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 10108087278 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 2431702674 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2431702674 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 2431702674 # Request fanout histogram - ----------- End Simulation Statistics ---------- diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,366 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=bzip2 input.source 1 -cwd=build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/bzip2 -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=Null -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=0:134217727 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simerr --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simerr Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,6 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(1, ...) diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,29 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 21 2016 14:09:29 -gem5 executing on e108600-lin, pid 4312 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/60.bzip2/alpha/tru64/simple-timing - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -info: Increasing stack size by one page. -spec_init -Loading Input Data -Input data 1048576 bytes in length -Compressing Input Data, level 7 -Compressed data 198546 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Compressing Input Data, level 9 -Compressed data 198677 bytes in length -Uncompressing Data -Uncompressed data 1048576 bytes in length -Uncompressed data compared correctly -Tested 1MB buffer: OK! -Exiting @ tick 2636719559500 because target called exit() diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,566 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 2.639614 # Number of seconds simulated -sim_ticks 2639613874500 # Number of ticks simulated -final_tick 2639613874500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2013574 # Simulator instruction rate (inst/s) -host_op_rate 2013574 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2920714569 # Simulator tick rate (ticks/s) -host_mem_usage 253500 # Number of bytes of host memory used -host_seconds 903.76 # Real time elapsed on the host -sim_insts 1819780127 # Number of instructions simulated -sim_ops 1819780127 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 51328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 126106432 # Number of bytes read from this memory -system.physmem.bytes_read::total 126157760 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 51328 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 51328 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 66087296 # Number of bytes written to this memory -system.physmem.bytes_written::total 66087296 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 802 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1970413 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1971215 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1032614 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1032614 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 19445 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 47774575 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 47794021 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 19445 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 19445 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 25036729 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 25036729 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 25036729 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 19445 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 47774575 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 72830749 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 444595663 # DTB read hits -system.cpu.dtb.read_misses 4897078 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 449492741 # DTB read accesses -system.cpu.dtb.write_hits 160728502 # DTB write hits -system.cpu.dtb.write_misses 1701304 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 162429806 # DTB write accesses -system.cpu.dtb.data_hits 605324165 # DTB hits -system.cpu.dtb.data_misses 6598382 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 611922547 # DTB accesses -system.cpu.itb.fetch_hits 1826378510 # ITB hits -system.cpu.itb.fetch_misses 18 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 1826378528 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 2639613874500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 5279227749 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 1819780127 # Number of instructions committed -system.cpu.committedOps 1819780127 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1725565901 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 805526 # Number of float alu accesses -system.cpu.num_func_calls 33534877 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 164021647 # number of instructions that are conditional controls -system.cpu.num_int_insts 1725565901 # number of integer instructions -system.cpu.num_fp_insts 805526 # number of float instructions -system.cpu.num_int_register_reads 2347934659 # number of times the integer registers were read -system.cpu.num_int_register_writes 1376202618 # number of times the integer registers were written -system.cpu.num_fp_register_reads 357 # number of times the floating registers were read -system.cpu.num_fp_register_writes 345 # number of times the floating registers were written -system.cpu.num_mem_refs 611922547 # number of memory refs -system.cpu.num_load_insts 449492741 # Number of load instructions -system.cpu.num_store_insts 162429806 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 5279227749 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 214632552 # Number of branches fetched -system.cpu.op_class::No_OpClass 83736345 4.58% 4.58% # Class of executed instruction -system.cpu.op_class::IntAlu 1129914150 61.87% 66.45% # Class of executed instruction -system.cpu.op_class::IntMult 75 0.00% 66.45% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 66.45% # Class of executed instruction -system.cpu.op_class::FloatAdd 805244 0.04% 66.50% # Class of executed instruction -system.cpu.op_class::FloatCmp 13 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::FloatCvt 100 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::FloatMult 11 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::FloatDiv 24 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 66.50% # Class of executed instruction -system.cpu.op_class::MemRead 449492662 24.61% 91.11% # Class of executed instruction -system.cpu.op_class::MemWrite 162429751 8.89% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 79 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 55 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1826378509 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 9107638 # number of replacements -system.cpu.dcache.tags.tagsinuse 4079.303630 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 596212431 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9111734 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 65.433476 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 41048093500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4079.303630 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.995924 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.995924 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1191 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2646 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 206 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1219760064 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1219760064 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 437373249 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 437373249 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 158839182 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 158839182 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 596212431 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 596212431 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 596212431 # number of overall hits -system.cpu.dcache.overall_hits::total 596212431 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7222414 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7222414 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1889320 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1889320 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 9111734 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9111734 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9111734 # number of overall misses -system.cpu.dcache.overall_misses::total 9111734 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 152711735000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 152711735000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 64261460000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 64261460000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 216973195000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 216973195000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 216973195000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 216973195000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 605324165 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 605324165 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 605324165 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016245 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.016245 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011755 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.011755 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.015053 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.015053 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.015053 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.015053 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21144.140311 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 21144.140311 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34013.009972 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34013.009972 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23812.503196 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23812.503196 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23812.503196 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23812.503196 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 3664823 # number of writebacks -system.cpu.dcache.writebacks::total 3664823 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222414 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7222414 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889320 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1889320 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9111734 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9111734 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9111734 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9111734 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 145489321000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 145489321000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 62372140000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 62372140000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 207861461000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 207861461000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 207861461000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 207861461000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011755 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011755 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.015053 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.015053 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20144.140311 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20144.140311 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33013.009972 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33013.009972 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22812.503196 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22812.503196 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22812.503196 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22812.503196 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 612.633318 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1826377708 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 802 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 2277278.937656 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 612.633318 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.299137 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.299137 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 801 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 730 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.391113 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 3652757822 # Number of tag accesses -system.cpu.icache.tags.data_accesses 3652757822 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 1826377708 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1826377708 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1826377708 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1826377708 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1826377708 # number of overall hits -system.cpu.icache.overall_hits::total 1826377708 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 802 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 802 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 802 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 802 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 802 # number of overall misses -system.cpu.icache.overall_misses::total 802 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 50541500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 50541500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 50541500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 50541500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 50541500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 50541500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1826378510 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1826378510 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1826378510 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1826378510 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1826378510 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1826378510 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63019.326683 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 63019.326683 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 63019.326683 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 63019.326683 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 63019.326683 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 63019.326683 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 1 # number of writebacks -system.cpu.icache.writebacks::total 1 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 802 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 802 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 802 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 802 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 802 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 49739500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 49739500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 49739500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 49739500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 49739500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 49739500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62019.326683 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62019.326683 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62019.326683 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 62019.326683 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62019.326683 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 62019.326683 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 1938767 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31260.683710 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 16248398 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1971535 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 8.241496 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 217871689000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 8.109026 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 38.419408 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31214.155276 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000247 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001172 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.952580 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.954000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 664 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2920 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1281 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27794 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 147732935 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 147732935 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 3664823 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 3664823 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1095314 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1095314 # number of ReadExReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6046007 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 6046007 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.data 7141321 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7141321 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 7141321 # number of overall hits -system.cpu.l2cache.overall_hits::total 7141321 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 794006 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 794006 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 802 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 802 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1176407 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 1176407 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 802 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1970413 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1971215 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 802 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1970413 # number of overall misses -system.cpu.l2cache.overall_misses::total 1971215 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 48037363000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 48037363000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 48529000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 48529000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 71172626500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 71172626500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 48529000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 119209989500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 119258518500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 48529000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 119209989500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 119258518500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 3664823 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 3664823 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889320 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1889320 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 802 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 802 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7222414 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 7222414 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 802 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9111734 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9112536 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 802 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9111734 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9112536 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.420260 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.420260 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.162883 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.162883 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.216250 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.216319 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.216250 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.216319 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60509.975062 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60509.975062 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500.002550 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500.002550 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60509.975062 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500.001523 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 60500.005580 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60509.975062 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500.001523 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 60500.005580 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 1032614 # number of writebacks -system.cpu.l2cache.writebacks::total 1032614 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 242 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 242 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 794006 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 794006 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 802 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 802 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1176407 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1176407 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 802 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1970413 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1971215 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1970413 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1971215 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 40097303000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 40097303000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 40509000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 40509000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 59408556500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 59408556500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40509000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 99505859500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 99546368500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40509000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 99505859500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 99546368500 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.420260 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.420260 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.162883 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.162883 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216250 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.216319 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216250 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.216319 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50509.975062 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50509.975062 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500.002550 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500.002550 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50509.975062 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500.001523 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.005580 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50509.975062 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500.001523 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.005580 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 18220175 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 9107639 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1292 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1292 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 7223216 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 4697437 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6348968 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1889320 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1889320 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 802 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7222414 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1605 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27331106 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27332711 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51392 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 817699648 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 817751040 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1938767 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 66087296 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 11051303 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000117 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.010812 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 11050011 99.99% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1292 0.01% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 11051303 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12774911500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1203000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13667601000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 3908932 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 1937717 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2639613874500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1177209 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1032614 # Transaction distribution -system.membus.trans_dist::CleanEvict 905103 # Transaction distribution -system.membus.trans_dist::ReadExReq 794006 # Transaction distribution -system.membus.trans_dist::ReadExResp 794006 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1177209 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5880147 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5880147 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 192245056 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 192245056 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 1971215 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1971215 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 1971215 # Request fanout histogram -system.membus.reqLayer0.occupancy 8039396000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 9856075000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.4 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/config.ini Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,877 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=MinorCPU -children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload -branchPred=system.cpu.branchPred -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -decodeCycleInput=true -decodeInputBufferSize=3 -decodeInputWidth=2 -decodeToExecuteForwardDelay=1 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -enableIdling=true -eventq_index=0 -executeAllowEarlyMemoryIssue=true -executeBranchDelay=1 -executeCommitLimit=2 -executeCycleInput=true -executeFuncUnits=system.cpu.executeFuncUnits -executeInputBufferSize=7 -executeInputWidth=2 -executeIssueLimit=2 -executeLSQMaxStoreBufferStoresPerCycle=2 -executeLSQRequestsQueueSize=1 -executeLSQStoreBufferSize=5 -executeLSQTransfersQueueSize=2 -executeMaxAccessesInMemory=2 -executeMemoryCommitLimit=1 -executeMemoryIssueLimit=1 -executeMemoryWidth=0 -executeSetTraceTimeOnCommit=true -executeSetTraceTimeOnIssue=false -fetch1FetchLimit=1 -fetch1LineSnapWidth=0 -fetch1LineWidth=0 -fetch1ToFetch2BackwardDelay=1 -fetch1ToFetch2ForwardDelay=1 -fetch2CycleInput=true -fetch2InputBufferSize=2 -fetch2ToDecodeForwardDelay=1 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -threadPolicy=RoundRobin -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.branchPred] -type=TournamentBP -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -indirectHashGHR=true -indirectHashTargets=true -indirectPathLength=3 -indirectSets=256 -indirectTagSize=16 -indirectWays=2 -instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 -useIndirect=true - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.executeFuncUnits] -type=MinorFUPool -children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 -eventq_index=0 -funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 - -[system.cpu.executeFuncUnits.funcUnits0] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits0.timings - -[system.cpu.executeFuncUnits.funcUnits0.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntAlu - -[system.cpu.executeFuncUnits.funcUnits0.timings] -type=MinorFUTiming -children=opClasses -description=Int -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits1] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits1.timings - -[system.cpu.executeFuncUnits.funcUnits1.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntAlu - -[system.cpu.executeFuncUnits.funcUnits1.timings] -type=MinorFUTiming -children=opClasses -description=Int -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits2] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits2.timings - -[system.cpu.executeFuncUnits.funcUnits2.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntMult - -[system.cpu.executeFuncUnits.funcUnits2.timings] -type=MinorFUTiming -children=opClasses -description=Mul -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses -srcRegsRelativeLats=0 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits3] -type=MinorFU -children=opClasses -cantForwardFromFUIndices= -eventq_index=0 -issueLat=9 -opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses -opLat=9 -timings= - -[system.cpu.executeFuncUnits.funcUnits3.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntDiv - -[system.cpu.executeFuncUnits.funcUnits4] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses -opLat=6 -timings=system.cpu.executeFuncUnits.funcUnits4.timings - -[system.cpu.executeFuncUnits.funcUnits4.opClasses] -type=MinorOpClassSet -children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] -type=MinorOpClass -eventq_index=0 -opClass=FloatAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01] -type=MinorOpClass -eventq_index=0 -opClass=FloatCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02] -type=MinorOpClass -eventq_index=0 -opClass=FloatCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] -type=MinorOpClass -eventq_index=0 -opClass=FloatMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] -type=MinorOpClass -eventq_index=0 -opClass=FloatDiv - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] -type=MinorOpClass -eventq_index=0 -opClass=FloatSqrt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] -type=MinorOpClass -eventq_index=0 -opClass=SimdAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] -type=MinorOpClass -eventq_index=0 -opClass=SimdAddAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] -type=MinorOpClass -eventq_index=0 -opClass=SimdAlu - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] -type=MinorOpClass -eventq_index=0 -opClass=SimdCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] -type=MinorOpClass -eventq_index=0 -opClass=SimdCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] -type=MinorOpClass -eventq_index=0 -opClass=SimdMisc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] -type=MinorOpClass -eventq_index=0 -opClass=SimdMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] -type=MinorOpClass -eventq_index=0 -opClass=SimdMultAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] -type=MinorOpClass -eventq_index=0 -opClass=SimdShift - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] -type=MinorOpClass -eventq_index=0 -opClass=SimdShiftAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] -type=MinorOpClass -eventq_index=0 -opClass=SimdSqrt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatAlu - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatDiv - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMisc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMultAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatSqrt - -[system.cpu.executeFuncUnits.funcUnits4.timings] -type=MinorFUTiming -children=opClasses -description=FloatSimd -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits5] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses -opLat=1 -timings=system.cpu.executeFuncUnits.funcUnits5.timings - -[system.cpu.executeFuncUnits.funcUnits5.opClasses] -type=MinorOpClassSet -children=opClasses0 opClasses1 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 - -[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] -type=MinorOpClass -eventq_index=0 -opClass=MemRead - -[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] -type=MinorOpClass -eventq_index=0 -opClass=MemWrite - -[system.cpu.executeFuncUnits.funcUnits5.timings] -type=MinorFUTiming -children=opClasses -description=Mem -eventq_index=0 -extraAssumedLat=2 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses -srcRegsRelativeLats=1 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits6] -type=MinorFU -children=opClasses -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses -opLat=1 -timings= - -[system.cpu.executeFuncUnits.funcUnits6.opClasses] -type=MinorOpClassSet -children=opClasses0 opClasses1 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 - -[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] -type=MinorOpClass -eventq_index=0 -opClass=IprAccess - -[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] -type=MinorOpClass -eventq_index=0 -opClass=InstPrefetch - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=twolf smred -cwd=build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/twolf -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=0:134217727:0:0:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=6000 -tXPDLL=0 -tXS=270000 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simerr --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simerr Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,7 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(1, ...) diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simout --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/simout Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,29 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:19:43 -gem5 executing on e108600-lin, pid 28042 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/70.twolf/alpha/tru64/minor-timing - -Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing/smred.sav -Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/minor-timing/smred.sv2 -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. - -TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 -Standard Cell Placement and Global Routing Program -Authors: Carl Sechen, Bill Swartz - Yale University - 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 - 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 - 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 - 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 - 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 - 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 -106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 53437621500 because target called exit() diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,795 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.053438 # Number of seconds simulated -sim_ticks 53437621500 # Number of ticks simulated -final_tick 53437621500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 468238 # Simulator instruction rate (inst/s) -host_op_rate 468238 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 272260061 # Simulator tick rate (ticks/s) -host_mem_usage 257916 # Number of bytes of host memory used -host_seconds 196.27 # Real time elapsed on the host -sim_insts 91903089 # Number of instructions simulated -sim_ops 91903089 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 202880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 137728 # Number of bytes read from this memory -system.physmem.bytes_read::total 340608 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 202880 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 202880 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3170 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2152 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5322 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 3796576 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2577360 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6373936 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3796576 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3796576 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3796576 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2577360 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6373936 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5322 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5322 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 340608 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 340608 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 468 # Per bank write bursts -system.physmem.perBankRdBursts::1 295 # Per bank write bursts -system.physmem.perBankRdBursts::2 308 # Per bank write bursts -system.physmem.perBankRdBursts::3 524 # Per bank write bursts -system.physmem.perBankRdBursts::4 224 # Per bank write bursts -system.physmem.perBankRdBursts::5 238 # Per bank write bursts -system.physmem.perBankRdBursts::6 222 # Per bank write bursts -system.physmem.perBankRdBursts::7 289 # Per bank write bursts -system.physmem.perBankRdBursts::8 254 # Per bank write bursts -system.physmem.perBankRdBursts::9 282 # Per bank write bursts -system.physmem.perBankRdBursts::10 254 # Per bank write bursts -system.physmem.perBankRdBursts::11 261 # Per bank write bursts -system.physmem.perBankRdBursts::12 410 # Per bank write bursts -system.physmem.perBankRdBursts::13 344 # Per bank write bursts -system.physmem.perBankRdBursts::14 501 # Per bank write bursts -system.physmem.perBankRdBursts::15 448 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 53437285500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5322 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4860 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 449 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 981 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 347.009174 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 213.710292 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 326.985210 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 311 31.70% 31.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 198 20.18% 51.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 103 10.50% 62.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 115 11.72% 74.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 57 5.81% 79.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 30 3.06% 82.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 30 3.06% 86.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 26 2.65% 88.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 111 11.31% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 981 # Bytes accessed per row activation -system.physmem.totQLat 132267250 # Total ticks spent queuing -system.physmem.totMemAccLat 232054750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 26610000 # Total ticks spent in databus transfers -system.physmem.avgQLat 24852.92 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 43602.92 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 6.37 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 6.37 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.05 # Data bus utilization in percentage -system.physmem.busUtilRead 0.05 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4338 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.51 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 10040827.79 # Average gap between requests -system.physmem.pageHitRate 81.51 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3348660 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1772265 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 18335520 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 173328480.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 64638000 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 9138240 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 468346770 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 218747040 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 12435217200 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 13392872175 # Total energy per rank (pJ) -system.physmem_0.averagePower 250.626273 # Core power per rank (mW) -system.physmem_0.totalIdleTime 53271099000 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 16953500 # Time in different power states -system.physmem_0.memoryStateTime::REF 73680000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 51675337000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 569631000 # Time in different power states -system.physmem_0.memoryStateTime::ACT 74922500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 1027097500 # Time in different power states -system.physmem_1.actEnergy 3677100 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1950630 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 19663560 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 191767680.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 68393160 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 9924480 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 510653310 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 251520000 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 12393371550 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 13451137230 # Total energy per rank (pJ) -system.physmem_1.averagePower 251.716611 # Core power per rank (mW) -system.physmem_1.totalIdleTime 53261175500 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 18732000 # Time in different power states -system.physmem_1.memoryStateTime::REF 81534000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 51486455000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 654968250 # Time in different power states -system.physmem_1.memoryStateTime::ACT 76126500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 1119805750 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 11450652 # Number of BP lookups -system.cpu.branchPred.condPredicted 8210942 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 765019 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 6085116 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5320742 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 87.438629 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1176677 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 216 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 26315 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 24242 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 2073 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 983 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20415218 # DTB read hits -system.cpu.dtb.read_misses 43383 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 20458601 # DTB read accesses -system.cpu.dtb.write_hits 6579912 # DTB write hits -system.cpu.dtb.write_misses 276 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 6580188 # DTB write accesses -system.cpu.dtb.data_hits 26995130 # DTB hits -system.cpu.dtb.data_misses 43659 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 27038789 # DTB accesses -system.cpu.itb.fetch_hits 22968644 # ITB hits -system.cpu.itb.fetch_misses 90 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 22968734 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 53437621500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 106875243 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 91903089 # Number of instructions committed -system.cpu.committedOps 91903089 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2191333 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.162912 # CPI: cycles per instruction -system.cpu.ipc 0.859910 # IPC: instructions per cycle -system.cpu.op_class_0::No_OpClass 7723353 8.40% 8.40% # Class of committed instruction -system.cpu.op_class_0::IntAlu 51001454 55.49% 63.90% # Class of committed instruction -system.cpu.op_class_0::IntMult 458252 0.50% 64.40% # Class of committed instruction -system.cpu.op_class_0::IntDiv 0 0.00% 64.40% # Class of committed instruction -system.cpu.op_class_0::FloatAdd 2732553 2.97% 67.37% # Class of committed instruction -system.cpu.op_class_0::FloatCmp 104605 0.11% 67.48% # Class of committed instruction -system.cpu.op_class_0::FloatCvt 2333953 2.54% 70.02% # Class of committed instruction -system.cpu.op_class_0::FloatMult 296445 0.32% 70.35% # Class of committed instruction -system.cpu.op_class_0::FloatMultAcc 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::FloatDiv 754822 0.82% 71.17% # Class of committed instruction -system.cpu.op_class_0::FloatMisc 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::FloatSqrt 318 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::SimdAdd 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::SimdAddAcc 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::SimdAlu 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::SimdCmp 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::SimdCvt 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::SimdMisc 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::SimdMult 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::SimdMultAcc 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::SimdShift 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::SimdShiftAcc 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::SimdSqrt 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAdd 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAlu 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCmp 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCvt 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::SimdFloatDiv 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMisc 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMult 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 71.17% # Class of committed instruction -system.cpu.op_class_0::MemRead 19433628 21.15% 92.31% # Class of committed instruction -system.cpu.op_class_0::MemWrite 6424338 6.99% 99.30% # Class of committed instruction -system.cpu.op_class_0::FloatMemRead 562580 0.61% 99.92% # Class of committed instruction -system.cpu.op_class_0::FloatMemWrite 76788 0.08% 100.00% # Class of committed instruction -system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 91903089 # Class of committed instruction -system.cpu.tickCycles 103792204 # Number of cycles that the object actually ticked -system.cpu.idleCycles 3083039 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.tagsinuse 1447.203649 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26572187 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2231 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11910.437920 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1447.203649 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.353321 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.353321 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 2074 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 44 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 228 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 405 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1379 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.506348 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 53153435 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 53153435 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 20074003 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20074003 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6498184 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6498184 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 26572187 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26572187 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26572187 # number of overall hits -system.cpu.dcache.overall_hits::total 26572187 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 496 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 496 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2919 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2919 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3415 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3415 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3415 # number of overall misses -system.cpu.dcache.overall_misses::total 3415 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 58822000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 58822000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 274731500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 274731500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 333553500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 333553500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 333553500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 333553500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20074499 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20074499 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 26575602 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 26575602 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 26575602 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 26575602 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000025 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000025 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000449 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000449 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000129 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000129 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000129 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000129 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 118592.741935 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 118592.741935 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 94118.362453 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 94118.362453 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 97673.060029 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 97673.060029 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 97673.060029 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 97673.060029 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 107 # number of writebacks -system.cpu.dcache.writebacks::total 107 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 8 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1176 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1176 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1184 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1184 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1184 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1184 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 488 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 488 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1743 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1743 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2231 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2231 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2231 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2231 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 57888500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 57888500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 165966000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 165966000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 223854500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 223854500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 223854500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 223854500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000268 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000268 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 118623.975410 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 118623.975410 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 95218.588640 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 95218.588640 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 100338.189153 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 100338.189153 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 100338.189153 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 100338.189153 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 13865 # number of replacements -system.cpu.icache.tags.tagsinuse 1642.239495 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22952813 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 15830 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1449.956601 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1642.239495 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.801875 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.801875 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1965 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 146 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 670 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 150 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 947 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.959473 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 45953118 # Number of tag accesses -system.cpu.icache.tags.data_accesses 45953118 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 22952813 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22952813 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22952813 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22952813 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22952813 # number of overall hits -system.cpu.icache.overall_hits::total 22952813 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 15831 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 15831 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 15831 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 15831 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 15831 # number of overall misses -system.cpu.icache.overall_misses::total 15831 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 456439000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 456439000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 456439000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 456439000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 456439000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 456439000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22968644 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22968644 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22968644 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22968644 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22968644 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22968644 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000689 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000689 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000689 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000689 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000689 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000689 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28831.975238 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 28831.975238 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 28831.975238 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 28831.975238 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 28831.975238 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 28831.975238 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 13865 # number of writebacks -system.cpu.icache.writebacks::total 13865 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15831 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 15831 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 15831 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 15831 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 15831 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 15831 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 440609000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 440609000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 440609000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 440609000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 440609000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 440609000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000689 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000689 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000689 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000689 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000689 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000689 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27832.038406 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27832.038406 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27832.038406 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 27832.038406 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27832.038406 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 27832.038406 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3574.446973 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 26761 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 5322 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 5.028373 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2101.836656 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1472.610316 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064143 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.044941 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.109083 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 5322 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 920 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 569 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3605 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.162415 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 261986 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 261986 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 107 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 107 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 13865 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 13865 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 12660 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 12660 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 53 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 53 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 12660 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 79 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 12739 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 12660 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 79 # number of overall hits -system.cpu.l2cache.overall_hits::total 12739 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 1717 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 1717 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3170 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 3170 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 435 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 435 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3170 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 2152 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 5322 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3170 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2152 # number of overall misses -system.cpu.l2cache.overall_misses::total 5322 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 163078000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 163078000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 283932500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 283932500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 56594000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 56594000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 283932500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 219672000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 503604500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 283932500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 219672000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 503604500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 107 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 107 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 13865 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 13865 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1743 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1743 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15830 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 15830 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 488 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 488 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 15830 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2231 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 18061 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 15830 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2231 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 18061 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985083 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.985083 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.200253 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.200253 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.891393 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.891393 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.200253 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.964590 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.294668 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.200253 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.964590 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.294668 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 94978.450786 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 94978.450786 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89568.611987 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89568.611987 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 130101.149425 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 130101.149425 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89568.611987 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 102078.066914 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 94626.925968 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89568.611987 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 102078.066914 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 94626.925968 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1717 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1717 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3170 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3170 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 435 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 435 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3170 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2152 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5322 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3170 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2152 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5322 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 145908000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 145908000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 252232500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 252232500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 52244000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 52244000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 252232500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 198152000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 450384500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 252232500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 198152000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 450384500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985083 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985083 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.200253 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.200253 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.891393 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.891393 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200253 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964590 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.294668 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200253 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964590 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.294668 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 84978.450786 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 84978.450786 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79568.611987 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79568.611987 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 120101.149425 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 120101.149425 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79568.611987 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 92078.066914 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84626.925968 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79568.611987 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 92078.066914 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84626.925968 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 32083 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 14022 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 16318 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 107 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 13865 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 50 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1743 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1743 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 15830 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 488 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45525 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4619 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 50144 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1900480 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149632 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2050112 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 18061 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 18061 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 18061 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 30013500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 23745000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3346500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 5322 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 53437621500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 3605 # Transaction distribution -system.membus.trans_dist::ReadExReq 1717 # Transaction distribution -system.membus.trans_dist::ReadExResp 1717 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3605 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10644 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10644 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 340608 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 340608 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 5322 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5322 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5322 # Request fanout histogram -system.membus.reqLayer0.occupancy 6424500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 28175000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,825 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=DerivO3CPU -children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload -LFSTSize=1024 -LQEntries=32 -LSQCheckLoads=true -LSQDepCheckShift=4 -SQEntries=32 -SSITSize=1024 -activity=0 -backComSize=5 -branchPred=system.cpu.branchPred -cachePorts=200 -checker=Null -clk_domain=system.cpu_clk_domain -commitToDecodeDelay=1 -commitToFetchDelay=1 -commitToIEWDelay=1 -commitToRenameDelay=1 -commitWidth=8 -cpu_id=0 -decodeToFetchDelay=1 -decodeToRenameDelay=1 -decodeWidth=8 -default_p_state=UNDEFINED -dispatchWidth=8 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -fetchBufferSize=64 -fetchQueueSize=32 -fetchToDecodeDelay=1 -fetchTrapLatency=1 -fetchWidth=8 -forwardComSize=5 -fuPool=system.cpu.fuPool -function_trace=false -function_trace_start=0 -iewToCommitDelay=1 -iewToDecodeDelay=1 -iewToFetchDelay=1 -iewToRenameDelay=1 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -issueToExecuteDelay=1 -issueWidth=8 -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -needsTSO=false -numIQEntries=64 -numPhysCCRegs=0 -numPhysFloatRegs=256 -numPhysIntRegs=256 -numROBEntries=192 -numRobs=1 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -renameToDecodeDelay=1 -renameToFetchDelay=1 -renameToIEWDelay=2 -renameToROBDelay=1 -renameWidth=8 -simpoint_start_insts= -smtCommitPolicy=RoundRobin -smtFetchPolicy=SingleThread -smtIQPolicy=Partitioned -smtIQThreshold=100 -smtLSQPolicy=Partitioned -smtLSQThreshold=100 -smtNumFetchingThreads=1 -smtROBPolicy=Partitioned -smtROBThreshold=100 -socket_id=0 -squashWidth=8 -store_set_clear_period=250000 -switched_out=false -system=system -tracer=system.cpu.tracer -trapLatency=13 -wbWidth=8 -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.branchPred] -type=TournamentBP -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -indirectHashGHR=true -indirectHashTargets=true -indirectPathLength=3 -indirectSets=256 -indirectTagSize=16 -indirectWays=2 -instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 -useIndirect=true - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.fuPool] -type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 -eventq_index=0 - -[system.cpu.fuPool.FUList0] -type=FUDesc -children=opList -count=6 -eventq_index=0 -opList=system.cpu.fuPool.FUList0.opList - -[system.cpu.fuPool.FUList0.opList] -type=OpDesc -eventq_index=0 -opClass=IntAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList1] -type=FUDesc -children=opList0 opList1 -count=2 -eventq_index=0 -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -eventq_index=0 -opClass=IntMult -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -eventq_index=0 -opClass=IntDiv -opLat=20 -pipelined=false - -[system.cpu.fuPool.FUList2] -type=FUDesc -children=opList0 opList1 opList2 -count=4 -eventq_index=0 -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -eventq_index=0 -opClass=FloatAdd -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -eventq_index=0 -opClass=FloatCmp -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -eventq_index=0 -opClass=FloatCvt -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList3] -type=FUDesc -children=opList0 opList1 opList2 -count=2 -eventq_index=0 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -eventq_index=0 -opClass=FloatMult -opLat=4 -pipelined=true - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -eventq_index=0 -opClass=FloatDiv -opLat=12 -pipelined=false - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -eventq_index=0 -opClass=FloatSqrt -opLat=24 -pipelined=false - -[system.cpu.fuPool.FUList4] -type=FUDesc -children=opList -count=0 -eventq_index=0 -opList=system.cpu.fuPool.FUList4.opList - -[system.cpu.fuPool.FUList4.opList] -type=OpDesc -eventq_index=0 -opClass=MemRead -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5] -type=FUDesc -children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 -count=4 -eventq_index=0 -opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 - -[system.cpu.fuPool.FUList5.opList00] -type=OpDesc -eventq_index=0 -opClass=SimdAdd -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList01] -type=OpDesc -eventq_index=0 -opClass=SimdAddAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList02] -type=OpDesc -eventq_index=0 -opClass=SimdAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList03] -type=OpDesc -eventq_index=0 -opClass=SimdCmp -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList04] -type=OpDesc -eventq_index=0 -opClass=SimdCvt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList05] -type=OpDesc -eventq_index=0 -opClass=SimdMisc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList06] -type=OpDesc -eventq_index=0 -opClass=SimdMult -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList07] -type=OpDesc -eventq_index=0 -opClass=SimdMultAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList08] -type=OpDesc -eventq_index=0 -opClass=SimdShift -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList09] -type=OpDesc -eventq_index=0 -opClass=SimdShiftAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList10] -type=OpDesc -eventq_index=0 -opClass=SimdSqrt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList11] -type=OpDesc -eventq_index=0 -opClass=SimdFloatAdd -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList12] -type=OpDesc -eventq_index=0 -opClass=SimdFloatAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList13] -type=OpDesc -eventq_index=0 -opClass=SimdFloatCmp -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList14] -type=OpDesc -eventq_index=0 -opClass=SimdFloatCvt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList15] -type=OpDesc -eventq_index=0 -opClass=SimdFloatDiv -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList16] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMisc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList17] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMult -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList18] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMultAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList19] -type=OpDesc -eventq_index=0 -opClass=SimdFloatSqrt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList6] -type=FUDesc -children=opList -count=0 -eventq_index=0 -opList=system.cpu.fuPool.FUList6.opList - -[system.cpu.fuPool.FUList6.opList] -type=OpDesc -eventq_index=0 -opClass=MemWrite -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList7] -type=FUDesc -children=opList0 opList1 -count=4 -eventq_index=0 -opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -eventq_index=0 -opClass=MemRead -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList7.opList1] -type=OpDesc -eventq_index=0 -opClass=MemWrite -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList8] -type=FUDesc -children=opList -count=1 -eventq_index=0 -opList=system.cpu.fuPool.FUList8.opList - -[system.cpu.fuPool.FUList8.opList] -type=OpDesc -eventq_index=0 -opClass=IprAccess -opLat=3 -pipelined=false - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=twolf smred -cwd=build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/twolf -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=0:134217727:0:0:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=6000 -tXPDLL=0 -tXS=270000 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simerr --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simerr Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,7 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(1, ...) diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,29 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:19:45 -gem5 executing on e108600-lin, pid 28064 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/70.twolf/alpha/tru64/o3-timing - -Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sav -Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sv2 -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. - -TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 -Standard Cell Placement and Global Routing Program -Authors: Carl Sechen, Bill Swartz - Yale University - 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 - 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 - 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 - 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 - 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 - 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 -106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 21954917500 because target called exit() diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.out --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.out Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,276 +0,0 @@ - -TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 -Standard Cell Placement and Global Routing Program -Authors: Carl Sechen, Bill Swartz - Yale University - - -NOTE: Restart file .rs2 not used - -TimberWolf will perform a global route step -rowSep: 1.000000 -feedThruWidth: 4 - -****************** -BLOCK DATA -block:1 desire:85 -block:2 desire:85 -Total Desired Length: 170 -total cell length: 168 -total block length: 168 -block x-span:84 block y-span:78 -implicit feed thru range: -84 -Using default value of bin.penalty.control:1.000000 -numBins automatically set to:5 -binWidth = average_cell_width + 0 sigma= 17 -average_cell_width is:16 -standard deviation of cell length is:23.6305 -TimberWolfSC starting from the beginning - - - -THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645 -The number of nets with 1 pin is 4 -The number of nets with 2 pin is 9 -The number of nets with 3 pin is 0 -The number of nets with 4 pin is 2 -The number of nets with 5 pin is 0 -The number of nets with 6 pin is 0 -The number of nets with 7 pin is 0 -The number of nets with 8 pin is 0 -The number of nets with 9 pin is 0 -The number of nets with 10 pin or more is 0 - -New Cost Function: Initial Horizontal Cost:242 -New Cost Function: FEEDS:0 MISSING_ROWS:-46 - -bdxlen:86 bdylen:78 -l:0 t:78 r:86 b:0 - - - -THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645 - - - -THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44 - -The rand generator seed was at utemp() : 1 - - - tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000 - tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000 - tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000 - tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000 - - I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs - 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40 - 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46 - 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.3 0.0 0 46 - 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48 - 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46 - 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52 - 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50 - 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48 - 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48 - 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48 - 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50 - 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44 - 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50 - 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50 - 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46 - 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52 - 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50 - 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48 - 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48 - 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52 - 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52 - 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50 - 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48 - 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42 - 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52 - 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52 - 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50 - 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48 - 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50 - 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46 - 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48 - 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48 - 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52 - 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48 - 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48 - 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50 - 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52 - 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52 - 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48 - 40 251 8 741 104 159 0.0 0.8 0.5 36.3 47.5 0.0 0 48 - 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50 - 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50 - 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48 - 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52 - 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50 - 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52 - 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52 - 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48 - 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52 - 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52 - 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52 - 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46 - 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44 - 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50 - 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52 - 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48 - 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52 - 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50 - 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50 - 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52 - 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48 - 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48 - 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52 - 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52 - 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50 - 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52 - 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52 - 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52 - 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52 - 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52 - 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52 - 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52 - 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52 - 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52 - 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52 - 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52 - 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52 - 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50 - 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52 - 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52 - 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52 - 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50 - 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50 - 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52 - 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52 - 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52 - 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52 - 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52 - 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52 - 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52 - 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52 - 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52 - 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52 - 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52 - 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52 - 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52 - 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52 - 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52 - 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52 -100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52 -101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52 -102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52 -103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52 -104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52 -105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52 -106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52 -107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52 -108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52 -109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52 -110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52 -111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52 -112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52 -113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52 -114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52 -115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52 -116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52 -117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52 -118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52 -119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52 -120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52 -121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8 - -Initial Wiring Cost: 645 Final Wiring Cost: 732 -############## Percent Wire Cost Reduction: -13 - - -Initial Wire Length: 645 Final Wire Length: 732 -************** Percent Wire Length Reduction: -13 - - -Initial Horiz. Wire: 216 Final Horiz. Wire: 147 -$$$$$$$$$$$ Percent H-Wire Length Reduction: 32 - - -Initial Vert. Wire: 429 Final Vert. Wire: 585 -@@@@@@@@@@@ Percent V-Wire Length Reduction: -36 - -Before Feeds are Added: -BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET - 1 82 -20 - 2 86 -16 - -LONGEST Block is:2 Its length is:86 -BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET - 1 86 -16 - 2 86 -16 - -LONGEST Block is:1 Its length is:86 -Added: 1 feed-through cells - -Removed the cell overlaps --- Will do neighbor interchanges only now - -TOTAL INTERCONNECT LENGTH: 994 -OVERLAP PENALTY: 0 - -initialRowControl: 1.650 -finalRowControl: 0.300 -iter T Wire accept - 122 0.001 976 16% - 123 0.001 971 0% - 124 0.001 971 0% -Total Feed-Alignment Movement (Pass 1): 0 -Total Feed-Alignment Movement (Pass 2): 0 -Total Feed-Alignment Movement (Pass 3): 0 -Total Feed-Alignment Movement (Pass 4): 0 -Total Feed-Alignment Movement (Pass 5): 0 -Total Feed-Alignment Movement (Pass 6): 0 -Total Feed-Alignment Movement (Pass 7): 0 -Total Feed-Alignment Movement (Pass 8): 0 - -The rand generator seed was at globroute() : 987654321 - - -Total Number of Net Segments: 9 -Number of Switchable Net Segments: 0 - -Number of channels: 3 - - - -THIS IS THE ORIGINAL NUMBER OF TRACKS: 5 - - -no. of accepted flips: 0 -no. of attempted flips: 0 -THIS IS THE NUMBER OF TRACKS: 5 - - - -FINAL NUMBER OF ROUTING TRACKS: 5 - -MAX OF CHANNEL: 1 is: 0 -MAX OF CHANNEL: 2 is: 4 -MAX OF CHANNEL: 3 is: 1 -FINAL TOTAL INTERCONNECT LENGTH: 978 -FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978 -MAX NUMBER OF ATTEMPTED FLIPS PER T: 55 - - -cost_scale_factor:3.90616 - -Number of Feed Thrus: 0 -Number of Implicit Feed Thrus: 0 - -Statistics: -Number of Standard Cells: 10 -Number of Pads: 0 -Number of Nets: 15 -Number of Pins: 46 -Usage statistics not available diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.pin --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.pin Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,17 +0,0 @@ -$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0 -$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0 -B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0 -B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0 -B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0 -B7 3 ACOUNT_1 01#Z 17 26 2 -1 0 -B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0 -B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0 -B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0 -$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0 -$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0 -$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0 -$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0 -$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0 -$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0 -$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0 -$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0 diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.pl1 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.pl1 Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,11 +0,0 @@ -$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1 -$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1 -$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1 -ACOUNT_1 14 0 18 26 2 1 -twfeed1 18 0 22 26 0 1 -$COUNT_1/$FJK3_1 22 0 86 26 0 1 -$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2 -$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2 -$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2 -$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2 -$COUNT_1/$FJK3_2 22 52 86 78 0 2 diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.pl2 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.pl2 Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,2 +0,0 @@ -1 0 0 86 26 0 0 -2 0 52 86 78 0 0 diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.sav --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.sav Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,18 +0,0 @@ -0.009592 -121 -0 -1 -0.000000 -0.500000 -3.906156 -1 -1 1 2 37 13 -2 2 0 34 65 -3 2 2 63 65 -4 1 0 59 13 -5 1 2 32 13 -6 2 0 23 65 -7 1 2 12 13 -8 2 0 6 65 -9 1 0 70 13 -10 2 0 70 65 diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.sv2 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.sv2 Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,19 +0,0 @@ -0.001000 -123 -0 -2 -0.000000 -0.500000 -3.906156 -1 -1 1 2 16 13 -2 2 2 19 65 -3 2 2 14 65 -4 1 0 11 13 -5 1 2 6 13 -6 2 0 3 65 -7 1 0 2 13 -8 2 2 9 65 -9 1 0 50 13 -10 2 0 54 65 -11 1 0 84 13 diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.twf --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.twf Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,29 +0,0 @@ -net 1 -segment channel 2 - pin1 1 pin2 7 0 0 -net 2 -segment channel 3 -pin1 41 pin2 42 0 0 -segment channel 2 -pin1 12 pin2 3 0 0 -net 3 -segment channel 2 -pin1 35 pin2 36 0 0 -segment channel 2 -pin1 19 pin2 35 0 0 -net 4 -segment channel 2 - pin1 5 pin2 38 0 0 -net 5 -net 7 -segment channel 2 - pin1 14 pin2 43 0 0 -net 8 -segment channel 2 - pin1 23 pin2 17 0 0 -net 9 -net 11 -segment channel 2 - pin1 25 pin2 31 0 0 -net 14 -net 15 diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,1074 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.021955 # Number of seconds simulated -sim_ticks 21954917500 # Number of ticks simulated -final_tick 21954917500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 353144 # Simulator instruction rate (inst/s) -host_op_rate 353144 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 92103562 # Simulator tick rate (ticks/s) -host_mem_usage 259964 # Number of bytes of host memory used -host_seconds 238.37 # Real time elapsed on the host -sim_insts 84179709 # Number of instructions simulated -sim_ops 84179709 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 21954917500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 195904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 138560 # Number of bytes read from this memory -system.physmem.bytes_read::total 334464 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 195904 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 195904 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3061 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2165 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5226 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 8923012 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 6311115 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15234127 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8923012 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8923012 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8923012 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 6311115 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 15234127 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5226 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5226 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 334464 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 334464 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 469 # Per bank write bursts -system.physmem.perBankRdBursts::1 292 # Per bank write bursts -system.physmem.perBankRdBursts::2 302 # Per bank write bursts -system.physmem.perBankRdBursts::3 523 # Per bank write bursts -system.physmem.perBankRdBursts::4 220 # Per bank write bursts -system.physmem.perBankRdBursts::5 223 # Per bank write bursts -system.physmem.perBankRdBursts::6 218 # Per bank write bursts -system.physmem.perBankRdBursts::7 288 # Per bank write bursts -system.physmem.perBankRdBursts::8 239 # Per bank write bursts -system.physmem.perBankRdBursts::9 278 # Per bank write bursts -system.physmem.perBankRdBursts::10 249 # Per bank write bursts -system.physmem.perBankRdBursts::11 251 # Per bank write bursts -system.physmem.perBankRdBursts::12 395 # Per bank write bursts -system.physmem.perBankRdBursts::13 338 # Per bank write bursts -system.physmem.perBankRdBursts::14 492 # Per bank write bursts -system.physmem.perBankRdBursts::15 449 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 21954815500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5226 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3223 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1200 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 523 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 260 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 861 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 385.932636 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 229.340491 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 360.649518 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 261 30.31% 30.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 173 20.09% 50.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 93 10.80% 61.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 57 6.62% 67.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 37 4.30% 72.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 30 3.48% 75.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 47 5.46% 81.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 33 3.83% 84.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 130 15.10% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 861 # Bytes accessed per row activation -system.physmem.totQLat 128746000 # Total ticks spent queuing -system.physmem.totMemAccLat 226733500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 26130000 # Total ticks spent in databus transfers -system.physmem.avgQLat 24635.67 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 43385.67 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 15.23 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 15.23 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.12 # Data bus utilization in percentage -system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4356 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.35 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 4201074.53 # Average gap between requests -system.physmem.pageHitRate 83.35 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3034500 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1593900 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 18099900 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 118625520.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 48811380 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 6176640 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 312556080 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 154176960 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 5001436845 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 5664547785 # Total energy per rank (pJ) -system.physmem_0.averagePower 258.008156 # Core power per rank (mW) -system.physmem_0.totalIdleTime 21831003750 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 11536500 # Time in different power states -system.physmem_0.memoryStateTime::REF 50426000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 20744771750 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 401491250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 61308000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 685384000 # Time in different power states -system.physmem_1.actEnergy 3177300 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1673595 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 19213740 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 106332720.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 46621440 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 5256960 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 301076850 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 131936160 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 5018107080 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 5633395845 # Total energy per rank (pJ) -system.physmem_1.averagePower 256.589251 # Core power per rank (mW) -system.physmem_1.totalIdleTime 21838957750 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 9258500 # Time in different power states -system.physmem_1.memoryStateTime::REF 45178000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 20835144000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 343577000 # Time in different power states -system.physmem_1.memoryStateTime::ACT 61468500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 660291500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 21954917500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 16102182 # Number of BP lookups -system.cpu.branchPred.condPredicted 11688137 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 930988 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8963257 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7508303 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 83.767575 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1594537 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 466 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 29363 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 25724 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 3639 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 560 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 24064359 # DTB read hits -system.cpu.dtb.read_misses 206311 # DTB read misses -system.cpu.dtb.read_acv 4 # DTB read access violations -system.cpu.dtb.read_accesses 24270670 # DTB read accesses -system.cpu.dtb.write_hits 7168837 # DTB write hits -system.cpu.dtb.write_misses 1192 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 7170029 # DTB write accesses -system.cpu.dtb.data_hits 31233196 # DTB hits -system.cpu.dtb.data_misses 207503 # DTB misses -system.cpu.dtb.data_acv 4 # DTB access violations -system.cpu.dtb.data_accesses 31440699 # DTB accesses -system.cpu.itb.fetch_hits 15932695 # ITB hits -system.cpu.itb.fetch_misses 79 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 15932774 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 21954917500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 43909836 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 16643979 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 137979397 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16102182 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9128564 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 26000321 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1939876 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 155 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2307 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 15932695 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 367713 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 43616730 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.163451 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.433365 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 19436456 44.56% 44.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2618537 6.00% 50.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1330059 3.05% 53.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1934096 4.43% 58.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3001834 6.88% 64.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1292274 2.96% 67.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1355703 3.11% 71.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 886638 2.03% 73.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 11761133 26.96% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 43616730 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.366710 # Number of branch fetches per cycle -system.cpu.fetch.rate 3.142335 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 12867029 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8250930 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19434015 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2106147 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 958609 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2654207 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 11848 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 132149793 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 49699 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 958609 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13986200 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4658485 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 10631 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20305693 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3697112 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 128776944 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 70815 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2027533 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1361651 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 79521 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 94599397 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 167333600 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 159779432 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 7554167 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 26172036 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 950 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 946 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 8272242 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26904484 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8704450 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3461355 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1614052 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 111855473 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1918 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 99762246 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 119439 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 27677681 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 21095832 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1529 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 43616730 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.287247 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.099564 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11270720 25.84% 25.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 7659760 17.56% 43.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7470187 17.13% 60.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5700495 13.07% 73.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4466514 10.24% 83.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2981046 6.83% 90.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2041941 4.68% 95.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1170841 2.68% 98.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 855226 1.96% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 43616730 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 484010 20.07% 20.07% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 20.07% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 20.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 538 0.02% 20.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 20.10% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 34926 1.45% 21.54% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 12192 0.51% 22.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 22.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1012503 41.99% 64.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 64.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 64.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 64.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.04% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 682717 28.32% 92.36% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 160804 6.67% 99.03% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 21053 0.87% 99.90% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 2406 0.10% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 60662676 60.81% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 489936 0.49% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2847523 2.85% 64.15% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 115351 0.12% 64.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2443321 2.45% 66.72% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 314198 0.31% 67.03% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.03% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 765838 0.77% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24115562 24.17% 91.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7190219 7.21% 99.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 739060 0.74% 99.92% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 78236 0.08% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 99762246 # Type of FU issued -system.cpu.iq.rate 2.271979 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2411149 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.024169 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 229977416 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 129921960 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 89757276 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15694394 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9653681 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7189481 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 93785924 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 8387464 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1923320 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6908286 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11342 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 40947 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2203347 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 42864 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1503 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 958609 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3613912 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 479107 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 122779790 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 241415 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26904484 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 8704450 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1918 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 38391 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 434865 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 40947 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 531949 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 502384 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1034333 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 98436741 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 24271214 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1325505 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10922399 # number of nop insts executed -system.cpu.iew.exec_refs 31441282 # number of memory reference insts executed -system.cpu.iew.exec_branches 12471732 # Number of branches executed -system.cpu.iew.exec_stores 7170068 # Number of stores executed -system.cpu.iew.exec_rate 2.241792 # Inst execution rate -system.cpu.iew.wb_sent 97645487 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 96946757 # cumulative count of insts written-back -system.cpu.iew.wb_producers 66976137 # num instructions producing a value -system.cpu.iew.wb_consumers 94960144 # num instructions consuming a value -system.cpu.iew.wb_rate 2.207860 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.705308 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 30878503 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 919659 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 39122931 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.349084 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.919383 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 14724541 37.64% 37.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8532800 21.81% 59.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3880104 9.92% 69.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 1909784 4.88% 74.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1376640 3.52% 77.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1034511 2.64% 80.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 692868 1.77% 82.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 729092 1.86% 84.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6242591 15.96% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 39122931 # Number of insts commited each cycle -system.cpu.commit.committedInsts 91903055 # Number of instructions committed -system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 26497301 # Number of memory references committed -system.cpu.commit.loads 19996198 # Number of loads committed -system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 10240685 # Number of branches committed -system.cpu.commit.fp_insts 6862061 # Number of committed floating point instructions. -system.cpu.commit.int_insts 79581076 # Number of committed integer instructions. -system.cpu.commit.function_calls 1029620 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 7723353 8.40% 8.40% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 51001453 55.49% 63.90% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 458252 0.50% 64.40% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 64.40% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 2732553 2.97% 67.37% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 104605 0.11% 67.48% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 2333953 2.54% 70.02% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 296445 0.32% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 754822 0.82% 71.17% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 71.17% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 318 0.00% 71.17% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 71.17% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 71.17% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 71.17% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 71.17% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 71.17% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 71.17% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 71.17% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 71.17% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 71.17% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 71.17% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 71.17% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 71.17% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 71.17% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 71.17% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 71.17% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 71.17% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 71.17% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 71.17% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.17% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.17% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 19433618 21.15% 92.31% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 6424318 6.99% 99.30% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemRead 562580 0.61% 99.92% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemWrite 76785 0.08% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 91903055 # Class of committed instruction -system.cpu.commit.bw_lim_events 6242591 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 155660858 # The number of ROB reads -system.cpu.rob.rob_writes 250112359 # The number of ROB writes -system.cpu.timesIdled 4774 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 293106 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 84179709 # Number of Instructions Simulated -system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.521620 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.521620 # CPI: Total CPI of All Threads -system.cpu.ipc 1.917104 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.917104 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 133010551 # number of integer regfile reads -system.cpu.int_regfile_writes 72904644 # number of integer regfile writes -system.cpu.fp_regfile_reads 6263409 # number of floating regfile reads -system.cpu.fp_regfile_writes 6178123 # number of floating regfile writes -system.cpu.misc_regfile_reads 719113 # number of misc regfile reads -system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 21954917500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 158 # number of replacements -system.cpu.dcache.tags.tagsinuse 1457.034872 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 28588531 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2245 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12734.312249 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1457.034872 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.355721 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.355721 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 2087 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 543 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1389 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.509521 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 57198427 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 57198427 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 21954917500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 22095438 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22095438 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6492623 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6492623 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 470 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 470 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 28588061 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28588061 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28588061 # number of overall hits -system.cpu.dcache.overall_hits::total 28588061 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1079 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1079 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8480 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8480 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9559 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9559 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9559 # number of overall misses -system.cpu.dcache.overall_misses::total 9559 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 87318000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 87318000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 649645257 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 649645257 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 106000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 106000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 736963257 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 736963257 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 736963257 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 736963257 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22096517 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22096517 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 471 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 471 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28597620 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28597620 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28597620 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28597620 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000049 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000049 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001304 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001304 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002123 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002123 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000334 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000334 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000334 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000334 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 80924.930491 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 80924.930491 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76609.110495 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 76609.110495 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 106000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 106000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 77096.271263 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 77096.271263 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 77096.271263 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 77096.271263 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 43101 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 174 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 350 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 3 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 123.145714 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 58 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 108 # number of writebacks -system.cpu.dcache.writebacks::total 108 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 564 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 564 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6751 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6751 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7315 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7315 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7315 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7315 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 515 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 515 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1729 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1729 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2244 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2244 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2244 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2244 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 47711000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 47711000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 177283495 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 177283495 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 105000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 105000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 224994495 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 224994495 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 224994495 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 224994495 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000266 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000266 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.002123 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.002123 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000078 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000078 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000078 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000078 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 92642.718447 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 92642.718447 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 102535.277617 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 102535.277617 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 105000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 105000 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 100264.926471 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 100264.926471 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 100264.926471 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 100264.926471 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 21954917500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 9511 # number of replacements -system.cpu.icache.tags.tagsinuse 1600.395362 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 15918262 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 11449 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1390.362652 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1600.395362 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.781443 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.781443 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1938 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 181 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 752 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 944 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.946289 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 31876835 # Number of tag accesses -system.cpu.icache.tags.data_accesses 31876835 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 21954917500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 15918262 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 15918262 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 15918262 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 15918262 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 15918262 # number of overall hits -system.cpu.icache.overall_hits::total 15918262 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 14431 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 14431 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 14431 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 14431 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 14431 # number of overall misses -system.cpu.icache.overall_misses::total 14431 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 508617000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 508617000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 508617000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 508617000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 508617000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 508617000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 15932693 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 15932693 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 15932693 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 15932693 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 15932693 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 15932693 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000906 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000906 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000906 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000906 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000906 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000906 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35244.750884 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 35244.750884 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35244.750884 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 35244.750884 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35244.750884 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 35244.750884 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 485 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 80.833333 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 9511 # number of writebacks -system.cpu.icache.writebacks::total 9511 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2981 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2981 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2981 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2981 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2981 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2981 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11450 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 11450 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 11450 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 11450 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 11450 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 11450 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 378748000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 378748000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 378748000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 378748000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 378748000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 378748000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000719 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000719 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000719 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000719 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000719 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000719 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33078.427948 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 33078.427948 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33078.427948 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 33078.427948 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33078.427948 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 33078.427948 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 21954917500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3489.228607 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 18138 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 5226 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 3.470723 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2006.844021 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1482.384585 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061244 # Average percentage of cache occupancy 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-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 21954917500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 108 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 108 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 9511 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 9511 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8389 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 8389 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 54 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 54 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 8389 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 80 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 8469 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 8389 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 80 # number of overall hits -system.cpu.l2cache.overall_hits::total 8469 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 1703 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 1703 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3061 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 3061 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 462 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 462 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3061 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 2165 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 5226 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3061 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2165 # number of overall misses -system.cpu.l2cache.overall_misses::total 5226 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 174274000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 174274000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 273178000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 273178000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 46458500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 46458500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 273178000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 220732500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 493910500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 273178000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 220732500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 493910500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 108 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 108 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 9511 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 9511 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1729 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1729 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 11450 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 11450 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 516 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 516 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 11450 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2245 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 13695 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 11450 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2245 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 13695 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.984962 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.984962 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.267336 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.267336 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.895349 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.895349 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.267336 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.964365 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.381599 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.267336 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.964365 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.381599 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 102333.529066 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 102333.529066 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89244.691277 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89244.691277 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 100559.523810 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 100559.523810 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89244.691277 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 101954.965358 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 94510.237275 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89244.691277 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 101954.965358 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 94510.237275 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1703 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1703 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3061 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3061 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 462 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 462 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3061 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2165 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5226 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3061 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2165 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5226 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 157244000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 157244000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 242568000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 242568000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 41838500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 41838500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 242568000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 199082500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 441650500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 242568000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 199082500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 441650500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.984962 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.984962 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.267336 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.267336 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.895349 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.895349 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.267336 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964365 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.381599 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.267336 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964365 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.381599 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 92333.529066 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 92333.529066 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79244.691277 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79244.691277 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 90559.523810 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 90559.523810 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79244.691277 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 91954.965358 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84510.237275 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79244.691277 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 91954.965358 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84510.237275 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 23364 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 9669 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 21954917500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 11965 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 108 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 9511 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 50 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1729 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1729 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 11450 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 516 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 32410 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4648 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 37058 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1341440 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150592 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 1492032 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 13695 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 13695 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 13695 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 21301000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 17173500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3367500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 5226 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 21954917500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 3523 # Transaction distribution -system.membus.trans_dist::ReadExReq 1703 # Transaction distribution -system.membus.trans_dist::ReadExResp 1703 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3523 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10452 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10452 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334464 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 334464 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 5226 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5226 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5226 # Request fanout histogram -system.membus.reqLayer0.occupancy 6271000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 27424000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,1442 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=true -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=LinuxAlphaSystem -children=bridge clk_domain cpu0 cpu1 cpu_clk_domain disk0 disk2 dvfs_handler intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami voltage_domain -boot_cpu_frequency=500 -boot_osflags=root=/dev/hda1 console=ttyS0 -cache_line_size=64 -clk_domain=system.clk_domain -console=/arm/projectscratch/randd/systems/dist/binaries/console -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=atomic -mem_ranges=0:134217727 -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pal=/arm/projectscratch/randd/systems/dist/binaries/ts_osfpal -power_model=Null -readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh -symbolfile= -system_rev=1024 -system_type=34 -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.bridge] -type=Bridge -clk_domain=system.clk_domain -default_p_state=UNDEFINED -delay=50000 -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -ranges=8796093022208:18446744073709551615 -req_size=16 -resp_size=16 -master=system.iobus.slave[0] -slave=system.membus.master[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu0] -type=AtomicSimpleCPU -children=dcache dtb icache interrupts isa itb tracer -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu0.dtb -eventq_index=0 -fastmem=false -function_trace=false -function_trace_start=0 -interrupts=system.cpu0.interrupts -isa=system.cpu0.isa -itb=system.cpu0.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -simulate_data_stalls=false -simulate_inst_stalls=false -socket_id=0 -switched_out=false -system=system -tracer=system.cpu0.tracer -width=1 -workload= -dcache_port=system.cpu0.dcache.cpu_side -icache_port=system.cpu0.icache.cpu_side - -[system.cpu0.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=4 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu0.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu0.dcache_port -mem_side=system.toL2Bus.slave[1] - -[system.cpu0.dcache.tags] -type=LRU -assoc=4 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu0.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu0.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=1 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu0.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu0.icache_port -mem_side=system.toL2Bus.slave[0] - -[system.cpu0.icache.tags] -type=LRU -assoc=1 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu0.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu0.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu0.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu0.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu1] -type=AtomicSimpleCPU -children=dcache dtb icache interrupts isa itb tracer -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=1 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu1.dtb -eventq_index=0 -fastmem=false -function_trace=false -function_trace_start=0 -interrupts=system.cpu1.interrupts -isa=system.cpu1.isa -itb=system.cpu1.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -simulate_data_stalls=false -simulate_inst_stalls=false -socket_id=0 -switched_out=false -system=system -tracer=system.cpu1.tracer -width=1 -workload= -dcache_port=system.cpu1.dcache.cpu_side -icache_port=system.cpu1.icache.cpu_side - -[system.cpu1.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=4 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu1.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu1.dcache_port -mem_side=system.toL2Bus.slave[3] - -[system.cpu1.dcache.tags] -type=LRU -assoc=4 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu1.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu1.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=1 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu1.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu1.icache_port -mem_side=system.toL2Bus.slave[2] - -[system.cpu1.icache.tags] -type=LRU -assoc=1 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu1.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu1.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu1.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu1.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.disk0] -type=IdeDisk -children=image -delay=1000000 -driveID=master -eventq_index=0 -image=system.disk0.image - -[system.disk0.image] -type=CowDiskImage -children=child -child=system.disk0.image.child -eventq_index=0 -image_file= -read_only=false -table_size=65536 - -[system.disk0.image.child] -type=RawDiskImage -eventq_index=0 -image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img -read_only=true - -[system.disk2] -type=IdeDisk -children=image -delay=1000000 -driveID=master -eventq_index=0 -image=system.disk2.image - -[system.disk2.image] -type=CowDiskImage -children=child -child=system.disk2.image.child -eventq_index=0 -image_file= -read_only=false -table_size=65536 - -[system.disk2.image.child] -type=RawDiskImage -eventq_index=0 -image_file=/arm/projectscratch/randd/systems/dist/disks/linux-bigswap2.img -read_only=true - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.intrctrl] -type=IntrControl -eventq_index=0 -sys=system - -[system.iobus] -type=NoncoherentXBar -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=1 -frontend_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -response_latency=2 -use_default_range=false -width=16 -master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side -slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma - -[system.iocache] -type=Cache -children=tags -addr_ranges=0:134217727 -assoc=8 -clk_domain=system.clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=50 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=50 -sequential_access=false -size=1024 -system=system -tags=system.iocache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.iobus.master[27] -mem_side=system.membus.slave[2] - -[system.iocache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=50 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=1024 - -[system.l2c] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=4194304 -system=system -tags=system.l2c.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.l2c.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=4194304 - -[system.membus] -type=CoherentXBar -children=badaddr_responder snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.physmem.port -slave=system.system_port system.l2c.mem_side system.iocache.mem_side - -[system.membus.badaddr_responder] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=0 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=true -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.membus.default - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=0:134217727 -port=system.membus.master[1] - -[system.simple_disk] -type=SimpleDisk -children=disk -disk=system.simple_disk.disk -eventq_index=0 -system=system - -[system.simple_disk.disk] -type=RawDiskImage -eventq_index=0 -image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img -read_only=true - -[system.terminal] -type=Terminal -eventq_index=0 -intr_control=system.intrctrl -number=0 -output=true -port=3456 - -[system.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.l2c.cpu_side -slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side - -[system.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.tsunami] -type=Tsunami -children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip uart -eventq_index=0 -intrctrl=system.intrctrl -system=system - -[system.tsunami.backdoor] -type=AlphaBackdoor -clk_domain=system.clk_domain -cpu=system.cpu0 -default_p_state=UNDEFINED -disk=system.simple_disk -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804682956800 -pio_latency=100000 -platform=system.tsunami -power_model=Null -system=system -terminal=system.terminal -pio=system.iobus.master[24] - -[system.tsunami.cchip] -type=TsunamiCChip -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8803072344064 -pio_latency=100000 -power_model=Null -system=system -tsunami=system.tsunami -pio=system.iobus.master[0] - -[system.tsunami.ethernet] -type=NSGigE -BAR0=1 -BAR0LegacyIO=false -BAR0Size=256 -BAR1=0 -BAR1LegacyIO=false -BAR1Size=4096 -BAR2=0 -BAR2LegacyIO=false -BAR2Size=0 -BAR3=0 -BAR3LegacyIO=false -BAR3Size=0 -BAR4=0 -BAR4LegacyIO=false -BAR4Size=0 -BAR5=0 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=2 -Command=0 -DeviceID=34 -ExpansionROM=0 -HeaderType=0 -InterruptLine=30 -InterruptPin=1 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=52 -MinimumGrant=176 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=0 -Revision=0 -Status=656 -SubClassCode=0 -SubsystemID=0 -SubsystemVendorID=0 -VendorID=4107 -clk_domain=system.clk_domain -config_latency=20000 -default_p_state=UNDEFINED -dma_data_free=false -dma_desc_free=false -dma_no_allocate=true -dma_read_delay=0 -dma_read_factor=0 -dma_write_delay=0 -dma_write_factor=0 -eventq_index=0 -hardware_address=00:90:00:00:00:01 -host=system.tsunami.pchip -intr_delay=10000000 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_bus=0 -pci_dev=1 -pci_func=0 -pio_latency=30000 -power_model=Null -rss=false -rx_delay=1000000 -rx_fifo_size=524288 -rx_filter=true -rx_thread=false -system=system -tx_delay=1000000 -tx_fifo_size=524288 -tx_thread=false -dma=system.iobus.slave[2] -pio=system.iobus.master[26] - -[system.tsunami.fake_OROM] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8796093677568 -pio_latency=100000 -pio_size=393216 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[8] - -[system.tsunami.fake_ata0] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848432 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[19] - -[system.tsunami.fake_ata1] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848304 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[20] - -[system.tsunami.fake_pnp_addr] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848569 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[9] - -[system.tsunami.fake_pnp_read0] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848451 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[11] - -[system.tsunami.fake_pnp_read1] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848515 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[12] - -[system.tsunami.fake_pnp_read2] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848579 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[13] - -[system.tsunami.fake_pnp_read3] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848643 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[14] - -[system.tsunami.fake_pnp_read4] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848707 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[15] - -[system.tsunami.fake_pnp_read5] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848771 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[16] - -[system.tsunami.fake_pnp_read6] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848835 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[17] - -[system.tsunami.fake_pnp_read7] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848899 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[18] - -[system.tsunami.fake_pnp_write] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615850617 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[10] - -[system.tsunami.fake_ppc] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848891 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[7] - -[system.tsunami.fake_sm_chip] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848816 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[2] - -[system.tsunami.fake_uart1] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848696 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[3] - -[system.tsunami.fake_uart2] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848936 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[4] - -[system.tsunami.fake_uart3] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848680 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[5] - -[system.tsunami.fake_uart4] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848944 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[6] - -[system.tsunami.fb] -type=BadDevice -clk_domain=system.clk_domain -default_p_state=UNDEFINED -devicename=FrameBuffer -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848912 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[21] - -[system.tsunami.ide] -type=IdeController -BAR0=1 -BAR0LegacyIO=false -BAR0Size=8 -BAR1=1 -BAR1LegacyIO=false -BAR1Size=4 -BAR2=1 -BAR2LegacyIO=false -BAR2Size=8 -BAR3=1 -BAR3LegacyIO=false -BAR3Size=4 -BAR4=1 -BAR4LegacyIO=false -BAR4Size=16 -BAR5=1 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=1 -Command=0 -DeviceID=28945 -ExpansionROM=0 -HeaderType=0 -InterruptLine=31 -InterruptPin=1 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=0 -MinimumGrant=0 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=133 -Revision=0 -Status=640 -SubClassCode=1 -SubsystemID=0 -SubsystemVendorID=0 -VendorID=32902 -clk_domain=system.clk_domain -config_latency=20000 -ctrl_offset=0 -default_p_state=UNDEFINED -disks=system.disk0 system.disk2 -eventq_index=0 -host=system.tsunami.pchip -io_shift=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_bus=0 -pci_dev=0 -pci_func=0 -pio_latency=30000 -power_model=Null -system=system -dma=system.iobus.slave[1] -pio=system.iobus.master[25] - -[system.tsunami.io] -type=TsunamiIO -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -frequency=976562500 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615847936 -pio_latency=100000 -power_model=Null -system=system -time=Thu Jan 1 00:00:00 2009 -tsunami=system.tsunami -year_is_bcd=false -pio=system.iobus.master[22] - -[system.tsunami.pchip] -type=TsunamiPChip -clk_domain=system.clk_domain -conf_base=8804649402368 -conf_device_bits=8 -conf_size=16777216 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_dma_base=0 -pci_mem_base=8796093022208 -pci_pio_base=8804615847936 -pio_addr=8802535473152 -pio_latency=100000 -platform=system.tsunami -power_model=Null -system=system -tsunami=system.tsunami -pio=system.iobus.master[1] - -[system.tsunami.uart] -type=Uart8250 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848952 -pio_latency=100000 -platform=system.tsunami -power_model=Null -system=system -terminal=system.terminal -pio=system.iobus.master[23] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,6 +0,0 @@ -warn: Sockets disabled, not accepting terminal connections -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,16 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 19 2016 12:24:26 -gem5 executing on e108600-lin, pid 39599 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual - -Global frequency set at 1000000000000 ticks per second -info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -info: Entering event queue @ 0. Starting simulation... -info: Launching CPU 1 @ 97861500 -Exiting @ tick 1869357999000 because m5_exit instruction encountered diff -r 9c673b990d5d -r e1835e5846b9 tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,1059 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 1.869358 # Number of seconds simulated -sim_ticks 1869357999000 # Number of ticks simulated -final_tick 1869357999000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3011659 # Simulator instruction rate (inst/s) -host_op_rate 3011657 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 86613414800 # Simulator tick rate (ticks/s) -host_mem_usage 336084 # Number of bytes of host memory used -host_seconds 21.58 # Real time elapsed on the host -sim_insts 64999904 # Number of instructions simulated -sim_ops 64999904 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.inst 758272 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 66535744 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 106112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 766400 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 68167488 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 758272 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 106112 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 864384 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7837888 # Number of bytes written to this memory -system.physmem.bytes_written::total 7837888 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 11848 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 1039621 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1658 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 11975 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1065117 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 122467 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122467 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 405632 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 35592831 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 56764 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 409980 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 514 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 36465721 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 405632 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 56764 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 462396 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4192823 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4192823 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4192823 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 405632 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 35592831 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 56764 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 409980 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 514 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 40658545 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dtb.fetch_hits 0 # ITB hits -system.cpu0.dtb.fetch_misses 0 # ITB misses -system.cpu0.dtb.fetch_acv 0 # ITB acv -system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7758808 # DTB read hits -system.cpu0.dtb.read_misses 7155 # DTB read misses -system.cpu0.dtb.read_acv 152 # DTB read access violations -system.cpu0.dtb.read_accesses 531148 # DTB read accesses -system.cpu0.dtb.write_hits 4740251 # DTB write hits -system.cpu0.dtb.write_misses 732 # DTB write misses -system.cpu0.dtb.write_acv 102 # DTB write access violations -system.cpu0.dtb.write_accesses 201714 # DTB write accesses -system.cpu0.dtb.data_hits 12499059 # DTB hits -system.cpu0.dtb.data_misses 7887 # DTB misses -system.cpu0.dtb.data_acv 254 # DTB access violations -system.cpu0.dtb.data_accesses 732862 # DTB accesses -system.cpu0.itb.fetch_hits 3525726 # ITB hits -system.cpu0.itb.fetch_misses 3572 # ITB misses -system.cpu0.itb.fetch_acv 127 # ITB acv -system.cpu0.itb.fetch_accesses 3529298 # ITB accesses -system.cpu0.itb.read_hits 0 # DTB read hits -system.cpu0.itb.read_misses 0 # DTB read misses -system.cpu0.itb.read_acv 0 # DTB read access violations -system.cpu0.itb.read_accesses 0 # DTB read accesses -system.cpu0.itb.write_hits 0 # DTB write hits -system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.write_acv 0 # DTB write access violations -system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.data_hits 0 # DTB hits -system.cpu0.itb.data_misses 0 # DTB misses -system.cpu0.itb.data_acv 0 # DTB access violations -system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numPwrStateTransitions 13588 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 6794 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 271506704.857374 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 434955692.191892 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 6794 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 21000 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 6794 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 24741446199 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 1844616552801 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 3738722793 # number of cpu cycles simulated -system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6794 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 150435 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 51398 40.00% 40.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 243 0.19% 40.19% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1907 1.48% 41.67% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 514 0.40% 42.07% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 74446 57.93% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 128508 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 51050 48.97% 48.97% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 243 0.23% 49.20% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1907 1.83% 51.03% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 514 0.49% 51.52% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 50536 48.48% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 104250 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1853222732000 99.14% 99.14% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 20110000 0.00% 99.14% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 82001000 0.00% 99.14% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 57621500 0.00% 99.15% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 15975327000 0.85% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1869357791500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.993229 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.678828 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.811234 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 6 2.63% 2.63% # number of syscalls executed -system.cpu0.kern.syscall::3 20 8.77% 11.40% # number of syscalls executed -system.cpu0.kern.syscall::4 2 0.88% 12.28% # number of syscalls executed -system.cpu0.kern.syscall::6 32 14.04% 26.32% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.44% 26.75% # number of syscalls executed -system.cpu0.kern.syscall::15 1 0.44% 27.19% # number of syscalls executed -system.cpu0.kern.syscall::17 9 3.95% 31.14% # number of syscalls executed -system.cpu0.kern.syscall::19 8 3.51% 34.65% # number of syscalls executed -system.cpu0.kern.syscall::20 6 2.63% 37.28% # number of syscalls executed -system.cpu0.kern.syscall::23 2 0.88% 38.16% # number of syscalls executed -system.cpu0.kern.syscall::24 4 1.75% 39.91% # number of syscalls executed -system.cpu0.kern.syscall::33 7 3.07% 42.98% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.88% 43.86% # number of syscalls executed -system.cpu0.kern.syscall::45 37 16.23% 60.09% # number of syscalls executed -system.cpu0.kern.syscall::47 4 1.75% 61.84% # number of syscalls executed -system.cpu0.kern.syscall::48 8 3.51% 65.35% # number of syscalls executed -system.cpu0.kern.syscall::54 10 4.39% 69.74% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.44% 70.18% # number of syscalls executed -system.cpu0.kern.syscall::59 5 2.19% 72.37% # number of syscalls executed -system.cpu0.kern.syscall::71 30 13.16% 85.53% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.32% 86.84% # number of syscalls executed -system.cpu0.kern.syscall::74 8 3.51% 90.35% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.44% 90.79% # number of syscalls executed -system.cpu0.kern.syscall::90 2 0.88% 91.67% # number of syscalls executed -system.cpu0.kern.syscall::92 9 3.95% 95.61% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.88% 96.49% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.88% 97.37% # number of syscalls executed -system.cpu0.kern.syscall::132 2 0.88% 98.25% # number of syscalls executed -system.cpu0.kern.syscall::144 2 0.88% 99.12% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.88% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 228 # number of syscalls executed -system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 616 0.45% 0.45% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.45% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.46% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.46% # number of callpals executed -system.cpu0.kern.callpal::swpctx 2743 2.02% 2.47% # number of callpals executed -system.cpu0.kern.callpal::tbi 39 0.03% 2.50% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.01% 2.51% # number of callpals executed -system.cpu0.kern.callpal::swpipl 121668 89.51% 92.02% # number of callpals executed -system.cpu0.kern.callpal::rdps 6149 4.52% 96.54% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.54% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 96.54% # number of callpals executed -system.cpu0.kern.callpal::rdusp 7 0.01% 96.55% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.55% # number of callpals executed -system.cpu0.kern.callpal::rti 4175 3.07% 99.62% # number of callpals executed -system.cpu0.kern.callpal::callsys 369 0.27% 99.89% # number of callpals executed -system.cpu0.kern.callpal::imb 146 0.11% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 135929 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6593 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1173 # number of protection mode switches -system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1172 -system.cpu0.kern.mode_good::user 1173 -system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.177764 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.301957 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1868349163500 99.95% 99.95% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1008627000 0.05% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 2744 # number of times the context was actually changed -system.cpu0.committedInsts 49477745 # Number of instructions committed -system.cpu0.committedOps 49477745 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 46201705 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 197598 # Number of float alu accesses -system.cpu0.num_func_calls 1124633 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 6043603 # number of instructions that are conditional controls -system.cpu0.num_int_insts 46201705 # number of integer instructions -system.cpu0.num_fp_insts 197598 # number of float instructions -system.cpu0.num_int_register_reads 64003225 # number of times the integer registers were read -system.cpu0.num_int_register_writes 34834421 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 97440 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 98967 # number of times the floating registers were written -system.cpu0.num_mem_refs 12536107 # number of memory refs -system.cpu0.num_load_insts 7783754 # Number of load instructions -system.cpu0.num_store_insts 4752353 # Number of store instructions -system.cpu0.num_idle_cycles 3689239810.666409 # Number of idle cycles -system.cpu0.num_busy_cycles 49482982.333591 # Number of busy cycles -system.cpu0.not_idle_fraction 0.013235 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.986765 # Percentage of idle cycles -system.cpu0.Branches 7530826 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2589816 5.23% 5.23% # Class of executed instruction -system.cpu0.op_class::IntAlu 33436017 67.57% 72.80% # Class of executed instruction -system.cpu0.op_class::IntMult 50540 0.10% 72.90% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 72.90% # Class of executed instruction -system.cpu0.op_class::FloatAdd 27840 0.06% 72.96% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::FloatMultAcc 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::FloatDiv 2233 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::FloatMisc 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 72.96% # Class of executed instruction -system.cpu0.op_class::MemRead 7859946 15.88% 88.85% # Class of executed instruction -system.cpu0.op_class::MemWrite 4676411 9.45% 98.30% # Class of executed instruction -system.cpu0.op_class::FloatMemRead 85644 0.17% 98.47% # Class of executed instruction -system.cpu0.op_class::FloatMemWrite 81881 0.17% 98.63% # Class of executed instruction -system.cpu0.op_class::IprAccess 675558 1.37% 100.00% # Class of executed instruction -system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 49485886 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 1781367 # number of replacements -system.cpu0.dcache.tags.tagsinuse 506.187330 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 10705767 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1781879 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 6.008134 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.187330 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988647 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.988647 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 446 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 51822038 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 51822038 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 6068885 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6068885 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4360096 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4360096 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 127592 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 127592 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 132871 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 132871 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10428981 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10428981 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10428981 # number of overall hits -system.cpu0.dcache.overall_hits::total 10428981 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1560065 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1560065 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 236527 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 236527 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 12626 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 12626 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 6899 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 6899 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1796592 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1796592 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1796592 # number of overall misses -system.cpu0.dcache.overall_misses::total 1796592 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7628950 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7628950 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4596623 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4596623 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 140218 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 140218 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 139770 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 139770 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12225573 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12225573 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12225573 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12225573 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.204493 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.204493 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051457 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.051457 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.090046 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.090046 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.049360 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.049360 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.146954 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.146954 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.146954 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.146954 # miss rate for overall accesses -system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 633925 # number of writebacks -system.cpu0.dcache.writebacks::total 633925 # number of writebacks -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 618292 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.240644 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 48866947 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 618804 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 78.969992 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 9786048500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.240644 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998517 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998517 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 116 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 333 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 50104825 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 50104825 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 48866947 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 48866947 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 48866947 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 48866947 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 48866947 # number of overall hits -system.cpu0.icache.overall_hits::total 48866947 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 618939 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 618939 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 618939 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 618939 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 618939 # number of overall misses -system.cpu0.icache.overall_misses::total 618939 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 49485886 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 49485886 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 49485886 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 49485886 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 49485886 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 49485886 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012507 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.012507 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.012507 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.012507 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.012507 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.012507 # miss rate for overall accesses -system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 618292 # number of writebacks -system.cpu0.icache.writebacks::total 618292 # number of writebacks -system.cpu1.dtb.fetch_hits 0 # ITB hits -system.cpu1.dtb.fetch_misses 0 # ITB misses -system.cpu1.dtb.fetch_acv 0 # ITB acv -system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2831559 # DTB read hits -system.cpu1.dtb.read_misses 3191 # DTB read misses -system.cpu1.dtb.read_acv 58 # DTB read access violations -system.cpu1.dtb.read_accesses 198160 # DTB read accesses -system.cpu1.dtb.write_hits 2101673 # DTB write hits -system.cpu1.dtb.write_misses 412 # DTB write misses -system.cpu1.dtb.write_acv 55 # DTB write access violations -system.cpu1.dtb.write_accesses 90619 # DTB write accesses -system.cpu1.dtb.data_hits 4933232 # DTB hits -system.cpu1.dtb.data_misses 3603 # DTB misses -system.cpu1.dtb.data_acv 113 # DTB access violations -system.cpu1.dtb.data_accesses 288779 # DTB accesses -system.cpu1.itb.fetch_hits 1950883 # ITB hits -system.cpu1.itb.fetch_misses 1451 # ITB misses -system.cpu1.itb.fetch_acv 57 # ITB acv -system.cpu1.itb.fetch_accesses 1952334 # ITB accesses -system.cpu1.itb.read_hits 0 # DTB read hits -system.cpu1.itb.read_misses 0 # DTB read misses -system.cpu1.itb.read_acv 0 # DTB read access violations -system.cpu1.itb.read_accesses 0 # DTB read accesses -system.cpu1.itb.write_hits 0 # DTB write hits -system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.write_acv 0 # DTB write access violations -system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.data_hits 0 # DTB hits -system.cpu1.itb.data_misses 0 # DTB misses -system.cpu1.itb.data_acv 0 # DTB access violations -system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numPwrStateTransitions 5407 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 2704 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 688459933.247041 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 437290592.854298 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 2704 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 400000 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 976035500 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 2704 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 7762339500 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 1861595659500 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 3738296609 # number of cpu cycles simulated -system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2704 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 92290 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 31964 39.34% 39.34% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1906 2.35% 41.68% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 616 0.76% 42.44% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 46769 57.56% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 81255 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 30935 48.51% 48.51% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1906 2.99% 51.49% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 616 0.97% 52.46% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 30319 47.54% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 63776 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1856123501500 99.30% 99.30% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 81958000 0.00% 99.31% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 70736500 0.00% 99.31% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 12870743500 0.69% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1869146939500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.967808 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.648271 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.784887 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::2 2 2.04% 2.04% # number of syscalls executed -system.cpu1.kern.syscall::3 10 10.20% 12.24% # number of syscalls executed -system.cpu1.kern.syscall::4 2 2.04% 14.29% # number of syscalls executed -system.cpu1.kern.syscall::6 10 10.20% 24.49% # number of syscalls executed -system.cpu1.kern.syscall::17 6 6.12% 30.61% # number of syscalls executed -system.cpu1.kern.syscall::19 2 2.04% 32.65% # number of syscalls executed -system.cpu1.kern.syscall::23 2 2.04% 34.69% # number of syscalls executed -system.cpu1.kern.syscall::24 2 2.04% 36.73% # number of syscalls executed -system.cpu1.kern.syscall::33 4 4.08% 40.82% # number of syscalls executed -system.cpu1.kern.syscall::45 17 17.35% 58.16% # number of syscalls executed -system.cpu1.kern.syscall::47 2 2.04% 60.20% # number of syscalls executed -system.cpu1.kern.syscall::48 2 2.04% 62.24% # number of syscalls executed -system.cpu1.kern.syscall::59 2 2.04% 64.29% # number of syscalls executed -system.cpu1.kern.syscall::71 24 24.49% 88.78% # number of syscalls executed -system.cpu1.kern.syscall::74 8 8.16% 96.94% # number of syscalls executed -system.cpu1.kern.syscall::90 1 1.02% 97.96% # number of syscalls executed -system.cpu1.kern.syscall::132 2 2.04% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 98 # number of syscalls executed -system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 514 0.61% 0.61% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.61% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.61% # number of callpals executed -system.cpu1.kern.callpal::swpctx 2506 2.96% 3.58% # number of callpals executed -system.cpu1.kern.callpal::tbi 14 0.02% 3.59% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 3.60% # number of callpals executed -system.cpu1.kern.callpal::swpipl 74617 88.26% 91.86% # number of callpals executed -system.cpu1.kern.callpal::rdps 2575 3.05% 94.91% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 94.91% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.00% 94.91% # number of callpals executed -system.cpu1.kern.callpal::rdusp 2 0.00% 94.91% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 94.92% # number of callpals executed -system.cpu1.kern.callpal::rti 4115 4.87% 99.79% # number of callpals executed -system.cpu1.kern.callpal::callsys 146 0.17% 99.96% # number of callpals executed -system.cpu1.kern.callpal::imb 34 0.04% 100.00% # number of callpals executed -system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 84542 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 2548 # number of protection mode switches -system.cpu1.kern.mode_switch::user 564 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 3056 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 1106 -system.cpu1.kern.mode_good::user 564 -system.cpu1.kern.mode_good::idle 542 -system.cpu1.kern.mode_switch_good::kernel 0.434066 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.177356 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.358625 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 5986368000 0.32% 0.32% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 456602000 0.02% 0.34% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1862102413500 99.66% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 2507 # number of times the context was actually changed -system.cpu1.committedInsts 15522159 # Number of instructions committed -system.cpu1.committedOps 15522159 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 14295544 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 198941 # Number of float alu accesses -system.cpu1.num_func_calls 493140 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1540068 # number of instructions that are conditional controls -system.cpu1.num_int_insts 14295544 # number of integer instructions -system.cpu1.num_fp_insts 198941 # number of float instructions -system.cpu1.num_int_register_reads 19514289 # number of times the integer registers were read -system.cpu1.num_int_register_writes 10457600 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 101734 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 104129 # number of times the floating registers were written -system.cpu1.num_mem_refs 4961786 # number of memory refs -system.cpu1.num_load_insts 2849090 # Number of load instructions -system.cpu1.num_store_insts 2112696 # Number of store instructions -system.cpu1.num_idle_cycles 3722773671.474783 # Number of idle cycles -system.cpu1.num_busy_cycles 15522937.525217 # Number of busy cycles -system.cpu1.not_idle_fraction 0.004152 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.995848 # Percentage of idle cycles -system.cpu1.Branches 2214163 # Number of branches fetched -system.cpu1.op_class::No_OpClass 856043 5.51% 5.51% # Class of executed instruction -system.cpu1.op_class::IntAlu 9156766 58.98% 64.49% # Class of executed instruction -system.cpu1.op_class::IntMult 25065 0.16% 64.65% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 64.65% # Class of executed instruction -system.cpu1.op_class::FloatAdd 12426 0.08% 64.73% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 64.73% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 64.73% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 64.73% # Class of executed instruction -system.cpu1.op_class::FloatMultAcc 0 0.00% 64.73% # Class of executed instruction -system.cpu1.op_class::FloatDiv 1409 0.01% 64.74% # Class of executed instruction -system.cpu1.op_class::FloatMisc 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.74% # Class of executed instruction -system.cpu1.op_class::MemRead 2842559 18.31% 83.05% # Class of executed instruction -system.cpu1.op_class::MemWrite 2023248 13.03% 96.08% # Class of executed instruction -system.cpu1.op_class::FloatMemRead 94457 0.61% 96.69% # Class of executed instruction -system.cpu1.op_class::FloatMemWrite 90649 0.58% 97.27% # Class of executed instruction -system.cpu1.op_class::IprAccess 423253 2.73% 100.00% # Class of executed instruction -system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 15525875 # Class of executed instruction -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 201757 # number of replacements -system.cpu1.dcache.tags.tagsinuse 497.601962 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 4718401 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 202065 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 23.350907 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 15869420000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 497.601962 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.971879 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.971879 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 306 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.601562 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 20020608 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 20020608 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 2632688 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2632688 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1954647 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1954647 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 61098 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 61098 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 64211 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 64211 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 4587335 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 4587335 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 4587335 # number of overall hits -system.cpu1.dcache.overall_hits::total 4587335 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 140885 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 140885 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 78313 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 78313 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11000 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 11000 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 7304 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 7304 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 219198 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 219198 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 219198 # number of overall misses -system.cpu1.dcache.overall_misses::total 219198 # number of overall misses -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2773573 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2773573 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 2032960 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 2032960 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 72098 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 72098 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 71515 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 71515 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 4806533 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 4806533 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 4806533 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 4806533 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.050795 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.050795 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.038522 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.038522 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.152570 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.152570 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.102132 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.102132 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.045604 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.045604 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.045604 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.045604 # miss rate for overall accesses -system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 144832 # number of writebacks -system.cpu1.dcache.writebacks::total 144832 # number of writebacks -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 380647 # number of replacements -system.cpu1.icache.tags.tagsinuse 453.133719 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 15144687 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 381159 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 39.733253 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1859777195500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 453.133719 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.885027 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.885027 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 509 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 15907063 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 15907063 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 15144687 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 15144687 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 15144687 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 15144687 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 15144687 # number of overall hits -system.cpu1.icache.overall_hits::total 15144687 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 381188 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 381188 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 381188 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 381188 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 381188 # number of overall misses -system.cpu1.icache.overall_misses::total 381188 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 15525875 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 15525875 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 15525875 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 15525875 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 15525875 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 15525875 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024552 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024552 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024552 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024552 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024552 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024552 # miss rate for overall accesses -system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 380647 # number of writebacks -system.cpu1.icache.writebacks::total 380647 # number of writebacks -system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). -system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. -system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_txs 395 # Number of DMA write transactions. -system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. -system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. -system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 7628 # Transaction distribution -system.iobus.trans_dist::ReadResp 7628 # Transaction distribution -system.iobus.trans_dist::WriteReq 56140 # Transaction distribution -system.iobus.trans_dist::WriteResp 56140 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14686 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1014 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 1076 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18036 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 44074 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83462 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83462 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 127536 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 58744 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2749 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 1392 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9018 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 86162 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661656 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661656 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2747818 # Cumulative packet size per connected master and slave (bytes) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 41699 # number of replacements -system.iocache.tags.tagsinuse 0.434096 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41715 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1685787164517 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.434096 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.027131 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.027131 # Average percentage of cache occupancy -system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id -system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375579 # Number of tag accesses -system.iocache.tags.data_accesses 375579 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.iocache.ReadReq_misses::tsunami.ide 179 # number of ReadReq misses -system.iocache.ReadReq_misses::total 179 # number of ReadReq misses -system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses -system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses -system.iocache.demand_misses::tsunami.ide 41731 # number of demand (read+write) misses -system.iocache.demand_misses::total 41731 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41731 # number of overall misses -system.iocache.overall_misses::total 41731 # number of overall misses -system.iocache.ReadReq_accesses::tsunami.ide 179 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 179 # number of ReadReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41731 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41731 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41731 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41731 # number of overall (read+write) accesses -system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses -system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses -system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.writebacks::writebacks 41520 # number of writebacks -system.iocache.writebacks::total 41520 # number of writebacks -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 999962 # number of replacements -system.l2c.tags.tagsinuse 65520.418446 # Cycle average of tags in use -system.l2c.tags.total_refs 4560628 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1065470 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 4.280391 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 618103500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 304.654016 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4865.757369 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 58473.870947 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 175.171504 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1700.964609 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.004649 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.074246 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.892240 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.002673 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.025955 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.999762 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65508 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 674 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 2411 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2462 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 9328 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 50633 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.999573 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 46077158 # Number of tag accesses -system.l2c.tags.data_accesses 46077158 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 778757 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 778757 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 721480 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 721480 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 3102 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 2744 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 5846 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 1187 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 1121 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 2308 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 111978 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 56627 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 168605 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 607070 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 379530 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 986600 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 626251 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 128790 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 755041 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.inst 607070 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 738229 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 379530 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 185417 # number of demand (read+write) hits -system.l2c.demand_hits::total 1910246 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 607070 # number of overall hits -system.l2c.overall_hits::cpu0.data 738229 # number of overall hits -system.l2c.overall_hits::cpu1.inst 379530 # number of overall hits -system.l2c.overall_hits::cpu1.data 185417 # number of overall hits -system.l2c.overall_hits::total 1910246 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 4 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 2 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 6 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 113307 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 11044 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 124351 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 11848 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 1658 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 13506 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 926616 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 1036 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 927652 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.inst 11848 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 1039923 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1658 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 12080 # number of demand (read+write) misses -system.l2c.demand_misses::total 1065509 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 11848 # number of overall misses -system.l2c.overall_misses::cpu0.data 1039923 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1658 # number of overall misses -system.l2c.overall_misses::cpu1.data 12080 # number of overall misses -system.l2c.overall_misses::total 1065509 # number of overall misses -system.l2c.WritebackDirty_accesses::writebacks 778757 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 778757 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackClean_accesses::writebacks 721480 # number of WritebackClean accesses(hits+misses) -system.l2c.WritebackClean_accesses::total 721480 # number of WritebackClean accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 3106 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 2746 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 5852 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 1187 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 1122 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 2309 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 225285 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 67671 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 292956 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu0.inst 618918 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu1.inst 381188 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::total 1000106 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 1552867 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 129826 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 1682693 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 618918 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1778152 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 381188 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 197497 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2975755 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 618918 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1778152 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 381188 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 197497 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2975755 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.001288 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.000728 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.001025 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.000891 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.000433 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.502950 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.163201 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.424470 # miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.019143 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.004350 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::total 0.013505 # miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.596713 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.007980 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.551290 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.019143 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.584834 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.004350 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.061165 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.358063 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.019143 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.584834 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.004350 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.061165 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.358063 # miss rate for overall accesses -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.writebacks::writebacks 80947 # number of writebacks -system.l2c.writebacks::total 80947 # number of writebacks -system.membus.snoop_filter.tot_requests 2174394 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 1068384 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 430 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 7449 # Transaction distribution -system.membus.trans_dist::ReadResp 948786 # Transaction distribution -system.membus.trans_dist::WriteReq 14588 # Transaction distribution -system.membus.trans_dist::WriteResp 14588 # Transaction distribution -system.membus.trans_dist::WritebackDirty 122467 # Transaction distribution -system.membus.trans_dist::CleanEvict 918018 # Transaction distribution -system.membus.trans_dist::UpgradeReq 13880 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 11895 # Transaction distribution -system.membus.trans_dist::UpgradeResp 135 # Transaction distribution -system.membus.trans_dist::ReadExReq 125245 # Transaction distribution -system.membus.trans_dist::ReadExResp 124223 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 941337 # Transaction distribution -system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 44074 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3156480 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 3200554 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 125161 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 125161 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 3325715 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 86162 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 73364992 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 73451154 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2668736 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2668736 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 76119890 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 2196431 # Request fanout histogram -system.membus.snoop_fanout::mean 0.000519 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.022766 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2195292 99.95% 99.95% # Request fanout histogram -system.membus.snoop_fanout::1 1139 0.05% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2196431 # Request fanout histogram -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 6035809 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 3018662 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 374456 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 1621 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 1531 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 90 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 7449 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2732152 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 14588 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 14588 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 778757 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 998939 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 1204367 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 19598 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 14203 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 33801 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 295242 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 295242 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1000127 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1724576 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1856170 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5450061 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1143023 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 684375 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 9133629 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 79182784 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 155817595 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 48757440 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 23377367 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 307135186 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1000983 # Total snoops (count) -system.toL2Bus.snoopTraffic 5197312 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 7058665 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.106769 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.309069 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 6305559 89.33% 89.33% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 752566 10.66% 99.99% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 538 0.01% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 2 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 7058665 # Request fanout histogram -system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post -system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR -system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post -system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post -system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post -system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post -system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post -system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post -system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post -system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post -system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU -system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states -system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1869357999000 # Cumulative time (in ticks) in various power states - ----------- End Simulation Statistics ---------- diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simerr --- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simerr Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,53 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -getting pixel output filename pixels_out.cook -opening control file chair.control.cook -opening camera file chair.camera -opening surfaces file chair.surfaces -reading data -processing 8parts -Grid measure is 6 by 3.0001 by 6 -cell dimension is 0.863065 -Creating grid for list of length 21 -Grid size = 7 by 4 by 7 -Total occupancy = 236 -reading control stream -reading camera stream -Writing to chair.cook.ppm -calculating 15 by 15 image with 196 samples -col 0. . . -col 1. . . -col 2. . . -col 3. . . -col 4. . . -col 5. . . -col 6. . . -col 7. . . -col 8. . . -col 9. . . -col 10. . . -col 11. . . -col 12. . . -col 13. . . -col 14. . . -Writing to chair.cook.ppm -0 8 14 -1 8 14 -2 8 14 -3 8 14 -4 8 14 -5 8 14 -6 8 14 -7 8 14 -8 8 14 -9 8 14 -10 8 14 -11 8 14 -12 8 14 -13 8 14 -14 8 14 -warn: ignoring syscall sigprocmask(1, ...) diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simout --- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/simout Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,17 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/minor-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/minor-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:19:45 -gem5 executing on e108600-lin, pid 28070 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/30.eon/alpha/tru64/minor-timing - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Eon, Version 1.1 -info: Increasing stack size by one page. -OO-style eon Time= 0.233333 -Exiting @ tick 233641094500 because target called exit() diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt --- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,794 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.233641 # Number of seconds simulated -sim_ticks 233641094500 # Number of ticks simulated -final_tick 233641094500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 449379 # Simulator instruction rate (inst/s) -host_op_rate 449379 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 263362780 # Simulator tick rate (ticks/s) -host_mem_usage 260228 # Number of bytes of host memory used -host_seconds 887.15 # Real time elapsed on the host -sim_insts 398664651 # Number of instructions simulated -sim_ops 398664651 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 249280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 254592 # Number of bytes read from this memory -system.physmem.bytes_read::total 503872 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 249280 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 249280 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3895 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3978 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7873 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1066936 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1089671 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2156607 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1066936 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1066936 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1066936 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1089671 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2156607 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7873 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7873 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 503872 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 503872 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 548 # Per bank write bursts -system.physmem.perBankRdBursts::1 675 # Per bank write bursts -system.physmem.perBankRdBursts::2 473 # Per bank write bursts -system.physmem.perBankRdBursts::3 633 # Per bank write bursts -system.physmem.perBankRdBursts::4 475 # Per bank write bursts -system.physmem.perBankRdBursts::5 477 # Per bank write bursts -system.physmem.perBankRdBursts::6 563 # Per bank write bursts -system.physmem.perBankRdBursts::7 560 # Per bank write bursts -system.physmem.perBankRdBursts::8 471 # Per bank write bursts -system.physmem.perBankRdBursts::9 437 # Per bank write bursts -system.physmem.perBankRdBursts::10 354 # Per bank write bursts -system.physmem.perBankRdBursts::11 323 # Per bank write bursts -system.physmem.perBankRdBursts::12 430 # Per bank write bursts -system.physmem.perBankRdBursts::13 556 # Per bank write bursts -system.physmem.perBankRdBursts::14 473 # Per bank write bursts -system.physmem.perBankRdBursts::15 425 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 233641000500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7873 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 6664 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 79 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1527 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 328.298625 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 196.524272 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 332.958390 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 522 34.18% 34.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 350 22.92% 57.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 181 11.85% 68.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 105 6.88% 75.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 64 4.19% 80.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 46 3.01% 83.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 30 1.96% 85.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 42 2.75% 87.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 187 12.25% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1527 # Bytes accessed per row activation -system.physmem.totQLat 179319500 # Total ticks spent queuing -system.physmem.totMemAccLat 326938250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 39365000 # Total ticks spent in databus transfers -system.physmem.avgQLat 22776.51 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 41526.51 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.16 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.16 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.02 # Data bus utilization in percentage -system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6337 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.49 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 29676235.30 # Average gap between requests -system.physmem.pageHitRate 80.49 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6326040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3347190 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 31444560 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 242168160.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 105016230 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 11391840 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 673376340 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 320465280 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 55494876360 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 56888412000 # Total energy per rank (pJ) -system.physmem_0.averagePower 243.486327 # Core power per rank (mW) -system.physmem_0.totalIdleTime 233381065000 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 19761500 # Time in different power states -system.physmem_0.memoryStateTime::REF 102860000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 231069881000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 834517500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 137354250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 1476720250 # Time in different power states -system.physmem_1.actEnergy 4641000 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2447775 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 24768660 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 215124000.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 84187860 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 12227040 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 535263060 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 280836480 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 55611059460 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 56770555335 # Total energy per rank (pJ) -system.physmem_1.averagePower 242.981892 # Core power per rank (mW) -system.physmem_1.totalIdleTime 233423818750 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 23567500 # Time in different power states -system.physmem_1.memoryStateTime::REF 91510000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 231519465750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 731339000 # Time in different power states -system.physmem_1.memoryStateTime::ACT 101377500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 1173834750 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 45912950 # Number of BP lookups -system.cpu.branchPred.condPredicted 26702746 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 565787 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 25186743 # Number of BTB lookups -system.cpu.branchPred.BTBHits 18811780 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 74.689212 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 8285572 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 323 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 2249876 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 2235903 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 13973 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 111495 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 95338456 # DTB read hits -system.cpu.dtb.read_misses 116 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 95338572 # DTB read accesses -system.cpu.dtb.write_hits 73578378 # DTB write hits -system.cpu.dtb.write_misses 847 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 73579225 # DTB write accesses -system.cpu.dtb.data_hits 168916834 # DTB hits -system.cpu.dtb.data_misses 963 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 168917797 # DTB accesses -system.cpu.itb.fetch_hits 96959253 # ITB hits -system.cpu.itb.fetch_misses 1239 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 96960492 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 233641094500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 467282189 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 398664651 # Number of instructions committed -system.cpu.committedOps 398664651 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2289293 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.172118 # CPI: cycles per instruction -system.cpu.ipc 0.853156 # IPC: instructions per cycle -system.cpu.op_class_0::No_OpClass 23123356 5.80% 5.80% # Class of committed instruction -system.cpu.op_class_0::IntAlu 141652555 35.53% 41.33% # Class of committed instruction -system.cpu.op_class_0::IntMult 2124322 0.53% 41.86% # Class of committed instruction -system.cpu.op_class_0::IntDiv 0 0.00% 41.86% # Class of committed instruction -system.cpu.op_class_0::FloatAdd 35620060 8.93% 50.80% # Class of committed instruction -system.cpu.op_class_0::FloatCmp 7072549 1.77% 52.57% # Class of committed instruction -system.cpu.op_class_0::FloatCvt 2735231 0.69% 53.26% # Class of committed instruction -system.cpu.op_class_0::FloatMult 16498021 4.14% 57.40% # Class of committed instruction -system.cpu.op_class_0::FloatMultAcc 0 0.00% 57.40% # Class of committed instruction -system.cpu.op_class_0::FloatDiv 1563283 0.39% 57.79% # Class of committed instruction -system.cpu.op_class_0::FloatMisc 0 0.00% 57.79% # Class of committed instruction -system.cpu.op_class_0::FloatSqrt 0 0.00% 57.79% # Class of committed instruction -system.cpu.op_class_0::SimdAdd 0 0.00% 57.79% # Class of committed instruction -system.cpu.op_class_0::SimdAddAcc 0 0.00% 57.79% # Class of committed instruction -system.cpu.op_class_0::SimdAlu 0 0.00% 57.79% # Class of committed instruction -system.cpu.op_class_0::SimdCmp 0 0.00% 57.79% # Class of committed instruction -system.cpu.op_class_0::SimdCvt 0 0.00% 57.79% # Class of committed instruction -system.cpu.op_class_0::SimdMisc 0 0.00% 57.79% # Class of committed instruction -system.cpu.op_class_0::SimdMult 0 0.00% 57.79% # Class of committed instruction -system.cpu.op_class_0::SimdMultAcc 0 0.00% 57.79% # Class of committed instruction -system.cpu.op_class_0::SimdShift 0 0.00% 57.79% # Class of committed instruction -system.cpu.op_class_0::SimdShiftAcc 0 0.00% 57.79% # Class of committed instruction -system.cpu.op_class_0::SimdSqrt 0 0.00% 57.79% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAdd 0 0.00% 57.79% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAlu 0 0.00% 57.79% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCmp 0 0.00% 57.79% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCvt 0 0.00% 57.79% # Class of committed instruction -system.cpu.op_class_0::SimdFloatDiv 0 0.00% 57.79% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMisc 0 0.00% 57.79% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMult 0 0.00% 57.79% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 57.79% # Class of committed instruction -system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 57.79% # Class of committed instruction -system.cpu.op_class_0::MemRead 46072315 11.56% 69.35% # Class of committed instruction -system.cpu.op_class_0::MemWrite 30396984 7.62% 76.97% # Class of committed instruction -system.cpu.op_class_0::FloatMemRead 48682195 12.21% 89.18% # Class of committed instruction -system.cpu.op_class_0::FloatMemWrite 43123780 10.82% 100.00% # Class of committed instruction -system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 398664651 # Class of committed instruction -system.cpu.tickCycles 455741730 # Number of cycles that the object actually ticked -system.cpu.idleCycles 11540459 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 771 # number of replacements -system.cpu.dcache.tags.tagsinuse 3291.586193 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 167817015 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 4165 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 40292.200480 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3291.586193 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.803610 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.803610 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 3394 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 216 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 3113 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.828613 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 335652183 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 335652183 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 94302219 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 94302219 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73514796 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73514796 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 167817015 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 167817015 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 167817015 # number of overall hits -system.cpu.dcache.overall_hits::total 167817015 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1061 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1061 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5933 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5933 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 6994 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 6994 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 6994 # number of overall misses -system.cpu.dcache.overall_misses::total 6994 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 94695000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 94695000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 540363000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 540363000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 635058000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 635058000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 635058000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 635058000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 94303280 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 94303280 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 167824009 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 167824009 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 167824009 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 167824009 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000011 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000011 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000081 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000081 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000042 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000042 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 89250.706880 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 89250.706880 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 91077.532446 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 91077.532446 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 90800.400343 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 90800.400343 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 90800.400343 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 90800.400343 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 654 # number of writebacks -system.cpu.dcache.writebacks::total 654 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 92 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 92 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2737 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2737 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2829 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2829 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2829 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2829 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 969 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 969 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3196 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3196 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4165 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4165 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4165 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4165 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 86354000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 86354000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 303749000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 303749000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 390103000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 390103000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 390103000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 390103000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000043 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89116.615067 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89116.615067 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 95040.362954 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 95040.362954 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 93662.184874 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 93662.184874 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 93662.184874 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 93662.184874 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 3194 # number of replacements -system.cpu.icache.tags.tagsinuse 1919.615846 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 96954081 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 5172 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18745.955336 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1919.615846 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.937312 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.937312 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1978 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 396 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1287 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.965820 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 193923678 # Number of tag accesses -system.cpu.icache.tags.data_accesses 193923678 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 96954081 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 96954081 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 96954081 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 96954081 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 96954081 # number of overall hits -system.cpu.icache.overall_hits::total 96954081 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5172 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5172 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5172 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5172 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5172 # number of overall misses -system.cpu.icache.overall_misses::total 5172 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 373067500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 373067500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 373067500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 373067500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 373067500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 373067500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 96959253 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 96959253 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 96959253 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 96959253 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 96959253 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 96959253 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000053 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000053 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000053 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000053 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000053 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72132.153906 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 72132.153906 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 72132.153906 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 72132.153906 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 72132.153906 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 72132.153906 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was 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-system.cpu.icache.overall_mshr_misses::cpu.inst 5172 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 5172 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 367895500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 367895500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 367895500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 367895500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 367895500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 367895500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71132.153906 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71132.153906 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71132.153906 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 71132.153906 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71132.153906 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 71132.153906 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 7128.397001 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 5429 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 7873 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.689572 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3411.799627 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 3716.597374 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.104120 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.113422 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.217541 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 7873 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 118 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 502 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 7186 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.240265 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 114289 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 114289 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 654 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 654 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 3194 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 3194 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 61 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 61 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1277 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1277 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 126 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 126 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1277 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 187 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1464 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1277 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 187 # number of overall hits -system.cpu.l2cache.overall_hits::total 1464 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 3137 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 3137 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3895 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 3895 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 841 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 841 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3895 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 3978 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 7873 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3895 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 3978 # number of overall misses -system.cpu.l2cache.overall_misses::total 7873 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 298441000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 298441000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 346727500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 346727500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 83414000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 83414000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 346727500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 381855000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 728582500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 346727500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 381855000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 728582500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 654 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 654 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 3194 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 3194 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 3198 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 3198 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 5172 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 5172 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 967 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 967 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 5172 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 4165 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9337 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 5172 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 4165 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9337 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.980926 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.980926 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.753094 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.753094 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.869700 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.869700 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.753094 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.955102 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.843204 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.753094 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.955102 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.843204 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 95135.798534 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 95135.798534 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89018.613607 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89018.613607 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 99184.304400 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 99184.304400 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89018.613607 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 95991.704374 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 92541.915407 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89018.613607 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 95991.704374 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 92541.915407 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3137 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 3137 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3895 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3895 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 841 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 841 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3895 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 3978 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7873 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3895 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 3978 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7873 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 267071000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 267071000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 307777500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 307777500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 75004000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 75004000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 307777500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 342075000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 649852500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 307777500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 342075000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 649852500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.980926 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.980926 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.753094 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.753094 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.869700 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.869700 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.753094 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955102 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.843204 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.753094 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955102 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.843204 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 85135.798534 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 85135.798534 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79018.613607 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79018.613607 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 89184.304400 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 89184.304400 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79018.613607 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 85991.704374 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 82541.915407 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79018.613607 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 85991.704374 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 82541.915407 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 13302 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 3965 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 6139 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 654 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 3194 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 117 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 3198 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 3198 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 5172 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 967 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13538 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9101 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 22639 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 535424 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 308416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 843840 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 9337 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 9337 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 9337 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10499000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7758000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6247500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 7873 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 233641094500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 4736 # Transaction distribution -system.membus.trans_dist::ReadExReq 3137 # Transaction distribution -system.membus.trans_dist::ReadExResp 3137 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 4736 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15746 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 15746 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 503872 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 503872 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 7873 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7873 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7873 # Request fanout histogram -system.membus.reqLayer0.occupancy 9215000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 41791500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,825 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=DerivO3CPU -children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload -LFSTSize=1024 -LQEntries=32 -LSQCheckLoads=true -LSQDepCheckShift=4 -SQEntries=32 -SSITSize=1024 -activity=0 -backComSize=5 -branchPred=system.cpu.branchPred -cachePorts=200 -checker=Null -clk_domain=system.cpu_clk_domain -commitToDecodeDelay=1 -commitToFetchDelay=1 -commitToIEWDelay=1 -commitToRenameDelay=1 -commitWidth=8 -cpu_id=0 -decodeToFetchDelay=1 -decodeToRenameDelay=1 -decodeWidth=8 -default_p_state=UNDEFINED -dispatchWidth=8 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -fetchBufferSize=64 -fetchQueueSize=32 -fetchToDecodeDelay=1 -fetchTrapLatency=1 -fetchWidth=8 -forwardComSize=5 -fuPool=system.cpu.fuPool -function_trace=false -function_trace_start=0 -iewToCommitDelay=1 -iewToDecodeDelay=1 -iewToFetchDelay=1 -iewToRenameDelay=1 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -issueToExecuteDelay=1 -issueWidth=8 -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -needsTSO=false -numIQEntries=64 -numPhysCCRegs=0 -numPhysFloatRegs=256 -numPhysIntRegs=256 -numROBEntries=192 -numRobs=1 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -renameToDecodeDelay=1 -renameToFetchDelay=1 -renameToIEWDelay=2 -renameToROBDelay=1 -renameWidth=8 -simpoint_start_insts= -smtCommitPolicy=RoundRobin -smtFetchPolicy=SingleThread -smtIQPolicy=Partitioned -smtIQThreshold=100 -smtLSQPolicy=Partitioned -smtLSQThreshold=100 -smtNumFetchingThreads=1 -smtROBPolicy=Partitioned -smtROBThreshold=100 -socket_id=0 -squashWidth=8 -store_set_clear_period=250000 -switched_out=false -system=system -tracer=system.cpu.tracer -trapLatency=13 -wbWidth=8 -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.branchPred] -type=TournamentBP -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -indirectHashGHR=true -indirectHashTargets=true -indirectPathLength=3 -indirectSets=256 -indirectTagSize=16 -indirectWays=2 -instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 -useIndirect=true - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.fuPool] -type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 -eventq_index=0 - -[system.cpu.fuPool.FUList0] -type=FUDesc -children=opList -count=6 -eventq_index=0 -opList=system.cpu.fuPool.FUList0.opList - -[system.cpu.fuPool.FUList0.opList] -type=OpDesc -eventq_index=0 -opClass=IntAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList1] -type=FUDesc -children=opList0 opList1 -count=2 -eventq_index=0 -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -eventq_index=0 -opClass=IntMult -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -eventq_index=0 -opClass=IntDiv -opLat=20 -pipelined=false - -[system.cpu.fuPool.FUList2] -type=FUDesc -children=opList0 opList1 opList2 -count=4 -eventq_index=0 -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -eventq_index=0 -opClass=FloatAdd -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -eventq_index=0 -opClass=FloatCmp -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -eventq_index=0 -opClass=FloatCvt -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList3] -type=FUDesc -children=opList0 opList1 opList2 -count=2 -eventq_index=0 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -eventq_index=0 -opClass=FloatMult -opLat=4 -pipelined=true - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -eventq_index=0 -opClass=FloatDiv -opLat=12 -pipelined=false - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -eventq_index=0 -opClass=FloatSqrt -opLat=24 -pipelined=false - -[system.cpu.fuPool.FUList4] -type=FUDesc -children=opList -count=0 -eventq_index=0 -opList=system.cpu.fuPool.FUList4.opList - -[system.cpu.fuPool.FUList4.opList] -type=OpDesc -eventq_index=0 -opClass=MemRead -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5] -type=FUDesc -children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 -count=4 -eventq_index=0 -opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 - -[system.cpu.fuPool.FUList5.opList00] -type=OpDesc -eventq_index=0 -opClass=SimdAdd -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList01] -type=OpDesc -eventq_index=0 -opClass=SimdAddAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList02] -type=OpDesc -eventq_index=0 -opClass=SimdAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList03] -type=OpDesc -eventq_index=0 -opClass=SimdCmp -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList04] -type=OpDesc -eventq_index=0 -opClass=SimdCvt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList05] -type=OpDesc -eventq_index=0 -opClass=SimdMisc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList06] -type=OpDesc -eventq_index=0 -opClass=SimdMult -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList07] -type=OpDesc -eventq_index=0 -opClass=SimdMultAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList08] -type=OpDesc -eventq_index=0 -opClass=SimdShift -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList09] -type=OpDesc -eventq_index=0 -opClass=SimdShiftAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList10] -type=OpDesc -eventq_index=0 -opClass=SimdSqrt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList11] -type=OpDesc -eventq_index=0 -opClass=SimdFloatAdd -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList12] -type=OpDesc -eventq_index=0 -opClass=SimdFloatAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList13] -type=OpDesc -eventq_index=0 -opClass=SimdFloatCmp -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList14] -type=OpDesc -eventq_index=0 -opClass=SimdFloatCvt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList15] -type=OpDesc -eventq_index=0 -opClass=SimdFloatDiv -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList16] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMisc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList17] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMult -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList18] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMultAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList19] -type=OpDesc -eventq_index=0 -opClass=SimdFloatSqrt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList6] -type=FUDesc -children=opList -count=0 -eventq_index=0 -opList=system.cpu.fuPool.FUList6.opList - -[system.cpu.fuPool.FUList6.opList] -type=OpDesc -eventq_index=0 -opClass=MemWrite -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList7] -type=FUDesc -children=opList0 opList1 -count=4 -eventq_index=0 -opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -eventq_index=0 -opClass=MemRead -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList7.opList1] -type=OpDesc -eventq_index=0 -opClass=MemWrite -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList8] -type=FUDesc -children=opList -count=1 -eventq_index=0 -opList=system.cpu.fuPool.FUList8.opList - -[system.cpu.fuPool.FUList8.opList] -type=OpDesc -eventq_index=0 -opClass=IprAccess -opLat=3 -pipelined=false - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/eon -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=0:134217727:0:0:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=6000 -tXPDLL=0 -tXS=270000 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simerr --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simerr Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,53 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -getting pixel output filename pixels_out.cook -opening control file chair.control.cook -opening camera file chair.camera -opening surfaces file chair.surfaces -reading data -processing 8parts -Grid measure is 6 by 3.0001 by 6 -cell dimension is 0.863065 -Creating grid for list of length 21 -Grid size = 7 by 4 by 7 -Total occupancy = 236 -reading control stream -reading camera stream -Writing to chair.cook.ppm -calculating 15 by 15 image with 196 samples -col 0. . . -col 1. . . -col 2. . . -col 3. . . -col 4. . . -col 5. . . -col 6. . . -col 7. . . -col 8. . . -col 9. . . -col 10. . . -col 11. . . -col 12. . . -col 13. . . -col 14. . . -Writing to chair.cook.ppm -0 8 14 -1 8 14 -2 8 14 -3 8 14 -4 8 14 -5 8 14 -6 8 14 -7 8 14 -8 8 14 -9 8 14 -10 8 14 -11 8 14 -12 8 14 -13 8 14 -14 8 14 -warn: ignoring syscall sigprocmask(1, ...) diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,17 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:19:44 -gem5 executing on e108600-lin, pid 28057 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/30.eon/alpha/tru64/o3-timing - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Eon, Version 1.1 -info: Increasing stack size by one page. -OO-style eon Time= 0.050000 -Exiting @ tick 64255452000 because target called exit() diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,1059 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.064255 # Number of seconds simulated -sim_ticks 64255452000 # Number of ticks simulated -final_tick 64255452000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 443081 # Simulator instruction rate (inst/s) -host_op_rate 443081 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 75804731 # Simulator tick rate (ticks/s) -host_mem_usage 261252 # Number of bytes of host memory used -host_seconds 847.64 # Real time elapsed on the host -sim_insts 375574794 # Number of instructions simulated -sim_ops 375574794 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 64255452000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 220800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 255296 # Number of bytes read from this memory -system.physmem.bytes_read::total 476096 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 220800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 220800 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3450 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3989 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7439 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 3436284 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3973141 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 7409426 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3436284 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3436284 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3436284 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3973141 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7409426 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7439 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7439 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 476096 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 476096 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 524 # Per bank write bursts -system.physmem.perBankRdBursts::1 651 # Per bank write bursts -system.physmem.perBankRdBursts::2 450 # Per bank write bursts -system.physmem.perBankRdBursts::3 600 # Per bank write bursts -system.physmem.perBankRdBursts::4 446 # Per bank write bursts -system.physmem.perBankRdBursts::5 454 # Per bank write bursts -system.physmem.perBankRdBursts::6 513 # Per bank write bursts -system.physmem.perBankRdBursts::7 524 # Per bank write bursts -system.physmem.perBankRdBursts::8 438 # Per bank write bursts -system.physmem.perBankRdBursts::9 408 # Per bank write bursts -system.physmem.perBankRdBursts::10 339 # Per bank write bursts -system.physmem.perBankRdBursts::11 306 # Per bank write bursts -system.physmem.perBankRdBursts::12 414 # Per bank write bursts -system.physmem.perBankRdBursts::13 540 # Per bank write bursts -system.physmem.perBankRdBursts::14 452 # Per bank write bursts -system.physmem.perBankRdBursts::15 380 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 64255349500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7439 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3982 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2008 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 898 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 438 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 111 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # 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-system.physmem.bytesPerActivate::samples 1349 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 351.644181 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 209.715239 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 347.080632 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 429 31.80% 31.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 311 23.05% 54.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 151 11.19% 66.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 87 6.45% 72.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 68 5.04% 77.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 39 2.89% 80.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 38 2.82% 83.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 30 2.22% 85.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 196 14.53% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1349 # Bytes accessed per row activation -system.physmem.totQLat 165053250 # Total ticks spent queuing -system.physmem.totMemAccLat 304534500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 37195000 # Total ticks spent in databus transfers -system.physmem.avgQLat 22187.56 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 40937.56 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 7.41 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 7.41 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.06 # Data bus utilization in percentage -system.physmem.busUtilRead 0.06 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6085 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.80 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 8637632.68 # Average gap between requests -system.physmem.pageHitRate 81.80 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 5454960 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2880405 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 29716680 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 128459760.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 63558420 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 5463840 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 397888500 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 152192640 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 15095921460 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 15881536665 # Total energy per rank (pJ) -system.physmem_0.averagePower 247.162475 # Core power per rank (mW) -system.physmem_0.totalIdleTime 64101767750 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 8572500 # Time in different power states -system.physmem_0.memoryStateTime::REF 54520000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 62832935750 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 396328750 # Time in different power states -system.physmem_0.memoryStateTime::ACT 90536500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 872558500 # Time in different power states -system.physmem_1.actEnergy 4212600 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2239050 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 23397780 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 172713840.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 67790100 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 10409760 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 394655460 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 234464640 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 15065735460 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 15975618690 # Total energy per rank (pJ) -system.physmem_1.averagePower 248.626662 # Core power per rank (mW) -system.physmem_1.totalIdleTime 64079571000 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 20607500 # Time in different power states -system.physmem_1.memoryStateTime::REF 73504000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 62603628000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 610590500 # Time in different power states -system.physmem_1.memoryStateTime::ACT 81643000 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 865479000 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 64255452000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 47858833 # Number of BP lookups -system.cpu.branchPred.condPredicted 27887840 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 573531 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 23350857 # Number of BTB lookups -system.cpu.branchPred.BTBHits 19575248 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 83.830962 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 8687752 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1405 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 2338807 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 2307668 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 31139 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 111329 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 98831063 # DTB read hits -system.cpu.dtb.read_misses 28342 # DTB read misses -system.cpu.dtb.read_acv 849 # DTB read access violations -system.cpu.dtb.read_accesses 98859405 # DTB read accesses -system.cpu.dtb.write_hits 75501441 # DTB write hits -system.cpu.dtb.write_misses 1449 # DTB write misses -system.cpu.dtb.write_acv 3 # DTB write access violations -system.cpu.dtb.write_accesses 75502890 # DTB write accesses -system.cpu.dtb.data_hits 174332504 # DTB hits -system.cpu.dtb.data_misses 29791 # DTB misses -system.cpu.dtb.data_acv 852 # DTB access violations -system.cpu.dtb.data_accesses 174362295 # DTB accesses -system.cpu.itb.fetch_hits 46958874 # ITB hits -system.cpu.itb.fetch_misses 432 # ITB misses -system.cpu.itb.fetch_acv 5 # ITB acv -system.cpu.itb.fetch_accesses 46959306 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 64255452000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 128510907 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 47429437 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 424837073 # Number of instructions fetch has processed -system.cpu.fetch.Branches 47858833 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 30570668 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 80085665 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1247776 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 13 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 297 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 13295 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 79 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 46958874 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 226146 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 128152674 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.315086 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.349633 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 53168247 41.49% 41.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4330315 3.38% 44.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 6713619 5.24% 50.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5107106 3.99% 54.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 10970093 8.56% 62.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 7524949 5.87% 68.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5303300 4.14% 72.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1847075 1.44% 74.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 33187970 25.90% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 128152674 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.372411 # Number of branch fetches per cycle -system.cpu.fetch.rate 3.305844 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 42097840 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 13659925 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 67904561 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3870622 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 619726 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 8883416 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4205 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 421920314 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 13831 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 619726 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 43662514 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3075430 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 529984 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 70109441 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 10155579 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 419899923 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 443686 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2538434 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2849903 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 3565226 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 273976095 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 552171720 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 393714640 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 158457079 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 259532319 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 14443776 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 37564 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 298 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 15805009 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 99734698 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 76520876 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 11857010 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9264279 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 392184083 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 290 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 389210637 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 196187 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 16609578 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 7664570 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 75 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 128152674 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 3.037086 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.181467 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 17313559 13.51% 13.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 19411245 15.15% 28.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 22012922 17.18% 45.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 17948678 14.01% 59.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 19074074 14.88% 74.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 13271943 10.36% 85.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8797733 6.87% 91.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 6095055 4.76% 96.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 4227465 3.30% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 128152674 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 253970 1.29% 1.29% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 2 0.00% 1.29% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 138834 0.71% 2.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 79013 0.40% 2.40% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 3594 0.02% 2.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 3443745 17.54% 19.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 19.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1647907 8.39% 28.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 28.36% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 28.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 28.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.36% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.36% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 3789083 19.30% 47.66% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1973005 10.05% 57.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 5150981 26.24% 83.95% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 3150937 16.05% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 146989472 37.77% 37.77% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2128309 0.55% 38.32% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 38.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 36418443 9.36% 47.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 7355119 1.89% 49.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2800065 0.72% 50.29% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 16556449 4.25% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 54.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 1584163 0.41% 54.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 54.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.95% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 48929897 12.57% 67.52% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 31583157 8.11% 75.63% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 50573051 12.99% 88.63% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 44258931 11.37% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 389210637 # Type of FU issued -system.cpu.iq.rate 3.028619 # Inst issue rate -system.cpu.iq.fu_busy_cnt 19631071 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.050438 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 593561800 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 242185048 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 227933309 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 332839406 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 166679024 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 158288157 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 235646895 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 173161232 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 19364531 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4980212 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 92962 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 70485 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 3000148 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 382479 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 3666 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 619726 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1854972 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 162334 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 415907776 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 109026 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 99734698 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 76520876 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 290 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 8920 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 152322 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 70485 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 412161 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 230865 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 643026 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 387624331 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 98860283 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1586306 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 23723403 # number of nop insts executed -system.cpu.iew.exec_refs 174363211 # number of memory reference insts executed -system.cpu.iew.exec_branches 45864022 # Number of branches executed -system.cpu.iew.exec_stores 75502928 # Number of stores executed -system.cpu.iew.exec_rate 3.016276 # Inst execution rate -system.cpu.iew.wb_sent 386484413 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 386221466 # cumulative count of insts written-back -system.cpu.iew.wb_producers 192314001 # num instructions producing a value -system.cpu.iew.wb_consumers 273852153 # num instructions consuming a value -system.cpu.iew.wb_rate 3.005359 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.702255 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 17244606 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 569369 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 125687681 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 3.171867 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 3.248348 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 42136978 33.53% 33.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 17569311 13.98% 47.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 8725420 6.94% 54.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9050963 7.20% 61.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 6228783 4.96% 66.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 4113989 3.27% 69.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 4743327 3.77% 73.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2404790 1.91% 75.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 30714120 24.44% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 125687681 # Number of insts commited each cycle -system.cpu.commit.committedInsts 398664569 # Number of instructions committed -system.cpu.commit.committedOps 398664569 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 168275214 # Number of memory references committed -system.cpu.commit.loads 94754486 # Number of loads committed -system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 44587530 # Number of branches committed -system.cpu.commit.fp_insts 155295106 # Number of committed floating point instructions. -system.cpu.commit.int_insts 316365825 # Number of committed integer instructions. -system.cpu.commit.function_calls 8007752 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 23123356 5.80% 5.80% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 141652533 35.53% 41.33% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 2124322 0.53% 41.86% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 41.86% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 35620060 8.93% 50.80% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 7072549 1.77% 52.57% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 2735231 0.69% 53.26% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 16498021 4.14% 57.40% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 57.40% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 1563283 0.39% 57.79% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 57.79% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 57.79% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 57.79% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 57.79% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 57.79% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 57.79% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 57.79% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 57.79% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 57.79% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 57.79% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 57.79% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 57.79% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 57.79% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 57.79% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 57.79% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 57.79% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 57.79% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 57.79% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 57.79% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 57.79% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 57.79% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 57.79% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 46072297 11.56% 69.35% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 30396955 7.62% 76.97% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemRead 48682189 12.21% 89.18% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemWrite 43123773 10.82% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 398664569 # Class of committed instruction -system.cpu.commit.bw_lim_events 30714120 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 510879759 # The number of ROB reads -system.cpu.rob.rob_writes 834289662 # The number of ROB writes -system.cpu.timesIdled 3136 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 358233 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 375574794 # Number of Instructions Simulated -system.cpu.committedOps 375574794 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.342171 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.342171 # CPI: Total CPI of All Threads -system.cpu.ipc 2.922513 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.922513 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 385452576 # number of integer regfile reads -system.cpu.int_regfile_writes 165252743 # number of integer regfile writes -system.cpu.fp_regfile_reads 154537274 # number of floating regfile reads -system.cpu.fp_regfile_writes 102070951 # number of floating regfile writes -system.cpu.misc_regfile_reads 350572 # number of misc regfile reads -system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 64255452000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 774 # number of replacements -system.cpu.dcache.tags.tagsinuse 3291.451205 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 152580730 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 4174 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 36555.038333 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3291.451205 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.803577 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.803577 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 3400 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 211 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 3116 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.830078 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 305207642 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 305207642 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 64255452000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 79079190 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 79079190 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73501534 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73501534 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 6 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 6 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 152580724 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 152580724 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 152580724 # number of overall hits -system.cpu.dcache.overall_hits::total 152580724 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1810 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1810 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19194 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19194 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 21004 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21004 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21004 # number of overall misses -system.cpu.dcache.overall_misses::total 21004 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 137671000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 137671000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1331646003 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1331646003 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1469317003 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1469317003 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1469317003 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1469317003 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 79081000 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 79081000 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 73520728 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 73520728 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 6 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 6 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 152601728 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 152601728 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 152601728 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 152601728 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000023 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000023 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000261 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000261 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000138 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000138 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000138 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000138 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76061.325967 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 76061.325967 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69378.243357 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 69378.243357 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 69954.151733 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 69954.151733 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 69954.151733 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 69954.151733 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 57813 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 94 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 689 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 83.908563 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 94 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 655 # number of writebacks -system.cpu.dcache.writebacks::total 655 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 824 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 824 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16006 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16006 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 16830 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 16830 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 16830 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 16830 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 986 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 986 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3188 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3188 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4174 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4174 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4174 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4174 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 83512000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 83512000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 299984000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 299984000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 383496000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 383496000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 383496000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 383496000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000012 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000043 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 84697.768763 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 84697.768763 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 94097.867001 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 94097.867001 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 91877.335889 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 91877.335889 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 91877.335889 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 91877.335889 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 64255452000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 2132 # number of replacements -system.cpu.icache.tags.tagsinuse 1829.599220 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 46953196 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4059 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 11567.675782 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1829.599220 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.893359 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.893359 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1927 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 179 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 297 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1342 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.940918 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 93921805 # Number of tag accesses -system.cpu.icache.tags.data_accesses 93921805 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 64255452000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 46953196 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 46953196 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 46953196 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 46953196 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 46953196 # number of overall hits -system.cpu.icache.overall_hits::total 46953196 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5677 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5677 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5677 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5677 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5677 # number of overall misses -system.cpu.icache.overall_misses::total 5677 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 436957499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 436957499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 436957499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 436957499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 436957499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 436957499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 46958873 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 46958873 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 46958873 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 46958873 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 46958873 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 46958873 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000121 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000121 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000121 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000121 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000121 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000121 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76969.790206 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 76969.790206 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 76969.790206 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 76969.790206 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 76969.790206 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 76969.790206 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 896 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 59.733333 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 2132 # number of writebacks -system.cpu.icache.writebacks::total 2132 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1618 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1618 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1618 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1618 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1618 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1618 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4059 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4059 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4059 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4059 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4059 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4059 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 323146500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 323146500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 323146500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 323146500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 323146500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 323146500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000086 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000086 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000086 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79612.342942 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79612.342942 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79612.342942 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 79612.342942 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79612.342942 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 79612.342942 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 64255452000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 6685.408988 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3700 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 7439 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.497379 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2964.630490 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 3720.778498 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.090473 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.113549 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.204022 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 7439 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 147 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 428 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 6755 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.227020 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 96551 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 96551 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 64255452000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 655 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 655 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 2132 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 2132 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 609 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 609 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 125 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 125 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 609 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 185 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 794 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 609 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 185 # number of overall hits -system.cpu.l2cache.overall_hits::total 794 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 3128 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 3128 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3450 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 3450 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 861 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 861 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3450 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 3989 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 7439 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3450 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 3989 # number of overall misses -system.cpu.l2cache.overall_misses::total 7439 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 294472000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 294472000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 310569500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 310569500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 80627500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 80627500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 310569500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 375099500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 685669000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 310569500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 375099500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 685669000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 655 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 655 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 2132 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 2132 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 3188 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 3188 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4059 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 4059 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 986 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 986 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 4059 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 4174 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 8233 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 4059 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 4174 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 8233 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981179 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.981179 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.849963 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.849963 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.873225 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.873225 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.849963 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.955678 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.903559 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.849963 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.955678 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.903559 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 94140.664962 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 94140.664962 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 90020.144928 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 90020.144928 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 93644.018583 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 93644.018583 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 90020.144928 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 94033.467034 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 92172.200565 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 90020.144928 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 94033.467034 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 92172.200565 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3128 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 3128 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3450 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3450 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 861 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 861 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3450 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 3989 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7439 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3450 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 3989 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7439 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 263192000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 263192000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 276069500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 276069500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 72017500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 72017500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 276069500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 335209500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 611279000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 276069500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 335209500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 611279000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981179 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981179 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.849963 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.849963 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.873225 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.873225 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.849963 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955678 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.903559 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.849963 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955678 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.903559 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 84140.664962 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 84140.664962 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 80020.144928 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 80020.144928 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 83644.018583 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 83644.018583 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 80020.144928 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84033.467034 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 82172.200565 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 80020.144928 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84033.467034 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 82172.200565 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 11139 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2906 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 64255452000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 5045 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 655 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 2132 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 119 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 3188 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 3188 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 4059 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 986 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10250 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9122 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 19372 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 396224 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 309056 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 705280 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 8233 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 8233 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 8233 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 8356500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6088500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6261000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 7439 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 64255452000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 4311 # Transaction distribution -system.membus.trans_dist::ReadExReq 3128 # Transaction distribution -system.membus.trans_dist::ReadExResp 3128 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 4311 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14878 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14878 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 476096 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 476096 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 7439 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7439 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7439 # Request fanout histogram -system.membus.reqLayer0.occupancy 9229500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 39165500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,366 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/eon -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=Null -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=0:134217727 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simerr --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simerr Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,52 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -getting pixel output filename pixels_out.cook -opening control file chair.control.cook -opening camera file chair.camera -opening surfaces file chair.surfaces -reading data -processing 8parts -Grid measure is 6 by 3.0001 by 6 -cell dimension is 0.863065 -Creating grid for list of length 21 -Grid size = 7 by 4 by 7 -Total occupancy = 236 -reading control stream -reading camera stream -Writing to chair.cook.ppm -calculating 15 by 15 image with 196 samples -col 0. . . -col 1. . . -col 2. . . -col 3. . . -col 4. . . -col 5. . . -col 6. . . -col 7. . . -col 8. . . -col 9. . . -col 10. . . -col 11. . . -col 12. . . -col 13. . . -col 14. . . -Writing to chair.cook.ppm -0 8 14 -1 8 14 -2 8 14 -3 8 14 -4 8 14 -5 8 14 -6 8 14 -7 8 14 -8 8 14 -9 8 14 -10 8 14 -11 8 14 -12 8 14 -13 8 14 -14 8 14 -warn: ignoring syscall sigprocmask(1, ...) diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,17 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 21 2016 14:09:28 -gem5 executing on e108600-lin, pid 4302 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/30.eon/alpha/tru64/simple-timing - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Eon, Version 1.1 -info: Increasing stack size by one page. -OO-style eon Time= 0.566667 -Exiting @ tick 567385356500 because target called exit() diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,555 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.567393 # Number of seconds simulated -sim_ticks 567392530500 # Number of ticks simulated -final_tick 567392530500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1833225 # Simulator instruction rate (inst/s) -host_op_rate 1833225 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2609105944 # Simulator tick rate (ticks/s) -host_mem_usage 258692 # Number of bytes of host memory used -host_seconds 217.47 # Real time elapsed on the host -sim_insts 398664609 # Number of instructions simulated -sim_ops 398664609 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 205120 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 254016 # Number of bytes read from this memory -system.physmem.bytes_read::total 459136 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 205120 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 205120 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3205 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7174 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 361513 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 447690 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 809203 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 361513 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 361513 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 361513 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 447690 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 809203 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 94754490 # DTB read hits -system.cpu.dtb.read_misses 21 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 94754511 # DTB read accesses -system.cpu.dtb.write_hits 73520730 # DTB write hits -system.cpu.dtb.write_misses 35 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 73520765 # DTB write accesses -system.cpu.dtb.data_hits 168275220 # DTB hits -system.cpu.dtb.data_misses 56 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 168275276 # DTB accesses -system.cpu.itb.fetch_hits 398664666 # ITB hits -system.cpu.itb.fetch_misses 173 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 398664839 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 567392530500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1134785061 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 398664609 # Number of instructions committed -system.cpu.committedOps 398664609 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 316365921 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 155295119 # Number of float alu accesses -system.cpu.num_func_calls 16015498 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 25997790 # number of instructions that are conditional controls -system.cpu.num_int_insts 316365921 # number of integer instructions -system.cpu.num_fp_insts 155295119 # number of float instructions -system.cpu.num_int_register_reads 372938779 # number of times the integer registers were read -system.cpu.num_int_register_writes 159335870 # number of times the integer registers were written -system.cpu.num_fp_register_reads 151776196 # number of times the floating registers were read -system.cpu.num_fp_register_writes 100196481 # number of times the floating registers were written -system.cpu.num_mem_refs 168275276 # number of memory refs -system.cpu.num_load_insts 94754511 # Number of load instructions -system.cpu.num_store_insts 73520765 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1134785061 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 44587535 # Number of branches fetched -system.cpu.op_class::No_OpClass 23123356 5.80% 5.80% # Class of executed instruction -system.cpu.op_class::IntAlu 141652567 35.53% 41.33% # Class of executed instruction -system.cpu.op_class::IntMult 2124322 0.53% 41.86% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 41.86% # Class of executed instruction -system.cpu.op_class::FloatAdd 35620060 8.93% 50.80% # Class of executed instruction -system.cpu.op_class::FloatCmp 7072549 1.77% 52.57% # Class of executed instruction -system.cpu.op_class::FloatCvt 2735231 0.69% 53.26% # Class of executed instruction -system.cpu.op_class::FloatMult 16498021 4.14% 57.40% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 57.40% # Class of executed instruction -system.cpu.op_class::FloatDiv 1563283 0.39% 57.79% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 57.79% # Class of executed instruction -system.cpu.op_class::MemRead 46072316 11.56% 69.35% # Class of executed instruction -system.cpu.op_class::MemWrite 30396985 7.62% 76.97% # Class of executed instruction -system.cpu.op_class::FloatMemRead 48682195 12.21% 89.18% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 43123780 10.82% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 398664665 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 764 # number of replacements -system.cpu.dcache.tags.tagsinuse 3288.789389 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168271068 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 4152 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 40527.713873 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3288.789389 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.802927 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.802927 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 3388 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 210 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 3112 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.827148 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 336554592 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 336554592 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 94753540 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 94753540 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73517528 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73517528 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 168271068 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168271068 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168271068 # number of overall hits -system.cpu.dcache.overall_hits::total 168271068 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 950 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 950 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3202 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3202 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 4152 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4152 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4152 # number of overall misses -system.cpu.dcache.overall_misses::total 4152 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 53715500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 53715500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 198735000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 198735000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 252450500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 252450500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 252450500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 252450500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 94754490 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 94754490 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 73520730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 168275220 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168275220 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 168275220 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 168275220 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000010 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000010 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000044 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000044 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56542.631579 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 56542.631579 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62065.896315 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62065.896315 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 60802.143545 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 60802.143545 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 60802.143545 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 60802.143545 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 649 # number of writebacks -system.cpu.dcache.writebacks::total 649 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3202 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4152 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 52765500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 52765500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 195533000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 195533000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 248298500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 248298500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 248298500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 248298500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 55542.631579 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 55542.631579 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61065.896315 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61065.896315 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59802.143545 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 59802.143545 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59802.143545 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 59802.143545 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1769 # number of replacements -system.cpu.icache.tags.tagsinuse 1795.076643 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 398660993 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 3673 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 108538.250204 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1795.076643 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.876502 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.876502 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1904 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 138 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 91 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 251 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1375 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.929688 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 797333005 # Number of tag accesses -system.cpu.icache.tags.data_accesses 797333005 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 398660993 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 398660993 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 398660993 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 398660993 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 398660993 # number of overall hits -system.cpu.icache.overall_hits::total 398660993 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 3673 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 3673 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 3673 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 3673 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 3673 # number of overall misses -system.cpu.icache.overall_misses::total 3673 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 208020000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 208020000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 208020000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 208020000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 208020000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 208020000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 398664666 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 398664666 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 398664666 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 398664666 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 398664666 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 398664666 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000009 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000009 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000009 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000009 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000009 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000009 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56634.903349 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 56634.903349 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 56634.903349 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 56634.903349 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 56634.903349 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 56634.903349 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 1769 # number of writebacks -system.cpu.icache.writebacks::total 1769 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3673 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 3673 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 3673 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 3673 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 3673 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 3673 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 204347000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 204347000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 204347000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 204347000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 204347000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 204347000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000009 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000009 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55634.903349 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55634.903349 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55634.903349 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 55634.903349 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55634.903349 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 55634.903349 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 6481.659208 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3184 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 7174 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.443825 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2770.348214 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 3711.310994 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084544 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.113260 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.197805 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 7174 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 116 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 75 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 392 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 6535 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.218933 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 90038 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 90038 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 649 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 649 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 1769 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1769 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 468 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 468 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 123 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 123 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 468 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 183 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 651 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 468 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 183 # number of overall hits -system.cpu.l2cache.overall_hits::total 651 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 3142 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 3142 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3205 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 3205 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 827 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 827 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3205 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 3969 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 7174 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3205 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses -system.cpu.l2cache.overall_misses::total 7174 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 190095000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 190095000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 193914000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 193914000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 50040500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 50040500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 193914000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 240135500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 434049500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 193914000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 240135500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 434049500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 649 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 649 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 1769 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 1769 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 3202 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 3202 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 3673 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 3673 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 950 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 950 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 3673 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 4152 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 7825 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 3673 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 4152 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 7825 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981262 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.981262 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.872584 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.872584 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.870526 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.870526 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.872584 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.955925 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.916805 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.872584 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.916805 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60501.273074 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60501.273074 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60503.588144 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60503.588144 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60508.464329 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60508.464329 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60503.588144 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60502.771479 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 60503.136326 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60503.588144 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60502.771479 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 60503.136326 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3142 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 3142 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3205 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3205 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 827 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 827 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3205 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 3969 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7174 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3205 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7174 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 158675000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 158675000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 161864000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 161864000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 41770500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 41770500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 161864000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 200445500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 362309500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 161864000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 200445500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 362309500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981262 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.981262 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.872584 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.870526 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.870526 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.916805 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.916805 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50501.273074 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50501.273074 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50503.588144 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50503.588144 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50508.464329 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50508.464329 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50503.588144 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50502.771479 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50503.136326 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50503.588144 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50502.771479 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50503.136326 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 10358 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2533 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 4623 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 649 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1769 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 115 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 3202 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 3202 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 3673 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 950 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9115 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9068 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 18183 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 348288 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 307264 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 655552 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 7825 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 7825 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 7825 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 7597000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 5509500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6228000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 7174 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 567392530500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 4032 # Transaction distribution -system.membus.trans_dist::ReadExReq 3142 # Transaction distribution -system.membus.trans_dist::ReadExResp 3142 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 4032 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14348 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14348 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 459136 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 459136 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 7174 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7174 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7174 # Request fanout histogram -system.membus.reqLayer0.occupancy 7196500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 35870000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/config.ini --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/config.ini Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,877 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=MinorCPU -children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload -branchPred=system.cpu.branchPred -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -decodeCycleInput=true -decodeInputBufferSize=3 -decodeInputWidth=2 -decodeToExecuteForwardDelay=1 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -enableIdling=true -eventq_index=0 -executeAllowEarlyMemoryIssue=true -executeBranchDelay=1 -executeCommitLimit=2 -executeCycleInput=true -executeFuncUnits=system.cpu.executeFuncUnits -executeInputBufferSize=7 -executeInputWidth=2 -executeIssueLimit=2 -executeLSQMaxStoreBufferStoresPerCycle=2 -executeLSQRequestsQueueSize=1 -executeLSQStoreBufferSize=5 -executeLSQTransfersQueueSize=2 -executeMaxAccessesInMemory=2 -executeMemoryCommitLimit=1 -executeMemoryIssueLimit=1 -executeMemoryWidth=0 -executeSetTraceTimeOnCommit=true -executeSetTraceTimeOnIssue=false -fetch1FetchLimit=1 -fetch1LineSnapWidth=0 -fetch1LineWidth=0 -fetch1ToFetch2BackwardDelay=1 -fetch1ToFetch2ForwardDelay=1 -fetch2CycleInput=true -fetch2InputBufferSize=2 -fetch2ToDecodeForwardDelay=1 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -threadPolicy=RoundRobin -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.branchPred] -type=TournamentBP -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -indirectHashGHR=true -indirectHashTargets=true -indirectPathLength=3 -indirectSets=256 -indirectTagSize=16 -indirectWays=2 -instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 -useIndirect=true - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.executeFuncUnits] -type=MinorFUPool -children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 -eventq_index=0 -funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 - -[system.cpu.executeFuncUnits.funcUnits0] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits0.timings - -[system.cpu.executeFuncUnits.funcUnits0.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntAlu - -[system.cpu.executeFuncUnits.funcUnits0.timings] -type=MinorFUTiming -children=opClasses -description=Int -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits1] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits1.timings - -[system.cpu.executeFuncUnits.funcUnits1.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntAlu - -[system.cpu.executeFuncUnits.funcUnits1.timings] -type=MinorFUTiming -children=opClasses -description=Int -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits2] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits2.timings - -[system.cpu.executeFuncUnits.funcUnits2.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntMult - -[system.cpu.executeFuncUnits.funcUnits2.timings] -type=MinorFUTiming -children=opClasses -description=Mul -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses -srcRegsRelativeLats=0 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits3] -type=MinorFU -children=opClasses -cantForwardFromFUIndices= -eventq_index=0 -issueLat=9 -opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses -opLat=9 -timings= - -[system.cpu.executeFuncUnits.funcUnits3.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntDiv - -[system.cpu.executeFuncUnits.funcUnits4] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses -opLat=6 -timings=system.cpu.executeFuncUnits.funcUnits4.timings - -[system.cpu.executeFuncUnits.funcUnits4.opClasses] -type=MinorOpClassSet -children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] -type=MinorOpClass -eventq_index=0 -opClass=FloatAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01] -type=MinorOpClass -eventq_index=0 -opClass=FloatCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02] -type=MinorOpClass -eventq_index=0 -opClass=FloatCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] -type=MinorOpClass -eventq_index=0 -opClass=FloatMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] -type=MinorOpClass -eventq_index=0 -opClass=FloatDiv - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] -type=MinorOpClass -eventq_index=0 -opClass=FloatSqrt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] -type=MinorOpClass -eventq_index=0 -opClass=SimdAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] -type=MinorOpClass -eventq_index=0 -opClass=SimdAddAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] -type=MinorOpClass -eventq_index=0 -opClass=SimdAlu - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] -type=MinorOpClass -eventq_index=0 -opClass=SimdCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] -type=MinorOpClass -eventq_index=0 -opClass=SimdCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] -type=MinorOpClass -eventq_index=0 -opClass=SimdMisc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] -type=MinorOpClass -eventq_index=0 -opClass=SimdMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] -type=MinorOpClass -eventq_index=0 -opClass=SimdMultAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] -type=MinorOpClass -eventq_index=0 -opClass=SimdShift - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] -type=MinorOpClass -eventq_index=0 -opClass=SimdShiftAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] -type=MinorOpClass -eventq_index=0 -opClass=SimdSqrt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatAlu - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatDiv - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMisc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMultAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatSqrt - -[system.cpu.executeFuncUnits.funcUnits4.timings] -type=MinorFUTiming -children=opClasses -description=FloatSimd -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits5] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses -opLat=1 -timings=system.cpu.executeFuncUnits.funcUnits5.timings - -[system.cpu.executeFuncUnits.funcUnits5.opClasses] -type=MinorOpClassSet -children=opClasses0 opClasses1 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 - -[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] -type=MinorOpClass -eventq_index=0 -opClass=MemRead - -[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] -type=MinorOpClass -eventq_index=0 -opClass=MemWrite - -[system.cpu.executeFuncUnits.funcUnits5.timings] -type=MinorFUTiming -children=opClasses -description=Mem -eventq_index=0 -extraAssumedLat=2 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses -srcRegsRelativeLats=1 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits6] -type=MinorFU -children=opClasses -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses -opLat=1 -timings= - -[system.cpu.executeFuncUnits.funcUnits6.opClasses] -type=MinorOpClassSet -children=opClasses0 opClasses1 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 - -[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] -type=MinorOpClass -eventq_index=0 -opClass=IprAccess - -[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] -type=MinorOpClass -eventq_index=0 -opClass=InstPrefetch - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=perlbmk -I. -I lib mdred.makerand.pl -cwd=build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/minor-timing -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/perlbmk -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=0:134217727:0:0:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=6000 -tXPDLL=0 -tXS=270000 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simerr --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simerr Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,8 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(1, ...) -warn: ignoring syscall sigprocmask(1, ...) diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simout --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/simout Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,653 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/minor-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/minor-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:19:44 -gem5 executing on e108600-lin, pid 28059 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/40.perlbmk/alpha/tru64/minor-timing - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -info: Increasing stack size by one page. -637000: 2581848540 -636000: 4117852332 -635000: 329081094 -634000: 545393176 -633000: 3107247613 -632000: 897887463 -631000: 806367477 -630000: 1682157095 -629000: 1188376072 -628000: 4076707785 -627000: 3521684454 -626000: 3144526095 -625000: 1399223384 -624000: 3380494826 -623000: 4086509498 -622000: 1473819475 -621000: 638751284 -620000: 3149483163 -619000: 1489851375 -618000: 1447059134 -617000: 136329498 -616000: 1288452788 -615000: 3949816816 -614000: 318984246 -613000: 1019963195 -612000: 2875280299 -611000: 2997394777 -610000: 4014932807 -609000: 2291235006 -608000: 355450951 -607000: 201970399 -606000: 3626124461 -605000: 2207253273 -604000: 2243886712 -603000: 46791684 -602000: 3176322294 -601000: 1120582847 -600000: 411705454 -599000: 3162380308 -598000: 2732375303 -597000: 1376844609 -596000: 3003023122 -595000: 3869968535 -594000: 1327286554 -593000: 160655029 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-33000: 226200467 -32000: 1765748697 -31000: 1418838964 -30000: 1362983292 -29000: 2877029789 -28000: 583076938 -27000: 2797138728 -26000: 3033567067 -25000: 3902265889 -24000: 3287868661 -23000: 2411740885 -22000: 2747756860 -21000: 1889759908 -20000: 2975722149 -19000: 3027693370 -18000: 2418258302 -17000: 490864179 -16000: 1944489573 -15000: 4212838860 -14000: 1782397962 -13000: 1981080238 -12000: 1213651424 -11000: 1407527546 -10000: 661520991 -9000: 143129551 -8000: 3293448370 -7000: 764314400 -6000: 2246553770 -5000: 2459308892 -4000: 3776833152 -3000: 2208260083 -2000: 2845746745 -1000: 2068042552 -0: 290958364 -Exiting @ tick 521167228000 because target called exit() diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,829 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.521167 # Number of seconds simulated -sim_ticks 521167228000 # Number of ticks simulated -final_tick 521167228000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 492017 # Simulator instruction rate (inst/s) -host_op_rate 492017 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 276083455 # Simulator tick rate (ticks/s) -host_mem_usage 263220 # Number of bytes of host memory used -host_seconds 1887.72 # Real time elapsed on the host -sim_insts 928789150 # Number of instructions simulated -sim_ops 928789150 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 521167228000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 185984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18520896 # Number of bytes read from this memory -system.physmem.bytes_read::total 18706880 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 185984 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 185984 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory -system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2906 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 289389 # Number of read requests responded to by this memory -system.physmem.num_reads::total 292295 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 356861 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 35537338 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 35894199 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 356861 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 356861 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 8188757 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 8188757 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 8188757 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 356861 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 35537338 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 44082956 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 292295 # Number of read requests accepted -system.physmem.writeReqs 66683 # Number of write requests accepted -system.physmem.readBursts 292295 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18686976 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 19904 # Total number of bytes read from write queue -system.physmem.bytesWritten 4265856 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18706880 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 311 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 18028 # Per bank write bursts -system.physmem.perBankRdBursts::1 18369 # Per bank write bursts -system.physmem.perBankRdBursts::2 18396 # Per bank write bursts -system.physmem.perBankRdBursts::3 18341 # Per bank write bursts -system.physmem.perBankRdBursts::4 18255 # Per bank write bursts -system.physmem.perBankRdBursts::5 18258 # Per bank write bursts -system.physmem.perBankRdBursts::6 18325 # Per bank write bursts -system.physmem.perBankRdBursts::7 18297 # Per bank write bursts -system.physmem.perBankRdBursts::8 18227 # Per bank write bursts -system.physmem.perBankRdBursts::9 18235 # Per bank write bursts -system.physmem.perBankRdBursts::10 18232 # Per bank write bursts -system.physmem.perBankRdBursts::11 18375 # Per bank write bursts -system.physmem.perBankRdBursts::12 18268 # Per bank write bursts -system.physmem.perBankRdBursts::13 18134 # Per bank write bursts -system.physmem.perBankRdBursts::14 18057 # Per bank write bursts -system.physmem.perBankRdBursts::15 18187 # Per bank write bursts -system.physmem.perBankWrBursts::0 4123 # Per bank write bursts -system.physmem.perBankWrBursts::1 4164 # Per bank write bursts -system.physmem.perBankWrBursts::2 4221 # Per bank write bursts -system.physmem.perBankWrBursts::3 4157 # Per bank write bursts -system.physmem.perBankWrBursts::4 4141 # Per bank write bursts -system.physmem.perBankWrBursts::5 4097 # Per bank write bursts -system.physmem.perBankWrBursts::6 4260 # Per bank write bursts -system.physmem.perBankWrBursts::7 4224 # Per bank write bursts -system.physmem.perBankWrBursts::8 4233 # Per bank write bursts -system.physmem.perBankWrBursts::9 4192 # Per bank write bursts -system.physmem.perBankWrBursts::10 4150 # Per bank write bursts -system.physmem.perBankWrBursts::11 4241 # Per bank write bursts -system.physmem.perBankWrBursts::12 4098 # Per bank write bursts -system.physmem.perBankWrBursts::13 4100 # Per bank write bursts -system.physmem.perBankWrBursts::14 4096 # Per bank write bursts -system.physmem.perBankWrBursts::15 4157 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 521167139500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 292295 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66683 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 291434 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 537 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 895 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 896 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4047 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4059 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 95989 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 239.106731 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 159.105135 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 271.560992 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 28950 30.16% 30.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 41784 43.53% 73.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 11694 12.18% 85.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2599 2.71% 88.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 913 0.95% 89.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 756 0.79% 90.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 331 0.34% 90.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 447 0.47% 91.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8515 8.87% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 95989 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4054 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 68.753823 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.637200 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 730.740597 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4046 99.80% 99.80% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.83% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::7168-8191 1 0.02% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-15359 5 0.12% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::30720-31743 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4054 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4054 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.441539 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.421503 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.829633 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3159 77.92% 77.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 895 22.08% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4054 # Writes before turning the bus around for reads -system.physmem.totQLat 15194551500 # Total ticks spent queuing -system.physmem.totMemAccLat 20669251500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1459920000 # Total ticks spent in databus transfers -system.physmem.avgQLat 52038.99 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 70788.99 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 35.86 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 8.19 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 35.89 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 8.19 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.34 # Data bus utilization in percentage -system.physmem.busUtilRead 0.28 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.40 # Average write queue length when enqueuing -system.physmem.readRowHits 210474 # Number of row buffer hits during reads -system.physmem.writeRowHits 52167 # Number of row buffer hits during writes -system.physmem.readRowHitRate 72.08 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.23 # Row buffer hit rate for writes -system.physmem.avgGap 1451808.02 # Average gap between requests -system.physmem.pageHitRate 73.23 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 341770380 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 181632495 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1044360660 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 174280140 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 28691395200.000008 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 8105258640 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1605839040 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 57337999170 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 51043667520 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 64046185080 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 212592411075 # Total energy per rank (pJ) -system.physmem_0.averagePower 407.915916 # Core power per rank (mW) -system.physmem_0.totalIdleTime 499165974500 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 3167480750 # Time in different power states -system.physmem_0.memoryStateTime::REF 12206580000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 240498579500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 132926079750 # Time in different power states -system.physmem_0.memoryStateTime::ACT 6626927000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 125741581000 # Time in different power states -system.physmem_1.actEnergy 343648200 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 182645760 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1040405100 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 173653740 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 28803874320.000008 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 8196268830 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1616284320 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 57528037740 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 51141308640 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 63870409695 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 212914803135 # Total energy per rank (pJ) -system.physmem_1.averagePower 408.534516 # Core power per rank (mW) -system.physmem_1.totalIdleTime 498942805750 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 3183963500 # Time in different power states -system.physmem_1.memoryStateTime::REF 12254448000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 239604631750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 133180372750 # Time in different power states -system.physmem_1.memoryStateTime::ACT 6785962500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 126157849500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 521167228000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 123851675 # Number of BP lookups -system.cpu.branchPred.condPredicted 79872959 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 686742 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 102066154 # Number of BTB lookups -system.cpu.branchPred.BTBHits 68190152 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 66.809759 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18697401 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 11223 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 14052181 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 14048615 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 3566 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 11656 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 237539296 # DTB read hits -system.cpu.dtb.read_misses 195211 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 237734507 # DTB read accesses -system.cpu.dtb.write_hits 98305023 # DTB write hits -system.cpu.dtb.write_misses 7170 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 98312193 # DTB write accesses -system.cpu.dtb.data_hits 335844319 # DTB hits -system.cpu.dtb.data_misses 202381 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 336046700 # DTB accesses -system.cpu.itb.fetch_hits 286584578 # ITB hits -system.cpu.itb.fetch_misses 119 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 286584697 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 521167228000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1042334456 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 928789150 # Number of instructions committed -system.cpu.committedOps 928789150 # Number of ops (including micro ops) committed -system.cpu.discardedOps 319598 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.122251 # CPI: cycles per instruction -system.cpu.ipc 0.891066 # IPC: instructions per cycle -system.cpu.op_class_0::No_OpClass 86206875 9.28% 9.28% # Class of committed instruction -system.cpu.op_class_0::IntAlu 486529511 52.38% 61.66% # Class of committed instruction -system.cpu.op_class_0::IntMult 7040 0.00% 61.67% # Class of committed instruction -system.cpu.op_class_0::IntDiv 0 0.00% 61.67% # Class of committed instruction -system.cpu.op_class_0::FloatAdd 13018262 1.40% 63.07% # Class of committed instruction -system.cpu.op_class_0::FloatCmp 3826477 0.41% 63.48% # Class of committed instruction -system.cpu.op_class_0::FloatCvt 3187663 0.34% 63.82% # Class of committed instruction -system.cpu.op_class_0::FloatMult 4 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::FloatMultAcc 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::FloatDiv 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::FloatMisc 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::FloatSqrt 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdAdd 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdAddAcc 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdAlu 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdCmp 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdCvt 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdMisc 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdMult 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdMultAcc 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdShift 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdShiftAcc 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdSqrt 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAdd 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAlu 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCmp 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCvt 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdFloatDiv 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMisc 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMult 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 63.82% # Class of committed instruction -system.cpu.op_class_0::MemRead 228135214 24.56% 88.39% # Class of committed instruction -system.cpu.op_class_0::MemWrite 94471145 10.17% 98.56% # Class of committed instruction -system.cpu.op_class_0::FloatMemRead 9570033 1.03% 99.59% # Class of committed instruction -system.cpu.op_class_0::FloatMemWrite 3836926 0.41% 100.00% # Class of committed instruction -system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 928789150 # Class of committed instruction -system.cpu.tickCycles 962817000 # Number of cycles that the object actually ticked -system.cpu.idleCycles 79517456 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 521167228000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 776559 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.209717 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 320318705 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 780655 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 410.320442 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 968708500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4092.209717 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999075 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999075 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 209 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 957 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1349 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1527 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 643115675 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 643115675 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 521167228000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 222154657 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 222154657 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 98164048 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 98164048 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 320318705 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 320318705 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 320318705 # number of overall hits -system.cpu.dcache.overall_hits::total 320318705 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 711653 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 711653 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 137152 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 137152 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 848805 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 848805 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 848805 # number of overall misses -system.cpu.dcache.overall_misses::total 848805 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 36922839000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 36922839000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10957317000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10957317000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 47880156000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 47880156000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 47880156000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 47880156000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 222866310 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 222866310 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 321167510 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 321167510 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 321167510 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 321167510 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003193 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003193 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001395 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001395 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002643 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002643 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002643 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002643 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51883.205720 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 51883.205720 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79891.777007 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 79891.777007 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 56408.899571 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 56408.899571 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 56408.899571 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 56408.899571 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 88440 # number of writebacks -system.cpu.dcache.writebacks::total 88440 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 9 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68141 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 68141 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 68150 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 68150 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 68150 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 68150 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711644 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 711644 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69011 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 69011 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 780655 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 780655 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 780655 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 780655 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36210490500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 36210490500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5501688000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5501688000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 41712178500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 41712178500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 41712178500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 41712178500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003193 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003193 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000702 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002431 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002431 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002431 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002431 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50882.871913 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50882.871913 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79721.899407 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79721.899407 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53432.282506 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53432.282506 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53432.282506 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53432.282506 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 521167228000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 10581 # number of replacements -system.cpu.icache.tags.tagsinuse 1690.101724 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 286572250 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 12327 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 23247.525756 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1690.101724 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.825245 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.825245 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1746 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1576 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.852539 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 573181483 # Number of tag accesses -system.cpu.icache.tags.data_accesses 573181483 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 521167228000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 286572250 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 286572250 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 286572250 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 286572250 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 286572250 # number of overall hits -system.cpu.icache.overall_hits::total 286572250 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 12328 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 12328 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 12328 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 12328 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 12328 # number of overall misses -system.cpu.icache.overall_misses::total 12328 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 376885500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 376885500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 376885500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 376885500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 376885500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 376885500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 286584578 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 286584578 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 286584578 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 286584578 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 286584578 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 286584578 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000043 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000043 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000043 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000043 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000043 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000043 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30571.503894 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 30571.503894 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 30571.503894 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 30571.503894 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 30571.503894 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 30571.503894 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 10581 # number of writebacks -system.cpu.icache.writebacks::total 10581 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12328 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 12328 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 12328 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 12328 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 12328 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 12328 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 364558500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 364558500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 364558500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 364558500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 364558500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 364558500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000043 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000043 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000043 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29571.585010 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29571.585010 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29571.585010 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 29571.585010 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29571.585010 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 29571.585010 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 521167228000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 259984 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32658.667775 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1287369 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 292752 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.397473 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 3857784000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 51.730334 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 79.865838 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 32527.071603 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.001579 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002437 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.992647 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996663 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 151 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 294 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2875 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29149 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 12933736 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 12933736 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 521167228000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 88440 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 88440 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 10581 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 10581 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 2366 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 2366 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 9421 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 9421 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 488900 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 488900 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 9421 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 491266 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 500687 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 9421 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 491266 # number of overall hits -system.cpu.l2cache.overall_hits::total 500687 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 66645 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 66645 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2907 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 2907 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222744 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 222744 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2907 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 289389 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 292296 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2907 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 289389 # number of overall misses -system.cpu.l2cache.overall_misses::total 292296 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5373301500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5373301500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 247147500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 247147500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 30009565500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 30009565500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 247147500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 35382867000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 35630014500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 247147500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 35382867000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 35630014500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 88440 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 88440 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 10581 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 10581 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 69011 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 69011 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 12328 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 12328 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 711644 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 711644 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 12328 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 780655 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 792983 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 12328 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 780655 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 792983 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.965716 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.965716 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.235805 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.235805 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312999 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312999 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.235805 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.370700 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.368603 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.235805 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.370700 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.368603 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80625.725861 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80625.725861 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 85018.059856 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 85018.059856 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 134726.706443 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 134726.706443 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 85018.059856 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 122267.491162 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 121897.030750 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 85018.059856 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 122267.491162 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 121897.030750 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 66683 # number of writebacks -system.cpu.l2cache.writebacks::total 66683 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 1 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66645 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 66645 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2907 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2907 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222744 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222744 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2907 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 289389 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 292296 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2907 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 289389 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 292296 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4706851500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4706851500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 218087500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 218087500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 27782125500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 27782125500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 218087500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 32488977000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 32707064500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 218087500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 32488977000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 32707064500 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.965716 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965716 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.235805 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.235805 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312999 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312999 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.235805 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370700 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.368603 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.235805 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370700 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.368603 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70625.725861 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70625.725861 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 75021.499828 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 75021.499828 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124726.706443 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124726.706443 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75021.499828 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 112267.491162 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 111897.064962 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75021.499828 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 112267.491162 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 111897.064962 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1580123 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 787140 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2096 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2096 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 521167228000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 723971 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 155123 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 10581 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 881420 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 69011 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 69011 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 12328 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 711644 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 35236 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2337869 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2373105 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1466112 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55622080 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 57088192 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 259984 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 4267712 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1052967 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001991 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.044571 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1050871 99.80% 99.80% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2096 0.20% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1052967 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 889082500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 18490500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1170982500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 550183 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 257888 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 521167228000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 225650 # Transaction distribution -system.membus.trans_dist::WritebackDirty 66683 # Transaction distribution -system.membus.trans_dist::CleanEvict 191205 # Transaction distribution -system.membus.trans_dist::ReadExReq 66645 # Transaction distribution -system.membus.trans_dist::ReadExResp 66645 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 225650 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842478 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 842478 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22974592 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22974592 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 292295 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 292295 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 292295 # Request fanout histogram -system.membus.reqLayer0.occupancy 925387500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1555624500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.3 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,825 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=DerivO3CPU -children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload -LFSTSize=1024 -LQEntries=32 -LSQCheckLoads=true -LSQDepCheckShift=4 -SQEntries=32 -SSITSize=1024 -activity=0 -backComSize=5 -branchPred=system.cpu.branchPred -cachePorts=200 -checker=Null -clk_domain=system.cpu_clk_domain -commitToDecodeDelay=1 -commitToFetchDelay=1 -commitToIEWDelay=1 -commitToRenameDelay=1 -commitWidth=8 -cpu_id=0 -decodeToFetchDelay=1 -decodeToRenameDelay=1 -decodeWidth=8 -default_p_state=UNDEFINED -dispatchWidth=8 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -fetchBufferSize=64 -fetchQueueSize=32 -fetchToDecodeDelay=1 -fetchTrapLatency=1 -fetchWidth=8 -forwardComSize=5 -fuPool=system.cpu.fuPool -function_trace=false -function_trace_start=0 -iewToCommitDelay=1 -iewToDecodeDelay=1 -iewToFetchDelay=1 -iewToRenameDelay=1 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -issueToExecuteDelay=1 -issueWidth=8 -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -needsTSO=false -numIQEntries=64 -numPhysCCRegs=0 -numPhysFloatRegs=256 -numPhysIntRegs=256 -numROBEntries=192 -numRobs=1 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -renameToDecodeDelay=1 -renameToFetchDelay=1 -renameToIEWDelay=2 -renameToROBDelay=1 -renameWidth=8 -simpoint_start_insts= -smtCommitPolicy=RoundRobin -smtFetchPolicy=SingleThread -smtIQPolicy=Partitioned -smtIQThreshold=100 -smtLSQPolicy=Partitioned -smtLSQThreshold=100 -smtNumFetchingThreads=1 -smtROBPolicy=Partitioned -smtROBThreshold=100 -socket_id=0 -squashWidth=8 -store_set_clear_period=250000 -switched_out=false -system=system -tracer=system.cpu.tracer -trapLatency=13 -wbWidth=8 -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.branchPred] -type=TournamentBP -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -indirectHashGHR=true -indirectHashTargets=true -indirectPathLength=3 -indirectSets=256 -indirectTagSize=16 -indirectWays=2 -instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 -useIndirect=true - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.fuPool] -type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 -eventq_index=0 - -[system.cpu.fuPool.FUList0] -type=FUDesc -children=opList -count=6 -eventq_index=0 -opList=system.cpu.fuPool.FUList0.opList - -[system.cpu.fuPool.FUList0.opList] -type=OpDesc -eventq_index=0 -opClass=IntAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList1] -type=FUDesc -children=opList0 opList1 -count=2 -eventq_index=0 -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -eventq_index=0 -opClass=IntMult -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -eventq_index=0 -opClass=IntDiv -opLat=20 -pipelined=false - -[system.cpu.fuPool.FUList2] -type=FUDesc -children=opList0 opList1 opList2 -count=4 -eventq_index=0 -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -eventq_index=0 -opClass=FloatAdd -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -eventq_index=0 -opClass=FloatCmp -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -eventq_index=0 -opClass=FloatCvt -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList3] -type=FUDesc -children=opList0 opList1 opList2 -count=2 -eventq_index=0 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -eventq_index=0 -opClass=FloatMult -opLat=4 -pipelined=true - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -eventq_index=0 -opClass=FloatDiv -opLat=12 -pipelined=false - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -eventq_index=0 -opClass=FloatSqrt -opLat=24 -pipelined=false - -[system.cpu.fuPool.FUList4] -type=FUDesc -children=opList -count=0 -eventq_index=0 -opList=system.cpu.fuPool.FUList4.opList - -[system.cpu.fuPool.FUList4.opList] -type=OpDesc -eventq_index=0 -opClass=MemRead -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5] -type=FUDesc -children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 -count=4 -eventq_index=0 -opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 - -[system.cpu.fuPool.FUList5.opList00] -type=OpDesc -eventq_index=0 -opClass=SimdAdd -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList01] -type=OpDesc -eventq_index=0 -opClass=SimdAddAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList02] -type=OpDesc -eventq_index=0 -opClass=SimdAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList03] -type=OpDesc -eventq_index=0 -opClass=SimdCmp -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList04] -type=OpDesc -eventq_index=0 -opClass=SimdCvt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList05] -type=OpDesc -eventq_index=0 -opClass=SimdMisc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList06] -type=OpDesc -eventq_index=0 -opClass=SimdMult -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList07] -type=OpDesc -eventq_index=0 -opClass=SimdMultAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList08] -type=OpDesc -eventq_index=0 -opClass=SimdShift -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList09] -type=OpDesc -eventq_index=0 -opClass=SimdShiftAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList10] -type=OpDesc -eventq_index=0 -opClass=SimdSqrt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList11] -type=OpDesc -eventq_index=0 -opClass=SimdFloatAdd -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList12] -type=OpDesc -eventq_index=0 -opClass=SimdFloatAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList13] -type=OpDesc -eventq_index=0 -opClass=SimdFloatCmp -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList14] -type=OpDesc -eventq_index=0 -opClass=SimdFloatCvt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList15] -type=OpDesc -eventq_index=0 -opClass=SimdFloatDiv -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList16] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMisc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList17] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMult -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList18] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMultAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList19] -type=OpDesc -eventq_index=0 -opClass=SimdFloatSqrt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList6] -type=FUDesc -children=opList -count=0 -eventq_index=0 -opList=system.cpu.fuPool.FUList6.opList - -[system.cpu.fuPool.FUList6.opList] -type=OpDesc -eventq_index=0 -opClass=MemWrite -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList7] -type=FUDesc -children=opList0 opList1 -count=4 -eventq_index=0 -opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -eventq_index=0 -opClass=MemRead -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList7.opList1] -type=OpDesc -eventq_index=0 -opClass=MemWrite -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList8] -type=FUDesc -children=opList -count=1 -eventq_index=0 -opList=system.cpu.fuPool.FUList8.opList - -[system.cpu.fuPool.FUList8.opList] -type=OpDesc -eventq_index=0 -opClass=IprAccess -opLat=3 -pipelined=false - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=perlbmk -I. -I lib mdred.makerand.pl -cwd=build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/perlbmk -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=0:134217727:0:0:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=6000 -tXPDLL=0 -tXS=270000 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simerr --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simerr Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,8 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(1, ...) -warn: ignoring syscall sigprocmask(1, ...) diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,653 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:19:46 -gem5 executing on e108600-lin, pid 28086 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/40.perlbmk/alpha/tru64/o3-timing - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -info: Increasing stack size by one page. -637000: 2581848540 -636000: 4117852332 -635000: 329081094 -634000: 545393176 -633000: 3107247613 -632000: 897887463 -631000: 806367477 -630000: 1682157095 -629000: 1188376072 -628000: 4076707785 -627000: 3521684454 -626000: 3144526095 -625000: 1399223384 -624000: 3380494826 -623000: 4086509498 -622000: 1473819475 -621000: 638751284 -620000: 3149483163 -619000: 1489851375 -618000: 1447059134 -617000: 136329498 -616000: 1288452788 -615000: 3949816816 -614000: 318984246 -613000: 1019963195 -612000: 2875280299 -611000: 2997394777 -610000: 4014932807 -609000: 2291235006 -608000: 355450951 -607000: 201970399 -606000: 3626124461 -605000: 2207253273 -604000: 2243886712 -603000: 46791684 -602000: 3176322294 -601000: 1120582847 -600000: 411705454 -599000: 3162380308 -598000: 2732375303 -597000: 1376844609 -596000: 3003023122 -595000: 3869968535 -594000: 1327286554 -593000: 160655029 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-33000: 226200467 -32000: 1765748697 -31000: 1418838964 -30000: 1362983292 -29000: 2877029789 -28000: 583076938 -27000: 2797138728 -26000: 3033567067 -25000: 3902265889 -24000: 3287868661 -23000: 2411740885 -22000: 2747756860 -21000: 1889759908 -20000: 2975722149 -19000: 3027693370 -18000: 2418258302 -17000: 490864179 -16000: 1944489573 -15000: 4212838860 -14000: 1782397962 -13000: 1981080238 -12000: 1213651424 -11000: 1407527546 -10000: 661520991 -9000: 143129551 -8000: 3293448370 -7000: 764314400 -6000: 2246553770 -5000: 2459308892 -4000: 3776833152 -3000: 2208260083 -2000: 2845746745 -1000: 2068042552 -0: 290958364 -Exiting @ tick 180964610500 because target called exit() diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,1097 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.180965 # Number of seconds simulated -sim_ticks 180964610500 # Number of ticks simulated -final_tick 180964610500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 431391 # Simulator instruction rate (inst/s) -host_op_rate 431391 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 92673550 # Simulator tick rate (ticks/s) -host_mem_usage 265016 # Number of bytes of host memory used -host_seconds 1952.71 # Real time elapsed on the host -sim_insts 842382029 # Number of instructions simulated -sim_ops 842382029 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 180964610500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 173952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18525056 # Number of bytes read from this memory -system.physmem.bytes_read::total 18699008 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 173952 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 173952 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4267648 # Number of bytes written to this memory -system.physmem.bytes_written::total 4267648 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2718 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 289454 # Number of read requests responded to by this memory -system.physmem.num_reads::total 292172 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66682 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66682 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 961249 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 102368391 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 103329640 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 961249 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 961249 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 23582777 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 23582777 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 23582777 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 961249 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 102368391 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 126912416 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 292172 # Number of read requests accepted -system.physmem.writeReqs 66682 # Number of write requests accepted -system.physmem.readBursts 292172 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 66682 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18678912 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 20096 # Total number of bytes read from write queue -system.physmem.bytesWritten 4266048 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18699008 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4267648 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 314 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 18010 # Per bank write bursts -system.physmem.perBankRdBursts::1 18337 # Per bank write bursts -system.physmem.perBankRdBursts::2 18388 # Per bank write bursts -system.physmem.perBankRdBursts::3 18350 # Per bank write bursts -system.physmem.perBankRdBursts::4 18232 # Per bank write bursts -system.physmem.perBankRdBursts::5 18236 # Per bank write bursts -system.physmem.perBankRdBursts::6 18319 # Per bank write bursts -system.physmem.perBankRdBursts::7 18311 # Per bank write bursts -system.physmem.perBankRdBursts::8 18232 # Per bank write bursts -system.physmem.perBankRdBursts::9 18232 # Per bank write bursts -system.physmem.perBankRdBursts::10 18215 # Per bank write bursts -system.physmem.perBankRdBursts::11 18381 # Per bank write bursts -system.physmem.perBankRdBursts::12 18250 # Per bank write bursts -system.physmem.perBankRdBursts::13 18122 # Per bank write bursts -system.physmem.perBankRdBursts::14 18054 # Per bank write bursts -system.physmem.perBankRdBursts::15 18189 # Per bank write bursts -system.physmem.perBankWrBursts::0 4125 # Per bank write bursts -system.physmem.perBankWrBursts::1 4164 # Per bank write bursts -system.physmem.perBankWrBursts::2 4223 # Per bank write bursts -system.physmem.perBankWrBursts::3 4160 # Per bank write bursts -system.physmem.perBankWrBursts::4 4142 # Per bank write bursts -system.physmem.perBankWrBursts::5 4099 # Per bank write bursts -system.physmem.perBankWrBursts::6 4261 # Per bank write bursts -system.physmem.perBankWrBursts::7 4226 # Per bank write bursts -system.physmem.perBankWrBursts::8 4233 # Per bank write bursts -system.physmem.perBankWrBursts::9 4182 # Per bank write bursts -system.physmem.perBankWrBursts::10 4150 # Per bank write bursts -system.physmem.perBankWrBursts::11 4241 # Per bank write bursts -system.physmem.perBankWrBursts::12 4098 # Per bank write bursts -system.physmem.perBankWrBursts::13 4100 # Per bank write bursts -system.physmem.perBankWrBursts::14 4096 # Per bank write bursts -system.physmem.perBankWrBursts::15 4157 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 180964514000 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 292172 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66682 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 214643 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 47013 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 29962 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 202 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 32 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 884 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 892 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2498 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4058 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4605 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4058 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 95105 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 241.251837 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 155.294089 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 287.548448 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 30650 32.23% 32.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 40922 43.03% 75.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 11798 12.41% 87.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 210 0.22% 87.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 215 0.23% 88.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 192 0.20% 88.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 361 0.38% 88.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1740 1.83% 90.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9017 9.48% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 95105 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4055 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 69.502343 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.667312 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 739.938886 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4047 99.80% 99.80% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.83% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::10240-11263 1 0.02% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::13312-14335 2 0.05% 99.90% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-15359 1 0.02% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::15360-16383 2 0.05% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::30720-31743 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4055 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4055 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.438224 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.418308 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.827243 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3164 78.03% 78.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 7 0.17% 78.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 882 21.75% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 2 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4055 # Writes before turning the bus around for reads -system.physmem.totQLat 10146386000 # Total ticks spent queuing -system.physmem.totMemAccLat 15618723500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1459290000 # Total ticks spent in databus transfers -system.physmem.avgQLat 34764.80 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 53514.80 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 103.22 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 23.57 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 103.33 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 23.58 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.99 # Data bus utilization in percentage -system.physmem.busUtilRead 0.81 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.18 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.36 # Average write queue length when enqueuing -system.physmem.readRowHits 211326 # Number of row buffer hits during reads -system.physmem.writeRowHits 52079 # Number of row buffer hits during writes -system.physmem.readRowHitRate 72.41 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.10 # Row buffer hit rate for writes -system.physmem.avgGap 504284.51 # Average gap between requests -system.physmem.pageHitRate 73.47 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 339192840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 180273885 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1043746620 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 174348000 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 16047635760.000004 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5505974850 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 757646880 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 38977794150 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 26263488480 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 5833398105 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 95148801450 # Total energy per rank (pJ) -system.physmem_0.averagePower 525.786736 # Core power per rank (mW) -system.physmem_0.totalIdleTime 166860797500 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 1403220500 # Time in different power states -system.physmem_0.memoryStateTime::REF 6819966000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 12988477500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 68394436250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 5880505500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 85478004750 # Time in different power states -system.physmem_1.actEnergy 339892560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 180649590 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1040119500 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 173601540 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 16056240720.000004 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5469389970 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 750054720 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 39161701800 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 26293456800 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 5720767110 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 95209751490 # Total energy per rank (pJ) -system.physmem_1.averagePower 526.123579 # Core power per rank (mW) -system.physmem_1.totalIdleTime 166963691000 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 1377166250 # Time in different power states -system.physmem_1.memoryStateTime::REF 6823618000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 12610325250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 68472559500 # Time in different power states -system.physmem_1.memoryStateTime::ACT 5800086000 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 85880855500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 180964610500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 129261099 # Number of BP lookups -system.cpu.branchPred.condPredicted 83045520 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 145257 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 93509067 # Number of BTB lookups -system.cpu.branchPred.BTBHits 70599314 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 75.499966 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 19428116 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1153 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 14846448 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 14825593 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 20855 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 4929 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 243608266 # DTB read hits -system.cpu.dtb.read_misses 267709 # DTB read misses -system.cpu.dtb.read_acv 2 # DTB read access violations -system.cpu.dtb.read_accesses 243875975 # DTB read accesses -system.cpu.dtb.write_hits 101634051 # DTB write hits -system.cpu.dtb.write_misses 39619 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 101673670 # DTB write accesses -system.cpu.dtb.data_hits 345242317 # DTB hits -system.cpu.dtb.data_misses 307328 # DTB misses -system.cpu.dtb.data_acv 2 # DTB access violations -system.cpu.dtb.data_accesses 345549645 # DTB accesses -system.cpu.itb.fetch_hits 116218000 # ITB hits -system.cpu.itb.fetch_misses 1612 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 116219612 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 180964610500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 361929222 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 116540326 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 973682349 # Number of instructions fetch has processed -system.cpu.fetch.Branches 129261099 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 104853023 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 244730119 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 756754 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 840 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 15490 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 28 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 116218000 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 168019 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 361665180 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.692220 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.078693 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 164951201 45.61% 45.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 21852654 6.04% 51.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 15621060 4.32% 55.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 24569981 6.79% 62.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 38586382 10.67% 73.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 15690881 4.34% 77.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 12539815 3.47% 81.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3986839 1.10% 82.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 63866367 17.66% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 361665180 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.357145 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.690256 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 85732697 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 98146269 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 158921683 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 18492948 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 371583 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 11928940 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 7011 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 968666226 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 25451 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 371583 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 93249960 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 12380390 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 15406 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 169252258 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 86395583 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 966785843 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1367 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 25166874 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 51736906 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 7729074 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 666569704 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1151545318 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1114509565 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 37035752 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 638967158 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27602546 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1366 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 87 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 87961020 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 245059340 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 102632582 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 35344831 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4698812 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 877945756 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 74 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 871651299 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 10628 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 35563800 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 10965429 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 37 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 361665180 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.410106 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.146787 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 87893149 24.30% 24.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 61352794 16.96% 41.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 57499290 15.90% 57.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 51081168 14.12% 71.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 45042350 12.45% 83.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 20636672 5.71% 89.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 18146014 5.02% 94.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 10282367 2.84% 97.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 9731376 2.69% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 361665180 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 3586644 18.56% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.56% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11632892 60.20% 78.76% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3008624 15.57% 94.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 913480 4.73% 99.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 182872 0.95% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1276 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 505104722 57.95% 57.95% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7855 0.00% 57.95% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 13297886 1.53% 59.47% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 3826557 0.44% 59.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 3339806 0.38% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 4 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.30% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 234518362 26.91% 87.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 97834915 11.22% 98.43% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 9747446 1.12% 99.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 3972470 0.46% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 871651299 # Type of FU issued -system.cpu.iq.rate 2.408347 # Inst issue rate -system.cpu.iq.fu_busy_cnt 19324512 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.022170 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2054837876 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 876768256 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 835988686 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 69465042 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 36778231 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 34166819 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 855694014 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 35280521 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 65597237 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 7548743 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 5138 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 37089 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 4331382 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2716 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4307 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 371583 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 4257057 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 608088 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 966007295 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 16673 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 245059340 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 102632582 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 74 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 538259 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 83477 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 37089 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 128251 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 15992 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 144243 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 871026557 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 243876094 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 624742 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 88061465 # number of nop insts executed -system.cpu.iew.exec_refs 345550079 # number of memory reference insts executed -system.cpu.iew.exec_branches 127153600 # Number of branches executed -system.cpu.iew.exec_stores 101673985 # Number of stores executed -system.cpu.iew.exec_rate 2.406621 # Inst execution rate -system.cpu.iew.wb_sent 870617196 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 870155505 # cumulative count of insts written-back -system.cpu.iew.wb_producers 525001925 # num instructions producing a value -system.cpu.iew.wb_consumers 821956019 # num instructions consuming a value -system.cpu.iew.wb_rate 2.404215 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.638723 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 31805123 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 138464 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 357537289 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.597177 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 3.046569 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 121797842 34.07% 34.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 81929888 22.92% 56.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 29949089 8.38% 65.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 19779772 5.53% 70.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 17819434 4.98% 75.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7962754 2.23% 78.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 3039675 0.85% 78.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3979990 1.11% 80.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 71278845 19.94% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 357537289 # Number of insts commited each cycle -system.cpu.commit.committedInsts 928587628 # Number of instructions committed -system.cpu.commit.committedOps 928587628 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 335811797 # Number of memory references committed -system.cpu.commit.loads 237510597 # Number of loads committed -system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 123111018 # Number of branches committed -system.cpu.commit.fp_insts 33436273 # Number of committed floating point instructions. -system.cpu.commit.int_insts 821934723 # Number of committed integer instructions. -system.cpu.commit.function_calls 18524163 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 86206875 9.28% 9.28% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 486529510 52.39% 61.68% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 7040 0.00% 61.68% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 61.68% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 13018262 1.40% 63.08% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 3826477 0.41% 63.49% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 3187663 0.34% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 4 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.84% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 227943648 24.55% 88.38% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 94464282 10.17% 98.56% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemRead 9566949 1.03% 99.59% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemWrite 3836918 0.41% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 928587628 # Class of committed instruction -system.cpu.commit.bw_lim_events 71278845 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1244030057 # The number of ROB reads -system.cpu.rob.rob_writes 1924915650 # The number of ROB writes -system.cpu.timesIdled 3145 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 264042 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 842382029 # Number of Instructions Simulated -system.cpu.committedOps 842382029 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.429650 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.429650 # CPI: Total CPI of All Threads -system.cpu.ipc 2.327477 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.327477 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1104175341 # number of integer regfile reads -system.cpu.int_regfile_writes 635597274 # number of integer regfile writes -system.cpu.fp_regfile_reads 36400867 # number of floating regfile reads -system.cpu.fp_regfile_writes 24677538 # number of floating regfile writes -system.cpu.misc_regfile_reads 1 # number of misc regfile reads -system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 180964610500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 776666 # number of replacements -system.cpu.dcache.tags.tagsinuse 4090.964650 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 273860034 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 780762 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 350.759942 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 396630500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4090.964650 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998771 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998771 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 412 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 1011 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2527 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 62 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 553391630 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 553391630 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 180964610500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 176451824 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 176451824 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 97408197 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 97408197 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 13 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 13 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 273860021 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 273860021 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 273860021 # number of overall hits -system.cpu.dcache.overall_hits::total 273860021 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1552397 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1552397 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 893003 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 893003 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2445400 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2445400 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2445400 # number of overall misses -system.cpu.dcache.overall_misses::total 2445400 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 96567477000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 96567477000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 65926918364 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 65926918364 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 162494395364 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 162494395364 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 162494395364 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 162494395364 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 178004221 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 178004221 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 276305421 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 276305421 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 276305421 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 276305421 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008721 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.008721 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009084 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.009084 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.008850 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.008850 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.008850 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.008850 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62205.400423 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62205.400423 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73826.088338 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73826.088338 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 66449.004402 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66449.004402 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 66449.004402 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66449.004402 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 25561 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 192860 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 308 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 519 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 82.990260 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 371.599229 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 88570 # number of writebacks -system.cpu.dcache.writebacks::total 88570 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 840254 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 840254 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 824384 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 824384 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1664638 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1664638 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1664638 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1664638 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712143 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 712143 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 68619 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 68619 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 780762 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 780762 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 780762 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 780762 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30603980500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 30603980500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6049145998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6049145998 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36653126498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 36653126498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36653126498 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 36653126498 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004001 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004001 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000698 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000698 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002826 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002826 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002826 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002826 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 42974.487568 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 42974.487568 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 88155.554555 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 88155.554555 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 46945.325846 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 46945.325846 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 46945.325846 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 46945.325846 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 180964610500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 4618 # number of replacements -system.cpu.icache.tags.tagsinuse 1647.809929 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 116209747 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 6323 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18378.894038 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1647.809929 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.804595 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.804595 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1705 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 80 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1545 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.832520 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 232442323 # Number of tag accesses -system.cpu.icache.tags.data_accesses 232442323 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 180964610500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 116209747 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 116209747 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 116209747 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 116209747 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 116209747 # number of overall hits -system.cpu.icache.overall_hits::total 116209747 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 8253 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 8253 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 8253 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 8253 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 8253 # number of overall misses -system.cpu.icache.overall_misses::total 8253 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 382535999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 382535999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 382535999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 382535999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 382535999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 382535999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 116218000 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 116218000 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 116218000 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 116218000 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 116218000 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 116218000 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000071 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000071 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000071 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000071 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000071 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000071 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46351.144917 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 46351.144917 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 46351.144917 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 46351.144917 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 46351.144917 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 46351.144917 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 811 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 62.384615 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 4618 # number of writebacks -system.cpu.icache.writebacks::total 4618 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1929 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1929 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1929 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1929 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1929 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1929 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6324 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 6324 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 6324 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 6324 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 6324 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 6324 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 282422000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 282422000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 282422000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 282422000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 282422000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 282422000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000054 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000054 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000054 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000054 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000054 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000054 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 44658.760278 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 44658.760278 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 44658.760278 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 44658.760278 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 44658.760278 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 44658.760278 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 180964610500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 259808 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32653.135367 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1275792 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 292576 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.360549 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 1306360000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 44.057169 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 68.938267 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 32540.139931 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.001345 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002104 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.993046 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996495 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 207 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 834 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 8358 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 23070 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 12839536 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 12839536 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 180964610500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 88570 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 88570 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 4618 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 4618 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1993 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1993 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3605 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 3605 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 489315 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 489315 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 3605 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 491308 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 494913 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 3605 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 491308 # number of overall hits -system.cpu.l2cache.overall_hits::total 494913 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 66626 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 66626 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2719 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 2719 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222828 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 222828 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2719 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 289454 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 292173 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2719 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 289454 # number of overall misses -system.cpu.l2cache.overall_misses::total 292173 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5925054000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5925054000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 234987000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 234987000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 24391913000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 24391913000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 234987000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 30316967000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 30551954000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 234987000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 30316967000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 30551954000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 88570 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 88570 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 4618 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 4618 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 68619 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 68619 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 6324 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 6324 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 712143 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 712143 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 6324 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 780762 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 787086 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 6324 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 780762 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 787086 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.970956 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.970956 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.429949 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.429949 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312898 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312898 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.429949 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.370733 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.371208 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.429949 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.370733 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.371208 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88930.057335 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88930.057335 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 86424.052961 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 86424.052961 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 109465.206347 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 109465.206347 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 86424.052961 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 104738.462761 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 104568.026477 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 86424.052961 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 104738.462761 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 104568.026477 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 66682 # number of writebacks -system.cpu.l2cache.writebacks::total 66682 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 1 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66626 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 66626 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2719 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2719 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222828 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222828 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2719 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 289454 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 292173 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2719 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 289454 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 292173 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5258794000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5258794000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 207807000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 207807000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 22163633000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 22163633000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 207807000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 27422427000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 27630234000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 207807000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 27422427000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 27630234000 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.970956 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.970956 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.429949 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.429949 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312898 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312898 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.429949 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370733 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.371208 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.429949 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370733 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.371208 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78930.057335 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78930.057335 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 76427.730783 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 76427.730783 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 99465.206347 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 99465.206347 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76427.730783 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 94738.462761 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 94568.060704 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76427.730783 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 94738.462761 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 94568.060704 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1568370 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 781284 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2012 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2012 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 180964610500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 718466 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 155252 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 4618 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 881222 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 68619 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 68619 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 6324 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 712143 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17265 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2338190 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2355455 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 700224 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55637248 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 56337472 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 259808 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 4267648 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1046894 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001922 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.043797 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1044882 99.81% 99.81% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2012 0.19% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1046894 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 877373000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 9484500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1171143000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 549969 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 257797 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 180964610500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 225546 # Transaction distribution -system.membus.trans_dist::WritebackDirty 66682 # Transaction distribution -system.membus.trans_dist::CleanEvict 191115 # Transaction distribution -system.membus.trans_dist::ReadExReq 66626 # Transaction distribution -system.membus.trans_dist::ReadExResp 66626 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 225546 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 842141 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 842141 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22966656 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22966656 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 292172 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 292172 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 292172 # Request fanout histogram -system.membus.reqLayer0.occupancy 877590500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 1551176250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.9 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,203 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=atomic -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=AtomicSimpleCPU -children=dtb interrupts isa itb tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -fastmem=false -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -simulate_data_stalls=false -simulate_inst_stalls=false -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -width=1 -workload=system.cpu.workload -dcache_port=system.membus.slave[2] -icache_port=system.membus.slave[1] - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=perlbmk -I. -I lib mdred.makerand.pl -cwd=build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/perlbmk -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=Null -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.icache_port system.cpu.dcache_port - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=0:134217727 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,7 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(1, ...) -warn: ignoring syscall sigprocmask(1, ...) diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,653 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic/simout -Redirecting stderr to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 21 2016 14:09:28 -gem5 executing on e108600-lin, pid 4304 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/40.perlbmk/alpha/tru64/simple-atomic - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -info: Increasing stack size by one page. -637000: 2581848540 -636000: 4117852332 -635000: 329081094 -634000: 545393176 -633000: 3107247613 -632000: 897887463 -631000: 806367477 -630000: 1682157095 -629000: 1188376072 -628000: 4076707785 -627000: 3521684454 -626000: 3144526095 -625000: 1399223384 -624000: 3380494826 -623000: 4086509498 -622000: 1473819475 -621000: 638751284 -620000: 3149483163 -619000: 1489851375 -618000: 1447059134 -617000: 136329498 -616000: 1288452788 -615000: 3949816816 -614000: 318984246 -613000: 1019963195 -612000: 2875280299 -611000: 2997394777 -610000: 4014932807 -609000: 2291235006 -608000: 355450951 -607000: 201970399 -606000: 3626124461 -605000: 2207253273 -604000: 2243886712 -603000: 46791684 -602000: 3176322294 -601000: 1120582847 -600000: 411705454 -599000: 3162380308 -598000: 2732375303 -597000: 1376844609 -596000: 3003023122 -595000: 3869968535 -594000: 1327286554 -593000: 160655029 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-33000: 226200467 -32000: 1765748697 -31000: 1418838964 -30000: 1362983292 -29000: 2877029789 -28000: 583076938 -27000: 2797138728 -26000: 3033567067 -25000: 3902265889 -24000: 3287868661 -23000: 2411740885 -22000: 2747756860 -21000: 1889759908 -20000: 2975722149 -19000: 3027693370 -18000: 2418258302 -17000: 490864179 -16000: 1944489573 -15000: 4212838860 -14000: 1782397962 -13000: 1981080238 -12000: 1213651424 -11000: 1407527546 -10000: 661520991 -9000: 143129551 -8000: 3293448370 -7000: 764314400 -6000: 2246553770 -5000: 2459308892 -4000: 3776833152 -3000: 2208260083 -2000: 2845746745 -1000: 2068042552 -0: 290958364 -Exiting @ tick 464394627000 because target called exit() diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,167 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.464395 # Number of seconds simulated -sim_ticks 464394627000 # Number of ticks simulated -final_tick 464394627000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2996785 # Simulator instruction rate (inst/s) -host_op_rate 2996785 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1498717563 # Simulator tick rate (ticks/s) -host_mem_usage 251436 # Number of bytes of host memory used -host_seconds 309.86 # Real time elapsed on the host -sim_insts 928587629 # Number of instructions simulated -sim_ops 928587629 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 464394627000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 3715156600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1657129778 # Number of bytes read from this memory -system.physmem.bytes_read::total 5372286378 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 3715156600 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 3715156600 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 737675461 # Number of bytes written to this memory -system.physmem.bytes_written::total 737675461 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 928789150 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 237510597 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1166299747 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 98301200 # Number of write requests responded to by this memory -system.physmem.num_writes::total 98301200 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7999999104 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3568365527 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 11568364631 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7999999104 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7999999104 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1588466830 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1588466830 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7999999104 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5156832357 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 13156831461 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 464394627000 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 237510597 # DTB read hits -system.cpu.dtb.read_misses 194650 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 237705247 # DTB read accesses -system.cpu.dtb.write_hits 98301200 # DTB write hits -system.cpu.dtb.write_misses 6871 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 98308071 # DTB write accesses -system.cpu.dtb.data_hits 335811797 # DTB hits -system.cpu.dtb.data_misses 201521 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 336013318 # DTB accesses -system.cpu.itb.fetch_hits 928789150 # ITB hits -system.cpu.itb.fetch_misses 105 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 928789255 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 464394627000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 928789255 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 928587629 # Number of instructions committed -system.cpu.committedOps 928587629 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 822136244 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 33439365 # Number of float alu accesses -system.cpu.num_func_calls 37048314 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 79645038 # number of instructions that are conditional controls -system.cpu.num_int_insts 822136244 # number of integer instructions -system.cpu.num_fp_insts 33439365 # number of float instructions -system.cpu.num_int_register_reads 1066359180 # number of times the integer registers were read -system.cpu.num_int_register_writes 614731604 # number of times the integer registers were written -system.cpu.num_fp_register_reads 35725528 # number of times the floating registers were read -system.cpu.num_fp_register_writes 24235554 # number of times the floating registers were written -system.cpu.num_mem_refs 336013318 # number of memory refs -system.cpu.num_load_insts 237705247 # Number of load instructions -system.cpu.num_store_insts 98308071 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 928789255 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 123111018 # Number of branches fetched -system.cpu.op_class::No_OpClass 86206875 9.28% 9.28% # Class of executed instruction -system.cpu.op_class::IntAlu 486529511 52.38% 61.66% # Class of executed instruction -system.cpu.op_class::IntMult 7040 0.00% 61.67% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 61.67% # Class of executed instruction -system.cpu.op_class::FloatAdd 13018262 1.40% 63.07% # Class of executed instruction -system.cpu.op_class::FloatCmp 3826477 0.41% 63.48% # Class of executed instruction -system.cpu.op_class::FloatCvt 3187663 0.34% 63.82% # Class of executed instruction -system.cpu.op_class::FloatMult 4 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::MemRead 228135214 24.56% 88.39% # Class of executed instruction -system.cpu.op_class::MemWrite 94471145 10.17% 98.56% # Class of executed instruction -system.cpu.op_class::FloatMemRead 9570033 1.03% 99.59% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 3836926 0.41% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 928789150 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 464394627000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 1166299747 # Transaction distribution -system.membus.trans_dist::ReadResp 1166299747 # Transaction distribution -system.membus.trans_dist::WriteReq 98301200 # Transaction distribution -system.membus.trans_dist::WriteResp 98301200 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1857578300 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 671623594 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 2529201894 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 3715156600 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 2394805239 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 6109961839 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 1264600947 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1264600947 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 1264600947 # Request fanout histogram - ----------- End Simulation Statistics ---------- diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,366 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=perlbmk -I. -I lib mdred.makerand.pl -cwd=build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/perlbmk -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=Null -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=0:134217727 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simerr --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simerr Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,7 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(1, ...) -warn: ignoring syscall sigprocmask(1, ...) diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,653 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jul 19 2016 12:23:51 -gem5 started Jul 21 2016 14:09:29 -gem5 executing on e108600-lin, pid 4305 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/40.perlbmk/alpha/tru64/simple-timing - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -info: Increasing stack size by one page. -637000: 2581848540 -636000: 4117852332 -635000: 329081094 -634000: 545393176 -633000: 3107247613 -632000: 897887463 -631000: 806367477 -630000: 1682157095 -629000: 1188376072 -628000: 4076707785 -627000: 3521684454 -626000: 3144526095 -625000: 1399223384 -624000: 3380494826 -623000: 4086509498 -622000: 1473819475 -621000: 638751284 -620000: 3149483163 -619000: 1489851375 -618000: 1447059134 -617000: 136329498 -616000: 1288452788 -615000: 3949816816 -614000: 318984246 -613000: 1019963195 -612000: 2875280299 -611000: 2997394777 -610000: 4014932807 -609000: 2291235006 -608000: 355450951 -607000: 201970399 -606000: 3626124461 -605000: 2207253273 -604000: 2243886712 -603000: 46791684 -602000: 3176322294 -601000: 1120582847 -600000: 411705454 -599000: 3162380308 -598000: 2732375303 -597000: 1376844609 -596000: 3003023122 -595000: 3869968535 -594000: 1327286554 -593000: 160655029 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-33000: 226200467 -32000: 1765748697 -31000: 1418838964 -30000: 1362983292 -29000: 2877029789 -28000: 583076938 -27000: 2797138728 -26000: 3033567067 -25000: 3902265889 -24000: 3287868661 -23000: 2411740885 -22000: 2747756860 -21000: 1889759908 -20000: 2975722149 -19000: 3027693370 -18000: 2418258302 -17000: 490864179 -16000: 1944489573 -15000: 4212838860 -14000: 1782397962 -13000: 1981080238 -12000: 1213651424 -11000: 1407527546 -10000: 661520991 -9000: 143129551 -8000: 3293448370 -7000: 764314400 -6000: 2246553770 -5000: 2459308892 -4000: 3776833152 -3000: 2208260083 -2000: 2845746745 -1000: 2068042552 -0: 290958364 -Exiting @ tick 1288319411500 because target called exit() diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,571 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 1.288611 # Number of seconds simulated -sim_ticks 1288611150500 # Number of ticks simulated -final_tick 1288611150500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2016883 # Simulator instruction rate (inst/s) -host_op_rate 2016883 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2798849858 # Simulator tick rate (ticks/s) -host_mem_usage 261432 # Number of bytes of host memory used -host_seconds 460.41 # Real time elapsed on the host -sim_insts 928587629 # Number of instructions simulated -sim_ops 928587629 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 137024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18512320 # Number of bytes read from this memory -system.physmem.bytes_read::total 18649344 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 137024 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 137024 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory -system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2141 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 289255 # Number of read requests responded to by this memory -system.physmem.num_reads::total 291396 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 106335 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 14366103 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14472437 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 106335 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 106335 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3311870 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3311870 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3311870 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 106335 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 14366103 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17784307 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 237510597 # DTB read hits -system.cpu.dtb.read_misses 194650 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 237705247 # DTB read accesses -system.cpu.dtb.write_hits 98301200 # DTB write hits -system.cpu.dtb.write_misses 6871 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 98308071 # DTB write accesses -system.cpu.dtb.data_hits 335811797 # DTB hits -system.cpu.dtb.data_misses 201521 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 336013318 # DTB accesses -system.cpu.itb.fetch_hits 928789151 # ITB hits -system.cpu.itb.fetch_misses 105 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 928789256 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 1288611150500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 2577222301 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 928587629 # Number of instructions committed -system.cpu.committedOps 928587629 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 822136244 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 33439365 # Number of float alu accesses -system.cpu.num_func_calls 37048314 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 79645038 # number of instructions that are conditional controls -system.cpu.num_int_insts 822136244 # number of integer instructions -system.cpu.num_fp_insts 33439365 # number of float instructions -system.cpu.num_int_register_reads 1066359180 # number of times the integer registers were read -system.cpu.num_int_register_writes 614731604 # number of times the integer registers were written -system.cpu.num_fp_register_reads 35725528 # number of times the floating registers were read -system.cpu.num_fp_register_writes 24235554 # number of times the floating registers were written -system.cpu.num_mem_refs 336013318 # number of memory refs -system.cpu.num_load_insts 237705247 # Number of load instructions -system.cpu.num_store_insts 98308071 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 2577222301 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 123111018 # Number of branches fetched -system.cpu.op_class::No_OpClass 86206875 9.28% 9.28% # Class of executed instruction -system.cpu.op_class::IntAlu 486529511 52.38% 61.66% # Class of executed instruction -system.cpu.op_class::IntMult 7040 0.00% 61.67% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 61.67% # Class of executed instruction -system.cpu.op_class::FloatAdd 13018262 1.40% 63.07% # Class of executed instruction -system.cpu.op_class::FloatCmp 3826477 0.41% 63.48% # Class of executed instruction -system.cpu.op_class::FloatCvt 3187663 0.34% 63.82% # Class of executed instruction -system.cpu.op_class::FloatMult 4 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.82% # Class of executed instruction -system.cpu.op_class::MemRead 228135214 24.56% 88.39% # Class of executed instruction -system.cpu.op_class::MemWrite 94471145 10.17% 98.56% # Class of executed instruction -system.cpu.op_class::FloatMemRead 9570033 1.03% 99.59% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 3836926 0.41% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 928789150 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 776432 # number of replacements -system.cpu.dcache.tags.tagsinuse 4094.168779 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 335031269 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 780528 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 429.236708 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1112572500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4094.168779 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999553 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999553 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 467 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 995 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 2427 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 672404122 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 672404122 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 236799083 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 236799083 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 98232186 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 98232186 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 335031269 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 335031269 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 335031269 # number of overall hits -system.cpu.dcache.overall_hits::total 335031269 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 711514 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 711514 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 69014 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 69014 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 780528 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 780528 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 780528 # number of overall misses -system.cpu.dcache.overall_misses::total 780528 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 20380048000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 20380048000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4229584000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4229584000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 24609632000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24609632000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 24609632000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24609632000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 237510597 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 237510597 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 335811797 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 335811797 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 335811797 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 335811797 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002996 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002996 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000702 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000702 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002324 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002324 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002324 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002324 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28643.214329 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28643.214329 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61285.884024 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61285.884024 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31529.467232 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31529.467232 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31529.467232 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31529.467232 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 88841 # number of writebacks -system.cpu.dcache.writebacks::total 88841 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711514 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 711514 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69014 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 69014 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 780528 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 780528 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 780528 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 780528 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19668534000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 19668534000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4160570000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4160570000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23829104000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23829104000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23829104000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23829104000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002996 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002996 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000702 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002324 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002324 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002324 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002324 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27643.214329 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27643.214329 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60285.884024 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60285.884024 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30529.467232 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 30529.467232 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30529.467232 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 30529.467232 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 4618 # number of replacements -system.cpu.icache.tags.tagsinuse 1474.409268 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 928782983 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 6168 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 150580.898671 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1474.409268 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.719926 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.719926 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1550 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 72 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1428 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.756836 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1857584470 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1857584470 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 928782983 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 928782983 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 928782983 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 928782983 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 928782983 # number of overall hits -system.cpu.icache.overall_hits::total 928782983 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 6168 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 6168 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 6168 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 6168 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 6168 # number of overall misses -system.cpu.icache.overall_misses::total 6168 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 187267500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 187267500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 187267500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 187267500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 187267500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 187267500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 928789151 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 928789151 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 928789151 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 928789151 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 928789151 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 928789151 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000007 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000007 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30361.138132 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 30361.138132 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 30361.138132 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 30361.138132 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 30361.138132 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 30361.138132 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 4618 # number of writebacks -system.cpu.icache.writebacks::total 4618 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6168 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 6168 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 6168 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 6168 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 6168 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 6168 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 181099500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 181099500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 181099500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 181099500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 181099500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 181099500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000007 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000007 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000007 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 29361.138132 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 29361.138132 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 29361.138132 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 29361.138132 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 29361.138132 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 29361.138132 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 258865 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32717.214949 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1276112 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 291633 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.375746 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 4209362000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 27.944200 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 47.856544 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 32641.414205 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000853 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001460 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.996137 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.998450 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 226 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 116 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1143 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31170 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 12833601 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 12833601 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 88841 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 88841 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 4618 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 4618 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 2366 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 2366 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 4027 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 4027 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 488907 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 488907 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 4027 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 491273 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 495300 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 4027 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 491273 # number of overall hits -system.cpu.l2cache.overall_hits::total 495300 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 66648 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 66648 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2141 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 2141 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222607 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 222607 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2141 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 289255 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 291396 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2141 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 289255 # number of overall misses -system.cpu.l2cache.overall_misses::total 291396 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4032205000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4032205000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 129556500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 129556500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13467735000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 13467735000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 129556500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 17499940000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 17629496500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 129556500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 17499940000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 17629496500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 88841 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 88841 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 4618 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 4618 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 69014 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 69014 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 6168 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 6168 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 711514 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 711514 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 6168 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 780528 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 786696 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 6168 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 780528 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 786696 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.965717 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.965717 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.347114 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.347114 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312864 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312864 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.347114 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.370589 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.370405 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.347114 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.370589 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.370405 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.015004 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.015004 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60512.143858 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60512.143858 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500.051661 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500.051661 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60512.143858 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500.043214 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 60500.132123 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60512.143858 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500.043214 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 60500.132123 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 66683 # number of writebacks -system.cpu.l2cache.writebacks::total 66683 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 1 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66648 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 66648 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2141 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2141 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222607 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222607 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2141 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 289255 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 291396 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2141 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 289255 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 291396 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3365725000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3365725000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 108146500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 108146500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11241665000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11241665000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 108146500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14607390000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14715536500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 108146500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14607390000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14715536500 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.965717 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965717 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.347114 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.347114 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312864 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312864 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.347114 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.370589 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.370405 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.347114 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.370589 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.370405 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.015004 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.015004 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50512.143858 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50512.143858 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500.051661 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500.051661 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50512.143858 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500.043214 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.132123 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50512.143858 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500.043214 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.132123 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1567746 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 781050 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 1726 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1726 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 717682 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 155524 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 4618 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 879773 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 69014 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 69014 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 6168 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 711514 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16954 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2337488 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2354442 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 690304 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55639616 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 56329920 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 258865 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 4267712 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1045561 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001651 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.040596 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1043835 99.83% 99.83% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1726 0.17% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1045561 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 877332000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 9252000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1170792000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 548536 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 257140 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1288611150500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 224748 # Transaction distribution -system.membus.trans_dist::WritebackDirty 66683 # Transaction distribution -system.membus.trans_dist::CleanEvict 190457 # Transaction distribution -system.membus.trans_dist::ReadExReq 66648 # Transaction distribution -system.membus.trans_dist::ReadExResp 66648 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 224748 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839932 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 839932 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22917056 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22917056 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 291396 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 291396 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 291396 # Request fanout histogram -system.membus.reqLayer0.occupancy 815280500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 1456980000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/config.ini Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,877 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=MinorCPU -children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload -branchPred=system.cpu.branchPred -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -decodeCycleInput=true -decodeInputBufferSize=3 -decodeInputWidth=2 -decodeToExecuteForwardDelay=1 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -enableIdling=true -eventq_index=0 -executeAllowEarlyMemoryIssue=true -executeBranchDelay=1 -executeCommitLimit=2 -executeCycleInput=true -executeFuncUnits=system.cpu.executeFuncUnits -executeInputBufferSize=7 -executeInputWidth=2 -executeIssueLimit=2 -executeLSQMaxStoreBufferStoresPerCycle=2 -executeLSQRequestsQueueSize=1 -executeLSQStoreBufferSize=5 -executeLSQTransfersQueueSize=2 -executeMaxAccessesInMemory=2 -executeMemoryCommitLimit=1 -executeMemoryIssueLimit=1 -executeMemoryWidth=0 -executeSetTraceTimeOnCommit=true -executeSetTraceTimeOnIssue=false -fetch1FetchLimit=1 -fetch1LineSnapWidth=0 -fetch1LineWidth=0 -fetch1ToFetch2BackwardDelay=1 -fetch1ToFetch2ForwardDelay=1 -fetch2CycleInput=true -fetch2InputBufferSize=2 -fetch2ToDecodeForwardDelay=1 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -threadPolicy=RoundRobin -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.branchPred] -type=TournamentBP -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -indirectHashGHR=true -indirectHashTargets=true -indirectPathLength=3 -indirectSets=256 -indirectTagSize=16 -indirectWays=2 -instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 -useIndirect=true - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.executeFuncUnits] -type=MinorFUPool -children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 -eventq_index=0 -funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 - -[system.cpu.executeFuncUnits.funcUnits0] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits0.timings - -[system.cpu.executeFuncUnits.funcUnits0.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntAlu - -[system.cpu.executeFuncUnits.funcUnits0.timings] -type=MinorFUTiming -children=opClasses -description=Int -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits1] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits1.timings - -[system.cpu.executeFuncUnits.funcUnits1.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntAlu - -[system.cpu.executeFuncUnits.funcUnits1.timings] -type=MinorFUTiming -children=opClasses -description=Int -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits2] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits2.timings - -[system.cpu.executeFuncUnits.funcUnits2.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntMult - -[system.cpu.executeFuncUnits.funcUnits2.timings] -type=MinorFUTiming -children=opClasses -description=Mul -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses -srcRegsRelativeLats=0 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits3] -type=MinorFU -children=opClasses -cantForwardFromFUIndices= -eventq_index=0 -issueLat=9 -opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses -opLat=9 -timings= - -[system.cpu.executeFuncUnits.funcUnits3.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntDiv - -[system.cpu.executeFuncUnits.funcUnits4] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses -opLat=6 -timings=system.cpu.executeFuncUnits.funcUnits4.timings - -[system.cpu.executeFuncUnits.funcUnits4.opClasses] -type=MinorOpClassSet -children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] -type=MinorOpClass -eventq_index=0 -opClass=FloatAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01] -type=MinorOpClass -eventq_index=0 -opClass=FloatCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02] -type=MinorOpClass -eventq_index=0 -opClass=FloatCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] -type=MinorOpClass -eventq_index=0 -opClass=FloatMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] -type=MinorOpClass -eventq_index=0 -opClass=FloatDiv - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] -type=MinorOpClass -eventq_index=0 -opClass=FloatSqrt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] -type=MinorOpClass -eventq_index=0 -opClass=SimdAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] -type=MinorOpClass -eventq_index=0 -opClass=SimdAddAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] -type=MinorOpClass -eventq_index=0 -opClass=SimdAlu - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] -type=MinorOpClass -eventq_index=0 -opClass=SimdCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] -type=MinorOpClass -eventq_index=0 -opClass=SimdCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] -type=MinorOpClass -eventq_index=0 -opClass=SimdMisc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] -type=MinorOpClass -eventq_index=0 -opClass=SimdMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] -type=MinorOpClass -eventq_index=0 -opClass=SimdMultAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] -type=MinorOpClass -eventq_index=0 -opClass=SimdShift - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] -type=MinorOpClass -eventq_index=0 -opClass=SimdShiftAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] -type=MinorOpClass -eventq_index=0 -opClass=SimdSqrt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatAlu - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatDiv - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMisc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMultAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatSqrt - -[system.cpu.executeFuncUnits.funcUnits4.timings] -type=MinorFUTiming -children=opClasses -description=FloatSimd -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits5] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses -opLat=1 -timings=system.cpu.executeFuncUnits.funcUnits5.timings - -[system.cpu.executeFuncUnits.funcUnits5.opClasses] -type=MinorOpClassSet -children=opClasses0 opClasses1 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 - -[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] -type=MinorOpClass -eventq_index=0 -opClass=MemRead - -[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] -type=MinorOpClass -eventq_index=0 -opClass=MemWrite - -[system.cpu.executeFuncUnits.funcUnits5.timings] -type=MinorFUTiming -children=opClasses -description=Mem -eventq_index=0 -extraAssumedLat=2 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses -srcRegsRelativeLats=1 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits6] -type=MinorFU -children=opClasses -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses -opLat=1 -timings= - -[system.cpu.executeFuncUnits.funcUnits6.opClasses] -type=MinorOpClassSet -children=opClasses0 opClasses1 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 - -[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] -type=MinorOpClass -eventq_index=0 -opClass=IprAccess - -[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] -type=MinorOpClass -eventq_index=0 -opClass=InstPrefetch - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=vortex lendian.raw -cwd=build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/minor-timing -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/vortex -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=0:134217727:0:0:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=6000 -tXPDLL=0 -tXS=270000 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simerr --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simerr Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,7 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(1, ...) diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simout --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/simout Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,14 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/minor-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/minor-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:19:45 -gem5 executing on e108600-lin, pid 28063 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/50.vortex/alpha/tru64/minor-timing - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Exiting @ tick 61709224000 because target called exit() diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,829 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.061709 # Number of seconds simulated -sim_ticks 61709224000 # Number of ticks simulated -final_tick 61709224000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 484192 # Simulator instruction rate (inst/s) -host_op_rate 484192 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 337853764 # Simulator tick rate (ticks/s) -host_mem_usage 263376 # Number of bytes of host memory used -host_seconds 182.65 # Real time elapsed on the host -sim_insts 88438073 # Number of instructions simulated -sim_ops 88438073 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 438336 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10169024 # Number of bytes read from this memory -system.physmem.bytes_read::total 10607360 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 438336 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 438336 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7376064 # Number of bytes written to this memory -system.physmem.bytes_written::total 7376064 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 6849 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158891 # Number of read requests responded to by this memory -system.physmem.num_reads::total 165740 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115251 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115251 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7103249 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 164789368 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 171892617 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7103249 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7103249 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 119529359 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 119529359 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 119529359 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7103249 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 164789368 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 291421976 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 165740 # Number of read requests accepted -system.physmem.writeReqs 115251 # Number of write requests accepted -system.physmem.readBursts 165740 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 115251 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10606656 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 704 # Total number of bytes read from write queue -system.physmem.bytesWritten 7374400 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10607360 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7376064 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 11 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10345 # Per bank write bursts -system.physmem.perBankRdBursts::1 10387 # Per bank write bursts -system.physmem.perBankRdBursts::2 10224 # Per bank write bursts -system.physmem.perBankRdBursts::3 10068 # Per bank write bursts -system.physmem.perBankRdBursts::4 10353 # Per bank write bursts -system.physmem.perBankRdBursts::5 10360 # Per bank write bursts -system.physmem.perBankRdBursts::6 9794 # Per bank write bursts -system.physmem.perBankRdBursts::7 10230 # Per bank write bursts -system.physmem.perBankRdBursts::8 10568 # Per bank write bursts -system.physmem.perBankRdBursts::9 10626 # Per bank write bursts -system.physmem.perBankRdBursts::10 10568 # Per bank write bursts -system.physmem.perBankRdBursts::11 10241 # Per bank write bursts -system.physmem.perBankRdBursts::12 10306 # Per bank write bursts -system.physmem.perBankRdBursts::13 10592 # Per bank write bursts -system.physmem.perBankRdBursts::14 10494 # Per bank write bursts -system.physmem.perBankRdBursts::15 10573 # Per bank write bursts -system.physmem.perBankWrBursts::0 7166 # Per bank write bursts -system.physmem.perBankWrBursts::1 7281 # Per bank write bursts -system.physmem.perBankWrBursts::2 7303 # Per bank write bursts -system.physmem.perBankWrBursts::3 7012 # Per bank write bursts -system.physmem.perBankWrBursts::4 7145 # Per bank write bursts -system.physmem.perBankWrBursts::5 7305 # Per bank write bursts -system.physmem.perBankWrBursts::6 6890 # Per bank write bursts -system.physmem.perBankWrBursts::7 7164 # Per bank write bursts -system.physmem.perBankWrBursts::8 7246 # Per bank write bursts -system.physmem.perBankWrBursts::9 7071 # Per bank write bursts -system.physmem.perBankWrBursts::10 7213 # Per bank write bursts -system.physmem.perBankWrBursts::11 7126 # Per bank write bursts -system.physmem.perBankWrBursts::12 7072 # Per bank write bursts -system.physmem.perBankWrBursts::13 7397 # Per bank write bursts -system.physmem.perBankWrBursts::14 7351 # Per bank write bursts -system.physmem.perBankWrBursts::15 7483 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 61709200500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 165740 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 115251 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 163346 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2365 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 469 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 476 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 7138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 47213 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 380.822570 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 228.196479 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 355.752308 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14428 30.56% 30.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 9567 20.26% 50.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5069 10.74% 61.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3353 7.10% 68.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2454 5.20% 73.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2040 4.32% 78.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1589 3.37% 81.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1422 3.01% 84.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7291 15.44% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 47213 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7138 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.216307 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 17.901212 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 310.822959 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 7136 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::25600-26623 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7138 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7138 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.142477 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.134126 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.540383 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6653 93.21% 93.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 14 0.20% 93.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 420 5.88% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 44 0.62% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 4 0.06% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 3 0.04% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7138 # Writes before turning the bus around for reads -system.physmem.totQLat 3617300750 # Total ticks spent queuing -system.physmem.totMemAccLat 6724719500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 828645000 # Total ticks spent in databus transfers -system.physmem.avgQLat 21826.60 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 40576.60 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 171.88 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 119.50 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 171.89 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 119.53 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.28 # Data bus utilization in percentage -system.physmem.busUtilRead 1.34 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.93 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.15 # Average write queue length when enqueuing -system.physmem.readRowHits 144262 # Number of row buffer hits during reads -system.physmem.writeRowHits 89468 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.05 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 77.63 # Row buffer hit rate for writes -system.physmem.avgGap 219612.73 # Average gap between requests -system.physmem.pageHitRate 83.18 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 162377880 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 86290710 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 583773540 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 298928520 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 2622054240.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2778043200 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 161720640 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 5591253690 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 3285210240 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 8699758440 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 24270201780 # Total energy per rank (pJ) -system.physmem_0.averagePower 393.299410 # Core power per rank (mW) -system.physmem_0.totalIdleTime 55193955500 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 247892750 # Time in different power states -system.physmem_0.memoryStateTime::REF 1114164000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 34377330500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 8555206500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 5153163500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 12261466750 # Time in different power states -system.physmem_1.actEnergy 174801480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 92882625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 599531520 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 302545980 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 2751743280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2889138480 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 174840000 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 5978432460 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 3387317760 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 8384762130 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 24736693185 # Total energy per rank (pJ) -system.physmem_1.averagePower 400.858918 # Core power per rank (mW) -system.physmem_1.totalIdleTime 54916270500 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 273467750 # Time in different power states -system.physmem_1.memoryStateTime::REF 1169204000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 32984792500 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 8821175750 # Time in different power states -system.physmem_1.memoryStateTime::ACT 5350059500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 13110524500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 14696527 # Number of BP lookups -system.cpu.branchPred.condPredicted 9501310 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 386077 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10213333 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6368117 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 62.351017 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1712242 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 84707 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 37535 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 31848 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 5687 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 7575 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20579387 # DTB read hits -system.cpu.dtb.read_misses 95377 # DTB read misses -system.cpu.dtb.read_acv 10 # DTB read access violations -system.cpu.dtb.read_accesses 20674764 # DTB read accesses -system.cpu.dtb.write_hits 14666029 # DTB write hits -system.cpu.dtb.write_misses 8840 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14674869 # DTB write accesses -system.cpu.dtb.data_hits 35245416 # DTB hits -system.cpu.dtb.data_misses 104217 # DTB misses -system.cpu.dtb.data_acv 10 # DTB access violations -system.cpu.dtb.data_accesses 35349633 # DTB accesses -system.cpu.itb.fetch_hits 25650137 # ITB hits -system.cpu.itb.fetch_misses 5179 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 25655316 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 61709224000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 123418448 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 88438073 # Number of instructions committed -system.cpu.committedOps 88438073 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1086074 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.395535 # CPI: cycles per instruction -system.cpu.ipc 0.716571 # IPC: instructions per cycle -system.cpu.op_class_0::No_OpClass 8748916 9.89% 9.89% # Class of committed instruction -system.cpu.op_class_0::IntAlu 44394799 50.20% 60.09% # Class of committed instruction -system.cpu.op_class_0::IntMult 41101 0.05% 60.14% # Class of committed instruction -system.cpu.op_class_0::IntDiv 0 0.00% 60.14% # Class of committed instruction -system.cpu.op_class_0::FloatAdd 114304 0.13% 60.27% # Class of committed instruction -system.cpu.op_class_0::FloatCmp 84 0.00% 60.27% # Class of committed instruction -system.cpu.op_class_0::FloatCvt 113640 0.13% 60.40% # Class of committed instruction -system.cpu.op_class_0::FloatMult 50 0.00% 60.40% # Class of committed instruction -system.cpu.op_class_0::FloatMultAcc 0 0.00% 60.40% # Class of committed instruction -system.cpu.op_class_0::FloatDiv 37764 0.04% 60.44% # Class of committed instruction -system.cpu.op_class_0::FloatMisc 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::FloatSqrt 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdAdd 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdAddAcc 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdAlu 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdCmp 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdCvt 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdMisc 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdMult 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdMultAcc 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdShift 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdShiftAcc 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdSqrt 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAdd 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAlu 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCmp 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCvt 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdFloatDiv 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMisc 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMult 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 60.44% # Class of committed instruction -system.cpu.op_class_0::MemRead 20366476 23.03% 83.47% # Class of committed instruction -system.cpu.op_class_0::MemWrite 14619024 16.53% 100.00% # Class of committed instruction -system.cpu.op_class_0::FloatMemRead 310 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::FloatMemWrite 1605 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 88438073 # Class of committed instruction -system.cpu.tickCycles 92007988 # Number of cycles that the object actually ticked -system.cpu.idleCycles 31410460 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 200809 # number of replacements -system.cpu.dcache.tags.tagsinuse 4069.967962 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 34647996 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 204905 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 169.092975 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 742257500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4069.967962 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993645 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993645 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 592 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3460 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 70184119 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 70184119 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 20314695 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20314695 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 14333301 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 14333301 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 34647996 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34647996 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34647996 # number of overall hits -system.cpu.dcache.overall_hits::total 34647996 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 61535 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 61535 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 280076 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 280076 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 341611 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 341611 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 341611 # number of overall misses -system.cpu.dcache.overall_misses::total 341611 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3155082500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3155082500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 23960624000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 23960624000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 27115706500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 27115706500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 27115706500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 27115706500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20376230 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20376230 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 34989607 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 34989607 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 34989607 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 34989607 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003020 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003020 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019166 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.019166 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009763 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009763 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009763 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009763 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51272.974730 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 51272.974730 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 85550.436310 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 85550.436310 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 79375.975891 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 79375.975891 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 79375.975891 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 79375.975891 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 168117 # number of writebacks -system.cpu.dcache.writebacks::total 168117 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 197 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 197 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 136509 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 136509 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 136706 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 136706 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 136706 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 136706 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61338 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 61338 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143567 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143567 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 204905 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 204905 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 204905 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 204905 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3088657500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3088657500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12182218500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12182218500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15270876000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 15270876000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15270876000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 15270876000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009824 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009824 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005856 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005856 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005856 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005856 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50354.714859 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50354.714859 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 84853.890518 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 84853.890518 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74526.614773 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 74526.614773 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74526.614773 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 74526.614773 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 153962 # number of replacements -system.cpu.icache.tags.tagsinuse 1929.475732 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 25494126 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 156010 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 163.413409 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 43906590500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1929.475732 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.942127 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.942127 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1010 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 824 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 51456284 # Number of tag accesses -system.cpu.icache.tags.data_accesses 51456284 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 25494126 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25494126 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25494126 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25494126 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25494126 # number of overall hits -system.cpu.icache.overall_hits::total 25494126 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 156011 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 156011 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 156011 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 156011 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 156011 # number of overall misses -system.cpu.icache.overall_misses::total 156011 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2690499000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2690499000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2690499000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2690499000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2690499000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2690499000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25650137 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25650137 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25650137 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25650137 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25650137 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25650137 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.006082 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.006082 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.006082 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.006082 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.006082 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.006082 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17245.572428 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 17245.572428 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 17245.572428 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 17245.572428 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 17245.572428 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 17245.572428 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 153962 # number of writebacks -system.cpu.icache.writebacks::total 153962 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 156011 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 156011 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 156011 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 156011 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 156011 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 156011 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2534489000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 2534489000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2534489000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 2534489000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2534489000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 2534489000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006082 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006082 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006082 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006082 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006082 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006082 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16245.578837 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16245.578837 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16245.578837 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 16245.578837 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16245.578837 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 16245.578837 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 135280 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31691.220276 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 547521 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 168048 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 3.258123 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 14447297000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 710.430921 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1986.776331 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 28994.013023 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.021681 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.060632 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.884827 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.967139 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 928 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 8856 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 22759 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 103 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 5893544 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 5893544 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 168117 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 168117 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 153962 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 153962 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 12659 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 12659 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 149161 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 149161 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 33355 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 33355 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 149161 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 46014 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 195175 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 149161 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 46014 # number of overall hits -system.cpu.l2cache.overall_hits::total 195175 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 130908 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 130908 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 6850 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 6850 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 27983 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 27983 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 6850 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 158891 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 165741 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 6850 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 158891 # number of overall misses -system.cpu.l2cache.overall_misses::total 165741 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11833894500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 11833894500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 734127500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 734127500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2646160500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 2646160500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 734127500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 14480055000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 15214182500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 734127500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 14480055000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 15214182500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 168117 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 168117 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 153962 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 153962 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 143567 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 143567 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 156011 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 156011 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 61338 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 61338 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 156011 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 204905 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 360916 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 156011 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 204905 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 360916 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911825 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.911825 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.043907 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.043907 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.456210 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.456210 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.043907 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.775437 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.459223 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.043907 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.775437 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.459223 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90398.558530 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90398.558530 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 107171.897810 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 107171.897810 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 94563.145481 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 94563.145481 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 107171.897810 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 91132.002442 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 91794.924008 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 107171.897810 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 91132.002442 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 91794.924008 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 115252 # number of writebacks -system.cpu.l2cache.writebacks::total 115252 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 117 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 117 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130908 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 130908 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 6850 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 6850 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 27983 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 27983 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 6850 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 158891 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 165741 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 6850 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 158891 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 165741 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10524814500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10524814500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 665637500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 665637500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2366330500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2366330500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 665637500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12891145000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 13556782500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 665637500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12891145000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 13556782500 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911825 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911825 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.043907 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.043907 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.456210 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.456210 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.043907 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775437 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.459223 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.043907 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775437 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.459223 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80398.558530 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80398.558530 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 97173.357664 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 97173.357664 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 84563.145481 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 84563.145481 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 97173.357664 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81132.002442 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 81794.984343 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 97173.357664 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81132.002442 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81794.984343 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 715687 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 354771 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 4259 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 4259 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 217348 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 283369 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 153962 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 52720 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143567 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143567 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 156011 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 61338 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 465983 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 610619 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1076602 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19838208 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23873408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 43711616 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 135280 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 7376128 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 496196 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.008583 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.092248 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 491937 99.14% 99.14% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4259 0.86% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 496196 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 679922500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 234015499 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 307361991 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 296877 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 131137 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 61709224000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 34832 # Transaction distribution -system.membus.trans_dist::WritebackDirty 115251 # Transaction distribution -system.membus.trans_dist::CleanEvict 15886 # Transaction distribution -system.membus.trans_dist::ReadExReq 130908 # Transaction distribution -system.membus.trans_dist::ReadExResp 130908 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 34832 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 462617 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 462617 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17983424 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17983424 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 165740 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 165740 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 165740 # Request fanout histogram -system.membus.reqLayer0.occupancy 829256000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 875104000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.4 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,825 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=DerivO3CPU -children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload -LFSTSize=1024 -LQEntries=32 -LSQCheckLoads=true -LSQDepCheckShift=4 -SQEntries=32 -SSITSize=1024 -activity=0 -backComSize=5 -branchPred=system.cpu.branchPred -cachePorts=200 -checker=Null -clk_domain=system.cpu_clk_domain -commitToDecodeDelay=1 -commitToFetchDelay=1 -commitToIEWDelay=1 -commitToRenameDelay=1 -commitWidth=8 -cpu_id=0 -decodeToFetchDelay=1 -decodeToRenameDelay=1 -decodeWidth=8 -default_p_state=UNDEFINED -dispatchWidth=8 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -fetchBufferSize=64 -fetchQueueSize=32 -fetchToDecodeDelay=1 -fetchTrapLatency=1 -fetchWidth=8 -forwardComSize=5 -fuPool=system.cpu.fuPool -function_trace=false -function_trace_start=0 -iewToCommitDelay=1 -iewToDecodeDelay=1 -iewToFetchDelay=1 -iewToRenameDelay=1 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -issueToExecuteDelay=1 -issueWidth=8 -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -needsTSO=false -numIQEntries=64 -numPhysCCRegs=0 -numPhysFloatRegs=256 -numPhysIntRegs=256 -numROBEntries=192 -numRobs=1 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -renameToDecodeDelay=1 -renameToFetchDelay=1 -renameToIEWDelay=2 -renameToROBDelay=1 -renameWidth=8 -simpoint_start_insts= -smtCommitPolicy=RoundRobin -smtFetchPolicy=SingleThread -smtIQPolicy=Partitioned -smtIQThreshold=100 -smtLSQPolicy=Partitioned -smtLSQThreshold=100 -smtNumFetchingThreads=1 -smtROBPolicy=Partitioned -smtROBThreshold=100 -socket_id=0 -squashWidth=8 -store_set_clear_period=250000 -switched_out=false -system=system -tracer=system.cpu.tracer -trapLatency=13 -wbWidth=8 -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.branchPred] -type=TournamentBP -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -indirectHashGHR=true -indirectHashTargets=true -indirectPathLength=3 -indirectSets=256 -indirectTagSize=16 -indirectWays=2 -instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 -useIndirect=true - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.fuPool] -type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 -eventq_index=0 - -[system.cpu.fuPool.FUList0] -type=FUDesc -children=opList -count=6 -eventq_index=0 -opList=system.cpu.fuPool.FUList0.opList - -[system.cpu.fuPool.FUList0.opList] -type=OpDesc -eventq_index=0 -opClass=IntAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList1] -type=FUDesc -children=opList0 opList1 -count=2 -eventq_index=0 -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -eventq_index=0 -opClass=IntMult -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -eventq_index=0 -opClass=IntDiv -opLat=20 -pipelined=false - -[system.cpu.fuPool.FUList2] -type=FUDesc -children=opList0 opList1 opList2 -count=4 -eventq_index=0 -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -eventq_index=0 -opClass=FloatAdd -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -eventq_index=0 -opClass=FloatCmp -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -eventq_index=0 -opClass=FloatCvt -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList3] -type=FUDesc -children=opList0 opList1 opList2 -count=2 -eventq_index=0 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -eventq_index=0 -opClass=FloatMult -opLat=4 -pipelined=true - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -eventq_index=0 -opClass=FloatDiv -opLat=12 -pipelined=false - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -eventq_index=0 -opClass=FloatSqrt -opLat=24 -pipelined=false - -[system.cpu.fuPool.FUList4] -type=FUDesc -children=opList -count=0 -eventq_index=0 -opList=system.cpu.fuPool.FUList4.opList - -[system.cpu.fuPool.FUList4.opList] -type=OpDesc -eventq_index=0 -opClass=MemRead -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5] -type=FUDesc -children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 -count=4 -eventq_index=0 -opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 - -[system.cpu.fuPool.FUList5.opList00] -type=OpDesc -eventq_index=0 -opClass=SimdAdd -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList01] -type=OpDesc -eventq_index=0 -opClass=SimdAddAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList02] -type=OpDesc -eventq_index=0 -opClass=SimdAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList03] -type=OpDesc -eventq_index=0 -opClass=SimdCmp -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList04] -type=OpDesc -eventq_index=0 -opClass=SimdCvt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList05] -type=OpDesc -eventq_index=0 -opClass=SimdMisc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList06] -type=OpDesc -eventq_index=0 -opClass=SimdMult -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList07] -type=OpDesc -eventq_index=0 -opClass=SimdMultAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList08] -type=OpDesc -eventq_index=0 -opClass=SimdShift -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList09] -type=OpDesc -eventq_index=0 -opClass=SimdShiftAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList10] -type=OpDesc -eventq_index=0 -opClass=SimdSqrt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList11] -type=OpDesc -eventq_index=0 -opClass=SimdFloatAdd -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList12] -type=OpDesc -eventq_index=0 -opClass=SimdFloatAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList13] -type=OpDesc -eventq_index=0 -opClass=SimdFloatCmp -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList14] -type=OpDesc -eventq_index=0 -opClass=SimdFloatCvt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList15] -type=OpDesc -eventq_index=0 -opClass=SimdFloatDiv -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList16] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMisc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList17] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMult -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList18] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMultAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList19] -type=OpDesc -eventq_index=0 -opClass=SimdFloatSqrt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList6] -type=FUDesc -children=opList -count=0 -eventq_index=0 -opList=system.cpu.fuPool.FUList6.opList - -[system.cpu.fuPool.FUList6.opList] -type=OpDesc -eventq_index=0 -opClass=MemWrite -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList7] -type=FUDesc -children=opList0 opList1 -count=4 -eventq_index=0 -opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -eventq_index=0 -opClass=MemRead -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList7.opList1] -type=OpDesc -eventq_index=0 -opClass=MemWrite -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList8] -type=FUDesc -children=opList -count=1 -eventq_index=0 -opList=system.cpu.fuPool.FUList8.opList - -[system.cpu.fuPool.FUList8.opList] -type=OpDesc -eventq_index=0 -opClass=IprAccess -opLat=3 -pipelined=false - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=vortex lendian.raw -cwd=build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/vortex -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=0:134217727:0:0:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=6000 -tXPDLL=0 -tXS=270000 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simerr --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simerr Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,7 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(1, ...) diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/system.cc --- a/src/arch/alpha/system.cc Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,238 +0,0 @@ -/* - * Copyright (c) 2002-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Ali Saidi - * Nathan Binkert - */ - -#include - -#include "arch/alpha/ev5.hh" -#include "arch/alpha/system.hh" -#include "arch/vtophys.hh" -#include "base/loader/object_file.hh" -#include "base/loader/symtab.hh" -#include "base/trace.hh" -#include "debug/Loader.hh" -#include "mem/fs_translating_port_proxy.hh" -#include "params/AlphaSystem.hh" -#include "sim/byteswap.hh" - -using namespace AlphaISA; - -AlphaSystem::AlphaSystem(Params *p) - : System(p), intrFreq(0), virtProxy(getSystemPort(), p->cache_line_size) -{ - consoleSymtab = new SymbolTable; - palSymtab = new SymbolTable; - - - /** - * Load the pal, and console code into memory - */ - // Load Console Code - console = createObjectFile(params()->console); - if (console == NULL) - fatal("Could not load console file %s", params()->console); - - // Load pal file - pal = createObjectFile(params()->pal); - if (pal == NULL) - fatal("Could not load PALcode file %s", params()->pal); - - // load symbols - if (!console->loadGlobalSymbols(consoleSymtab)) - panic("could not load console symbols\n"); - - if (!pal->loadGlobalSymbols(palSymtab)) - panic("could not load pal symbols\n"); - - if (!pal->loadLocalSymbols(palSymtab)) - panic("could not load pal symbols\n"); - - if (!console->loadGlobalSymbols(debugSymbolTable)) - panic("could not load console symbols\n"); - - if (!pal->loadGlobalSymbols(debugSymbolTable)) - panic("could not load pal symbols\n"); - - if (!pal->loadLocalSymbols(debugSymbolTable)) - panic("could not load pal symbols\n"); - - -} - -AlphaSystem::~AlphaSystem() -{ - delete consoleSymtab; - delete console; - delete pal; -#ifdef DEBUG - delete consolePanicEvent; -#endif -} - -void -AlphaSystem::initState() -{ - Addr addr = 0; - - // Moved from the constructor to here since it relies on the - // address map being resolved in the interconnect - - // Call the initialisation of the super class - System::initState(); - - // Load program sections into memory - pal->loadSections(physProxy, loadAddrMask); - console->loadSections(physProxy, loadAddrMask); - - /** - * Copy the osflags (kernel arguments) into the consoles - * memory. (Presently Linux does not use the console service - * routine to get these command line arguments, but Tru64 and - * others do.) - */ - if (consoleSymtab->findAddress("env_booted_osflags", addr)) { - virtProxy.writeBlob(addr, (uint8_t*)params()->boot_osflags.c_str(), - strlen(params()->boot_osflags.c_str())); - } - - /** - * Set the hardware reset parameter block system type and revision - * information to Tsunami. - */ - if (consoleSymtab->findAddress("m5_rpb", addr)) { - uint64_t data; - data = htog(params()->system_type); - virtProxy.write(addr+0x50, data); - data = htog(params()->system_rev); - virtProxy.write(addr+0x58, data); - } else - panic("could not find hwrpb\n"); -} - -void -AlphaSystem::startup() -{ - // Setup all the function events now that we have a system and a symbol - // table - setupFuncEvents(); -} - -void -AlphaSystem::setupFuncEvents() -{ -#ifndef NDEBUG - consolePanicEvent = addConsoleFuncEvent("panic"); -#endif -} - -/** - * This function fixes up addresses that are used to match PCs for - * hooking simulator events on to target function executions. - * - * Alpha binaries may have multiple global offset table (GOT) - * sections. A function that uses the GOT starts with a - * two-instruction prolog which sets the global pointer (gp == r29) to - * the appropriate GOT section. The proper gp value is calculated - * based on the function address, which must be passed by the caller - * in the procedure value register (pv aka t12 == r27). This sequence - * looks like the following: - * - * opcode Ra Rb offset - * ldah gp,X(pv) 09 29 27 X - * lda gp,Y(gp) 08 29 29 Y - * - * for some constant offsets X and Y. The catch is that the linker - * (or maybe even the compiler, I'm not sure) may recognize that the - * caller and callee are using the same GOT section, making this - * prolog redundant, and modify the call target to skip these - * instructions. If we check for execution of the first instruction - * of a function (the one the symbol points to) to detect when to skip - * it, we'll miss all these modified calls. It might work to - * unconditionally check for the third instruction, but not all - * functions have this prolog, and there's some chance that those - * first two instructions could have undesired consequences. So we do - * the Right Thing and pattern-match the first two instructions of the - * function to decide where to patch. - * - * Eventually this code should be moved into an ISA-specific file. - */ -Addr -AlphaSystem::fixFuncEventAddr(Addr addr) -{ - // mask for just the opcode, Ra, and Rb fields (not the offset) - const uint32_t inst_mask = 0xffff0000; - // ldah gp,X(pv): opcode 9, Ra = 29, Rb = 27 - const uint32_t gp_ldah_pattern = (9 << 26) | (29 << 21) | (27 << 16); - // lda gp,Y(gp): opcode 8, Ra = 29, rb = 29 - const uint32_t gp_lda_pattern = (8 << 26) | (29 << 21) | (29 << 16); - - uint32_t i1 = virtProxy.read(addr); - uint32_t i2 = virtProxy.read(addr + sizeof(MachInst)); - - if ((i1 & inst_mask) == gp_ldah_pattern && - (i2 & inst_mask) == gp_lda_pattern) { - Addr new_addr = addr + 2 * sizeof(MachInst); - DPRINTF(Loader, "fixFuncEventAddr: %p -> %p", addr, new_addr); - return new_addr; - } else { - return addr; - } -} - -void -AlphaSystem::setAlphaAccess(Addr access) -{ - Addr addr = 0; - if (consoleSymtab->findAddress("m5AlphaAccess", addr)) { - virtProxy.write(addr, htog(Phys2K0Seg(access))); - } else { - panic("could not find m5AlphaAccess\n"); - } -} - -void -AlphaSystem::serializeSymtab(CheckpointOut &cp) const -{ - consoleSymtab->serialize("console_symtab", cp); - palSymtab->serialize("pal_symtab", cp); -} - -void -AlphaSystem::unserializeSymtab(CheckpointIn &cp) -{ - consoleSymtab->unserialize("console_symtab", cp); - palSymtab->unserialize("pal_symtab", cp); -} - -AlphaSystem * -AlphaSystemParams::create() -{ - return new AlphaSystem(this); -} diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/tlb.hh --- a/src/arch/alpha/tlb.hh Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,156 +0,0 @@ -/* - * Copyright (c) 2001-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Nathan Binkert - * Steve Reinhardt - */ - -#ifndef __ARCH_ALPHA_TLB_HH__ -#define __ARCH_ALPHA_TLB_HH__ - -#include - -#include "arch/alpha/ev5.hh" -#include "arch/alpha/isa_traits.hh" -#include "arch/alpha/pagetable.hh" -#include "arch/alpha/utility.hh" -#include "arch/alpha/vtophys.hh" -#include "arch/generic/tlb.hh" -#include "base/statistics.hh" -#include "mem/request.hh" -#include "params/AlphaTLB.hh" - -class ThreadContext; - -namespace AlphaISA { - -struct TlbEntry; - -class TLB : public BaseTLB -{ - protected: - mutable Stats::Scalar fetch_hits; - mutable Stats::Scalar fetch_misses; - mutable Stats::Scalar fetch_acv; - mutable Stats::Formula fetch_accesses; - mutable Stats::Scalar read_hits; - mutable Stats::Scalar read_misses; - mutable Stats::Scalar read_acv; - mutable Stats::Scalar read_accesses; - mutable Stats::Scalar write_hits; - mutable Stats::Scalar write_misses; - mutable Stats::Scalar write_acv; - mutable Stats::Scalar write_accesses; - Stats::Formula data_hits; - Stats::Formula data_misses; - Stats::Formula data_acv; - Stats::Formula data_accesses; - - - typedef std::multimap PageTable; - PageTable lookupTable; // Quick lookup into page table - - std::vector table; // the Page Table - int nlu; // not last used entry (for replacement) - - void nextnlu() { if (++nlu >= table.size()) nlu = 0; } - TlbEntry *lookup(Addr vpn, uint8_t asn); - - public: - typedef AlphaTLBParams Params; - TLB(const Params *p); - virtual ~TLB(); - - void takeOverFrom(BaseTLB *otlb) override {} - - void regStats() override; - - int getsize() const { return table.size(); } - - TlbEntry &index(bool advance = true); - void insert(Addr vaddr, TlbEntry &entry); - - void flushAll() override; - void flushProcesses(); - void flushAddr(Addr addr, uint8_t asn); - - void - demapPage(Addr vaddr, uint64_t asn) override - { - assert(asn < (1 << 8)); - flushAddr(vaddr, asn); - } - - // static helper functions... really EV5 VM traits - static bool - validVirtualAddress(Addr vaddr) - { - // unimplemented bits must be all 0 or all 1 - Addr unimplBits = vaddr & VAddrUnImplMask; - return unimplBits == 0 || unimplBits == VAddrUnImplMask; - } - - static Fault checkCacheability(RequestPtr &req, bool itb = false); - - // Checkpointing - void serialize(CheckpointOut &cp) const override; - void unserialize(CheckpointIn &cp) override; - - // Most recently used page table entries - TlbEntry *EntryCache[3]; - inline void - flushCache() - { - memset(EntryCache, 0, 3 * sizeof(TlbEntry*)); - } - - inline TlbEntry * - updateCache(TlbEntry *entry) { - EntryCache[2] = EntryCache[1]; - EntryCache[1] = EntryCache[0]; - EntryCache[0] = entry; - return entry; - } - - protected: - Fault translateData(RequestPtr req, ThreadContext *tc, bool write); - Fault translateInst(RequestPtr req, ThreadContext *tc); - - public: - Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode); - void translateTiming(RequestPtr req, ThreadContext *tc, - Translation *translation, Mode mode); - /** - * translateFunctional stub function for future CheckerCPU support - */ - Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode); - Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const; -}; - -} // namespace AlphaISA - -#endif // __ARCH_ALPHA_TLB_HH__ diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/tlb.cc --- a/src/arch/alpha/tlb.cc Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,637 +0,0 @@ -/* - * Copyright (c) 2001-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Nathan Binkert - * Steve Reinhardt - * Andrew Schultz - */ - -#include "arch/alpha/tlb.hh" - -#include -#include -#include -#include - -#include "arch/alpha/faults.hh" -#include "arch/alpha/pagetable.hh" -#include "arch/generic/debugfaults.hh" -#include "base/inifile.hh" -#include "base/str.hh" -#include "base/trace.hh" -#include "cpu/thread_context.hh" -#include "debug/TLB.hh" -#include "sim/full_system.hh" - -using namespace std; - -namespace AlphaISA { - -/////////////////////////////////////////////////////////////////////// -// -// Alpha TLB -// - -#ifdef DEBUG -bool uncacheBit39 = false; -bool uncacheBit40 = false; -#endif - -#define MODE2MASK(X) (1 << (X)) - -TLB::TLB(const Params *p) - : BaseTLB(p), table(p->size), nlu(0) -{ - flushCache(); -} - -TLB::~TLB() -{ -} - -void -TLB::regStats() -{ - BaseTLB::regStats(); - - fetch_hits - .name(name() + ".fetch_hits") - .desc("ITB hits"); - fetch_misses - .name(name() + ".fetch_misses") - .desc("ITB misses"); - fetch_acv - .name(name() + ".fetch_acv") - .desc("ITB acv"); - fetch_accesses - .name(name() + ".fetch_accesses") - .desc("ITB accesses"); - - fetch_accesses = fetch_hits + fetch_misses; - - read_hits - .name(name() + ".read_hits") - .desc("DTB read hits") - ; - - read_misses - .name(name() + ".read_misses") - .desc("DTB read misses") - ; - - read_acv - .name(name() + ".read_acv") - .desc("DTB read access violations") - ; - - read_accesses - .name(name() + ".read_accesses") - .desc("DTB read accesses") - ; - - write_hits - .name(name() + ".write_hits") - .desc("DTB write hits") - ; - - write_misses - .name(name() + ".write_misses") - .desc("DTB write misses") - ; - - write_acv - .name(name() + ".write_acv") - .desc("DTB write access violations") - ; - - write_accesses - .name(name() + ".write_accesses") - .desc("DTB write accesses") - ; - - data_hits - .name(name() + ".data_hits") - .desc("DTB hits") - ; - - data_misses - .name(name() + ".data_misses") - .desc("DTB misses") - ; - - data_acv - .name(name() + ".data_acv") - .desc("DTB access violations") - ; - - data_accesses - .name(name() + ".data_accesses") - .desc("DTB accesses") - ; - - data_hits = read_hits + write_hits; - data_misses = read_misses + write_misses; - data_acv = read_acv + write_acv; - data_accesses = read_accesses + write_accesses; -} - -// look up an entry in the TLB -TlbEntry * -TLB::lookup(Addr vpn, uint8_t asn) -{ - // assume not found... - TlbEntry *retval = NULL; - - if (EntryCache[0]) { - if (vpn == EntryCache[0]->tag && - (EntryCache[0]->asma || EntryCache[0]->asn == asn)) - retval = EntryCache[0]; - else if (EntryCache[1]) { - if (vpn == EntryCache[1]->tag && - (EntryCache[1]->asma || EntryCache[1]->asn == asn)) - retval = EntryCache[1]; - else if (EntryCache[2] && vpn == EntryCache[2]->tag && - (EntryCache[2]->asma || EntryCache[2]->asn == asn)) - retval = EntryCache[2]; - } - } - - if (retval == NULL) { - PageTable::const_iterator i = lookupTable.find(vpn); - if (i != lookupTable.end()) { - while (i->first == vpn) { - int index = i->second; - TlbEntry *entry = &table[index]; - assert(entry->valid); - if (vpn == entry->tag && (entry->asma || entry->asn == asn)) { - retval = updateCache(entry); - break; - } - - ++i; - } - } - } - - DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn, - retval ? "hit" : "miss", retval ? retval->ppn : 0); - return retval; -} - -Fault -TLB::checkCacheability(RequestPtr &req, bool itb) -{ - // in Alpha, cacheability is controlled by upper-level bits of the - // physical address - - /* - * We support having the uncacheable bit in either bit 39 or bit - * 40. The Turbolaser platform (and EV5) support having the bit - * in 39, but Tsunami (which Linux assumes uses an EV6) generates - * accesses with the bit in 40. So we must check for both, but we - * have debug flags to catch a weird case where both are used, - * which shouldn't happen. - */ - - - if (req->getPaddr() & PAddrUncachedBit43) { - // IPR memory space not implemented - if (PAddrIprSpace(req->getPaddr())) { - return std::make_shared( - "IPR memory space not implemented!"); - } else { - // mark request as uncacheable - req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER); - - // Clear bits 42:35 of the physical address (10-2 in - // Tsunami manual) - req->setPaddr(req->getPaddr() & PAddrUncachedMask); - } - // We shouldn't be able to read from an uncachable address in Alpha as - // we don't have a ROM and we don't want to try to fetch from a device - // register as we destroy any data that is clear-on-read. - if (req->isUncacheable() && itb) - return std::make_shared( - "CPU trying to fetch from uncached I/O"); - - } - return NoFault; -} - - -// insert a new TLB entry -void -TLB::insert(Addr addr, TlbEntry &entry) -{ - flushCache(); - VAddr vaddr = addr; - if (table[nlu].valid) { - Addr oldvpn = table[nlu].tag; - PageTable::iterator i = lookupTable.find(oldvpn); - - if (i == lookupTable.end()) - panic("TLB entry not found in lookupTable"); - - int index; - while ((index = i->second) != nlu) { - if (table[index].tag != oldvpn) - panic("TLB entry not found in lookupTable"); - - ++i; - } - - DPRINTF(TLB, "remove @%d: %#x -> %#x\n", nlu, oldvpn, table[nlu].ppn); - - lookupTable.erase(i); - } - - DPRINTF(TLB, "insert @%d: %#x -> %#x\n", nlu, vaddr.vpn(), entry.ppn); - - table[nlu] = entry; - table[nlu].tag = vaddr.vpn(); - table[nlu].valid = true; - - lookupTable.insert(make_pair(vaddr.vpn(), nlu)); - nextnlu(); -} - -void -TLB::flushAll() -{ - DPRINTF(TLB, "flushAll\n"); - std::fill(table.begin(), table.end(), TlbEntry()); - flushCache(); - lookupTable.clear(); - nlu = 0; -} - -void -TLB::flushProcesses() -{ - flushCache(); - PageTable::iterator i = lookupTable.begin(); - PageTable::iterator end = lookupTable.end(); - while (i != end) { - int index = i->second; - TlbEntry *entry = &table[index]; - assert(entry->valid); - - // we can't increment i after we erase it, so save a copy and - // increment it to get the next entry now - PageTable::iterator cur = i; - ++i; - - if (!entry->asma) { - DPRINTF(TLB, "flush @%d: %#x -> %#x\n", index, - entry->tag, entry->ppn); - entry->valid = false; - lookupTable.erase(cur); - } - } -} - -void -TLB::flushAddr(Addr addr, uint8_t asn) -{ - flushCache(); - VAddr vaddr = addr; - - PageTable::iterator i = lookupTable.find(vaddr.vpn()); - if (i == lookupTable.end()) - return; - - while (i != lookupTable.end() && i->first == vaddr.vpn()) { - int index = i->second; - TlbEntry *entry = &table[index]; - assert(entry->valid); - - if (vaddr.vpn() == entry->tag && (entry->asma || entry->asn == asn)) { - DPRINTF(TLB, "flushaddr @%d: %#x -> %#x\n", index, vaddr.vpn(), - entry->ppn); - - // invalidate this entry - entry->valid = false; - - lookupTable.erase(i++); - } else { - ++i; - } - } -} - - -void -TLB::serialize(CheckpointOut &cp) const -{ - const unsigned size(table.size()); - SERIALIZE_SCALAR(size); - SERIALIZE_SCALAR(nlu); - - for (int i = 0; i < size; i++) - table[i].serializeSection(cp, csprintf("Entry%d", i)); -} - -void -TLB::unserialize(CheckpointIn &cp) -{ - unsigned size(0); - UNSERIALIZE_SCALAR(size); - UNSERIALIZE_SCALAR(nlu); - - table.resize(size); - for (int i = 0; i < size; i++) { - table[i].unserializeSection(cp, csprintf("Entry%d", i)); - if (table[i].valid) { - lookupTable.insert(make_pair(table[i].tag, i)); - } - } -} - -Fault -TLB::translateInst(RequestPtr req, ThreadContext *tc) -{ - //If this is a pal pc, then set PHYSICAL - if (FullSystem && PcPAL(req->getPC())) - req->setFlags(Request::PHYSICAL); - - if (PcPAL(req->getPC())) { - // strip off PAL PC marker (lsb is 1) - req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask); - fetch_hits++; - return NoFault; - } - - if (req->getFlags() & Request::PHYSICAL) { - req->setPaddr(req->getVaddr()); - } else { - // verify that this is a good virtual address - if (!validVirtualAddress(req->getVaddr())) { - fetch_acv++; - return std::make_shared(req->getVaddr()); - } - - - // VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5 - // VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6 - if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) { - // only valid in kernel mode - if (ICM_CM(tc->readMiscRegNoEffect(IPR_ICM)) != - mode_kernel) { - fetch_acv++; - return std::make_shared(req->getVaddr()); - } - - req->setPaddr(req->getVaddr() & PAddrImplMask); - - // sign extend the physical address properly - if (req->getPaddr() & PAddrUncachedBit40) - req->setPaddr(req->getPaddr() | ULL(0xf0000000000)); - else - req->setPaddr(req->getPaddr() & ULL(0xffffffffff)); - } else { - // not a physical address: need to look up pte - int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN)); - TlbEntry *entry = lookup(VAddr(req->getVaddr()).vpn(), - asn); - - if (!entry) { - fetch_misses++; - return std::make_shared(req->getVaddr()); - } - - req->setPaddr((entry->ppn << PageShift) + - (VAddr(req->getVaddr()).offset() - & ~3)); - - // check permissions for this access - if (!(entry->xre & - (1 << ICM_CM(tc->readMiscRegNoEffect(IPR_ICM))))) { - // instruction access fault - fetch_acv++; - return std::make_shared(req->getVaddr()); - } - - fetch_hits++; - } - } - - // check that the physical address is ok (catch bad physical addresses) - if (req->getPaddr() & ~PAddrImplMask) { - return std::make_shared(); - } - - return checkCacheability(req, true); - -} - -Fault -TLB::translateData(RequestPtr req, ThreadContext *tc, bool write) -{ - mode_type mode = - (mode_type)DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM)); - - /** - * Check for alignment faults - */ - if (req->getVaddr() & (req->getSize() - 1)) { - DPRINTF(TLB, "Alignment Fault on %#x, size = %d\n", req->getVaddr(), - req->getSize()); - uint64_t flags = write ? MM_STAT_WR_MASK : 0; - return std::make_shared(req->getVaddr(), - req->getFlags(), - flags); - } - - if (PcPAL(req->getPC())) { - mode = (req->getFlags() & AlphaRequestFlags::ALTMODE) ? - (mode_type)ALT_MODE_AM( - tc->readMiscRegNoEffect(IPR_ALT_MODE)) - : mode_kernel; - } - - if (req->getFlags() & Request::PHYSICAL) { - req->setPaddr(req->getVaddr()); - } else { - // verify that this is a good virtual address - if (!validVirtualAddress(req->getVaddr())) { - if (write) { write_acv++; } else { read_acv++; } - uint64_t flags = (write ? MM_STAT_WR_MASK : 0) | - MM_STAT_BAD_VA_MASK | - MM_STAT_ACV_MASK; - return std::make_shared(req->getVaddr(), - req->getFlags(), - flags); - } - - // Check for "superpage" mapping - if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) { - // only valid in kernel mode - if (DTB_CM_CM(tc->readMiscRegNoEffect(IPR_DTB_CM)) != - mode_kernel) { - if (write) { write_acv++; } else { read_acv++; } - uint64_t flags = ((write ? MM_STAT_WR_MASK : 0) | - MM_STAT_ACV_MASK); - - return std::make_shared(req->getVaddr(), - req->getFlags(), - flags); - } - - req->setPaddr(req->getVaddr() & PAddrImplMask); - - // sign extend the physical address properly - if (req->getPaddr() & PAddrUncachedBit40) - req->setPaddr(req->getPaddr() | ULL(0xf0000000000)); - else - req->setPaddr(req->getPaddr() & ULL(0xffffffffff)); - } else { - if (write) - write_accesses++; - else - read_accesses++; - - int asn = DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN)); - - // not a physical address: need to look up pte - TlbEntry *entry = lookup(VAddr(req->getVaddr()).vpn(), asn); - - if (!entry) { - // page fault - if (write) { write_misses++; } else { read_misses++; } - uint64_t flags = (write ? MM_STAT_WR_MASK : 0) | - MM_STAT_DTB_MISS_MASK; - return (req->getFlags() & AlphaRequestFlags::VPTE) ? - (Fault)(std::make_shared(req->getVaddr(), - req->getFlags(), - flags)) : - (Fault)(std::make_shared(req->getVaddr(), - req->getFlags(), - flags)); - } - - req->setPaddr((entry->ppn << PageShift) + - VAddr(req->getVaddr()).offset()); - - if (write) { - if (!(entry->xwe & MODE2MASK(mode))) { - // declare the instruction access fault - write_acv++; - uint64_t flags = MM_STAT_WR_MASK | - MM_STAT_ACV_MASK | - (entry->fonw ? MM_STAT_FONW_MASK : 0); - return std::make_shared(req->getVaddr(), - req->getFlags(), - flags); - } - if (entry->fonw) { - write_acv++; - uint64_t flags = MM_STAT_WR_MASK | MM_STAT_FONW_MASK; - return std::make_shared(req->getVaddr(), - req->getFlags(), - flags); - } - } else { - if (!(entry->xre & MODE2MASK(mode))) { - read_acv++; - uint64_t flags = MM_STAT_ACV_MASK | - (entry->fonr ? MM_STAT_FONR_MASK : 0); - return std::make_shared(req->getVaddr(), - req->getFlags(), - flags); - } - if (entry->fonr) { - read_acv++; - uint64_t flags = MM_STAT_FONR_MASK; - return std::make_shared(req->getVaddr(), - req->getFlags(), - flags); - } - } - } - - if (write) - write_hits++; - else - read_hits++; - } - - // check that the physical address is ok (catch bad physical addresses) - if (req->getPaddr() & ~PAddrImplMask) { - return std::make_shared(); - } - - return checkCacheability(req); -} - -TlbEntry & -TLB::index(bool advance) -{ - TlbEntry *entry = &table[nlu]; - - if (advance) - nextnlu(); - - return *entry; -} - -Fault -TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) -{ - if (mode == Execute) - return translateInst(req, tc); - else - return translateData(req, tc, mode == Write); -} - -void -TLB::translateTiming(RequestPtr req, ThreadContext *tc, - Translation *translation, Mode mode) -{ - assert(translation); - translation->finish(translateAtomic(req, tc, mode), req, tc, mode); -} - -Fault -TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode) -{ - panic("Not implemented\n"); - return NoFault; -} - -Fault -TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const -{ - return NoFault; -} - -} // namespace AlphaISA - -AlphaISA::TLB * -AlphaTLBParams::create() -{ - return new AlphaISA::TLB(this); -} diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/tru64/process.hh --- a/src/arch/alpha/tru64/process.hh Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,60 +0,0 @@ -/* - * Copyright (c) 2003-2004 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Steve Reinhardt - */ - -#ifndef __ARCH_ALPHA_TRU64_PROCESS_HH__ -#define __ARCH_ALPHA_TRU64_PROCESS_HH__ - -#include "arch/alpha/process.hh" - -namespace AlphaISA { - -/// A process with emulated Alpha Tru64 syscalls. -class AlphaTru64Process : public AlphaLiveProcess -{ - public: - /// Constructor. - AlphaTru64Process(LiveProcessParams * params, - ObjectFile *objFile); - - /// Array of syscall descriptors, indexed by call number. - static SyscallDesc syscallDescs[]; - - /// Array of mach syscall descriptors, indexed by call number. - static SyscallDesc machSyscallDescs[]; - - const int Num_Syscall_Descs; - const int Num_Mach_Syscall_Descs; - - virtual SyscallDesc *getDesc(int callnum); -}; - -} // namespace AlphaISA - -#endif // __ARCH_ALPHA_TRU64_PROCESS_HH__ diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/tru64/process.cc --- a/src/arch/alpha/tru64/process.cc Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,584 +0,0 @@ -/* - * Copyright (c) 2001-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Steve Reinhardt - * Ali Saidi - */ - -#include "arch/alpha/tru64/process.hh" -#include "arch/alpha/tru64/tru64.hh" -#include "arch/alpha/isa_traits.hh" -#include "cpu/thread_context.hh" -#include "kern/tru64/tru64.hh" -#include "sim/byteswap.hh" -#include "sim/process.hh" -#include "sim/syscall_emul.hh" - -using namespace std; -using namespace AlphaISA; - -/// Target uname() handler. -static SyscallReturn -unameFunc(SyscallDesc *desc, int callnum, LiveProcess *process, - ThreadContext *tc) -{ - int index = 0; - TypedBufferArg name(process->getSyscallArg(tc, index)); - - strcpy(name->sysname, "OSF1"); - strcpy(name->nodename, "m5.eecs.umich.edu"); - strcpy(name->release, "V5.1"); - strcpy(name->version, "732"); - strcpy(name->machine, "alpha"); - - name.copyOut(tc->getMemProxy()); - return 0; -} - -/// Target getsysyinfo() handler. -static SyscallReturn -getsysinfoFunc(SyscallDesc *desc, int callnum, LiveProcess *process, - ThreadContext *tc) -{ - int index = 0; - unsigned op = process->getSyscallArg(tc, index); - Addr bufPtr = process->getSyscallArg(tc, index); - unsigned nbytes = process->getSyscallArg(tc, index); - - switch (op) { - - case AlphaTru64::GSI_MAX_CPU: { - TypedBufferArg max_cpu(bufPtr); - *max_cpu = htog((uint32_t)process->numCpus()); - max_cpu.copyOut(tc->getMemProxy()); - return 1; - } - - case AlphaTru64::GSI_CPUS_IN_BOX: { - TypedBufferArg cpus_in_box(bufPtr); - *cpus_in_box = htog((uint32_t)process->numCpus()); - cpus_in_box.copyOut(tc->getMemProxy()); - return 1; - } - - case AlphaTru64::GSI_PHYSMEM: { - TypedBufferArg physmem(bufPtr); - *physmem = htog((uint64_t)1024 * 1024); // physical memory in KB - physmem.copyOut(tc->getMemProxy()); - return 1; - } - - case AlphaTru64::GSI_CPU_INFO: { - TypedBufferArg infop(bufPtr); - - infop->current_cpu = htog(0); - infop->cpus_in_box = htog(process->numCpus()); - infop->cpu_type = htog(57); - infop->ncpus = htog(process->numCpus()); - uint64_t cpumask = (1 << process->numCpus()) - 1; - infop->cpus_present = infop->cpus_running = htog(cpumask); - infop->cpu_binding = htog(0); - infop->cpu_ex_binding = htog(0); - infop->mhz = htog(667); - - infop.copyOut(tc->getMemProxy()); - return 1; - } - - case AlphaTru64::GSI_PROC_TYPE: { - TypedBufferArg proc_type(bufPtr); - *proc_type = htog((uint64_t)11); - proc_type.copyOut(tc->getMemProxy()); - return 1; - } - - case AlphaTru64::GSI_PLATFORM_NAME: { - BufferArg bufArg(bufPtr, nbytes); - strncpy((char *)bufArg.bufferPtr(), - "COMPAQ Professional Workstation XP1000", - nbytes); - bufArg.copyOut(tc->getMemProxy()); - return 1; - } - - case AlphaTru64::GSI_CLK_TCK: { - TypedBufferArg clk_hz(bufPtr); - *clk_hz = htog((uint64_t)1024); - clk_hz.copyOut(tc->getMemProxy()); - return 1; - } - - default: - warn("getsysinfo: unknown op %d\n", op); - break; - } - - return 0; -} - -/// Target setsysyinfo() handler. -static SyscallReturn -setsysinfoFunc(SyscallDesc *desc, int callnum, LiveProcess *process, - ThreadContext *tc) -{ - int index = 0; - unsigned op = process->getSyscallArg(tc, index); - - switch (op) { - case AlphaTru64::SSI_IEEE_FP_CONTROL: - warn("setsysinfo: ignoring ieee_set_fp_control() arg 0x%x\n", - process->getSyscallArg(tc, index)); - break; - - default: - warn("setsysinfo: unknown op %d\n", op); - break; - } - - return 0; -} - -/// Target table() handler. -static SyscallReturn -tableFunc(SyscallDesc *desc, int callnum, LiveProcess *process, - ThreadContext *tc) -{ - using namespace std; - - int argIndex = 0; - int id = process->getSyscallArg(tc, argIndex); // table ID - int index = process->getSyscallArg(tc, argIndex); // index into table - Addr bufPtr = process->getSyscallArg(tc, argIndex); - // arg 2 is buffer pointer; type depends on table ID - int nel = process->getSyscallArg(tc, argIndex); // number of elements - int lel = process->getSyscallArg(tc, argIndex); // expected element size - - switch (id) { - case AlphaTru64::TBL_SYSINFO: { - if (index != 0 || nel != 1 || lel != sizeof(Tru64::tbl_sysinfo)) - return -EINVAL; - TypedBufferArg elp(bufPtr); - - const int clk_hz = one_million; - elp->si_user = htog(curTick() / (SimClock::Frequency / clk_hz)); - elp->si_nice = htog(0); - elp->si_sys = htog(0); - elp->si_idle = htog(0); - elp->wait = htog(0); - elp->si_hz = htog(clk_hz); - elp->si_phz = htog(clk_hz); - elp->si_boottime = htog(seconds_since_epoch); // seconds since epoch? - elp->si_max_procs = htog(process->numCpus()); - elp.copyOut(tc->getMemProxy()); - return 0; - } - - default: - cerr << "table(): id " << id << " unknown." << endl; - return -EINVAL; - } -} - -SyscallDesc AlphaTru64Process::syscallDescs[] = { - /* 0 */ SyscallDesc("syscall (#0)", AlphaTru64::indirectSyscallFunc, - SyscallDesc::SuppressReturnValue), - /* 1 */ SyscallDesc("exit", exitFunc), - /* 2 */ SyscallDesc("fork", unimplementedFunc), - /* 3 */ SyscallDesc("read", readFunc), - /* 4 */ SyscallDesc("write", writeFunc), - /* 5 */ SyscallDesc("old_open", unimplementedFunc), - /* 6 */ SyscallDesc("close", closeFunc), - /* 7 */ SyscallDesc("wait4", unimplementedFunc), - /* 8 */ SyscallDesc("old_creat", unimplementedFunc), - /* 9 */ SyscallDesc("link", unimplementedFunc), - /* 10 */ SyscallDesc("unlink", unlinkFunc), - /* 11 */ SyscallDesc("execv", unimplementedFunc), - /* 12 */ SyscallDesc("chdir", unimplementedFunc), - /* 13 */ SyscallDesc("fchdir", unimplementedFunc), - /* 14 */ SyscallDesc("mknod", unimplementedFunc), - /* 15 */ SyscallDesc("chmod", unimplementedFunc), - /* 16 */ SyscallDesc("chown", unimplementedFunc), - /* 17 */ SyscallDesc("obreak", brkFunc), - /* 18 */ SyscallDesc("pre_F64_getfsstat", unimplementedFunc), - /* 19 */ SyscallDesc("lseek", lseekFunc), - /* 20 */ SyscallDesc("getpid", getpidPseudoFunc), - /* 21 */ SyscallDesc("mount", unimplementedFunc), - /* 22 */ SyscallDesc("unmount", unimplementedFunc), - /* 23 */ SyscallDesc("setuid", setuidFunc), - /* 24 */ SyscallDesc("getuid", getuidPseudoFunc), - /* 25 */ SyscallDesc("exec_with_loader", unimplementedFunc), - /* 26 */ SyscallDesc("ptrace", unimplementedFunc), - /* 27 */ SyscallDesc("recvmsg", unimplementedFunc), - /* 28 */ SyscallDesc("sendmsg", unimplementedFunc), - /* 29 */ SyscallDesc("recvfrom", unimplementedFunc), - /* 30 */ SyscallDesc("accept", unimplementedFunc), - /* 31 */ SyscallDesc("getpeername", unimplementedFunc), - /* 32 */ SyscallDesc("getsockname", unimplementedFunc), - /* 33 */ SyscallDesc("access", unimplementedFunc), - /* 34 */ SyscallDesc("chflags", unimplementedFunc), - /* 35 */ SyscallDesc("fchflags", unimplementedFunc), - /* 36 */ SyscallDesc("sync", unimplementedFunc), - /* 37 */ SyscallDesc("kill", unimplementedFunc), - /* 38 */ SyscallDesc("old_stat", unimplementedFunc), - /* 39 */ SyscallDesc("setpgid", unimplementedFunc), - /* 40 */ SyscallDesc("old_lstat", unimplementedFunc), - /* 41 */ SyscallDesc("dup", unimplementedFunc), - /* 42 */ SyscallDesc("pipe", unimplementedFunc), - /* 43 */ SyscallDesc("set_program_attributes", unimplementedFunc), - /* 44 */ SyscallDesc("profil", unimplementedFunc), - /* 45 */ SyscallDesc("open", openFunc), - /* 46 */ SyscallDesc("obsolete osigaction", unimplementedFunc), - /* 47 */ SyscallDesc("getgid", getgidPseudoFunc), - /* 48 */ SyscallDesc("sigprocmask", ignoreFunc), - /* 49 */ SyscallDesc("getlogin", unimplementedFunc), - /* 50 */ SyscallDesc("setlogin", unimplementedFunc), - /* 51 */ SyscallDesc("acct", unimplementedFunc), - /* 52 */ SyscallDesc("sigpending", unimplementedFunc), - /* 53 */ SyscallDesc("classcntl", unimplementedFunc), - /* 54 */ SyscallDesc("ioctl", ioctlFunc), - /* 55 */ SyscallDesc("reboot", unimplementedFunc), - /* 56 */ SyscallDesc("revoke", unimplementedFunc), - /* 57 */ SyscallDesc("symlink", unimplementedFunc), - /* 58 */ SyscallDesc("readlink", readlinkFunc), - /* 59 */ SyscallDesc("execve", unimplementedFunc), - /* 60 */ SyscallDesc("umask", umaskFunc), - /* 61 */ SyscallDesc("chroot", unimplementedFunc), - /* 62 */ SyscallDesc("old_fstat", unimplementedFunc), - /* 63 */ SyscallDesc("getpgrp", unimplementedFunc), - /* 64 */ SyscallDesc("getpagesize", getpagesizeFunc), - /* 65 */ SyscallDesc("mremap", unimplementedFunc), - /* 66 */ SyscallDesc("vfork", unimplementedFunc), - /* 67 */ SyscallDesc("pre_F64_stat", statFunc), - /* 68 */ SyscallDesc("pre_F64_lstat", lstatFunc), - /* 69 */ SyscallDesc("sbrk", unimplementedFunc), - /* 70 */ SyscallDesc("sstk", unimplementedFunc), - /* 71 */ SyscallDesc("mmap", mmapFunc), - /* 72 */ SyscallDesc("ovadvise", unimplementedFunc), - /* 73 */ SyscallDesc("munmap", munmapFunc), - /* 74 */ SyscallDesc("mprotect", ignoreFunc), - /* 75 */ SyscallDesc("madvise", unimplementedFunc), - /* 76 */ SyscallDesc("old_vhangup", unimplementedFunc), - /* 77 */ SyscallDesc("kmodcall", unimplementedFunc), - /* 78 */ SyscallDesc("mincore", unimplementedFunc), - /* 79 */ SyscallDesc("getgroups", unimplementedFunc), - /* 80 */ SyscallDesc("setgroups", unimplementedFunc), - /* 81 */ SyscallDesc("old_getpgrp", unimplementedFunc), - /* 82 */ SyscallDesc("setpgrp", unimplementedFunc), - /* 83 */ SyscallDesc("setitimer", unimplementedFunc), - /* 84 */ SyscallDesc("old_wait", unimplementedFunc), - /* 85 */ SyscallDesc("table", tableFunc), - /* 86 */ SyscallDesc("getitimer", unimplementedFunc), - /* 87 */ SyscallDesc("gethostname", gethostnameFunc), - /* 88 */ SyscallDesc("sethostname", unimplementedFunc), - /* 89 */ SyscallDesc("getdtablesize", unimplementedFunc), - /* 90 */ SyscallDesc("dup2", unimplementedFunc), - /* 91 */ SyscallDesc("pre_F64_fstat", fstatFunc), - /* 92 */ SyscallDesc("fcntl", fcntlFunc), - /* 93 */ SyscallDesc("select", unimplementedFunc), - /* 94 */ SyscallDesc("poll", unimplementedFunc), - /* 95 */ SyscallDesc("fsync", unimplementedFunc), - /* 96 */ SyscallDesc("setpriority", unimplementedFunc), - /* 97 */ SyscallDesc("socket", unimplementedFunc), - /* 98 */ SyscallDesc("connect", unimplementedFunc), - /* 99 */ SyscallDesc("old_accept", unimplementedFunc), - /* 100 */ SyscallDesc("getpriority", unimplementedFunc), - /* 101 */ SyscallDesc("old_send", unimplementedFunc), - /* 102 */ SyscallDesc("old_recv", unimplementedFunc), - /* 103 */ SyscallDesc("sigreturn", AlphaTru64::sigreturnFunc, - SyscallDesc::SuppressReturnValue), - /* 104 */ SyscallDesc("bind", unimplementedFunc), - /* 105 */ SyscallDesc("setsockopt", unimplementedFunc), - /* 106 */ SyscallDesc("listen", unimplementedFunc), - /* 107 */ SyscallDesc("plock", unimplementedFunc), - /* 108 */ SyscallDesc("old_sigvec", unimplementedFunc), - /* 109 */ SyscallDesc("old_sigblock", unimplementedFunc), - /* 110 */ SyscallDesc("old_sigsetmask", unimplementedFunc), - /* 111 */ SyscallDesc("sigsuspend", unimplementedFunc), - /* 112 */ SyscallDesc("sigstack", ignoreFunc), - /* 113 */ SyscallDesc("old_recvmsg", unimplementedFunc), - /* 114 */ SyscallDesc("old_sendmsg", unimplementedFunc), - /* 115 */ SyscallDesc("obsolete vtrace", unimplementedFunc), - /* 116 */ SyscallDesc("gettimeofday", gettimeofdayFunc), - /* 117 */ SyscallDesc("getrusage", getrusageFunc), - /* 118 */ SyscallDesc("getsockopt", unimplementedFunc), - /* 119 */ SyscallDesc("numa_syscalls", unimplementedFunc), - /* 120 */ SyscallDesc("readv", unimplementedFunc), - /* 121 */ SyscallDesc("writev", unimplementedFunc), - /* 122 */ SyscallDesc("settimeofday", unimplementedFunc), - /* 123 */ SyscallDesc("fchown", unimplementedFunc), - /* 124 */ SyscallDesc("fchmod", unimplementedFunc), - /* 125 */ SyscallDesc("old_recvfrom", unimplementedFunc), - /* 126 */ SyscallDesc("setreuid", unimplementedFunc), - /* 127 */ SyscallDesc("setregid", unimplementedFunc), - /* 128 */ SyscallDesc("rename", renameFunc), - /* 129 */ SyscallDesc("truncate", truncateFunc), - /* 130 */ SyscallDesc("ftruncate", ftruncateFunc), - /* 131 */ SyscallDesc("flock", unimplementedFunc), - /* 132 */ SyscallDesc("setgid", unimplementedFunc), - /* 133 */ SyscallDesc("sendto", unimplementedFunc), - /* 134 */ SyscallDesc("shutdown", unimplementedFunc), - /* 135 */ SyscallDesc("socketpair", unimplementedFunc), - /* 136 */ SyscallDesc("mkdir", mkdirFunc), - /* 137 */ SyscallDesc("rmdir", unimplementedFunc), - /* 138 */ SyscallDesc("utimes", unimplementedFunc), - /* 139 */ SyscallDesc("obsolete 4.2 sigreturn", unimplementedFunc), - /* 140 */ SyscallDesc("adjtime", unimplementedFunc), - /* 141 */ SyscallDesc("old_getpeername", unimplementedFunc), - /* 142 */ SyscallDesc("gethostid", unimplementedFunc), - /* 143 */ SyscallDesc("sethostid", unimplementedFunc), - /* 144 */ SyscallDesc("getrlimit", getrlimitFunc), - /* 145 */ SyscallDesc("setrlimit", ignoreFunc), - /* 146 */ SyscallDesc("old_killpg", unimplementedFunc), - /* 147 */ SyscallDesc("setsid", unimplementedFunc), - /* 148 */ SyscallDesc("quotactl", unimplementedFunc), - /* 149 */ SyscallDesc("oldquota", unimplementedFunc), - /* 150 */ SyscallDesc("old_getsockname", unimplementedFunc), - /* 151 */ SyscallDesc("pread", unimplementedFunc), - /* 152 */ SyscallDesc("pwrite", unimplementedFunc), - /* 153 */ SyscallDesc("pid_block", unimplementedFunc), - /* 154 */ SyscallDesc("pid_unblock", unimplementedFunc), - /* 155 */ SyscallDesc("signal_urti", unimplementedFunc), - /* 156 */ SyscallDesc("sigaction", ignoreFunc), - /* 157 */ SyscallDesc("sigwaitprim", unimplementedFunc), - /* 158 */ SyscallDesc("nfssvc", unimplementedFunc), - /* 159 */ SyscallDesc("getdirentries", AlphaTru64::getdirentriesFunc), - /* 160 */ SyscallDesc("pre_F64_statfs", statfsFunc), - /* 161 */ SyscallDesc("pre_F64_fstatfs", fstatfsFunc), - /* 162 */ SyscallDesc("unknown #162", unimplementedFunc), - /* 163 */ SyscallDesc("async_daemon", unimplementedFunc), - /* 164 */ SyscallDesc("getfh", unimplementedFunc), - /* 165 */ SyscallDesc("getdomainname", unimplementedFunc), - /* 166 */ SyscallDesc("setdomainname", unimplementedFunc), - /* 167 */ SyscallDesc("unknown #167", unimplementedFunc), - /* 168 */ SyscallDesc("unknown #168", unimplementedFunc), - /* 169 */ SyscallDesc("exportfs", unimplementedFunc), - /* 170 */ SyscallDesc("unknown #170", unimplementedFunc), - /* 171 */ SyscallDesc("unknown #171", unimplementedFunc), - /* 172 */ SyscallDesc("unknown #172", unimplementedFunc), - /* 173 */ SyscallDesc("unknown #173", unimplementedFunc), - /* 174 */ SyscallDesc("unknown #174", unimplementedFunc), - /* 175 */ SyscallDesc("unknown #175", unimplementedFunc), - /* 176 */ SyscallDesc("unknown #176", unimplementedFunc), - /* 177 */ SyscallDesc("unknown #177", unimplementedFunc), - /* 178 */ SyscallDesc("unknown #178", unimplementedFunc), - /* 179 */ SyscallDesc("unknown #179", unimplementedFunc), - /* 180 */ SyscallDesc("unknown #180", unimplementedFunc), - /* 181 */ SyscallDesc("alt_plock", unimplementedFunc), - /* 182 */ SyscallDesc("unknown #182", unimplementedFunc), - /* 183 */ SyscallDesc("unknown #183", unimplementedFunc), - /* 184 */ SyscallDesc("getmnt", unimplementedFunc), - /* 185 */ SyscallDesc("unknown #185", unimplementedFunc), - /* 186 */ SyscallDesc("unknown #186", unimplementedFunc), - /* 187 */ SyscallDesc("alt_sigpending", unimplementedFunc), - /* 188 */ SyscallDesc("alt_setsid", unimplementedFunc), - /* 189 */ SyscallDesc("unknown #189", unimplementedFunc), - /* 190 */ SyscallDesc("unknown #190", unimplementedFunc), - /* 191 */ SyscallDesc("unknown #191", unimplementedFunc), - /* 192 */ SyscallDesc("unknown #192", unimplementedFunc), - /* 193 */ SyscallDesc("unknown #193", unimplementedFunc), - /* 194 */ SyscallDesc("unknown #194", unimplementedFunc), - /* 195 */ SyscallDesc("unknown #195", unimplementedFunc), - /* 196 */ SyscallDesc("unknown #196", unimplementedFunc), - /* 197 */ SyscallDesc("unknown #197", unimplementedFunc), - /* 198 */ SyscallDesc("unknown #198", unimplementedFunc), - /* 199 */ SyscallDesc("swapon", unimplementedFunc), - /* 200 */ SyscallDesc("msgctl", unimplementedFunc), - /* 201 */ SyscallDesc("msgget", unimplementedFunc), - /* 202 */ SyscallDesc("msgrcv", unimplementedFunc), - /* 203 */ SyscallDesc("msgsnd", unimplementedFunc), - /* 204 */ SyscallDesc("semctl", unimplementedFunc), - /* 205 */ SyscallDesc("semget", unimplementedFunc), - /* 206 */ SyscallDesc("semop", unimplementedFunc), - /* 207 */ SyscallDesc("uname", unameFunc), - /* 208 */ SyscallDesc("lchown", unimplementedFunc), - /* 209 */ SyscallDesc("shmat", unimplementedFunc), - /* 210 */ SyscallDesc("shmctl", unimplementedFunc), - /* 211 */ SyscallDesc("shmdt", unimplementedFunc), - /* 212 */ SyscallDesc("shmget", unimplementedFunc), - /* 213 */ SyscallDesc("mvalid", unimplementedFunc), - /* 214 */ SyscallDesc("getaddressconf", unimplementedFunc), - /* 215 */ SyscallDesc("msleep", unimplementedFunc), - /* 216 */ SyscallDesc("mwakeup", unimplementedFunc), - /* 217 */ SyscallDesc("msync", unimplementedFunc), - /* 218 */ SyscallDesc("signal", unimplementedFunc), - /* 219 */ SyscallDesc("utc_gettime", unimplementedFunc), - /* 220 */ SyscallDesc("utc_adjtime", unimplementedFunc), - /* 221 */ SyscallDesc("unknown #221", unimplementedFunc), - /* 222 */ SyscallDesc("security", unimplementedFunc), - /* 223 */ SyscallDesc("kloadcall", unimplementedFunc), - /* 224 */ SyscallDesc("stat", statFunc), - /* 225 */ SyscallDesc("lstat", lstatFunc), - /* 226 */ SyscallDesc("fstat", fstatFunc), - /* 227 */ SyscallDesc("statfs", statfsFunc), - /* 228 */ SyscallDesc("fstatfs", fstatfsFunc), - /* 229 */ SyscallDesc("getfsstat", unimplementedFunc), - /* 230 */ SyscallDesc("gettimeofday64", unimplementedFunc), - /* 231 */ SyscallDesc("settimeofday64", unimplementedFunc), - /* 232 */ SyscallDesc("unknown #232", unimplementedFunc), - /* 233 */ SyscallDesc("getpgid", unimplementedFunc), - /* 234 */ SyscallDesc("getsid", unimplementedFunc), - /* 235 */ SyscallDesc("sigaltstack", ignoreFunc), - /* 236 */ SyscallDesc("waitid", unimplementedFunc), - /* 237 */ SyscallDesc("priocntlset", unimplementedFunc), - /* 238 */ SyscallDesc("sigsendset", unimplementedFunc), - /* 239 */ SyscallDesc("set_speculative", unimplementedFunc), - /* 240 */ SyscallDesc("msfs_syscall", unimplementedFunc), - /* 241 */ SyscallDesc("sysinfo", unimplementedFunc), - /* 242 */ SyscallDesc("uadmin", unimplementedFunc), - /* 243 */ SyscallDesc("fuser", unimplementedFunc), - /* 244 */ SyscallDesc("proplist_syscall", unimplementedFunc), - /* 245 */ SyscallDesc("ntp_adjtime", unimplementedFunc), - /* 246 */ SyscallDesc("ntp_gettime", unimplementedFunc), - /* 247 */ SyscallDesc("pathconf", unimplementedFunc), - /* 248 */ SyscallDesc("fpathconf", unimplementedFunc), - /* 249 */ SyscallDesc("sync2", unimplementedFunc), - /* 250 */ SyscallDesc("uswitch", unimplementedFunc), - /* 251 */ SyscallDesc("usleep_thread", unimplementedFunc), - /* 252 */ SyscallDesc("audcntl", unimplementedFunc), - /* 253 */ SyscallDesc("audgen", unimplementedFunc), - /* 254 */ SyscallDesc("sysfs", unimplementedFunc), - /* 255 */ SyscallDesc("subsys_info", unimplementedFunc), - /* 256 */ SyscallDesc("getsysinfo", getsysinfoFunc), - /* 257 */ SyscallDesc("setsysinfo", setsysinfoFunc), - /* 258 */ SyscallDesc("afs_syscall", unimplementedFunc), - /* 259 */ SyscallDesc("swapctl", unimplementedFunc), - /* 260 */ SyscallDesc("memcntl", unimplementedFunc), - /* 261 */ SyscallDesc("fdatasync", unimplementedFunc), - /* 262 */ SyscallDesc("oflock", unimplementedFunc), - /* 263 */ SyscallDesc("F64_readv", unimplementedFunc), - /* 264 */ SyscallDesc("F64_writev", unimplementedFunc), - /* 265 */ SyscallDesc("cdslxlate", unimplementedFunc), - /* 266 */ SyscallDesc("sendfile", unimplementedFunc), -}; - -SyscallDesc AlphaTru64Process::machSyscallDescs[] = { - /* 0 */ SyscallDesc("kern_invalid", unimplementedFunc), - /* 1 */ SyscallDesc("m5_mutex_lock", AlphaTru64::m5_mutex_lockFunc), - /* 2 */ SyscallDesc("m5_mutex_trylock", AlphaTru64::m5_mutex_trylockFunc), - /* 3 */ SyscallDesc("m5_mutex_unlock", AlphaTru64::m5_mutex_unlockFunc), - /* 4 */ SyscallDesc("m5_cond_signal", AlphaTru64::m5_cond_signalFunc), - /* 5 */ SyscallDesc("m5_cond_broadcast", - AlphaTru64::m5_cond_broadcastFunc), - /* 6 */ SyscallDesc("m5_cond_wait", AlphaTru64::m5_cond_waitFunc), - /* 7 */ SyscallDesc("m5_thread_exit", AlphaTru64::m5_thread_exitFunc), - /* 8 */ SyscallDesc("kern_invalid", unimplementedFunc), - /* 9 */ SyscallDesc("kern_invalid", unimplementedFunc), - /* 10 */ SyscallDesc("task_self", unimplementedFunc), - /* 11 */ SyscallDesc("thread_reply", unimplementedFunc), - /* 12 */ SyscallDesc("task_notify", unimplementedFunc), - /* 13 */ SyscallDesc("thread_self", unimplementedFunc), - /* 14 */ SyscallDesc("kern_invalid", unimplementedFunc), - /* 15 */ SyscallDesc("kern_invalid", unimplementedFunc), - /* 16 */ SyscallDesc("kern_invalid", unimplementedFunc), - /* 17 */ SyscallDesc("kern_invalid", unimplementedFunc), - /* 18 */ SyscallDesc("kern_invalid", unimplementedFunc), - /* 19 */ SyscallDesc("kern_invalid", unimplementedFunc), - /* 20 */ SyscallDesc("msg_send_trap", unimplementedFunc), - /* 21 */ SyscallDesc("msg_receive_trap", unimplementedFunc), - /* 22 */ SyscallDesc("msg_rpc_trap", unimplementedFunc), - /* 23 */ SyscallDesc("kern_invalid", unimplementedFunc), - /* 24 */ SyscallDesc("nxm_block", AlphaTru64::nxm_blockFunc), - /* 25 */ SyscallDesc("nxm_unblock", AlphaTru64::nxm_unblockFunc), - /* 26 */ SyscallDesc("kern_invalid", unimplementedFunc), - /* 27 */ SyscallDesc("kern_invalid", unimplementedFunc), - /* 28 */ SyscallDesc("kern_invalid", unimplementedFunc), - /* 29 */ SyscallDesc("nxm_thread_destroy", unimplementedFunc), - /* 30 */ SyscallDesc("lw_wire", unimplementedFunc), - /* 31 */ SyscallDesc("lw_unwire", unimplementedFunc), - /* 32 */ SyscallDesc("nxm_thread_create", - AlphaTru64::nxm_thread_createFunc), - /* 33 */ SyscallDesc("nxm_task_init", AlphaTru64::nxm_task_initFunc), - /* 34 */ SyscallDesc("kern_invalid", unimplementedFunc), - /* 35 */ SyscallDesc("nxm_idle", AlphaTru64::nxm_idleFunc), - /* 36 */ SyscallDesc("nxm_wakeup_idle", unimplementedFunc), - /* 37 */ SyscallDesc("nxm_set_pthid", unimplementedFunc), - /* 38 */ SyscallDesc("nxm_thread_kill", unimplementedFunc), - /* 39 */ SyscallDesc("nxm_thread_block", AlphaTru64::nxm_thread_blockFunc), - /* 40 */ SyscallDesc("nxm_thread_wakeup", unimplementedFunc), - /* 41 */ SyscallDesc("init_process", unimplementedFunc), - /* 42 */ SyscallDesc("nxm_get_binding", unimplementedFunc), - /* 43 */ SyscallDesc("map_fd", unimplementedFunc), - /* 44 */ SyscallDesc("nxm_resched", unimplementedFunc), - /* 45 */ SyscallDesc("nxm_set_cancel", unimplementedFunc), - /* 46 */ SyscallDesc("nxm_set_binding", unimplementedFunc), - /* 47 */ SyscallDesc("stack_create", AlphaTru64::stack_createFunc), - /* 48 */ SyscallDesc("nxm_get_state", unimplementedFunc), - /* 49 */ SyscallDesc("nxm_thread_suspend", unimplementedFunc), - /* 50 */ SyscallDesc("nxm_thread_resume", unimplementedFunc), - /* 51 */ SyscallDesc("nxm_signal_check", unimplementedFunc), - /* 52 */ SyscallDesc("htg_unix_syscall", unimplementedFunc), - /* 53 */ SyscallDesc("kern_invalid", unimplementedFunc), - /* 54 */ SyscallDesc("kern_invalid", unimplementedFunc), - /* 55 */ SyscallDesc("host_self", unimplementedFunc), - /* 56 */ SyscallDesc("host_priv_self", unimplementedFunc), - /* 57 */ SyscallDesc("kern_invalid", unimplementedFunc), - /* 58 */ SyscallDesc("kern_invalid", unimplementedFunc), - /* 59 */ SyscallDesc("swtch_pri", AlphaTru64::swtch_priFunc), - /* 60 */ SyscallDesc("swtch", unimplementedFunc), - /* 61 */ SyscallDesc("thread_switch", unimplementedFunc), - /* 62 */ SyscallDesc("semop_fast", unimplementedFunc), - /* 63 */ SyscallDesc("nxm_pshared_init", unimplementedFunc), - /* 64 */ SyscallDesc("nxm_pshared_block", unimplementedFunc), - /* 65 */ SyscallDesc("nxm_pshared_unblock", unimplementedFunc), - /* 66 */ SyscallDesc("nxm_pshared_destroy", unimplementedFunc), - /* 67 */ SyscallDesc("nxm_swtch_pri", AlphaTru64::swtch_priFunc), - /* 68 */ SyscallDesc("lw_syscall", unimplementedFunc), - /* 69 */ SyscallDesc("kern_invalid", unimplementedFunc), - /* 70 */ SyscallDesc("mach_sctimes_0", unimplementedFunc), - /* 71 */ SyscallDesc("mach_sctimes_1", unimplementedFunc), - /* 72 */ SyscallDesc("mach_sctimes_2", unimplementedFunc), - /* 73 */ SyscallDesc("mach_sctimes_3", unimplementedFunc), - /* 74 */ SyscallDesc("mach_sctimes_4", unimplementedFunc), - /* 75 */ SyscallDesc("mach_sctimes_5", unimplementedFunc), - /* 76 */ SyscallDesc("mach_sctimes_6", unimplementedFunc), - /* 77 */ SyscallDesc("mach_sctimes_7", unimplementedFunc), - /* 78 */ SyscallDesc("mach_sctimes_8", unimplementedFunc), - /* 79 */ SyscallDesc("mach_sctimes_9", unimplementedFunc), - /* 80 */ SyscallDesc("mach_sctimes_10", unimplementedFunc), - /* 81 */ SyscallDesc("mach_sctimes_11", unimplementedFunc), - /* 82 */ SyscallDesc("mach_sctimes_port_alloc_dealloc", unimplementedFunc) -}; - -SyscallDesc* -AlphaTru64Process::getDesc(int callnum) -{ - if (callnum < -Num_Mach_Syscall_Descs || callnum > Num_Syscall_Descs) - return NULL; - - if (callnum < 0) - return &machSyscallDescs[-callnum]; - else - return &syscallDescs[callnum]; -} - -AlphaTru64Process::AlphaTru64Process(LiveProcessParams *params, - ObjectFile *objFile) - : AlphaLiveProcess(params, objFile), - Num_Syscall_Descs(sizeof(syscallDescs) / sizeof(SyscallDesc)), - Num_Mach_Syscall_Descs(sizeof(machSyscallDescs) / sizeof(SyscallDesc)) -{ -} diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/tru64/system.hh --- a/src/arch/alpha/tru64/system.hh Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,76 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Nathan Binkert - * Lisa Hsu - */ - -#ifndef __ARCH_ALPHA_TRU64_SYSTEM_HH__ -#define __ARCH_ALPHA_TRU64_SYSTEM_HH__ - -#include "arch/alpha/system.hh" -#include "arch/isa_traits.hh" -#include "params/Tru64AlphaSystem.hh" -#include "sim/system.hh" - -class ThreadContext; - -class BreakPCEvent; -class BadAddrEvent; -class SkipFuncEvent; -class PrintfEvent; -class DebugPrintfEvent; -class DebugPrintfrEvent; -class DumpMbufEvent; -class AlphaArguments; - -class Tru64AlphaSystem : public AlphaSystem -{ - private: -#ifdef DEBUG - /** Event to halt the simulator if the kernel calls panic() */ - BreakPCEvent *kernelPanicEvent; -#endif - - BadAddrEvent *badaddrEvent; - SkipFuncEvent *skipPowerStateEvent; - SkipFuncEvent *skipScavengeBootEvent; - PrintfEvent *printfEvent; - DebugPrintfEvent *debugPrintfEvent; - DebugPrintfrEvent *debugPrintfrEvent; - DumpMbufEvent *dumpMbufEvent; - - public: - typedef Tru64AlphaSystemParams Params; - Tru64AlphaSystem(Params *p); - ~Tru64AlphaSystem(); - - static void Printf(AlphaArguments args); - static void DumpMbuf(AlphaArguments args); -}; - -#endif // __ARCH_ALPHA_TRU64_SYSTEM_HH__ diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/tru64/system.cc --- a/src/arch/alpha/tru64/system.cc Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,92 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Nathan Binkert - * Lisa Hsu - */ - -#include "arch/alpha/tru64/system.hh" -#include "arch/isa_traits.hh" -#include "arch/vtophys.hh" -#include "base/loader/symtab.hh" -#include "base/trace.hh" -#include "cpu/base.hh" -#include "cpu/thread_context.hh" -#include "kern/tru64/tru64_events.hh" -#include "kern/system_events.hh" -#include "mem/fs_translating_port_proxy.hh" - -using namespace std; - -Tru64AlphaSystem::Tru64AlphaSystem(Tru64AlphaSystem::Params *p) - : AlphaSystem(p) -{ - Addr addr = 0; - if (kernelSymtab->findAddress("enable_async_printf", addr)) { - virtProxy.write(addr, (uint32_t)0); - } - -#ifdef DEBUG - kernelPanicEvent = addKernelFuncEventOrPanic("panic"); -#endif - - badaddrEvent = addKernelFuncEventOrPanic("badaddr"); - - skipPowerStateEvent = - addKernelFuncEvent("tl_v48_capture_power_state"); - skipScavengeBootEvent = - addKernelFuncEvent("pmap_scavenge_boot"); - -#if TRACING_ON - printfEvent = addKernelFuncEvent("printf"); - debugPrintfEvent = addKernelFuncEvent("m5printf"); - debugPrintfrEvent = addKernelFuncEvent("m5printfr"); - dumpMbufEvent = addKernelFuncEvent("m5_dump_mbuf"); -#endif -} - -Tru64AlphaSystem::~Tru64AlphaSystem() -{ -#ifdef DEBUG - delete kernelPanicEvent; -#endif - delete badaddrEvent; - delete skipPowerStateEvent; - delete skipScavengeBootEvent; -#if TRACING_ON - delete printfEvent; - delete debugPrintfEvent; - delete debugPrintfrEvent; - delete dumpMbufEvent; -#endif -} - -Tru64AlphaSystem * -Tru64AlphaSystemParams::create() -{ - return new Tru64AlphaSystem(this); -} diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/tru64/tru64.hh --- a/src/arch/alpha/tru64/tru64.hh Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,168 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Korey Sewell - */ - -#ifndef __ALPHA_ALPHA_TRU64_TRU64_HH__ -#define __ALPHA_ALPHA_TRU64_TRU64_HH__ - -#include "kern/tru64/tru64.hh" - -class AlphaTru64 : public Tru64 -{ - public: - /// This table maps the target open() flags to the corresponding - /// host open() flags. - static SyscallFlagTransTable openFlagTable[]; - - /// Number of entries in openFlagTable[]. - static const int NUM_OPEN_FLAGS; - - //@{ - /// open(2) flag values. - static const int TGT_O_RDONLY = 00000000; //!< O_RDONLY - static const int TGT_O_WRONLY = 00000001; //!< O_WRONLY - static const int TGT_O_RDWR = 00000002; //!< O_RDWR - static const int TGT_O_NONBLOCK = 00000004; //!< O_NONBLOCK - static const int TGT_O_APPEND = 00000010; //!< O_APPEND - static const int TGT_O_CREAT = 00001000; //!< O_CREAT - static const int TGT_O_TRUNC = 00002000; //!< O_TRUNC - static const int TGT_O_EXCL = 00004000; //!< O_EXCL - static const int TGT_O_NOCTTY = 00010000; //!< O_NOCTTY - static const int TGT_O_SYNC = 00040000; //!< O_SYNC - static const int TGT_O_DRD = 00100000; //!< O_DRD - static const int TGT_O_DIRECTIO = 00200000; //!< O_DIRECTIO - static const int TGT_O_CACHE = 00400000; //!< O_CACHE - static const int TGT_O_DSYNC = 02000000; //!< O_DSYNC - static const int TGT_O_RSYNC = 04000000; //!< O_RSYNC - //@} - - /// For mmap(). - static SyscallFlagTransTable mmapFlagTable[]; - - static const unsigned TGT_MAP_SHARED = 0x00001; - static const unsigned TGT_MAP_PRIVATE = 0x00002; - static const unsigned TGT_MAP_32BIT = 0x00040; - static const unsigned TGT_MAP_ANON = 0x00020; - static const unsigned TGT_MAP_DENYWRITE = 0x00800; - static const unsigned TGT_MAP_EXECUTABLE = 0x01000; - static const unsigned TGT_MAP_FILE = 0x00000; - static const unsigned TGT_MAP_GROWSDOWN = 0x00100; - static const unsigned TGT_MAP_HUGETLB = 0x40000; - static const unsigned TGT_MAP_LOCKED = 0x02000; - static const unsigned TGT_MAP_NONBLOCK = 0x10000; - static const unsigned TGT_MAP_NORESERVE = 0x04000; - static const unsigned TGT_MAP_POPULATE = 0x08000; - static const unsigned TGT_MAP_STACK = 0x20000; - static const unsigned TGT_MAP_ANONYMOUS = 0x00020; - static const unsigned TGT_MAP_FIXED = 0x00010; - - static const unsigned NUM_MMAP_FLAGS; - - //@{ - - //@{ - /// For getsysinfo(). - static const unsigned GSI_PLATFORM_NAME = 103; //!< platform name string - static const unsigned GSI_CPU_INFO = 59; //!< CPU information - static const unsigned GSI_PROC_TYPE = 60; //!< get proc_type - static const unsigned GSI_MAX_CPU = 30; //!< max # CPUs on machine - static const unsigned GSI_CPUS_IN_BOX = 55; //!< number of CPUs in system - static const unsigned GSI_PHYSMEM = 19; //!< Physical memory in KB - static const unsigned GSI_CLK_TCK = 42; //!< clock freq in Hz - //@} - - //@{ - /// For getrusage(). - static const int TGT_RUSAGE_THREAD = 1; - static const int TGT_RUSAGE_SELF = 0; - static const int TGT_RUSAGE_CHILDREN = -1; - //@} - - //@{ - /// For setsysinfo(). - static const unsigned SSI_IEEE_FP_CONTROL = 14; //!< ieee_set_fp_control() - //@} - - //@{ - /// ioctl() command codes. - static const unsigned TGT_TIOCGETP = 0x40067408; - static const unsigned TGT_TIOCSETP = 0x80067409; - static const unsigned TGT_TIOCSETN = 0x8006740a; - static const unsigned TGT_TIOCSETC = 0x80067411; - static const unsigned TGT_TIOCGETC = 0x40067412; - static const unsigned TGT_FIONREAD = 0x4004667f; - static const unsigned TGT_TIOCISATTY = 0x2000745e; - static const unsigned TGT_TCGETS = 0x402c7413; - static const unsigned TGT_TCGETA = 0x40127417; - static const unsigned TGT_TCSETAW = 0x80147419; // 2.6.15 kernel - //@} - - static bool - isTtyReq(unsigned req) - { - switch (req) { - case TGT_TIOCGETP: - case TGT_TIOCSETP: - case TGT_TIOCSETN: - case TGT_TIOCSETC: - case TGT_TIOCGETC: - case TGT_FIONREAD: - case TGT_TIOCISATTY: - case TGT_TCGETS: - case TGT_TCGETA: - case TGT_TCSETAW: - return true; - default: - return false; - } - } - - //@{ - /// For table(). - static const int TBL_SYSINFO = 12; - //@} - - /// Resource enumeration for getrlimit(). - enum rlimit_resources { - TGT_RLIMIT_CPU = 0, - TGT_RLIMIT_FSIZE = 1, - TGT_RLIMIT_DATA = 2, - TGT_RLIMIT_STACK = 3, - TGT_RLIMIT_CORE = 4, - TGT_RLIMIT_RSS = 5, - TGT_RLIMIT_NOFILE = 6, - TGT_RLIMIT_AS = 7, - TGT_RLIMIT_VMEM = 7, - TGT_RLIMIT_NPROC = 8, - TGT_RLIMIT_MEMLOCK = 9, - TGT_RLIMIT_LOCKS = 10 - }; -}; - -#endif // __ALPHA_ALPHA_TRU64_TRU64_HH__ diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/tru64/tru64.cc --- a/src/arch/alpha/tru64/tru64.cc Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,94 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Korey Sewell - */ - -#include "arch/alpha/tru64/tru64.hh" - -// open(2) flags translation table -SyscallFlagTransTable AlphaTru64::openFlagTable[] = { -#ifdef _MSC_VER - { AlphaTru64::TGT_O_RDONLY, _O_RDONLY }, - { AlphaTru64::TGT_O_WRONLY, _O_WRONLY }, - { AlphaTru64::TGT_O_RDWR, _O_RDWR }, - { AlphaTru64::TGT_O_APPEND, _O_APPEND }, - { AlphaTru64::TGT_O_CREAT, _O_CREAT }, - { AlphaTru64::TGT_O_TRUNC, _O_TRUNC }, - { AlphaTru64::TGT_O_EXCL, _O_EXCL }, -#ifdef _O_NONBLOCK - { AlphaTru64::TGT_O_NONBLOCK, _O_NONBLOCK }, -#endif -#ifdef _O_NOCTTY - { AlphaTru64::TGT_O_NOCTTY, _O_NOCTTY }, -#endif -#ifdef _O_SYNC - { AlphaTru64::TGT_O_SYNC, _O_SYNC }, -#endif -#else /* !_MSC_VER */ - { AlphaTru64::TGT_O_RDONLY, O_RDONLY }, - { AlphaTru64::TGT_O_WRONLY, O_WRONLY }, - { AlphaTru64::TGT_O_RDWR, O_RDWR }, - { AlphaTru64::TGT_O_APPEND, O_APPEND }, - { AlphaTru64::TGT_O_CREAT, O_CREAT }, - { AlphaTru64::TGT_O_TRUNC, O_TRUNC }, - { AlphaTru64::TGT_O_EXCL, O_EXCL }, - { AlphaTru64::TGT_O_NONBLOCK, O_NONBLOCK }, - { AlphaTru64::TGT_O_NOCTTY, O_NOCTTY }, -#ifdef O_SYNC - { AlphaTru64::TGT_O_SYNC, O_SYNC }, -#endif -#endif /* _MSC_VER */ -}; - -const int AlphaTru64::NUM_OPEN_FLAGS = - (sizeof(AlphaTru64::openFlagTable)/sizeof(AlphaTru64::openFlagTable[0])); - -// mmap(2) flags translation table -SyscallFlagTransTable AlphaTru64::mmapFlagTable[] = { - { TGT_MAP_SHARED, MAP_SHARED }, - { TGT_MAP_PRIVATE, MAP_PRIVATE }, - { TGT_MAP_32BIT, MAP_32BIT}, - { TGT_MAP_ANON, MAP_ANON }, - { TGT_MAP_DENYWRITE, MAP_DENYWRITE }, - { TGT_MAP_EXECUTABLE, MAP_EXECUTABLE }, - { TGT_MAP_FILE, MAP_FILE }, - { TGT_MAP_GROWSDOWN, MAP_GROWSDOWN }, - { TGT_MAP_HUGETLB, MAP_HUGETLB }, - { TGT_MAP_LOCKED, MAP_LOCKED }, - { TGT_MAP_NONBLOCK, MAP_NONBLOCK }, - { TGT_MAP_NORESERVE, MAP_NORESERVE }, - { TGT_MAP_POPULATE, MAP_POPULATE }, - { TGT_MAP_STACK, MAP_STACK }, - { TGT_MAP_ANONYMOUS, MAP_ANONYMOUS }, - { TGT_MAP_FIXED, MAP_FIXED }, -}; - -const unsigned AlphaTru64::NUM_MMAP_FLAGS = - sizeof(AlphaTru64::mmapFlagTable) / - sizeof(AlphaTru64::mmapFlagTable[0]); - diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/types.hh --- a/src/arch/alpha/types.hh Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,70 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Nathan Binkert - * Steve Reinhardt - */ - -#ifndef __ARCH_ALPHA_TYPES_HH__ -#define __ARCH_ALPHA_TYPES_HH__ - -#include "arch/generic/types.hh" -#include "base/types.hh" - -namespace AlphaISA { - -typedef uint32_t MachInst; -typedef uint64_t ExtMachInst; - -typedef GenericISA::SimplePCState PCState; - -enum annotes -{ - ANNOTE_NONE = 0, - // An impossible number for instruction annotations - ITOUCH_ANNOTE = 0xffffffff -}; - -/** - * Alpha-specific memory request flags - * - * These flags map to the architecture-specific lower 8 bits of the - * flags field in Request. - */ -struct AlphaRequestFlags -{ - typedef uint8_t ArchFlagsType; - - /** The request is an ALPHA VPTE pal access (hw_ld). */ - static const ArchFlagsType VPTE = 0x01; - /** Use the alternate mode bits in ALPHA. */ - static const ArchFlagsType ALTMODE = 0x02; -}; - -} // namespace AlphaISA - -#endif // __ARCH_ALPHA_TYPES_HH__ diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/utility.hh --- a/src/arch/alpha/utility.hh Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,121 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Nathan Binkert - * Steve Reinhardt - */ - -#ifndef __ARCH_ALPHA_UTILITY_HH__ -#define __ARCH_ALPHA_UTILITY_HH__ - -#include "arch/alpha/isa_traits.hh" -#include "arch/alpha/registers.hh" -#include "arch/alpha/types.hh" -#include "base/misc.hh" -#include "cpu/static_inst.hh" -#include "cpu/thread_context.hh" -#include "arch/alpha/ev5.hh" - -namespace AlphaISA { - -inline PCState -buildRetPC(const PCState &curPC, const PCState &callPC) -{ - PCState retPC = callPC; - retPC.advance(); - return retPC; -} - -uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp); - -inline bool -inUserMode(ThreadContext *tc) -{ - return (tc->readMiscRegNoEffect(IPR_DTB_CM) & 0x18) != 0; -} - -/** - * Function to insure ISA semantics about 0 registers. - * @param tc The thread context. - */ -template -void zeroRegisters(TC *tc); - -// Alpha IPR register accessors -inline bool PcPAL(Addr addr) { return addr & 0x3; } -inline void startupCPU(ThreadContext *tc, int cpuId) -{ tc->activate(); } - -//////////////////////////////////////////////////////////////////////// -// -// Translation stuff -// - -inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; } - -// User Virtual -inline bool IsUSeg(Addr a) { assert(USegBase == 0); return a <= USegEnd; } - -// Kernel Direct Mapped -inline bool IsK0Seg(Addr a) { return K0SegBase <= a && a <= K0SegEnd; } -inline Addr K0Seg2Phys(Addr addr) { return addr & ~K0SegBase; } - -// Kernel Virtual -inline bool IsK1Seg(Addr a) { return K1SegBase <= a && a <= K1SegEnd; } - -inline Addr -TruncPage(Addr addr) -{ return addr & ~(PageBytes - 1); } - -inline Addr -RoundPage(Addr addr) -{ return (addr + PageBytes - 1) & ~(PageBytes - 1); } - -void initIPRs(ThreadContext *tc, int cpuId); -void initCPU(ThreadContext *tc, int cpuId); - -void copyRegs(ThreadContext *src, ThreadContext *dest); - -void copyMiscRegs(ThreadContext *src, ThreadContext *dest); - -void skipFunction(ThreadContext *tc); - -inline void -advancePC(PCState &pc, const StaticInstPtr &inst) -{ - pc.advance(); -} - -inline uint64_t -getExecutingAsid(ThreadContext *tc) -{ - return DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN)); -} - -} // namespace AlphaISA - -#endif // __ARCH_ALPHA_UTILITY_HH__ diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/utility.cc --- a/src/arch/alpha/utility.cc Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,109 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Nathan Binkert - * Ali Saidi - */ - -#include "arch/alpha/utility.hh" -#include "arch/alpha/vtophys.hh" -#include "mem/fs_translating_port_proxy.hh" -#include "sim/full_system.hh" - -namespace AlphaISA { - -uint64_t -getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp) -{ - if (!FullSystem) { - panic("getArgument() is Full system only\n"); - M5_DUMMY_RETURN; - } - - const int NumArgumentRegs = 6; - if (number < NumArgumentRegs) { - if (fp) - return tc->readFloatRegBits(16 + number); - else - return tc->readIntReg(16 + number); - } else { - Addr sp = tc->readIntReg(StackPointerReg); - FSTranslatingPortProxy &vp = tc->getVirtProxy(); - uint64_t arg = vp.read(sp + - (number-NumArgumentRegs) * - sizeof(uint64_t)); - return arg; - } -} - -void -copyRegs(ThreadContext *src, ThreadContext *dest) -{ - // First loop through the integer registers. - for (int i = 0; i < NumIntRegs; ++i) - dest->setIntReg(i, src->readIntReg(i)); - - // Then loop through the floating point registers. - for (int i = 0; i < NumFloatRegs; ++i) - dest->setFloatRegBits(i, src->readFloatRegBits(i)); - - // Would need to add condition-code regs if implemented - assert(NumCCRegs == 0); - - // Copy misc. registers - copyMiscRegs(src, dest); - - // Lastly copy PC/NPC - dest->pcState(src->pcState()); -} - -void -copyMiscRegs(ThreadContext *src, ThreadContext *dest) -{ - dest->setMiscRegNoEffect(MISCREG_FPCR, - src->readMiscRegNoEffect(MISCREG_FPCR)); - dest->setMiscRegNoEffect(MISCREG_UNIQ, - src->readMiscRegNoEffect(MISCREG_UNIQ)); - dest->setMiscRegNoEffect(MISCREG_LOCKFLAG, - src->readMiscRegNoEffect(MISCREG_LOCKFLAG)); - dest->setMiscRegNoEffect(MISCREG_LOCKADDR, - src->readMiscRegNoEffect(MISCREG_LOCKADDR)); - - copyIprs(src, dest); -} - -void -skipFunction(ThreadContext *tc) -{ - TheISA::PCState newPC = tc->pcState(); - newPC.set(tc->readIntReg(ReturnAddressReg)); - tc->pcState(newPC); -} - - -} // namespace AlphaISA - diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/vtophys.hh --- a/src/arch/alpha/vtophys.hh Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,53 +0,0 @@ -/* - * Copyright (c) 2002-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Nathan Binkert - * Steve Reinhardt - */ - -#ifndef __ARCH_ALPHA_VTOPHYS_H__ -#define __ARCH_ALPHA_VTOPHYS_H__ - -#include "arch/alpha/isa_traits.hh" -#include "arch/alpha/pagetable.hh" -#include "arch/alpha/utility.hh" - -class ThreadContext; -class PortProxy; - -namespace AlphaISA { - -PageTableEntry kernel_pte_lookup(PortProxy &mem, Addr ptbr, - VAddr vaddr); - -Addr vtophys(Addr vaddr); -Addr vtophys(ThreadContext *tc, Addr vaddr); - -} // namespace AlphaISA - -#endif // __ARCH_ALPHA_VTOPHYS_H__ - diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/vtophys.cc --- a/src/arch/alpha/vtophys.cc Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,118 +0,0 @@ -/* - * Copyright (c) 2002-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Nathan Binkert - * Steve Reinhardt - * Ali Saidi - */ - -#include - -#include "arch/alpha/ev5.hh" -#include "arch/alpha/vtophys.hh" -#include "base/chunk_generator.hh" -#include "base/trace.hh" -#include "cpu/thread_context.hh" -#include "debug/VtoPhys.hh" -#include "mem/port_proxy.hh" - -using namespace std; - -namespace AlphaISA { - -PageTableEntry -kernel_pte_lookup(PortProxy &mem, Addr ptbr, VAddr vaddr) -{ - Addr level1_pte = ptbr + vaddr.level1(); - PageTableEntry level1 = mem.read(level1_pte); - if (!level1.valid()) { - DPRINTF(VtoPhys, "level 1 PTE not valid, va = %#\n", vaddr); - return 0; - } - - Addr level2_pte = level1.paddr() + vaddr.level2(); - PageTableEntry level2 = mem.read(level2_pte); - if (!level2.valid()) { - DPRINTF(VtoPhys, "level 2 PTE not valid, va = %#x\n", vaddr); - return 0; - } - - Addr level3_pte = level2.paddr() + vaddr.level3(); - PageTableEntry level3 = mem.read(level3_pte); - if (!level3.valid()) { - DPRINTF(VtoPhys, "level 3 PTE not valid, va = %#x\n", vaddr); - return 0; - } - return level3; -} - -Addr -vtophys(Addr vaddr) -{ - Addr paddr = 0; - if (IsUSeg(vaddr)) - DPRINTF(VtoPhys, "vtophys: invalid vaddr %#x", vaddr); - else if (IsK0Seg(vaddr)) - paddr = K0Seg2Phys(vaddr); - else - panic("vtophys: ptbr is not set on virtual lookup"); - - DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr); - - return paddr; -} - -Addr -vtophys(ThreadContext *tc, Addr addr) -{ - VAddr vaddr = addr; - Addr ptbr = tc->readMiscRegNoEffect(IPR_PALtemp20); - Addr paddr = 0; - //@todo Andrew couldn't remember why he commented some of this code - //so I put it back in. Perhaps something to do with gdb debugging? - if (PcPAL(vaddr) && (vaddr < PalMax)) { - paddr = vaddr & ~ULL(1); - } else { - if (IsK0Seg(vaddr)) { - paddr = K0Seg2Phys(vaddr); - } else if (!ptbr) { - paddr = vaddr; - } else { - PageTableEntry pte = - kernel_pte_lookup(tc->getPhysProxy(), ptbr, vaddr); - if (pte.valid()) - paddr = pte.paddr() | vaddr.offset(); - } - } - - - DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr); - - return paddr; -} - -} // namespace AlphaISA diff -r 9c673b990d5d -r e1835e5846b9 src/base/SConscript --- a/src/base/SConscript Mon Oct 24 21:38:48 2016 +0100 +++ b/src/base/SConscript Mon Oct 24 21:40:04 2016 +0100 @@ -60,9 +60,7 @@ Source('trace.cc') Source('types.cc') -Source('loader/aout_object.cc') Source('loader/dtb_object.cc') -Source('loader/ecoff_object.cc') Source('loader/elf_object.cc') Source('loader/hex_file.cc') Source('loader/object_file.cc') diff -r 9c673b990d5d -r e1835e5846b9 src/base/loader/aout_object.hh --- a/src/base/loader/aout_object.hh Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,63 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Steve Reinhardt - */ - -#ifndef __AOUT_OBJECT_HH__ -#define __AOUT_OBJECT_HH__ - -#include "base/loader/object_file.hh" - -// forward decls: avoid including exec_aout.h here -struct aout_exechdr; - -class AoutObject : public ObjectFile -{ - protected: - aout_exechdr *execHdr; - - AoutObject(const std::string &_filename, - size_t _len, uint8_t *_data, - Arch _arch, OpSys _opSys); - - public: - virtual ~AoutObject() {} - - virtual bool loadAllSymbols(SymbolTable *symtab, Addr base = 0, - Addr offset = 0, Addr addr_mask = maxAddr); - virtual bool loadGlobalSymbols(SymbolTable *symtab, Addr base = 0, - Addr offset = 0, - Addr addr_mask = maxAddr); - virtual bool loadLocalSymbols(SymbolTable *symtab, Addr base = 0, - Addr offset = 0, Addr addr_mask = maxAddr); - - static ObjectFile *tryFile(const std::string &fname, - size_t len, uint8_t *data); -}; - -#endif // __AOUT_OBJECT_HH__ diff -r 9c673b990d5d -r e1835e5846b9 src/base/loader/aout_object.cc --- a/src/base/loader/aout_object.cc Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,103 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Steve Reinhardt - */ - -#include - -#include "base/loader/aout_object.hh" -#include "base/loader/exec_aout.h" -#include "base/loader/symtab.hh" -#include "base/trace.hh" -#include "debug/Loader.hh" - -using namespace std; - -ObjectFile * -AoutObject::tryFile(const string &fname, size_t len, uint8_t *data) -{ - if (!N_BADMAG(*(aout_exechdr *)data)) { - // right now this is only used for Alpha PAL code - return new AoutObject(fname, len, data, - ObjectFile::Alpha, ObjectFile::UnknownOpSys); - } - else { - return NULL; - } -} - - -AoutObject::AoutObject(const string &_filename, - size_t _len, uint8_t *_data, - Arch _arch, OpSys _opSys) - : ObjectFile(_filename, _len, _data, _arch, _opSys) -{ - execHdr = (aout_exechdr *)fileData; - - entry = execHdr->entry; - - text.baseAddr = N_TXTADDR(*execHdr); - text.size = execHdr->tsize; - text.fileImage = fileData + N_TXTOFF(*execHdr); - - data.baseAddr = N_DATADDR(*execHdr); - data.size = execHdr->dsize; - data.fileImage = fileData + N_DATOFF(*execHdr); - - bss.baseAddr = N_BSSADDR(*execHdr); - bss.size = execHdr->bsize; - bss.fileImage = NULL; - - DPRINTFR(Loader, "text: 0x%x %d\ndata: 0x%x %d\nbss: 0x%x %d\n", - text.baseAddr, text.size, data.baseAddr, data.size, - bss.baseAddr, bss.size); -} - - -bool -AoutObject::loadAllSymbols(SymbolTable *symtab, Addr base, Addr offset, - Addr addr_mask) -{ - return false; -} - -bool -AoutObject::loadGlobalSymbols(SymbolTable *symtab, Addr base, Addr offset, - Addr addr_mask) -{ - // a.out symbols not supported yet - return false; -} - -bool -AoutObject::loadLocalSymbols(SymbolTable *symtab, Addr base, Addr offset, - Addr addr_mask) -{ - // a.out symbols not supported yet - return false; -} diff -r 9c673b990d5d -r e1835e5846b9 src/base/loader/ecoff_object.hh --- a/src/base/loader/ecoff_object.hh Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,65 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Steve Reinhardt - */ - -#ifndef __ECOFF_OBJECT_HH__ -#define __ECOFF_OBJECT_HH__ - -#include "base/loader/object_file.hh" - -// forward decls: avoid including exec_ecoff.h here -struct ecoff_exechdr; -struct ecoff_filehdr; -struct ecoff_aouthdr; - -class EcoffObject : public ObjectFile -{ - protected: - ecoff_exechdr *execHdr; - ecoff_filehdr *fileHdr; - ecoff_aouthdr *aoutHdr; - - EcoffObject(const std::string &_filename, size_t _len, uint8_t *_data, - Arch _arch, OpSys _opSys); - - public: - virtual ~EcoffObject() {} - - virtual bool loadAllSymbols(SymbolTable *symtab, Addr base = 0, - Addr offset = 0, Addr addr_mask = maxAddr); - virtual bool loadGlobalSymbols(SymbolTable *symtab, Addr base = 0, - Addr offset = 0, Addr addr_mask = maxAddr); - virtual bool loadLocalSymbols(SymbolTable *symtab, Addr base = 0, - Addr offset = 0, Addr addr_mask = maxAddr); - - static ObjectFile *tryFile(const std::string &fname, - size_t len, uint8_t *data); -}; - -#endif // __ECOFF_OBJECT_HH__ diff -r 9c673b990d5d -r e1835e5846b9 src/base/loader/ecoff_object.cc --- a/src/base/loader/ecoff_object.cc Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,170 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Steve Reinhardt - */ - -#include - -#include "base/loader/ecoff_object.hh" -#include "base/loader/symtab.hh" -#include "base/misc.hh" -#include "base/trace.hh" -#include "base/types.hh" -#include "debug/Loader.hh" - -// Only alpha will be able to load ecoff files for now. -// base/types.hh and ecoff_machdep.h must be before the other .h files -// because they are are gathered from other code bases and require some -// typedefs from those files. -#include "arch/alpha/ecoff_machdep.h" -#include "base/loader/coff_sym.h" -#include "base/loader/coff_symconst.h" -#include "base/loader/exec_ecoff.h" - -using namespace std; - -ObjectFile * -EcoffObject::tryFile(const string &fname, size_t len, uint8_t *data) -{ - if (((ecoff_filehdr *)data)->f_magic == ECOFF_MAGIC_ALPHA) { - // it's Alpha ECOFF - return new EcoffObject(fname, len, data, - ObjectFile::Alpha, ObjectFile::Tru64); - } - else { - return NULL; - } -} - - -EcoffObject::EcoffObject(const string &_filename, size_t _len, uint8_t *_data, - Arch _arch, OpSys _opSys) - : ObjectFile(_filename, _len, _data, _arch, _opSys) -{ - execHdr = (ecoff_exechdr *)fileData; - fileHdr = &(execHdr->f); - aoutHdr = &(execHdr->a); - - entry = aoutHdr->entry; - - text.baseAddr = aoutHdr->text_start; - text.size = aoutHdr->tsize; - text.fileImage = fileData + ECOFF_TXTOFF(execHdr); - - data.baseAddr = aoutHdr->data_start; - data.size = aoutHdr->dsize; - data.fileImage = fileData + ECOFF_DATOFF(execHdr); - - bss.baseAddr = aoutHdr->bss_start; - bss.size = aoutHdr->bsize; - bss.fileImage = NULL; - - DPRINTFR(Loader, "text: 0x%x %d\ndata: 0x%x %d\nbss: 0x%x %d\n", - text.baseAddr, text.size, data.baseAddr, data.size, - bss.baseAddr, bss.size); -} - -bool -EcoffObject::loadAllSymbols(SymbolTable *symtab, Addr base, Addr offset, - Addr addr_mask) -{ - bool retval = loadGlobalSymbols(symtab, base, offset, addr_mask); - retval = retval && loadLocalSymbols(symtab, base, offset, addr_mask); - return retval; -} - -bool -EcoffObject::loadGlobalSymbols(SymbolTable *symtab, Addr base, Addr offset, - Addr addr_mask) -{ - if (!symtab) - return false; - - if (fileHdr->f_magic != ECOFF_MAGIC_ALPHA) { - warn("loadGlobalSymbols: wrong magic on %s\n", filename); - return false; - } - - ecoff_symhdr *syms = (ecoff_symhdr *)(fileData + fileHdr->f_symptr); - if (syms->magic != magicSym2) { - warn("loadGlobalSymbols: bad symbol header magic on %s\n", filename); - return false; - } - - ecoff_extsym *ext_syms = (ecoff_extsym *)(fileData + syms->cbExtOffset); - - char *ext_strings = (char *)(fileData + syms->cbSsExtOffset); - for (int i = 0; i < syms->iextMax; i++) { - ecoff_sym *entry = &(ext_syms[i].asym); - if (entry->iss != -1) - symtab->insert(entry->value, ext_strings + entry->iss); - } - - return true; -} - -bool -EcoffObject::loadLocalSymbols(SymbolTable *symtab, Addr base, Addr offset, - Addr addr_mask) -{ - if (!symtab) - return false; - - if (fileHdr->f_magic != ECOFF_MAGIC_ALPHA) { - warn("loadGlobalSymbols: wrong magic on %s\n", filename); - return false; - } - - ecoff_symhdr *syms = (ecoff_symhdr *)(fileData + fileHdr->f_symptr); - if (syms->magic != magicSym2) { - warn("loadGlobalSymbols: bad symbol header magic on %s\n", filename); - return false; - } - - ecoff_sym *local_syms = (ecoff_sym *)(fileData + syms->cbSymOffset); - char *local_strings = (char *)(fileData + syms->cbSsOffset); - ecoff_fdr *fdesc = (ecoff_fdr *)(fileData + syms->cbFdOffset); - - for (int i = 0; i < syms->ifdMax; i++) { - ecoff_sym *entry = (ecoff_sym *)(local_syms + fdesc[i].isymBase); - char *strings = (char *)(local_strings + fdesc[i].issBase); - for (int j = 0; j < fdesc[i].csym; j++) { - if (entry[j].st == stGlobal || entry[j].st == stProc) - if (entry[j].iss != -1) - symtab->insert(entry[j].value, strings + entry[j].iss); - } - } - - for (int i = 0; i < syms->isymMax; i++) { - ecoff_sym *entry = &(local_syms[i]); - if (entry->st == stProc) - symtab->insert(entry->value, local_strings + entry->iss); - } - - return true; -} diff -r 9c673b990d5d -r e1835e5846b9 src/base/loader/elf_object.cc --- a/src/base/loader/elf_object.cc Mon Oct 24 21:38:48 2016 +0100 +++ b/src/base/loader/elf_object.cc Mon Oct 24 21:40:04 2016 +0100 @@ -123,11 +123,6 @@ fatal("The binary you're trying to load is compiled for 64-bit " "Power. M5\n only supports 32-bit Power. Please " "recompile your binary.\n"); - } else if (ehdr.e_ident[EI_CLASS] == ELFCLASS64) { - // Since we don't know how to check for alpha right now, we'll - // just assume if it wasn't something else and it's 64 bit, that's - // what it must be. - arch = Alpha; } else { warn("Unknown architecture: %d\n", ehdr.e_machine); arch = UnknownArch; diff -r 9c673b990d5d -r e1835e5846b9 src/base/loader/exec_aout.h --- a/src/base/loader/exec_aout.h Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,61 +0,0 @@ -/* - * Taken from NetBSD sys/exec_aout.h - */ - -/* $NetBSD: exec_aout.h,v 1.29 2002/12/10 17:14:31 thorpej Exp $ */ - -/* - * Copyright (c) 1993, 1994 Christopher G. Demetriou - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by Christopher G. Demetriou. - * 4. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _SYS_EXEC_AOUT_H_ -#define _SYS_EXEC_AOUT_H_ - -#ifndef N_PAGSIZ -#define N_PAGSIZ(ex) (AOUT_LDPGSZ) -#endif - -/* a_magic */ -#define OMAGIC 0407 /* old impure format */ -#define NMAGIC 0410 /* read-only text */ -#define ZMAGIC 0413 /* demand load format */ - -#define N_ALIGN(ex,x) \ - (N_GETMAGIC(ex) == ZMAGIC ? \ - ((x) + AOUT_LDPGSZ - 1) & ~(AOUT_LDPGSZ - 1) : (x)) - -/* Valid magic number check. */ -#define N_BADMAG(ex) \ - (N_GETMAGIC(ex) != NMAGIC && N_GETMAGIC(ex) != OMAGIC && \ - N_GETMAGIC(ex) != ZMAGIC) - -//Only alpha will be able to load aout for now -#include "arch/alpha/aout_machdep.h" - -#endif /* !_SYS_EXEC_AOUT_H_ */ diff -r 9c673b990d5d -r e1835e5846b9 src/base/loader/object_file.cc --- a/src/base/loader/object_file.cc Mon Oct 24 21:38:48 2016 +0100 +++ b/src/base/loader/object_file.cc Mon Oct 24 21:40:04 2016 +0100 @@ -39,9 +39,7 @@ #include #include -#include "base/loader/aout_object.hh" #include "base/loader/dtb_object.hh" -#include "base/loader/ecoff_object.hh" #include "base/loader/elf_object.hh" #include "base/loader/object_file.hh" #include "base/loader/raw_object.hh" @@ -191,14 +189,6 @@ return file_obj; } - if ((file_obj = EcoffObject::tryFile(fname, len, file_data)) != NULL) { - return file_obj; - } - - if ((file_obj = AoutObject::tryFile(fname, len, file_data)) != NULL) { - return file_obj; - } - if ((file_obj = DtbObject::tryFile(fname, len, file_data)) != NULL) { return file_obj; } diff -r 9c673b990d5d -r e1835e5846b9 src/cpu/BaseCPU.py --- a/src/cpu/BaseCPU.py Mon Oct 24 21:38:48 2016 +0100 +++ b/src/cpu/BaseCPU.py Mon Oct 24 21:40:04 2016 +0100 @@ -55,12 +55,7 @@ default_tracer = ExeTracer() -if buildEnv['TARGET_ISA'] == 'alpha': - from AlphaTLB import AlphaDTB, AlphaITB - from AlphaInterrupts import AlphaInterrupts - from AlphaISA import AlphaISA - isa_class = AlphaISA -elif buildEnv['TARGET_ISA'] == 'sparc': +if buildEnv['TARGET_ISA'] == 'sparc': from SparcTLB import SparcTLB from SparcInterrupts import SparcInterrupts from SparcISA import SparcISA @@ -153,12 +148,6 @@ interrupts = VectorParam.SparcInterrupts( [], "Interrupt Controller") isa = VectorParam.SparcISA([ isa_class() ], "ISA instance") - elif buildEnv['TARGET_ISA'] == 'alpha': - dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB") - itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB") - interrupts = VectorParam.AlphaInterrupts( - [], "Interrupt Controller") - isa = VectorParam.AlphaISA([ isa_class() ], "ISA instance") elif buildEnv['TARGET_ISA'] == 'x86': dtb = Param.X86TLB(X86TLB(), "Data TLB") itb = Param.X86TLB(X86TLB(), "Instruction TLB") @@ -226,8 +215,6 @@ def createInterruptController(self): if buildEnv['TARGET_ISA'] == 'sparc': self.interrupts = [SparcInterrupts() for i in xrange(self.numThreads)] - elif buildEnv['TARGET_ISA'] == 'alpha': - self.interrupts = [AlphaInterrupts() for i in xrange(self.numThreads)] elif buildEnv['TARGET_ISA'] == 'x86': self.apic_clk_domain = DerivedClockDomain(clk_domain = Parent.clk_domain, diff -r 9c673b990d5d -r e1835e5846b9 src/cpu/checker/cpu.hh --- a/src/cpu/checker/cpu.hh Mon Oct 24 21:38:48 2016 +0100 +++ b/src/cpu/checker/cpu.hh Mon Oct 24 21:40:04 2016 +0100 @@ -387,9 +387,6 @@ {} ///////////////////////////////////////////////////// - Fault hwrei() override { return thread->hwrei(); } - bool simPalCheck(int palFunc) override - { return thread->simPalCheck(palFunc); } void wakeup(ThreadID tid) override { } // Assume that the normal CPU's call to syscall was successful. // The checker's state would have already been updated by the syscall. diff -r 9c673b990d5d -r e1835e5846b9 src/cpu/checker/cpu_impl.hh --- a/src/cpu/checker/cpu_impl.hh Mon Oct 24 21:38:48 2016 +0100 +++ b/src/cpu/checker/cpu_impl.hh Mon Oct 24 21:40:04 2016 +0100 @@ -207,9 +207,6 @@ // maintain $r0 semantics thread->setIntReg(ZeroReg, 0); -#if THE_ISA == ALPHA_ISA - thread->setFloatReg(ZeroReg, 0.0); -#endif // Check if any recent PC changes match up with anything we // expect to happen. This is mostly to check if traps or diff -r 9c673b990d5d -r e1835e5846b9 src/cpu/exec_context.hh --- a/src/cpu/exec_context.hh Mon Oct 24 21:38:48 2016 +0100 +++ b/src/cpu/exec_context.hh Mon Oct 24 21:40:04 2016 +0100 @@ -237,25 +237,6 @@ /** * @{ - * @name Alpha-Specific Interfaces - */ - - /** - * Somewhat Alpha-specific function that handles returning from an - * error or interrupt. - */ - virtual Fault hwrei() = 0; - - /** - * Check for special simulator handling of specific PAL calls. If - * return value is false, actual PAL call will be suppressed. - */ - virtual bool simPalCheck(int palFunc) = 0; - - /** @} */ - - /** - * @{ * @name ARM-Specific Interfaces */ diff -r 9c673b990d5d -r e1835e5846b9 src/cpu/minor/exec_context.hh --- a/src/cpu/minor/exec_context.hh Mon Oct 24 21:38:48 2016 +0100 +++ b/src/cpu/minor/exec_context.hh Mon Oct 24 21:40:04 2016 +0100 @@ -98,9 +98,6 @@ pcState(inst->pc); setPredicate(true); thread.setIntReg(TheISA::ZeroReg, 0); -#if THE_ISA == ALPHA_ISA - thread.setFloatReg(TheISA::ZeroReg, 0.0); -#endif } Fault @@ -220,26 +217,6 @@ return thread.setMiscReg(reg_idx, val); } - Fault - hwrei() override - { -#if THE_ISA == ALPHA_ISA - return thread.hwrei(); -#else - return NoFault; -#endif - } - - bool - simPalCheck(int palFunc) override - { -#if THE_ISA == ALPHA_ISA - return thread.simPalCheck(palFunc); -#else - return false; -#endif - } - void syscall(int64_t callnum) override { diff -r 9c673b990d5d -r e1835e5846b9 src/cpu/minor/fetch1.cc --- a/src/cpu/minor/fetch1.cc Mon Oct 24 21:38:48 2016 +0100 +++ b/src/cpu/minor/fetch1.cc Mon Oct 24 21:40:04 2016 +0100 @@ -195,15 +195,7 @@ /* Step the PC for the next line onto the line aligned next address. * Note that as instructions can span lines, this PC is only a * reliable 'new' PC if the next line has a new stream sequence number. */ -#if THE_ISA == ALPHA_ISA - /* Restore the low bits of the PC used as address space flags */ - Addr pc_low_bits = thread.pc.instAddr() & - ((Addr) (1 << sizeof(TheISA::MachInst)) - 1); - - thread.pc.set(aligned_pc + request_size + pc_low_bits); -#else thread.pc.set(aligned_pc + request_size); -#endif } std::ostream & diff -r 9c673b990d5d -r e1835e5846b9 src/cpu/o3/commit_impl.hh --- a/src/cpu/o3/commit_impl.hh Mon Oct 24 21:38:48 2016 +0100 +++ b/src/cpu/o3/commit_impl.hh Mon Oct 24 21:40:04 2016 +0100 @@ -1040,9 +1040,7 @@ toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum; if (tid == 0) { - canHandleInterrupts = (!head_inst->isDelayedCommit()) && - ((THE_ISA != ALPHA_ISA) || - (!(pc[0].instAddr() & 0x3))); + canHandleInterrupts = !head_inst->isDelayedCommit(); } // Updates misc. registers. diff -r 9c673b990d5d -r e1835e5846b9 src/cpu/o3/cpu.hh --- a/src/cpu/o3/cpu.hh Mon Oct 24 21:38:48 2016 +0100 +++ b/src/cpu/o3/cpu.hh Mon Oct 24 21:40:04 2016 +0100 @@ -377,11 +377,6 @@ /** Traps to handle given fault. */ void trap(const Fault &fault, ThreadID tid, const StaticInstPtr &inst); - /** HW return from error interrupt. */ - Fault hwrei(ThreadID tid); - - bool simPalCheck(int palFunc, ThreadID tid); - /** Returns the Fault for any valid interrupt. */ Fault getInterrupts(); diff -r 9c673b990d5d -r e1835e5846b9 src/cpu/o3/cpu.cc --- a/src/cpu/o3/cpu.cc Mon Oct 24 21:38:48 2016 +0100 +++ b/src/cpu/o3/cpu.cc Mon Oct 24 21:40:04 2016 +0100 @@ -66,11 +66,6 @@ #include "sim/stat_control.hh" #include "sim/system.hh" -#if THE_ISA == ALPHA_ISA -#include "arch/alpha/osfpal.hh" -#include "debug/Activity.hh" -#endif - struct BaseCPUParams; using namespace TheISA; @@ -179,7 +174,7 @@ scoreboard(name() + ".scoreboard", regFile.totalNumPhysRegs(), TheISA::NumMiscRegs, - TheISA::ZeroReg, TheISA::ZeroReg), + TheISA::ZeroReg), isa(numThreads, NULL), @@ -261,8 +256,7 @@ if (active_threads > Impl::MaxThreads) { panic("Workload Size too large. Increase the 'MaxThreads' " - "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) " - "or edit your workload size."); + "constant or edit your workload size."); } } @@ -278,18 +272,9 @@ for (ThreadID tid = 0; tid < numThreads; tid++) { isa[tid] = params->isa[tid]; - // Only Alpha has an FP zero register, so for other ISAs we - // use an invalid FP register index to avoid special treatment - // of any valid FP reg. - RegIndex invalidFPReg = TheISA::NumFloatRegs + 1; - RegIndex fpZeroReg = - (THE_ISA == ALPHA_ISA) ? TheISA::ZeroReg : invalidFPReg; + commitRenameMap[tid].init(®File, TheISA::ZeroReg, &freeList); - commitRenameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg, - &freeList); - - renameMap[tid].init(®File, TheISA::ZeroReg, fpZeroReg, - &freeList); + renameMap[tid].init(®File, TheISA::ZeroReg, &freeList); } // Initialize rename map to assign physical registers to the @@ -895,47 +880,6 @@ template Fault -FullO3CPU::hwrei(ThreadID tid) -{ -#if THE_ISA == ALPHA_ISA - // Need to clear the lock flag upon returning from an interrupt. - this->setMiscRegNoEffect(AlphaISA::MISCREG_LOCKFLAG, false, tid); - - this->thread[tid]->kernelStats->hwrei(); - - // FIXME: XXX check for interrupts? XXX -#endif - return NoFault; -} - -template -bool -FullO3CPU::simPalCheck(int palFunc, ThreadID tid) -{ -#if THE_ISA == ALPHA_ISA - if (this->thread[tid]->kernelStats) - this->thread[tid]->kernelStats->callpal(palFunc, - this->threadContexts[tid]); - - switch (palFunc) { - case PAL::halt: - halt(); - if (--System::numSystemsRunning == 0) - exitSimLoop("all cpus halted"); - break; - - case PAL::bpt: - case PAL::bugchk: - if (this->system->breakpoint()) - return false; - break; - } -#endif - return true; -} - -template -Fault FullO3CPU::getInterrupts() { // Check if there are any outstanding interrupts diff -r 9c673b990d5d -r e1835e5846b9 src/cpu/o3/cpu_policy.hh --- a/src/cpu/o3/cpu_policy.hh Mon Oct 24 21:38:48 2016 +0100 +++ b/src/cpu/o3/cpu_policy.hh Mon Oct 24 21:40:04 2016 +0100 @@ -53,9 +53,7 @@ * classes use the typedefs defined here to determine what are the * classes of the other stages and communication buffers. In order to * change a structure such as the IQ, simply change the typedef here - * to use the desired class instead, and recompile. In order to - * create a different CPU to be used simultaneously with this one, see - * the alpha_impl.hh file for instructions. + * to use the desired class instead, and recompile. */ template struct SimpleCPUPolicy diff -r 9c673b990d5d -r e1835e5846b9 src/cpu/o3/dyn_inst.hh --- a/src/cpu/o3/dyn_inst.hh Mon Oct 24 21:38:48 2016 +0100 +++ b/src/cpu/o3/dyn_inst.hh Mon Oct 24 21:40:04 2016 +0100 @@ -230,11 +230,8 @@ } } } - /** Calls hardware return from error interrupt. */ - Fault hwrei(); /** Traps to handle specified fault. */ void trap(const Fault &fault); - bool simPalCheck(int palFunc); /** Emulates a syscall. */ void syscall(int64_t callnum); diff -r 9c673b990d5d -r e1835e5846b9 src/cpu/o3/dyn_inst_impl.hh --- a/src/cpu/o3/dyn_inst_impl.hh Mon Oct 24 21:38:48 2016 +0100 +++ b/src/cpu/o3/dyn_inst_impl.hh Mon Oct 24 21:40:04 2016 +0100 @@ -196,34 +196,6 @@ } template -Fault -BaseO3DynInst::hwrei() -{ -#if THE_ISA == ALPHA_ISA - // Can only do a hwrei when in pal mode. - if (!(this->instAddr() & 0x3)) - return std::make_shared(); - - // Set the next PC based on the value of the EXC_ADDR IPR. - AlphaISA::PCState pc = this->pcState(); - pc.npc(this->cpu->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR, - this->threadNumber)); - this->pcState(pc); - if (CPA::available()) { - ThreadContext *tc = this->cpu->tcBase(this->threadNumber); - CPA::cpa()->swAutoBegin(tc, this->nextInstAddr()); - } - - // Tell CPU to clear any state it needs to if a hwrei is taken. - this->cpu->hwrei(this->threadNumber); -#else - -#endif - // FIXME: XXX check for interrupts? XXX - return NoFault; -} - -template void BaseO3DynInst::trap(const Fault &fault) { @@ -231,16 +203,6 @@ } template -bool -BaseO3DynInst::simPalCheck(int palFunc) -{ -#if THE_ISA != ALPHA_ISA - panic("simPalCheck called, but PAL only exists in Alpha!\n"); -#endif - return this->cpu->simPalCheck(palFunc, this->threadNumber); -} - -template void BaseO3DynInst::syscall(int64_t callnum) { diff -r 9c673b990d5d -r e1835e5846b9 src/cpu/o3/fetch.hh --- a/src/cpu/o3/fetch.hh Mon Oct 24 21:38:48 2016 +0100 +++ b/src/cpu/o3/fetch.hh Mon Oct 24 21:40:04 2016 +0100 @@ -304,7 +304,7 @@ bool checkInterrupt(Addr pc) { - return (interruptPending && (THE_ISA != ALPHA_ISA || !(pc & 0x3))); + return interruptPending; } /** Squashes a specific thread and resets the PC. */ diff -r 9c673b990d5d -r e1835e5846b9 src/cpu/o3/regfile.hh --- a/src/cpu/o3/regfile.hh Mon Oct 24 21:38:48 2016 +0100 +++ b/src/cpu/o3/regfile.hh Mon Oct 24 21:40:04 2016 +0100 @@ -230,10 +230,7 @@ DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n", int(reg_idx), (uint64_t)val); -#if THE_ISA == ALPHA_ISA - if (reg_offset != TheISA::ZeroReg) -#endif - floatRegFile[reg_offset].d = val; + floatRegFile[reg_offset].d = val; } void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val) diff -r 9c673b990d5d -r e1835e5846b9 src/cpu/o3/rename_map.hh --- a/src/cpu/o3/rename_map.hh Mon Oct 24 21:38:48 2016 +0100 +++ b/src/cpu/o3/rename_map.hh Mon Oct 24 21:40:04 2016 +0100 @@ -192,7 +192,6 @@ /** Initializes rename map with given parameters. */ void init(PhysRegFile *_regFile, RegIndex _intZeroReg, - RegIndex _floatZeroReg, UnifiedFreeList *freeList); /** diff -r 9c673b990d5d -r e1835e5846b9 src/cpu/o3/rename_map.cc --- a/src/cpu/o3/rename_map.cc Mon Oct 24 21:38:48 2016 +0100 +++ b/src/cpu/o3/rename_map.cc Mon Oct 24 21:40:04 2016 +0100 @@ -89,14 +89,14 @@ void UnifiedRenameMap::init(PhysRegFile *_regFile, RegIndex _intZeroReg, - RegIndex _floatZeroReg, UnifiedFreeList *freeList) { regFile = _regFile; intMap.init(TheISA::NumIntRegs, &(freeList->intList), _intZeroReg); - floatMap.init(TheISA::NumFloatRegs, &(freeList->floatList), _floatZeroReg); + floatMap.init(TheISA::NumFloatRegs, &(freeList->floatList), + TheISA::NumFloatRegs + 1); ccMap.init(TheISA::NumCCRegs, &(freeList->ccList), (RegIndex)-1); } diff -r 9c673b990d5d -r e1835e5846b9 src/cpu/o3/scoreboard.hh --- a/src/cpu/o3/scoreboard.hh Mon Oct 24 21:38:48 2016 +0100 +++ b/src/cpu/o3/scoreboard.hh Mon Oct 24 21:40:04 2016 +0100 @@ -77,13 +77,9 @@ /** The index of the zero register. */ PhysRegIndex zeroRegIdx; - /** The index of the FP zero register. */ - PhysRegIndex fpZeroRegIdx; - bool isZeroReg(PhysRegIndex idx) const { - return (idx == zeroRegIdx || - (THE_ISA == ALPHA_ISA && idx == fpZeroRegIdx)); + return idx == zeroRegIdx; } public: @@ -91,14 +87,11 @@ * @param _numPhysicalRegs Number of physical registers. * @param _numMiscRegs Number of miscellaneous registers. * @param _zeroRegIdx Index of the zero register. - * @param _fpZeroRegIdx Index of the FP zero register (if any, currently - * used only for Alpha). */ Scoreboard(const std::string &_my_name, unsigned _numPhysicalRegs, unsigned _numMiscRegs, - PhysRegIndex _zeroRegIdx, - PhysRegIndex _fpZeroRegIdx); + PhysRegIndex _zeroRegIdx); /** Destructor. */ ~Scoreboard() {} diff -r 9c673b990d5d -r e1835e5846b9 src/cpu/o3/scoreboard.cc --- a/src/cpu/o3/scoreboard.cc Mon Oct 24 21:38:48 2016 +0100 +++ b/src/cpu/o3/scoreboard.cc Mon Oct 24 21:40:04 2016 +0100 @@ -36,11 +36,11 @@ Scoreboard::Scoreboard(const std::string &_my_name, unsigned _numPhysicalRegs, unsigned _numMiscRegs, - PhysRegIndex _zeroRegIdx, PhysRegIndex _fpZeroRegIdx) + PhysRegIndex _zeroRegIdx) : _name(_my_name), regScoreBoard(_numPhysicalRegs, true), numPhysRegs(_numPhysicalRegs), numTotalRegs(_numPhysicalRegs + _numMiscRegs), - zeroRegIdx(_zeroRegIdx), fpZeroRegIdx(_fpZeroRegIdx) + zeroRegIdx(_zeroRegIdx) { } diff -r 9c673b990d5d -r e1835e5846b9 src/cpu/simple/base.cc --- a/src/cpu/simple/base.cc Mon Oct 24 21:38:48 2016 +0100 +++ b/src/cpu/simple/base.cc Mon Oct 24 21:40:04 2016 +0100 @@ -471,9 +471,6 @@ // maintain $r0 semantics thread->setIntReg(ZeroReg, 0); -#if THE_ISA == ALPHA_ISA - thread->setFloatReg(ZeroReg, 0.0); -#endif // ALPHA_ISA // check for instruction-count-based events comInstEventQueue[curThread]->serviceEvents(t_info.numInst); diff -r 9c673b990d5d -r e1835e5846b9 src/cpu/simple/exec_context.hh --- a/src/cpu/simple/exec_context.hh Mon Oct 24 21:38:48 2016 +0100 +++ b/src/cpu/simple/exec_context.hh Mon Oct 24 21:40:04 2016 +0100 @@ -337,24 +337,6 @@ return thread->getTC(); } - /** - * Somewhat Alpha-specific function that handles returning from an - * error or interrupt. - */ - Fault hwrei() override - { - return thread->hwrei(); - } - - /** - * Check for special simulator handling of specific PAL calls. If - * return value is false, actual PAL call will be suppressed. - */ - bool simPalCheck(int palFunc) override - { - return thread->simPalCheck(palFunc); - } - bool readPredicate() override { return thread->readPredicate(); diff -r 9c673b990d5d -r e1835e5846b9 src/cpu/simple_thread.hh --- a/src/cpu/simple_thread.hh Mon Oct 24 21:38:48 2016 +0100 +++ b/src/cpu/simple_thread.hh Mon Oct 24 21:40:04 2016 +0100 @@ -187,10 +187,6 @@ void dumpFuncProfile(); - Fault hwrei(); - - bool simPalCheck(int palFunc); - /******************************************* * ThreadContext interface functions. ******************************************/ diff -r 9c673b990d5d -r e1835e5846b9 src/cpu/simple_thread.cc --- a/src/cpu/simple_thread.cc Mon Oct 24 21:38:48 2016 +0100 +++ b/src/cpu/simple_thread.cc Mon Oct 24 21:40:04 2016 +0100 @@ -207,19 +207,3 @@ { TheISA::copyRegs(src_tc, tc); } - -// The following methods are defined in src/arch/alpha/ev5.cc for -// Alpha. -#if THE_ISA != ALPHA_ISA -Fault -SimpleThread::hwrei() -{ - return NoFault; -} - -bool -SimpleThread::simPalCheck(int palFunc) -{ - return true; -} -#endif diff -r 9c673b990d5d -r e1835e5846b9 src/dev/alpha/AlphaBackdoor.py --- a/src/dev/alpha/AlphaBackdoor.py Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,41 +0,0 @@ -# Copyright (c) 2005-2007 The Regents of The University of Michigan -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer; -# redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution; -# neither the name of the copyright holders nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Authors: Nathan Binkert - -from m5.defines import buildEnv -from m5.params import * -from m5.proxy import * -from Device import BasicPioDevice - -class AlphaBackdoor(BasicPioDevice): - type = 'AlphaBackdoor' - cxx_header = "dev/alpha/backdoor.hh" - cpu = Param.BaseCPU(Parent.cpu[0], "Processor") - disk = Param.SimpleDisk("Simple Disk") - terminal = Param.Terminal(Parent.any, "The console terminal") - platform = Param.Platform(Parent.any, "Platform this device is part of.") - system = Param.AlphaSystem(Parent.any, "system object") diff -r 9c673b990d5d -r e1835e5846b9 src/dev/alpha/SConscript --- a/src/dev/alpha/SConscript Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,45 +0,0 @@ -# -*- mode:python -*- - -# Copyright (c) 2006 The Regents of The University of Michigan -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer; -# redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution; -# neither the name of the copyright holders nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Authors: Steve Reinhardt -# Gabe Black - -Import('*') - -if env['TARGET_ISA'] == 'alpha': - SimObject('AlphaBackdoor.py') - SimObject('Tsunami.py') - - Source('backdoor.cc') - Source('tsunami.cc') - Source('tsunami_cchip.cc') - Source('tsunami_io.cc') - Source('tsunami_pchip.cc') - - DebugFlag('AlphaBackdoor') - DebugFlag('Tsunami') diff -r 9c673b990d5d -r e1835e5846b9 src/dev/alpha/Tsunami.py --- a/src/dev/alpha/Tsunami.py Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,133 +0,0 @@ -# Copyright (c) 2005-2007 The Regents of The University of Michigan -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer; -# redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution; -# neither the name of the copyright holders nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Authors: Nathan Binkert - -from m5.params import * -from m5.proxy import * -from BadDevice import BadDevice -from AlphaBackdoor import AlphaBackdoor -from Device import BasicPioDevice, IsaFake, BadAddr -from PciHost import GenericPciHost -from Platform import Platform -from Uart import Uart8250 - -class TsunamiCChip(BasicPioDevice): - type = 'TsunamiCChip' - cxx_header = "dev/alpha/tsunami_cchip.hh" - tsunami = Param.Tsunami(Parent.any, "Tsunami") - -class TsunamiIO(BasicPioDevice): - type = 'TsunamiIO' - cxx_header = "dev/alpha/tsunami_io.hh" - time = Param.Time('01/01/2009', - "System time to use ('Now' for actual time)") - year_is_bcd = Param.Bool(False, - "The RTC should interpret the year as a BCD value") - tsunami = Param.Tsunami(Parent.any, "Tsunami") - frequency = Param.Frequency('1024Hz', "frequency of interrupts") - -class TsunamiPChip(GenericPciHost): - type = 'TsunamiPChip' - cxx_header = "dev/alpha/tsunami_pchip.hh" - - conf_base = 0x801fe000000 - conf_size = "16MB" - - pci_pio_base = 0x801fc000000 - pci_mem_base = 0x80000000000 - - pio_addr = Param.Addr("Device Address") - pio_latency = Param.Latency('100ns', "Programmed IO latency") - - tsunami = Param.Tsunami(Parent.any, "Tsunami") - -class Tsunami(Platform): - type = 'Tsunami' - cxx_header = "dev/alpha/tsunami.hh" - system = Param.System(Parent.any, "system") - - cchip = TsunamiCChip(pio_addr=0x801a0000000) - pchip = TsunamiPChip(pio_addr=0x80180000000) - fake_sm_chip = IsaFake(pio_addr=0x801fc000370) - - fake_uart1 = IsaFake(pio_addr=0x801fc0002f8) - fake_uart2 = IsaFake(pio_addr=0x801fc0003e8) - fake_uart3 = IsaFake(pio_addr=0x801fc0002e8) - fake_uart4 = IsaFake(pio_addr=0x801fc0003f0) - - fake_ppc = IsaFake(pio_addr=0x801fc0003bb) - - fake_OROM = IsaFake(pio_addr=0x800000a0000, pio_size=0x60000) - - fake_pnp_addr = IsaFake(pio_addr=0x801fc000279) - fake_pnp_write = IsaFake(pio_addr=0x801fc000a79) - fake_pnp_read0 = IsaFake(pio_addr=0x801fc000203) - fake_pnp_read1 = IsaFake(pio_addr=0x801fc000243) - fake_pnp_read2 = IsaFake(pio_addr=0x801fc000283) - fake_pnp_read3 = IsaFake(pio_addr=0x801fc0002c3) - fake_pnp_read4 = IsaFake(pio_addr=0x801fc000303) - fake_pnp_read5 = IsaFake(pio_addr=0x801fc000343) - fake_pnp_read6 = IsaFake(pio_addr=0x801fc000383) - fake_pnp_read7 = IsaFake(pio_addr=0x801fc0003c3) - - fake_ata0 = IsaFake(pio_addr=0x801fc0001f0) - fake_ata1 = IsaFake(pio_addr=0x801fc000170) - - fb = BadDevice(pio_addr=0x801fc0003d0, devicename='FrameBuffer') - io = TsunamiIO(pio_addr=0x801fc000000) - uart = Uart8250(pio_addr=0x801fc0003f8) - backdoor = AlphaBackdoor(pio_addr=0x80200000000, disk=Parent.simple_disk) - - # Attach I/O devices to specified bus object. Can't do this - # earlier, since the bus object itself is typically defined at the - # System level. - def attachIO(self, bus): - self.cchip.pio = bus.master - self.pchip.pio = bus.master - self.fake_sm_chip.pio = bus.master - self.fake_uart1.pio = bus.master - self.fake_uart2.pio = bus.master - self.fake_uart3.pio = bus.master - self.fake_uart4.pio = bus.master - self.fake_ppc.pio = bus.master - self.fake_OROM.pio = bus.master - self.fake_pnp_addr.pio = bus.master - self.fake_pnp_write.pio = bus.master - self.fake_pnp_read0.pio = bus.master - self.fake_pnp_read1.pio = bus.master - self.fake_pnp_read2.pio = bus.master - self.fake_pnp_read3.pio = bus.master - self.fake_pnp_read4.pio = bus.master - self.fake_pnp_read5.pio = bus.master - self.fake_pnp_read6.pio = bus.master - self.fake_pnp_read7.pio = bus.master - self.fake_ata0.pio = bus.master - self.fake_ata1.pio = bus.master - self.fb.pio = bus.master - self.io.pio = bus.master - self.uart.pio = bus.master - self.backdoor.pio = bus.master diff -r 9c673b990d5d -r e1835e5846b9 src/dev/alpha/access.h --- a/src/dev/alpha/access.h Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,75 +0,0 @@ -/* - * Copyright (c) 2002-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Nathan Binkert - */ - -#ifndef __ALPHA_ACCESS_H__ -#define __ALPHA_ACCESS_H__ - -/** @file - * System Console Memory Mapped Register Definition - */ - -#define ALPHA_ACCESS_VERSION (1305) - -#ifdef CONSOLE -typedef unsigned uint32_t; -typedef unsigned long uint64_t; -#endif - -// This structure hacked up from simos -struct AlphaAccess -{ - uint32_t last_offset; // 00: must be first field - uint32_t version; // 04: - uint32_t numCPUs; // 08: - uint32_t intrClockFrequency; // 0C: Hz - uint64_t cpuClock; // 10: MHz - uint64_t mem_size; // 18: - - // Loaded kernel - uint64_t kernStart; // 20: - uint64_t kernEnd; // 28: - uint64_t entryPoint; // 30: - - // console disk stuff - uint64_t diskUnit; // 38: - uint64_t diskCount; // 40: - uint64_t diskPAddr; // 48: - uint64_t diskBlock; // 50: - uint64_t diskOperation; // 58: - - // console simple output stuff - uint64_t outputChar; // 60: Placeholder for output - uint64_t inputChar; // 68: Placeholder for input - - // MP boot - uint64_t cpuStack[64]; // 70: -}; - -#endif // __ALPHA_ACCESS_H__ diff -r 9c673b990d5d -r e1835e5846b9 src/dev/alpha/backdoor.hh --- a/src/dev/alpha/backdoor.hh Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,125 +0,0 @@ -/* - * Copyright (c) 2001-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Nathan Binkert - */ - -/** @file - * System Console Backdoor Interface - */ - -#ifndef __DEV_ALPHA_BACKDOOR_HH__ -#define __DEV_ALPHA_BACKDOOR_HH__ - -#include "base/types.hh" -#include "dev/alpha/access.h" -#include "dev/io_device.hh" -#include "params/AlphaBackdoor.hh" -#include "sim/sim_object.hh" - -class BaseCPU; -class Terminal; -class AlphaSystem; -class SimpleDisk; - -/** - * Memory mapped interface to the system console. This device - * represents a shared data region between the OS Kernel and the - * System Console Backdoor. - * - * The system console is a small standalone program that is initially - * run when the system boots. It contains the necessary code to - * access the boot disk, to read/write from the console, and to pass - * boot parameters to the kernel. - * - * This version of the system console is very different from the one - * that would be found in a real system. Many of the functions use - * some sort of backdoor to get their job done. For example, reading - * from the boot device on a real system would require a minimal - * device driver to access the disk controller, but since we have a - * simulator here, we are able to bypass the disk controller and - * access the disk image directly. There are also some things like - * reading the kernel off the disk image into memory that are normally - * taken care of by the console that are now taken care of by the - * simulator. - * - * These shortcuts are acceptable since the system console is - * primarily used doing boot before the kernel has loaded its device - * drivers. - */ -class AlphaBackdoor : public BasicPioDevice -{ - protected: - struct Access : public AlphaAccess, public Serializable - { - void serialize(CheckpointOut &cp) const override; - void unserialize(CheckpointIn &cp) override; - }; - - union { - Access *alphaAccess; - uint8_t *consoleData; - }; - - /** the disk must be accessed from the console */ - SimpleDisk *disk; - - /** the system console (the terminal) is accessable from the console */ - Terminal *terminal; - - /** a pointer to the system we are running in */ - AlphaSystem *system; - - /** a pointer to the CPU boot cpu */ - BaseCPU *cpu; - - public: - typedef AlphaBackdoorParams Params; - AlphaBackdoor(const Params *p); - - const Params * - params() const - { - return dynamic_cast(_params); - } - - void startup() override; - - /** - * memory mapped reads and writes - */ - Tick read(PacketPtr pkt) override; - Tick write(PacketPtr pkt) override; - - /** - * standard serialization routines for checkpointing - */ - void serialize(CheckpointOut &cp) const override; - void unserialize(CheckpointIn &cp) override; -}; - -#endif // __DEV_ALPHA_BACKDOOR_HH__ diff -r 9c673b990d5d -r e1835e5846b9 src/dev/alpha/backdoor.cc --- a/src/dev/alpha/backdoor.cc Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,314 +0,0 @@ -/* - * Copyright (c) 2001-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Nathan Binkert - * Ali Saidi - * Steve Reinhardt - * Erik Hallnor - */ - -/** @file - * Alpha Console Backdoor Definition - */ - -#include -#include - -#include "arch/alpha/system.hh" -#include "base/inifile.hh" -#include "base/str.hh" -#include "base/trace.hh" -#include "cpu/base.hh" -#include "cpu/thread_context.hh" -#include "debug/AlphaBackdoor.hh" -#include "dev/alpha/backdoor.hh" -#include "dev/alpha/tsunami.hh" -#include "dev/alpha/tsunami_cchip.hh" -#include "dev/alpha/tsunami_io.hh" -#include "dev/platform.hh" -#include "dev/storage/simple_disk.hh" -#include "dev/terminal.hh" -#include "mem/packet.hh" -#include "mem/packet_access.hh" -#include "mem/physical.hh" -#include "params/AlphaBackdoor.hh" -#include "sim/sim_object.hh" - -using namespace std; -using namespace AlphaISA; - -AlphaBackdoor::AlphaBackdoor(const Params *p) - : BasicPioDevice(p, sizeof(struct AlphaAccess)), - disk(p->disk), terminal(p->terminal), - system(p->system), cpu(p->cpu) -{ - alphaAccess = new Access(); - alphaAccess->last_offset = pioSize - 1; - - alphaAccess->version = ALPHA_ACCESS_VERSION; - alphaAccess->diskUnit = 1; - - alphaAccess->diskCount = 0; - alphaAccess->diskPAddr = 0; - alphaAccess->diskBlock = 0; - alphaAccess->diskOperation = 0; - alphaAccess->outputChar = 0; - alphaAccess->inputChar = 0; - std::memset(alphaAccess->cpuStack, 0, sizeof(alphaAccess->cpuStack)); - -} - -void -AlphaBackdoor::startup() -{ - system->setAlphaAccess(pioAddr); - alphaAccess->numCPUs = system->numContexts(); - alphaAccess->kernStart = system->getKernelStart(); - alphaAccess->kernEnd = system->getKernelEnd(); - alphaAccess->entryPoint = system->getKernelEntry(); - alphaAccess->mem_size = system->memSize(); - alphaAccess->cpuClock = cpu->frequency() / 1000000; // In MHz - Tsunami *tsunami = dynamic_cast(params()->platform); - if (!tsunami) - fatal("Platform is not Tsunami.\n"); - alphaAccess->intrClockFrequency = tsunami->io->frequency(); -} - -Tick -AlphaBackdoor::read(PacketPtr pkt) -{ - - /** XXX Do we want to push the addr munging to a bus brige or something? So - * the device has it's physical address and then the bridge adds on whatever - * machine dependent address swizzle is required? - */ - - assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); - - Addr daddr = pkt->getAddr() - pioAddr; - - pkt->makeAtomicResponse(); - - switch (pkt->getSize()) - { - case sizeof(uint32_t): - switch (daddr) - { - case offsetof(AlphaAccess, last_offset): - pkt->set(alphaAccess->last_offset); - break; - case offsetof(AlphaAccess, version): - pkt->set(alphaAccess->version); - break; - case offsetof(AlphaAccess, numCPUs): - pkt->set(alphaAccess->numCPUs); - break; - case offsetof(AlphaAccess, intrClockFrequency): - pkt->set(alphaAccess->intrClockFrequency); - break; - default: - /* Old console code read in everyting as a 32bit int - * we now break that for better error checking. - */ - pkt->setBadAddress(); - } - DPRINTF(AlphaBackdoor, "read: offset=%#x val=%#x\n", daddr, - pkt->get()); - break; - case sizeof(uint64_t): - switch (daddr) - { - case offsetof(AlphaAccess, inputChar): - pkt->set(terminal->console_in()); - break; - case offsetof(AlphaAccess, cpuClock): - pkt->set(alphaAccess->cpuClock); - break; - case offsetof(AlphaAccess, mem_size): - pkt->set(alphaAccess->mem_size); - break; - case offsetof(AlphaAccess, kernStart): - pkt->set(alphaAccess->kernStart); - break; - case offsetof(AlphaAccess, kernEnd): - pkt->set(alphaAccess->kernEnd); - break; - case offsetof(AlphaAccess, entryPoint): - pkt->set(alphaAccess->entryPoint); - break; - case offsetof(AlphaAccess, diskUnit): - pkt->set(alphaAccess->diskUnit); - break; - case offsetof(AlphaAccess, diskCount): - pkt->set(alphaAccess->diskCount); - break; - case offsetof(AlphaAccess, diskPAddr): - pkt->set(alphaAccess->diskPAddr); - break; - case offsetof(AlphaAccess, diskBlock): - pkt->set(alphaAccess->diskBlock); - break; - case offsetof(AlphaAccess, diskOperation): - pkt->set(alphaAccess->diskOperation); - break; - case offsetof(AlphaAccess, outputChar): - pkt->set(alphaAccess->outputChar); - break; - default: - int cpunum = (daddr - offsetof(AlphaAccess, cpuStack)) / - sizeof(alphaAccess->cpuStack[0]); - - if (cpunum >= 0 && cpunum < 64) - pkt->set(alphaAccess->cpuStack[cpunum]); - else - panic("Unknown 64bit access, %#x\n", daddr); - } - DPRINTF(AlphaBackdoor, "read: offset=%#x val=%#x\n", daddr, - pkt->get()); - break; - default: - pkt->setBadAddress(); - } - return pioDelay; -} - -Tick -AlphaBackdoor::write(PacketPtr pkt) -{ - assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); - Addr daddr = pkt->getAddr() - pioAddr; - - uint64_t val = pkt->get(); - assert(pkt->getSize() == sizeof(uint64_t)); - - switch (daddr) { - case offsetof(AlphaAccess, diskUnit): - alphaAccess->diskUnit = val; - break; - - case offsetof(AlphaAccess, diskCount): - alphaAccess->diskCount = val; - break; - - case offsetof(AlphaAccess, diskPAddr): - alphaAccess->diskPAddr = val; - break; - - case offsetof(AlphaAccess, diskBlock): - alphaAccess->diskBlock = val; - break; - - case offsetof(AlphaAccess, diskOperation): - if (val == 0x13) - disk->read(alphaAccess->diskPAddr, alphaAccess->diskBlock, - alphaAccess->diskCount); - else - panic("Invalid disk operation!"); - - break; - - case offsetof(AlphaAccess, outputChar): - terminal->out((char)(val & 0xff)); - break; - - default: - int cpunum = (daddr - offsetof(AlphaAccess, cpuStack)) / - sizeof(alphaAccess->cpuStack[0]); - inform("Launching CPU %d @ %d", cpunum, curTick()); - assert(val > 0 && "Must not access primary cpu"); - if (cpunum >= 0 && cpunum < 64) - alphaAccess->cpuStack[cpunum] = val; - else - panic("Unknown 64bit access, %#x\n", daddr); - } - - pkt->makeAtomicResponse(); - - return pioDelay; -} - -void -AlphaBackdoor::Access::serialize(CheckpointOut &cp) const -{ - SERIALIZE_SCALAR(last_offset); - SERIALIZE_SCALAR(version); - SERIALIZE_SCALAR(numCPUs); - SERIALIZE_SCALAR(mem_size); - SERIALIZE_SCALAR(cpuClock); - SERIALIZE_SCALAR(intrClockFrequency); - SERIALIZE_SCALAR(kernStart); - SERIALIZE_SCALAR(kernEnd); - SERIALIZE_SCALAR(entryPoint); - SERIALIZE_SCALAR(diskUnit); - SERIALIZE_SCALAR(diskCount); - SERIALIZE_SCALAR(diskPAddr); - SERIALIZE_SCALAR(diskBlock); - SERIALIZE_SCALAR(diskOperation); - SERIALIZE_SCALAR(outputChar); - SERIALIZE_SCALAR(inputChar); - SERIALIZE_ARRAY(cpuStack,64); -} - -void -AlphaBackdoor::Access::unserialize(CheckpointIn &cp) -{ - UNSERIALIZE_SCALAR(last_offset); - UNSERIALIZE_SCALAR(version); - UNSERIALIZE_SCALAR(numCPUs); - UNSERIALIZE_SCALAR(mem_size); - UNSERIALIZE_SCALAR(cpuClock); - UNSERIALIZE_SCALAR(intrClockFrequency); - UNSERIALIZE_SCALAR(kernStart); - UNSERIALIZE_SCALAR(kernEnd); - UNSERIALIZE_SCALAR(entryPoint); - UNSERIALIZE_SCALAR(diskUnit); - UNSERIALIZE_SCALAR(diskCount); - UNSERIALIZE_SCALAR(diskPAddr); - UNSERIALIZE_SCALAR(diskBlock); - UNSERIALIZE_SCALAR(diskOperation); - UNSERIALIZE_SCALAR(outputChar); - UNSERIALIZE_SCALAR(inputChar); - UNSERIALIZE_ARRAY(cpuStack, 64); -} - -void -AlphaBackdoor::serialize(CheckpointOut &cp) const -{ - alphaAccess->serialize(cp); -} - -void -AlphaBackdoor::unserialize(CheckpointIn &cp) -{ - alphaAccess->unserialize(cp); -} - -AlphaBackdoor * -AlphaBackdoorParams::create() -{ - return new AlphaBackdoor(this); -} diff -r 9c673b990d5d -r e1835e5846b9 src/dev/alpha/tsunami.hh --- a/src/dev/alpha/tsunami.hh Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,100 +0,0 @@ -/* - * Copyright (c) 2004-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Ali Saidi - */ - -/** - * @file - * Declaration of top level class for the Tsunami chipset. This class just - * retains pointers to all its children so the children can communicate. - */ - -#ifndef __DEV_TSUNAMI_HH__ -#define __DEV_TSUNAMI_HH__ - -#include "dev/platform.hh" -#include "params/Tsunami.hh" - -class IdeController; -class TsunamiCChip; -class TsunamiPChip; -class TsunamiIO; -class System; - -/** - * Top level class for Tsunami Chipset emulation. - * This structure just contains pointers to all the - * children so the children can commnicate to do the - * read work - */ - -class Tsunami : public Platform -{ - public: - /** Max number of CPUs in a Tsunami */ - static const int Max_CPUs = 64; - - /** Pointer to the system */ - System *system; - - /** Pointer to the TsunamiIO device which has the RTC */ - TsunamiIO *io; - - /** Pointer to the Tsunami CChip. - * The chip contains some configuration information and - * all the interrupt mask and status registers - */ - TsunamiCChip *cchip; - - /** Pointer to the Tsunami PChip. - * The pchip is the interface to the PCI bus, in our case - * it does not have to do much. - */ - TsunamiPChip *pchip; - - int intr_sum_type[Tsunami::Max_CPUs]; - int ipi_pending[Tsunami::Max_CPUs]; - - void init() override; - - public: - typedef TsunamiParams Params; - Tsunami(const Params *p); - - void serialize(CheckpointOut &cp) const override; - void unserialize(CheckpointIn &cp) override; - - public: // Public Platform interfaces - void postConsoleInt() override; - void clearConsoleInt() override; - - void postPciInt(int line) override; - void clearPciInt(int line) override; -}; - -#endif // __DEV_TSUNAMI_HH__ diff -r 9c673b990d5d -r e1835e5846b9 src/dev/alpha/tsunami.cc --- a/src/dev/alpha/tsunami.cc Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,107 +0,0 @@ -/* - * Copyright (c) 2004-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Ali Saidi - */ - -/** @file - * Implementation of Tsunami platform. - */ - -#include -#include -#include - -#include "arch/alpha/system.hh" -#include "config/the_isa.hh" -#include "cpu/intr_control.hh" -#include "dev/alpha/tsunami.hh" -#include "dev/alpha/tsunami_cchip.hh" -#include "dev/alpha/tsunami_io.hh" -#include "dev/alpha/tsunami_pchip.hh" -#include "dev/terminal.hh" - -using namespace std; -//Should this be AlphaISA? -using namespace TheISA; - -Tsunami::Tsunami(const Params *p) - : Platform(p), system(p->system) -{ - for (int i = 0; i < Tsunami::Max_CPUs; i++) - intr_sum_type[i] = 0; -} - -void -Tsunami::init() -{ - AlphaSystem *alphaSystem = dynamic_cast(system); - assert(alphaSystem); - alphaSystem->setIntrFreq(io->frequency()); -} - -void -Tsunami::postConsoleInt() -{ - io->postPIC(0x10); -} - -void -Tsunami::clearConsoleInt() -{ - io->clearPIC(0x10); -} - -void -Tsunami::postPciInt(int line) -{ - cchip->postDRIR(line); -} - -void -Tsunami::clearPciInt(int line) -{ - cchip->clearDRIR(line); -} - -void -Tsunami::serialize(CheckpointOut &cp) const -{ - SERIALIZE_ARRAY(intr_sum_type, Tsunami::Max_CPUs); -} - -void -Tsunami::unserialize(CheckpointIn &cp) -{ - UNSERIALIZE_ARRAY(intr_sum_type, Tsunami::Max_CPUs); -} - -Tsunami * -TsunamiParams::create() -{ - return new Tsunami(this); -} diff -r 9c673b990d5d -r e1835e5846b9 src/dev/alpha/tsunami_cchip.hh --- a/src/dev/alpha/tsunami_cchip.hh Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,138 +0,0 @@ -/* - * Copyright (c) 2004-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Ali Saidi - */ - -/** @file - * Emulation of the Tsunami CChip CSRs - */ - -#ifndef __TSUNAMI_CCHIP_HH__ -#define __TSUNAMI_CCHIP_HH__ - -#include "dev/alpha/tsunami.hh" -#include "dev/io_device.hh" -#include "params/TsunamiCChip.hh" - -/** - * Tsunami CChip CSR Emulation. This device includes all the interrupt - * handling code for the chipset. - */ -class TsunamiCChip : public BasicPioDevice -{ - protected: - /** - * pointer to the tsunami object. - * This is our access to all the other tsunami - * devices. - */ - Tsunami *tsunami; - - /** - * The dims are device interrupt mask registers. - * One exists for each CPU, the DRIR X DIM = DIR - */ - uint64_t dim[Tsunami::Max_CPUs]; - - /** - * The dirs are device interrupt registers. - * One exists for each CPU, the DRIR X DIM = DIR - */ - uint64_t dir[Tsunami::Max_CPUs]; - - /** - * This register contains bits for each PCI interrupt - * that can occur. - */ - uint64_t drir; - - /** Indicator of which CPUs have an IPI interrupt */ - uint64_t ipint; - - /** Indicator of which CPUs have an RTC interrupt */ - uint64_t itint; - - public: - typedef TsunamiCChipParams Params; - /** - * Initialize the Tsunami CChip by setting all of the - * device register to 0. - * @param p params struct - */ - TsunamiCChip(const Params *p); - - const Params * - params() const - { - return dynamic_cast(_params); - } - - Tick read(PacketPtr pkt) override; - - Tick write(PacketPtr pkt) override; - - /** - * post an RTC interrupt to the CPU - */ - void postRTC(); - - /** - * post an interrupt to the CPU. - * @param interrupt the interrupt number to post (0-64) - */ - void postDRIR(uint32_t interrupt); - - /** - * clear an interrupt previously posted to the CPU. - * @param interrupt the interrupt number to post (0-64) - */ - void clearDRIR(uint32_t interrupt); - - /** - * post an ipi interrupt to the CPU. - * @param ipintr the cpu number to clear(bitvector) - */ - void clearIPI(uint64_t ipintr); - - /** - * clear a timer interrupt previously posted to the CPU. - * @param itintr the cpu number to clear(bitvector) - */ - void clearITI(uint64_t itintr); - - /** - * request an interrupt be posted to the CPU. - * @param ipreq the cpu number to interrupt(bitvector) - */ - void reqIPI(uint64_t ipreq); - - void serialize(CheckpointOut &cp) const override; - void unserialize(CheckpointIn &cp) override; -}; - -#endif // __TSUNAMI_CCHIP_HH__ diff -r 9c673b990d5d -r e1835e5846b9 src/dev/alpha/tsunami_cchip.cc --- a/src/dev/alpha/tsunami_cchip.cc Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,533 +0,0 @@ -/* - * Copyright (c) 2004-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Ali Saidi - * Ron Dreslinski - */ - -/** @file - * Emulation of the Tsunami CChip CSRs - */ - -#include -#include -#include - -#include "arch/alpha/ev5.hh" -#include "base/trace.hh" -#include "config/the_isa.hh" -#include "cpu/intr_control.hh" -#include "cpu/thread_context.hh" -#include "debug/IPI.hh" -#include "debug/Tsunami.hh" -#include "dev/alpha/tsunami.hh" -#include "dev/alpha/tsunami_cchip.hh" -#include "dev/alpha/tsunamireg.h" -#include "mem/packet.hh" -#include "mem/packet_access.hh" -#include "mem/port.hh" -#include "params/TsunamiCChip.hh" -#include "sim/system.hh" - -//Should this be AlphaISA? -using namespace TheISA; - -TsunamiCChip::TsunamiCChip(const Params *p) - : BasicPioDevice(p, 0x10000000), tsunami(p->tsunami) -{ - drir = 0; - ipint = 0; - itint = 0; - - for (int x = 0; x < Tsunami::Max_CPUs; x++) - { - dim[x] = 0; - dir[x] = 0; - } - - //Put back pointer in tsunami - tsunami->cchip = this; -} - -Tick -TsunamiCChip::read(PacketPtr pkt) -{ - DPRINTF(Tsunami, "read va=%#x size=%d\n", pkt->getAddr(), pkt->getSize()); - - assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); - - Addr regnum = (pkt->getAddr() - pioAddr) >> 6; - Addr daddr = (pkt->getAddr() - pioAddr); - - switch (pkt->getSize()) { - - case sizeof(uint64_t): - pkt->set(0); - - if (daddr & TSDEV_CC_BDIMS) - { - pkt->set(dim[(daddr >> 4) & 0x3F]); - break; - } - - if (daddr & TSDEV_CC_BDIRS) - { - pkt->set(dir[(daddr >> 4) & 0x3F]); - break; - } - - switch(regnum) { - case TSDEV_CC_CSR: - pkt->set(0x0); - break; - case TSDEV_CC_MTR: - panic("TSDEV_CC_MTR not implemeted\n"); - break; - case TSDEV_CC_MISC: - pkt->set(((ipint << 8) & 0xF) | ((itint << 4) & 0xF) | - (pkt->req->contextId() & 0x3)); - // currently, FS cannot handle MT so contextId and - // cpuId are effectively the same, don't know if it will - // matter if FS becomes MT enabled. I suspect no because - // we are currently able to boot up to 64 procs anyway - // which would render the CPUID of this register useless - // anyway - break; - case TSDEV_CC_AAR0: - case TSDEV_CC_AAR1: - case TSDEV_CC_AAR2: - case TSDEV_CC_AAR3: - pkt->set(0); - break; - case TSDEV_CC_DIM0: - pkt->set(dim[0]); - break; - case TSDEV_CC_DIM1: - pkt->set(dim[1]); - break; - case TSDEV_CC_DIM2: - pkt->set(dim[2]); - break; - case TSDEV_CC_DIM3: - pkt->set(dim[3]); - break; - case TSDEV_CC_DIR0: - pkt->set(dir[0]); - break; - case TSDEV_CC_DIR1: - pkt->set(dir[1]); - break; - case TSDEV_CC_DIR2: - pkt->set(dir[2]); - break; - case TSDEV_CC_DIR3: - pkt->set(dir[3]); - break; - case TSDEV_CC_DRIR: - pkt->set(drir); - break; - case TSDEV_CC_PRBEN: - panic("TSDEV_CC_PRBEN not implemented\n"); - break; - case TSDEV_CC_IIC0: - case TSDEV_CC_IIC1: - case TSDEV_CC_IIC2: - case TSDEV_CC_IIC3: - panic("TSDEV_CC_IICx not implemented\n"); - break; - case TSDEV_CC_MPR0: - case TSDEV_CC_MPR1: - case TSDEV_CC_MPR2: - case TSDEV_CC_MPR3: - panic("TSDEV_CC_MPRx not implemented\n"); - break; - case TSDEV_CC_IPIR: - pkt->set(ipint); - break; - case TSDEV_CC_ITIR: - pkt->set(itint); - break; - default: - panic("default in cchip read reached, accessing 0x%x\n"); - } // uint64_t - - break; - case sizeof(uint32_t): - case sizeof(uint16_t): - case sizeof(uint8_t): - default: - panic("invalid access size(?) for tsunami register!\n"); - } - DPRINTF(Tsunami, "Tsunami CChip: read regnum=%#x size=%d data=%lld\n", - regnum, pkt->getSize(), pkt->get()); - - pkt->makeAtomicResponse(); - return pioDelay; -} - -Tick -TsunamiCChip::write(PacketPtr pkt) -{ - assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); - Addr daddr = pkt->getAddr() - pioAddr; - Addr regnum = (pkt->getAddr() - pioAddr) >> 6 ; - - - assert(pkt->getSize() == sizeof(uint64_t)); - - DPRINTF(Tsunami, "write - addr=%#x value=%#x\n", pkt->getAddr(), pkt->get()); - - bool supportedWrite = false; - - - if (daddr & TSDEV_CC_BDIMS) - { - int number = (daddr >> 4) & 0x3F; - - uint64_t bitvector; - uint64_t olddim; - uint64_t olddir; - - olddim = dim[number]; - olddir = dir[number]; - dim[number] = pkt->get(); - dir[number] = dim[number] & drir; - for (int x = 0; x < Tsunami::Max_CPUs; x++) - { - bitvector = ULL(1) << x; - // Figure out which bits have changed - if ((dim[number] & bitvector) != (olddim & bitvector)) - { - // The bit is now set and it wasn't before (set) - if ((dim[number] & bitvector) && (dir[number] & bitvector)) - { - tsunami->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x); - DPRINTF(Tsunami, "dim write resulting in posting dir" - " interrupt to cpu %d\n", number); - } - else if ((olddir & bitvector) && - !(dir[number] & bitvector)) - { - // The bit was set and now its now clear and - // we were interrupting on that bit before - tsunami->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x); - DPRINTF(Tsunami, "dim write resulting in clear" - " dir interrupt to cpu %d\n", number); - - } - - - } - } - } else { - switch(regnum) { - case TSDEV_CC_CSR: - panic("TSDEV_CC_CSR write\n"); - case TSDEV_CC_MTR: - panic("TSDEV_CC_MTR write not implemented\n"); - case TSDEV_CC_MISC: - uint64_t ipreq; - ipreq = (pkt->get() >> 12) & 0xF; - //If it is bit 12-15, this is an IPI post - if (ipreq) { - reqIPI(ipreq); - supportedWrite = true; - } - - //If it is bit 8-11, this is an IPI clear - uint64_t ipintr; - ipintr = (pkt->get() >> 8) & 0xF; - if (ipintr) { - clearIPI(ipintr); - supportedWrite = true; - } - - //If it is the 4-7th bit, clear the RTC interrupt - uint64_t itintr; - itintr = (pkt->get() >> 4) & 0xF; - if (itintr) { - clearITI(itintr); - supportedWrite = true; - } - - // ignore NXMs - if (pkt->get() & 0x10000000) - supportedWrite = true; - - if (!supportedWrite) - panic("TSDEV_CC_MISC write not implemented\n"); - - break; - case TSDEV_CC_AAR0: - case TSDEV_CC_AAR1: - case TSDEV_CC_AAR2: - case TSDEV_CC_AAR3: - panic("TSDEV_CC_AARx write not implemeted\n"); - case TSDEV_CC_DIM0: - case TSDEV_CC_DIM1: - case TSDEV_CC_DIM2: - case TSDEV_CC_DIM3: - int number; - if (regnum == TSDEV_CC_DIM0) - number = 0; - else if (regnum == TSDEV_CC_DIM1) - number = 1; - else if (regnum == TSDEV_CC_DIM2) - number = 2; - else - number = 3; - - uint64_t bitvector; - uint64_t olddim; - uint64_t olddir; - - olddim = dim[number]; - olddir = dir[number]; - dim[number] = pkt->get(); - dir[number] = dim[number] & drir; - for (int x = 0; x < 64; x++) - { - bitvector = ULL(1) << x; - // Figure out which bits have changed - if ((dim[number] & bitvector) != (olddim & bitvector)) - { - // The bit is now set and it wasn't before (set) - if ((dim[number] & bitvector) && (dir[number] & bitvector)) - { - tsunami->intrctrl->post(number, TheISA::INTLEVEL_IRQ1, x); - DPRINTF(Tsunami, "posting dir interrupt to cpu 0\n"); - } - else if ((olddir & bitvector) && - !(dir[number] & bitvector)) - { - // The bit was set and now its now clear and - // we were interrupting on that bit before - tsunami->intrctrl->clear(number, TheISA::INTLEVEL_IRQ1, x); - DPRINTF(Tsunami, "dim write resulting in clear" - " dir interrupt to cpu %d\n", - x); - - } - - - } - } - break; - case TSDEV_CC_DIR0: - case TSDEV_CC_DIR1: - case TSDEV_CC_DIR2: - case TSDEV_CC_DIR3: - panic("TSDEV_CC_DIR write not implemented\n"); - case TSDEV_CC_DRIR: - panic("TSDEV_CC_DRIR write not implemented\n"); - case TSDEV_CC_PRBEN: - panic("TSDEV_CC_PRBEN write not implemented\n"); - case TSDEV_CC_IIC0: - case TSDEV_CC_IIC1: - case TSDEV_CC_IIC2: - case TSDEV_CC_IIC3: - panic("TSDEV_CC_IICx write not implemented\n"); - case TSDEV_CC_MPR0: - case TSDEV_CC_MPR1: - case TSDEV_CC_MPR2: - case TSDEV_CC_MPR3: - panic("TSDEV_CC_MPRx write not implemented\n"); - case TSDEV_CC_IPIR: - clearIPI(pkt->get()); - break; - case TSDEV_CC_ITIR: - clearITI(pkt->get()); - break; - case TSDEV_CC_IPIQ: - reqIPI(pkt->get()); - break; - default: - panic("default in cchip read reached, accessing 0x%x\n"); - } // swtich(regnum) - } // not BIG_TSUNAMI write - pkt->makeAtomicResponse(); - return pioDelay; -} - -void -TsunamiCChip::clearIPI(uint64_t ipintr) -{ - int numcpus = sys->threadContexts.size(); - assert(numcpus <= Tsunami::Max_CPUs); - - if (ipintr) { - for (int cpunum=0; cpunum < numcpus; cpunum++) { - // Check each cpu bit - uint64_t cpumask = ULL(1) << cpunum; - if (ipintr & cpumask) { - // Check if there is a pending ipi - if (ipint & cpumask) { - ipint &= ~cpumask; - tsunami->intrctrl->clear(cpunum, TheISA::INTLEVEL_IRQ3, 0); - DPRINTF(IPI, "clear IPI IPI cpu=%d\n", cpunum); - } - else - warn("clear IPI for CPU=%d, but NO IPI\n", cpunum); - } - } - } - else - panic("Big IPI Clear, but not processors indicated\n"); -} - -void -TsunamiCChip::clearITI(uint64_t itintr) -{ - int numcpus = sys->threadContexts.size(); - assert(numcpus <= Tsunami::Max_CPUs); - - if (itintr) { - for (int i=0; i < numcpus; i++) { - uint64_t cpumask = ULL(1) << i; - if (itintr & cpumask & itint) { - tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ2, 0); - itint &= ~cpumask; - DPRINTF(Tsunami, "clearing rtc interrupt to cpu=%d\n", i); - } - } - } - else - panic("Big ITI Clear, but not processors indicated\n"); -} - -void -TsunamiCChip::reqIPI(uint64_t ipreq) -{ - int numcpus = sys->threadContexts.size(); - assert(numcpus <= Tsunami::Max_CPUs); - - if (ipreq) { - for (int cpunum=0; cpunum < numcpus; cpunum++) { - // Check each cpu bit - uint64_t cpumask = ULL(1) << cpunum; - if (ipreq & cpumask) { - // Check if there is already an ipi (bits 8:11) - if (!(ipint & cpumask)) { - ipint |= cpumask; - tsunami->intrctrl->post(cpunum, TheISA::INTLEVEL_IRQ3, 0); - DPRINTF(IPI, "send IPI cpu=%d\n", cpunum); - } - else - warn("post IPI for CPU=%d, but IPI already\n", cpunum); - } - } - } - else - panic("Big IPI Request, but not processors indicated\n"); -} - - -void -TsunamiCChip::postRTC() -{ - int size = sys->threadContexts.size(); - assert(size <= Tsunami::Max_CPUs); - - for (int i = 0; i < size; i++) { - uint64_t cpumask = ULL(1) << i; - if (!(cpumask & itint)) { - itint |= cpumask; - tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ2, 0); - DPRINTF(Tsunami, "Posting RTC interrupt to cpu=%d\n", i); - } - } - -} - -void -TsunamiCChip::postDRIR(uint32_t interrupt) -{ - uint64_t bitvector = ULL(1) << interrupt; - uint64_t size = sys->threadContexts.size(); - assert(size <= Tsunami::Max_CPUs); - drir |= bitvector; - - for (int i=0; i < size; i++) { - dir[i] = dim[i] & drir; - if (dim[i] & bitvector) { - tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ1, interrupt); - DPRINTF(Tsunami, "posting dir interrupt to cpu %d," - "interrupt %d\n",i, interrupt); - } - } -} - -void -TsunamiCChip::clearDRIR(uint32_t interrupt) -{ - uint64_t bitvector = ULL(1) << interrupt; - uint64_t size = sys->threadContexts.size(); - assert(size <= Tsunami::Max_CPUs); - - if (drir & bitvector) - { - drir &= ~bitvector; - for (int i=0; i < size; i++) { - if (dir[i] & bitvector) { - tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ1, interrupt); - DPRINTF(Tsunami, "clearing dir interrupt to cpu %d," - "interrupt %d\n",i, interrupt); - - } - dir[i] = dim[i] & drir; - } - } - else - DPRINTF(Tsunami, "Spurrious clear? interrupt %d\n", interrupt); -} - - -void -TsunamiCChip::serialize(CheckpointOut &cp) const -{ - SERIALIZE_ARRAY(dim, Tsunami::Max_CPUs); - SERIALIZE_ARRAY(dir, Tsunami::Max_CPUs); - SERIALIZE_SCALAR(ipint); - SERIALIZE_SCALAR(itint); - SERIALIZE_SCALAR(drir); -} - -void -TsunamiCChip::unserialize(CheckpointIn &cp) -{ - UNSERIALIZE_ARRAY(dim, Tsunami::Max_CPUs); - UNSERIALIZE_ARRAY(dir, Tsunami::Max_CPUs); - UNSERIALIZE_SCALAR(ipint); - UNSERIALIZE_SCALAR(itint); - UNSERIALIZE_SCALAR(drir); -} - -TsunamiCChip * -TsunamiCChipParams::create() -{ - return new TsunamiCChip(this); -} diff -r 9c673b990d5d -r e1835e5846b9 src/dev/alpha/tsunami_io.hh --- a/src/dev/alpha/tsunami_io.hh Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,151 +0,0 @@ -/* - * Copyright (c) 2004-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Ali Saidi - * Andrew Schultz - * Miguel Serrano - */ - -/** @file - * Tsunami I/O Space mapping including RTC/timer interrupts - */ - -#ifndef __DEV_TSUNAMI_IO_HH__ -#define __DEV_TSUNAMI_IO_HH__ - -#include "dev/alpha/tsunami.hh" -#include "dev/alpha/tsunami_cchip.hh" -#include "dev/intel_8254_timer.hh" -#include "dev/io_device.hh" -#include "dev/mc146818.hh" -#include "params/TsunamiIO.hh" -#include "sim/eventq.hh" - -/** - * Tsunami I/O device is a catch all for all the south bridge stuff we care - * to implement. - */ -class TsunamiIO : public BasicPioDevice -{ - - protected: - - class RTC : public MC146818 - { - public: - Tsunami *tsunami; - RTC(const std::string &n, const TsunamiIOParams *p); - - protected: - void handleEvent() - { - //Actually interrupt the processor here - tsunami->cchip->postRTC(); - } - }; - - /** Mask of the PIC1 */ - uint8_t mask1; - - /** Mask of the PIC2 */ - uint8_t mask2; - - /** Mode of PIC1. Not used for anything */ - uint8_t mode1; - - /** Mode of PIC2. Not used for anything */ - uint8_t mode2; - - /** Raw PIC interrupt register before masking */ - uint8_t picr; //Raw PIC interrput register - - /** Is the pic interrupting right now or not. */ - bool picInterrupting; - - /** A pointer to the Tsunami device which be belong to */ - Tsunami *tsunami; - - /** Intel 8253 Periodic Interval Timer */ - Intel8254Timer pitimer; - - RTC rtc; - - uint8_t rtcAddr; - - /** The interval is set via two writes to the PIT. - * This variable contains a flag as to how many writes have happened, and - * the time so far. - */ - uint16_t timerData; - - public: - /** - * Return the freqency of the RTC - * @return interrupt rate of the RTC - */ - Tick frequency() const; - - public: - typedef TsunamiIOParams Params; - /** - * Initialize all the data for devices supported by Tsunami I/O. - * @param p pointer to Params struct - */ - TsunamiIO(const Params *p); - - const Params * - params() const - { - return dynamic_cast(_params); - } - - Tick read(PacketPtr pkt) override; - Tick write(PacketPtr pkt) override; - - /** - * Post an PIC interrupt to the CPU via the CChip - * @param bitvector interrupt to post. - */ - void postPIC(uint8_t bitvector); - - /** - * Clear a posted interrupt - * @param bitvector interrupt to clear - */ - void clearPIC(uint8_t bitvector); - - void serialize(CheckpointOut &cp) const override; - void unserialize(CheckpointIn &cp) override; - - /** - * Start running. - */ - void startup() override; - -}; - -#endif // __DEV_TSUNAMI_IO_HH__ diff -r 9c673b990d5d -r e1835e5846b9 src/dev/alpha/tsunami_io.cc --- a/src/dev/alpha/tsunami_io.cc Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,298 +0,0 @@ -/* - * Copyright (c) 2004-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Ali Saidi - * Andrew Schultz - * Miguel Serrano - */ - -/** @file - * Tsunami I/O including PIC, PIT, RTC, DMA - */ - -#include - -#include -#include -#include - -#include "base/time.hh" -#include "base/trace.hh" -#include "config/the_isa.hh" -#include "debug/Tsunami.hh" -#include "dev/alpha/tsunami.hh" -#include "dev/alpha/tsunami_cchip.hh" -#include "dev/alpha/tsunami_io.hh" -#include "dev/alpha/tsunamireg.h" -#include "dev/rtcreg.h" -#include "mem/packet.hh" -#include "mem/packet_access.hh" -#include "mem/port.hh" -#include "sim/system.hh" - -// clang complains about std::set being overloaded with Packet::set if -// we open up the entire namespace std -using std::string; -using std::ostream; - -//Should this be AlphaISA? -using namespace TheISA; - -TsunamiIO::RTC::RTC(const string &n, const TsunamiIOParams *p) - : MC146818(p->tsunami, n, p->time, p->year_is_bcd, p->frequency), - tsunami(p->tsunami) -{ -} - -TsunamiIO::TsunamiIO(const Params *p) - : BasicPioDevice(p, 0x100), tsunami(p->tsunami), - pitimer(this, p->name + "pitimer"), rtc(p->name + ".rtc", p) -{ - // set the back pointer from tsunami to myself - tsunami->io = this; - - timerData = 0; - picr = 0; - picInterrupting = false; -} - -Tick -TsunamiIO::frequency() const -{ - return SimClock::Frequency / params()->frequency; -} - -Tick -TsunamiIO::read(PacketPtr pkt) -{ - assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); - - Addr daddr = pkt->getAddr() - pioAddr; - - DPRINTF(Tsunami, "io read va=%#x size=%d IOPorrt=%#x\n", pkt->getAddr(), - pkt->getSize(), daddr); - - if (pkt->getSize() == sizeof(uint8_t)) { - switch(daddr) { - // PIC1 mask read - case TSDEV_PIC1_MASK: - pkt->set(~mask1); - break; - case TSDEV_PIC2_MASK: - pkt->set(~mask2); - break; - case TSDEV_PIC1_ISR: - // !!! If this is modified 64bit case needs to be too - // Pal code has to do a 64 bit physical read because there is - // no load physical byte instruction - pkt->set(picr); - break; - case TSDEV_PIC2_ISR: - // PIC2 not implemnted... just return 0 - pkt->set(0x00); - break; - case TSDEV_TMR0_DATA: - pkt->set(pitimer.readCounter(0)); - break; - case TSDEV_TMR1_DATA: - pkt->set(pitimer.readCounter(1)); - break; - case TSDEV_TMR2_DATA: - pkt->set(pitimer.readCounter(2)); - break; - case TSDEV_RTC_DATA: - pkt->set(rtc.readData(rtcAddr)); - break; - case TSDEV_CTRL_PORTB: - if (pitimer.outputHigh(2)) - pkt->set(PORTB_SPKR_HIGH); - else - pkt->set(0x00); - break; - default: - panic("I/O Read - va%#x size %d\n", pkt->getAddr(), pkt->getSize()); - } - } else if (pkt->getSize() == sizeof(uint64_t)) { - if (daddr == TSDEV_PIC1_ISR) - pkt->set(picr); - else - panic("I/O Read - invalid addr - va %#x size %d\n", - pkt->getAddr(), pkt->getSize()); - } else { - panic("I/O Read - invalid size - va %#x size %d\n", pkt->getAddr(), pkt->getSize()); - } - pkt->makeAtomicResponse(); - return pioDelay; -} - -Tick -TsunamiIO::write(PacketPtr pkt) -{ - assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); - Addr daddr = pkt->getAddr() - pioAddr; - - DPRINTF(Tsunami, "io write - va=%#x size=%d IOPort=%#x Data=%#x\n", - pkt->getAddr(), pkt->getSize(), pkt->getAddr() & 0xfff, (uint32_t)pkt->get()); - - assert(pkt->getSize() == sizeof(uint8_t)); - - switch(daddr) { - case TSDEV_PIC1_MASK: - mask1 = ~(pkt->get()); - if ((picr & mask1) && !picInterrupting) { - picInterrupting = true; - tsunami->cchip->postDRIR(55); - DPRINTF(Tsunami, "posting pic interrupt to cchip\n"); - } - if ((!(picr & mask1)) && picInterrupting) { - picInterrupting = false; - tsunami->cchip->clearDRIR(55); - DPRINTF(Tsunami, "clearing pic interrupt\n"); - } - break; - case TSDEV_PIC2_MASK: - mask2 = pkt->get(); - //PIC2 Not implemented to interrupt - break; - case TSDEV_PIC1_ACK: - // clear the interrupt on the PIC - picr &= ~(1 << (pkt->get() & 0xF)); - if (!(picr & mask1)) - tsunami->cchip->clearDRIR(55); - break; - case TSDEV_DMA1_MODE: - mode1 = pkt->get(); - break; - case TSDEV_DMA2_MODE: - mode2 = pkt->get(); - break; - case TSDEV_TMR0_DATA: - pitimer.writeCounter(0, pkt->get()); - break; - case TSDEV_TMR1_DATA: - pitimer.writeCounter(1, pkt->get()); - break; - case TSDEV_TMR2_DATA: - pitimer.writeCounter(2, pkt->get()); - break; - case TSDEV_TMR_CTRL: - pitimer.writeControl(pkt->get()); - break; - case TSDEV_RTC_ADDR: - rtcAddr = pkt->get(); - break; - case TSDEV_RTC_DATA: - rtc.writeData(rtcAddr, pkt->get()); - break; - case TSDEV_KBD: - case TSDEV_DMA1_CMND: - case TSDEV_DMA2_CMND: - case TSDEV_DMA1_MMASK: - case TSDEV_DMA2_MMASK: - case TSDEV_PIC2_ACK: - case TSDEV_DMA1_RESET: - case TSDEV_DMA2_RESET: - case TSDEV_DMA1_MASK: - case TSDEV_DMA2_MASK: - case TSDEV_CTRL_PORTB: - break; - default: - panic("I/O Write - va%#x size %d data %#x\n", pkt->getAddr(), pkt->getSize(), pkt->get()); - } - - pkt->makeAtomicResponse(); - return pioDelay; -} - -void -TsunamiIO::postPIC(uint8_t bitvector) -{ - //PIC2 Is not implemented, because nothing of interest there - picr |= bitvector; - if (picr & mask1) { - tsunami->cchip->postDRIR(55); - DPRINTF(Tsunami, "posting pic interrupt to cchip\n"); - } -} - -void -TsunamiIO::clearPIC(uint8_t bitvector) -{ - //PIC2 Is not implemented, because nothing of interest there - picr &= ~bitvector; - if (!(picr & mask1)) { - tsunami->cchip->clearDRIR(55); - DPRINTF(Tsunami, "clearing pic interrupt to cchip\n"); - } -} - -void -TsunamiIO::serialize(CheckpointOut &cp) const -{ - SERIALIZE_SCALAR(rtcAddr); - SERIALIZE_SCALAR(timerData); - SERIALIZE_SCALAR(mask1); - SERIALIZE_SCALAR(mask2); - SERIALIZE_SCALAR(mode1); - SERIALIZE_SCALAR(mode2); - SERIALIZE_SCALAR(picr); - SERIALIZE_SCALAR(picInterrupting); - - // Serialize the timers - pitimer.serialize("pitimer", cp); - rtc.serialize("rtc", cp); -} - -void -TsunamiIO::unserialize(CheckpointIn &cp) -{ - UNSERIALIZE_SCALAR(rtcAddr); - UNSERIALIZE_SCALAR(timerData); - UNSERIALIZE_SCALAR(mask1); - UNSERIALIZE_SCALAR(mask2); - UNSERIALIZE_SCALAR(mode1); - UNSERIALIZE_SCALAR(mode2); - UNSERIALIZE_SCALAR(picr); - UNSERIALIZE_SCALAR(picInterrupting); - - // Unserialize the timers - pitimer.unserialize("pitimer", cp); - rtc.unserialize("rtc", cp); -} - -void -TsunamiIO::startup() -{ - rtc.startup(); - pitimer.startup(); -} - -TsunamiIO * -TsunamiIOParams::create() -{ - return new TsunamiIO(this); -} diff -r 9c673b990d5d -r e1835e5846b9 src/dev/alpha/tsunami_pchip.hh --- a/src/dev/alpha/tsunami_pchip.hh Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,98 +0,0 @@ -/* - * Copyright (c) 2004-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Ali Saidi - */ - -/** @file - * Tsunami PCI interface CSRs - */ - -#ifndef __TSUNAMI_PCHIP_HH__ -#define __TSUNAMI_PCHIP_HH__ - -#include "dev/alpha/tsunami.hh" -#include "dev/pci/host.hh" -#include "params/TsunamiPChip.hh" - -/** - * A very simple implementation of the Tsunami PCI interface chips. - */ -class TsunamiPChip : public GenericPciHost -{ - protected: - - /** Pchip control register */ - uint64_t pctl; - - /** Window Base addresses */ - uint64_t wsba[4]; - - /** Window masks */ - uint64_t wsm[4]; - - /** Translated Base Addresses */ - uint64_t tba[4]; - - public: - typedef TsunamiPChipParams Params; - /** - * Register the PChip with the mmu and init all wsba, wsm, and tba to 0 - * @param p pointer to the parameters struct - */ - TsunamiPChip(const Params *p); - - const Params * - params() const - { - return dynamic_cast(_params); - } - - - void serialize(CheckpointOut &cp) const override; - void unserialize(CheckpointIn &cp) override; - - public: - Tick read(PacketPtr pkt) override; - Tick write(PacketPtr pkt) override; - - AddrRangeList getAddrRanges() const override; - - /** - * Translate a PCI bus address to a memory address for DMA. - * @todo Andrew says this needs to be fixed. What's wrong with it? - * @param pci_addr PCI address to translate. - * @return memory system address - */ - Addr dmaAddr(const PciBusAddr &addr, Addr pci_addr) const override; - - protected: - const AddrRange pioRange; - const Tick pioDelay; -}; - -#endif // __TSUNAMI_PCHIP_HH__ diff -r 9c673b990d5d -r e1835e5846b9 src/dev/alpha/tsunami_pchip.cc --- a/src/dev/alpha/tsunami_pchip.cc Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,350 +0,0 @@ -/* - * Copyright (c) 2004-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Ali Saidi - * Andrew Schultz - */ - -/** @file - * Tsunami PChip (pci) - */ -#include "dev/alpha/tsunami_pchip.hh" - -#include -#include -#include - -#include "base/trace.hh" -#include "config/the_isa.hh" -#include "debug/Tsunami.hh" -#include "dev/alpha/tsunami.hh" -#include "dev/alpha/tsunami_cchip.hh" -#include "dev/alpha/tsunamireg.h" -#include "dev/pci/device.hh" -#include "mem/packet.hh" -#include "mem/packet_access.hh" -#include "sim/system.hh" - -using namespace std; -//Should this be AlphaISA? -using namespace TheISA; - -TsunamiPChip::TsunamiPChip(const Params *p) - : GenericPciHost(p), - pioRange(RangeSize(p->pio_addr, 0x1000)), - pioDelay(p->pio_latency) -{ - for (int i = 0; i < 4; i++) { - wsba[i] = 0; - wsm[i] = 0; - tba[i] = 0; - } - - // initialize pchip control register - pctl = (ULL(0x1) << 20) | (ULL(0x1) << 32) | (ULL(0x2) << 36); - - //Set back pointer in tsunami - p->tsunami->pchip = this; -} - -Tick -TsunamiPChip::read(PacketPtr pkt) -{ - // We only need to handle our own configuration registers, pass - // unknown addresses to the generic code. - if (!pioRange.contains(pkt->getAddr())) - return GenericPciHost::read(pkt); - - Addr daddr = (pkt->getAddr() - pioRange.start()) >> 6;; - assert(pkt->getSize() == sizeof(uint64_t)); - - - DPRINTF(Tsunami, "read va=%#x size=%d\n", pkt->getAddr(), pkt->getSize()); - - switch(daddr) { - case TSDEV_PC_WSBA0: - pkt->set(wsba[0]); - break; - case TSDEV_PC_WSBA1: - pkt->set(wsba[1]); - break; - case TSDEV_PC_WSBA2: - pkt->set(wsba[2]); - break; - case TSDEV_PC_WSBA3: - pkt->set(wsba[3]); - break; - case TSDEV_PC_WSM0: - pkt->set(wsm[0]); - break; - case TSDEV_PC_WSM1: - pkt->set(wsm[1]); - break; - case TSDEV_PC_WSM2: - pkt->set(wsm[2]); - break; - case TSDEV_PC_WSM3: - pkt->set(wsm[3]); - break; - case TSDEV_PC_TBA0: - pkt->set(tba[0]); - break; - case TSDEV_PC_TBA1: - pkt->set(tba[1]); - break; - case TSDEV_PC_TBA2: - pkt->set(tba[2]); - break; - case TSDEV_PC_TBA3: - pkt->set(tba[3]); - break; - case TSDEV_PC_PCTL: - pkt->set(pctl); - break; - case TSDEV_PC_PLAT: - panic("PC_PLAT not implemented\n"); - case TSDEV_PC_RES: - panic("PC_RES not implemented\n"); - case TSDEV_PC_PERROR: - pkt->set((uint64_t)0x00); - break; - case TSDEV_PC_PERRMASK: - pkt->set((uint64_t)0x00); - break; - case TSDEV_PC_PERRSET: - panic("PC_PERRSET not implemented\n"); - case TSDEV_PC_TLBIV: - panic("PC_TLBIV not implemented\n"); - case TSDEV_PC_TLBIA: - pkt->set((uint64_t)0x00); // shouldn't be readable, but linux - break; - case TSDEV_PC_PMONCTL: - panic("PC_PMONCTL not implemented\n"); - case TSDEV_PC_PMONCNT: - panic("PC_PMONCTN not implemented\n"); - default: - panic("Default in PChip Read reached reading 0x%x\n", daddr); - } - - pkt->makeAtomicResponse(); - return pioDelay; - -} - -Tick -TsunamiPChip::write(PacketPtr pkt) -{ - // We only need to handle our own configuration registers, pass - // unknown addresses to the generic code. - if (!pioRange.contains(pkt->getAddr())) - return GenericPciHost::write(pkt); - - Addr daddr = (pkt->getAddr() - pioRange.start()) >> 6; - - assert(pkt->getSize() == sizeof(uint64_t)); - - DPRINTF(Tsunami, "write - va=%#x size=%d \n", pkt->getAddr(), pkt->getSize()); - - switch(daddr) { - case TSDEV_PC_WSBA0: - wsba[0] = pkt->get(); - break; - case TSDEV_PC_WSBA1: - wsba[1] = pkt->get(); - break; - case TSDEV_PC_WSBA2: - wsba[2] = pkt->get(); - break; - case TSDEV_PC_WSBA3: - wsba[3] = pkt->get(); - break; - case TSDEV_PC_WSM0: - wsm[0] = pkt->get(); - break; - case TSDEV_PC_WSM1: - wsm[1] = pkt->get(); - break; - case TSDEV_PC_WSM2: - wsm[2] = pkt->get(); - break; - case TSDEV_PC_WSM3: - wsm[3] = pkt->get(); - break; - case TSDEV_PC_TBA0: - tba[0] = pkt->get(); - break; - case TSDEV_PC_TBA1: - tba[1] = pkt->get(); - break; - case TSDEV_PC_TBA2: - tba[2] = pkt->get(); - break; - case TSDEV_PC_TBA3: - tba[3] = pkt->get(); - break; - case TSDEV_PC_PCTL: - pctl = pkt->get(); - break; - case TSDEV_PC_PLAT: - panic("PC_PLAT not implemented\n"); - case TSDEV_PC_RES: - panic("PC_RES not implemented\n"); - case TSDEV_PC_PERROR: - break; - case TSDEV_PC_PERRMASK: - panic("PC_PERRMASK not implemented\n"); - case TSDEV_PC_PERRSET: - panic("PC_PERRSET not implemented\n"); - case TSDEV_PC_TLBIV: - panic("PC_TLBIV not implemented\n"); - case TSDEV_PC_TLBIA: - break; // value ignored, supposted to invalidate SG TLB - case TSDEV_PC_PMONCTL: - panic("PC_PMONCTL not implemented\n"); - case TSDEV_PC_PMONCNT: - panic("PC_PMONCTN not implemented\n"); - default: - panic("Default in PChip write reached reading 0x%x\n", daddr); - - } // uint64_t - - pkt->makeAtomicResponse(); - return pioDelay; -} - - -AddrRangeList -TsunamiPChip::getAddrRanges() const -{ - return AddrRangeList({ - RangeSize(confBase, confSize), - pioRange - }); -} - - -#define DMA_ADDR_MASK ULL(0x3ffffffff) - -Addr -TsunamiPChip::dmaAddr(const PciBusAddr &dev, Addr busAddr) const -{ - // compare the address to the window base registers - uint64_t tbaMask = 0; - uint64_t baMask = 0; - - uint64_t windowMask = 0; - uint64_t windowBase = 0; - - uint64_t pteEntry = 0; - - Addr pteAddr; - Addr dmaAddr; - -#if 0 - DPRINTF(IdeDisk, "Translation for bus address: %#x\n", busAddr); - for (int i = 0; i < 4; i++) { - DPRINTF(IdeDisk, "(%d) base:%#x mask:%#x\n", - i, wsba[i], wsm[i]); - - windowBase = wsba[i]; - windowMask = ~wsm[i] & (ULL(0xfff) << 20); - - if ((busAddr & windowMask) == (windowBase & windowMask)) { - DPRINTF(IdeDisk, "Would have matched %d (wb:%#x wm:%#x --> ba&wm:%#x wb&wm:%#x)\n", - i, windowBase, windowMask, (busAddr & windowMask), - (windowBase & windowMask)); - } - } -#endif - - for (int i = 0; i < 4; i++) { - - windowBase = wsba[i]; - windowMask = ~wsm[i] & (ULL(0xfff) << 20); - - if ((busAddr & windowMask) == (windowBase & windowMask)) { - - if (wsba[i] & 0x1) { // see if enabled - if (wsba[i] & 0x2) { // see if SG bit is set - /** @todo - This currently is faked by just doing a direct - read from memory, however, to be realistic, this - needs to actually do a bus transaction. The process - is explained in the tsunami documentation on page - 10-12 and basically munges the address to look up a - PTE from a table in memory and then uses that mapping - to create an address for the SG page - */ - - tbaMask = ~(((wsm[i] & (ULL(0xfff) << 20)) >> 10) | ULL(0x3ff)); - baMask = (wsm[i] & (ULL(0xfff) << 20)) | (ULL(0x7f) << 13); - pteAddr = (tba[i] & tbaMask) | ((busAddr & baMask) >> 10); - - sys->physProxy.readBlob(pteAddr, (uint8_t*)&pteEntry, - sizeof(uint64_t)); - - dmaAddr = ((pteEntry & ~ULL(0x1)) << 12) | (busAddr & ULL(0x1fff)); - - } else { - baMask = (wsm[i] & (ULL(0xfff) << 20)) | ULL(0xfffff); - tbaMask = ~baMask; - dmaAddr = (tba[i] & tbaMask) | (busAddr & baMask); - } - - return (dmaAddr & DMA_ADDR_MASK); - } - } - } - - // if no match was found, then return the original address - return busAddr; -} - -void -TsunamiPChip::serialize(CheckpointOut &cp) const -{ - SERIALIZE_SCALAR(pctl); - SERIALIZE_ARRAY(wsba, 4); - SERIALIZE_ARRAY(wsm, 4); - SERIALIZE_ARRAY(tba, 4); -} - -void -TsunamiPChip::unserialize(CheckpointIn &cp) -{ - UNSERIALIZE_SCALAR(pctl); - UNSERIALIZE_ARRAY(wsba, 4); - UNSERIALIZE_ARRAY(wsm, 4); - UNSERIALIZE_ARRAY(tba, 4); -} - - -TsunamiPChip * -TsunamiPChipParams::create() -{ - return new TsunamiPChip(this); -} diff -r 9c673b990d5d -r e1835e5846b9 src/dev/alpha/tsunamireg.h --- a/src/dev/alpha/tsunamireg.h Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,152 +0,0 @@ -/* - * Copyright (c) 2004-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Ali Saidi - */ - -/** @file - * List of Tsunami CSRs - */ - -#ifndef __TSUNAMIREG_H__ -#define __TSUNAMIREG_H__ - -#define ALPHA_K0SEG_BASE ULL(0xfffffc0000000000) - -// CChip Registers -#define TSDEV_CC_CSR 0x00 -#define TSDEV_CC_MTR 0x01 -#define TSDEV_CC_MISC 0x02 - -#define TSDEV_CC_AAR0 0x04 -#define TSDEV_CC_AAR1 0x05 -#define TSDEV_CC_AAR2 0x06 -#define TSDEV_CC_AAR3 0x07 -#define TSDEV_CC_DIM0 0x08 -#define TSDEV_CC_DIM1 0x09 -#define TSDEV_CC_DIR0 0x0A -#define TSDEV_CC_DIR1 0x0B -#define TSDEV_CC_DRIR 0x0C -#define TSDEV_CC_PRBEN 0x0D -#define TSDEV_CC_IIC0 0x0E -#define TSDEV_CC_IIC1 0x0F -#define TSDEV_CC_MPR0 0x10 -#define TSDEV_CC_MPR1 0x11 -#define TSDEV_CC_MPR2 0x12 -#define TSDEV_CC_MPR3 0x13 - -#define TSDEV_CC_DIM2 0x18 -#define TSDEV_CC_DIM3 0x19 -#define TSDEV_CC_DIR2 0x1A -#define TSDEV_CC_DIR3 0x1B -#define TSDEV_CC_IIC2 0x1C -#define TSDEV_CC_IIC3 0x1D - -// BigTsunami Registers -#define TSDEV_CC_BDIMS 0x1000000 -#define TSDEV_CC_BDIRS 0x2000000 -#define TSDEV_CC_IPIQ 0x20 //0xf01a000800 -#define TSDEV_CC_IPIR 0x21 //0xf01a000840 -#define TSDEV_CC_ITIR 0x22 //0xf01a000880 - - -// PChip Registers -#define TSDEV_PC_WSBA0 0x00 -#define TSDEV_PC_WSBA1 0x01 -#define TSDEV_PC_WSBA2 0x02 -#define TSDEV_PC_WSBA3 0x03 -#define TSDEV_PC_WSM0 0x04 -#define TSDEV_PC_WSM1 0x05 -#define TSDEV_PC_WSM2 0x06 -#define TSDEV_PC_WSM3 0x07 -#define TSDEV_PC_TBA0 0x08 -#define TSDEV_PC_TBA1 0x09 -#define TSDEV_PC_TBA2 0x0A -#define TSDEV_PC_TBA3 0x0B -#define TSDEV_PC_PCTL 0x0C -#define TSDEV_PC_PLAT 0x0D -#define TSDEV_PC_RES 0x0E -#define TSDEV_PC_PERROR 0x0F -#define TSDEV_PC_PERRMASK 0x10 -#define TSDEV_PC_PERRSET 0x11 -#define TSDEV_PC_TLBIV 0x12 -#define TSDEV_PC_TLBIA 0x13 -#define TSDEV_PC_PMONCTL 0x14 -#define TSDEV_PC_PMONCNT 0x15 - -#define TSDEV_PC_SPST 0x20 - - -// DChip Registers -#define TSDEV_DC_DSC 0x20 -#define TSDEV_DC_STR 0x21 -#define TSDEV_DC_DREV 0x22 -#define TSDEV_DC_DSC2 0x23 - -// I/O Ports -#define TSDEV_PIC1_MASK 0x21 -#define TSDEV_PIC2_MASK 0xA1 -#define TSDEV_PIC1_ISR 0x20 -#define TSDEV_PIC2_ISR 0xA0 -#define TSDEV_PIC1_ACK 0x20 -#define TSDEV_PIC2_ACK 0xA0 -#define TSDEV_DMA1_RESET 0x0D -#define TSDEV_DMA2_RESET 0xDA -#define TSDEV_DMA1_MODE 0x0B -#define TSDEV_DMA2_MODE 0xD6 -#define TSDEV_DMA1_MASK 0x0A -#define TSDEV_DMA2_MASK 0xD4 -#define TSDEV_CTRL_PORTB 0x61 -#define TSDEV_TMR0_DATA 0x40 -#define TSDEV_TMR1_DATA 0x41 -#define TSDEV_TMR2_DATA 0x42 -#define TSDEV_TMR_CTRL 0x43 -#define TSDEV_KBD 0x64 -#define TSDEV_DMA1_CMND 0x08 -#define TSDEV_DMA1_STAT TSDEV_DMA1_CMND -#define TSDEV_DMA2_CMND 0xD0 -#define TSDEV_DMA2_STAT TSDEV_DMA2_CMND -#define TSDEV_DMA1_MMASK 0x0F -#define TSDEV_DMA2_MMASK 0xDE - -/* Added for keyboard accesses */ -#define TSDEV_KBD 0x64 - -#define TSDEV_RTC_ADDR 0x70 -#define TSDEV_RTC_DATA 0x71 - -#define PCHIP_PCI0_MEMORY ULL(0x00000000000) -#define PCHIP_PCI0_IO ULL(0x001FC000000) -#define TSUNAMI_UNCACHABLE_BIT ULL(0x80000000000) -#define TSUNAMI_PCI0_MEMORY TSUNAMI_UNCACHABLE_BIT + PCHIP_PCI0_MEMORY -#define TSUNAMI_PCI0_IO TSUNAMI_UNCACHABLE_BIT + PCHIP_PCI0_IO - - -// System Control PortB Status Bits -#define PORTB_SPKR_HIGH 0x20 - -#endif // __TSUNAMIREG_H__ diff -r 9c673b990d5d -r e1835e5846b9 src/dev/isa_fake.hh --- a/src/dev/isa_fake.hh Mon Oct 24 21:38:48 2016 +0100 +++ b/src/dev/isa_fake.hh Mon Oct 24 21:40:04 2016 +0100 @@ -38,7 +38,6 @@ #include #include "dev/io_device.hh" -// #include "dev/alpha/tsunami.hh" #include "mem/packet.hh" #include "params/IsaFake.hh" diff -r 9c673b990d5d -r e1835e5846b9 src/kern/SConscript --- a/src/kern/SConscript Mon Oct 24 21:38:48 2016 +0100 +++ b/src/kern/SConscript Mon Oct 24 21:40:04 2016 +0100 @@ -44,11 +44,3 @@ DebugFlag('DebugPrintf') DebugFlag('Printf') - -if env['TARGET_ISA'] == 'alpha': - Source('tru64/dump_mbuf.cc') - Source('tru64/printf.cc') - Source('tru64/tru64_events.cc') - Source('tru64/tru64_syscalls.cc') - - DebugFlag('BADADDR') diff -r 9c673b990d5d -r e1835e5846b9 src/kern/kernel_stats.hh --- a/src/kern/kernel_stats.hh Mon Oct 24 21:38:48 2016 +0100 +++ b/src/kern/kernel_stats.hh Mon Oct 24 21:40:04 2016 +0100 @@ -51,18 +51,12 @@ protected: Stats::Scalar _arm; Stats::Scalar _quiesce; - Stats::Scalar _hwrei; Stats::Vector _iplCount; Stats::Vector _iplGood; Stats::Vector _iplTicks; Stats::Formula _iplUsed; -#if THE_ISA == ALPHA_ISA - Stats::Vector _syscall; -#endif -// Stats::Vector _faults; - private: int iplLast; Tick iplLastTick; diff -r 9c673b990d5d -r e1835e5846b9 src/kern/kernel_stats.cc --- a/src/kern/kernel_stats.cc Mon Oct 24 21:38:48 2016 +0100 +++ b/src/kern/kernel_stats.cc Mon Oct 24 21:40:04 2016 +0100 @@ -34,9 +34,6 @@ #include "base/trace.hh" #include "cpu/thread_context.hh" #include "kern/kernel_stats.hh" -#if THE_ISA == ALPHA_ISA -#include "kern/tru64/tru64_syscalls.hh" -#endif #include "sim/system.hh" using namespace std; @@ -92,14 +89,6 @@ ; _iplUsed = _iplGood / _iplCount; -#if THE_ISA == ALPHA_ISA - _syscall - .init(SystemCalls::Number) - .name(name() + ".syscall") - .desc("number of syscalls executed") - .flags(total | pdf | nozero | nonan) - ; -#endif //@todo This needs to get the names of syscalls from an appropriate place. #if 0 diff -r 9c673b990d5d -r e1835e5846b9 src/kern/tru64/dump_mbuf.hh --- a/src/kern/tru64/dump_mbuf.hh Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,40 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Nathan Binkert - */ - -#ifndef __DUMP_MBUF_HH__ -#define __DUMP_MBUF_HH__ - -#include "sim/arguments.hh" - -namespace tru64 { - void DumpMbuf(Arguments args); -} - -#endif // __DUMP_MBUF_HH__ diff -r 9c673b990d5d -r e1835e5846b9 src/kern/tru64/dump_mbuf.cc --- a/src/kern/tru64/dump_mbuf.cc Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,82 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Nathan Binkert - */ - -#include - -#include - -#include "arch/isa_traits.hh" -#include "arch/vtophys.hh" -#include "base/loader/symtab.hh" -#include "base/cprintf.hh" -#include "base/trace.hh" -#include "base/types.hh" -#include "config/the_isa.hh" -#include "cpu/thread_context.hh" -#include "kern/tru64/dump_mbuf.hh" -#include "kern/tru64/mbuf.hh" -#include "sim/arguments.hh" -#include "sim/system.hh" - -using namespace TheISA; - -namespace tru64 { - -void -DumpMbuf(Arguments args) -{ - ThreadContext *tc = args.getThreadContext(); - StringWrap name(tc->getSystemPtr()->name()); - Addr addr = (Addr)args; - struct mbuf m; - - CopyOut(tc, &m, addr, sizeof(m)); - - int count = m.m_pkthdr.len; - - DPRINTFN("m=%#lx, m->m_pkthdr.len=%#d\n", addr, m.m_pkthdr.len); - - while (count > 0) { - DPRINTFN("m=%#lx, m->m_data=%#lx, m->m_len=%d\n", - addr, m.m_data, m.m_len); - char *buffer = new char[m.m_len]; - CopyOut(tc, buffer, m.m_data, m.m_len); - DDUMPN((uint8_t *)buffer, m.m_len); - delete [] buffer; - - count -= m.m_len; - if (!m.m_next) - break; - - CopyOut(tc, &m, m.m_next, sizeof(m)); - } -} - -} // namespace Tru64 diff -r 9c673b990d5d -r e1835e5846b9 src/kern/tru64/mbuf.hh --- a/src/kern/tru64/mbuf.hh Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,100 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Nathan Binkert - */ - -#ifndef __MBUF_HH__ -#define __MBUF_HH__ - -#include "arch/isa_traits.hh" -#include "base/types.hh" - -namespace tru64 { - -struct m_hdr { - Addr mh_next; // 0x00 - Addr mh_nextpkt; // 0x08 - Addr mh_data; // 0x10 - int32_t mh_len; // 0x18 - int32_t mh_type; // 0x1C - int32_t mh_flags; // 0x20 - int32_t mh_pad0; // 0x24 - Addr mh_foo[4]; // 0x28, 0x30, 0x38, 0x40 -}; - -struct pkthdr { - int32_t len; - int32_t protocolSum; - Addr rcvif; -}; - -struct m_ext { - Addr ext_buf; // 0x00 - Addr ext_free; // 0x08 - uint32_t ext_size; // 0x10 - uint32_t ext_pad0; // 0x14 - Addr ext_arg; // 0x18 - struct ext_refq { - Addr forw, back; // 0x20, 0x28 - } ext_ref; - Addr uiomove_f; // 0x30 - int32_t protocolSum; // 0x38 - int32_t bytesSummed; // 0x3C - Addr checksum; // 0x40 -}; - -struct mbuf { - struct m_hdr m_hdr; - union { - struct { - struct pkthdr MH_pkthdr; - union { - struct m_ext MH_ext; - char MH_databuf[1]; - } MH_dat; - } MH; - char M_databuf[1]; - } M_dat; -}; - -#define m_attr m_hdr.mh_attr -#define m_next m_hdr.mh_next -#define m_len m_hdr.mh_len -#define m_data m_hdr.mh_data -#define m_type m_hdr.mh_type -#define m_flags m_hdr.mh_flags -#define m_nextpkt m_hdr.mh_nextpkt -#define m_act m_nextpkt -#define m_pkthdr M_dat.MH.MH_pkthdr -#define m_ext M_dat.MH.MH_dat.MH_ext -#define m_pktdat M_dat.MH.MH_dat.MH_databuf -#define m_dat M_dat.M_databuf - -} - -#endif // __MBUF_HH__ diff -r 9c673b990d5d -r e1835e5846b9 src/kern/tru64/printf.hh --- a/src/kern/tru64/printf.hh Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,40 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Nathan Binkert - */ - -#ifndef __PRINTF_HH__ -#define __PRINTF_HH__ - -#include "sim/arguments.hh" - -namespace tru64 { - void Printf(Arguments args); -} - -#endif // __PRINTF_HH__ diff -r 9c673b990d5d -r e1835e5846b9 src/kern/tru64/printf.cc --- a/src/kern/tru64/printf.cc Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,272 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Nathan Binkert - */ - -#include - -#include - -#include "arch/vtophys.hh" -#include "base/cprintf.hh" -#include "base/trace.hh" -#include "base/types.hh" -#include "kern/tru64/printf.hh" -#include "sim/arguments.hh" - -using namespace std; - -namespace tru64 { - -void -Printf(Arguments args) -{ - std::ostream &out = Trace::output(); - - char *p = (char *)args++; - - ios::fmtflags saved_flags = out.flags(); - char old_fill = out.fill(); - int old_precision = out.precision(); - - while (*p) { - switch (*p) { - case '%': { - bool more = true; - bool islong = false; - bool leftjustify = false; - bool format = false; - bool zero = false; - int width = 0; - while (more && *++p) { - switch (*p) { - case 'l': - case 'L': - islong = true; - break; - case '-': - leftjustify = true; - break; - case '#': - format = true; - break; - case '0': - if (width) - width *= 10; - else - zero = true; - break; - default: - if (*p >= '1' && *p <= '9') - width = 10 * width + *p - '0'; - else - more = false; - break; - } - } - - bool hexnum = false; - bool octal = false; - bool sign = false; - switch (*p) { - case 'X': - case 'x': - hexnum = true; - break; - case 'O': - case 'o': - octal = true; - break; - case 'D': - case 'd': - sign = true; - break; - case 'P': - format = true; - case 'p': - hexnum = true; - break; - } - - switch (*p) { - case 'D': - case 'd': - case 'U': - case 'u': - case 'X': - case 'x': - case 'O': - case 'o': - case 'P': - case 'p': { - if (hexnum) - out << hex; - - if (octal) - out << oct; - - if (format) { - if (!zero) - out.setf(ios::showbase); - else { - if (hexnum) { - out << "0x"; - width -= 2; - } else if (octal) { - out << "0"; - width -= 1; - } - } - } - - if (zero) - out.fill('0'); - - if (width > 0) - out.width(width); - - if (leftjustify && !zero) - out.setf(ios::left); - - if (sign) { - if (islong) - out << (int64_t)args; - else - out << (int32_t)args; - } else { - if (islong) - out << (uint64_t)args; - else - out << (uint32_t)args; - } - - if (zero) - out.fill(' '); - - if (width > 0) - out.width(0); - - out << dec; - - ++args; - } - break; - - case 's': { - const char *s = (char *)args; - if (!s) - s = ""; - - if (width > 0) - out.width(width); - if (leftjustify) - out.setf(ios::left); - - out << s; - ++args; - } - break; - case 'C': - case 'c': { - uint64_t mask = (*p == 'C') ? 0xffL : 0x7fL; - uint64_t num; - int width; - - if (islong) { - num = (uint64_t)args; - width = sizeof(uint64_t); - } else { - num = (uint32_t)args; - width = sizeof(uint32_t); - } - - while (width-- > 0) { - char c = (char)(num & mask); - if (c) - out << c; - num >>= 8; - } - - ++args; - } - break; - case 'b': { - uint64_t n = (uint64_t)args++; - char *s = (char *)args++; - out << s << ": " << n; - } - break; - case 'n': - case 'N': { - args += 2; -#if 0 - uint64_t n = (uint64_t)args++; - struct reg_values *rv = (struct reg_values *)args++; -#endif - } - break; - case 'r': - case 'R': { - args += 2; -#if 0 - uint64_t n = (uint64_t)args++; - struct reg_desc *rd = (struct reg_desc *)args++; -#endif - } - break; - case '%': - out << '%'; - break; - } - ++p; - } - break; - case '\n': - out << endl; - ++p; - break; - case '\r': - ++p; - if (*p != '\n') - out << endl; - break; - - default: { - size_t len = strcspn(p, "%\n\r\0"); - out.write(p, len); - p += len; - } - } - } - - out.flags(saved_flags); - out.fill(old_fill); - out.precision(old_precision); -} - -} // namespace Tru64 diff -r 9c673b990d5d -r e1835e5846b9 src/kern/tru64/tru64.hh --- a/src/kern/tru64/tru64.hh Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,1222 +0,0 @@ -/* - * Copyright (c) 2001-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Nathan Binkert - * Ali Saidi - */ - -#ifndef __TRU64_HH__ -#define __TRU64_HH__ - -#include "kern/operatingsystem.hh" -#include "sim/byteswap.hh" - -#include -#include -#if defined(__OpenBSD__) || defined(__APPLE__) || defined(__FreeBSD__) -#include -#include -#else -#include -#endif - -#include -#include -#include - -#include -#include // for memset() - -#include "arch/alpha/registers.hh" -#include "config/the_isa.hh" -#include "cpu/base.hh" -#include "debug/SyscallVerbose.hh" -#include "sim/core.hh" -#include "sim/syscall_emul.hh" - -typedef struct stat global_stat; -typedef struct statfs global_statfs; -typedef struct dirent global_dirent; - -class SETranslatingPortProxy; - -/// -/// This class encapsulates the types, structures, constants, -/// functions, and syscall-number mappings specific to the Alpha Tru64 -/// syscall interface. -/// -class Tru64 : public OperatingSystem -{ - - public: - - //@{ - /// Basic Tru64 types. - typedef uint64_t size_t; - typedef uint64_t off_t; - typedef uint16_t nlink_t; - typedef int32_t dev_t; - typedef uint32_t uid_t; - typedef uint32_t gid_t; - typedef uint32_t time_t; - typedef uint32_t mode_t; - typedef uint32_t ino_t; - typedef struct { int val[2]; } quad; - typedef quad fsid_t; - //@} - - - /// For statfs(). - struct F64_statfs { - int16_t f_type; - int16_t f_flags; - int32_t f_retired1; - int32_t f_retired2; - int32_t f_retired3; - int32_t f_retired4; - int32_t f_retired5; - int32_t f_retired6; - int32_t f_retired7; - fsid_t f_fsid; - int32_t f_spare[9]; - char f_retired8[90]; - char f_retired9[90]; - uint64_t dummy[10]; // was union mount_info mount_info; - uint64_t f_flags2; - int64_t f_spare2[14]; - int64_t f_fsize; - int64_t f_bsize; - int64_t f_blocks; - int64_t f_bfree; - int64_t f_bavail; - int64_t f_files; - int64_t f_ffree; - char f_mntonname[1024]; - char f_mntfromname[1024]; - }; - - /// For old Tru64 v4.x statfs() - struct pre_F64_statfs { - int16_t f_type; - int16_t f_flags; - int32_t f_fsize; - int32_t f_bsize; - int32_t f_blocks; - int32_t f_bfree; - int32_t f_bavail; - int32_t f_files; - int32_t f_ffree; - fsid_t f_fsid; - int32_t f_spare[9]; - char f_mntonname[90]; - char f_mntfromname[90]; - uint64_t dummy[10]; // was union mount_info mount_info; - }; - - /// For getdirentries(). - struct dirent - { - ino_t d_ino; //!< file number of entry - uint16_t d_reclen; //!< length of this record - uint16_t d_namlen; //!< length of string in d_name - char d_name[256]; //!< dummy name length - }; - - - /// Length of strings in struct utsname (plus 1 for null char). - static const int _SYS_NMLN = 32; - - /// Interface struct for uname(). - struct utsname { - char sysname[_SYS_NMLN]; //!< System name. - char nodename[_SYS_NMLN]; //!< Node name. - char release[_SYS_NMLN]; //!< OS release. - char version[_SYS_NMLN]; //!< OS version. - char machine[_SYS_NMLN]; //!< Machine type. - }; - - /// Limit struct for getrlimit/setrlimit. - struct rlimit { - uint64_t rlim_cur; //!< soft limit - uint64_t rlim_max; //!< hard limit - }; - - - /// For getsysinfo() GSI_CPU_INFO option. - struct cpu_info { - uint32_t current_cpu; //!< current_cpu - uint32_t cpus_in_box; //!< cpus_in_box - uint32_t cpu_type; //!< cpu_type - uint32_t ncpus; //!< ncpus - uint64_t cpus_present; //!< cpus_present - uint64_t cpus_running; //!< cpus_running - uint64_t cpu_binding; //!< cpu_binding - uint64_t cpu_ex_binding; //!< cpu_ex_binding - uint32_t mhz; //!< mhz - uint32_t unused[3]; //!< future expansion - }; - - /// For gettimeofday. - struct timeval { - uint32_t tv_sec; //!< seconds - uint32_t tv_usec; //!< microseconds - }; - - /// For getrusage(). - struct rusage { - struct timeval ru_utime; //!< user time used - struct timeval ru_stime; //!< system time used - uint64_t ru_maxrss; //!< ru_maxrss - uint64_t ru_ixrss; //!< integral shared memory size - uint64_t ru_idrss; //!< integral unshared data " - uint64_t ru_isrss; //!< integral unshared stack " - uint64_t ru_minflt; //!< page reclaims - total vmfaults - uint64_t ru_majflt; //!< page faults - uint64_t ru_nswap; //!< swaps - uint64_t ru_inblock; //!< block input operations - uint64_t ru_oublock; //!< block output operations - uint64_t ru_msgsnd; //!< messages sent - uint64_t ru_msgrcv; //!< messages received - uint64_t ru_nsignals; //!< signals received - uint64_t ru_nvcsw; //!< voluntary context switches - uint64_t ru_nivcsw; //!< involuntary " - }; - - /// For sigreturn(). - struct sigcontext { - int64_t sc_onstack; //!< sigstack state to restore - int64_t sc_mask; //!< signal mask to restore - int64_t sc_pc; //!< pc at time of signal - int64_t sc_ps; //!< psl to retore - int64_t sc_regs[32]; //!< processor regs 0 to 31 - int64_t sc_ownedfp; //!< fp has been used - int64_t sc_fpregs[32]; //!< fp regs 0 to 31 - uint64_t sc_fpcr; //!< floating point control reg - uint64_t sc_fp_control; //!< software fpcr - int64_t sc_reserved1; //!< reserved for kernel - uint32_t sc_kreserved1; //!< reserved for kernel - uint32_t sc_kreserved2; //!< reserved for kernel - size_t sc_ssize; //!< stack size - caddr_t sc_sbase; //!< stack start - uint64_t sc_traparg_a0; //!< a0 argument to trap on exc - uint64_t sc_traparg_a1; //!< a1 argument to trap on exc - uint64_t sc_traparg_a2; //!< a2 argument to trap on exc - uint64_t sc_fp_trap_pc; //!< imprecise pc - uint64_t sc_fp_trigger_sum; //!< Exception summary at trigg - uint64_t sc_fp_trigger_inst; //!< Instruction at trigger pc - }; - - - - /// For table(). - struct tbl_sysinfo { - uint64_t si_user; //!< User time - uint64_t si_nice; //!< Nice time - uint64_t si_sys; //!< System time - uint64_t si_idle; //!< Idle time - uint64_t si_hz; //!< hz - uint64_t si_phz; //!< phz - uint64_t si_boottime; //!< Boot time in seconds - uint64_t wait; //!< Wait time - uint32_t si_max_procs; //!< rpb->rpb_numprocs - uint32_t pad; //!< padding - }; - - - /// For stack_create. - struct vm_stack { - // was void * - Addr address; //!< address hint - size_t rsize; //!< red zone size - size_t ysize; //!< yellow zone size - size_t gsize; //!< green zone size - size_t swap; //!< amount of swap to reserve - size_t incr; //!< growth increment - uint64_t align; //!< address alignment - uint64_t flags; //!< MAP_FIXED etc. - // was struct memalloc_attr * - Addr attr; //!< allocation policy - uint64_t reserved; //!< reserved - }; - - /// Return values for nxm calls. - enum { - KERN_NOT_RECEIVER = 7, - KERN_NOT_IN_SET = 12 - }; - - /// For nxm_task_init. - static const int NXM_TASK_INIT_VP = 2; //!< initial thread is VP - - /// Task attribute structure. - struct nxm_task_attr { - int64_t nxm_callback; //!< nxm_callback - unsigned int nxm_version; //!< nxm_version - unsigned short nxm_uniq_offset; //!< nxm_uniq_offset - unsigned short flags; //!< flags - int nxm_quantum; //!< nxm_quantum - int pad1; //!< pad1 - int64_t pad2; //!< pad2 - }; - - /// Signal set. - typedef uint64_t sigset_t; - - /// Thread state shared between user & kernel. - struct ushared_state { - sigset_t sigmask; //!< thread signal mask - sigset_t sig; //!< thread pending mask - // struct nxm_pth_state * - Addr pth_id; //!< out-of-line state - int flags; //!< shared flags -#define US_SIGSTACK 0x1 // thread called sigaltstack -#define US_ONSTACK 0x2 // thread is running on altstack -#define US_PROFILE 0x4 // thread called profil -#define US_SYSCALL 0x8 // thread in syscall -#define US_TRAP 0x10 // thread has trapped -#define US_YELLOW 0x20 // thread has mellowed yellow -#define US_YZONE 0x40 // thread has zoned out -#define US_FP_OWNED 0x80 // thread used floating point - - int cancel_state; //!< thread's cancelation state -#define US_CANCEL 0x1 // cancel pending -#define US_NOCANCEL 0X2 // synch cancel disabled -#define US_SYS_NOCANCEL 0x4 // syscall cancel disabled -#define US_ASYNC_NOCANCEL 0x8 // asynch cancel disabled -#define US_CANCEL_BITS (US_NOCANCEL|US_SYS_NOCANCEL|US_ASYNC_NOCANCEL) -#define US_CANCEL_MASK (US_CANCEL|US_NOCANCEL|US_SYS_NOCANCEL| \ - US_ASYNC_NOCANCEL) - - // These are semi-shared. They are always visible to - // the kernel but are never context-switched by the library. - - int nxm_ssig; //!< scheduler's synchronous signals - int reserved1; //!< reserved1 - int64_t nxm_active; //!< scheduler active - int64_t reserved2; //!< reserved2 - }; - - struct nxm_sched_state { - struct ushared_state nxm_u; //!< state own by user thread - unsigned int nxm_bits; //!< scheduler state / slot - int nxm_quantum; //!< quantum count-down value - int nxm_set_quantum; //!< quantum reset value - int nxm_sysevent; //!< syscall state - // struct nxm_upcall * - Addr nxm_uc_ret; //!< stack ptr of null thread - // void * - Addr nxm_tid; //!< scheduler's thread id - int64_t nxm_va; //!< page fault address - // struct nxm_pth_state * - Addr nxm_pthid; //!< id of null thread - uint64_t nxm_bound_pcs_count; //!< bound PCS thread count - int64_t pad[2]; //!< pad - }; - - /// nxm_shared. - struct nxm_shared { - int64_t nxm_callback; //!< address of upcall routine - unsigned int nxm_version; //!< version number - unsigned short nxm_uniq_offset; //!< correction factor for TEB - unsigned short pad1; //!< pad1 - int64_t space[2]; //!< future growth - struct nxm_sched_state nxm_ss[1]; //!< array of shared areas - }; - - /// nxm_slot_state_t. - enum nxm_slot_state_t { - NXM_SLOT_AVAIL, - NXM_SLOT_BOUND, - NXM_SLOT_UNBOUND, - NXM_SLOT_EMPTY - }; - - /// nxm_config_info - struct nxm_config_info { - int nxm_nslots_per_rad; //!< max number of VP slots per RAD - int nxm_nrads; //!< max number of RADs - // nxm_slot_state_t * - Addr nxm_slot_state; //!< per-VP slot state - // struct nxm_shared * - Addr nxm_rad[1]; //!< per-RAD shared areas - }; - - /// For nxm_thread_create. - enum nxm_thread_type { - NXM_TYPE_SCS = 0, - NXM_TYPE_VP = 1, - NXM_TYPE_MANAGER = 2 - }; - - /// Thread attributes. - struct nxm_thread_attr { - int version; //!< version - int type; //!< type - int cancel_flags; //!< cancel_flags - int priority; //!< priority - int policy; //!< policy - int signal_type; //!< signal_type - // void * - Addr pthid; //!< pthid - sigset_t sigmask; //!< sigmask - /// Initial register values. - struct { - uint64_t pc; //!< pc - uint64_t sp; //!< sp - uint64_t a0; //!< a0 - } registers; - uint64_t pad2[2]; //!< pad2 - }; - - /// Helper function to convert a host statfs buffer to a target statfs - /// buffer. Also copies the target buffer out to the simulated - /// memory space. Used by statfs() and fstatfs(). - template - static void - copyOutStatfsBuf(SETranslatingPortProxy &mem, Addr addr, - global_statfs *host) - { - using namespace TheISA; - - TypedBufferArg tgt(addr); - -#if defined(__OpenBSD__) || defined(__APPLE__) || defined(__FreeBSD__) - tgt->f_type = 0; -#else - tgt->f_type = htog(host->f_type); -#endif - tgt->f_bsize = htog(host->f_bsize); - tgt->f_blocks = htog(host->f_blocks); - tgt->f_bfree = htog(host->f_bfree); - tgt->f_bavail = htog(host->f_bavail); - tgt->f_files = htog(host->f_files); - tgt->f_ffree = htog(host->f_ffree); - - // Is this as string normally? - memcpy(&tgt->f_fsid, &host->f_fsid, sizeof(host->f_fsid)); - - tgt.copyOut(mem); - } - - - /// The target system's hostname. - static const char *hostname; - - - /// Target getdirentries() handler. - static SyscallReturn - getdirentriesFunc(SyscallDesc *desc, int callnum, LiveProcess *process, - ThreadContext *tc) - { - using namespace TheISA; - -#if defined(__APPLE__) || defined(__CYGWIN__) - panic("getdirent not implemented on cygwin!"); -#else - int index = 0; - int fd = process->getSimFD(process->getSyscallArg(tc, index)); - Addr tgt_buf = process->getSyscallArg(tc, index); - int tgt_nbytes = process->getSyscallArg(tc, index); - Addr tgt_basep = process->getSyscallArg(tc, index); - - char * const host_buf = new char[tgt_nbytes]; - - // just pass basep through uninterpreted. - TypedBufferArg basep(tgt_basep); - basep.copyIn(tc->getMemProxy()); - long host_basep = (off_t)htog((int64_t)*basep); - int host_result = getdirentries(fd, host_buf, tgt_nbytes, &host_basep); - - // check for error - if (host_result < 0) { - delete [] host_buf; - return -errno; - } - - // no error: copy results back to target space - Addr tgt_buf_ptr = tgt_buf; - char *host_buf_ptr = host_buf; - char *host_buf_end = host_buf + host_result; - while (host_buf_ptr < host_buf_end) { - global_dirent *host_dp = (global_dirent *)host_buf_ptr; - int namelen = strlen(host_dp->d_name); - - // Actual size includes padded string rounded up for alignment. - // Subtract 256 for dummy char array in Tru64::dirent definition. - // Add 1 to namelen for terminating null char. - int tgt_bufsize = sizeof(Tru64::dirent) - 256 + roundUp(namelen+1, 8); - TypedBufferArg tgt_dp(tgt_buf_ptr, tgt_bufsize); - tgt_dp->d_ino = host_dp->d_ino; - tgt_dp->d_reclen = tgt_bufsize; - tgt_dp->d_namlen = namelen; - strcpy(tgt_dp->d_name, host_dp->d_name); - tgt_dp.copyOut(tc->getMemProxy()); - - tgt_buf_ptr += tgt_bufsize; - host_buf_ptr += host_dp->d_reclen; - } - - delete [] host_buf; - - *basep = htog((int64_t)host_basep); - basep.copyOut(tc->getMemProxy()); - - return tgt_buf_ptr - tgt_buf; -#endif - } - - /// Target sigreturn() handler. - static SyscallReturn - sigreturnFunc(SyscallDesc *desc, int callnum, LiveProcess *process, - ThreadContext *tc) - { - using namespace TheISA; - - int index = 0; - TypedBufferArg sc(process->getSyscallArg(tc, index)); - - sc.copyIn(tc->getMemProxy()); - - // Restore state from sigcontext structure. - // Note that we'll advance PC <- NPC before the end of the cycle, - // so we need to restore the desired PC into NPC. - // The current regs->pc will get clobbered. - PCState pc = tc->pcState(); - pc.npc(htog(sc->sc_pc)); - tc->pcState(pc); - - for (int i = 0; i < 31; ++i) { - tc->setIntReg(i, htog(sc->sc_regs[i])); - tc->setFloatRegBits(i, htog(sc->sc_fpregs[i])); - } - - tc->setMiscRegNoEffect(AlphaISA::MISCREG_FPCR, htog(sc->sc_fpcr)); - - return 0; - } - - - // - // Mach syscalls -- identified by negated syscall numbers - // - - /// Create a stack region for a thread. - static SyscallReturn - stack_createFunc(SyscallDesc *desc, int callnum, LiveProcess *process, - ThreadContext *tc) - { - using namespace TheISA; - - int index = 0; - TypedBufferArg argp(process->getSyscallArg(tc, index)); - - argp.copyIn(tc->getMemProxy()); - - int stack_size = - gtoh(argp->rsize) + gtoh(argp->ysize) + gtoh(argp->gsize); - - // if the user chose an address, just let them have it. Otherwise - // pick one for them. - Addr stack_base = gtoh(argp->address); - - if (stack_base == 0) { - stack_base = process->next_thread_stack_base; - process->next_thread_stack_base -= stack_size; - } - - Addr rounded_stack_base = roundDown(stack_base, PageBytes); - Addr rounded_stack_size = roundUp(stack_size, PageBytes); - - DPRINTF(SyscallVerbose, - "stack_create: allocating stack @ %#x size %#x " - "(rounded from %#x, %#x)\n", - rounded_stack_base, rounded_stack_size, - stack_base, stack_size); - - // map memory - process->allocateMem(rounded_stack_base, rounded_stack_size); - - argp->address = gtoh(rounded_stack_base); - argp.copyOut(tc->getMemProxy()); - - return 0; - } - - /// NXM library version stamp. - static - const int NXM_LIB_VERSION = 301003; - - /// This call sets up the interface between the user and kernel - /// schedulers by creating a shared-memory region. The shared memory - /// region has several structs, some global, some per-RAD, some per-VP. - static SyscallReturn - nxm_task_initFunc(SyscallDesc *desc, int callnum, LiveProcess *process, - ThreadContext *tc) - { - using namespace std; - using namespace TheISA; - - int index = 0; - TypedBufferArg - attrp(process->getSyscallArg(tc, index)); - TypedBufferArg configptr_ptr(process->getSyscallArg(tc, index)); - - attrp.copyIn(tc->getMemProxy()); - - if (gtoh(attrp->nxm_version) != NXM_LIB_VERSION) { - cerr << "nxm_task_init: thread library version mismatch! " - << "got " << attrp->nxm_version - << ", expected " << NXM_LIB_VERSION << endl; - abort(); - } - - if (gtoh(attrp->flags) != Tru64::NXM_TASK_INIT_VP) { - cerr << "nxm_task_init: bad flag value " << attrp->flags - << " (expected " << Tru64::NXM_TASK_INIT_VP << ")" << endl; - abort(); - } - - Addr base_addr = 0x12000; // was 0x3f0000000LL; - Addr cur_addr = base_addr; // next addresses to use - // first comes the config_info struct - Addr config_addr = cur_addr; - cur_addr += sizeof(Tru64::nxm_config_info); - // next comes the per-cpu state vector - Addr slot_state_addr = cur_addr; - int slot_state_size = - process->numCpus() * sizeof(Tru64::nxm_slot_state_t); - cur_addr += slot_state_size; - // now the per-RAD state struct (we only support one RAD) - cur_addr = 0x14000; // bump up addr for alignment - Addr rad_state_addr = cur_addr; - int rad_state_size = - (sizeof(Tru64::nxm_shared) - + (process->numCpus()-1) * sizeof(Tru64::nxm_sched_state)); - cur_addr += rad_state_size; - - // now initialize a config_info struct and copy it out to user space - TypedBufferArg config(config_addr); - - config->nxm_nslots_per_rad = htog(process->numCpus()); - config->nxm_nrads = htog(1); // only one RAD in our system! - config->nxm_slot_state = htog(slot_state_addr); - config->nxm_rad[0] = htog(rad_state_addr); - - // initialize the slot_state array and copy it out - TypedBufferArg slot_state(slot_state_addr, - slot_state_size); - for (int i = 0; i < process->numCpus(); ++i) { - // CPU 0 is bound to the calling process; all others are available - // XXX this code should have an endian conversion, but I don't think - // it works anyway - slot_state[i] = - (i == 0) ? Tru64::NXM_SLOT_BOUND : Tru64::NXM_SLOT_AVAIL; - } - - // same for the per-RAD "shared" struct. Note that we need to - // allocate extra bytes for the per-VP array which is embedded at - // the end. - TypedBufferArg rad_state(rad_state_addr, - rad_state_size); - - rad_state->nxm_callback = attrp->nxm_callback; - rad_state->nxm_version = attrp->nxm_version; - rad_state->nxm_uniq_offset = attrp->nxm_uniq_offset; - for (int i = 0; i < process->numCpus(); ++i) { - Tru64::nxm_sched_state *ssp = &rad_state->nxm_ss[i]; - ssp->nxm_u.sigmask = htog(0); - ssp->nxm_u.sig = htog(0); - ssp->nxm_u.flags = htog(0); - ssp->nxm_u.cancel_state = htog(0); - ssp->nxm_u.nxm_ssig = 0; - ssp->nxm_bits = htog(0); - ssp->nxm_quantum = attrp->nxm_quantum; - ssp->nxm_set_quantum = attrp->nxm_quantum; - ssp->nxm_sysevent = htog(0); - - if (i == 0) { - uint64_t uniq = tc->readMiscRegNoEffect(AlphaISA::MISCREG_UNIQ); - ssp->nxm_u.pth_id = htog(uniq + gtoh(attrp->nxm_uniq_offset)); - ssp->nxm_u.nxm_active = htog(uniq | 1); - } - else { - ssp->nxm_u.pth_id = htog(0); - ssp->nxm_u.nxm_active = htog(0); - } - } - - // - // copy pointer to shared config area out to user - // - *configptr_ptr = htog(config_addr); - - // Register this as a valid address range with the process - base_addr = roundDown(base_addr, PageBytes); - int size = cur_addr - base_addr; - process->allocateMem(base_addr, roundUp(size, PageBytes)); - - config.copyOut(tc->getMemProxy()); - slot_state.copyOut(tc->getMemProxy()); - rad_state.copyOut(tc->getMemProxy()); - configptr_ptr.copyOut(tc->getMemProxy()); - - return 0; - } - - /// Initialize thread context. - static void - init_thread_context(LiveProcess *process, ThreadContext *tc, - Tru64::nxm_thread_attr *attrp, uint64_t uniq_val) - { - using namespace TheISA; - - tc->clearArchRegs(); - - process->setSyscallArg(tc, 0, gtoh(attrp->registers.a0)); - tc->setIntReg(27/*t12*/, gtoh(attrp->registers.pc)); - tc->setIntReg(TheISA::StackPointerReg, gtoh(attrp->registers.sp)); - tc->setMiscRegNoEffect(AlphaISA::MISCREG_UNIQ, uniq_val); - - tc->pcState(gtoh(attrp->registers.pc)); - - tc->activate(); - } - - /// Create thread. - static SyscallReturn - nxm_thread_createFunc(SyscallDesc *desc, int callnum, LiveProcess *process, - ThreadContext *tc) - { - using namespace std; - using namespace TheISA; - - int index = 0; - TypedBufferArg - attrp(process->getSyscallArg(tc, index)); - TypedBufferArg kidp(process->getSyscallArg(tc, index)); - int thread_index = process->getSyscallArg(tc, index); - - // get attribute args - attrp.copyIn(tc->getMemProxy()); - - if (gtoh(attrp->version) != NXM_LIB_VERSION) { - cerr << "nxm_thread_create: thread library version mismatch! " - << "got " << attrp->version - << ", expected " << NXM_LIB_VERSION << endl; - abort(); - } - - if (thread_index < 0 || thread_index > process->numCpus()) { - cerr << "nxm_thread_create: bad thread index " << thread_index - << endl; - abort(); - } - - // On a real machine, the per-RAD shared structure is in - // shared memory, so both the user and kernel can get at it. - // We don't have that luxury, so we just copy it in and then - // back out again. - int rad_state_size = - (sizeof(Tru64::nxm_shared) + - (process->numCpus()-1) * sizeof(Tru64::nxm_sched_state)); - - TypedBufferArg rad_state(0x14000, - rad_state_size); - rad_state.copyIn(tc->getMemProxy()); - - uint64_t uniq_val = gtoh(attrp->pthid) - gtoh(rad_state->nxm_uniq_offset); - - if (gtoh(attrp->type) == Tru64::NXM_TYPE_MANAGER) { - // DEC pthreads seems to always create one of these (in - // addition to N application threads), but we don't use it, - // so don't bother creating it. - - // This is supposed to be a port number. Make something up. - *kidp = htog(99); - kidp.copyOut(tc->getMemProxy()); - - return 0; - } else if (gtoh(attrp->type) == Tru64::NXM_TYPE_VP) { - // A real "virtual processor" kernel thread. Need to fork - // this thread on another CPU. - Tru64::nxm_sched_state *ssp = &rad_state->nxm_ss[thread_index]; - - if (gtoh(ssp->nxm_u.nxm_active) != 0) - return (int) Tru64::KERN_NOT_RECEIVER; - - ssp->nxm_u.pth_id = attrp->pthid; - ssp->nxm_u.nxm_active = htog(uniq_val | 1); - - rad_state.copyOut(tc->getMemProxy()); - - Addr slot_state_addr = 0x12000 + sizeof(Tru64::nxm_config_info); - int slot_state_size = - process->numCpus() * sizeof(Tru64::nxm_slot_state_t); - - TypedBufferArg - slot_state(slot_state_addr, - slot_state_size); - - slot_state.copyIn(tc->getMemProxy()); - - if (slot_state[thread_index] != Tru64::NXM_SLOT_AVAIL) { - cerr << "nxm_thread_createFunc: requested VP slot " - << thread_index << " not available!" << endl; - fatal(""); - } - - // XXX This should have an endian conversion but I think this code - // doesn't work anyway - slot_state[thread_index] = Tru64::NXM_SLOT_BOUND; - - slot_state.copyOut(tc->getMemProxy()); - - // Find a free simulator thread context. - ThreadContext *tc = process->findFreeContext(); - if (tc) { - // inactive context... grab it - init_thread_context(process, tc, attrp, uniq_val); - - // This is supposed to be a port number, but we'll try - // and get away with just sticking the thread index - // here. - *kidp = htog(thread_index); - kidp.copyOut(tc->getMemProxy()); - - return 0; - } - - // fell out of loop... no available inactive context - cerr << "nxm_thread_create: no idle contexts available." << endl; - abort(); - } else { - cerr << "nxm_thread_create: can't handle thread type " - << attrp->type << endl; - abort(); - } - - return 0; - } - - /// Thread idle call (like yield()). - static SyscallReturn - nxm_idleFunc(SyscallDesc *desc, int callnum, LiveProcess *process, - ThreadContext *tc) - { - return 0; - } - - /// Block thread. - static SyscallReturn - nxm_thread_blockFunc(SyscallDesc *desc, int callnum, LiveProcess *process, - ThreadContext *tc) - { - using namespace std; - - int index = 0; - uint64_t tid = process->getSyscallArg(tc, index); - uint64_t secs = process->getSyscallArg(tc, index); - uint64_t flags = process->getSyscallArg(tc, index); - uint64_t action = process->getSyscallArg(tc, index); - uint64_t usecs = process->getSyscallArg(tc, index); - - cout << tc->getCpuPtr()->name() << ": nxm_thread_block " << tid << " " - << secs << " " << flags << " " << action << " " << usecs << endl; - - return 0; - } - - /// block. - static SyscallReturn - nxm_blockFunc(SyscallDesc *desc, int callnum, LiveProcess *process, - ThreadContext *tc) - { - using namespace std; - - int index = 0; - Addr uaddr = process->getSyscallArg(tc, index); - uint64_t val = process->getSyscallArg(tc, index); - uint64_t secs = process->getSyscallArg(tc, index); - uint64_t usecs = process->getSyscallArg(tc, index); - uint64_t flags = process->getSyscallArg(tc, index); - - BaseCPU *cpu = tc->getCpuPtr(); - - cout << cpu->name() << ": nxm_block " - << hex << uaddr << dec << " " << val - << " " << secs << " " << usecs - << " " << flags << endl; - - return 0; - } - - /// Unblock thread. - static SyscallReturn - nxm_unblockFunc(SyscallDesc *desc, int callnum, LiveProcess *process, - ThreadContext *tc) - { - using namespace std; - - int index = 0; - Addr uaddr = process->getSyscallArg(tc, index); - - cout << tc->getCpuPtr()->name() << ": nxm_unblock " - << hex << uaddr << dec << endl; - - return 0; - } - - /// Switch thread priority. - static SyscallReturn - swtch_priFunc(SyscallDesc *desc, int callnum, LiveProcess *process, - ThreadContext *tc) - { - // Attempts to switch to another runnable thread (if there is - // one). Returns false if there are no other threads to run - // (i.e., the thread can reasonably spin-wait) or true if there - // are other threads. - // - // Since we assume at most one "kernel" thread per CPU, it's - // always safe to return false here. - return 0; //false; - } - - - /// Activate thread context waiting on a channel. Just activate one - /// by default. - static int - activate_waiting_context(Addr uaddr, LiveProcess *process, - bool activate_all = false) - { - using namespace std; - - int num_activated = 0; - - list::iterator i = process->waitList.begin(); - list::iterator end = process->waitList.end(); - - while (i != end && (num_activated == 0 || activate_all)) { - if (i->waitChan == uaddr) { - // found waiting process: make it active - ThreadContext *newCtx = i->waitingContext; - assert(newCtx->status() == ThreadContext::Suspended); - newCtx->activate(); - - // get rid of this record - i = process->waitList.erase(i); - - ++num_activated; - } else { - ++i; - } - } - - return num_activated; - } - - /// M5 hacked-up lock acquire. - static void - m5_lock_mutex(Addr uaddr, LiveProcess *process, ThreadContext *tc) - { - using namespace TheISA; - - TypedBufferArg lockp(uaddr); - - lockp.copyIn(tc->getMemProxy()); - - if (gtoh(*lockp) == 0) { - // lock is free: grab it - *lockp = htog(1); - lockp.copyOut(tc->getMemProxy()); - } else { - // lock is busy: disable until free - process->waitList.push_back(Process::WaitRec(uaddr, tc)); - tc->suspend(); - } - } - - /// M5 unlock call. - static void - m5_unlock_mutex(Addr uaddr, LiveProcess *process, ThreadContext *tc) - { - TypedBufferArg lockp(uaddr); - - lockp.copyIn(tc->getMemProxy()); - assert(*lockp != 0); - - // Check for a process waiting on the lock. - int num_waiting = activate_waiting_context(uaddr, process); - - // clear lock field if no waiting context is taking over the lock - if (num_waiting == 0) { - *lockp = 0; - lockp.copyOut(tc->getMemProxy()); - } - } - - /// Lock acquire syscall handler. - static SyscallReturn - m5_mutex_lockFunc(SyscallDesc *desc, int callnum, LiveProcess *process, - ThreadContext *tc) - { - int index = 0; - Addr uaddr = process->getSyscallArg(tc, index); - - m5_lock_mutex(uaddr, process, tc); - - // Return 0 since we will always return to the user with the lock - // acquired. We will just keep the context inactive until that is - // true. - return 0; - } - - /// Try lock (non-blocking). - static SyscallReturn - m5_mutex_trylockFunc(SyscallDesc *desc, int callnum, LiveProcess *process, - ThreadContext *tc) - { - using namespace TheISA; - - int index = 0; - Addr uaddr = process->getSyscallArg(tc, index); - TypedBufferArg lockp(uaddr); - - lockp.copyIn(tc->getMemProxy()); - - if (gtoh(*lockp) == 0) { - // lock is free: grab it - *lockp = htog(1); - lockp.copyOut(tc->getMemProxy()); - return 0; - } else { - return 1; - } - } - - /// Unlock syscall handler. - static SyscallReturn - m5_mutex_unlockFunc(SyscallDesc *desc, int callnum, LiveProcess *process, - ThreadContext *tc) - { - int index = 0; - Addr uaddr = process->getSyscallArg(tc, index); - - m5_unlock_mutex(uaddr, process, tc); - - return 0; - } - - /// Signal ocndition. - static SyscallReturn - m5_cond_signalFunc(SyscallDesc *desc, int callnum, LiveProcess *process, - ThreadContext *tc) - { - int index = 0; - Addr cond_addr = process->getSyscallArg(tc, index); - - // Wake up one process waiting on the condition variable. - activate_waiting_context(cond_addr, process); - - return 0; - } - - /// Wake up all processes waiting on the condition variable. - static SyscallReturn - m5_cond_broadcastFunc(SyscallDesc *desc, int callnum, LiveProcess *process, - ThreadContext *tc) - { - int index = 0; - Addr cond_addr = process->getSyscallArg(tc, index); - - activate_waiting_context(cond_addr, process, true); - - return 0; - } - - /// Wait on a condition. - static SyscallReturn - m5_cond_waitFunc(SyscallDesc *desc, int callnum, LiveProcess *process, - ThreadContext *tc) - { - using namespace TheISA; - - int index = 0; - Addr cond_addr = process->getSyscallArg(tc, index); - Addr lock_addr = process->getSyscallArg(tc, index); - TypedBufferArg condp(cond_addr); - TypedBufferArg lockp(lock_addr); - - // user is supposed to acquire lock before entering - lockp.copyIn(tc->getMemProxy()); - assert(gtoh(*lockp) != 0); - - m5_unlock_mutex(lock_addr, process, tc); - - process->waitList.push_back(Process::WaitRec(cond_addr, tc)); - tc->suspend(); - - return 0; - } - - /// Thread exit. - static SyscallReturn - m5_thread_exitFunc(SyscallDesc *desc, int callnum, LiveProcess *process, - ThreadContext *tc) - { - assert(tc->status() == ThreadContext::Active); - tc->halt(); - - return 0; - } - - /// Indirect syscall invocation (call #0). - static SyscallReturn - indirectSyscallFunc(SyscallDesc *desc, int callnum, LiveProcess *process, - ThreadContext *tc) - { - int index = 0; - int new_callnum = process->getSyscallArg(tc, index); - - for (int i = 0; i < 5; ++i) - process->setSyscallArg(tc, i, process->getSyscallArg(tc, index)); - - - SyscallDesc *new_desc = process->getDesc(new_callnum); - if (desc == NULL) - fatal("Syscall %d out of range", callnum); - - new_desc->doSyscall(new_callnum, process, tc); - - return 0; - } - -}; // class Tru64 - -class Tru64_F64 : public Tru64 -{ - public: - - /// Stat buffer. Note that Tru64 v5.0+ use a new "F64" stat - /// structure, and a new set of syscall numbers for stat calls. - /// On some hosts (notably Linux) define st_atime, st_mtime, and - /// st_ctime as macros, so we append an X to get around this. - struct F64_stat { - dev_t st_dev; //!< st_dev - int32_t st_retired1; //!< st_retired1 - mode_t st_mode; //!< st_mode - nlink_t st_nlink; //!< st_nlink - uint16_t st_nlink_reserved; //!< st_nlink_reserved - uid_t st_uid; //!< st_uid - gid_t st_gid; //!< st_gid - dev_t st_rdev; //!< st_rdev - dev_t st_ldev; //!< st_ldev - off_t st_size; //!< st_size - time_t st_retired2; //!< st_retired2 - int32_t st_uatime; //!< st_uatime - time_t st_retired3; //!< st_retired3 - int32_t st_umtime; //!< st_umtime - time_t st_retired4; //!< st_retired4 - int32_t st_uctime; //!< st_uctime - int32_t st_retired5; //!< st_retired5 - int32_t st_retired6; //!< st_retired6 - uint32_t st_flags; //!< st_flags - uint32_t st_gen; //!< st_gen - uint64_t st_spare[4]; //!< st_spare[4] - ino_t st_ino; //!< st_ino - int32_t st_ino_reserved; //!< st_ino_reserved - time_t st_atimeX; //!< st_atime - int32_t st_atime_reserved; //!< st_atime_reserved - time_t st_mtimeX; //!< st_mtime - int32_t st_mtime_reserved; //!< st_mtime_reserved - time_t st_ctimeX; //!< st_ctime - int32_t st_ctime_reserved; //!< st_ctime_reserved - uint64_t st_blksize; //!< st_blksize - uint64_t st_blocks; //!< st_blocks - }; - - typedef F64_stat tgt_stat; -/* - static void copyOutStatBuf(SETranslatingPortProxy &mem, Addr addr, - global_stat *host) - { - Tru64::copyOutStatBuf(mem, addr, host); - }*/ - - static void copyOutStatfsBuf(SETranslatingPortProxy &mem, Addr addr, - global_statfs *host) - { - Tru64::copyOutStatfsBuf(mem, addr, host); - } -}; - -class Tru64_PreF64 : public Tru64 -{ - public: - - /// Old Tru64 v4.x stat struct. - /// Tru64 maintains backwards compatibility with v4.x by - /// implementing another set of stat functions using the old - /// structure definition and binding them to the old syscall - /// numbers. - - struct pre_F64_stat { - dev_t st_dev; - ino_t st_ino; - mode_t st_mode; - nlink_t st_nlink; - uid_t st_uid __attribute__ ((aligned(sizeof(uid_t)))); - gid_t st_gid; - dev_t st_rdev; - off_t st_size __attribute__ ((aligned(sizeof(off_t)))); - time_t st_atimeX; - int32_t st_uatime; - time_t st_mtimeX; - int32_t st_umtime; - time_t st_ctimeX; - int32_t st_uctime; - uint32_t st_blksize; - int32_t st_blocks; - uint32_t st_flags; - uint32_t st_gen; - }; - - typedef pre_F64_stat tgt_stat; -/* - static void copyOutStatBuf(SETranslatingPortProxy &mem, Addr addr, - global_stat *host) - { - Tru64::copyOutStatBuf(mem, addr, host); - }*/ - - static void copyOutStatfsBuf(SETranslatingPortProxy &mem, Addr addr, - global_statfs *host) - { - Tru64::copyOutStatfsBuf(mem, addr, host); - } -}; - -#endif // __TRU64_HH__ diff -r 9c673b990d5d -r e1835e5846b9 src/kern/tru64/tru64_events.hh --- a/src/kern/tru64/tru64_events.hh Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,86 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Nathan Binkert - * Lisa Hsu - */ - -#ifndef __TRU64_EVENTS_HH__ -#define __TRU64_EVENTS_HH__ - -#include - -#include "cpu/pc_event.hh" -#include "kern/system_events.hh" - -class ThreadContext; - -class BadAddrEvent : public SkipFuncEvent -{ - public: - BadAddrEvent(PCEventQueue *q, const std::string &desc, Addr addr) - : SkipFuncEvent(q, desc, addr) {} - virtual void process(ThreadContext *tc); -}; - -class PrintfEvent : public PCEvent -{ - public: - PrintfEvent(PCEventQueue *q, const std::string &desc, Addr addr) - : PCEvent(q, desc, addr) {} - virtual void process(ThreadContext *tc); -}; - -class DebugPrintfEvent : public PCEvent -{ - private: - bool raw; - - public: - DebugPrintfEvent(PCEventQueue *q, const std::string &desc, Addr addr, - bool r = false) - : PCEvent(q, desc, addr), raw(r) {} - virtual void process(ThreadContext *tc); -}; - -class DebugPrintfrEvent : public DebugPrintfEvent -{ - public: - DebugPrintfrEvent(PCEventQueue *q, const std::string &desc, Addr addr) - : DebugPrintfEvent(q, desc, addr, true) - {} -}; - -class DumpMbufEvent : public PCEvent -{ - public: - DumpMbufEvent(PCEventQueue *q, const std::string &desc, Addr addr) - : PCEvent(q, desc, addr) {} - virtual void process(ThreadContext *tc); -}; - -#endif // __TRU64_EVENTS_HH__ diff -r 9c673b990d5d -r e1835e5846b9 src/kern/tru64/tru64_events.cc --- a/src/kern/tru64/tru64_events.cc Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,114 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Nathan Binkert - * Lisa Hsu - */ - -#include "arch/alpha/ev5.hh" -#include "arch/isa_traits.hh" -#include "config/the_isa.hh" -#include "cpu/base.hh" -#include "cpu/thread_context.hh" -#include "debug/BADADDR.hh" -#include "debug/DebugPrintf.hh" -#include "debug/Printf.hh" -#include "kern/tru64/dump_mbuf.hh" -#include "kern/tru64/printf.hh" -#include "kern/tru64/tru64_events.hh" -#include "kern/system_events.hh" -#include "sim/arguments.hh" -#include "sim/system.hh" - -using namespace TheISA; - -//void SkipFuncEvent::process(ExecContext *tc); - -void -BadAddrEvent::process(ThreadContext *tc) -{ - // The following gross hack is the equivalent function to the - // annotation for vmunix::badaddr in: - // simos/simulation/apps/tcl/osf/tlaser.tcl - - uint64_t a0 = tc->readIntReg(16); - - bool found = false; - - MasterPort &dataPort = tc->getCpuPtr()->getDataPort(); - - // get the address ranges of the connected slave port - AddrRangeList resp = dataPort.getAddrRanges(); - for (const auto &iter : resp) { - if (iter.contains(K0Seg2Phys(a0) & PAddrImplMask)) - found = true; - } - - if (!IsK0Seg(a0) || found ) { - - DPRINTF(BADADDR, "badaddr arg=%#x bad\n", a0); - tc->setIntReg(ReturnValueReg, 0x1); - SkipFuncEvent::process(tc); - } else { - DPRINTF(BADADDR, "badaddr arg=%#x good\n", a0); - } -} - -void -PrintfEvent::process(ThreadContext *tc) -{ - if (DTRACE(Printf)) { - StringWrap name(tc->getSystemPtr()->name()); - DPRINTFN(""); - - Arguments args(tc); - tru64::Printf(args); - } -} - -void -DebugPrintfEvent::process(ThreadContext *tc) -{ - if (DTRACE(DebugPrintf)) { - if (!raw) { - StringWrap name(tc->getSystemPtr()->name()); - DPRINTFN(""); - } - - Arguments args(tc); - tru64::Printf(args); - } -} - -void -DumpMbufEvent::process(ThreadContext *tc) -{ - if (DTRACE(DebugPrintf)) { - Arguments args(tc); - tru64::DumpMbuf(args); - } -} diff -r 9c673b990d5d -r e1835e5846b9 src/kern/tru64/tru64_syscalls.hh --- a/src/kern/tru64/tru64_syscalls.hh Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,361 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Nathan Binkert - */ - -#ifndef __KERN_TRU64_TRU64_SYSCALLS_HH__ -#define __KERN_TRU64_TRU64_SYSCALLS_HH__ - -#include "kern/tru64/tru64.hh" - -template -class SystemCalls; - -template <> -class SystemCalls -{ - public: - enum { - syscall = 0, - exit = 1, - fork = 2, - read = 3, - write = 4, - old_open = 5, - close = 6, - wait4 = 7, - old_creat = 8, - link = 9, - unlink = 10, - execv = 11, - chdir = 12, - fchdir = 13, - mknod = 14, - chmod = 15, - chown = 16, - obreak = 17, - pre_F64_getfsstat = 18, - lseek = 19, - getpid = 20, - mount = 21, - unmount = 22, - setuid = 23, - getuid = 24, - exec_with_loader = 25, - ptrace = 26, - recvmsg = 27, - sendmsg = 28, - recvfrom = 29, - accept = 30, - getpeername = 31, - getsockname = 32, - access = 33, - chflags = 34, - fchflags = 35, - sync = 36, - kill = 37, - old_stat = 38, - setpgid = 39, - old_lstat = 40, - dup = 41, - pipe = 42, - set_program_attributes = 43, - profil = 44, - open = 45, - obsolete_osigaction = 46, - getgid = 47, - sigprocmask = 48, - getlogin = 49, - setlogin = 50, - acct = 51, - sigpending = 52, - classcntl = 53, - ioctl = 54, - reboot = 55, - revoke = 56, - symlink = 57, - readlink = 58, - execve = 59, - umask = 60, - chroot = 61, - old_fstat = 62, - getpgrp = 63, - getpagesize = 64, - mremap = 65, - vfork = 66, - pre_F64_stat = 67, - pre_F64_lstat = 68, - sbrk = 69, - sstk = 70, - mmap = 71, - ovadvise = 72, - munmap = 73, - mprotect = 74, - madvise = 75, - old_vhangup = 76, - kmodcall = 77, - mincore = 78, - getgroups = 79, - setgroups = 80, - old_getpgrp = 81, - setpgrp = 82, - setitimer = 83, - old_wait = 84, - table = 85, - getitimer = 86, - gethostname = 87, - sethostname = 88, - getdtablesize = 89, - dup2 = 90, - pre_F64_fstat = 91, - fcntl = 92, - select = 93, - poll = 94, - fsync = 95, - setpriority = 96, - socket = 97, - connect = 98, - old_accept = 99, - getpriority = 100, - old_send = 101, - old_recv = 102, - sigreturn = 103, - bind = 104, - setsockopt = 105, - listen = 106, - plock = 107, - old_sigvec = 108, - old_sigblock = 109, - old_sigsetmask = 110, - sigsuspend = 111, - sigstack = 112, - old_recvmsg = 113, - old_sendmsg = 114, - obsolete_vtrcae = 115, - gettimeofday = 116, - getrusage = 117, - getsockopt = 118, - numa_syscalls = 119, - readv = 120, - writev = 121, - settimeofday = 122, - fchown = 123, - fchmod = 124, - old_recvfrom = 125, - setreuid = 126, - setregid = 127, - rename = 128, - truncate = 129, - ftruncate = 130, - flock = 131, - setgid = 132, - sendto = 133, - shutdown = 134, - socketpair = 135, - mkdir = 136, - rmdir = 137, - utimes = 138, - obsolete_42_sigreturn = 139, - adjtime = 140, - old_getpeername = 141, - gethostid = 142, - sethostid = 143, - getrlimit = 144, - setrlimit = 145, - old_killpg = 146, - setsid = 147, - quotactl = 148, - oldquota = 149, - old_getsockname = 150, - pread = 151, - pwrite = 152, - pid_block = 153, - pid_unblock = 154, - signal_urti = 155, - sigaction = 156, - sigwaitprim = 157, - nfssvc = 158, - getdirentries = 159, - pre_F64_statfs = 160, - pre_F64_fstatfs = 161, - async_daemon = 163, - getfh = 164, - getdomainname = 165, - setdomainname = 166, - exportfs = 169, - alt_plock = 181, - getmnt = 184, - alt_sigpending = 187, - alt_setsid = 188, - swapon = 199, - msgctl = 200, - msgget = 201, - msgrcv = 202, - msgsnd = 203, - semctl = 204, - semget = 205, - semop = 206, - uname = 207, - lchown = 208, - shmat = 209, - shmctl = 210, - shmdt = 211, - shmget = 212, - mvalid = 213, - getaddressconf = 214, - msleep = 215, - mwakeup = 216, - msync = 217, - signal = 218, - utc_gettime = 219, - utc_adjtime = 220, - security = 222, - kloadcall = 223, - stat = 224, - lstat = 225, - fstat = 226, - statfs = 227, - fstatfs = 228, - getfsstat = 229, - gettimeofday64 = 230, - settimeofday64 = 231, - getpgid = 233, - getsid = 234, - sigaltstack = 235, - waitid = 236, - priocntlset = 237, - sigsendset = 238, - set_speculative = 239, - msfs_syscall = 240, - sysinfo = 241, - uadmin = 242, - fuser = 243, - proplist_syscall = 244, - ntp_adjtime = 245, - ntp_gettime = 246, - pathconf = 247, - fpathconf = 248, - sync2 = 249, - uswitch = 250, - usleep_thread = 251, - audcntl = 252, - audgen = 253, - sysfs = 254, - subsys_info = 255, - getsysinfo = 256, - setsysinfo = 257, - afs_syscall = 258, - swapctl = 259, - memcntl = 260, - fdatasync = 261, - oflock = 262, - _F64_readv = 263, - _F64_writev = 264, - cdslxlate = 265, - sendfile = 266, - StandardNumber - }; - - enum { - task_self = 10, - thread_reply = 11, - task_notify = 12, - thread_self = 13, - msg_send_trap = 20, - msg_receive_trap = 21, - msg_rpc_trap = 22, - nxm_block = 24, - nxm_unblock = 25, - nxm_thread_destroy = 29, - lw_wire = 30, - lw_unwire = 31, - nxm_thread_create = 32, - nxm_task_init = 33, - nxm_idle = 35, - nxm_wakeup_idle = 36, - nxm_set_pthid = 37, - nxm_thread_kill = 38, - nxm_thread_block = 39, - nxm_thread_wakeup = 40, - init_process = 41, - nxm_get_binding = 42, - map_fd = 43, - nxm_resched = 44, - nxm_set_cancel = 45, - nxm_set_binding = 46, - stack_create = 47, - nxm_get_state = 48, - nxm_thread_suspend = 49, - nxm_thread_resume = 50, - nxm_signal_check = 51, - htg_unix_syscall = 52, - host_self = 55, - host_priv_self = 56, - swtch_pri = 59, - swtch = 60, - thread_switch = 61, - semop_fast = 62, - nxm_pshared_init = 63, - nxm_pshared_block = 64, - nxm_pshared_unblock = 65, - nxm_pshared_destroy = 66, - nxm_swtch_pri = 67, - lw_syscall = 68, - mach_sctimes_0 = 70, - mach_sctimes_1 = 71, - mach_sctimes_2 = 72, - mach_sctimes_3 = 73, - mach_sctimes_4 = 74, - mach_sctimes_5 = 75, - mach_sctimes_6 = 76, - mach_sctimes_7 = 77, - mach_sctimes_8 = 78, - mach_sctimes_9 = 79, - mach_sctimes_10 = 80, - mach_sctimes_11 = 81, - mach_sctimes_port_alloc_dealloc = 82, - MachNumber - }; - - static const int Number = StandardNumber + MachNumber; - - static const char *name(int num); - - static bool validSyscallNumber(int num) { - return -MachNumber < num && num < StandardNumber; - } - - static int convert(int syscall_num) { - if (!validSyscallNumber(syscall_num)) - return -1; - - return syscall_num < 0 ? StandardNumber - syscall_num : syscall_num; - } -}; - -#endif // __KERN_TRU64_TRU64_SYSCALLS_HH__ diff -r 9c673b990d5d -r e1835e5846b9 src/kern/tru64/tru64_syscalls.cc --- a/src/kern/tru64/tru64_syscalls.cc Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,440 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Nathan Binkert - */ - -#include "kern/tru64/tru64_syscalls.hh" - -namespace { - const char * - standard_strings[SystemCalls::StandardNumber] = { - "syscall", // 0 - "exit", // 1 - "fork", // 2 - "read", // 3 - "write", // 4 - "old_open", // 5 - "close", // 6 - "wait4", // 7 - "old_creat", // 8 - "link", // 9 - - "unlink", // 10 - "execv", // 11 - "chdir", // 12 - "fchdir", // 13 - "mknod", // 14 - "chmod", // 15 - "chown", // 16 - "obreak", // 17 - "pre_F64_getfsstat", // 18 - "lseek", // 19 - - "getpid", // 20 - "mount", // 21 - "unmount", // 22 - "setuid", // 23 - "getuid", // 24 - "exec_with_loader", // 25 - "ptrace", // 26 - "recvmsg", // 27 - "sendmsg", // 28 - "recvfrom", // 29 - - "accept", // 30 - "getpeername", // 31 - "getsockname", // 32 - "access", // 33 - "chflags", // 34 - "fchflags", // 35 - "sync", // 36 - "kill", // 37 - "old_stat", // 38 - "setpgid", // 39 - - "old_lstat", // 40 - "dup", // 41 - "pipe", // 42 - "set_program_attributes", // 43 - "profil", // 44 - "open", // 45 - "obsolete_osigaction", // 46 - "getgid", // 47 - "sigprocmask", // 48 - "getlogin", // 49 - - "setlogin", // 50 - "acct", // 51 - "sigpending", // 52 - "classcntl", // 53 - "ioctl", // 54 - "reboot", // 55 - "revoke", // 56 - "symlink", // 57 - "readlink", // 58 - "execve", // 59 - - "umask", // 60 - "chroot", // 61 - "old_fstat", // 62 - "getpgrp", // 63 - "getpagesize", // 64 - "mremap", // 65 - "vfork", // 66 - "pre_F64_stat", // 67 - "pre_F64_lstat", // 68 - "sbrk", // 69 - - "sstk", // 70 - "mmap", // 71 - "ovadvise", // 72 - "munmap", // 73 - "mprotect", // 74 - "madvise", // 75 - "old_vhangup", // 76 - "kmodcall", // 77 - "mincore", // 78 - "getgroups", // 79 - - "setgroups", // 80 - "old_getpgrp", // 81 - "setpgrp", // 82 - "setitimer", // 83 - "old_wait", // 84 - "table", // 85 - "getitimer", // 86 - "gethostname", // 87 - "sethostname", // 88 - "getdtablesize", // 89 - - "dup2", // 90 - "pre_F64_fstat", // 91 - "fcntl", // 92 - "select", // 93 - "poll", // 94 - "fsync", // 95 - "setpriority", // 96 - "socket", // 97 - "connect", // 98 - "old_accept", // 99 - - "getpriority", // 100 - "old_send", // 101 - "old_recv", // 102 - "sigreturn", // 103 - "bind", // 104 - "setsockopt", // 105 - "listen", // 106 - "plock", // 107 - "old_sigvec", // 108 - "old_sigblock", // 109 - - "old_sigsetmask", // 110 - "sigsuspend", // 111 - "sigstack", // 112 - "old_recvmsg", // 113 - "old_sendmsg", // 114 - "obsolete_vtrcae", // 115 - "gettimeofday", // 116 - "getrusage", // 117 - "getsockopt", // 118 - "numa_syscalls", // 119 - - "readv", // 120 - "writev", // 121 - "settimeofday", // 122 - "fchown", // 123 - "fchmod", // 124 - "old_recvfrom", // 125 - "setreuid", // 126 - "setregid", // 127 - "rename", // 128 - "truncate", // 129 - - "ftruncate", // 130 - "flock", // 131 - "setgid", // 132 - "sendto", // 133 - "shutdown", // 134 - "socketpair", // 135 - "mkdir", // 136 - "rmdir", // 137 - "utimes", // 138 - "obsolete_42_sigreturn", // 139 - - "adjtime", // 140 - "old_getpeername", // 141 - "gethostid", // 142 - "sethostid", // 143 - "getrlimit", // 144 - "setrlimit", // 145 - "old_killpg", // 146 - "setsid", // 147 - "quotactl", // 148 - "oldquota", // 149 - - "old_getsockname", // 150 - "pread", // 151 - "pwrite", // 152 - "pid_block", // 153 - "pid_unblock", // 154 - "signal_urti", // 155 - "sigaction", // 156 - "sigwaitprim", // 157 - "nfssvc", // 158 - "getdirentries", // 159 - - "pre_F64_statfs", // 160 - "pre_F64_fstatfs", // 161 - 0, // 162 - "async_daemon", // 163 - "getfh", // 164 - "getdomainname", // 165 - "setdomainname", // 166 - 0, // 167 - 0, // 168 - "exportfs", // 169 - - 0, // 170 - 0, // 171 - 0, // 172 - 0, // 173 - 0, // 174 - 0, // 175 - 0, // 176 - 0, // 177 - 0, // 178 - 0, // 179 - - 0, // 180 - "alt_plock", // 181 - 0, // 182 - 0, // 183 - "getmnt", // 184 - 0, // 185 - 0, // 186 - "alt_sigpending", // 187 - "alt_setsid", // 188 - 0, // 189 - - 0, // 190 - 0, // 191 - 0, // 192 - 0, // 193 - 0, // 194 - 0, // 195 - 0, // 196 - 0, // 197 - 0, // 198 - "swapon", // 199 - - "msgctl", // 200 - "msgget", // 201 - "msgrcv", // 202 - "msgsnd", // 203 - "semctl", // 204 - "semget", // 205 - "semop", // 206 - "uname", // 207 - "lchown", // 208 - "shmat", // 209 - - "shmctl", // 210 - "shmdt", // 211 - "shmget", // 212 - "mvalid", // 213 - "getaddressconf", // 214 - "msleep", // 215 - "mwakeup", // 216 - "msync", // 217 - "signal", // 218 - "utc_gettime", // 219 - - "utc_adjtime", // 220 - 0, // 221 - "security", // 222 - "kloadcall", // 223 - "stat", // 224 - "lstat", // 225 - "fstat", // 226 - "statfs", // 227 - "fstatfs", // 228 - "getfsstat", // 229 - - "gettimeofday64", // 230 - "settimeofday64", // 231 - 0, // 232 - "getpgid", // 233 - "getsid", // 234 - "sigaltstack", // 235 - "waitid", // 236 - "priocntlset", // 237 - "sigsendset", // 238 - "set_speculative", // 239 - - "msfs_syscall", // 240 - "sysinfo", // 241 - "uadmin", // 242 - "fuser", // 243 - "proplist_syscall", // 244 - "ntp_adjtime", // 245 - "ntp_gettime", // 246 - "pathconf", // 247 - "fpathconf", // 248 - "sync2", // 249 - - "uswitch", // 250 - "usleep_thread", // 251 - "audcntl", // 252 - "audgen", // 253 - "sysfs", // 254 - "subsys_info", // 255 - "getsysinfo", // 256 - "setsysinfo", // 257 - "afs_syscall", // 258 - "swapctl", // 259 - - "memcntl", // 260 - "fdatasync", // 261 - "oflock", // 262 - "_F64_readv", // 263 - "_F64_writev", // 264 - "cdslxlate", // 265 - "sendfile", // 266 - }; - - const char * - mach_strings[SystemCalls::MachNumber] = { - 0, // 0 - 0, // 1 - 0, // 2 - 0, // 3 - 0, // 4 - 0, // 5 - 0, // 6 - 0, // 7 - 0, // 8 - 0, // 9 - - "task_self", // 10 - "thread_reply", // 11 - "task_notify", // 12 - "thread_self", // 13 - 0, // 14 - 0, // 15 - 0, // 16 - 0, // 17 - 0, // 18 - 0, // 19 - - "msg_send_trap", // 20 - "msg_receive_trap", // 21 - "msg_rpc_trap", // 22 - 0, // 23 - "nxm_block", // 24 - "nxm_unblock", // 25 - 0, // 26 - 0, // 27 - 0, // 28 - "nxm_thread_destroy", // 29 - - "lw_wire", // 30 - "lw_unwire", // 31 - "nxm_thread_create", // 32 - "nxm_task_init", // 33 - 0, // 34 - "nxm_idle", // 35 - "nxm_wakeup_idle", // 36 - "nxm_set_pthid", // 37 - "nxm_thread_kill", // 38 - "nxm_thread_block", // 39 - - "nxm_thread_wakeup", // 40 - "init_process", // 41 - "nxm_get_binding", // 42 - "map_fd", // 43 - "nxm_resched", // 44 - "nxm_set_cancel", // 45 - "nxm_set_binding", // 46 - "stack_create", // 47 - "nxm_get_state", // 48 - "nxm_thread_suspend", // 49 - - "nxm_thread_resume", // 50 - "nxm_signal_check", // 51 - "htg_unix_syscall", // 52 - 0, // 53 - 0, // 54 - "host_self", // 55 - "host_priv_self", // 56 - 0, // 57 - 0, // 58 - "swtch_pri", // 59 - - "swtch", // 60 - "thread_switch", // 61 - "semop_fast", // 62 - "nxm_pshared_init", // 63 - "nxm_pshared_block", // 64 - "nxm_pshared_unblock", // 65 - "nxm_pshared_destroy", // 66 - "nxm_swtch_pri", // 67 - "lw_syscall", // 68 - 0, // 69 - - "mach_sctimes_0", // 70 - "mach_sctimes_1", // 71 - "mach_sctimes_2", // 72 - "mach_sctimes_3", // 73 - "mach_sctimes_4", // 74 - "mach_sctimes_5", // 75 - "mach_sctimes_6", // 76 - "mach_sctimes_7", // 77 - "mach_sctimes_8", // 78 - "mach_sctimes_9", // 79 - - "mach_sctimes_10", // 80 - "mach_sctimes_11", // 81 - "mach_sctimes_port_alloc_dealloc", // 82 - }; -} - -const char * -SystemCalls::name(int num) -{ - if (num >= Number) - return 0; - else if (num >= StandardNumber) - return mach_strings[num - StandardNumber]; - else if (num >= 0) - return standard_strings[num]; - else if (num > -MachNumber) - return mach_strings[-num]; - else - return 0; -} diff -r 9c673b990d5d -r e1835e5846b9 src/mem/fs_translating_port_proxy.hh --- a/src/mem/fs_translating_port_proxy.hh Mon Oct 24 21:38:48 2016 +0100 +++ b/src/mem/fs_translating_port_proxy.hh Mon Oct 24 21:40:04 2016 +0100 @@ -68,7 +68,7 @@ * physical address and then calls the read/write functions of the * port. If a thread context is provided the address can alway be * translated, If not it can only be translated if it is a simple - * address masking operation (such as alpha super page accesses). + * address masking operation. */ class FSTranslatingPortProxy : public PortProxy { diff -r 9c673b990d5d -r e1835e5846b9 src/sim/process.cc --- a/src/sim/process.cc Mon Oct 24 21:38:48 2016 +0100 +++ b/src/sim/process.cc Mon Oct 24 21:40:04 2016 +0100 @@ -68,10 +68,7 @@ #include "sim/syscall_emul.hh" #include "sim/system.hh" -#if THE_ISA == ALPHA_ISA -#include "arch/alpha/linux/process.hh" -#include "arch/alpha/tru64/process.hh" -#elif THE_ISA == SPARC_ISA +#if THE_ISA == SPARC_ISA #include "arch/sparc/linux/process.hh" #include "arch/sparc/solaris/process.hh" #elif THE_ISA == MIPS_ISA @@ -586,26 +583,7 @@ fatal("Can't load object file %s", params->executable); } -#if THE_ISA == ALPHA_ISA - if (objFile->getArch() != ObjectFile::Alpha) - fatal("Object file architecture does not match compiled ISA (Alpha)."); - - switch (objFile->getOpSys()) { - case ObjectFile::Tru64: - process = new AlphaTru64Process(params, objFile); - break; - - case ObjectFile::UnknownOpSys: - warn("Unknown operating system; assuming Linux."); - // fall through - case ObjectFile::Linux: - process = new AlphaLinuxProcess(params, objFile); - break; - - default: - fatal("Unknown/unsupported operating system."); - } -#elif THE_ISA == SPARC_ISA +#if THE_ISA == SPARC_ISA if (objFile->getArch() != ObjectFile::SPARC64 && objFile->getArch() != ObjectFile::SPARC32) fatal("Object file architecture does not match compiled ISA (SPARC)."); diff -r 9c673b990d5d -r e1835e5846b9 src/sim/syscall_emul.cc --- a/src/sim/syscall_emul.cc Mon Oct 24 21:38:48 2016 +0100 +++ b/src/sim/syscall_emul.cc Mon Oct 24 21:40:04 2016 +0100 @@ -879,7 +879,7 @@ ctc->clearArchRegs(); // Arch-specific cloning code - #if THE_ISA == ALPHA_ISA or THE_ISA == X86_ISA + #if THE_ISA == X86_ISA // Cloning the misc. regs for these archs is enough TheISA::copyMiscRegs(tc, ctc); #elif THE_ISA == SPARC_ISA @@ -909,11 +909,6 @@ // Set up syscall return values in parent and child ctc->setIntReg(ReturnValueReg, 0); // return value, child - // Alpha needs SyscallSuccessReg=0 in child - #if THE_ISA == ALPHA_ISA - ctc->setIntReg(TheISA::SyscallSuccessReg, 0); - #endif - // In SPARC/Linux, clone returns 0 on pseudo-return register if // parent, non-zero if child #if THE_ISA == SPARC_ISA diff -r 9c673b990d5d -r e1835e5846b9 tests/configs/alpha_generic.py --- a/tests/configs/alpha_generic.py Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,100 +0,0 @@ -# Copyright (c) 2012 ARM Limited -# All rights reserved. -# -# The license below extends only to copyright in the software and shall -# not be construed as granting a license to any other intellectual -# property including but not limited to intellectual property relating -# to a hardware implementation of the functionality of the software -# licensed hereunder. You may use the software subject to the license -# terms below provided that you ensure that this notice is replicated -# unmodified and in its entirety in all distributions of the software, -# modified or unmodified, in source code or in binary form. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer; -# redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution; -# neither the name of the copyright holders nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Authors: Andreas Sandberg - -from abc import ABCMeta, abstractmethod -import m5 -from m5.objects import * -from m5.proxy import * -m5.util.addToPath('../configs/') -from common import FSConfig -from common.Caches import * -from base_config import * - -class LinuxAlphaSystemBuilder(object): - """Mix-in that implements create_system. - - This mix-in is intended as a convenient way of adding an - Alpha-specific create_system method to a class deriving from one of - the generic base systems. - """ - def __init__(self): - """ - Arguments: - machine_type -- String describing the platform to simulate - """ - pass - - def create_system(self): - system = FSConfig.makeLinuxAlphaSystem(self.mem_mode) - self.init_system(system) - return system - -class LinuxAlphaFSSystem(LinuxAlphaSystemBuilder, - BaseFSSystem): - """Basic Alpha full system builder.""" - - def __init__(self, **kwargs): - """Initialize an Alpha system that supports full system simulation. - - Note: Keyword arguments that are not listed below will be - passed to the BaseFSSystem. - - Keyword Arguments: - - - """ - BaseSystem.__init__(self, **kwargs) - LinuxAlphaSystemBuilder.__init__(self) - -class LinuxAlphaFSSystemUniprocessor(LinuxAlphaSystemBuilder, - BaseFSSystemUniprocessor): - """Basic Alpha full system builder for uniprocessor systems. - - Note: This class is a specialization of the AlphaFSSystem and is - only really needed to provide backwards compatibility for existing - test cases. - """ - - def __init__(self, **kwargs): - BaseFSSystemUniprocessor.__init__(self, **kwargs) - LinuxAlphaSystemBuilder.__init__(self) - -class LinuxAlphaFSSwitcheroo(LinuxAlphaSystemBuilder, BaseFSSwitcheroo): - """Uniprocessor Alpha system prepared for CPU switching""" - - def __init__(self, **kwargs): - BaseFSSwitcheroo.__init__(self, **kwargs) - LinuxAlphaSystemBuilder.__init__(self) diff -r 9c673b990d5d -r e1835e5846b9 tests/configs/tsunami-minor-dual.py --- a/tests/configs/tsunami-minor-dual.py Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,44 +0,0 @@ -# Copyright (c) 2012 ARM Limited -# All rights reserved. -# -# The license below extends only to copyright in the software and shall -# not be construed as granting a license to any other intellectual -# property including but not limited to intellectual property relating -# to a hardware implementation of the functionality of the software -# licensed hereunder. You may use the software subject to the license -# terms below provided that you ensure that this notice is replicated -# unmodified and in its entirety in all distributions of the software, -# modified or unmodified, in source code or in binary form. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer; -# redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution; -# neither the name of the copyright holders nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Authors: Andreas Sandberg - -from m5.objects import * -from alpha_generic import * - -root = LinuxAlphaFSSystem(mem_mode='timing', - mem_class=DDR3_1600_x64, - cpu_class=MinorCPU, - num_cpus=2).create_root() diff -r 9c673b990d5d -r e1835e5846b9 tests/configs/tsunami-minor.py --- a/tests/configs/tsunami-minor.py Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,43 +0,0 @@ -# Copyright (c) 2012 ARM Limited -# All rights reserved. -# -# The license below extends only to copyright in the software and shall -# not be construed as granting a license to any other intellectual -# property including but not limited to intellectual property relating -# to a hardware implementation of the functionality of the software -# licensed hereunder. You may use the software subject to the license -# terms below provided that you ensure that this notice is replicated -# unmodified and in its entirety in all distributions of the software, -# modified or unmodified, in source code or in binary form. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer; -# redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution; -# neither the name of the copyright holders nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Authors: Andreas Sandberg - -from m5.objects import * -from alpha_generic import * - -root = LinuxAlphaFSSystemUniprocessor(mem_mode='timing', - mem_class=DDR3_1600_x64, - cpu_class=MinorCPU).create_root() diff -r 9c673b990d5d -r e1835e5846b9 tests/configs/tsunami-o3-dual.py --- a/tests/configs/tsunami-o3-dual.py Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,44 +0,0 @@ -# Copyright (c) 2012 ARM Limited -# All rights reserved. -# -# The license below extends only to copyright in the software and shall -# not be construed as granting a license to any other intellectual -# property including but not limited to intellectual property relating -# to a hardware implementation of the functionality of the software -# licensed hereunder. You may use the software subject to the license -# terms below provided that you ensure that this notice is replicated -# unmodified and in its entirety in all distributions of the software, -# modified or unmodified, in source code or in binary form. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer; -# redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution; -# neither the name of the copyright holders nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Authors: Andreas Sandberg - -from m5.objects import * -from alpha_generic import * - -root = LinuxAlphaFSSystem(mem_mode='timing', - mem_class=DDR3_1600_x64, - cpu_class=DerivO3CPU, - num_cpus=2).create_root() diff -r 9c673b990d5d -r e1835e5846b9 tests/configs/tsunami-o3.py --- a/tests/configs/tsunami-o3.py Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,43 +0,0 @@ -# Copyright (c) 2012 ARM Limited -# All rights reserved. -# -# The license below extends only to copyright in the software and shall -# not be construed as granting a license to any other intellectual -# property including but not limited to intellectual property relating -# to a hardware implementation of the functionality of the software -# licensed hereunder. You may use the software subject to the license -# terms below provided that you ensure that this notice is replicated -# unmodified and in its entirety in all distributions of the software, -# modified or unmodified, in source code or in binary form. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer; -# redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution; -# neither the name of the copyright holders nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Authors: Andreas Sandberg - -from m5.objects import * -from alpha_generic import * - -root = LinuxAlphaFSSystemUniprocessor(mem_mode='timing', - mem_class=DDR3_1600_x64, - cpu_class=DerivO3CPU).create_root() diff -r 9c673b990d5d -r e1835e5846b9 tests/configs/tsunami-simple-atomic-dual.py --- a/tests/configs/tsunami-simple-atomic-dual.py Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,44 +0,0 @@ -# Copyright (c) 2012 ARM Limited -# All rights reserved. -# -# The license below extends only to copyright in the software and shall -# not be construed as granting a license to any other intellectual -# property including but not limited to intellectual property relating -# to a hardware implementation of the functionality of the software -# licensed hereunder. You may use the software subject to the license -# terms below provided that you ensure that this notice is replicated -# unmodified and in its entirety in all distributions of the software, -# modified or unmodified, in source code or in binary form. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer; -# redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution; -# neither the name of the copyright holders nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Authors: Andreas Sandberg - -from m5.objects import * -from alpha_generic import * - -root = LinuxAlphaFSSystem(mem_mode='atomic', - mem_class=SimpleMemory, - cpu_class=AtomicSimpleCPU, - num_cpus=2).create_root() diff -r 9c673b990d5d -r e1835e5846b9 tests/configs/tsunami-simple-atomic.py --- a/tests/configs/tsunami-simple-atomic.py Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,43 +0,0 @@ -# Copyright (c) 2012 ARM Limited -# All rights reserved. -# -# The license below extends only to copyright in the software and shall -# not be construed as granting a license to any other intellectual -# property including but not limited to intellectual property relating -# to a hardware implementation of the functionality of the software -# licensed hereunder. You may use the software subject to the license -# terms below provided that you ensure that this notice is replicated -# unmodified and in its entirety in all distributions of the software, -# modified or unmodified, in source code or in binary form. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer; -# redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution; -# neither the name of the copyright holders nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Authors: Andreas Sandberg - -from m5.objects import * -from alpha_generic import * - -root = LinuxAlphaFSSystemUniprocessor(mem_mode='atomic', - mem_class=SimpleMemory, - cpu_class=AtomicSimpleCPU).create_root() diff -r 9c673b990d5d -r e1835e5846b9 tests/configs/tsunami-simple-timing-dual.py --- a/tests/configs/tsunami-simple-timing-dual.py Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,44 +0,0 @@ -# Copyright (c) 2012 ARM Limited -# All rights reserved. -# -# The license below extends only to copyright in the software and shall -# not be construed as granting a license to any other intellectual -# property including but not limited to intellectual property relating -# to a hardware implementation of the functionality of the software -# licensed hereunder. You may use the software subject to the license -# terms below provided that you ensure that this notice is replicated -# unmodified and in its entirety in all distributions of the software, -# modified or unmodified, in source code or in binary form. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer; -# redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution; -# neither the name of the copyright holders nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Authors: Andreas Sandberg - -from m5.objects import * -from alpha_generic import * - -root = LinuxAlphaFSSystem(mem_mode='timing', - mem_class=DDR3_1600_x64, - cpu_class=TimingSimpleCPU, - num_cpus=2).create_root() diff -r 9c673b990d5d -r e1835e5846b9 tests/configs/tsunami-simple-timing.py --- a/tests/configs/tsunami-simple-timing.py Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,43 +0,0 @@ -# Copyright (c) 2012 ARM Limited -# All rights reserved. -# -# The license below extends only to copyright in the software and shall -# not be construed as granting a license to any other intellectual -# property including but not limited to intellectual property relating -# to a hardware implementation of the functionality of the software -# licensed hereunder. You may use the software subject to the license -# terms below provided that you ensure that this notice is replicated -# unmodified and in its entirety in all distributions of the software, -# modified or unmodified, in source code or in binary form. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer; -# redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution; -# neither the name of the copyright holders nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Authors: Andreas Sandberg - -from m5.objects import * -from alpha_generic import * - -root = LinuxAlphaFSSystemUniprocessor(mem_mode='timing', - mem_class=DDR3_1600_x64, - cpu_class=TimingSimpleCPU).create_root() diff -r 9c673b990d5d -r e1835e5846b9 tests/configs/tsunami-switcheroo-full.py --- a/tests/configs/tsunami-switcheroo-full.py Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,49 +0,0 @@ -# Copyright (c) 2012 ARM Limited -# All rights reserved. -# -# The license below extends only to copyright in the software and shall -# not be construed as granting a license to any other intellectual -# property including but not limited to intellectual property relating -# to a hardware implementation of the functionality of the software -# licensed hereunder. You may use the software subject to the license -# terms below provided that you ensure that this notice is replicated -# unmodified and in its entirety in all distributions of the software, -# modified or unmodified, in source code or in binary form. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer; -# redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution; -# neither the name of the copyright holders nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Authors: Andreas Sandberg - -from m5.objects import * -from alpha_generic import * -import switcheroo - -root = LinuxAlphaFSSwitcheroo( - mem_class=DDR3_1600_x64, - cpu_classes=(AtomicSimpleCPU, TimingSimpleCPU, DerivO3CPU) - ).create_root() - -# Setup a custom test method that uses the switcheroo tester that -# switches between CPU models. -run_test = switcheroo.run_test diff -r 9c673b990d5d -r e1835e5846b9 tests/configs/twosys-tsunami-simple-atomic.py --- a/tests/configs/twosys-tsunami-simple-atomic.py Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,104 +0,0 @@ -# Copyright (c) 2006 The Regents of The University of Michigan -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer; -# redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution; -# neither the name of the copyright holders nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Authors: Lisa Hsu - -import m5 -from m5.objects import * -m5.util.addToPath('../configs/') -from common.FSConfig import * -from common.Benchmarks import * - -test_sys = makeLinuxAlphaSystem('atomic', - SysConfig('netperf-stream-client.rcS')) - -# Dummy voltage domain for all test_sys clock domains -test_sys.voltage_domain = VoltageDomain() - -# Create the system clock domain -test_sys.clk_domain = SrcClockDomain(clock = '1GHz', - voltage_domain = test_sys.voltage_domain) - -test_sys.cpu = AtomicSimpleCPU(cpu_id=0) -# create the interrupt controller -test_sys.cpu.createInterruptController() -test_sys.cpu.connectAllPorts(test_sys.membus) - -# Create a seperate clock domain for components that should run at -# CPUs frequency -test_sys.cpu.clk_domain = SrcClockDomain(clock = '2GHz', - voltage_domain = - test_sys.voltage_domain) - -# Create a separate clock domain for Ethernet -test_sys.tsunami.ethernet.clk_domain = SrcClockDomain(clock = '500MHz', - voltage_domain = - test_sys.voltage_domain) - -# In contrast to the other (one-system) Tsunami configurations we do -# not have an IO cache but instead rely on an IO bridge for accesses -# from masters on the IO bus to the memory bus -test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges) -test_sys.iobridge.slave = test_sys.iobus.master -test_sys.iobridge.master = test_sys.membus.slave - -test_sys.physmem = SimpleMemory(range = test_sys.mem_ranges[0]) -test_sys.physmem.port = test_sys.membus.master - -drive_sys = makeLinuxAlphaSystem('atomic', - SysConfig('netperf-server.rcS')) -# Dummy voltage domain for all drive_sys clock domains -drive_sys.voltage_domain = VoltageDomain() -# Create the system clock domain -drive_sys.clk_domain = SrcClockDomain(clock = '1GHz', - voltage_domain = - drive_sys.voltage_domain) -drive_sys.cpu = AtomicSimpleCPU(cpu_id=0) -# create the interrupt controller -drive_sys.cpu.createInterruptController() -drive_sys.cpu.connectAllPorts(drive_sys.membus) - -# Create a seperate clock domain for components that should run at -# CPUs frequency -drive_sys.cpu.clk_domain = SrcClockDomain(clock = '4GHz', - voltage_domain = - drive_sys.voltage_domain) - -# Create a separate clock domain for Ethernet -drive_sys.tsunami.ethernet.clk_domain = SrcClockDomain(clock = '500MHz', - voltage_domain = - drive_sys.voltage_domain) - -drive_sys.iobridge = Bridge(delay='50ns', ranges = drive_sys.mem_ranges) -drive_sys.iobridge.slave = drive_sys.iobus.master -drive_sys.iobridge.master = drive_sys.membus.slave - -drive_sys.physmem = SimpleMemory(range = drive_sys.mem_ranges[0]) -drive_sys.physmem.port = drive_sys.membus.master - -root = makeDualRoot(True, test_sys, drive_sys, "ethertrace") - -maxtick = 199999999 diff -r 9c673b990d5d -r e1835e5846b9 tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,1784 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=true -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=LinuxAlphaSystem -children=bridge clk_domain cpu cpu_clk_domain disk0 disk2 dvfs_handler intrctrl iobus iocache membus physmem simple_disk terminal tsunami voltage_domain -boot_cpu_frequency=500 -boot_osflags=root=/dev/hda1 console=ttyS0 -cache_line_size=64 -clk_domain=system.clk_domain -console=/arm/projectscratch/randd/systems/dist/binaries/console -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges=0:134217727:0:0:0:0 -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pal=/arm/projectscratch/randd/systems/dist/binaries/ts_osfpal -power_model=Null -readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh -symbolfile= -system_rev=1024 -system_type=34 -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.bridge] -type=Bridge -clk_domain=system.clk_domain -default_p_state=UNDEFINED -delay=50000 -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -ranges=8796093022208:18446744073709551615:0:0:0:0 -req_size=16 -resp_size=16 -master=system.iobus.slave[0] -slave=system.membus.master[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=MinorCPU -children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer -branchPred=system.cpu.branchPred -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -decodeCycleInput=true -decodeInputBufferSize=3 -decodeInputWidth=2 -decodeToExecuteForwardDelay=1 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -enableIdling=true -eventq_index=0 -executeAllowEarlyMemoryIssue=true -executeBranchDelay=1 -executeCommitLimit=2 -executeCycleInput=true -executeFuncUnits=system.cpu.executeFuncUnits -executeInputBufferSize=7 -executeInputWidth=2 -executeIssueLimit=2 -executeLSQMaxStoreBufferStoresPerCycle=2 -executeLSQRequestsQueueSize=1 -executeLSQStoreBufferSize=5 -executeLSQTransfersQueueSize=2 -executeMaxAccessesInMemory=2 -executeMemoryCommitLimit=1 -executeMemoryIssueLimit=1 -executeMemoryWidth=0 -executeSetTraceTimeOnCommit=true -executeSetTraceTimeOnIssue=false -fetch1FetchLimit=1 -fetch1LineSnapWidth=0 -fetch1LineWidth=0 -fetch1ToFetch2BackwardDelay=1 -fetch1ToFetch2ForwardDelay=1 -fetch2CycleInput=true -fetch2InputBufferSize=2 -fetch2ToDecodeForwardDelay=1 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -threadPolicy=RoundRobin -tracer=system.cpu.tracer -workload= -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.branchPred] -type=TournamentBP -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -indirectHashGHR=true -indirectHashTargets=true -indirectPathLength=3 -indirectSets=256 -indirectTagSize=16 -indirectWays=2 -instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 -useIndirect=true - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=4 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=4 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.executeFuncUnits] -type=MinorFUPool -children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 -eventq_index=0 -funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 - -[system.cpu.executeFuncUnits.funcUnits0] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits0.timings - -[system.cpu.executeFuncUnits.funcUnits0.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntAlu - -[system.cpu.executeFuncUnits.funcUnits0.timings] -type=MinorFUTiming -children=opClasses -description=Int -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits1] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits1.timings - -[system.cpu.executeFuncUnits.funcUnits1.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntAlu - -[system.cpu.executeFuncUnits.funcUnits1.timings] -type=MinorFUTiming -children=opClasses -description=Int -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits2] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits2.timings - -[system.cpu.executeFuncUnits.funcUnits2.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntMult - -[system.cpu.executeFuncUnits.funcUnits2.timings] -type=MinorFUTiming -children=opClasses -description=Mul -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses -srcRegsRelativeLats=0 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits3] -type=MinorFU -children=opClasses -cantForwardFromFUIndices= -eventq_index=0 -issueLat=9 -opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses -opLat=9 -timings= - -[system.cpu.executeFuncUnits.funcUnits3.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntDiv - -[system.cpu.executeFuncUnits.funcUnits4] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses -opLat=6 -timings=system.cpu.executeFuncUnits.funcUnits4.timings - -[system.cpu.executeFuncUnits.funcUnits4.opClasses] -type=MinorOpClassSet -children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] -type=MinorOpClass -eventq_index=0 -opClass=FloatAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01] -type=MinorOpClass -eventq_index=0 -opClass=FloatCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02] -type=MinorOpClass -eventq_index=0 -opClass=FloatCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] -type=MinorOpClass -eventq_index=0 -opClass=FloatMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] -type=MinorOpClass -eventq_index=0 -opClass=FloatDiv - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] -type=MinorOpClass -eventq_index=0 -opClass=FloatSqrt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] -type=MinorOpClass -eventq_index=0 -opClass=SimdAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] -type=MinorOpClass -eventq_index=0 -opClass=SimdAddAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] -type=MinorOpClass -eventq_index=0 -opClass=SimdAlu - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] -type=MinorOpClass -eventq_index=0 -opClass=SimdCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] -type=MinorOpClass -eventq_index=0 -opClass=SimdCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] -type=MinorOpClass -eventq_index=0 -opClass=SimdMisc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] -type=MinorOpClass -eventq_index=0 -opClass=SimdMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] -type=MinorOpClass -eventq_index=0 -opClass=SimdMultAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] -type=MinorOpClass -eventq_index=0 -opClass=SimdShift - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] -type=MinorOpClass -eventq_index=0 -opClass=SimdShiftAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] -type=MinorOpClass -eventq_index=0 -opClass=SimdSqrt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatAlu - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatDiv - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMisc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMultAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatSqrt - -[system.cpu.executeFuncUnits.funcUnits4.timings] -type=MinorFUTiming -children=opClasses -description=FloatSimd -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits5] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses -opLat=1 -timings=system.cpu.executeFuncUnits.funcUnits5.timings - -[system.cpu.executeFuncUnits.funcUnits5.opClasses] -type=MinorOpClassSet -children=opClasses0 opClasses1 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 - -[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] -type=MinorOpClass -eventq_index=0 -opClass=MemRead - -[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] -type=MinorOpClass -eventq_index=0 -opClass=MemWrite - -[system.cpu.executeFuncUnits.funcUnits5.timings] -type=MinorFUTiming -children=opClasses -description=Mem -eventq_index=0 -extraAssumedLat=2 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses -srcRegsRelativeLats=1 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits6] -type=MinorFU -children=opClasses -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses -opLat=1 -timings= - -[system.cpu.executeFuncUnits.funcUnits6.opClasses] -type=MinorOpClassSet -children=opClasses0 opClasses1 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 - -[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] -type=MinorOpClass -eventq_index=0 -opClass=IprAccess - -[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] -type=MinorOpClass -eventq_index=0 -opClass=InstPrefetch - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=1 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=1 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=4194304 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=4194304 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.disk0] -type=IdeDisk -children=image -delay=1000000 -driveID=master -eventq_index=0 -image=system.disk0.image - -[system.disk0.image] -type=CowDiskImage -children=child -child=system.disk0.image.child -eventq_index=0 -image_file= -read_only=false -table_size=65536 - -[system.disk0.image.child] -type=RawDiskImage -eventq_index=0 -image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img -read_only=true - -[system.disk2] -type=IdeDisk -children=image -delay=1000000 -driveID=master -eventq_index=0 -image=system.disk2.image - -[system.disk2.image] -type=CowDiskImage -children=child -child=system.disk2.image.child -eventq_index=0 -image_file= -read_only=false -table_size=65536 - -[system.disk2.image.child] -type=RawDiskImage -eventq_index=0 -image_file=/arm/projectscratch/randd/systems/dist/disks/linux-bigswap2.img -read_only=true - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.intrctrl] -type=IntrControl -eventq_index=0 -sys=system - -[system.iobus] -type=NoncoherentXBar -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=1 -frontend_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -response_latency=2 -use_default_range=false -width=16 -master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side -slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma - -[system.iocache] -type=Cache -children=tags -addr_ranges=0:134217727:0:0:0:0 -assoc=8 -clk_domain=system.clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=50 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=50 -sequential_access=false -size=1024 -system=system -tags=system.iocache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.iobus.master[27] -mem_side=system.membus.slave[2] - -[system.iocache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=50 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=1024 - -[system.membus] -type=CoherentXBar -children=badaddr_responder snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side - -[system.membus.badaddr_responder] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=0 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=true -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.membus.default - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=0:134217727:0:0:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=6000 -tXPDLL=0 -tXS=270000 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[1] - -[system.simple_disk] -type=SimpleDisk -children=disk -disk=system.simple_disk.disk -eventq_index=0 -system=system - -[system.simple_disk.disk] -type=RawDiskImage -eventq_index=0 -image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img -read_only=true - -[system.terminal] -type=Terminal -eventq_index=0 -intr_control=system.intrctrl -number=0 -output=true -port=3456 - -[system.tsunami] -type=Tsunami -children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip uart -eventq_index=0 -intrctrl=system.intrctrl -system=system - -[system.tsunami.backdoor] -type=AlphaBackdoor -clk_domain=system.clk_domain -cpu=system.cpu -default_p_state=UNDEFINED -disk=system.simple_disk -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804682956800 -pio_latency=100000 -platform=system.tsunami -power_model=Null -system=system -terminal=system.terminal -pio=system.iobus.master[24] - -[system.tsunami.cchip] -type=TsunamiCChip -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8803072344064 -pio_latency=100000 -power_model=Null -system=system -tsunami=system.tsunami -pio=system.iobus.master[0] - -[system.tsunami.ethernet] -type=NSGigE -BAR0=1 -BAR0LegacyIO=false -BAR0Size=256 -BAR1=0 -BAR1LegacyIO=false -BAR1Size=4096 -BAR2=0 -BAR2LegacyIO=false -BAR2Size=0 -BAR3=0 -BAR3LegacyIO=false -BAR3Size=0 -BAR4=0 -BAR4LegacyIO=false -BAR4Size=0 -BAR5=0 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=2 -Command=0 -DeviceID=34 -ExpansionROM=0 -HeaderType=0 -InterruptLine=30 -InterruptPin=1 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=52 -MinimumGrant=176 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=0 -Revision=0 -Status=656 -SubClassCode=0 -SubsystemID=0 -SubsystemVendorID=0 -VendorID=4107 -clk_domain=system.clk_domain -config_latency=20000 -default_p_state=UNDEFINED -dma_data_free=false -dma_desc_free=false -dma_no_allocate=true -dma_read_delay=0 -dma_read_factor=0 -dma_write_delay=0 -dma_write_factor=0 -eventq_index=0 -hardware_address=00:90:00:00:00:01 -host=system.tsunami.pchip -intr_delay=10000000 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_bus=0 -pci_dev=1 -pci_func=0 -pio_latency=30000 -power_model=Null -rss=false -rx_delay=1000000 -rx_fifo_size=524288 -rx_filter=true -rx_thread=false -system=system -tx_delay=1000000 -tx_fifo_size=524288 -tx_thread=false -dma=system.iobus.slave[2] -pio=system.iobus.master[26] - -[system.tsunami.fake_OROM] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8796093677568 -pio_latency=100000 -pio_size=393216 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[8] - -[system.tsunami.fake_ata0] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848432 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[19] - -[system.tsunami.fake_ata1] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848304 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[20] - -[system.tsunami.fake_pnp_addr] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848569 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[9] - -[system.tsunami.fake_pnp_read0] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848451 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[11] - -[system.tsunami.fake_pnp_read1] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848515 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[12] - -[system.tsunami.fake_pnp_read2] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848579 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[13] - -[system.tsunami.fake_pnp_read3] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848643 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[14] - -[system.tsunami.fake_pnp_read4] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848707 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[15] - -[system.tsunami.fake_pnp_read5] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848771 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[16] - -[system.tsunami.fake_pnp_read6] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848835 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[17] - -[system.tsunami.fake_pnp_read7] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848899 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[18] - -[system.tsunami.fake_pnp_write] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615850617 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[10] - -[system.tsunami.fake_ppc] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848891 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[7] - -[system.tsunami.fake_sm_chip] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848816 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[2] - -[system.tsunami.fake_uart1] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848696 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[3] - -[system.tsunami.fake_uart2] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848936 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[4] - -[system.tsunami.fake_uart3] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848680 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[5] - -[system.tsunami.fake_uart4] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848944 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[6] - -[system.tsunami.fb] -type=BadDevice -clk_domain=system.clk_domain -default_p_state=UNDEFINED -devicename=FrameBuffer -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848912 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[21] - -[system.tsunami.ide] -type=IdeController -BAR0=1 -BAR0LegacyIO=false -BAR0Size=8 -BAR1=1 -BAR1LegacyIO=false -BAR1Size=4 -BAR2=1 -BAR2LegacyIO=false -BAR2Size=8 -BAR3=1 -BAR3LegacyIO=false -BAR3Size=4 -BAR4=1 -BAR4LegacyIO=false -BAR4Size=16 -BAR5=1 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=1 -Command=0 -DeviceID=28945 -ExpansionROM=0 -HeaderType=0 -InterruptLine=31 -InterruptPin=1 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=0 -MinimumGrant=0 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=133 -Revision=0 -Status=640 -SubClassCode=1 -SubsystemID=0 -SubsystemVendorID=0 -VendorID=32902 -clk_domain=system.clk_domain -config_latency=20000 -ctrl_offset=0 -default_p_state=UNDEFINED -disks=system.disk0 system.disk2 -eventq_index=0 -host=system.tsunami.pchip -io_shift=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_bus=0 -pci_dev=0 -pci_func=0 -pio_latency=30000 -power_model=Null -system=system -dma=system.iobus.slave[1] -pio=system.iobus.master[25] - -[system.tsunami.io] -type=TsunamiIO -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -frequency=976562500 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615847936 -pio_latency=100000 -power_model=Null -system=system -time=Thu Jan 1 00:00:00 2009 -tsunami=system.tsunami -year_is_bcd=false -pio=system.iobus.master[22] - -[system.tsunami.pchip] -type=TsunamiPChip -clk_domain=system.clk_domain -conf_base=8804649402368 -conf_device_bits=8 -conf_size=16777216 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_dma_base=0 -pci_mem_base=8796093022208 -pci_pio_base=8804615847936 -pio_addr=8802535473152 -pio_latency=100000 -platform=system.tsunami -power_model=Null -system=system -tsunami=system.tsunami -pio=system.iobus.master[1] - -[system.tsunami.uart] -type=Uart8250 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848952 -pio_latency=100000 -platform=system.tsunami -power_model=Null -system=system -terminal=system.terminal -pio=system.iobus.master[23] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff -r 9c673b990d5d -r e1835e5846b9 tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simerr --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simerr Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,6 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Sockets disabled, not accepting terminal connections -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything diff -r 9c673b990d5d -r e1835e5846b9 tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simout --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simout Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,15 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-minor/simout -Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-minor/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:19:46 -gem5 executing on e108600-lin, pid 28076 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-minor -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/alpha/linux/tsunami-minor - -Global frequency set at 1000000000000 ticks per second -info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1893220881500 because m5_exit instruction encountered diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/stacktrace.cc --- a/src/arch/alpha/stacktrace.cc Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,363 +0,0 @@ -/* - * Copyright (c) 2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Nathan Binkert - */ - -#include - -#include "arch/alpha/isa_traits.hh" -#include "arch/alpha/stacktrace.hh" -#include "arch/alpha/vtophys.hh" -#include "base/bitfield.hh" -#include "base/trace.hh" -#include "cpu/base.hh" -#include "cpu/thread_context.hh" -#include "mem/fs_translating_port_proxy.hh" -#include "sim/system.hh" - -using namespace std; - -namespace AlphaISA { - -ProcessInfo::ProcessInfo(ThreadContext *_tc) - : tc(_tc) -{ - Addr addr = 0; - FSTranslatingPortProxy &vp = tc->getVirtProxy(); - SymbolTable *symtab = tc->getSystemPtr()->kernelSymtab; - - if (!symtab->findAddress("thread_info_size", addr)) - panic("thread info not compiled into kernel\n"); - thread_info_size = vp.readGtoH(addr); - - if (!symtab->findAddress("task_struct_size", addr)) - panic("thread info not compiled into kernel\n"); - task_struct_size = vp.readGtoH(addr); - - if (!symtab->findAddress("thread_info_task", addr)) - panic("thread info not compiled into kernel\n"); - task_off = vp.readGtoH(addr); - - if (!symtab->findAddress("task_struct_pid", addr)) - panic("thread info not compiled into kernel\n"); - pid_off = vp.readGtoH(addr); - - if (!symtab->findAddress("task_struct_comm", addr)) - panic("thread info not compiled into kernel\n"); - name_off = vp.readGtoH(addr); -} - -Addr -ProcessInfo::task(Addr ksp) const -{ - Addr base = ksp & ~0x3fff; - if (base == ULL(0xfffffc0000000000)) - return 0; - - Addr tsk; - - FSTranslatingPortProxy &vp = tc->getVirtProxy(); - tsk = vp.readGtoH(base + task_off); - - return tsk; -} - -int -ProcessInfo::pid(Addr ksp) const -{ - Addr task = this->task(ksp); - if (!task) - return -1; - - uint16_t pd; - - FSTranslatingPortProxy &vp = tc->getVirtProxy(); - pd = vp.readGtoH(task + pid_off); - - return pd; -} - -string -ProcessInfo::name(Addr ksp) const -{ - Addr task = this->task(ksp); - if (!task) - return "console"; - - char comm[256]; - CopyStringOut(tc, comm, task + name_off, sizeof(comm)); - if (!comm[0]) - return "startup"; - - return comm; -} - -StackTrace::StackTrace() - : tc(0), stack(64) -{ -} - -StackTrace::StackTrace(ThreadContext *_tc, const StaticInstPtr &inst) - : tc(0), stack(64) -{ - trace(_tc, inst); -} - -StackTrace::~StackTrace() -{ -} - -void -StackTrace::trace(ThreadContext *_tc, bool is_call) -{ - tc = _tc; - - System *sys = tc->getSystemPtr(); - - bool usermode = - (tc->readMiscRegNoEffect(IPR_DTB_CM) & 0x18) != 0; - - Addr pc = tc->pcState().pc(); - bool kernel = sys->kernelStart <= pc && pc <= sys->kernelEnd; - - if (usermode) { - stack.push_back(user); - return; - } - - if (!kernel) { - stack.push_back(console); - return; - } - - SymbolTable *symtab = sys->kernelSymtab; - Addr ksp = tc->readIntReg(StackPointerReg); - Addr bottom = ksp & ~0x3fff; - - if (is_call) { - Addr addr; - if (!symtab->findNearestAddr(pc, addr)) - panic("could not find address %#x", pc); - - stack.push_back(addr); - pc = tc->pcState().pc(); - } - - while (ksp > bottom) { - Addr addr; - if (!symtab->findNearestAddr(pc, addr)) - panic("could not find symbol for pc=%#x", pc); - assert(pc >= addr && "symbol botch: callpc < func"); - - stack.push_back(addr); - - if (isEntry(addr)) - return; - - Addr ra; - int size; - if (decodePrologue(ksp, pc, addr, size, ra)) { - if (!ra) - return; - - if (size <= 0) { - stack.push_back(unknown); - return; - } - - pc = ra; - ksp += size; - } else { - stack.push_back(unknown); - return; - } - - kernel = sys->kernelStart <= pc && pc <= sys->kernelEnd; - if (!kernel) - return; - - if (stack.size() >= 1000) - panic("unwinding too far"); - } - - panic("unwinding too far"); -} - -bool -StackTrace::isEntry(Addr addr) -{ - if (addr == tc->readMiscRegNoEffect(IPR_PALtemp12)) - return true; - - if (addr == tc->readMiscRegNoEffect(IPR_PALtemp7)) - return true; - - if (addr == tc->readMiscRegNoEffect(IPR_PALtemp11)) - return true; - - if (addr == tc->readMiscRegNoEffect(IPR_PALtemp21)) - return true; - - if (addr == tc->readMiscRegNoEffect(IPR_PALtemp9)) - return true; - - if (addr == tc->readMiscRegNoEffect(IPR_PALtemp2)) - return true; - - return false; -} - -bool -StackTrace::decodeStack(MachInst inst, int &disp) -{ - // lda $sp, -disp($sp) - // - // Opcode<31:26> == 0x08 - // RA<25:21> == 30 - // RB<20:16> == 30 - // Disp<15:0> - const MachInst mem_mask = 0xffff0000; - const MachInst lda_pattern = 0x23de0000; - const MachInst lda_disp_mask = 0x0000ffff; - - // subq $sp, disp, $sp - // addq $sp, disp, $sp - // - // Opcode<31:26> == 0x10 - // RA<25:21> == 30 - // Lit<20:13> - // One<12> = 1 - // Func<11:5> == 0x20 (addq) - // Func<11:5> == 0x29 (subq) - // RC<4:0> == 30 - const MachInst intop_mask = 0xffe01fff; - const MachInst addq_pattern = 0x43c0141e; - const MachInst subq_pattern = 0x43c0153e; - const MachInst intop_disp_mask = 0x001fe000; - const int intop_disp_shift = 13; - - if ((inst & mem_mask) == lda_pattern) - disp = -sext<16>(inst & lda_disp_mask); - else if ((inst & intop_mask) == addq_pattern) - disp = -int((inst & intop_disp_mask) >> intop_disp_shift); - else if ((inst & intop_mask) == subq_pattern) - disp = int((inst & intop_disp_mask) >> intop_disp_shift); - else - return false; - - return true; -} - -bool -StackTrace::decodeSave(MachInst inst, int ®, int &disp) -{ - // lda $stq, disp($sp) - // - // Opcode<31:26> == 0x08 - // RA<25:21> == ? - // RB<20:16> == 30 - // Disp<15:0> - const MachInst stq_mask = 0xfc1f0000; - const MachInst stq_pattern = 0xb41e0000; - const MachInst stq_disp_mask = 0x0000ffff; - const MachInst reg_mask = 0x03e00000; - const int reg_shift = 21; - - if ((inst & stq_mask) == stq_pattern) { - reg = (inst & reg_mask) >> reg_shift; - disp = sext<16>(inst & stq_disp_mask); - } else { - return false; - } - - return true; -} - -/* - * Decode the function prologue for the function we're in, and note - * which registers are stored where, and how large the stack frame is. - */ -bool -StackTrace::decodePrologue(Addr sp, Addr callpc, Addr func, int &size, - Addr &ra) -{ - size = 0; - ra = 0; - - for (Addr pc = func; pc < callpc; pc += sizeof(MachInst)) { - MachInst inst; - CopyOut(tc, (uint8_t *)&inst, pc, sizeof(MachInst)); - - int reg, disp; - if (decodeStack(inst, disp)) { - if (size) { - // panic("decoding frame size again"); - return true; - } - size += disp; - } else if (decodeSave(inst, reg, disp)) { - if (!ra && reg == ReturnAddressReg) { - CopyOut(tc, (uint8_t *)&ra, sp + disp, sizeof(Addr)); - if (!ra) { - // panic("no return address value pc=%#x\n", pc); - return false; - } - } - } - } - - return true; -} - -#if TRACING_ON -void -StackTrace::dump() -{ - StringWrap name(tc->getCpuPtr()->name()); - SymbolTable *symtab = tc->getSystemPtr()->kernelSymtab; - - DPRINTFN("------ Stack ------\n"); - - string symbol; - for (int i = 0, size = stack.size(); i < size; ++i) { - Addr addr = stack[size - i - 1]; - if (addr == user) - symbol = "user"; - else if (addr == console) - symbol = "console"; - else if (addr == unknown) - symbol = "unknown"; - else - symtab->findSymbol(addr, symbol); - - DPRINTFN("%#x: %s\n", addr, symbol); - } -} -#endif - -} // namespace AlphaISA diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/system.hh --- a/src/arch/alpha/system.hh Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,131 +0,0 @@ -/* - * Copyright (c) 2002-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Ali Saidi - * Nathan Binkert - */ - -#ifndef __ARCH_ALPHA_SYSTEM_HH__ -#define __ARCH_ALPHA_SYSTEM_HH__ - -#include -#include - -#include "base/loader/symtab.hh" -#include "cpu/pc_event.hh" -#include "kern/system_events.hh" -#include "mem/fs_translating_port_proxy.hh" -#include "params/AlphaSystem.hh" -#include "sim/sim_object.hh" -#include "sim/system.hh" - -class AlphaSystem : public System -{ - public: - typedef AlphaSystemParams Params; - AlphaSystem(Params *p); - ~AlphaSystem(); - - public: - - /** - * Initialise the state of the system. - */ - void initState() override; - - /** - * Serialization stuff - */ - void serializeSymtab(CheckpointOut &cp) const override; - void unserializeSymtab(CheckpointIn &cp) override; - - /** Override startup() to provide a path to call setupFuncEvents() - */ - void startup() override; - - /** - * Set the m5AlphaAccess pointer in the console - */ - void setAlphaAccess(Addr access); - - /** console symbol table */ - SymbolTable *consoleSymtab; - - /** pal symbol table */ - SymbolTable *palSymtab; - - /** Object pointer for the console code */ - ObjectFile *console; - - /** Object pointer for the PAL code */ - ObjectFile *pal; - -#ifndef NDEBUG - /** Event to halt the simulator if the console calls panic() */ - BreakPCEvent *consolePanicEvent; -#endif - - protected: - Tick intrFreq; - - /** - * Proxy used to copy arguments directly into kernel memory. - */ - FSTranslatingPortProxy virtProxy; - - const Params *params() const { return (const Params *)_params; } - - - /** Setup all the function events. Must be done after init() for Alpha since - * fixFuncEvent() requires a function port - */ - virtual void setupFuncEvents(); - - /** Add a function-based event to PALcode. */ - template - T * - addPalFuncEvent(const char *lbl) - { - return addFuncEvent(palSymtab, lbl); - } - - /** Add a function-based event to the console code. */ - template - T * - addConsoleFuncEvent(const char *lbl) - { - return addFuncEvent(consoleSymtab, lbl); - } - - Addr fixFuncEventAddr(Addr addr) override; - - public: - void setIntrFreq(Tick freq) { intrFreq = freq; } -}; - -#endif // __ARCH_ALPHA_SYSTEM_HH__ - diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/20.parser/ref/alpha/tru64/minor-timing/simout --- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/simout Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,72 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/se/20.parser/alpha/tru64/minor-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/long/se/20.parser/alpha/tru64/minor-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:19:45 -gem5 executing on e108600-lin, pid 28069 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/20.parser/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/20.parser/alpha/tru64/minor-timing - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. - - Reading the dictionary files: ************************************************* - - -Welcome to the Link Parser -- Version 2.1 - - Copyright (C) 1991-1995 Daniel Sleator and Davy Temperley - -Processing sentences in batch mode - -Echoing of input sentence turned on. -* as had expected the party to be a success , it was a success -* do you know where John 's -* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor -* how fast the program is it -* I am wondering whether to invite to the party -* I gave him for his birthday it -* I thought terrible after our discussion -* I wonder how much money have you earned -* Janet who is an expert on dogs helped me choose one -* she interviewed more programmers than was hired -* such flowers are found chiefly particularly in Europe -* the dogs some of which were very large ran after the man -* the man whom I play tennis is here -* there is going to be an important meeting January -* to pretend that our program is usable in its current form would be happy -* we're thinking about going to a movie this theater -* which dog you said you chased -- also invited to the meeting were several prominent scientists -- he ran home so quickly that his mother could hardly believe he had called from school -- so many people attended that they spilled over into several neighboring fields -- voting in favor of the bill were 36 Republicans and 4 moderate Democrats -: Grace may not be possible to fix the problem - any program as good as ours should be useful - biochemically , I think the experiment has a lot of problems - Fred has had five years of experience as a programmer - he is looking for another job - how did John do it - how many more people do you think will come - how much more spilled - I have more money than John has time - I made it clear that I was angry - I wonder how John did it - I wonder how much more quickly he ran - invite John and whoever else you want to invite - it is easier to ignore the problem than it is to solve it - many who initially supported Thomas later changed their minds - neither Mary nor Louise are coming to the party - she interviewed more programmers than were hired - telling Joe that Sue was coming to the party would create a real problem - the man with whom I play tennis is here - there is a dog in the park - this is not the man we know and love - we like to eat at restaurants , usually on weekends - what did John say he thought you should do - about 2 million people attended - the five best costumes got prizes -No errors! -Exiting @ tick 422342506500 because target called exit() diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt --- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,833 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.422343 # Number of seconds simulated -sim_ticks 422342506500 # Number of ticks simulated -final_tick 422342506500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 474436 # Simulator instruction rate (inst/s) -host_op_rate 474436 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 327462122 # Simulator tick rate (ticks/s) -host_mem_usage 257604 # Number of bytes of host memory used -host_seconds 1289.74 # Real time elapsed on the host -sim_insts 611901617 # Number of instructions simulated -sim_ops 611901617 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 422342506500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 156672 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24196288 # Number of bytes read from this memory -system.physmem.bytes_read::total 24352960 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 156672 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 156672 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18839168 # Number of bytes written to this memory -system.physmem.bytes_written::total 18839168 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2448 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 378067 # Number of read requests responded to by this memory -system.physmem.num_reads::total 380515 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 294362 # Number of write requests responded to by this memory -system.physmem.num_writes::total 294362 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 370960 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 57290677 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 57661636 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 370960 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 370960 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 44606374 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 44606374 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 44606374 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 370960 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 57290677 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 102268011 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 380515 # Number of read requests accepted -system.physmem.writeReqs 294362 # Number of write requests accepted -system.physmem.readBursts 380515 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 294362 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24331840 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 21120 # Total number of bytes read from write queue -system.physmem.bytesWritten 18837824 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24352960 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18839168 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 330 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 23759 # Per bank write bursts -system.physmem.perBankRdBursts::1 23180 # Per bank write bursts -system.physmem.perBankRdBursts::2 23498 # Per bank write bursts -system.physmem.perBankRdBursts::3 24625 # Per bank write bursts -system.physmem.perBankRdBursts::4 25498 # Per bank write bursts -system.physmem.perBankRdBursts::5 23629 # Per bank write bursts -system.physmem.perBankRdBursts::6 23701 # Per bank write bursts -system.physmem.perBankRdBursts::7 23987 # Per bank write bursts -system.physmem.perBankRdBursts::8 23227 # Per bank write bursts -system.physmem.perBankRdBursts::9 24022 # Per bank write bursts -system.physmem.perBankRdBursts::10 24752 # Per bank write bursts -system.physmem.perBankRdBursts::11 22836 # Per bank write bursts -system.physmem.perBankRdBursts::12 23786 # Per bank write bursts -system.physmem.perBankRdBursts::13 24450 # Per bank write bursts -system.physmem.perBankRdBursts::14 22762 # Per bank write bursts -system.physmem.perBankRdBursts::15 22473 # Per bank write bursts -system.physmem.perBankWrBursts::0 17837 # Per bank write bursts -system.physmem.perBankWrBursts::1 17476 # Per bank write bursts -system.physmem.perBankWrBursts::2 17996 # Per bank write bursts -system.physmem.perBankWrBursts::3 18950 # Per bank write bursts -system.physmem.perBankWrBursts::4 19553 # Per bank write bursts -system.physmem.perBankWrBursts::5 18644 # Per bank write bursts -system.physmem.perBankWrBursts::6 18825 # Per bank write bursts -system.physmem.perBankWrBursts::7 18731 # Per bank write bursts -system.physmem.perBankWrBursts::8 18487 # Per bank write bursts -system.physmem.perBankWrBursts::9 18977 # Per bank write bursts -system.physmem.perBankWrBursts::10 19288 # Per bank write bursts -system.physmem.perBankWrBursts::11 18104 # Per bank write bursts -system.physmem.perBankWrBursts::12 18331 # Per bank write bursts -system.physmem.perBankWrBursts::13 18778 # Per bank write bursts -system.physmem.perBankWrBursts::14 17209 # Per bank write bursts -system.physmem.perBankWrBursts::15 17155 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 422342412500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 380515 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 294362 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 379040 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1139 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6479 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6849 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 17525 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17560 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17563 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17563 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17562 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17561 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17562 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17562 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17561 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17568 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17565 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17567 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17575 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17580 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17569 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17569 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 138956 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 310.667780 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 185.031528 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 328.663803 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 47467 34.16% 34.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 38428 27.65% 61.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13549 9.75% 71.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 8124 5.85% 77.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5242 3.77% 81.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3828 2.75% 83.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3157 2.27% 86.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2628 1.89% 88.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16533 11.90% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 138956 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17561 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.649109 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 17.965863 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 233.199678 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17556 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 2 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17561 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17561 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.761061 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.733847 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.964147 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 10711 60.99% 60.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 371 2.11% 63.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 6450 36.73% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 26 0.15% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17561 # Writes before turning the bus around for reads -system.physmem.totQLat 8688901500 # Total ticks spent queuing -system.physmem.totMemAccLat 15817370250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1900925000 # Total ticks spent in databus transfers -system.physmem.avgQLat 22854.40 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 41604.40 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 57.61 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 44.60 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 57.66 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 44.61 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.80 # Data bus utilization in percentage -system.physmem.busUtilRead 0.45 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.35 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 20.60 # Average write queue length when enqueuing -system.physmem.readRowHits 314590 # Number of row buffer hits during reads -system.physmem.writeRowHits 220977 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.75 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.07 # Row buffer hit rate for writes -system.physmem.avgGap 625806.50 # Average gap between requests -system.physmem.pageHitRate 79.40 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 505526280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 268693590 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1370001780 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 772622640 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 11362849680.000002 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 8093551410 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 616183200 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 31552584270 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 13412815680 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 73287717855 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 141246410115 # Total energy per rank (pJ) -system.physmem_0.averagePower 334.435695 # Core power per rank (mW) -system.physmem_0.totalIdleTime 402979630750 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 931134000 # Time in different power states -system.physmem_0.memoryStateTime::REF 4824278000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 298856786250 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 34929182250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 13606935500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 69194190500 # Time in different power states -system.physmem_1.actEnergy 486640980 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 258644430 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1344519120 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 763837380 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 10801683360.000002 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 7884425820 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 575860800 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 29572982250 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 12813870240 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 74790220020 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 139297315230 # Total energy per rank (pJ) -system.physmem_1.averagePower 329.820729 # Core power per rank (mW) -system.physmem_1.totalIdleTime 403542198250 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 850086750 # Time in different power states -system.physmem_1.memoryStateTime::REF 4586322000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 305319724750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 33369590750 # Time in different power states -system.physmem_1.memoryStateTime::ACT 13363845750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 64852936500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 422342506500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 124433445 # Number of BP lookups -system.cpu.branchPred.condPredicted 87996604 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6213149 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 71713401 # Number of BTB lookups -system.cpu.branchPred.BTBHits 67452940 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.059045 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 15161931 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1121038 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 7034 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 4431 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 2603 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 736 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 149830728 # DTB read hits -system.cpu.dtb.read_misses 559329 # DTB read misses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 150390057 # DTB read accesses -system.cpu.dtb.write_hits 57603632 # DTB write hits -system.cpu.dtb.write_misses 71396 # DTB write misses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 57675028 # DTB write accesses -system.cpu.dtb.data_hits 207434360 # DTB hits -system.cpu.dtb.data_misses 630725 # DTB misses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 208065085 # DTB accesses -system.cpu.itb.fetch_hits 227956774 # ITB hits -system.cpu.itb.fetch_misses 48 # ITB misses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 227956822 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 485 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 422342506500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 844685013 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 611901617 # Number of instructions committed -system.cpu.committedOps 611901617 # Number of ops (including micro ops) committed -system.cpu.discardedOps 14840042 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.380426 # CPI: cycles per instruction -system.cpu.ipc 0.724414 # IPC: instructions per cycle -system.cpu.op_class_0::No_OpClass 52179272 8.53% 8.53% # Class of committed instruction -system.cpu.op_class_0::IntAlu 355264620 58.06% 66.59% # Class of committed instruction -system.cpu.op_class_0::IntMult 152833 0.02% 66.61% # Class of committed instruction -system.cpu.op_class_0::IntDiv 0 0.00% 66.61% # Class of committed instruction -system.cpu.op_class_0::FloatAdd 144588 0.02% 66.64% # Class of committed instruction -system.cpu.op_class_0::FloatCmp 3 0.00% 66.64% # Class of committed instruction -system.cpu.op_class_0::FloatCvt 369991 0.06% 66.70% # Class of committed instruction -system.cpu.op_class_0::FloatMult 2 0.00% 66.70% # Class of committed instruction -system.cpu.op_class_0::FloatMultAcc 0 0.00% 66.70% # Class of committed instruction -system.cpu.op_class_0::FloatDiv 3790 0.00% 66.70% # Class of committed instruction -system.cpu.op_class_0::FloatMisc 0 0.00% 66.70% # Class of committed instruction -system.cpu.op_class_0::FloatSqrt 0 0.00% 66.70% # Class of committed instruction -system.cpu.op_class_0::SimdAdd 0 0.00% 66.70% # Class of committed instruction -system.cpu.op_class_0::SimdAddAcc 0 0.00% 66.70% # Class of committed instruction -system.cpu.op_class_0::SimdAlu 0 0.00% 66.70% # Class of committed instruction -system.cpu.op_class_0::SimdCmp 0 0.00% 66.70% # Class of committed instruction -system.cpu.op_class_0::SimdCvt 0 0.00% 66.70% # Class of committed instruction -system.cpu.op_class_0::SimdMisc 0 0.00% 66.70% # Class of committed instruction -system.cpu.op_class_0::SimdMult 0 0.00% 66.70% # Class of committed instruction -system.cpu.op_class_0::SimdMultAcc 0 0.00% 66.70% # Class of committed instruction -system.cpu.op_class_0::SimdShift 0 0.00% 66.70% # Class of committed instruction -system.cpu.op_class_0::SimdShiftAcc 0 0.00% 66.70% # Class of committed instruction -system.cpu.op_class_0::SimdSqrt 0 0.00% 66.70% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAdd 0 0.00% 66.70% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAlu 0 0.00% 66.70% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCmp 0 0.00% 66.70% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCvt 0 0.00% 66.70% # Class of committed instruction -system.cpu.op_class_0::SimdFloatDiv 0 0.00% 66.70% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMisc 0 0.00% 66.70% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMult 0 0.00% 66.70% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 66.70% # Class of committed instruction -system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 66.70% # Class of committed instruction -system.cpu.op_class_0::MemRead 146469180 23.94% 90.63% # Class of committed instruction -system.cpu.op_class_0::MemWrite 57213427 9.35% 99.98% # Class of committed instruction -system.cpu.op_class_0::FloatMemRead 96355 0.02% 100.00% # Class of committed instruction -system.cpu.op_class_0::FloatMemWrite 7556 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 611901617 # Class of committed instruction -system.cpu.tickCycles 746838140 # Number of cycles that the object actually ticked -system.cpu.idleCycles 97846873 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 422342506500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2535505 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.585414 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 203187430 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2539601 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 80.007619 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1692948500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.585414 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997946 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997946 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 827 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3149 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 415624517 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 415624517 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 422342506500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 147521210 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 147521210 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 55666220 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 55666220 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 203187430 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 203187430 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 203187430 # number of overall hits -system.cpu.dcache.overall_hits::total 203187430 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1811214 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1811214 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1543814 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1543814 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3355028 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3355028 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3355028 # number of overall misses -system.cpu.dcache.overall_misses::total 3355028 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 39457833000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 39457833000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 51431912500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 51431912500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 90889745500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 90889745500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 90889745500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 90889745500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 149332424 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 149332424 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 57210034 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 57210034 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 206542458 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 206542458 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 206542458 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 206542458 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012129 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012129 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.026985 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.026985 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.016244 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.016244 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.016244 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.016244 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21785.295940 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 21785.295940 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33314.837474 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33314.837474 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 27090.607142 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 27090.607142 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 27090.607142 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 27090.607142 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2339286 # number of writebacks -system.cpu.dcache.writebacks::total 2339286 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 46422 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 46422 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 769005 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 769005 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 815427 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 815427 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 815427 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 815427 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1764792 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1764792 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 774809 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 774809 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2539601 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2539601 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2539601 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2539601 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36307875000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 36307875000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 25218661500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 25218661500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 61526536500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 61526536500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 61526536500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 61526536500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.011818 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.011818 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.013543 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.013543 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012296 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.012296 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012296 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.012296 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20573.458515 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20573.458515 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32548.229951 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32548.229951 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24226.851580 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24226.851580 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24226.851580 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24226.851580 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 422342506500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 3176 # number of replacements -system.cpu.icache.tags.tagsinuse 1116.241776 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 227951769 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 5005 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 45544.808991 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1116.241776 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.545040 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.545040 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1829 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 75 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1592 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.893066 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 455918553 # Number of tag accesses -system.cpu.icache.tags.data_accesses 455918553 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 422342506500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 227951769 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 227951769 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 227951769 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 227951769 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 227951769 # number of overall hits -system.cpu.icache.overall_hits::total 227951769 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5005 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5005 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5005 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5005 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5005 # number of overall misses -system.cpu.icache.overall_misses::total 5005 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 293603500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 293603500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 293603500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 293603500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 293603500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 293603500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 227956774 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 227956774 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 227956774 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 227956774 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 227956774 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 227956774 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58662.037962 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 58662.037962 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 58662.037962 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 58662.037962 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 58662.037962 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 58662.037962 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 3176 # number of writebacks -system.cpu.icache.writebacks::total 3176 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5005 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 5005 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 5005 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 5005 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 5005 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 5005 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 288598500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 288598500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 288598500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 288598500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 288598500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 288598500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 57662.037962 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 57662.037962 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 57662.037962 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 57662.037962 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 57662.037962 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 57662.037962 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 422342506500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 348623 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30598.806406 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4701891 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 381391 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 12.328269 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 70474186000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 42.061592 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 159.646104 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 30397.098711 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.001284 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004872 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.927646 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.933801 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 172 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1626 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 30708 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 41047687 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 41047687 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 422342506500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 2339286 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 2339286 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 3176 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 3176 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 571694 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 571694 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2557 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 2557 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1589840 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1589840 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 2557 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2161534 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2164091 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 2557 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2161534 # number of overall hits -system.cpu.l2cache.overall_hits::total 2164091 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 206458 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 206458 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2448 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 2448 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 171609 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 171609 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2448 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 378067 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 380515 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2448 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 378067 # number of overall misses -system.cpu.l2cache.overall_misses::total 380515 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 18097806000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 18097806000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 254224000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 254224000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 16908659000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 16908659000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 254224000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 35006465000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 35260689000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 254224000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 35006465000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 35260689000 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 2339286 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 2339286 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 3176 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 3176 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 778152 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 778152 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 5005 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 5005 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1761449 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1761449 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 5005 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2539601 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2544606 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 5005 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2539601 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2544606 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.265318 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.265318 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.489111 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.489111 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.097425 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.097425 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.489111 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.148869 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.149538 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.489111 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.148869 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.149538 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 87658.535877 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 87658.535877 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 103849.673203 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 103849.673203 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 98530.141193 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 98530.141193 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 103849.673203 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 92593.283730 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 92665.700432 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 103849.673203 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 92593.283730 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 92665.700432 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 294362 # number of writebacks -system.cpu.l2cache.writebacks::total 294362 # number of writebacks -system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 5 # number of CleanEvict MSHR misses -system.cpu.l2cache.CleanEvict_mshr_misses::total 5 # number of CleanEvict MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206458 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 206458 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2448 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2448 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 171609 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 171609 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2448 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 378067 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 380515 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2448 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 378067 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 380515 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 16033226000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 16033226000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 229744000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 229744000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15192569000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15192569000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 229744000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 31225795000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 31455539000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 229744000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 31225795000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 31455539000 # number of overall MSHR miss cycles -system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.265318 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.265318 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.489111 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.489111 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.097425 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.097425 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.489111 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148869 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.149538 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.489111 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148869 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.149538 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77658.535877 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77658.535877 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 93849.673203 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 93849.673203 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 88530.141193 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 88530.141193 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 93849.673203 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 82593.283730 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 82665.700432 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 93849.673203 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 82593.283730 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 82665.700432 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 5083287 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2538681 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2446 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2446 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 422342506500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 1766454 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2633648 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 3176 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 250480 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 778152 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 778152 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 5005 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1761449 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 13186 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7614707 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7627893 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 523584 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312248768 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 312772352 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 348623 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 18839168 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2893229 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000845 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.029064 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2890783 99.92% 99.92% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 2446 0.08% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2893229 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4884105500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7507500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3809401500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 726697 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 346182 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 422342506500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 174057 # Transaction distribution -system.membus.trans_dist::WritebackDirty 294362 # Transaction distribution -system.membus.trans_dist::CleanEvict 51820 # Transaction distribution -system.membus.trans_dist::ReadExReq 206458 # Transaction distribution -system.membus.trans_dist::ReadExResp 206458 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 174057 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1107212 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1107212 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43192128 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43192128 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 380515 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 380515 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 380515 # Request fanout histogram -system.membus.reqLayer0.occupancy 2021742500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 2013933750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.5 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/30.eon/ref/alpha/tru64/minor-timing/config.ini --- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/config.ini Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,877 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=MinorCPU -children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload -branchPred=system.cpu.branchPred -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -decodeCycleInput=true -decodeInputBufferSize=3 -decodeInputWidth=2 -decodeToExecuteForwardDelay=1 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -enableIdling=true -eventq_index=0 -executeAllowEarlyMemoryIssue=true -executeBranchDelay=1 -executeCommitLimit=2 -executeCycleInput=true -executeFuncUnits=system.cpu.executeFuncUnits -executeInputBufferSize=7 -executeInputWidth=2 -executeIssueLimit=2 -executeLSQMaxStoreBufferStoresPerCycle=2 -executeLSQRequestsQueueSize=1 -executeLSQStoreBufferSize=5 -executeLSQTransfersQueueSize=2 -executeMaxAccessesInMemory=2 -executeMemoryCommitLimit=1 -executeMemoryIssueLimit=1 -executeMemoryWidth=0 -executeSetTraceTimeOnCommit=true -executeSetTraceTimeOnIssue=false -fetch1FetchLimit=1 -fetch1LineSnapWidth=0 -fetch1LineWidth=0 -fetch1ToFetch2BackwardDelay=1 -fetch1ToFetch2ForwardDelay=1 -fetch2CycleInput=true -fetch2InputBufferSize=2 -fetch2ToDecodeForwardDelay=1 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -threadPolicy=RoundRobin -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.branchPred] -type=TournamentBP -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -indirectHashGHR=true -indirectHashTargets=true -indirectPathLength=3 -indirectSets=256 -indirectTagSize=16 -indirectWays=2 -instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 -useIndirect=true - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.executeFuncUnits] -type=MinorFUPool -children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 -eventq_index=0 -funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 - -[system.cpu.executeFuncUnits.funcUnits0] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits0.timings - -[system.cpu.executeFuncUnits.funcUnits0.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntAlu - -[system.cpu.executeFuncUnits.funcUnits0.timings] -type=MinorFUTiming -children=opClasses -description=Int -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits1] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits1.timings - -[system.cpu.executeFuncUnits.funcUnits1.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntAlu - -[system.cpu.executeFuncUnits.funcUnits1.timings] -type=MinorFUTiming -children=opClasses -description=Int -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits2] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits2.timings - -[system.cpu.executeFuncUnits.funcUnits2.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntMult - -[system.cpu.executeFuncUnits.funcUnits2.timings] -type=MinorFUTiming -children=opClasses -description=Mul -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses -srcRegsRelativeLats=0 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits3] -type=MinorFU -children=opClasses -cantForwardFromFUIndices= -eventq_index=0 -issueLat=9 -opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses -opLat=9 -timings= - -[system.cpu.executeFuncUnits.funcUnits3.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntDiv - -[system.cpu.executeFuncUnits.funcUnits4] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses -opLat=6 -timings=system.cpu.executeFuncUnits.funcUnits4.timings - -[system.cpu.executeFuncUnits.funcUnits4.opClasses] -type=MinorOpClassSet -children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] -type=MinorOpClass -eventq_index=0 -opClass=FloatAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01] -type=MinorOpClass -eventq_index=0 -opClass=FloatCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02] -type=MinorOpClass -eventq_index=0 -opClass=FloatCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] -type=MinorOpClass -eventq_index=0 -opClass=FloatMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] -type=MinorOpClass -eventq_index=0 -opClass=FloatDiv - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] -type=MinorOpClass -eventq_index=0 -opClass=FloatSqrt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] -type=MinorOpClass -eventq_index=0 -opClass=SimdAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] -type=MinorOpClass -eventq_index=0 -opClass=SimdAddAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] -type=MinorOpClass -eventq_index=0 -opClass=SimdAlu - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] -type=MinorOpClass -eventq_index=0 -opClass=SimdCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] -type=MinorOpClass -eventq_index=0 -opClass=SimdCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] -type=MinorOpClass -eventq_index=0 -opClass=SimdMisc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] -type=MinorOpClass -eventq_index=0 -opClass=SimdMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] -type=MinorOpClass -eventq_index=0 -opClass=SimdMultAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] -type=MinorOpClass -eventq_index=0 -opClass=SimdShift - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] -type=MinorOpClass -eventq_index=0 -opClass=SimdShiftAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] -type=MinorOpClass -eventq_index=0 -opClass=SimdSqrt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatAlu - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatDiv - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMisc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMultAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatSqrt - -[system.cpu.executeFuncUnits.funcUnits4.timings] -type=MinorFUTiming -children=opClasses -description=FloatSimd -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits5] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses -opLat=1 -timings=system.cpu.executeFuncUnits.funcUnits5.timings - -[system.cpu.executeFuncUnits.funcUnits5.opClasses] -type=MinorOpClassSet -children=opClasses0 opClasses1 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 - -[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] -type=MinorOpClass -eventq_index=0 -opClass=MemRead - -[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] -type=MinorOpClass -eventq_index=0 -opClass=MemWrite - -[system.cpu.executeFuncUnits.funcUnits5.timings] -type=MinorFUTiming -children=opClasses -description=Mem -eventq_index=0 -extraAssumedLat=2 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses -srcRegsRelativeLats=1 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits6] -type=MinorFU -children=opClasses -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses -opLat=1 -timings= - -[system.cpu.executeFuncUnits.funcUnits6.opClasses] -type=MinorOpClassSet -children=opClasses0 opClasses1 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 - -[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] -type=MinorOpClass -eventq_index=0 -opClass=IprAccess - -[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] -type=MinorOpClass -eventq_index=0 -opClass=InstPrefetch - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/minor-timing -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/eon -gid=100 -input=cin -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=0:134217727:0:0:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=6000 -tXPDLL=0 -tXS=270000 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/20.parser/ref/alpha/tru64/minor-timing/config.ini --- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/config.ini Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,877 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=MinorCPU -children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload -branchPred=system.cpu.branchPred -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -decodeCycleInput=true -decodeInputBufferSize=3 -decodeInputWidth=2 -decodeToExecuteForwardDelay=1 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -enableIdling=true -eventq_index=0 -executeAllowEarlyMemoryIssue=true -executeBranchDelay=1 -executeCommitLimit=2 -executeCycleInput=true -executeFuncUnits=system.cpu.executeFuncUnits -executeInputBufferSize=7 -executeInputWidth=2 -executeIssueLimit=2 -executeLSQMaxStoreBufferStoresPerCycle=2 -executeLSQRequestsQueueSize=1 -executeLSQStoreBufferSize=5 -executeLSQTransfersQueueSize=2 -executeMaxAccessesInMemory=2 -executeMemoryCommitLimit=1 -executeMemoryIssueLimit=1 -executeMemoryWidth=0 -executeSetTraceTimeOnCommit=true -executeSetTraceTimeOnIssue=false -fetch1FetchLimit=1 -fetch1LineSnapWidth=0 -fetch1LineWidth=0 -fetch1ToFetch2BackwardDelay=1 -fetch1ToFetch2ForwardDelay=1 -fetch2CycleInput=true -fetch2InputBufferSize=2 -fetch2ToDecodeForwardDelay=1 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -system=system -threadPolicy=RoundRobin -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.branchPred] -type=TournamentBP -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -indirectHashGHR=true -indirectHashTargets=true -indirectPathLength=3 -indirectSets=256 -indirectTagSize=16 -indirectWays=2 -instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 -useIndirect=true - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.executeFuncUnits] -type=MinorFUPool -children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 -eventq_index=0 -funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 - -[system.cpu.executeFuncUnits.funcUnits0] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits0.timings - -[system.cpu.executeFuncUnits.funcUnits0.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntAlu - -[system.cpu.executeFuncUnits.funcUnits0.timings] -type=MinorFUTiming -children=opClasses -description=Int -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits1] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits1.timings - -[system.cpu.executeFuncUnits.funcUnits1.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntAlu - -[system.cpu.executeFuncUnits.funcUnits1.timings] -type=MinorFUTiming -children=opClasses -description=Int -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits2] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses -opLat=3 -timings=system.cpu.executeFuncUnits.funcUnits2.timings - -[system.cpu.executeFuncUnits.funcUnits2.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntMult - -[system.cpu.executeFuncUnits.funcUnits2.timings] -type=MinorFUTiming -children=opClasses -description=Mul -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses -srcRegsRelativeLats=0 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits3] -type=MinorFU -children=opClasses -cantForwardFromFUIndices= -eventq_index=0 -issueLat=9 -opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses -opLat=9 -timings= - -[system.cpu.executeFuncUnits.funcUnits3.opClasses] -type=MinorOpClassSet -children=opClasses -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses - -[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] -type=MinorOpClass -eventq_index=0 -opClass=IntDiv - -[system.cpu.executeFuncUnits.funcUnits4] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses -opLat=6 -timings=system.cpu.executeFuncUnits.funcUnits4.timings - -[system.cpu.executeFuncUnits.funcUnits4.opClasses] -type=MinorOpClassSet -children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] -type=MinorOpClass -eventq_index=0 -opClass=FloatAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01] -type=MinorOpClass -eventq_index=0 -opClass=FloatCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02] -type=MinorOpClass -eventq_index=0 -opClass=FloatCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] -type=MinorOpClass -eventq_index=0 -opClass=FloatMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] -type=MinorOpClass -eventq_index=0 -opClass=FloatDiv - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] -type=MinorOpClass -eventq_index=0 -opClass=FloatSqrt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] -type=MinorOpClass -eventq_index=0 -opClass=SimdAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] -type=MinorOpClass -eventq_index=0 -opClass=SimdAddAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] -type=MinorOpClass -eventq_index=0 -opClass=SimdAlu - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] -type=MinorOpClass -eventq_index=0 -opClass=SimdCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] -type=MinorOpClass -eventq_index=0 -opClass=SimdCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] -type=MinorOpClass -eventq_index=0 -opClass=SimdMisc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] -type=MinorOpClass -eventq_index=0 -opClass=SimdMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] -type=MinorOpClass -eventq_index=0 -opClass=SimdMultAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] -type=MinorOpClass -eventq_index=0 -opClass=SimdShift - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] -type=MinorOpClass -eventq_index=0 -opClass=SimdShiftAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] -type=MinorOpClass -eventq_index=0 -opClass=SimdSqrt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatAdd - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatAlu - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatCmp - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatCvt - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatDiv - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMisc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMult - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatMultAcc - -[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] -type=MinorOpClass -eventq_index=0 -opClass=SimdFloatSqrt - -[system.cpu.executeFuncUnits.funcUnits4.timings] -type=MinorFUTiming -children=opClasses -description=FloatSimd -eventq_index=0 -extraAssumedLat=0 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits4.timings.opClasses -srcRegsRelativeLats=2 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits4.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits5] -type=MinorFU -children=opClasses timings -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses -opLat=1 -timings=system.cpu.executeFuncUnits.funcUnits5.timings - -[system.cpu.executeFuncUnits.funcUnits5.opClasses] -type=MinorOpClassSet -children=opClasses0 opClasses1 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 - -[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] -type=MinorOpClass -eventq_index=0 -opClass=MemRead - -[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1] -type=MinorOpClass -eventq_index=0 -opClass=MemWrite - -[system.cpu.executeFuncUnits.funcUnits5.timings] -type=MinorFUTiming -children=opClasses -description=Mem -eventq_index=0 -extraAssumedLat=2 -extraCommitLat=0 -extraCommitLatExpr=Null -mask=0 -match=0 -opClasses=system.cpu.executeFuncUnits.funcUnits5.timings.opClasses -srcRegsRelativeLats=1 -suppress=false - -[system.cpu.executeFuncUnits.funcUnits5.timings.opClasses] -type=MinorOpClassSet -eventq_index=0 -opClasses= - -[system.cpu.executeFuncUnits.funcUnits6] -type=MinorFU -children=opClasses -cantForwardFromFUIndices= -eventq_index=0 -issueLat=1 -opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses -opLat=1 -timings= - -[system.cpu.executeFuncUnits.funcUnits6.opClasses] -type=MinorOpClassSet -children=opClasses0 opClasses1 -eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1 - -[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0] -type=MinorOpClass -eventq_index=0 -opClass=IprAccess - -[system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1] -type=MinorOpClass -eventq_index=0 -opClass=InstPrefetch - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=parser 2.1.dict -batch -cwd=build/ALPHA/tests/opt/long/se/20.parser/alpha/tru64/minor-timing -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/parser -gid=100 -input=/arm/projectscratch/randd/systems/dist/cpu2000/data/parser/mdred/input/parser.in -kvmInSE=false -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=114600000000 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=0:134217727:0:0:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=6000 -tXPDLL=0 -tXS=270000 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/20.parser/ref/alpha/tru64/minor-timing/simerr --- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/simerr Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,7 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -warn: ignoring syscall sigprocmask(1, ...) diff -r 9c673b990d5d -r e1835e5846b9 tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,108 +0,0 @@ -M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 - Got Configuration 623 - memsize 8000000 pages 4000 - First free page after ROM 0xFFFFFC0000018000 - HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000 - kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x1 - CPU Clock at 2000 MHz IntrClockFrequency=1024 - Booting with 1 processor(s) - KSP: 0x20043FE8 PTBR 0x20 - Console Callback at 0x0, fixup at 0x0, crb offset: 0x510 - Memory cluster 0 [0 - 392] - Memory cluster 1 [392 - 15992] - Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000 - ConsoleDispatch at virt 10000658 phys 18658 val FFFFFC00000100A8 - unix_boot_mem ends at FFFFFC0000076000 - k_argc = 0 - jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067) - CallbackFixup 0 18000, t7=FFFFFC000070C000 - Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006 - Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM - Major Options: SMP LEGACY_START VERBOSE_MCHECK - Command line: root=/dev/hda1 console=ttyS0 - memcluster 0, usage 1, start 0, end 392 - memcluster 1, usage 0, start 392, end 16384 - freeing pages 1069:16384 - reserving pages 1069:1070 - 4096K Bcache detected; load hit latency 30 cycles, load miss latency 167 cycles - SMP: 1 CPUs probed -- cpu_present_mask = 1 - Built 1 zonelists - Kernel command line: root=/dev/hda1 console=ttyS0 - PID hash table entries: 1024 (order: 10, 32768 bytes) - Using epoch = 1900 - Console: colour dummy device 80x25 - Dentry cache hash table entries: 32768 (order: 5, 262144 bytes) - Inode-cache hash table entries: 16384 (order: 4, 131072 bytes) - Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init) - Mount-cache hash table entries: 512 - SMP mode deactivated. - Brought up 1 CPUs - SMP: Total of 1 processors activated (4002.20 BogoMIPS). - NET: Registered protocol family 16 - EISA bus registered - pci: enabling save/restore of SRM state - SCSI subsystem initialized - srm_env: version 0.0.5 loaded successfully - Installing knfsd (copyright (C) 1996 okir@monad.swb.de). - Initializing Cryptographic API - rtc: Standard PC (1900) epoch (1900) detected - Real Time Clock Driver v1.12 - Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled - ttyS0 at I/O 0x3f8 (irq = 4) is a 8250 - io scheduler noop registered - io scheduler anticipatory registered - io scheduler deadline registered - io scheduler cfq registered - loop: loaded (max 8 devices) - nbd: registered device at major 43 - ns83820.c: National Semiconductor DP83820 10/100/1000 driver. - PCI: Setting latency timer of device 0000:00:01.0 to 64 - eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000 - eth0: enabling optical transceiver - eth0: using 64 bit addressing. - eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=h,sg - tun: Universal TUN/TAP device driver, 1.6 - tun: (C) 1999-2004 Max Krasnyansky - Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2 - ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx - PIIX4: IDE controller at PCI slot 0000:00:00.0 - PIIX4: chipset revision 0 - PIIX4: 100% native mode on irq 31 - PCI: Setting latency timer of device 0000:00:00.0 to 64 - ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA - ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA - hda: M5 IDE Disk, ATA DISK drive - hdb: M5 IDE Disk, ATA DISK drive - ide0 at 0x8410-0x8417,0x8422 on irq 31 - hda: max request size: 128KiB - hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33) - hda: cache flushes not supported - hda: hda1 - hdb: max request size: 128KiB - hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33) - hdb: cache flushes not supported - hdb: unknown partition table - mice: PS/2 mouse device common for all mice - NET: Registered protocol family 2 - IP route cache hash table entries: 4096 (order: 2, 32768 bytes) - TCP established hash table entries: 16384 (order: 5, 262144 bytes) - TCP bind hash table entries: 16384 (order: 5, 262144 bytes) - TCP: Hash tables configured (established 16384 bind 16384) - TCP reno registered - ip_conntrack version 2.1 (512 buckets, 4096 max) - 296 bytes per conntrack - ip_tables: (C) 2000-2002 Netfilter core team - arp_tables: (C) 2002 David S. Miller - TCP bic registered - Initializing IPsec netlink socket - NET: Registered protocol family 1 - NET: Registered protocol family 17 - NET: Registered protocol family 15 - Bridge firewalling registered - 802.1Q VLAN Support v1.8 Ben Greear - All bugs added by David S. Miller - VFS: Mounted root (ext2 filesystem) readonly. - Freeing unused kernel memory: 224k freed - init started: BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary -mounting filesystems... -EXT2-fs warning: checktime reached, running e2fsck is recommended - loading script... diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/20.parser/ref/alpha/tru64/NOTE --- a/tests/long/se/20.parser/ref/alpha/tru64/NOTE Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,6 +0,0 @@ -I removed the reference outputs for this program because it's taking -way too long... over an hour for simple-atomic and over 19 hrs for -o3-timing. We need to find a shorter input if we want to keep this -in the regressions. - -Steve diff -r 9c673b990d5d -r e1835e5846b9 tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,6 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Sockets disabled, not accepting terminal connections -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything diff -r 9c673b990d5d -r e1835e5846b9 tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,15 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3/simout -Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:19:44 -gem5 executing on e108600-lin, pid 28053 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/alpha/linux/tsunami-o3 - -Global frequency set at 1000000000000 ticks per second -info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1865011607500 because m5_exit instruction encountered diff -r 9c673b990d5d -r e1835e5846b9 tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,1563 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 1.865012 # Number of seconds simulated -sim_ticks 1865011607500 # Number of ticks simulated -final_tick 1865011607500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 237504 # Simulator instruction rate (inst/s) -host_op_rate 237504 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8362303090 # Simulator tick rate (ticks/s) -host_mem_usage 338380 # Number of bytes of host memory used -host_seconds 223.03 # Real time elapsed on the host -sim_insts 52969539 # Number of instructions simulated -sim_ops 52969539 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 962688 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24879872 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25843520 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 962688 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 962688 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7514368 # Number of bytes written to this memory -system.physmem.bytes_written::total 7514368 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15042 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388748 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 403805 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117412 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117412 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 516183 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13340331 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 515 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13857029 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 516183 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 516183 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4029127 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4029127 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4029127 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 516183 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13340331 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 515 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17886156 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 403805 # Number of read requests accepted -system.physmem.writeReqs 117412 # Number of write requests accepted -system.physmem.readBursts 403805 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 117412 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25836672 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6848 # Total number of bytes read from write queue -system.physmem.bytesWritten 7513280 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25843520 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7514368 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 107 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25445 # Per bank write bursts -system.physmem.perBankRdBursts::1 25617 # Per bank write bursts -system.physmem.perBankRdBursts::2 25496 # Per bank write bursts -system.physmem.perBankRdBursts::3 25620 # Per bank write bursts -system.physmem.perBankRdBursts::4 25117 # Per bank write bursts -system.physmem.perBankRdBursts::5 25178 # Per bank write bursts -system.physmem.perBankRdBursts::6 24740 # Per bank write bursts -system.physmem.perBankRdBursts::7 24558 # Per bank write bursts -system.physmem.perBankRdBursts::8 25032 # Per bank write bursts -system.physmem.perBankRdBursts::9 25302 # Per bank write bursts -system.physmem.perBankRdBursts::10 25290 # Per bank write bursts -system.physmem.perBankRdBursts::11 25006 # Per bank write bursts -system.physmem.perBankRdBursts::12 24377 # Per bank write bursts -system.physmem.perBankRdBursts::13 25425 # Per bank write bursts -system.physmem.perBankRdBursts::14 25800 # Per bank write bursts -system.physmem.perBankRdBursts::15 25695 # Per bank write bursts -system.physmem.perBankWrBursts::0 7802 # Per bank write bursts -system.physmem.perBankWrBursts::1 7592 # Per bank write bursts -system.physmem.perBankWrBursts::2 7774 # Per bank write bursts -system.physmem.perBankWrBursts::3 7602 # Per bank write bursts -system.physmem.perBankWrBursts::4 7239 # Per bank write bursts -system.physmem.perBankWrBursts::5 7182 # Per bank write bursts -system.physmem.perBankWrBursts::6 6741 # Per bank write bursts -system.physmem.perBankWrBursts::7 6416 # Per bank write bursts -system.physmem.perBankWrBursts::8 7149 # Per bank write bursts -system.physmem.perBankWrBursts::9 6926 # Per bank write bursts -system.physmem.perBankWrBursts::10 7200 # Per bank write bursts -system.physmem.perBankWrBursts::11 7003 # Per bank write bursts -system.physmem.perBankWrBursts::12 6957 # Per bank write bursts -system.physmem.perBankWrBursts::13 7880 # Per bank write bursts -system.physmem.perBankWrBursts::14 8017 # Per bank write bursts -system.physmem.perBankWrBursts::15 7915 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 50 # Number of times write queue was full causing retry -system.physmem.totGap 1865006319500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 403805 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 117412 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 314207 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 36490 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 28744 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 24151 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 88 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1450 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2607 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5585 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7310 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7943 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7596 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6918 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6963 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6888 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7091 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5971 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6192 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 746 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 476 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 325 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 301 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 308 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 376 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 400 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 341 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 305 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 305 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 103 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 61234 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 544.625012 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 334.721385 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 417.137572 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13321 21.75% 21.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10685 17.45% 39.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4509 7.36% 46.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2718 4.44% 51.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2169 3.54% 54.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1832 2.99% 57.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1887 3.08% 60.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1551 2.53% 63.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22562 36.85% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 61234 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5157 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 78.280396 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2939.585639 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5154 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5157 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5157 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.764204 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.942160 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 24.363230 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4631 89.80% 89.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 32 0.62% 90.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 183 3.55% 93.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 6 0.12% 94.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 4 0.08% 94.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 9 0.17% 94.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 9 0.17% 94.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 4 0.08% 94.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 32 0.62% 95.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 5 0.10% 95.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 155 3.01% 98.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 14 0.27% 98.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 9 0.17% 98.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 2 0.04% 98.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 9 0.17% 98.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 4 0.08% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 1 0.02% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 2 0.04% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 8 0.16% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 6 0.12% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 10 0.19% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 10 0.19% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 1 0.02% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 1 0.02% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 4 0.08% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 2 0.04% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 2 0.04% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5157 # Writes before turning the bus around for reads -system.physmem.totQLat 7801574500 # Total ticks spent queuing -system.physmem.totMemAccLat 15370912000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2018490000 # Total ticks spent in databus transfers -system.physmem.avgQLat 19325.27 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 38075.27 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.85 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.03 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.86 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 4.03 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.14 # Data bus utilization in percentage -system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.96 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.64 # Average write queue length when enqueuing -system.physmem.readRowHits 364428 # Number of row buffer hits during reads -system.physmem.writeRowHits 95430 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.27 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 81.28 # Row buffer hit rate for writes -system.physmem.avgGap 3578176.31 # Average gap between requests -system.physmem.pageHitRate 88.25 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 214821180 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 114180165 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1440644940 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 304576560 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3637439520.000001 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 4203799590 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 238276320 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 7970182890 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 4260887040 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 438967517640 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 461353182075 # Total energy per rank (pJ) -system.physmem_0.averagePower 247.372821 # Core power per rank (mW) -system.physmem_0.totalIdleTime 1855132089750 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 377139000 # Time in different power states -system.physmem_0.memoryStateTime::REF 1545232000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 1826595828250 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 11096155750 # Time in different power states -system.physmem_0.memoryStateTime::ACT 7918821750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 17478430750 # Time in different power states -system.physmem_1.actEnergy 222396720 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 118202865 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1441758780 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 308225340 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3641127360.000001 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 4165097730 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 227687040 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 8135120370 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 4246672320 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 438904577085 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 461412058890 # Total energy per rank (pJ) -system.physmem_1.averagePower 247.404390 # Core power per rank (mW) -system.physmem_1.totalIdleTime 1855277049250 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 349511250 # Time in different power states -system.physmem_1.memoryStateTime::REF 1546624000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 1826382821500 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 11059060000 # Time in different power states -system.physmem_1.memoryStateTime::ACT 7833171250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 17840419500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 19540652 # Number of BP lookups -system.cpu.branchPred.condPredicted 16609155 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 593501 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 12781935 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5419166 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 42.397071 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1123794 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 42287 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 6265125 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 563559 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 5701566 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 264926 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 11133148 # DTB read hits -system.cpu.dtb.read_misses 49550 # DTB read misses -system.cpu.dtb.read_acv 604 # DTB read access violations -system.cpu.dtb.read_accesses 995639 # DTB read accesses -system.cpu.dtb.write_hits 6779390 # DTB write hits -system.cpu.dtb.write_misses 12217 # DTB write misses -system.cpu.dtb.write_acv 419 # DTB write access violations -system.cpu.dtb.write_accesses 345330 # DTB write accesses -system.cpu.dtb.data_hits 17912538 # DTB hits -system.cpu.dtb.data_misses 61767 # DTB misses -system.cpu.dtb.data_acv 1023 # DTB access violations -system.cpu.dtb.data_accesses 1340969 # DTB accesses -system.cpu.itb.fetch_hits 1814760 # ITB hits -system.cpu.itb.fetch_misses 10379 # ITB misses -system.cpu.itb.fetch_acv 753 # ITB acv -system.cpu.itb.fetch_accesses 1825139 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numPwrStateTransitions 12878 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 6439 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 279577818.217114 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 438970116.286468 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 6439 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::min_value 62000 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 6439 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 64810036000 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 1800201571500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 129626512 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 30190363 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 85695972 # Number of instructions fetch has processed -system.cpu.fetch.Branches 19540652 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 7106519 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 91835709 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1682318 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 61 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 29737 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 207098 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 428060 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 576 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9928105 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 408572 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 123532763 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.693710 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.023135 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 107696719 87.18% 87.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1032377 0.84% 88.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2107068 1.71% 89.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 968796 0.78% 90.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2908740 2.35% 92.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 664008 0.54% 93.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 809572 0.66% 94.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1033225 0.84% 94.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 6312258 5.11% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 123532763 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.150746 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.661099 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 24222797 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 86210181 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 10254650 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2038697 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 806437 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 738100 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 35530 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 74041720 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 113425 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 806437 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 25231796 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 56630169 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 20045874 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 11215615 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 9602870 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 71021126 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 199714 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2114917 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 266619 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 5298821 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 47846131 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 85558708 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 85377795 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 168460 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38170817 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9675306 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1730146 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 277278 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13907871 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 11664536 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 7226725 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1727084 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1123210 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 62712842 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2208202 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 60540114 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 93631 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11951500 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 5299174 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1546957 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 123532763 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.490073 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.235792 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 98992964 80.13% 80.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10407106 8.42% 88.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 4428528 3.58% 92.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 3186499 2.58% 94.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 3245157 2.63% 97.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1605158 1.30% 98.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1098083 0.89% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 432605 0.35% 99.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 136663 0.11% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 123532763 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 207032 16.63% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 1 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 16.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 606591 48.74% 65.37% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 372500 29.93% 95.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 31949 2.57% 97.87% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 26498 2.13% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 7276 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 40915146 67.58% 67.60% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 62152 0.10% 67.70% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 38560 0.06% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.77% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 11521390 19.03% 86.80% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6745321 11.14% 97.94% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 156180 0.26% 98.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 141327 0.23% 98.43% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 949126 1.57% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 60540114 # Type of FU issued -system.cpu.iq.rate 0.467035 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1244571 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.020558 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 245211528 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 76534751 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 58316055 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 739664 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 359442 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 336937 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 61379259 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 398150 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 691177 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2573780 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3893 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 22128 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 849514 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 18020 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 462679 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 806437 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 52697038 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1357053 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 68903527 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 198807 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 11664536 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 7226725 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1959166 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 45872 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1108146 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 22128 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 230653 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 630212 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 860865 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 59685899 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 11215511 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 854214 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3982483 # number of nop insts executed -system.cpu.iew.exec_refs 18027322 # number of memory reference insts executed -system.cpu.iew.exec_branches 9384105 # Number of branches executed -system.cpu.iew.exec_stores 6811811 # Number of stores executed -system.cpu.iew.exec_rate 0.460445 # Inst execution rate -system.cpu.iew.wb_sent 58897557 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 58652992 # cumulative count of insts written-back -system.cpu.iew.wb_producers 29769052 # num instructions producing a value -system.cpu.iew.wb_consumers 41264413 # num instructions consuming a value -system.cpu.iew.wb_rate 0.452477 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.721422 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 12552458 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 661245 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 769809 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 121361631 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.462746 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.395074 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 101505032 83.64% 83.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7973925 6.57% 90.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4190958 3.45% 93.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2263923 1.87% 95.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1758393 1.45% 96.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 630847 0.52% 97.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 481222 0.40% 97.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 521755 0.43% 98.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2035576 1.68% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 121361631 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56159642 # Number of instructions committed -system.cpu.commit.committedOps 56159642 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15467967 # Number of memory references committed -system.cpu.commit.loads 9090756 # Number of loads committed -system.cpu.commit.membars 226364 # Number of memory barriers committed -system.cpu.commit.branches 8439956 # Number of branches committed -system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52009640 # Number of committed integer instructions. -system.cpu.commit.function_calls 740476 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 3197376 5.69% 5.69% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 36210459 64.48% 70.17% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 60672 0.11% 70.28% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 38085 0.07% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 3636 0.01% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 9172524 16.33% 86.69% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 6245101 11.12% 97.81% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemRead 144596 0.26% 98.06% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemWrite 138067 0.25% 98.31% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 949126 1.69% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 56159642 # Class of committed instruction -system.cpu.commit.bw_lim_events 2035576 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 187788618 # The number of ROB reads -system.cpu.rob.rob_writes 139599579 # The number of ROB writes -system.cpu.timesIdled 556181 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 6093749 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3600396704 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52969539 # Number of Instructions Simulated -system.cpu.committedOps 52969539 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.447190 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.447190 # CPI: Total CPI of All Threads -system.cpu.ipc 0.408632 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.408632 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 77875565 # number of integer regfile reads -system.cpu.int_regfile_writes 42594378 # number of integer regfile writes -system.cpu.fp_regfile_reads 166655 # number of floating regfile reads -system.cpu.fp_regfile_writes 175866 # number of floating regfile writes -system.cpu.misc_regfile_reads 2002132 # number of misc regfile reads -system.cpu.misc_regfile_writes 939499 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 1405977 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.994060 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 12626898 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1406489 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.977602 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 28232500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.994060 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999988 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999988 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 414 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 96 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 67141007 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 67141007 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 8018368 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 8018368 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4180367 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4180367 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 212226 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 212226 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 215667 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 215667 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 12198735 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 12198735 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 12198735 # number of overall hits -system.cpu.dcache.overall_hits::total 12198735 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1817070 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1817070 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1966374 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1966374 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 23459 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 23459 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 98 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 98 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3783444 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3783444 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3783444 # number of overall misses -system.cpu.dcache.overall_misses::total 3783444 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 45126424500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 45126424500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 92431305073 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 92431305073 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 416761500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 416761500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 1368500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 1368500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 137557729573 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 137557729573 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 137557729573 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 137557729573 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9835438 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9835438 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6146741 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6146741 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 235685 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 235685 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 215765 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 215765 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15982179 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15982179 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15982179 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15982179 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.184747 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.184747 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.319905 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.319905 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.099535 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.099535 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000454 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000454 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.236729 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.236729 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.236729 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.236729 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24834.719906 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24834.719906 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47005.963806 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 47005.963806 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17765.527090 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17765.527090 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13964.285714 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13964.285714 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 36357.807747 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 36357.807747 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 36357.807747 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 36357.807747 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 4938618 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 4294 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 133157 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 28 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 37.088685 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 153.357143 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 844399 # number of writebacks -system.cpu.dcache.writebacks::total 844399 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 716933 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 716933 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1676859 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1676859 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 6505 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 6505 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2393792 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2393792 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2393792 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2393792 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1100137 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1100137 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289515 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 289515 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16954 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 16954 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 98 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 98 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1389652 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1389652 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1389652 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1389652 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable -system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9599 # number of WriteReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::total 9599 # number of WriteReq MSHR uncacheable -system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16529 # number of overall MSHR uncacheable misses -system.cpu.dcache.overall_mshr_uncacheable_misses::total 16529 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33017901000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 33017901000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14364764991 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 14364764991 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 212848500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 212848500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 1270500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 1270500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47382665991 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 47382665991 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47382665991 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 47382665991 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1535128000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1535128000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1535128000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 1535128000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.111854 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.111854 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047101 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047101 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.071935 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.071935 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000454 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000454 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.086950 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.086950 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.086950 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.086950 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30012.535711 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30012.535711 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49616.651956 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49616.651956 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12554.470921 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12554.470921 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 12964.285714 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 12964.285714 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34096.785376 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 34096.785376 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34096.785376 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 34096.785376 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221519.191919 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221519.191919 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92874.826063 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92874.826063 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1076759 # number of replacements -system.cpu.icache.tags.tagsinuse 509.003606 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 8782144 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1077267 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 8.152245 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 30283847500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.003606 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.994148 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.994148 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 306 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 11005677 # Number of tag accesses -system.cpu.icache.tags.data_accesses 11005677 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 8782144 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8782144 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 8782144 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8782144 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 8782144 # number of overall hits -system.cpu.icache.overall_hits::total 8782144 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1145952 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1145952 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1145952 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1145952 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1145952 # number of overall misses -system.cpu.icache.overall_misses::total 1145952 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16332614990 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16332614990 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16332614990 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16332614990 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16332614990 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16332614990 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9928096 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9928096 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9928096 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9928096 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9928096 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9928096 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.115425 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.115425 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.115425 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.115425 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.115425 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.115425 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14252.442502 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14252.442502 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14252.442502 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14252.442502 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14252.442502 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14252.442502 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 8348 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 326 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 25.607362 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 1076759 # number of writebacks -system.cpu.icache.writebacks::total 1076759 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68371 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 68371 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 68371 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 68371 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 68371 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 68371 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1077581 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1077581 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1077581 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1077581 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1077581 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1077581 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14423902993 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14423902993 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14423902993 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14423902993 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14423902993 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14423902993 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108539 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.108539 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108539 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.108539 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108539 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.108539 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13385.446656 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13385.446656 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13385.446656 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13385.446656 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13385.446656 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13385.446656 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 338614 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65420.353665 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4559964 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 404136 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 11.283241 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 6414398000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 255.266765 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 5296.205124 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 59868.881776 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.003895 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.080814 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.913527 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.998235 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65522 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 896 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 448 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5602 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 58570 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999786 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 40121077 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 40121077 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 844399 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 844399 # number of WritebackDirty hits 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accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.276703 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.162755 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.013966 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.276703 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.162755 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 46500 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 46500 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 104989.919372 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 104989.919372 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 100827.373039 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 100827.373039 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81585.239756 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81585.239756 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 100827.373039 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88484.410008 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 88943.764286 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 100827.373039 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88484.410008 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 88943.764286 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 75900 # number of writebacks -system.cpu.l2cache.writebacks::total 75900 # number of writebacks -system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 9 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 9 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 114725 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 114725 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 15043 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 15043 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 274467 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 274467 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 15043 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 389192 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 404235 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 15043 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 389192 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 404235 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 9599 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.WriteReq_mshr_uncacheable::total 9599 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16529 # number of overall MSHR uncacheable misses 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-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1366325500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 30550733000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 31917058500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1366325500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 30550733000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 31917058500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1448486500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1448486500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1448486500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1448486500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.115385 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.115385 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382415 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382415 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.013965 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.013965 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.248043 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248043 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.013965 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.276703 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.162754 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.013965 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.276703 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.162754 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 36500 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 36500 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 94989.919372 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 94989.919372 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 90827.993086 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 90827.993086 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71604.289405 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71604.289405 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 90827.993086 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78497.844252 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78956.692271 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 90827.993086 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78497.844252 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78956.692271 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 209016.810967 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 209016.810967 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87633.038901 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87633.038901 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 4967024 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2483092 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2362 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 951 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 951 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2191157 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 9599 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 9599 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 920299 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1076759 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 824292 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 78 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 98 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 176 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 300001 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 300001 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1077581 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1106690 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 40 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 237 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3231525 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4252605 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7484130 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 137852416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 144111100 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 281963516 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 339563 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 4892928 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2839828 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.001278 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.035720 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2836200 99.87% 99.87% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3628 0.13% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2839828 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4417734000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 291883 # Layer occupancy (ticks) -system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1617399440 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2121770107 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). -system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. -system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_txs 395 # Number of DMA write transactions. -system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. -system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. -system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 7103 # Transaction distribution -system.iobus.trans_dist::ReadResp 7103 # Transaction distribution -system.iobus.trans_dist::WriteReq 51151 # Transaction distribution -system.iobus.trans_dist::WriteResp 51151 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5054 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33058 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 116508 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20216 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 44156 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2705764 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 5359000 # Layer occupancy (ticks) -system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 816500 # Layer occupancy (ticks) -system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 11000 # Layer occupancy (ticks) -system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) -system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 178500 # Layer occupancy (ticks) -system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 14034000 # Layer occupancy (ticks) -system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 2179500 # Layer occupancy (ticks) -system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 6056500 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 92500 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 216222032 # Layer occupancy (ticks) -system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 23459000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.265413 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1714256790000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.265413 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.079088 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.079088 # Average percentage of cache occupancy -system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id -system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375525 # Number of tag accesses -system.iocache.tags.data_accesses 375525 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses -system.iocache.ReadReq_misses::total 173 # number of ReadReq misses -system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses -system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses -system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses -system.iocache.demand_misses::total 41725 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses -system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21932883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21932883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4939835149 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4939835149 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 4961768032 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4961768032 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 4961768032 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4961768032 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses -system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses -system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses -system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126779.670520 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 126779.670520 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118883.210170 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118883.210170 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 118915.950437 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 118915.950437 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 118915.950437 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 118915.950437 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 2115 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 16 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 132.187500 # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.writebacks::writebacks 41512 # number of writebacks -system.iocache.writebacks::total 41512 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13282883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13282883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2859804565 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2859804565 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 2873087448 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2873087448 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 2873087448 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2873087448 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76779.670520 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 76779.670520 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68824.715176 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68824.715176 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68857.697975 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68857.697975 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68857.697975 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68857.697975 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 825525 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 380458 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 414 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 6930 # Transaction distribution -system.membus.trans_dist::ReadResp 296573 # Transaction distribution -system.membus.trans_dist::WriteReq 9599 # Transaction distribution -system.membus.trans_dist::WriteResp 9599 # Transaction distribution -system.membus.trans_dist::WritebackDirty 117412 # Transaction distribution -system.membus.trans_dist::CleanEvict 262094 # Transaction distribution -system.membus.trans_dist::UpgradeReq 137 # Transaction distribution -system.membus.trans_dist::UpgradeResp 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 114597 # Transaction distribution -system.membus.trans_dist::ReadExResp 114597 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 289683 # Transaction distribution -system.membus.trans_dist::BadAddressError 40 # Transaction distribution -system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33058 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1145815 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 80 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1178953 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1262378 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44156 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30700160 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30744316 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33402044 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 438 # Total snoops (count) -system.membus.snoopTraffic 27840 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 462498 # Request fanout histogram -system.membus.snoop_fanout::mean 0.001464 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.038232 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 461821 99.85% 99.85% # Request fanout histogram -system.membus.snoop_fanout::1 677 0.15% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 462498 # Request fanout histogram -system.membus.reqLayer0.occupancy 28738500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1313413567 # Layer occupancy (ticks) -system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 48500 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2137867250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 917617 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post -system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR -system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post -system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post -system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post -system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post -system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post -system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post -system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post -system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post -system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU -system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1865011607500 # Cumulative time (in ticks) in various power states -system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6439 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211030 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74670 40.97% 40.97% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1881 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105578 57.93% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182260 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73303 49.32% 49.32% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1881 1.27% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73303 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148618 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1819136783500 97.54% 97.54% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 67099500 0.00% 97.54% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 565538000 0.03% 97.57% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 45241360000 2.43% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1865010781000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981693 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694302 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815418 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed -system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed -system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed -system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed -system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed -system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed -system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed -system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed -system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed -system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed -system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed -system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed -system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed -system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed -system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed -system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed -system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed -system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed -system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed -system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed -system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed -system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed -system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed -system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed -system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed -system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed -system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed -system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed -system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed -system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed -system.cpu.kern.syscall::total 326 # number of syscalls executed -system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed -system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed -system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175141 91.22% 93.43% # number of callpals executed -system.cpu.kern.callpal::rdps 6785 3.53% 96.97% # number of callpals executed -system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed -system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed -system.cpu.kern.callpal::rti 5106 2.66% 99.64% # number of callpals executed -system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed -system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 191988 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5852 # number of protection mode switches -system.cpu.kern.mode_switch::user 1738 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1908 -system.cpu.kern.mode_good::user 1738 -system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.326042 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.393971 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29668657000 1.59% 1.59% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2761122500 0.15% 1.74% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1832580993500 98.26% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4177 # number of times the context was actually changed - ----------- End Simulation Statistics ---------- diff -r 9c673b990d5d -r e1835e5846b9 tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,1272 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 1.893221 # Number of seconds simulated -sim_ticks 1893220881500 # Number of ticks simulated -final_tick 1893220881500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 27932 # Simulator instruction rate (inst/s) -host_op_rate 27932 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 941819152 # Simulator tick rate (ticks/s) -host_mem_usage 393408 # Number of bytes of host memory used -host_seconds 2010.17 # Real time elapsed on the host -sim_insts 56147815 # Number of instructions simulated -sim_ops 56147815 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 1046208 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24860800 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25907968 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1046208 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1046208 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7566592 # Number of bytes written to this memory -system.physmem.bytes_written::total 7566592 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 16347 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388450 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 404812 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 118228 # Number of write requests responded to by this memory -system.physmem.num_writes::total 118228 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 552607 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13131484 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 507 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13684599 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 552607 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 552607 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3996677 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3996677 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3996677 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 552607 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13131484 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 507 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17681276 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 404812 # Number of read requests accepted -system.physmem.writeReqs 118228 # Number of write requests accepted -system.physmem.readBursts 404812 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 118228 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25900544 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7424 # Total number of bytes read from write queue -system.physmem.bytesWritten 7565312 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25907968 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7566592 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 116 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25483 # Per bank write bursts -system.physmem.perBankRdBursts::1 25705 # Per bank write bursts -system.physmem.perBankRdBursts::2 25813 # Per bank write bursts -system.physmem.perBankRdBursts::3 25775 # Per bank write bursts -system.physmem.perBankRdBursts::4 25223 # Per bank write bursts -system.physmem.perBankRdBursts::5 24955 # Per bank write bursts -system.physmem.perBankRdBursts::6 24789 # Per bank write bursts -system.physmem.perBankRdBursts::7 24583 # Per bank write bursts -system.physmem.perBankRdBursts::8 25108 # Per bank write bursts -system.physmem.perBankRdBursts::9 25258 # Per bank write bursts -system.physmem.perBankRdBursts::10 25518 # Per bank write bursts -system.physmem.perBankRdBursts::11 24875 # Per bank write bursts -system.physmem.perBankRdBursts::12 24528 # Per bank write bursts -system.physmem.perBankRdBursts::13 25564 # Per bank write bursts -system.physmem.perBankRdBursts::14 25798 # Per bank write bursts -system.physmem.perBankRdBursts::15 25721 # Per bank write bursts -system.physmem.perBankWrBursts::0 7829 # Per bank write bursts -system.physmem.perBankWrBursts::1 7671 # Per bank write bursts -system.physmem.perBankWrBursts::2 8071 # Per bank write bursts -system.physmem.perBankWrBursts::3 7745 # Per bank write bursts -system.physmem.perBankWrBursts::4 7318 # Per bank write bursts -system.physmem.perBankWrBursts::5 6944 # Per bank write bursts -system.physmem.perBankWrBursts::6 6788 # Per bank write bursts -system.physmem.perBankWrBursts::7 6427 # Per bank write bursts -system.physmem.perBankWrBursts::8 7237 # Per bank write bursts -system.physmem.perBankWrBursts::9 6873 # Per bank write bursts -system.physmem.perBankWrBursts::10 7386 # Per bank write bursts -system.physmem.perBankWrBursts::11 6888 # Per bank write bursts -system.physmem.perBankWrBursts::12 7081 # Per bank write bursts -system.physmem.perBankWrBursts::13 8010 # Per bank write bursts -system.physmem.perBankWrBursts::14 7995 # Per bank write bursts -system.physmem.perBankWrBursts::15 7945 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 68 # Number of times write queue was full causing retry -system.physmem.totGap 1893211891000 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 404812 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 118228 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 402391 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2236 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 57 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2487 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5523 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5674 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7340 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6034 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5819 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 428 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 418 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 332 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 341 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 369 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 345 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 274 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 227 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 192 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 329 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 399 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 169 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 63319 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 528.527867 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 322.547536 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 413.556682 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14397 22.74% 22.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11107 17.54% 40.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4705 7.43% 47.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3113 4.92% 52.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2233 3.53% 56.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2328 3.68% 59.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1953 3.08% 62.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1598 2.52% 65.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 21885 34.56% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 63319 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5233 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 77.334798 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2918.735904 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5230 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5233 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5233 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.588955 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.741886 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 24.816216 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4718 90.16% 90.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 33 0.63% 90.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 174 3.33% 94.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 5 0.10% 94.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 3 0.06% 94.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 12 0.23% 94.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 8 0.15% 94.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 1 0.02% 94.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 32 0.61% 95.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 4 0.08% 95.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 151 2.89% 98.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 15 0.29% 98.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 10 0.19% 98.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 2 0.04% 98.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 6 0.11% 98.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 3 0.06% 98.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 3 0.06% 98.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 1 0.02% 99.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 10 0.19% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 6 0.11% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 12 0.23% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 9 0.17% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 1 0.02% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 5 0.10% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 4 0.08% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 3 0.06% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-279 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5233 # Writes before turning the bus around for reads -system.physmem.totQLat 5895300250 # Total ticks spent queuing -system.physmem.totMemAccLat 13483350250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2023480000 # Total ticks spent in databus transfers -system.physmem.avgQLat 14567.23 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 33317.23 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.68 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.68 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 4.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.14 # Data bus utilization in percentage -system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.81 # Average write queue length when enqueuing -system.physmem.readRowHits 363810 # Number of row buffer hits during reads -system.physmem.writeRowHits 95775 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.90 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 81.01 # Row buffer hit rate for writes -system.physmem.avgGap 3619631.18 # Average gap between requests -system.physmem.pageHitRate 87.89 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 221882640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 117933420 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1444607640 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 306899460 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 4693391040.000001 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 4737017490 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 303974400 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 10896307530 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 5550083520 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 443242644240 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 471515616450 # Total energy per rank (pJ) -system.physmem_0.averagePower 249.054730 # Core power per rank (mW) -system.physmem_0.totalIdleTime 1881921702000 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 481983250 # Time in different power states -system.physmem_0.memoryStateTime::REF 1993748000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 1843690402750 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 14453321750 # Time in different power states -system.physmem_0.memoryStateTime::ACT 8706248250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 23895177500 # Time in different power states -system.physmem_1.actEnergy 230215020 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 122362185 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1444921800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 310146300 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 4816933680.000001 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 4925461770 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 303573120 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 11119407240 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 5660238720 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 442986687510 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 471921610125 # Total energy per rank (pJ) -system.physmem_1.averagePower 249.269176 # Core power per rank (mW) -system.physmem_1.totalIdleTime 1881622925500 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 484393500 # Time in different power states -system.physmem_1.memoryStateTime::REF 2046440000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 1842500290250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 14740166500 # Time in different power states -system.physmem_1.memoryStateTime::ACT 9065047000 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 24384544250 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 15264339 # Number of BP lookups -system.cpu.branchPred.condPredicted 13122374 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 525708 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 12102111 # Number of BTB lookups -system.cpu.branchPred.BTBHits 4571092 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 37.771030 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 863726 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 33596 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 6525159 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 541190 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 5983969 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 222121 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9321681 # DTB read hits -system.cpu.dtb.read_misses 17691 # DTB read misses -system.cpu.dtb.read_acv 211 # DTB read access violations -system.cpu.dtb.read_accesses 764795 # DTB read accesses -system.cpu.dtb.write_hits 6394158 # DTB write hits -system.cpu.dtb.write_misses 2442 # DTB write misses -system.cpu.dtb.write_acv 159 # DTB write access violations -system.cpu.dtb.write_accesses 298776 # DTB write accesses -system.cpu.dtb.data_hits 15715839 # DTB hits -system.cpu.dtb.data_misses 20133 # DTB misses -system.cpu.dtb.data_acv 370 # DTB access violations -system.cpu.dtb.data_accesses 1063571 # DTB accesses -system.cpu.itb.fetch_hits 4020046 # ITB hits -system.cpu.itb.fetch_misses 6280 # ITB misses -system.cpu.itb.fetch_acv 699 # ITB acv -system.cpu.itb.fetch_accesses 4026326 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numPwrStateTransitions 12752 # Number of power state transitions -system.cpu.pwrStateClkGateDist::samples 6376 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 281786440.323087 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 439974345.162947 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::1000-5e+10 6376 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::min_value 369000 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::total 6376 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 96550538000 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 1796670343500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 193121889 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56147815 # Number of instructions committed -system.cpu.committedOps 56147815 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2978612 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 6376 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 3593319874 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 3.439526 # CPI: cycles per instruction -system.cpu.ipc 0.290738 # IPC: instructions per cycle -system.cpu.op_class_0::No_OpClass 3199269 5.70% 5.70% # Class of committed instruction -system.cpu.op_class_0::IntAlu 36201024 64.47% 70.17% # Class of committed instruction -system.cpu.op_class_0::IntMult 60831 0.11% 70.28% # Class of committed instruction -system.cpu.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction -system.cpu.op_class_0::FloatAdd 38079 0.07% 70.35% # Class of committed instruction -system.cpu.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::FloatMultAcc 0 0.00% 70.35% # Class of committed instruction -system.cpu.op_class_0::FloatDiv 3636 0.01% 70.36% # Class of committed instruction -system.cpu.op_class_0::FloatMisc 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::FloatSqrt 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdAdd 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdAddAcc 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdAlu 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdCmp 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdCvt 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdMisc 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdMult 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdMultAcc 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdShift 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdShiftAcc 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdSqrt 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAdd 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAlu 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCmp 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCvt 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdFloatDiv 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMisc 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMult 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 70.36% # Class of committed instruction -system.cpu.op_class_0::MemRead 9175906 16.34% 86.70% # Class of committed instruction -system.cpu.op_class_0::MemWrite 6235361 11.11% 97.80% # Class of committed instruction -system.cpu.op_class_0::FloatMemRead 144497 0.26% 98.06% # Class of committed instruction -system.cpu.op_class_0::FloatMemWrite 137980 0.25% 98.31% # Class of committed instruction -system.cpu.op_class_0::IprAccess 951232 1.69% 100.00% # Class of committed instruction -system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 56147815 # Class of committed instruction -system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211531 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74800 40.93% 40.93% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 131 0.07% 41.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1905 1.04% 42.05% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105905 57.95% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182741 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73433 49.32% 49.32% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1905 1.28% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73433 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148902 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1837683771000 97.07% 97.07% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 86162500 0.00% 97.07% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 712688000 0.04% 97.11% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 54737244500 2.89% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1893219866000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981725 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.693386 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814825 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed -system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed -system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed -system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed -system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed -system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed -system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed -system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed -system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed -system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed -system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed -system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed -system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed -system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed -system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed -system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed -system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed -system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed -system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed -system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed -system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed -system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed -system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed -system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed -system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed -system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed -system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed -system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed -system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed -system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed -system.cpu.kern.syscall::total 326 # number of syscalls executed -system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4173 2.17% 2.17% # number of callpals executed -system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed -system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175574 91.22% 93.43% # number of callpals executed -system.cpu.kern.callpal::rdps 6808 3.54% 96.96% # number of callpals executed -system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::rti 5130 2.67% 99.64% # number of callpals executed -system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed -system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192465 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5875 # number of protection mode switches -system.cpu.kern.mode_switch::user 1737 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1905 -system.cpu.kern.mode_good::user 1737 -system.cpu.kern.mode_good::idle 168 -system.cpu.kern.mode_switch_good::kernel 0.324255 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080229 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392541 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 37297482500 1.97% 1.97% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 4311459500 0.23% 2.20% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1851610914000 97.80% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4174 # number of times the context was actually changed -system.cpu.tickCycles 85352026 # Number of cycles that the object actually ticked -system.cpu.idleCycles 107769863 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 1394246 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.980074 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 13946627 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1394758 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 9.999317 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 99338500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.980074 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999961 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999961 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 225 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 219 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63927104 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63927104 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 7985415 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7985415 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5578562 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5578562 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183593 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183593 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199022 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199022 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13563977 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13563977 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13563977 # number of overall hits -system.cpu.dcache.overall_hits::total 13563977 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1096352 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1096352 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 573692 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 573692 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 16450 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 16450 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1670044 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1670044 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1670044 # number of overall misses -system.cpu.dcache.overall_misses::total 1670044 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 33571810000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 33571810000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 25337965000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 25337965000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 222587500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 222587500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 58909775000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 58909775000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 58909775000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 58909775000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9081767 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9081767 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6152254 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6152254 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200043 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200043 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 199022 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199022 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15234021 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15234021 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15234021 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15234021 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120720 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120720 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093249 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.093249 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.082232 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.082232 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.109626 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.109626 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.109626 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.109626 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30621.378900 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 30621.378900 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44166.495262 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 44166.495262 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13531.155015 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13531.155015 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 35274.384986 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 35274.384986 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 35274.384986 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 35274.384986 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 837664 # number of writebacks -system.cpu.dcache.writebacks::total 837664 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21993 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 21993 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 269693 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 269693 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 291686 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 291686 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 291686 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 291686 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074359 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1074359 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 303999 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 303999 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 16447 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 16447 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1378358 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1378358 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1378358 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1378358 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 6930 # number of ReadReq MSHR uncacheable -system.cpu.dcache.ReadReq_mshr_uncacheable::total 6930 # number of ReadReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9623 # number of WriteReq MSHR uncacheable -system.cpu.dcache.WriteReq_mshr_uncacheable::total 9623 # number of WriteReq MSHR uncacheable -system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16553 # number of overall MSHR uncacheable misses -system.cpu.dcache.overall_mshr_uncacheable_misses::total 16553 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32011150000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 32011150000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12927980000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12927980000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 205437000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 205437000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 44939130000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 44939130000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 44939130000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 44939130000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1534184500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1534184500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 1534184500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 1534184500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.118298 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.118298 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049413 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049413 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.082217 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.082217 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090479 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.090479 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090479 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.090479 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29795.580434 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29795.580434 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42526.389889 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42526.389889 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12490.849395 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12490.849395 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 32603.380254 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 32603.380254 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32603.380254 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 32603.380254 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 221383.044733 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221383.044733 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92683.169214 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92683.169214 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1477105 # number of replacements -system.cpu.icache.tags.tagsinuse 509.256263 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 19233040 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1477616 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 13.016264 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 36168250500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.256263 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.994641 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.994641 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 400 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 22188623 # 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14005.091048 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14005.091048 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14005.091048 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14005.091048 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14005.091048 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 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miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13005.091048 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13005.091048 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13005.091048 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13005.091048 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13005.091048 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 339628 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65408.612363 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 5336325 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 405150 # Sample count of references to valid blocks. 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-system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16553 # number of overall MSHR uncacheable misses -system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16553 # number of overall MSHR uncacheable misses -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 271000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 271000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9332571500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9332571500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1455004000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1455004000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19244147500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19244147500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1455004000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 28576719000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 30031723000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1455004000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 28576719000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 30031723000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1447540500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1447540500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 1447540500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 1447540500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.285714 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.285714 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383711 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383711 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.011063 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.011063 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.249571 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249571 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011063 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278809 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.141070 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011063 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278809 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.141070 # mshr miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 45166.666667 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 45166.666667 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80003.527586 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80003.527586 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 89001.957426 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 89001.957426 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70691.805706 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70691.805706 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 89001.957426 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73485.049296 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 74111.046675 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 89001.957426 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73485.049296 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 74111.046675 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 208880.303030 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 208880.303030 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 87448.831028 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 87448.831028 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 5743946 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2871549 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1963 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 999 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 999 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 6930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2575626 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 9623 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 9623 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 914380 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1477105 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 819494 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 21 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 21 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304010 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304010 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1477790 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1090934 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 24 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 242 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4432629 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4217118 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8649747 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 189109696 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142929468 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 332039164 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 340242 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 4923392 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 3229178 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000972 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.031158 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 3226040 99.90% 99.90% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3138 0.10% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3229178 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5199830000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 291883 # Layer occupancy (ticks) -system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2216814740 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2103909988 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). -system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. -system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_txs 395 # Number of DMA write transactions. -system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. -system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. -system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 7103 # Transaction distribution -system.iobus.trans_dist::ReadResp 7103 # Transaction distribution -system.iobus.trans_dist::WriteReq 51175 # Transaction distribution -system.iobus.trans_dist::WriteResp 51175 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33106 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 116556 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20408 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 44348 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2705956 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 5417000 # Layer occupancy (ticks) -system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 803500 # Layer occupancy (ticks) -system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 10500 # Layer occupancy (ticks) -system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) -system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 180500 # Layer occupancy (ticks) -system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 15637500 # Layer occupancy (ticks) -system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 2305500 # Layer occupancy (ticks) -system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 6005000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 90500 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 216245035 # Layer occupancy (ticks) -system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 23483000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.299106 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1735874546000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.299106 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.081194 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.081194 # Average percentage of cache occupancy -system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id -system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375525 # Number of tag accesses -system.iocache.tags.data_accesses 375525 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses -system.iocache.ReadReq_misses::total 173 # number of ReadReq misses -system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses -system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses -system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses -system.iocache.demand_misses::total 41725 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses -system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 22024383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 22024383 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4948308652 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4948308652 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 4970333035 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4970333035 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 4970333035 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4970333035 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses -system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses -system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses -system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 127308.572254 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 127308.572254 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 119087.135445 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 119087.135445 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 119121.223128 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 119121.223128 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 119121.223128 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 119121.223128 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 1402 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 13 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 107.846154 # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.writebacks::writebacks 41512 # number of writebacks -system.iocache.writebacks::total 41512 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13374383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13374383 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2868251757 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2868251757 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 2881626140 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2881626140 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 2881626140 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2881626140 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 77308.572254 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 77308.572254 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 69028.007244 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69028.007244 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 69062.340084 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 69062.340084 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 69062.340084 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 69062.340084 # average overall mshr miss latency -system.membus.snoop_filter.tot_requests 827498 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 381477 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 410 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 6930 # Transaction distribution -system.membus.trans_dist::ReadResp 295653 # Transaction distribution -system.membus.trans_dist::WriteReq 9623 # Transaction distribution -system.membus.trans_dist::WriteResp 9623 # Transaction distribution -system.membus.trans_dist::WritebackDirty 118228 # Transaction distribution -system.membus.trans_dist::CleanEvict 262245 # Transaction distribution -system.membus.trans_dist::UpgradeReq 138 # Transaction distribution -system.membus.trans_dist::UpgradeResp 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 116520 # Transaction distribution -system.membus.trans_dist::ReadExResp 116520 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 288747 # Transaction distribution -system.membus.trans_dist::BadAddressError 24 # Transaction distribution -system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33106 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1148793 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 48 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1181947 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83425 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 83425 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1265372 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44348 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30816832 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30861180 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2657728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2657728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33518908 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 434 # Total snoops (count) -system.membus.snoopTraffic 27584 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 463510 # Request fanout histogram -system.membus.snoop_fanout::mean 0.001463 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.038218 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 462832 99.85% 99.85% # Request fanout histogram -system.membus.snoop_fanout::1 678 0.15% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 463510 # Request fanout histogram -system.membus.reqLayer0.occupancy 30461000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1319556082 # Layer occupancy (ticks) -system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 30000 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2160064000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 943117 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post -system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR -system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post -system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post -system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post -system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post -system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post -system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post -system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post -system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post -system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU -system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states -system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1893220881500 # Cumulative time (in ticks) in various power states - ----------- End Simulation Statistics ---------- diff -r 9c673b990d5d -r e1835e5846b9 tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/system.terminal --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/system.terminal Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,108 +0,0 @@ -M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 - Got Configuration 623 - memsize 8000000 pages 4000 - First free page after ROM 0xFFFFFC0000018000 - HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000 - kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x1 - CPU Clock at 2000 MHz IntrClockFrequency=1024 - Booting with 1 processor(s) - KSP: 0x20043FE8 PTBR 0x20 - Console Callback at 0x0, fixup at 0x0, crb offset: 0x510 - Memory cluster 0 [0 - 392] - Memory cluster 1 [392 - 15992] - Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000 - ConsoleDispatch at virt 10000658 phys 18658 val FFFFFC00000100A8 - unix_boot_mem ends at FFFFFC0000076000 - k_argc = 0 - jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067) - CallbackFixup 0 18000, t7=FFFFFC000070C000 - Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006 - Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM - Major Options: SMP LEGACY_START VERBOSE_MCHECK - Command line: root=/dev/hda1 console=ttyS0 - memcluster 0, usage 1, start 0, end 392 - memcluster 1, usage 0, start 392, end 16384 - freeing pages 1069:16384 - reserving pages 1069:1070 - 4096K Bcache detected; load hit latency 30 cycles, load miss latency 167 cycles - SMP: 1 CPUs probed -- cpu_present_mask = 1 - Built 1 zonelists - Kernel command line: root=/dev/hda1 console=ttyS0 - PID hash table entries: 1024 (order: 10, 32768 bytes) - Using epoch = 1900 - Console: colour dummy device 80x25 - Dentry cache hash table entries: 32768 (order: 5, 262144 bytes) - Inode-cache hash table entries: 16384 (order: 4, 131072 bytes) - Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init) - Mount-cache hash table entries: 512 - SMP mode deactivated. - Brought up 1 CPUs - SMP: Total of 1 processors activated (4002.20 BogoMIPS). - NET: Registered protocol family 16 - EISA bus registered - pci: enabling save/restore of SRM state - SCSI subsystem initialized - srm_env: version 0.0.5 loaded successfully - Installing knfsd (copyright (C) 1996 okir@monad.swb.de). - Initializing Cryptographic API - rtc: Standard PC (1900) epoch (1900) detected - Real Time Clock Driver v1.12 - Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled - ttyS0 at I/O 0x3f8 (irq = 4) is a 8250 - io scheduler noop registered - io scheduler anticipatory registered - io scheduler deadline registered - io scheduler cfq registered - loop: loaded (max 8 devices) - nbd: registered device at major 43 - ns83820.c: National Semiconductor DP83820 10/100/1000 driver. - PCI: Setting latency timer of device 0000:00:01.0 to 64 - eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000 - eth0: enabling optical transceiver - eth0: using 64 bit addressing. - eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=h,sg - tun: Universal TUN/TAP device driver, 1.6 - tun: (C) 1999-2004 Max Krasnyansky - Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2 - ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx - PIIX4: IDE controller at PCI slot 0000:00:00.0 - PIIX4: chipset revision 0 - PIIX4: 100% native mode on irq 31 - PCI: Setting latency timer of device 0000:00:00.0 to 64 - ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA - ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA - hda: M5 IDE Disk, ATA DISK drive - hdb: M5 IDE Disk, ATA DISK drive - ide0 at 0x8410-0x8417,0x8422 on irq 31 - hda: max request size: 128KiB - hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33) - hda: cache flushes not supported - hda: hda1 - hdb: max request size: 128KiB - hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33) - hdb: cache flushes not supported - hdb: unknown partition table - mice: PS/2 mouse device common for all mice - NET: Registered protocol family 2 - IP route cache hash table entries: 4096 (order: 2, 32768 bytes) - TCP established hash table entries: 16384 (order: 5, 262144 bytes) - TCP bind hash table entries: 16384 (order: 5, 262144 bytes) - TCP: Hash tables configured (established 16384 bind 16384) - TCP reno registered - ip_conntrack version 2.1 (512 buckets, 4096 max) - 296 bytes per conntrack - ip_tables: (C) 2000-2002 Netfilter core team - arp_tables: (C) 2002 David S. Miller - TCP bic registered - Initializing IPsec netlink socket - NET: Registered protocol family 1 - NET: Registered protocol family 17 - NET: Registered protocol family 15 - Bridge firewalling registered - 802.1Q VLAN Support v1.8 Ben Greear - All bugs added by David S. Miller - VFS: Mounted root (ext2 filesystem) readonly. - Freeing unused kernel memory: 224k freed - init started: BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary -mounting filesystems... -EXT2-fs warning: checktime reached, running e2fsck is recommended - loading script... diff -r 9c673b990d5d -r e1835e5846b9 tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,2271 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=true -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=LinuxAlphaSystem -children=bridge clk_domain cpu0 cpu1 cpu_clk_domain disk0 disk2 dvfs_handler intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami voltage_domain -boot_cpu_frequency=500 -boot_osflags=root=/dev/hda1 console=ttyS0 -cache_line_size=64 -clk_domain=system.clk_domain -console=/arm/projectscratch/randd/systems/dist/binaries/console -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges=0:134217727:0:0:0:0 -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pal=/arm/projectscratch/randd/systems/dist/binaries/ts_osfpal -power_model=Null -readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh -symbolfile= -system_rev=1024 -system_type=34 -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.bridge] -type=Bridge -clk_domain=system.clk_domain -default_p_state=UNDEFINED -delay=50000 -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -ranges=8796093022208:18446744073709551615:0:0:0:0 -req_size=16 -resp_size=16 -master=system.iobus.slave[0] -slave=system.membus.master[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu0] -type=DerivO3CPU -children=branchPred dcache dtb fuPool icache interrupts isa itb tracer -LFSTSize=1024 -LQEntries=32 -LSQCheckLoads=true -LSQDepCheckShift=4 -SQEntries=32 -SSITSize=1024 -activity=0 -backComSize=5 -branchPred=system.cpu0.branchPred -cachePorts=200 -checker=Null -clk_domain=system.cpu_clk_domain -commitToDecodeDelay=1 -commitToFetchDelay=1 -commitToIEWDelay=1 -commitToRenameDelay=1 -commitWidth=8 -cpu_id=0 -decodeToFetchDelay=1 -decodeToRenameDelay=1 -decodeWidth=8 -default_p_state=UNDEFINED -dispatchWidth=8 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu0.dtb -eventq_index=0 -fetchBufferSize=64 -fetchQueueSize=32 -fetchToDecodeDelay=1 -fetchTrapLatency=1 -fetchWidth=8 -forwardComSize=5 -fuPool=system.cpu0.fuPool -function_trace=false -function_trace_start=0 -iewToCommitDelay=1 -iewToDecodeDelay=1 -iewToFetchDelay=1 -iewToRenameDelay=1 -interrupts=system.cpu0.interrupts -isa=system.cpu0.isa -issueToExecuteDelay=1 -issueWidth=8 -itb=system.cpu0.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -needsTSO=false -numIQEntries=64 -numPhysCCRegs=0 -numPhysFloatRegs=256 -numPhysIntRegs=256 -numROBEntries=192 -numRobs=1 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -renameToDecodeDelay=1 -renameToFetchDelay=1 -renameToIEWDelay=2 -renameToROBDelay=1 -renameWidth=8 -simpoint_start_insts= -smtCommitPolicy=RoundRobin -smtFetchPolicy=SingleThread -smtIQPolicy=Partitioned -smtIQThreshold=100 -smtLSQPolicy=Partitioned -smtLSQThreshold=100 -smtNumFetchingThreads=1 -smtROBPolicy=Partitioned -smtROBThreshold=100 -socket_id=0 -squashWidth=8 -store_set_clear_period=250000 -switched_out=false -system=system -tracer=system.cpu0.tracer -trapLatency=13 -wbWidth=8 -workload= -dcache_port=system.cpu0.dcache.cpu_side -icache_port=system.cpu0.icache.cpu_side - -[system.cpu0.branchPred] -type=TournamentBP -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -indirectHashGHR=true -indirectHashTargets=true -indirectPathLength=3 -indirectSets=256 -indirectTagSize=16 -indirectWays=2 -instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 -useIndirect=true - -[system.cpu0.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=4 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu0.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu0.dcache_port -mem_side=system.toL2Bus.slave[1] - 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-[system.cpu1.fuPool.FUList5.opList00] -type=OpDesc -eventq_index=0 -opClass=SimdAdd -opLat=1 -pipelined=true - -[system.cpu1.fuPool.FUList5.opList01] -type=OpDesc -eventq_index=0 -opClass=SimdAddAcc -opLat=1 -pipelined=true - -[system.cpu1.fuPool.FUList5.opList02] -type=OpDesc -eventq_index=0 -opClass=SimdAlu -opLat=1 -pipelined=true - -[system.cpu1.fuPool.FUList5.opList03] -type=OpDesc -eventq_index=0 -opClass=SimdCmp -opLat=1 -pipelined=true - -[system.cpu1.fuPool.FUList5.opList04] -type=OpDesc -eventq_index=0 -opClass=SimdCvt -opLat=1 -pipelined=true - -[system.cpu1.fuPool.FUList5.opList05] -type=OpDesc -eventq_index=0 -opClass=SimdMisc -opLat=1 -pipelined=true - -[system.cpu1.fuPool.FUList5.opList06] -type=OpDesc -eventq_index=0 -opClass=SimdMult -opLat=1 -pipelined=true - -[system.cpu1.fuPool.FUList5.opList07] -type=OpDesc -eventq_index=0 -opClass=SimdMultAcc -opLat=1 -pipelined=true - -[system.cpu1.fuPool.FUList5.opList08] -type=OpDesc -eventq_index=0 -opClass=SimdShift -opLat=1 -pipelined=true - -[system.cpu1.fuPool.FUList5.opList09] -type=OpDesc -eventq_index=0 -opClass=SimdShiftAcc -opLat=1 -pipelined=true - -[system.cpu1.fuPool.FUList5.opList10] -type=OpDesc -eventq_index=0 -opClass=SimdSqrt -opLat=1 -pipelined=true - -[system.cpu1.fuPool.FUList5.opList11] -type=OpDesc -eventq_index=0 -opClass=SimdFloatAdd -opLat=1 -pipelined=true - -[system.cpu1.fuPool.FUList5.opList12] -type=OpDesc -eventq_index=0 -opClass=SimdFloatAlu -opLat=1 -pipelined=true - -[system.cpu1.fuPool.FUList5.opList13] -type=OpDesc -eventq_index=0 -opClass=SimdFloatCmp -opLat=1 -pipelined=true - -[system.cpu1.fuPool.FUList5.opList14] -type=OpDesc -eventq_index=0 -opClass=SimdFloatCvt -opLat=1 -pipelined=true - -[system.cpu1.fuPool.FUList5.opList15] -type=OpDesc -eventq_index=0 -opClass=SimdFloatDiv -opLat=1 -pipelined=true - -[system.cpu1.fuPool.FUList5.opList16] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMisc -opLat=1 -pipelined=true - -[system.cpu1.fuPool.FUList5.opList17] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMult -opLat=1 -pipelined=true - -[system.cpu1.fuPool.FUList5.opList18] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMultAcc -opLat=1 -pipelined=true - -[system.cpu1.fuPool.FUList5.opList19] -type=OpDesc -eventq_index=0 -opClass=SimdFloatSqrt -opLat=1 -pipelined=true - -[system.cpu1.fuPool.FUList6] -type=FUDesc -children=opList -count=0 -eventq_index=0 -opList=system.cpu1.fuPool.FUList6.opList - -[system.cpu1.fuPool.FUList6.opList] -type=OpDesc -eventq_index=0 -opClass=MemWrite -opLat=1 -pipelined=true - -[system.cpu1.fuPool.FUList7] -type=FUDesc -children=opList0 opList1 -count=4 -eventq_index=0 -opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 - -[system.cpu1.fuPool.FUList7.opList0] -type=OpDesc -eventq_index=0 -opClass=MemRead -opLat=1 -pipelined=true - -[system.cpu1.fuPool.FUList7.opList1] -type=OpDesc -eventq_index=0 -opClass=MemWrite -opLat=1 -pipelined=true - -[system.cpu1.fuPool.FUList8] -type=FUDesc -children=opList -count=1 -eventq_index=0 -opList=system.cpu1.fuPool.FUList8.opList - -[system.cpu1.fuPool.FUList8.opList] -type=OpDesc -eventq_index=0 -opClass=IprAccess -opLat=3 -pipelined=false - -[system.cpu1.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=1 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu1.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu1.icache_port -mem_side=system.toL2Bus.slave[2] - -[system.cpu1.icache.tags] -type=LRU -assoc=1 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu1.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu1.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu1.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu1.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.disk0] -type=IdeDisk -children=image -delay=1000000 -driveID=master -eventq_index=0 -image=system.disk0.image - -[system.disk0.image] -type=CowDiskImage -children=child -child=system.disk0.image.child -eventq_index=0 -image_file= -read_only=false -table_size=65536 - -[system.disk0.image.child] -type=RawDiskImage -eventq_index=0 -image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img -read_only=true - -[system.disk2] -type=IdeDisk -children=image -delay=1000000 -driveID=master -eventq_index=0 -image=system.disk2.image - -[system.disk2.image] -type=CowDiskImage -children=child -child=system.disk2.image.child -eventq_index=0 -image_file= -read_only=false -table_size=65536 - -[system.disk2.image.child] -type=RawDiskImage -eventq_index=0 -image_file=/arm/projectscratch/randd/systems/dist/disks/linux-bigswap2.img -read_only=true - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.intrctrl] -type=IntrControl -eventq_index=0 -sys=system - -[system.iobus] -type=NoncoherentXBar -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=1 -frontend_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -response_latency=2 -use_default_range=false -width=16 -master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side -slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma - -[system.iocache] -type=Cache -children=tags -addr_ranges=0:134217727:0:0:0:0 -assoc=8 -clk_domain=system.clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=50 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=50 -sequential_access=false -size=1024 -system=system -tags=system.iocache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.iobus.master[27] -mem_side=system.membus.slave[2] - -[system.iocache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=50 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=1024 - -[system.l2c] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=4194304 -system=system -tags=system.l2c.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.l2c.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=4194304 - -[system.membus] -type=CoherentXBar -children=badaddr_responder snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.physmem.port -slave=system.system_port system.l2c.mem_side system.iocache.mem_side - -[system.membus.badaddr_responder] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=0 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=true -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.membus.default - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=0:134217727:0:0:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=6000 -tXPDLL=0 -tXS=270000 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[1] - -[system.simple_disk] -type=SimpleDisk -children=disk -disk=system.simple_disk.disk -eventq_index=0 -system=system - -[system.simple_disk.disk] -type=RawDiskImage -eventq_index=0 -image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img -read_only=true - -[system.terminal] -type=Terminal -eventq_index=0 -intr_control=system.intrctrl -number=0 -output=true -port=3456 - -[system.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.l2c.cpu_side -slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side - -[system.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.tsunami] -type=Tsunami -children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip uart -eventq_index=0 -intrctrl=system.intrctrl -system=system - -[system.tsunami.backdoor] -type=AlphaBackdoor -clk_domain=system.clk_domain -cpu=system.cpu0 -default_p_state=UNDEFINED -disk=system.simple_disk -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804682956800 -pio_latency=100000 -platform=system.tsunami -power_model=Null -system=system -terminal=system.terminal -pio=system.iobus.master[24] - -[system.tsunami.cchip] -type=TsunamiCChip -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8803072344064 -pio_latency=100000 -power_model=Null -system=system -tsunami=system.tsunami -pio=system.iobus.master[0] - -[system.tsunami.ethernet] -type=NSGigE -BAR0=1 -BAR0LegacyIO=false -BAR0Size=256 -BAR1=0 -BAR1LegacyIO=false -BAR1Size=4096 -BAR2=0 -BAR2LegacyIO=false -BAR2Size=0 -BAR3=0 -BAR3LegacyIO=false -BAR3Size=0 -BAR4=0 -BAR4LegacyIO=false -BAR4Size=0 -BAR5=0 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=2 -Command=0 -DeviceID=34 -ExpansionROM=0 -HeaderType=0 -InterruptLine=30 -InterruptPin=1 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=52 -MinimumGrant=176 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=0 -Revision=0 -Status=656 -SubClassCode=0 -SubsystemID=0 -SubsystemVendorID=0 -VendorID=4107 -clk_domain=system.clk_domain -config_latency=20000 -default_p_state=UNDEFINED -dma_data_free=false -dma_desc_free=false -dma_no_allocate=true -dma_read_delay=0 -dma_read_factor=0 -dma_write_delay=0 -dma_write_factor=0 -eventq_index=0 -hardware_address=00:90:00:00:00:01 -host=system.tsunami.pchip -intr_delay=10000000 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_bus=0 -pci_dev=1 -pci_func=0 -pio_latency=30000 -power_model=Null -rss=false -rx_delay=1000000 -rx_fifo_size=524288 -rx_filter=true -rx_thread=false -system=system -tx_delay=1000000 -tx_fifo_size=524288 -tx_thread=false -dma=system.iobus.slave[2] -pio=system.iobus.master[26] - -[system.tsunami.fake_OROM] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8796093677568 -pio_latency=100000 -pio_size=393216 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[8] - -[system.tsunami.fake_ata0] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848432 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[19] - -[system.tsunami.fake_ata1] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848304 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[20] - -[system.tsunami.fake_pnp_addr] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848569 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[9] - -[system.tsunami.fake_pnp_read0] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848451 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[11] - -[system.tsunami.fake_pnp_read1] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848515 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[12] - -[system.tsunami.fake_pnp_read2] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848579 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[13] - -[system.tsunami.fake_pnp_read3] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848643 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[14] - -[system.tsunami.fake_pnp_read4] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848707 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[15] - -[system.tsunami.fake_pnp_read5] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848771 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[16] - -[system.tsunami.fake_pnp_read6] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848835 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[17] - -[system.tsunami.fake_pnp_read7] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848899 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[18] - -[system.tsunami.fake_pnp_write] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615850617 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[10] - -[system.tsunami.fake_ppc] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848891 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[7] - -[system.tsunami.fake_sm_chip] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848816 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[2] - -[system.tsunami.fake_uart1] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848696 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[3] - -[system.tsunami.fake_uart2] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848936 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[4] - -[system.tsunami.fake_uart3] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848680 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[5] - -[system.tsunami.fake_uart4] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848944 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[6] - -[system.tsunami.fb] -type=BadDevice -clk_domain=system.clk_domain -default_p_state=UNDEFINED -devicename=FrameBuffer -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848912 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[21] - -[system.tsunami.ide] -type=IdeController -BAR0=1 -BAR0LegacyIO=false -BAR0Size=8 -BAR1=1 -BAR1LegacyIO=false -BAR1Size=4 -BAR2=1 -BAR2LegacyIO=false -BAR2Size=8 -BAR3=1 -BAR3LegacyIO=false -BAR3Size=4 -BAR4=1 -BAR4LegacyIO=false -BAR4Size=16 -BAR5=1 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=1 -Command=0 -DeviceID=28945 -ExpansionROM=0 -HeaderType=0 -InterruptLine=31 -InterruptPin=1 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=0 -MinimumGrant=0 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=133 -Revision=0 -Status=640 -SubClassCode=1 -SubsystemID=0 -SubsystemVendorID=0 -VendorID=32902 -clk_domain=system.clk_domain -config_latency=20000 -ctrl_offset=0 -default_p_state=UNDEFINED -disks=system.disk0 system.disk2 -eventq_index=0 -host=system.tsunami.pchip -io_shift=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_bus=0 -pci_dev=0 -pci_func=0 -pio_latency=30000 -power_model=Null -system=system -dma=system.iobus.slave[1] -pio=system.iobus.master[25] - -[system.tsunami.io] -type=TsunamiIO -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -frequency=976562500 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615847936 -pio_latency=100000 -power_model=Null -system=system -time=Thu Jan 1 00:00:00 2009 -tsunami=system.tsunami -year_is_bcd=false -pio=system.iobus.master[22] - -[system.tsunami.pchip] -type=TsunamiPChip -clk_domain=system.clk_domain -conf_base=8804649402368 -conf_device_bits=8 -conf_size=16777216 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_dma_base=0 -pci_mem_base=8796093022208 -pci_pio_base=8804615847936 -pio_addr=8802535473152 -pio_latency=100000 -platform=system.tsunami -power_model=Null -system=system -tsunami=system.tsunami -pio=system.iobus.master[1] - -[system.tsunami.uart] -type=Uart8250 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848952 -pio_latency=100000 -platform=system.tsunami -power_model=Null -system=system -terminal=system.terminal -pio=system.iobus.master[23] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff -r 9c673b990d5d -r e1835e5846b9 tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,7 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Sockets disabled, not accepting terminal connections -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything diff -r 9c673b990d5d -r e1835e5846b9 tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,16 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual/simout -Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:19:46 -gem5 executing on e108600-lin, pid 28085 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual - -Global frequency set at 1000000000000 ticks per second -info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -info: Entering event queue @ 0. Starting simulation... -info: Launching CPU 1 @ 133768500 -Exiting @ tick 1907549438500 because m5_exit instruction encountered diff -r 9c673b990d5d -r e1835e5846b9 tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,2396 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 1.907549 # Number of seconds simulated -sim_ticks 1907549438500 # Number of ticks simulated -final_tick 1907549438500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 238870 # Simulator instruction rate (inst/s) -host_op_rate 238870 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8039623402 # Simulator tick rate (ticks/s) -host_mem_usage 342472 # Number of bytes of host memory used -host_seconds 237.27 # Real time elapsed on the host -sim_insts 56676315 # Number of instructions simulated -sim_ops 56676315 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.inst 857728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24440448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 121088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 888256 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26308480 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 857728 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 121088 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 978816 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7911424 # Number of bytes written to this memory -system.physmem.bytes_written::total 7911424 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13402 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 381882 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1892 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 13879 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 411070 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 123616 # Number of write requests responded to by this memory -system.physmem.num_writes::total 123616 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 449649 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12812485 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 63478 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 465653 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 503 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13791768 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 449649 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 63478 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 513127 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4147428 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4147428 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4147428 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 449649 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12812485 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 63478 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 465653 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 503 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17939196 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 411070 # Number of read requests accepted -system.physmem.writeReqs 123616 # Number of write requests accepted -system.physmem.readBursts 411070 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 123616 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26300288 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8192 # Total number of bytes read from write queue -system.physmem.bytesWritten 7909696 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26308480 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7911424 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 128 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 26240 # Per bank write bursts -system.physmem.perBankRdBursts::1 25986 # Per bank write bursts -system.physmem.perBankRdBursts::2 25958 # Per bank write bursts -system.physmem.perBankRdBursts::3 25690 # Per bank write bursts -system.physmem.perBankRdBursts::4 25582 # Per bank write bursts -system.physmem.perBankRdBursts::5 25570 # Per bank write bursts -system.physmem.perBankRdBursts::6 25628 # Per bank write bursts -system.physmem.perBankRdBursts::7 25343 # Per bank write bursts -system.physmem.perBankRdBursts::8 25590 # Per bank write bursts -system.physmem.perBankRdBursts::9 25698 # Per bank write bursts -system.physmem.perBankRdBursts::10 25929 # Per bank write bursts -system.physmem.perBankRdBursts::11 25525 # Per bank write bursts -system.physmem.perBankRdBursts::12 26076 # Per bank write bursts -system.physmem.perBankRdBursts::13 25420 # Per bank write bursts -system.physmem.perBankRdBursts::14 25099 # Per bank write bursts -system.physmem.perBankRdBursts::15 25608 # Per bank write bursts -system.physmem.perBankWrBursts::0 8587 # Per bank write bursts -system.physmem.perBankWrBursts::1 8090 # Per bank write bursts -system.physmem.perBankWrBursts::2 7940 # Per bank write bursts -system.physmem.perBankWrBursts::3 7436 # Per bank write bursts -system.physmem.perBankWrBursts::4 7275 # Per bank write bursts -system.physmem.perBankWrBursts::5 7415 # Per bank write bursts -system.physmem.perBankWrBursts::6 7544 # Per bank write bursts -system.physmem.perBankWrBursts::7 7156 # Per bank write bursts -system.physmem.perBankWrBursts::8 7532 # Per bank write bursts -system.physmem.perBankWrBursts::9 7639 # Per bank write bursts -system.physmem.perBankWrBursts::10 7820 # Per bank write bursts -system.physmem.perBankWrBursts::11 7739 # Per bank write bursts -system.physmem.perBankWrBursts::12 8260 # Per bank write bursts -system.physmem.perBankWrBursts::13 7848 # Per bank write bursts -system.physmem.perBankWrBursts::14 7518 # Per bank write bursts -system.physmem.perBankWrBursts::15 7790 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 73 # Number of times write queue was full causing retry -system.physmem.totGap 1907545081500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 411070 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 123616 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 316681 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 38865 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 30168 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 25023 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 157 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1506 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2688 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4408 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6666 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7521 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8639 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7738 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7919 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7524 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6711 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 778 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 552 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 357 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 289 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 340 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 374 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 376 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 270 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 412 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 360 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 442 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 187 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64388 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 531.308940 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 323.701196 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 416.289256 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14473 22.48% 22.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11513 17.88% 40.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5038 7.82% 48.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2819 4.38% 52.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2271 3.53% 56.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1853 2.88% 58.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1969 3.06% 62.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1608 2.50% 64.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22844 35.48% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64388 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5502 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 74.686478 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2827.616380 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5499 99.95% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5502 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5502 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.462559 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.761271 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 24.372868 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4982 90.55% 90.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 39 0.71% 91.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 171 3.11% 94.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 6 0.11% 94.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 5 0.09% 94.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 13 0.24% 94.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 3 0.05% 94.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 6 0.11% 94.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 29 0.53% 95.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 6 0.11% 95.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 149 2.71% 98.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 8 0.15% 98.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 14 0.25% 98.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 3 0.05% 98.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 12 0.22% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 2 0.04% 99.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 1 0.02% 99.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 1 0.02% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 2 0.04% 99.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 11 0.20% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 6 0.11% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 14 0.25% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 3 0.05% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 1 0.02% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 8 0.15% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 5 0.09% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5502 # Writes before turning the bus around for reads -system.physmem.totQLat 8174654750 # Total ticks spent queuing -system.physmem.totMemAccLat 15879817250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2054710000 # Total ticks spent in databus transfers -system.physmem.avgQLat 19892.48 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 38642.48 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.79 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.15 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.79 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 4.15 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.14 # Data bus utilization in percentage -system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.34 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.44 # Average write queue length when enqueuing -system.physmem.readRowHits 370634 # Number of row buffer hits during reads -system.physmem.writeRowHits 99508 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.19 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.50 # Row buffer hit rate for writes -system.physmem.avgGap 3567598.71 # Average gap between requests -system.physmem.pageHitRate 87.95 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 229108320 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 121773960 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1470818580 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 320732460 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3850104960.000001 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 4304249550 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 244489440 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 8392475940 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 4645539360 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 448697608680 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 472278008880 # Total energy per rank (pJ) -system.physmem_0.averagePower 247.583627 # Core power per rank (mW) -system.physmem_0.totalIdleTime 1897458465500 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 385946750 # Time in different power states -system.physmem_0.memoryStateTime::REF 1635552000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 1866968885000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 12097849250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 8056520750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 18404684750 # Time in different power states -system.physmem_1.actEnergy 230629140 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 122578500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1463307300 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 324402120 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3763440720.000001 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 4252821870 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 240122400 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 8356841250 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 4387202880 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 448891199505 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 472033988085 # Total energy per rank (pJ) -system.physmem_1.averagePower 247.455703 # Core power per rank (mW) -system.physmem_1.totalIdleTime 1897589722250 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 380622500 # Time in different power states -system.physmem_1.memoryStateTime::REF 1598754000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 1867843123750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 11424948500 # Time in different power states -system.physmem_1.memoryStateTime::ACT 7975953750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 18326036000 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.cpu0.branchPred.lookups 16746871 # Number of BP lookups -system.cpu0.branchPred.condPredicted 14324468 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 462281 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 10727156 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 4756454 # Number of BTB hits -system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 44.340308 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 926491 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 34071 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 5119287 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 497756 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 4621531 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 206577 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dtb.fetch_hits 0 # ITB hits -system.cpu0.dtb.fetch_misses 0 # ITB misses -system.cpu0.dtb.fetch_acv 0 # ITB acv -system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 9412979 # DTB read hits -system.cpu0.dtb.read_misses 34328 # DTB read misses -system.cpu0.dtb.read_acv 621 # DTB read access violations -system.cpu0.dtb.read_accesses 567042 # DTB read accesses -system.cpu0.dtb.write_hits 5709982 # DTB write hits -system.cpu0.dtb.write_misses 8326 # DTB write misses -system.cpu0.dtb.write_acv 453 # DTB write access violations -system.cpu0.dtb.write_accesses 184750 # DTB write accesses -system.cpu0.dtb.data_hits 15122961 # DTB hits -system.cpu0.dtb.data_misses 42654 # DTB misses -system.cpu0.dtb.data_acv 1074 # DTB access violations -system.cpu0.dtb.data_accesses 751792 # DTB accesses -system.cpu0.itb.fetch_hits 1307701 # ITB hits -system.cpu0.itb.fetch_misses 6903 # ITB misses -system.cpu0.itb.fetch_acv 605 # ITB acv -system.cpu0.itb.fetch_accesses 1314604 # ITB accesses -system.cpu0.itb.read_hits 0 # DTB read hits -system.cpu0.itb.read_misses 0 # DTB read misses -system.cpu0.itb.read_acv 0 # DTB read access violations -system.cpu0.itb.read_accesses 0 # DTB read accesses -system.cpu0.itb.write_hits 0 # DTB write hits -system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.write_acv 0 # DTB write access violations -system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.data_hits 0 # DTB hits -system.cpu0.itb.data_misses 0 # DTB misses -system.cpu0.itb.data_acv 0 # DTB access violations -system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numPwrStateTransitions 12949 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 6475 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 285376318.378378 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 440714536.369915 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 6475 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 79500 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 6475 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 59737777000 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 1847811661500 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 119482029 # number of cpu cycles simulated -system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 25760123 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 73391497 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 16746871 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6180701 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 86881424 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1333696 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 1 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 31404 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 137910 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 424032 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 391 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 8451225 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 316387 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 113902133 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.644338 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.954525 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 100270966 88.03% 88.03% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 886228 0.78% 88.81% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1867927 1.64% 90.45% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 772028 0.68% 91.13% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2612142 2.29% 93.42% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 579506 0.51% 93.93% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 682297 0.60% 94.53% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 834861 0.73% 95.26% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 5396178 4.74% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 113902133 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.140162 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.614247 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 20705856 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 82013409 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 8738075 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1805880 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 638912 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 611998 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 28528 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 63750944 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 85334 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 638912 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 21566893 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 55682864 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 17571842 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9616135 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 8825485 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 61313705 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 198555 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 2000786 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 244905 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 4945993 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 41348673 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 74029068 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 73897769 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 122571 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 33810397 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 7538276 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1420468 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 230583 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 12282803 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9801073 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6065767 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1438850 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 936003 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 54214575 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1853218 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 52616152 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 74253 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 9353064 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 4027640 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1289091 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 113902133 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.461942 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.202978 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 92500805 81.21% 81.21% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 9147500 8.03% 89.24% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3821730 3.36% 92.60% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2743420 2.41% 95.01% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2859412 2.51% 97.52% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1408857 1.24% 98.75% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 945269 0.83% 99.58% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 359735 0.32% 99.90% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 115405 0.10% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 113902133 # Number of insts issued each cycle -system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 168885 16.81% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMultAcc 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMisc 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 16.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 486832 48.47% 65.28% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 300564 29.92% 95.20% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMemRead 26620 2.65% 97.85% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMemWrite 21571 2.15% 100.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 2537 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 36110587 68.63% 68.64% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 55774 0.11% 68.74% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.74% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 25398 0.05% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMultAcc 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1267 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMisc 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.79% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9721676 18.48% 87.27% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5686986 10.81% 98.08% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMemRead 122455 0.23% 98.31% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMemWrite 110756 0.21% 98.52% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 778716 1.48% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 52616152 # Type of FU issued -system.cpu0.iq.rate 0.440369 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1004472 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.019091 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 219643746 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 65164078 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 50897823 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 569416 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 274599 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 257683 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 53310020 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 308067 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 606515 # Number of loads that had data forwarded from stores -system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1936563 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 4258 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 18275 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 663361 # Number of stores squashed -system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18355 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 359900 # Number of times an access to memory failed due to the cache being blocked -system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 638912 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 52175649 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 1047801 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 59607584 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 159494 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9801073 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6065767 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1641866 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 39898 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 807337 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 18275 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 179860 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 504304 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 684164 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 51934418 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9472740 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 681734 # Number of squashed instructions skipped in execute -system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3539791 # number of nop insts executed -system.cpu0.iew.exec_refs 15207952 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8258466 # Number of branches executed -system.cpu0.iew.exec_stores 5735212 # Number of stores executed -system.cpu0.iew.exec_rate 0.434663 # Inst execution rate -system.cpu0.iew.wb_sent 51337506 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 51155506 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 26224773 # num instructions producing a value -system.cpu0.iew.wb_consumers 36250862 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.428144 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.723425 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 9849450 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 564127 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 611071 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 112190301 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.442089 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.364280 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 94635636 84.35% 84.35% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6985533 6.23% 90.58% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 3776917 3.37% 93.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2005568 1.79% 95.73% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1565673 1.40% 97.13% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 565948 0.50% 97.63% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 418764 0.37% 98.01% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 453132 0.40% 98.41% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1783130 1.59% 100.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 112190301 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 49598051 # Number of instructions committed -system.cpu0.commit.committedOps 49598051 # Number of ops (including micro ops) committed -system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13266916 # Number of memory references committed -system.cpu0.commit.loads 7864510 # Number of loads committed -system.cpu0.commit.membars 192309 # Number of memory barriers committed -system.cpu0.commit.branches 7509354 # Number of branches committed -system.cpu0.commit.fp_insts 248727 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 45907115 # Number of committed integer instructions. -system.cpu0.commit.function_calls 632192 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 2885858 5.82% 5.82% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 32387672 65.30% 71.12% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 54445 0.11% 71.23% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 71.23% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 24929 0.05% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMultAcc 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 1267 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMisc 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.28% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 7943636 16.02% 87.30% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 5298998 10.68% 97.98% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMemRead 113183 0.23% 98.21% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMemWrite 109348 0.22% 98.43% # Class of committed instruction -system.cpu0.commit.op_class_0::IprAccess 778715 1.57% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 49598051 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1783130 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 169680194 # The number of ROB reads -system.cpu0.rob.rob_writes 120607262 # The number of ROB writes -system.cpu0.timesIdled 481372 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 5579896 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3694980588 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 46714728 # Number of Instructions Simulated -system.cpu0.committedOps 46714728 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 2.557695 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.557695 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.390977 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.390977 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 68002622 # number of integer regfile reads -system.cpu0.int_regfile_writes 37262146 # number of integer regfile writes -system.cpu0.fp_regfile_reads 121389 # number of floating regfile reads -system.cpu0.fp_regfile_writes 130195 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1657828 # number of misc regfile reads -system.cpu0.misc_regfile_writes 782201 # number of misc regfile writes -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 1253317 # number of replacements -system.cpu0.dcache.tags.tagsinuse 506.016530 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 10648438 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1253753 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 8.493250 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 28164500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.016530 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988314 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.988314 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 436 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 414 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 22 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.851562 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 56881554 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 56881554 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 6768789 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6768789 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3521179 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3521179 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 174329 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 174329 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 179913 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 179913 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10289968 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10289968 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10289968 # number of overall hits -system.cpu0.dcache.overall_hits::total 10289968 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1553170 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1553170 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1684058 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1684058 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20354 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 20354 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 3039 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 3039 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3237228 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3237228 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3237228 # number of overall misses -system.cpu0.dcache.overall_misses::total 3237228 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 41477053500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 41477053500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 85173031211 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 85173031211 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 394024000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 394024000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 17098500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 17098500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 126650084711 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 126650084711 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 126650084711 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 126650084711 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8321959 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8321959 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5205237 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5205237 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 194683 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 194683 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 182952 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 182952 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13527196 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 13527196 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13527196 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 13527196 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.186635 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.186635 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.323531 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.323531 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.104549 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.104549 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.016611 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.016611 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.239313 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.239313 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.239313 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.239313 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26704.773785 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 26704.773785 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50576.067577 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 50576.067577 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 19358.553601 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 19358.553601 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5626.357354 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5626.357354 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39123.004222 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 39123.004222 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39123.004222 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 39123.004222 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 4484825 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 6096 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 108156 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 130 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 41.466262 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 46.892308 # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 737739 # number of writebacks -system.cpu0.dcache.writebacks::total 737739 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 551343 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 551343 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1432280 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1432280 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5686 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5686 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1983623 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1983623 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1983623 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1983623 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1001827 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1001827 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251778 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 251778 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 14668 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 14668 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 3039 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 3039 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1253605 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1253605 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1253605 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1253605 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 6977 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 6977 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 9906 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 9906 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 16883 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 16883 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 31605979000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 31605979000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 13230681248 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 13230681248 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 170838000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 170838000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 14059500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 14059500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 44836660248 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 44836660248 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 44836660248 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 44836660248 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1556905500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1556905500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1556905500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1556905500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.120384 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.120384 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048370 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048370 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.075343 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.075343 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.016611 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.016611 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092673 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.092673 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092673 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.092673 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 31548.340182 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 31548.340182 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 52548.996529 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 52548.996529 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11646.986638 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11646.986638 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4626.357354 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4626.357354 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35766.178539 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35766.178539 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35766.178539 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35766.178539 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 223148.272897 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223148.272897 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 92217.348812 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 92217.348812 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 894430 # number of replacements -system.cpu0.icache.tags.tagsinuse 509.352767 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 7502081 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 894941 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 8.382766 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 30333693500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.352767 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994830 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.994830 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 501 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 9346457 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 9346457 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 7502081 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 7502081 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 7502081 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 7502081 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 7502081 # number of overall hits -system.cpu0.icache.overall_hits::total 7502081 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 949140 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 949140 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 949140 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 949140 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 949140 # number of overall misses -system.cpu0.icache.overall_misses::total 949140 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13882658989 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 13882658989 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 13882658989 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 13882658989 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 13882658989 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13882658989 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 8451221 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 8451221 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 8451221 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 8451221 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 8451221 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 8451221 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.112308 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.112308 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.112308 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.112308 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.112308 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.112308 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14626.566143 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14626.566143 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14626.566143 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14626.566143 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14626.566143 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14626.566143 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 6715 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 267 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 25.149813 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 894430 # number of writebacks -system.cpu0.icache.writebacks::total 894430 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 53904 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 53904 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 53904 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 53904 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 53904 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 53904 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 895236 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 895236 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 895236 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 895236 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 895236 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 895236 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12277660991 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 12277660991 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12277660991 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 12277660991 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12277660991 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 12277660991 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.105930 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.105930 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.105930 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.105930 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.105930 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.105930 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13714.440651 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13714.440651 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13714.440651 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13714.440651 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13714.440651 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13714.440651 # average overall mshr miss latency -system.cpu1.branchPred.lookups 4438770 # Number of BP lookups -system.cpu1.branchPred.condPredicted 3818546 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 113828 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 2325021 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 880835 # Number of BTB hits -system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 37.885034 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 228893 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 8586 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 1265295 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 163281 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 1102014 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 40695 # Number of mispredicted indirect branches. -system.cpu1.dtb.fetch_hits 0 # ITB hits -system.cpu1.dtb.fetch_misses 0 # ITB misses -system.cpu1.dtb.fetch_acv 0 # ITB acv -system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2431495 # DTB read hits -system.cpu1.dtb.read_misses 15697 # DTB read misses -system.cpu1.dtb.read_acv 126 # DTB read access violations -system.cpu1.dtb.read_accesses 432376 # DTB read accesses -system.cpu1.dtb.write_hits 1439190 # DTB write hits -system.cpu1.dtb.write_misses 3913 # DTB write misses -system.cpu1.dtb.write_acv 68 # DTB write access violations -system.cpu1.dtb.write_accesses 163232 # DTB write accesses -system.cpu1.dtb.data_hits 3870685 # DTB hits -system.cpu1.dtb.data_misses 19610 # DTB misses -system.cpu1.dtb.data_acv 194 # DTB access violations -system.cpu1.dtb.data_accesses 595608 # DTB accesses -system.cpu1.itb.fetch_hits 677547 # ITB hits -system.cpu1.itb.fetch_misses 3477 # ITB misses -system.cpu1.itb.fetch_acv 144 # ITB acv -system.cpu1.itb.fetch_accesses 681024 # ITB accesses -system.cpu1.itb.read_hits 0 # DTB read hits -system.cpu1.itb.read_misses 0 # DTB read misses -system.cpu1.itb.read_acv 0 # DTB read access violations -system.cpu1.itb.read_accesses 0 # DTB read accesses -system.cpu1.itb.write_hits 0 # DTB write hits -system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.write_acv 0 # DTB write access violations -system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.data_hits 0 # DTB hits -system.cpu1.itb.data_misses 0 # DTB misses -system.cpu1.itb.data_acv 0 # DTB access violations -system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numPwrStateTransitions 5082 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 2541 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 747256549.980323 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 396382548.008070 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 2541 100.00% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 400000 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 975495000 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 2541 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 8770545000 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 1898778893500 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 17543632 # number of cpu cycles simulated -system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 7091057 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 17620667 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 4438770 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1273009 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 9220507 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 378986 # Number of cycles fetch has spent squashing -system.cpu1.fetch.MiscStallCycles 26066 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 68380 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 52547 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 66 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1980567 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 84330 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 16648116 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.058418 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.465473 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 13552832 81.41% 81.41% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 195919 1.18% 82.58% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 328483 1.97% 84.56% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 235159 1.41% 85.97% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 403136 2.42% 88.39% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 149696 0.90% 89.29% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 175199 1.05% 90.34% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 211449 1.27% 91.61% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1396243 8.39% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 16648116 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.253013 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.004391 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 5799032 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 8189176 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 2194913 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 283013 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 181981 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 153262 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 7666 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 14395116 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 24052 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 181981 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 5988192 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 920488 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 6008083 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 2289928 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 1259442 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 13629732 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 4042 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 109065 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 36629 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 635484 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 9050413 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 16252880 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 16186853 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 59441 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 7085651 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1964754 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 511413 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 53676 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 2285701 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 2541438 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1543271 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 322798 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 171550 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 11950332 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 586300 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 11472464 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 27528 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 2575040 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 1218372 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 432674 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 16648116 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.689115 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.415855 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 11949949 71.78% 71.78% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 2021085 12.14% 83.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 863131 5.18% 89.10% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 621327 3.73% 92.84% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 572760 3.44% 96.28% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 302852 1.82% 98.10% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 196760 1.18% 99.28% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 86740 0.52% 99.80% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 33512 0.20% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 16648116 # Number of insts issued each cycle -system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 33628 10.29% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMultAcc 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMisc 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 10.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 174409 53.35% 63.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 103464 31.65% 95.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMemRead 7989 2.44% 97.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMemWrite 7397 2.26% 100.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 4751 0.04% 0.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 7109835 61.97% 62.01% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 17232 0.15% 62.16% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.16% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 14002 0.12% 62.29% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.29% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.29% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.29% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMultAcc 0 0.00% 62.29% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 2375 0.02% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMisc 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.31% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 2510604 21.88% 84.19% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1425191 12.42% 96.61% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMemRead 45057 0.39% 97.01% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMemWrite 43675 0.38% 97.39% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 299742 2.61% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 11472464 # Type of FU issued -system.cpu1.iq.rate 0.653939 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 326887 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.028493 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 39721827 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 15008897 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 10951678 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 225631 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 107813 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 104885 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 11674105 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 120495 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 118360 # Number of loads that had data forwarded from stores -system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 553503 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 1124 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 5247 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 178223 # Number of stores squashed -system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 530 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 100466 # Number of times an access to memory failed due to the cache being blocked -system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 181981 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 560519 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 287887 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 13187033 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 58459 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 2541438 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1543271 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 532420 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 6842 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 279702 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 5247 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 45694 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 148663 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 194357 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 11283035 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 2456415 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 189428 # Number of squashed instructions skipped in execute -system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 650401 # number of nop insts executed -system.cpu1.iew.exec_refs 3906085 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1687752 # Number of branches executed -system.cpu1.iew.exec_stores 1449670 # Number of stores executed -system.cpu1.iew.exec_rate 0.643141 # Inst execution rate -system.cpu1.iew.wb_sent 11111703 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 11056563 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 5287384 # num instructions producing a value -system.cpu1.iew.wb_consumers 7447136 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.630232 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.709989 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 2591726 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 153626 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 169211 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 16186649 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.645421 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.620431 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 12404611 76.63% 76.63% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1746252 10.79% 87.42% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 623750 3.85% 91.28% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 386653 2.39% 93.67% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 297145 1.84% 95.50% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 125489 0.78% 96.28% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 112472 0.69% 96.97% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 119580 0.74% 97.71% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 370697 2.29% 100.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 16186649 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 10447204 # Number of instructions committed -system.cpu1.commit.committedOps 10447204 # Number of ops (including micro ops) committed -system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 3352983 # Number of memory references committed -system.cpu1.commit.loads 1987935 # Number of loads committed -system.cpu1.commit.membars 48912 # Number of memory barriers committed -system.cpu1.commit.branches 1499265 # Number of branches committed -system.cpu1.commit.fp_insts 102779 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 9704534 # Number of committed integer instructions. -system.cpu1.commit.function_calls 163857 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 490367 4.69% 4.69% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 6221313 59.55% 64.24% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 16935 0.16% 64.41% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.41% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 13993 0.13% 64.54% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.54% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.54% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.54% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMultAcc 0 0.00% 64.54% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 2375 0.02% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMisc 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.56% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 1992105 19.07% 83.63% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 1323963 12.67% 96.30% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMemRead 44742 0.43% 96.73% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMemWrite 41669 0.40% 97.13% # Class of committed instruction -system.cpu1.commit.op_class_0::IprAccess 299742 2.87% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 10447204 # Class of committed instruction -system.cpu1.commit.bw_lim_events 370697 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 28744557 # The number of ROB reads -system.cpu1.rob.rob_writes 26537349 # The number of ROB writes -system.cpu1.timesIdled 134728 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 895516 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3797555246 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 9961587 # Number of Instructions Simulated -system.cpu1.committedOps 9961587 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.761128 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.761128 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.567818 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.567818 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 14521823 # number of integer regfile reads -system.cpu1.int_regfile_writes 7909607 # number of integer regfile writes -system.cpu1.fp_regfile_reads 58779 # number of floating regfile reads -system.cpu1.fp_regfile_writes 57835 # number of floating regfile writes -system.cpu1.misc_regfile_reads 571518 # number of misc regfile reads -system.cpu1.misc_regfile_writes 244969 # number of misc regfile writes -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 130966 # number of replacements -system.cpu1.dcache.tags.tagsinuse 487.964655 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 3061418 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 131478 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 23.284641 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 49531315500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 487.964655 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.953056 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.953056 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 223 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 241 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 14512669 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 14512669 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 1946433 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1946433 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1026063 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1026063 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 40785 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 40785 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 37242 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 37242 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 2972496 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 2972496 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 2972496 # number of overall hits -system.cpu1.dcache.overall_hits::total 2972496 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 241711 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 241711 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 292248 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 292248 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5308 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 5308 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 3094 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 3094 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 533959 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 533959 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 533959 # number of overall misses -system.cpu1.dcache.overall_misses::total 533959 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3394927000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 3394927000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 12114051455 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 12114051455 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 54394000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 54394000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 17165000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 17165000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 15508978455 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 15508978455 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 15508978455 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 15508978455 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2188144 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2188144 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1318311 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1318311 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 46093 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 46093 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 40336 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 40336 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 3506455 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 3506455 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 3506455 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 3506455 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.110464 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.110464 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.221684 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.221684 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.115158 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.115158 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.076706 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.076706 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.152279 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.152279 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.152279 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.152279 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14045.397189 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14045.397189 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41451.272395 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 41451.272395 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10247.550867 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10247.550867 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5547.834518 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5547.834518 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 29045.260881 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 29045.260881 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29045.260881 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 29045.260881 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 715753 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 884 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 24925 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 13 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 28.716269 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 68 # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 84601 # number of writebacks -system.cpu1.dcache.writebacks::total 84601 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 148639 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 148639 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 243827 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 243827 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 846 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 846 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 392466 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 392466 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 392466 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 392466 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 93072 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 93072 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 48421 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 48421 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4462 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4462 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3093 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 3093 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 141493 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 141493 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 141493 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 141493 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 218 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 218 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3153 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3153 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3371 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3371 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1262526500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1262526500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1947214752 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1947214752 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 40086500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 40086500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 14072000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 14072000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3209741252 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3209741252 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3209741252 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 3209741252 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 41866500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 41866500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 41866500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 41866500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.042535 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042535 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036730 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036730 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.096804 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.096804 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.076681 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.076681 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.040352 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.040352 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.040352 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.040352 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13565.051788 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13565.051788 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 40214.261416 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 40214.261416 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8983.975796 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8983.975796 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4549.628193 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4549.628193 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22684.805976 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22684.805976 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22684.805976 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22684.805976 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 192048.165138 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 192048.165138 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 12419.608425 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 12419.608425 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 256896 # number of replacements -system.cpu1.icache.tags.tagsinuse 470.782709 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 1710963 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 257408 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 6.646891 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1882016787500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 470.782709 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.919497 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.919497 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 424 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 2238053 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 2238053 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 1710963 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1710963 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1710963 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1710963 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1710963 # number of overall hits -system.cpu1.icache.overall_hits::total 1710963 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 269604 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 269604 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 269604 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 269604 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 269604 # number of overall misses -system.cpu1.icache.overall_misses::total 269604 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3754413998 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 3754413998 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 3754413998 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 3754413998 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 3754413998 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 3754413998 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1980567 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1980567 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1980567 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1980567 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1980567 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1980567 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.136125 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.136125 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.136125 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.136125 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.136125 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.136125 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13925.661333 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13925.661333 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13925.661333 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13925.661333 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13925.661333 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13925.661333 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 473 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 42 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.261905 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 256896 # number of writebacks -system.cpu1.icache.writebacks::total 256896 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 12118 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 12118 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 12118 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 12118 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 12118 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 12118 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 257486 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 257486 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 257486 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 257486 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 257486 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 257486 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3368066498 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3368066498 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3368066498 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3368066498 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3368066498 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3368066498 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.130006 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.130006 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.130006 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.130006 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.130006 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.130006 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13080.581072 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13080.581072 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13080.581072 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 13080.581072 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13080.581072 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 13080.581072 # average overall mshr miss latency -system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). -system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. -system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_txs 395 # Number of DMA write transactions. -system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. -system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. -system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 7374 # Transaction distribution -system.iobus.trans_dist::ReadResp 7374 # Transaction distribution -system.iobus.trans_dist::WriteReq 54611 # Transaction distribution -system.iobus.trans_dist::WriteResp 54611 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11908 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1010 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 40508 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83462 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83462 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 123970 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 47632 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2733 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 73858 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661656 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661656 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2735514 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 12353502 # Layer occupancy (ticks) -system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 824500 # Layer occupancy (ticks) -system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 11000 # Layer occupancy (ticks) -system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 11000 # Layer occupancy (ticks) -system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 180500 # Layer occupancy (ticks) -system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 13988000 # Layer occupancy (ticks) -system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 2829000 # Layer occupancy (ticks) -system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 6060500 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 90500 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 216282007 # Layer occupancy (ticks) -system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 27449000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 41958000 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 41699 # number of replacements -system.iocache.tags.tagsinuse 0.490946 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41715 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1714262123000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.490946 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.030684 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.030684 # Average percentage of cache occupancy -system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id -system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375579 # Number of tag accesses -system.iocache.tags.data_accesses 375579 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.iocache.ReadReq_misses::tsunami.ide 179 # number of ReadReq misses -system.iocache.ReadReq_misses::total 179 # number of ReadReq misses -system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses -system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses -system.iocache.demand_misses::tsunami.ide 41731 # number of demand (read+write) misses -system.iocache.demand_misses::total 41731 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41731 # number of overall misses -system.iocache.overall_misses::total 41731 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 22774383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 22774383 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 4918988624 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4918988624 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 4941763007 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4941763007 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 4941763007 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4941763007 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 179 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 179 # number of ReadReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41731 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41731 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41731 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41731 # number of overall (read+write) accesses -system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses -system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses -system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 127231.189944 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 127231.189944 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 118381.512899 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118381.512899 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 118419.472502 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 118419.472502 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 118419.472502 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 118419.472502 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 1165 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 8 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 145.625000 # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.writebacks::writebacks 41520 # number of writebacks -system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 179 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 179 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41731 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41731 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41731 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41731 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13824383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13824383 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2838948426 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2838948426 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 2852772809 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2852772809 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 2852772809 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2852772809 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 77231.189944 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 77231.189944 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 68322.786533 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68322.786533 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 68360.998035 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68360.998035 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 68360.998035 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68360.998035 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 345941 # number of replacements -system.l2c.tags.tagsinuse 65423.095027 # Cycle average of tags in use -system.l2c.tags.total_refs 4335515 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 411463 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 10.536828 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 6416575000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 293.307825 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5315.079150 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 58827.069962 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 210.319847 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 777.318243 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.004476 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.081102 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.897630 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.003209 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.011861 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.998277 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65522 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 1694 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1843 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5673 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 56180 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.999786 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 38390429 # Number of tag accesses -system.l2c.tags.data_accesses 38390429 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 822340 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 822340 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 875169 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 875169 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 2863 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 1494 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 4357 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 501 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 467 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 968 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 145988 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 30963 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 176951 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 881644 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 255533 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 1137177 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 722233 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 84048 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 806281 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.inst 881644 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 868221 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 255533 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 115011 # number of demand (read+write) hits -system.l2c.demand_hits::total 2120409 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 881644 # number of overall hits -system.l2c.overall_hits::cpu0.data 868221 # number of overall hits -system.l2c.overall_hits::cpu1.inst 255533 # number of overall hits -system.l2c.overall_hits::cpu1.data 115011 # number of overall hits -system.l2c.overall_hits::total 2120409 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 6 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 5 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 11 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 109595 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 12065 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 121660 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 13405 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 1909 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 15314 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 272577 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 1964 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 274541 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.inst 13405 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 382172 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1909 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 14029 # number of demand (read+write) misses -system.l2c.demand_misses::total 411515 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 13405 # number of overall misses -system.l2c.overall_misses::cpu0.data 382172 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1909 # number of overall misses -system.l2c.overall_misses::cpu1.data 14029 # number of overall misses -system.l2c.overall_misses::total 411515 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0.data 332000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 117000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 449000 # number of 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-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 90191.435392 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77819.955423 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 90518.234672 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 114567.467389 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 79534.143637 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210644.188046 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 179548.165138 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209702.015288 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 87049.961500 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 11611.242955 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 74494.223363 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 852108 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 399805 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 437 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 7195 # Transaction distribution -system.membus.trans_dist::ReadResp 297167 # Transaction distribution -system.membus.trans_dist::WriteReq 13059 # Transaction distribution -system.membus.trans_dist::WriteResp 13059 # Transaction distribution -system.membus.trans_dist::WritebackDirty 123616 # Transaction distribution -system.membus.trans_dist::CleanEvict 263125 # Transaction distribution -system.membus.trans_dist::UpgradeReq 6609 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 5164 # Transaction distribution -system.membus.trans_dist::UpgradeResp 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 121953 # Transaction distribution -system.membus.trans_dist::ReadExResp 121548 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 290016 # Transaction distribution -system.membus.trans_dist::BadAddressError 44 # Transaction distribution -system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40508 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1179616 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 88 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1220212 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83445 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 83445 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1303657 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 73858 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31561664 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31635522 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 34293762 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 12507 # Total snoops (count) -system.membus.snoopTraffic 28800 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 485548 # Request fanout histogram -system.membus.snoop_fanout::mean 0.001427 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.037752 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 484855 99.86% 99.86% # Request fanout histogram -system.membus.snoop_fanout::1 693 0.14% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 485548 # Request fanout histogram -system.membus.reqLayer0.occupancy 36350498 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1353965073 # Layer occupancy (ticks) -system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 55000 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2179761000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 960863 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 5108724 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2554049 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 343728 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 1075 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 1007 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 68 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 7195 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2263429 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 13059 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 13059 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 904436 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1151326 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 825788 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 10854 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 6132 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 16986 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 300014 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 300014 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1152722 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1103559 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 44 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 238 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2684715 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3812301 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 771824 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 417816 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7686656 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 114526656 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 127297140 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 32917632 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 13697806 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 288439234 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 382362 # Total snoops (count) -system.toL2Bus.snoopTraffic 6813696 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 2939714 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.123574 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.329478 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 2576793 87.65% 87.65% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 362587 12.33% 99.99% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 316 0.01% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 18 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 2939714 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4544765338 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 301885 # Layer occupancy (ticks) -system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1344393906 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1911305093 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 387758410 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 217734513 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post -system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR -system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post -system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post -system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post -system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post -system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post -system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post -system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post -system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post -system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU -system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1907549438500 # Cumulative time (in ticks) in various power states -system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6475 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 176726 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 62785 40.28% 40.28% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.08% 40.36% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1925 1.23% 41.60% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 181 0.12% 41.71% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 90860 58.29% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 155882 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 61770 49.18% 49.18% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.10% 49.29% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1925 1.53% 50.82% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 181 0.14% 50.96% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 61589 49.04% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 125596 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1862335551000 97.65% 97.65% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 64321000 0.00% 97.65% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 576343500 0.03% 97.68% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 87551500 0.00% 97.68% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 44167527000 2.32% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1907231294000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.983834 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.677845 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.805712 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 7 4.14% 4.14% # number of syscalls executed -system.cpu0.kern.syscall::3 14 8.28% 12.43% # number of syscalls executed -system.cpu0.kern.syscall::4 4 2.37% 14.79% # number of syscalls executed -system.cpu0.kern.syscall::6 26 15.38% 30.18% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.59% 30.77% # number of syscalls executed -system.cpu0.kern.syscall::17 5 2.96% 33.73% # number of syscalls executed -system.cpu0.kern.syscall::19 7 4.14% 37.87% # number of syscalls executed -system.cpu0.kern.syscall::20 4 2.37% 40.24% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.59% 40.83% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.78% 42.60% # number of syscalls executed -system.cpu0.kern.syscall::33 5 2.96% 45.56% # number of syscalls executed -system.cpu0.kern.syscall::41 2 1.18% 46.75% # number of syscalls executed -system.cpu0.kern.syscall::45 26 15.38% 62.13% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.78% 63.91% # number of syscalls executed -system.cpu0.kern.syscall::48 8 4.73% 68.64% # number of syscalls executed -system.cpu0.kern.syscall::54 8 4.73% 73.37% # number of syscalls executed -system.cpu0.kern.syscall::59 6 3.55% 76.92% # number of syscalls executed -system.cpu0.kern.syscall::71 15 8.88% 85.80% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.78% 87.57% # number of syscalls executed -system.cpu0.kern.syscall::74 3 1.78% 89.35% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.59% 89.94% # number of syscalls executed -system.cpu0.kern.syscall::90 2 1.18% 91.12% # number of syscalls executed -system.cpu0.kern.syscall::92 7 4.14% 95.27% # number of syscalls executed -system.cpu0.kern.syscall::97 2 1.18% 96.45% # number of syscalls executed -system.cpu0.kern.syscall::98 2 1.18% 97.63% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.59% 98.22% # number of syscalls executed -system.cpu0.kern.syscall::144 1 0.59% 98.82% # number of syscalls executed -system.cpu0.kern.syscall::147 2 1.18% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 169 # number of syscalls executed -system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 293 0.18% 0.18% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.18% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.18% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.18% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3349 2.05% 2.23% # number of callpals executed -system.cpu0.kern.callpal::tbi 48 0.03% 2.26% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.26% # number of callpals executed -system.cpu0.kern.callpal::swpipl 149333 91.35% 93.61% # number of callpals executed -system.cpu0.kern.callpal::rdps 5683 3.48% 97.09% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 97.09% # number of callpals executed -system.cpu0.kern.callpal::wrusp 1 0.00% 97.09% # number of callpals executed -system.cpu0.kern.callpal::rdusp 8 0.00% 97.10% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.10% # number of callpals executed -system.cpu0.kern.callpal::rti 4311 2.64% 99.73% # number of callpals executed -system.cpu0.kern.callpal::callsys 303 0.19% 99.92% # number of callpals executed -system.cpu0.kern.callpal::imb 132 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 163475 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6664 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1070 # number of protection mode switches -system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1070 -system.cpu0.kern.mode_good::user 1070 -system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.160564 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.276700 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1905216688000 99.91% 99.91% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1682440000 0.09% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3350 # number of times the context was actually changed -system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2541 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 62895 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 19560 37.60% 37.60% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1924 3.70% 41.30% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 293 0.56% 41.86% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 30244 58.14% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 52021 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 19198 47.61% 47.61% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1924 4.77% 52.38% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 293 0.73% 53.11% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 18906 46.89% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 40321 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1872948111000 98.19% 98.19% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 564456500 0.03% 98.22% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 141435000 0.01% 98.22% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 33894599000 1.78% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1907548601500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.981493 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.625116 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.775091 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::2 1 0.64% 0.64% # number of syscalls executed -system.cpu1.kern.syscall::3 16 10.19% 10.83% # number of syscalls executed -system.cpu1.kern.syscall::6 16 10.19% 21.02% # number of syscalls executed -system.cpu1.kern.syscall::15 1 0.64% 21.66% # number of syscalls executed -system.cpu1.kern.syscall::17 10 6.37% 28.03% # number of syscalls executed -system.cpu1.kern.syscall::19 3 1.91% 29.94% # number of syscalls executed -system.cpu1.kern.syscall::20 2 1.27% 31.21% # number of syscalls executed -system.cpu1.kern.syscall::23 3 1.91% 33.12% # number of syscalls executed -system.cpu1.kern.syscall::24 3 1.91% 35.03% # number of syscalls executed -system.cpu1.kern.syscall::33 6 3.82% 38.85% # number of syscalls executed -system.cpu1.kern.syscall::45 28 17.83% 56.69% # number of syscalls executed -system.cpu1.kern.syscall::47 3 1.91% 58.60% # number of syscalls executed -system.cpu1.kern.syscall::48 2 1.27% 59.87% # number of syscalls executed -system.cpu1.kern.syscall::54 2 1.27% 61.15% # number of syscalls executed -system.cpu1.kern.syscall::58 1 0.64% 61.78% # number of syscalls executed -system.cpu1.kern.syscall::59 1 0.64% 62.42% # number of syscalls executed -system.cpu1.kern.syscall::71 39 24.84% 87.26% # number of syscalls executed -system.cpu1.kern.syscall::74 13 8.28% 95.54% # number of syscalls executed -system.cpu1.kern.syscall::90 1 0.64% 96.18% # number of syscalls executed -system.cpu1.kern.syscall::92 2 1.27% 97.45% # number of syscalls executed -system.cpu1.kern.syscall::132 3 1.91% 99.36% # number of syscalls executed -system.cpu1.kern.syscall::144 1 0.64% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 157 # number of syscalls executed -system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 181 0.33% 0.33% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1228 2.25% 2.59% # number of callpals executed -system.cpu1.kern.callpal::tbi 5 0.01% 2.60% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 2.61% # number of callpals executed -system.cpu1.kern.callpal::swpipl 46558 85.31% 87.92% # number of callpals executed -system.cpu1.kern.callpal::rdps 3077 5.64% 93.55% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 93.56% # number of callpals executed -system.cpu1.kern.callpal::wrusp 6 0.01% 93.57% # number of callpals executed -system.cpu1.kern.callpal::rdusp 1 0.00% 93.57% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 93.57% # number of callpals executed -system.cpu1.kern.callpal::rti 3246 5.95% 99.52% # number of callpals executed -system.cpu1.kern.callpal::callsys 212 0.39% 99.91% # number of callpals executed -system.cpu1.kern.callpal::imb 48 0.09% 100.00% # number of callpals executed -system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 54577 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1699 # number of protection mode switches -system.cpu1.kern.mode_switch::user 669 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2429 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 888 -system.cpu1.kern.mode_good::user 669 -system.cpu1.kern.mode_good::idle 219 -system.cpu1.kern.mode_switch_good::kernel 0.522660 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.090161 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.370231 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 5315508000 0.28% 0.28% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1058693000 0.06% 0.33% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1901174392500 99.67% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1229 # number of times the context was actually changed - ----------- End Simulation Statistics ---------- diff -r 9c673b990d5d -r e1835e5846b9 tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,113 +0,0 @@ -M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 - Got Configuration 623 - memsize 8000000 pages 4000 - First free page after ROM 0xFFFFFC0000018000 - HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000 - kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x2 - CPU Clock at 2000 MHz IntrClockFrequency=1024 - Booting with 2 processor(s) - KSP: 0x20043FE8 PTBR 0x20 - KSP: 0x20043FE8 PTBR 0x20 - Console Callback at 0x0, fixup at 0x0, crb offset: 0x790 - Memory cluster 0 [0 - 392] - Memory cluster 1 [392 - 15992] - Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000 - ConsoleDispatch at virt 100008D8 phys 188D8 val FFFFFC00000100A8 - Bootstraping CPU 1 with sp=0xFFFFFC0000076000 - unix_boot_mem ends at FFFFFC0000078000 - k_argc = 0 - jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067) - CallbackFixup 0 18000, t7=FFFFFC000070C000 - Entering slaveloop for cpu 1 my_rpb=FFFFFC0000018400 - Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006 - Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM - Major Options: SMP LEGACY_START VERBOSE_MCHECK - Command line: root=/dev/hda1 console=ttyS0 - memcluster 0, usage 1, start 0, end 392 - memcluster 1, usage 0, start 392, end 16384 - freeing pages 1069:16384 - reserving pages 1069:1070 - 4096K Bcache detected; load hit latency 30 cycles, load miss latency 167 cycles - SMP: 2 CPUs probed -- cpu_present_mask = 3 - Built 1 zonelists - Kernel command line: root=/dev/hda1 console=ttyS0 - PID hash table entries: 1024 (order: 10, 32768 bytes) - Using epoch = 1900 - Console: colour dummy device 80x25 - Dentry cache hash table entries: 32768 (order: 5, 262144 bytes) - Inode-cache hash table entries: 16384 (order: 4, 131072 bytes) - Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init) - Mount-cache hash table entries: 512 - SMP starting up secondaries. - Slave CPU 1 console command START -SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb FFFFFC0000018400 my_rpb_phys 18400 - Brought up 2 CPUs - SMP: Total of 2 processors activated (8000.15 BogoMIPS). - NET: Registered protocol family 16 - EISA bus registered - pci: enabling save/restore of SRM state - SCSI subsystem initialized - srm_env: version 0.0.5 loaded successfully - Installing knfsd (copyright (C) 1996 okir@monad.swb.de). - Initializing Cryptographic API - rtc: Standard PC (1900) epoch (1900) detected - Real Time Clock Driver v1.12 - Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled - ttyS0 at I/O 0x3f8 (irq = 4) is a 8250 - io scheduler noop registered - io scheduler anticipatory registered - io scheduler deadline registered - io scheduler cfq registered - loop: loaded (max 8 devices) - nbd: registered device at major 43 - ns83820.c: National Semiconductor DP83820 10/100/1000 driver. - PCI: Setting latency timer of device 0000:00:01.0 to 64 - eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000 - eth0: enabling optical transceiver - eth0: using 64 bit addressing. - eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=h,sg - tun: Universal TUN/TAP device driver, 1.6 - tun: (C) 1999-2004 Max Krasnyansky - Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2 - ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx - PIIX4: IDE controller at PCI slot 0000:00:00.0 - PIIX4: chipset revision 0 - PIIX4: 100% native mode on irq 31 - PCI: Setting latency timer of device 0000:00:00.0 to 64 - ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA - ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA - hda: M5 IDE Disk, ATA DISK drive - hdb: M5 IDE Disk, ATA DISK drive - ide0 at 0x8410-0x8417,0x8422 on irq 31 - hda: max request size: 128KiB - hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33) - hda: cache flushes not supported - hda: hda1 - hdb: max request size: 128KiB - hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33) - hdb: cache flushes not supported - hdb: unknown partition table - mice: PS/2 mouse device common for all mice - NET: Registered protocol family 2 - IP route cache hash table entries: 4096 (order: 2, 32768 bytes) - TCP established hash table entries: 16384 (order: 5, 262144 bytes) - TCP bind hash table entries: 16384 (order: 5, 262144 bytes) - TCP: Hash tables configured (established 16384 bind 16384) - TCP reno registered - ip_conntrack version 2.1 (512 buckets, 4096 max) - 296 bytes per conntrack - ip_tables: (C) 2000-2002 Netfilter core team - arp_tables: (C) 2002 David S. Miller - TCP bic registered - Initializing IPsec netlink socket - NET: Registered protocol family 1 - NET: Registered protocol family 17 - NET: Registered protocol family 15 - Bridge firewalling registered - 802.1Q VLAN Support v1.8 Ben Greear - All bugs added by David S. Miller - VFS: Mounted root (ext2 filesystem) readonly. - Freeing unused kernel memory: 224k freed - init started: BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary -mounting filesystems... -EXT2-fs warning: checktime reached, running e2fsck is recommended - loading script... diff -r 9c673b990d5d -r e1835e5846b9 tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,1732 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=true -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=LinuxAlphaSystem -children=bridge clk_domain cpu cpu_clk_domain disk0 disk2 dvfs_handler intrctrl iobus iocache membus physmem simple_disk terminal tsunami voltage_domain -boot_cpu_frequency=500 -boot_osflags=root=/dev/hda1 console=ttyS0 -cache_line_size=64 -clk_domain=system.clk_domain -console=/arm/projectscratch/randd/systems/dist/binaries/console -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges=0:134217727:0:0:0:0 -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pal=/arm/projectscratch/randd/systems/dist/binaries/ts_osfpal -power_model=Null -readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh -symbolfile= -system_rev=1024 -system_type=34 -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.bridge] -type=Bridge -clk_domain=system.clk_domain -default_p_state=UNDEFINED -delay=50000 -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -ranges=8796093022208:18446744073709551615:0:0:0:0 -req_size=16 -resp_size=16 -master=system.iobus.slave[0] -slave=system.membus.master[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=DerivO3CPU -children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer -LFSTSize=1024 -LQEntries=32 -LSQCheckLoads=true -LSQDepCheckShift=4 -SQEntries=32 -SSITSize=1024 -activity=0 -backComSize=5 -branchPred=system.cpu.branchPred -cachePorts=200 -checker=Null -clk_domain=system.cpu_clk_domain -commitToDecodeDelay=1 -commitToFetchDelay=1 -commitToIEWDelay=1 -commitToRenameDelay=1 -commitWidth=8 -cpu_id=0 -decodeToFetchDelay=1 -decodeToRenameDelay=1 -decodeWidth=8 -default_p_state=UNDEFINED -dispatchWidth=8 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -fetchBufferSize=64 -fetchQueueSize=32 -fetchToDecodeDelay=1 -fetchTrapLatency=1 -fetchWidth=8 -forwardComSize=5 -fuPool=system.cpu.fuPool -function_trace=false -function_trace_start=0 -iewToCommitDelay=1 -iewToDecodeDelay=1 -iewToFetchDelay=1 -iewToRenameDelay=1 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -issueToExecuteDelay=1 -issueWidth=8 -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -needsTSO=false -numIQEntries=64 -numPhysCCRegs=0 -numPhysFloatRegs=256 -numPhysIntRegs=256 -numROBEntries=192 -numRobs=1 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -renameToDecodeDelay=1 -renameToFetchDelay=1 -renameToIEWDelay=2 -renameToROBDelay=1 -renameWidth=8 -simpoint_start_insts= -smtCommitPolicy=RoundRobin -smtFetchPolicy=SingleThread -smtIQPolicy=Partitioned -smtIQThreshold=100 -smtLSQPolicy=Partitioned -smtLSQThreshold=100 -smtNumFetchingThreads=1 -smtROBPolicy=Partitioned -smtROBThreshold=100 -socket_id=0 -squashWidth=8 -store_set_clear_period=250000 -switched_out=false -system=system -tracer=system.cpu.tracer -trapLatency=13 -wbWidth=8 -workload= -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.branchPred] -type=TournamentBP -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -indirectHashGHR=true -indirectHashTargets=true -indirectPathLength=3 -indirectSets=256 -indirectTagSize=16 -indirectWays=2 -instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 -useIndirect=true - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=4 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=4 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu.dtb] -type=AlphaTLB -eventq_index=0 -size=64 - -[system.cpu.fuPool] -type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 -eventq_index=0 - -[system.cpu.fuPool.FUList0] -type=FUDesc -children=opList -count=6 -eventq_index=0 -opList=system.cpu.fuPool.FUList0.opList - -[system.cpu.fuPool.FUList0.opList] -type=OpDesc -eventq_index=0 -opClass=IntAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList1] -type=FUDesc -children=opList0 opList1 -count=2 -eventq_index=0 -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -eventq_index=0 -opClass=IntMult -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -eventq_index=0 -opClass=IntDiv -opLat=20 -pipelined=false - -[system.cpu.fuPool.FUList2] -type=FUDesc -children=opList0 opList1 opList2 -count=4 -eventq_index=0 -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -eventq_index=0 -opClass=FloatAdd -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -eventq_index=0 -opClass=FloatCmp -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -eventq_index=0 -opClass=FloatCvt -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList3] -type=FUDesc -children=opList0 opList1 opList2 -count=2 -eventq_index=0 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -eventq_index=0 -opClass=FloatMult -opLat=4 -pipelined=true - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -eventq_index=0 -opClass=FloatDiv -opLat=12 -pipelined=false - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -eventq_index=0 -opClass=FloatSqrt -opLat=24 -pipelined=false - -[system.cpu.fuPool.FUList4] -type=FUDesc -children=opList -count=0 -eventq_index=0 -opList=system.cpu.fuPool.FUList4.opList - -[system.cpu.fuPool.FUList4.opList] -type=OpDesc -eventq_index=0 -opClass=MemRead -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5] -type=FUDesc -children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 -count=4 -eventq_index=0 -opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 - -[system.cpu.fuPool.FUList5.opList00] -type=OpDesc -eventq_index=0 -opClass=SimdAdd -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList01] -type=OpDesc -eventq_index=0 -opClass=SimdAddAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList02] -type=OpDesc -eventq_index=0 -opClass=SimdAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList03] -type=OpDesc -eventq_index=0 -opClass=SimdCmp -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList04] -type=OpDesc -eventq_index=0 -opClass=SimdCvt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList05] -type=OpDesc -eventq_index=0 -opClass=SimdMisc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList06] -type=OpDesc -eventq_index=0 -opClass=SimdMult -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList07] -type=OpDesc -eventq_index=0 -opClass=SimdMultAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList08] -type=OpDesc -eventq_index=0 -opClass=SimdShift -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList09] -type=OpDesc -eventq_index=0 -opClass=SimdShiftAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList10] -type=OpDesc -eventq_index=0 -opClass=SimdSqrt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList11] -type=OpDesc -eventq_index=0 -opClass=SimdFloatAdd -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList12] -type=OpDesc -eventq_index=0 -opClass=SimdFloatAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList13] -type=OpDesc -eventq_index=0 -opClass=SimdFloatCmp -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList14] -type=OpDesc -eventq_index=0 -opClass=SimdFloatCvt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList15] -type=OpDesc -eventq_index=0 -opClass=SimdFloatDiv -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList16] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMisc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList17] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMult -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList18] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMultAcc -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList5.opList19] -type=OpDesc -eventq_index=0 -opClass=SimdFloatSqrt -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList6] -type=FUDesc -children=opList -count=0 -eventq_index=0 -opList=system.cpu.fuPool.FUList6.opList - -[system.cpu.fuPool.FUList6.opList] -type=OpDesc -eventq_index=0 -opClass=MemWrite -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList7] -type=FUDesc -children=opList0 opList1 -count=4 -eventq_index=0 -opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -eventq_index=0 -opClass=MemRead -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList7.opList1] -type=OpDesc -eventq_index=0 -opClass=MemWrite -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList8] -type=FUDesc -children=opList -count=1 -eventq_index=0 -opList=system.cpu.fuPool.FUList8.opList - -[system.cpu.fuPool.FUList8.opList] -type=OpDesc -eventq_index=0 -opClass=IprAccess -opLat=3 -pipelined=false - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=1 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=1 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu.interrupts] -type=AlphaInterrupts -eventq_index=0 - -[system.cpu.isa] -type=AlphaISA -eventq_index=0 -system=system - -[system.cpu.itb] -type=AlphaTLB -eventq_index=0 -size=48 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=4194304 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=4194304 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.disk0] -type=IdeDisk -children=image -delay=1000000 -driveID=master -eventq_index=0 -image=system.disk0.image - -[system.disk0.image] -type=CowDiskImage -children=child -child=system.disk0.image.child -eventq_index=0 -image_file= -read_only=false -table_size=65536 - -[system.disk0.image.child] -type=RawDiskImage -eventq_index=0 -image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img -read_only=true - -[system.disk2] -type=IdeDisk -children=image -delay=1000000 -driveID=master -eventq_index=0 -image=system.disk2.image - -[system.disk2.image] -type=CowDiskImage -children=child -child=system.disk2.image.child -eventq_index=0 -image_file= -read_only=false -table_size=65536 - -[system.disk2.image.child] -type=RawDiskImage -eventq_index=0 -image_file=/arm/projectscratch/randd/systems/dist/disks/linux-bigswap2.img -read_only=true - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.intrctrl] -type=IntrControl -eventq_index=0 -sys=system - -[system.iobus] -type=NoncoherentXBar -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=1 -frontend_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -response_latency=2 -use_default_range=false -width=16 -master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side -slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma - -[system.iocache] -type=Cache -children=tags -addr_ranges=0:134217727:0:0:0:0 -assoc=8 -clk_domain=system.clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=50 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=50 -sequential_access=false -size=1024 -system=system -tags=system.iocache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.iobus.master[27] -mem_side=system.membus.slave[2] - -[system.iocache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=50 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=1024 - -[system.membus] -type=CoherentXBar -children=badaddr_responder snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side - -[system.membus.badaddr_responder] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=0 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=true -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.membus.default - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=0:134217727:0:0:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=6000 -tXPDLL=0 -tXS=270000 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[1] - -[system.simple_disk] -type=SimpleDisk -children=disk -disk=system.simple_disk.disk -eventq_index=0 -system=system - -[system.simple_disk.disk] -type=RawDiskImage -eventq_index=0 -image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img -read_only=true - -[system.terminal] -type=Terminal -eventq_index=0 -intr_control=system.intrctrl -number=0 -output=true -port=3456 - -[system.tsunami] -type=Tsunami -children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip uart -eventq_index=0 -intrctrl=system.intrctrl -system=system - -[system.tsunami.backdoor] -type=AlphaBackdoor -clk_domain=system.clk_domain -cpu=system.cpu -default_p_state=UNDEFINED -disk=system.simple_disk -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804682956800 -pio_latency=100000 -platform=system.tsunami -power_model=Null -system=system -terminal=system.terminal -pio=system.iobus.master[24] - -[system.tsunami.cchip] -type=TsunamiCChip -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8803072344064 -pio_latency=100000 -power_model=Null -system=system -tsunami=system.tsunami -pio=system.iobus.master[0] - -[system.tsunami.ethernet] -type=NSGigE -BAR0=1 -BAR0LegacyIO=false -BAR0Size=256 -BAR1=0 -BAR1LegacyIO=false -BAR1Size=4096 -BAR2=0 -BAR2LegacyIO=false -BAR2Size=0 -BAR3=0 -BAR3LegacyIO=false -BAR3Size=0 -BAR4=0 -BAR4LegacyIO=false -BAR4Size=0 -BAR5=0 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=2 -Command=0 -DeviceID=34 -ExpansionROM=0 -HeaderType=0 -InterruptLine=30 -InterruptPin=1 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=52 -MinimumGrant=176 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=0 -Revision=0 -Status=656 -SubClassCode=0 -SubsystemID=0 -SubsystemVendorID=0 -VendorID=4107 -clk_domain=system.clk_domain -config_latency=20000 -default_p_state=UNDEFINED -dma_data_free=false -dma_desc_free=false -dma_no_allocate=true -dma_read_delay=0 -dma_read_factor=0 -dma_write_delay=0 -dma_write_factor=0 -eventq_index=0 -hardware_address=00:90:00:00:00:01 -host=system.tsunami.pchip -intr_delay=10000000 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_bus=0 -pci_dev=1 -pci_func=0 -pio_latency=30000 -power_model=Null -rss=false -rx_delay=1000000 -rx_fifo_size=524288 -rx_filter=true -rx_thread=false -system=system -tx_delay=1000000 -tx_fifo_size=524288 -tx_thread=false -dma=system.iobus.slave[2] -pio=system.iobus.master[26] - -[system.tsunami.fake_OROM] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8796093677568 -pio_latency=100000 -pio_size=393216 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[8] - -[system.tsunami.fake_ata0] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848432 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[19] - -[system.tsunami.fake_ata1] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848304 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[20] - -[system.tsunami.fake_pnp_addr] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848569 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[9] - -[system.tsunami.fake_pnp_read0] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848451 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[11] - -[system.tsunami.fake_pnp_read1] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848515 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[12] - -[system.tsunami.fake_pnp_read2] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848579 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[13] - -[system.tsunami.fake_pnp_read3] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848643 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[14] - -[system.tsunami.fake_pnp_read4] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848707 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[15] - -[system.tsunami.fake_pnp_read5] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848771 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[16] - -[system.tsunami.fake_pnp_read6] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848835 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[17] - -[system.tsunami.fake_pnp_read7] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848899 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[18] - -[system.tsunami.fake_pnp_write] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615850617 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[10] - -[system.tsunami.fake_ppc] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848891 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[7] - -[system.tsunami.fake_sm_chip] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848816 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[2] - -[system.tsunami.fake_uart1] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848696 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[3] - -[system.tsunami.fake_uart2] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848936 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[4] - -[system.tsunami.fake_uart3] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848680 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[5] - -[system.tsunami.fake_uart4] -type=IsaFake -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -fake_mem=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848944 -pio_latency=100000 -pio_size=8 -power_model=Null -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.master[6] - -[system.tsunami.fb] -type=BadDevice -clk_domain=system.clk_domain -default_p_state=UNDEFINED -devicename=FrameBuffer -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848912 -pio_latency=100000 -power_model=Null -system=system -pio=system.iobus.master[21] - -[system.tsunami.ide] -type=IdeController -BAR0=1 -BAR0LegacyIO=false -BAR0Size=8 -BAR1=1 -BAR1LegacyIO=false -BAR1Size=4 -BAR2=1 -BAR2LegacyIO=false -BAR2Size=8 -BAR3=1 -BAR3LegacyIO=false -BAR3Size=4 -BAR4=1 -BAR4LegacyIO=false -BAR4Size=16 -BAR5=1 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CapabilityPtr=0 -CardbusCIS=0 -ClassCode=1 -Command=0 -DeviceID=28945 -ExpansionROM=0 -HeaderType=0 -InterruptLine=31 -InterruptPin=1 -LatencyTimer=0 -LegacyIOBase=0 -MSICAPBaseOffset=0 -MSICAPCapId=0 -MSICAPMaskBits=0 -MSICAPMsgAddr=0 -MSICAPMsgCtrl=0 -MSICAPMsgData=0 -MSICAPMsgUpperAddr=0 -MSICAPNextCapability=0 -MSICAPPendingBits=0 -MSIXCAPBaseOffset=0 -MSIXCAPCapId=0 -MSIXCAPNextCapability=0 -MSIXMsgCtrl=0 -MSIXPbaOffset=0 -MSIXTableOffset=0 -MaximumLatency=0 -MinimumGrant=0 -PMCAPBaseOffset=0 -PMCAPCapId=0 -PMCAPCapabilities=0 -PMCAPCtrlStatus=0 -PMCAPNextCapability=0 -PXCAPBaseOffset=0 -PXCAPCapId=0 -PXCAPCapabilities=0 -PXCAPDevCap2=0 -PXCAPDevCapabilities=0 -PXCAPDevCtrl=0 -PXCAPDevCtrl2=0 -PXCAPDevStatus=0 -PXCAPLinkCap=0 -PXCAPLinkCtrl=0 -PXCAPLinkStatus=0 -PXCAPNextCapability=0 -ProgIF=133 -Revision=0 -Status=640 -SubClassCode=1 -SubsystemID=0 -SubsystemVendorID=0 -VendorID=32902 -clk_domain=system.clk_domain -config_latency=20000 -ctrl_offset=0 -default_p_state=UNDEFINED -disks=system.disk0 system.disk2 -eventq_index=0 -host=system.tsunami.pchip -io_shift=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_bus=0 -pci_dev=0 -pci_func=0 -pio_latency=30000 -power_model=Null -system=system -dma=system.iobus.slave[1] -pio=system.iobus.master[25] - -[system.tsunami.io] -type=TsunamiIO -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -frequency=976562500 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615847936 -pio_latency=100000 -power_model=Null -system=system -time=Thu Jan 1 00:00:00 2009 -tsunami=system.tsunami -year_is_bcd=false -pio=system.iobus.master[22] - -[system.tsunami.pchip] -type=TsunamiPChip -clk_domain=system.clk_domain -conf_base=8804649402368 -conf_device_bits=8 -conf_size=16777216 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pci_dma_base=0 -pci_mem_base=8796093022208 -pci_pio_base=8804615847936 -pio_addr=8802535473152 -pio_latency=100000 -platform=system.tsunami -power_model=Null -system=system -tsunami=system.tsunami -pio=system.iobus.master[1] - -[system.tsunami.uart] -type=Uart8250 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=8804615848952 -pio_latency=100000 -platform=system.tsunami -power_model=Null -system=system -terminal=system.terminal -pio=system.iobus.master[23] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff -r 9c673b990d5d -r e1835e5846b9 build_opts/ALPHA_MESI_Two_Level --- a/build_opts/ALPHA_MESI_Two_Level Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,3 +0,0 @@ -SS_COMPATIBLE_FP = 1 -CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,MinorCPU' -PROTOCOL = 'MESI_Two_Level' diff -r 9c673b990d5d -r e1835e5846b9 build_opts/ALPHA_MOESI_CMP_directory --- a/build_opts/ALPHA_MOESI_CMP_directory Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,3 +0,0 @@ -SS_COMPATIBLE_FP = 1 -CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,MinorCPU' -PROTOCOL = 'MOESI_CMP_directory' diff -r 9c673b990d5d -r e1835e5846b9 SConstruct --- a/SConstruct Mon Oct 24 21:38:48 2016 +0100 +++ b/SConstruct Mon Oct 24 21:40:04 2016 +0100 @@ -49,7 +49,7 @@ # # While in this directory ('gem5'), just type 'scons' to build the default # configuration (see below), or type 'scons build//' -# to build some other configuration (e.g., 'build/ALPHA/gem5.opt' for +# to build some other configuration (e.g., 'build/ARM/gem5.opt' for # the optimized full-system version). # # You can build gem5 in a different directory as long as there is a @@ -61,15 +61,15 @@ # # The following two commands are equivalent. The '-u' option tells # scons to search up the directory tree for this SConstruct file. -# % cd /gem5 ; scons build/ALPHA/gem5.debug -# % cd /gem5/build/ALPHA; scons -u gem5.debug +# % cd /gem5 ; scons build/ARM/gem5.debug +# % cd /gem5/build/ARM; scons -u gem5.debug # # The following two commands are equivalent and demonstrate building # in a directory outside of the source tree. The '-C' option tells # scons to chdir to the specified directory to find this SConstruct # file. -# % cd /gem5 ; scons /local/foo/build/ALPHA/gem5.debug -# % cd /local/foo/build/ALPHA; scons -C /gem5 gem5.debug +# % cd /gem5 ; scons /local/foo/build/ARM/gem5.debug +# % cd /local/foo/build/ARM; scons -C /gem5 gem5.debug # # You can use 'scons -H' to print scons options. If you're in this # 'gem5' directory (or use -u or -C to tell scons where to find this @@ -418,7 +418,7 @@ ################################################### # Find default configuration & binary. -Default(environ.get('M5_DEFAULT_BINARY', 'build/ALPHA/gem5.debug')) +Default(environ.get('M5_DEFAULT_BINARY', 'build/ARM/gem5.debug')) # helper function: find last occurrence of element in list def rfind(l, elt, offs = -1): @@ -436,8 +436,8 @@ # Each target must have 'build' in the interior of the path; the # directory below this will determine the build parameters. For -# example, for target 'foo/bar/build/ALPHA_SE/arch/alpha/blah.do' we -# recognize that ALPHA_SE specifies the configuration because it +# example, for target 'foo/bar/build/ARM/arch/arm/blah.do' we +# recognize that ARM specifies the configuration because it # follow 'build' in the build path. # The funky assignment to "[:]" is needed to replace the list contents @@ -485,7 +485,7 @@ # # Set up global sticky variables... these are common to an entire build -# tree (not specific to a particular build like ALPHA_SE) +# tree (not specific to a particular build like ARM) # global_vars_file = joinpath(build_root, 'variables.global') @@ -1223,16 +1223,13 @@ all_gpu_isa_list.sort() sticky_vars.AddVariables( - EnumVariable('TARGET_ISA', 'Target ISA', 'alpha', all_isa_list), + EnumVariable('TARGET_ISA', 'Target ISA', 'arm', all_isa_list), EnumVariable('TARGET_GPU_ISA', 'Target GPU ISA', 'hsail', all_gpu_isa_list), ListVariable('CPU_MODELS', 'CPU models', sorted(n for n,m in CpuModel.dict.iteritems() if m.default), sorted(CpuModel.dict.keys())), BoolVariable('EFENCE', 'Link with Electric Fence malloc debugger', False), - BoolVariable('SS_COMPATIBLE_FP', - 'Make floating-point results compatible with SimpleScalar', - False), BoolVariable('USE_SSE2', 'Compile for SSE2 (-msse2) to get IEEE FP on x86 hosts', False), @@ -1248,7 +1245,7 @@ ) # These variables get exported to #defines in config/*.hh (see src/SConscript). -export_vars += ['USE_FENV', 'SS_COMPATIBLE_FP', 'TARGET_ISA', 'TARGET_GPU_ISA', +export_vars += ['USE_FENV', 'TARGET_ISA', 'TARGET_GPU_ISA', 'CP_ANNOTATE', 'USE_POSIX_CLOCK', 'USE_KVM', 'PROTOCOL', 'HAVE_PROTOBUF', 'HAVE_PERF_ATTR_EXCLUDE_HOST'] diff -r 9c673b990d5d -r e1835e5846b9 build_opts/ALPHA --- a/build_opts/ALPHA Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,4 +0,0 @@ -TARGET_ISA = 'alpha' -SS_COMPATIBLE_FP = 1 -CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,MinorCPU' -PROTOCOL = 'MI_example' diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/idle_event.hh --- a/src/arch/alpha/idle_event.hh Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,47 +0,0 @@ -/* - * Copyright (c) 2004-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Nathan Binkert - * Lisa Hsu - * Ali Saidi - */ - -#ifndef __KERN_ALPHA_IDLE_EVENT_HH__ -#define __KERN_ALPHA_IDLE_EVENT_HH__ - -#include "cpu/pc_event.hh" - -class IdleStartEvent : public PCEvent -{ - public: - IdleStartEvent(PCEventQueue *q, const std::string &desc, Addr addr) - : PCEvent(q, desc, addr) - {} - virtual void process(ThreadContext *tc); -}; - -#endif // __KERN_ALPHA_IDLE_EVENT_HH__ diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/idle_event.cc --- a/src/arch/alpha/idle_event.cc Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,46 +0,0 @@ -/* - * Copyright (c) 2004-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Lisa Hsu - * Nathan Binkert - */ - -#include "arch/alpha/idle_event.hh" -#include "arch/alpha/kernel_stats.hh" -#include "cpu/thread_context.hh" - -using namespace AlphaISA; - -void -IdleStartEvent::process(ThreadContext *tc) -{ - if (tc->getKernelStats()) { - MiscReg val = tc->readMiscRegNoEffect(IPR_PALtemp23); - tc->getKernelStats()->setIdleProcess(val, tc); - } - remove(); -} diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/interrupts.hh --- a/src/arch/alpha/interrupts.hh Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,224 +0,0 @@ -/* - * Copyright (c) 2006 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Steve Reinhardt - * Kevin Lim - */ - -#ifndef __ARCH_ALPHA_INTERRUPT_HH__ -#define __ARCH_ALPHA_INTERRUPT_HH__ - -#include - -#include "arch/alpha/faults.hh" -#include "arch/alpha/isa_traits.hh" -#include "base/compiler.hh" -#include "base/trace.hh" -#include "cpu/thread_context.hh" -#include "debug/Flow.hh" -#include "debug/Interrupt.hh" -#include "params/AlphaInterrupts.hh" -#include "sim/sim_object.hh" - -namespace AlphaISA { - -class Interrupts : public SimObject -{ - private: - bool newInfoSet; - int newIpl; - int newSummary; - BaseCPU * cpu; - - protected: - uint64_t interrupts[NumInterruptLevels]; - uint64_t intstatus; - - public: - typedef AlphaInterruptsParams Params; - - const Params * - params() const - { - return dynamic_cast(_params); - } - - Interrupts(Params * p) : SimObject(p), cpu(NULL) - { - memset(interrupts, 0, sizeof(interrupts)); - intstatus = 0; - newInfoSet = false; - } - - void - setCPU(BaseCPU * _cpu) - { - cpu = _cpu; - } - - void - post(int int_num, int index) - { - DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index); - - if (int_num < 0 || int_num >= NumInterruptLevels) - panic("int_num out of bounds\n"); - - if (index < 0 || index >= (int)sizeof(uint64_t) * 8) - panic("int_num out of bounds\n"); - - interrupts[int_num] |= 1 << index; - intstatus |= (ULL(1) << int_num); - } - - void - clear(int int_num, int index) - { - DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index); - - if (int_num < 0 || int_num >= NumInterruptLevels) - panic("int_num out of bounds\n"); - - if (index < 0 || index >= (int)sizeof(uint64_t) * 8) - panic("int_num out of bounds\n"); - - interrupts[int_num] &= ~(1 << index); - if (interrupts[int_num] == 0) - intstatus &= ~(ULL(1) << int_num); - } - - void - clearAll() - { - DPRINTF(Interrupt, "Interrupts all cleared\n"); - - memset(interrupts, 0, sizeof(interrupts)); - intstatus = 0; - } - - void - serialize(CheckpointOut &cp) const - { - SERIALIZE_ARRAY(interrupts, NumInterruptLevels); - SERIALIZE_SCALAR(intstatus); - } - - void - unserialize(CheckpointIn &cp) - { - UNSERIALIZE_ARRAY(interrupts, NumInterruptLevels); - UNSERIALIZE_SCALAR(intstatus); - } - - bool - checkInterrupts(ThreadContext *tc) const - { - if (intstatus == 0) - return false; - - if (tc->pcState().pc() & 0x3) - return false; - - if (tc->readMiscRegNoEffect(IPR_ASTRR)) - panic("asynchronous traps not implemented\n"); - - uint64_t ipl = 0; - uint64_t summary = 0; - - if (tc->readMiscRegNoEffect(IPR_SIRR)) { - for (uint64_t i = INTLEVEL_SOFTWARE_MIN; - i < INTLEVEL_SOFTWARE_MAX; i++) { - if (tc->readMiscRegNoEffect(IPR_SIRR) & (ULL(1) << i)) { - // See table 4-19 of 21164 hardware reference - ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1; - summary |= (ULL(1) << i); - } - } - } - - for (uint64_t i = INTLEVEL_EXTERNAL_MIN; i < INTLEVEL_EXTERNAL_MAX; - i++) { - if (intstatus & (ULL(1) << i)) { - // See table 4-19 of 21164 hardware reference - ipl = i; - summary |= (ULL(1) << i); - } - } - - return ipl && ipl > tc->readMiscRegNoEffect(IPR_IPLR); - } - - Fault - getInterrupt(ThreadContext *tc) - { - assert(checkInterrupts(tc)); - - uint64_t ipl = 0; - uint64_t summary = 0; - if (tc->readMiscRegNoEffect(IPR_SIRR)) { - for (uint64_t i = INTLEVEL_SOFTWARE_MIN; - i < INTLEVEL_SOFTWARE_MAX; i++) { - if (tc->readMiscRegNoEffect(IPR_SIRR) & (ULL(1) << i)) { - // See table 4-19 of 21164 hardware reference - ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1; - summary |= (ULL(1) << i); - } - } - } - - for (uint64_t i = INTLEVEL_EXTERNAL_MIN; i < INTLEVEL_EXTERNAL_MAX; - i++) { - if (intstatus & (ULL(1) << i)) { - // See table 4-19 of 21164 hardware reference - ipl = i; - summary |= (ULL(1) << i); - } - } - - newIpl = ipl; - newSummary = summary; - newInfoSet = true; - DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", - tc->readMiscRegNoEffect(IPR_IPLR), ipl, summary); - - return std::make_shared(); - } - - void - updateIntrInfo(ThreadContext *tc) - { - assert(newInfoSet); - tc->setMiscRegNoEffect(IPR_ISR, newSummary); - tc->setMiscRegNoEffect(IPR_INTID, newIpl); - newInfoSet = false; - } -}; - -} // namespace AlphaISA - -#endif // __ARCH_ALPHA_INTERRUPT_HH__ - diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/interrupts.cc --- a/src/arch/alpha/interrupts.cc Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,37 +0,0 @@ -/* - * Copyright (c) 2008 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - */ - -#include "arch/alpha/interrupts.hh" - -AlphaISA::Interrupts * -AlphaInterruptsParams::create() -{ - return new AlphaISA::Interrupts(this); -} diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/ipr.hh --- a/src/arch/alpha/ipr.hh Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,239 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Steve Reinhardt - * Gabe Black - */ - -#ifndef __ARCH_ALPHA_IPR_HH__ -#define __ARCH_ALPHA_IPR_HH__ - -namespace AlphaISA { - -//////////////////////////////////////////////////////////////////////// -// -// Internal Processor Reigsters -// -enum md_ipr_names { - RAW_IPR_ISR = 0x100, // interrupt summary - RAW_IPR_ITB_TAG = 0x101, // ITLB tag - RAW_IPR_ITB_PTE = 0x102, // ITLB page table entry - RAW_IPR_ITB_ASN = 0x103, // ITLB address space - RAW_IPR_ITB_PTE_TEMP = 0x104, // ITLB page table entry temp - RAW_IPR_ITB_IA = 0x105, // ITLB invalidate all - RAW_IPR_ITB_IAP = 0x106, // ITLB invalidate all process - RAW_IPR_ITB_IS = 0x107, // ITLB invalidate select - RAW_IPR_SIRR = 0x108, // software interrupt request - RAW_IPR_ASTRR = 0x109, // asynchronous system trap request - RAW_IPR_ASTER = 0x10a, // asynchronous system trap enable - RAW_IPR_EXC_ADDR = 0x10b, // exception address - RAW_IPR_EXC_SUM = 0x10c, // exception summary - RAW_IPR_EXC_MASK = 0x10d, // exception mask - RAW_IPR_PAL_BASE = 0x10e, // PAL base address - RAW_IPR_ICM = 0x10f, // instruction current mode - RAW_IPR_IPLR = 0x110, // interrupt priority level - RAW_IPR_INTID = 0x111, // interrupt ID - RAW_IPR_IFAULT_VA_FORM = 0x112, // formatted faulting virtual addr - RAW_IPR_IVPTBR = 0x113, // virtual page table base - RAW_IPR_HWINT_CLR = 0x115, // H/W interrupt clear - RAW_IPR_SL_XMIT = 0x116, // serial line transmit - RAW_IPR_SL_RCV = 0x117, // serial line receive - RAW_IPR_ICSR = 0x118, // instruction control and status - RAW_IPR_IC_FLUSH = 0x119, // instruction cache flush control - RAW_IPR_IC_PERR_STAT = 0x11a, // inst cache parity error status - RAW_IPR_PMCTR = 0x11c, // performance counter - - // PAL temporary registers... - // register meanings gleaned from osfpal.s source code - RAW_IPR_PALtemp0 = 0x140, // local scratch - RAW_IPR_PALtemp1 = 0x141, // local scratch - RAW_IPR_PALtemp2 = 0x142, // entUna - RAW_IPR_PALtemp3 = 0x143, // CPU specific impure area pointer - RAW_IPR_PALtemp4 = 0x144, // memory management temp - RAW_IPR_PALtemp5 = 0x145, // memory management temp - RAW_IPR_PALtemp6 = 0x146, // memory management temp - RAW_IPR_PALtemp7 = 0x147, // entIF - RAW_IPR_PALtemp8 = 0x148, // intmask - RAW_IPR_PALtemp9 = 0x149, // entSys - RAW_IPR_PALtemp10 = 0x14a, // ?? - RAW_IPR_PALtemp11 = 0x14b, // entInt - RAW_IPR_PALtemp12 = 0x14c, // entArith - RAW_IPR_PALtemp13 = 0x14d, // reserved for platform specific PAL - RAW_IPR_PALtemp14 = 0x14e, // reserved for platform specific PAL - RAW_IPR_PALtemp15 = 0x14f, // reserved for platform specific PAL - RAW_IPR_PALtemp16 = 0x150, // scratch / whami<7:0> / mces<4:0> - RAW_IPR_PALtemp17 = 0x151, // sysval - RAW_IPR_PALtemp18 = 0x152, // usp - RAW_IPR_PALtemp19 = 0x153, // ksp - RAW_IPR_PALtemp20 = 0x154, // PTBR - RAW_IPR_PALtemp21 = 0x155, // entMM - RAW_IPR_PALtemp22 = 0x156, // kgp - RAW_IPR_PALtemp23 = 0x157, // PCBB - - RAW_IPR_DTB_ASN = 0x200, // DTLB address space number - RAW_IPR_DTB_CM = 0x201, // DTLB current mode - RAW_IPR_DTB_TAG = 0x202, // DTLB tag - RAW_IPR_DTB_PTE = 0x203, // DTLB page table entry - RAW_IPR_DTB_PTE_TEMP = 0x204, // DTLB page table entry temporary - - RAW_IPR_MM_STAT = 0x205, // data MMU fault status - RAW_IPR_VA = 0x206, // fault virtual address - RAW_IPR_VA_FORM = 0x207, // formatted virtual address - RAW_IPR_MVPTBR = 0x208, // MTU virtual page table base - RAW_IPR_DTB_IAP = 0x209, // DTLB invalidate all process - RAW_IPR_DTB_IA = 0x20a, // DTLB invalidate all - RAW_IPR_DTB_IS = 0x20b, // DTLB invalidate single - RAW_IPR_ALT_MODE = 0x20c, // alternate mode - RAW_IPR_CC = 0x20d, // cycle counter - RAW_IPR_CC_CTL = 0x20e, // cycle counter control - RAW_IPR_MCSR = 0x20f, // MTU control - - RAW_IPR_DC_FLUSH = 0x210, - RAW_IPR_DC_PERR_STAT = 0x212, // Dcache parity error status - RAW_IPR_DC_TEST_CTL = 0x213, // Dcache test tag control - RAW_IPR_DC_TEST_TAG = 0x214, // Dcache test tag - RAW_IPR_DC_TEST_TAG_TEMP = 0x215, // Dcache test tag temporary - RAW_IPR_DC_MODE = 0x216, // Dcache mode - RAW_IPR_MAF_MODE = 0x217, // miss address file mode - - MaxInternalProcRegs // number of IPRs -}; - -enum MiscRegIpr -{ - //Write only - MinWriteOnlyIpr, - IPR_HWINT_CLR = MinWriteOnlyIpr, - IPR_SL_XMIT, - IPR_DC_FLUSH, - IPR_IC_FLUSH, - IPR_ALT_MODE, - IPR_DTB_IA, - IPR_DTB_IAP, - IPR_ITB_IA, - MaxWriteOnlyIpr, - IPR_ITB_IAP = MaxWriteOnlyIpr, - - //Read only - MinReadOnlyIpr, - IPR_INTID = MinReadOnlyIpr, - IPR_SL_RCV, - IPR_MM_STAT, - IPR_ITB_PTE_TEMP, - MaxReadOnlyIpr, - IPR_DTB_PTE_TEMP = MaxReadOnlyIpr, - - IPR_ISR, - IPR_ITB_TAG, - IPR_ITB_PTE, - IPR_ITB_ASN, - IPR_ITB_IS, - IPR_SIRR, - IPR_ASTRR, - IPR_ASTER, - IPR_EXC_ADDR, - IPR_EXC_SUM, - IPR_EXC_MASK, - IPR_PAL_BASE, - IPR_ICM, - IPR_IPLR, - IPR_IFAULT_VA_FORM, - IPR_IVPTBR, - IPR_ICSR, - IPR_IC_PERR_STAT, - IPR_PMCTR, - - // PAL temporary registers... - // register meanings gleaned from osfpal.s source code - IPR_PALtemp0, - IPR_PALtemp1, - IPR_PALtemp2, - IPR_PALtemp3, - IPR_PALtemp4, - IPR_PALtemp5, - IPR_PALtemp6, - IPR_PALtemp7, - IPR_PALtemp8, - IPR_PALtemp9, - IPR_PALtemp10, - IPR_PALtemp11, - IPR_PALtemp12, - IPR_PALtemp13, - IPR_PALtemp14, - IPR_PALtemp15, - IPR_PALtemp16, - IPR_PALtemp17, - IPR_PALtemp18, - IPR_PALtemp19, - IPR_PALtemp20, - IPR_PALtemp21, - IPR_PALtemp22, - IPR_PALtemp23, - - IPR_DTB_ASN, - IPR_DTB_CM, - IPR_DTB_TAG, - IPR_DTB_PTE, - - IPR_VA, - IPR_VA_FORM, - IPR_MVPTBR, - IPR_DTB_IS, - IPR_CC, - IPR_CC_CTL, - IPR_MCSR, - - IPR_DC_PERR_STAT, - IPR_DC_TEST_CTL, - IPR_DC_TEST_TAG, - IPR_DC_TEST_TAG_TEMP, - IPR_DC_MODE, - IPR_MAF_MODE, - - NumInternalProcRegs // number of IPR registers -}; - -inline bool -IprIsWritable(int index) -{ - return index < MinReadOnlyIpr || index > MaxReadOnlyIpr; -} - -inline bool -IprIsReadable(int index) -{ - return index < MinWriteOnlyIpr || index > MaxWriteOnlyIpr; -} - -extern md_ipr_names MiscRegIndexToIpr[NumInternalProcRegs]; -extern int IprToMiscRegIndex[MaxInternalProcRegs]; - -void initializeIprTable(); - -} // namespace AlphaISA - -#endif // __ARCH_ALPHA_IPR_HH__ diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/ipr.cc --- a/src/arch/alpha/ipr.cc Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,142 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - */ - -#include -#include - -#include "arch/alpha/ipr.hh" - -namespace AlphaISA { - -md_ipr_names MiscRegIndexToIpr[NumInternalProcRegs] = { - - //Write only - RAW_IPR_HWINT_CLR, // H/W interrupt clear register - RAW_IPR_SL_XMIT, // serial line transmit register - RAW_IPR_DC_FLUSH, - RAW_IPR_IC_FLUSH, // instruction cache flush control - RAW_IPR_ALT_MODE, // alternate mode register - RAW_IPR_DTB_IA, // DTLB invalidate all register - RAW_IPR_DTB_IAP, // DTLB invalidate all process register - RAW_IPR_ITB_IA, // ITLB invalidate all register - RAW_IPR_ITB_IAP, // ITLB invalidate all process register - - //Read only - RAW_IPR_INTID, // interrupt ID register - RAW_IPR_SL_RCV, // serial line receive register - RAW_IPR_MM_STAT, // data MMU fault status register - RAW_IPR_ITB_PTE_TEMP, // ITLB page table entry temp register - RAW_IPR_DTB_PTE_TEMP, // DTLB page table entry temporary register - - RAW_IPR_ISR, // interrupt summary register - RAW_IPR_ITB_TAG, // ITLB tag register - RAW_IPR_ITB_PTE, // ITLB page table entry register - RAW_IPR_ITB_ASN, // ITLB address space register - RAW_IPR_ITB_IS, // ITLB invalidate select register - RAW_IPR_SIRR, // software interrupt request register - RAW_IPR_ASTRR, // asynchronous system trap request register - RAW_IPR_ASTER, // asynchronous system trap enable register - RAW_IPR_EXC_ADDR, // exception address register - RAW_IPR_EXC_SUM, // exception summary register - RAW_IPR_EXC_MASK, // exception mask register - RAW_IPR_PAL_BASE, // PAL base address register - RAW_IPR_ICM, // instruction current mode - RAW_IPR_IPLR, // interrupt priority level register - RAW_IPR_IFAULT_VA_FORM, // formatted faulting virtual addr register - RAW_IPR_IVPTBR, // virtual page table base register - RAW_IPR_ICSR, // instruction control and status register - RAW_IPR_IC_PERR_STAT, // inst cache parity error status register - RAW_IPR_PMCTR, // performance counter register - - // PAL temporary registers... - // register meanings gleaned from osfpal.s source code - RAW_IPR_PALtemp0, // local scratch - RAW_IPR_PALtemp1, // local scratch - RAW_IPR_PALtemp2, // entUna - RAW_IPR_PALtemp3, // CPU specific impure area pointer - RAW_IPR_PALtemp4, // memory management temp - RAW_IPR_PALtemp5, // memory management temp - RAW_IPR_PALtemp6, // memory management temp - RAW_IPR_PALtemp7, // entIF - RAW_IPR_PALtemp8, // intmask - RAW_IPR_PALtemp9, // entSys - RAW_IPR_PALtemp10, // ?? - RAW_IPR_PALtemp11, // entInt - RAW_IPR_PALtemp12, // entArith - RAW_IPR_PALtemp13, // reserved for platform specific PAL - RAW_IPR_PALtemp14, // reserved for platform specific PAL - RAW_IPR_PALtemp15, // reserved for platform specific PAL - RAW_IPR_PALtemp16, // scratch / whami<7:0> / mces<4:0> - RAW_IPR_PALtemp17, // sysval - RAW_IPR_PALtemp18, // usp - RAW_IPR_PALtemp19, // ksp - RAW_IPR_PALtemp20, // PTBR - RAW_IPR_PALtemp21, // entMM - RAW_IPR_PALtemp22, // kgp - RAW_IPR_PALtemp23, // PCBB - - RAW_IPR_DTB_ASN, // DTLB address space number register - RAW_IPR_DTB_CM, // DTLB current mode register - RAW_IPR_DTB_TAG, // DTLB tag register - RAW_IPR_DTB_PTE, // DTLB page table entry register - - RAW_IPR_VA, // fault virtual address register - RAW_IPR_VA_FORM, // formatted virtual address register - RAW_IPR_MVPTBR, // MTU virtual page table base register - RAW_IPR_DTB_IS, // DTLB invalidate single register - RAW_IPR_CC, // cycle counter register - RAW_IPR_CC_CTL, // cycle counter control register - RAW_IPR_MCSR, // MTU control register - - RAW_IPR_DC_PERR_STAT, // Dcache parity error status register - RAW_IPR_DC_TEST_CTL, // Dcache test tag control register - RAW_IPR_DC_TEST_TAG, // Dcache test tag register - RAW_IPR_DC_TEST_TAG_TEMP, // Dcache test tag temporary register - RAW_IPR_DC_MODE, // Dcache mode register - RAW_IPR_MAF_MODE // miss address file mode register -}; - -int IprToMiscRegIndex[MaxInternalProcRegs]; - -void -initializeIprTable() -{ - static bool initialized = false; - if (initialized) - return; - - memset(IprToMiscRegIndex, -1, MaxInternalProcRegs * sizeof(int)); - - for (int x = 0; x < NumInternalProcRegs; x++) - IprToMiscRegIndex[MiscRegIndexToIpr[x]] = x; -} - -} // namespace AlphaISA - diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/isa.hh --- a/src/arch/alpha/isa.hh Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,134 +0,0 @@ -/* - * Copyright (c) 2009 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - */ - -#ifndef __ARCH_ALPHA_ISA_HH__ -#define __ARCH_ALPHA_ISA_HH__ - -#include -#include -#include - -#include "arch/alpha/registers.hh" -#include "arch/alpha/types.hh" -#include "base/types.hh" -#include "sim/sim_object.hh" -#include "sim/system.hh" - -struct AlphaISAParams; -class BaseCPU; -class Checkpoint; -class EventManager; -class ThreadContext; - -namespace AlphaISA -{ - class ISA : public SimObject - { - public: - typedef uint64_t InternalProcReg; - typedef AlphaISAParams Params; - - protected: - // Parent system - System *system; - - uint64_t fpcr; // floating point condition codes - uint64_t uniq; // process-unique register - bool lock_flag; // lock flag for LL/SC - Addr lock_addr; // lock address for LL/SC - int intr_flag; - - InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs - - protected: - InternalProcReg readIpr(int idx, ThreadContext *tc); - void setIpr(int idx, InternalProcReg val, ThreadContext *tc); - - public: - - MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const; - MiscReg readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid = 0); - - void setMiscRegNoEffect(int misc_reg, const MiscReg &val, - ThreadID tid = 0); - void setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc, - ThreadID tid = 0); - - void - clear() - { - fpcr = 0; - uniq = 0; - lock_flag = 0; - lock_addr = 0; - intr_flag = 0; - memset(ipr, 0, sizeof(ipr)); - } - - void serialize(CheckpointOut &cp) const override; - void unserialize(CheckpointIn &cp) override; - - int - flattenIntIndex(int reg) const - { - return reg; - } - - int - flattenFloatIndex(int reg) const - { - return reg; - } - - // dummy - int - flattenCCIndex(int reg) const - { - return reg; - } - - int - flattenMiscIndex(int reg) const - { - return reg; - } - - const Params *params() const; - - ISA(Params *p); - - void startup(ThreadContext *tc) {} - - /// Explicitly import the otherwise hidden startup - using SimObject::startup; - }; -} - -#endif diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/isa.cc --- a/src/arch/alpha/isa.cc Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,173 +0,0 @@ -/* - * Copyright (c) 2009 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - */ - -#include - -#include "arch/alpha/isa.hh" -#include "base/misc.hh" -#include "cpu/thread_context.hh" -#include "params/AlphaISA.hh" -#include "sim/serialize.hh" - -namespace AlphaISA -{ - -ISA::ISA(Params *p) - : SimObject(p), system(p->system) -{ - clear(); - initializeIprTable(); -} - -const AlphaISAParams * -ISA::params() const -{ - return dynamic_cast(_params); -} - -void -ISA::serialize(CheckpointOut &cp) const -{ - SERIALIZE_SCALAR(fpcr); - SERIALIZE_SCALAR(uniq); - SERIALIZE_SCALAR(lock_flag); - SERIALIZE_SCALAR(lock_addr); - SERIALIZE_ARRAY(ipr, NumInternalProcRegs); -} - -void -ISA::unserialize(CheckpointIn &cp) -{ - UNSERIALIZE_SCALAR(fpcr); - UNSERIALIZE_SCALAR(uniq); - UNSERIALIZE_SCALAR(lock_flag); - UNSERIALIZE_SCALAR(lock_addr); - UNSERIALIZE_ARRAY(ipr, NumInternalProcRegs); -} - - -MiscReg -ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid) const -{ - switch (misc_reg) { - case MISCREG_FPCR: - return fpcr; - case MISCREG_UNIQ: - return uniq; - case MISCREG_LOCKFLAG: - return lock_flag; - case MISCREG_LOCKADDR: - return lock_addr; - case MISCREG_INTR: - return intr_flag; - default: - assert(misc_reg < NumInternalProcRegs); - return ipr[misc_reg]; - } -} - -MiscReg -ISA::readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid) -{ - switch (misc_reg) { - case MISCREG_FPCR: - return fpcr; - case MISCREG_UNIQ: - return uniq; - case MISCREG_LOCKFLAG: - return lock_flag; - case MISCREG_LOCKADDR: - return lock_addr; - case MISCREG_INTR: - return intr_flag; - default: - return readIpr(misc_reg, tc); - } -} - -void -ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid) -{ - switch (misc_reg) { - case MISCREG_FPCR: - fpcr = val; - return; - case MISCREG_UNIQ: - uniq = val; - return; - case MISCREG_LOCKFLAG: - lock_flag = val; - return; - case MISCREG_LOCKADDR: - lock_addr = val; - return; - case MISCREG_INTR: - intr_flag = val; - return; - default: - assert(misc_reg < NumInternalProcRegs); - ipr[misc_reg] = val; - return; - } -} - -void -ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc, - ThreadID tid) -{ - switch (misc_reg) { - case MISCREG_FPCR: - fpcr = val; - return; - case MISCREG_UNIQ: - uniq = val; - return; - case MISCREG_LOCKFLAG: - lock_flag = val; - return; - case MISCREG_LOCKADDR: - lock_addr = val; - return; - case MISCREG_INTR: - intr_flag = val; - return; - default: - setIpr(misc_reg, val, tc); - return; - } -} - -} - -AlphaISA::ISA * -AlphaISAParams::create() -{ - return new AlphaISA::ISA(this); -} diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/isa/branch.isa --- a/src/arch/alpha/isa/branch.isa Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,280 +0,0 @@ -// -*- mode:c++ -*- - -// Copyright (c) 2003-2005 The Regents of The University of Michigan -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are -// met: redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer; -// redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution; -// neither the name of the copyright holders nor the names of its -// contributors may be used to endorse or promote products derived from -// this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// Authors: Steve Reinhardt - -//////////////////////////////////////////////////////////////////// -// -// Control transfer instructions -// - -output header {{ - - /** - * Base class for instructions whose disassembly is not purely a - * function of the machine instruction (i.e., it depends on the - * PC). This class overrides the disassemble() method to check - * the PC and symbol table values before re-using a cached - * disassembly string. This is necessary for branches and jumps, - * where the disassembly string includes the target address (which - * may depend on the PC and/or symbol table). - */ - class PCDependentDisassembly : public AlphaStaticInst - { - protected: - /// Cached program counter from last disassembly - mutable Addr cachedPC; - /// Cached symbol table pointer from last disassembly - mutable const SymbolTable *cachedSymtab; - - /// Constructor - PCDependentDisassembly(const char *mnem, ExtMachInst _machInst, - OpClass __opClass) - : AlphaStaticInst(mnem, _machInst, __opClass), - cachedPC(0), cachedSymtab(0) - { - } - - const std::string & - disassemble(Addr pc, const SymbolTable *symtab) const; - }; - - /** - * Base class for branches (PC-relative control transfers), - * conditional or unconditional. - */ - class Branch : public PCDependentDisassembly - { - protected: - /// Displacement to target address (signed). - int32_t disp; - - /// Constructor. - Branch(const char *mnem, ExtMachInst _machInst, OpClass __opClass) - : PCDependentDisassembly(mnem, _machInst, __opClass), - disp(BRDISP << 2) - { - } - - AlphaISA::PCState branchTarget(const AlphaISA::PCState &branchPC) const; - - /// Explicitly import the otherwise hidden branchTarget - using StaticInst::branchTarget; - - std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const; - }; - - /** - * Base class for jumps (register-indirect control transfers). In - * the Alpha ISA, these are always unconditional. - */ - class Jump : public PCDependentDisassembly - { - protected: - - /// Displacement to target address (signed). - int32_t disp; - - public: - /// Constructor - Jump(const char *mnem, ExtMachInst _machInst, OpClass __opClass) - : PCDependentDisassembly(mnem, _machInst, __opClass), - disp(BRDISP) - { - } - - AlphaISA::PCState branchTarget(ThreadContext *tc) const; - - /// Explicitly import the otherwise hidden branchTarget - using StaticInst::branchTarget; - - std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const; - }; -}}; - -output decoder {{ - AlphaISA::PCState - Branch::branchTarget(const AlphaISA::PCState &branchPC) const - { - return branchPC.pc() + 4 + disp; - } - - AlphaISA::PCState - Jump::branchTarget(ThreadContext *tc) const - { - PCState pc = tc->pcState(); - uint64_t Rb = tc->readIntReg(_srcRegIdx[0]); - pc.set((Rb & ~3) | (pc.pc() & 1)); - return pc; - } - - const std::string & - PCDependentDisassembly::disassemble(Addr pc, - const SymbolTable *symtab) const - { - if (!cachedDisassembly || - pc != cachedPC || symtab != cachedSymtab) - { - if (cachedDisassembly) - delete cachedDisassembly; - - cachedDisassembly = - new std::string(generateDisassembly(pc, symtab)); - cachedPC = pc; - cachedSymtab = symtab; - } - - return *cachedDisassembly; - } - - std::string - Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const - { - std::stringstream ss; - - ccprintf(ss, "%-10s ", mnemonic); - - // There's only one register arg (RA), but it could be - // either a source (the condition for conditional - // branches) or a destination (the link reg for - // unconditional branches) - if (_numSrcRegs > 0) { - printReg(ss, _srcRegIdx[0]); - ss << ","; - } - else if (_numDestRegs > 0) { - printReg(ss, _destRegIdx[0]); - ss << ","; - } - -#ifdef SS_COMPATIBLE_DISASSEMBLY - if (_numSrcRegs == 0 && _numDestRegs == 0) { - printReg(ss, 31); - ss << ","; - } -#endif - - Addr target = pc + 4 + disp; - - std::string str; - if (symtab && symtab->findSymbol(target, str)) - ss << str; - else - ccprintf(ss, "0x%x", target); - - return ss.str(); - } - - std::string - Jump::generateDisassembly(Addr pc, const SymbolTable *symtab) const - { - std::stringstream ss; - - ccprintf(ss, "%-10s ", mnemonic); - -#ifdef SS_COMPATIBLE_DISASSEMBLY - if (_numDestRegs == 0) { - printReg(ss, 31); - ss << ","; - } -#endif - - if (_numDestRegs > 0) { - printReg(ss, _destRegIdx[0]); - ss << ","; - } - - ccprintf(ss, "(r%d)", RB); - - return ss.str(); - } -}}; - -def template JumpOrBranchDecode {{ - return (RA == 31) - ? (StaticInst *)new %(class_name)s(machInst) - : (StaticInst *)new %(class_name)sAndLink(machInst); -}}; - -def format CondBranch(code) {{ - code = ''' - bool cond; - %(code)s; - if (cond) - NPC = NPC + disp; - else - NPC = NPC; - ''' % { "code" : code } - iop = InstObjParams(name, Name, 'Branch', code, - ('IsDirectControl', 'IsCondControl')) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - decode_block = BasicDecode.subst(iop) - exec_output = BasicExecute.subst(iop) -}}; - -let {{ -def UncondCtrlBase(name, Name, base_class, npc_expr, flags): - # Declare basic control transfer w/o link (i.e. link reg is R31) - nolink_code = 'NPC = %s;\n' % npc_expr - nolink_iop = InstObjParams(name, Name, base_class, - nolink_code, flags) - header_output = BasicDeclare.subst(nolink_iop) - decoder_output = BasicConstructor.subst(nolink_iop) - exec_output = BasicExecute.subst(nolink_iop) - - # Generate declaration of '*AndLink' version, append to decls - link_code = 'Ra = NPC & ~3;\n' + nolink_code - link_iop = InstObjParams(name, Name + 'AndLink', base_class, - link_code, flags) - header_output += BasicDeclare.subst(link_iop) - decoder_output += BasicConstructor.subst(link_iop) - exec_output += BasicExecute.subst(link_iop) - - # need to use link_iop for the decode template since it is expecting - # the shorter version of class_name (w/o "AndLink") - - return (header_output, decoder_output, - JumpOrBranchDecode.subst(nolink_iop), exec_output) -}}; - -def format UncondBranch(*flags) {{ - flags += ('IsUncondControl', 'IsDirectControl') - (header_output, decoder_output, decode_block, exec_output) = \ - UncondCtrlBase(name, Name, 'Branch', 'NPC + disp', flags) -}}; - -def format Jump(*flags) {{ - flags += ('IsUncondControl', 'IsIndirectControl') - (header_output, decoder_output, decode_block, exec_output) = \ - UncondCtrlBase(name, Name, 'Jump', '(Rb & ~3) | (NPC & 1)', flags) -}}; - - diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/isa/decoder.isa --- a/src/arch/alpha/isa/decoder.isa Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,1084 +0,0 @@ -// -*- mode:c++ -*- - -// Copyright (c) 2013 ARM Limited -// All rights reserved -// -// The license below extends only to copyright in the software and shall -// not be construed as granting a license to any other intellectual -// property including but not limited to intellectual property relating -// to a hardware implementation of the functionality of the software -// licensed hereunder. You may use the software subject to the license -// terms below provided that you ensure that this notice is replicated -// unmodified and in its entirety in all distributions of the software, -// modified or unmodified, in source code or in binary form. -// -// Copyright (c) 2003-2006 The Regents of The University of Michigan -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are -// met: redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer; -// redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution; -// neither the name of the copyright holders nor the names of its -// contributors may be used to endorse or promote products derived from -// this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// Authors: Steve Reinhardt - -//////////////////////////////////////////////////////////////////// -// -// The actual decoder specification -// - -decode OPCODE default Unknown::unknown() { - - format LoadAddress { - 0x08: lda({{ Ra = Rb + disp; }}); - 0x09: ldah({{ Ra = Rb + (disp << 16); }}); - } - - format LoadOrNop { - 0x0a: ldbu({{ Ra_uq = Mem_ub; }}); - 0x0c: ldwu({{ Ra_uq = Mem_uw; }}); - 0x0b: ldq_u({{ Ra = Mem_uq; }}, ea_code = {{ EA = (Rb + disp) & ~7; }}); - 0x23: ldt({{ Fa = Mem_df; }}); - 0x2a: ldl_l({{ Ra_sl = Mem_sl; }}, mem_flags = LLSC); - 0x2b: ldq_l({{ Ra_uq = Mem_uq; }}, mem_flags = LLSC); - } - - format LoadOrPrefetch { - 0x28: ldl({{ Ra_sl = Mem_sl; }}); - 0x29: ldq({{ Ra_uq = Mem_uq; }}, pf_flags = EVICT_NEXT); - // IsFloating flag on lds gets the prefetch to disassemble - // using f31 instead of r31... funcitonally it's unnecessary - 0x22: lds({{ Fa_uq = s_to_t(Mem_ul); }}, - pf_flags = PF_EXCLUSIVE, inst_flags = IsFloating); - } - - format Store { - 0x0e: stb({{ Mem_ub = Ra<7:0>; }}); - 0x0d: stw({{ Mem_uw = Ra<15:0>; }}); - 0x2c: stl({{ Mem_ul = Ra<31:0>; }}); - 0x2d: stq({{ Mem_uq = Ra_uq; }}); - 0x0f: stq_u({{ Mem_uq = Ra_uq; }}, {{ EA = (Rb + disp) & ~7; }}); - 0x26: sts({{ Mem_ul = t_to_s(Fa_uq); }}); - 0x27: stt({{ Mem_df = Fa; }}); - } - - format StoreCond { - 0x2e: stl_c({{ Mem_ul = Ra<31:0>; }}, - {{ - uint64_t tmp = write_result; - // see stq_c - Ra = (tmp == 0 || tmp == 1) ? tmp : Ra; - if (tmp == 1) { - xc->setStCondFailures(0); - } - }}, mem_flags = LLSC, inst_flags = IsStoreConditional); - 0x2f: stq_c({{ Mem_uq = Ra; }}, - {{ - uint64_t tmp = write_result; - // If the write operation returns 0 or 1, then - // this was a conventional store conditional, - // and the value indicates the success/failure - // of the operation. If another value is - // returned, then this was a Turbolaser - // mailbox access, and we don't update the - // result register at all. - Ra = (tmp == 0 || tmp == 1) ? tmp : Ra; - if (tmp == 1) { - // clear failure counter... this is - // non-architectural and for debugging - // only. - xc->setStCondFailures(0); - } - }}, mem_flags = LLSC, inst_flags = IsStoreConditional); - } - - format IntegerOperate { - - 0x10: decode INTFUNC { // integer arithmetic operations - - 0x00: addl({{ Rc_sl = Ra_sl + Rb_or_imm_sl; }}); - 0x40: addlv({{ - int32_t tmp = Ra_sl + Rb_or_imm_sl; - // signed overflow occurs when operands have same sign - // and sign of result does not match. - if (Ra_sl<31:> == Rb_or_imm_sl<31:> && tmp<31:> != Ra_sl<31:>) - fault = std::make_shared(); - Rc_sl = tmp; - }}); - 0x02: s4addl({{ Rc_sl = (Ra_sl << 2) + Rb_or_imm_sl; }}); - 0x12: s8addl({{ Rc_sl = (Ra_sl << 3) + Rb_or_imm_sl; }}); - - 0x20: addq({{ Rc = Ra + Rb_or_imm; }}); - 0x60: addqv({{ - uint64_t tmp = Ra + Rb_or_imm; - // signed overflow occurs when operands have same sign - // and sign of result does not match. - if (Ra<63:> == Rb_or_imm<63:> && tmp<63:> != Ra<63:>) - fault = std::make_shared(); - Rc = tmp; - }}); - 0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }}); - 0x32: s8addq({{ Rc = (Ra << 3) + Rb_or_imm; }}); - - 0x09: subl({{ Rc_sl = Ra_sl - Rb_or_imm_sl; }}); - 0x49: sublv({{ - int32_t tmp = Ra_sl - Rb_or_imm_sl; - // signed overflow detection is same as for add, - // except we need to look at the *complemented* - // sign bit of the subtrahend (Rb), i.e., if the initial - // signs are the *same* then no overflow can occur - if (Ra_sl<31:> != Rb_or_imm_sl<31:> && tmp<31:> != Ra_sl<31:>) - fault = std::make_shared(); - Rc_sl = tmp; - }}); - 0x0b: s4subl({{ Rc_sl = (Ra_sl << 2) - Rb_or_imm_sl; }}); - 0x1b: s8subl({{ Rc_sl = (Ra_sl << 3) - Rb_or_imm_sl; }}); - - 0x29: subq({{ Rc = Ra - Rb_or_imm; }}); - 0x69: subqv({{ - uint64_t tmp = Ra - Rb_or_imm; - // signed overflow detection is same as for add, - // except we need to look at the *complemented* - // sign bit of the subtrahend (Rb), i.e., if the initial - // signs are the *same* then no overflow can occur - if (Ra<63:> != Rb_or_imm<63:> && tmp<63:> != Ra<63:>) - fault = std::make_shared(); - Rc = tmp; - }}); - 0x2b: s4subq({{ Rc = (Ra << 2) - Rb_or_imm; }}); - 0x3b: s8subq({{ Rc = (Ra << 3) - Rb_or_imm; }}); - - 0x2d: cmpeq({{ Rc = (Ra == Rb_or_imm); }}); - 0x6d: cmple({{ Rc = (Ra_sq <= Rb_or_imm_sq); }}); - 0x4d: cmplt({{ Rc = (Ra_sq < Rb_or_imm_sq); }}); - 0x3d: cmpule({{ Rc = (Ra_uq <= Rb_or_imm_uq); }}); - 0x1d: cmpult({{ Rc = (Ra_uq < Rb_or_imm_uq); }}); - - 0x0f: cmpbge({{ - int hi = 7; - int lo = 0; - uint64_t tmp = 0; - for (int i = 0; i < 8; ++i) { - tmp |= (Ra_uq >= Rb_or_imm_uq) << i; - hi += 8; - lo += 8; - } - Rc = tmp; - }}); - } - - 0x11: decode INTFUNC { // integer logical operations - - 0x00: and({{ Rc = Ra & Rb_or_imm; }}); - 0x08: bic({{ Rc = Ra & ~Rb_or_imm; }}); - 0x20: bis({{ Rc = Ra | Rb_or_imm; }}); - 0x28: ornot({{ Rc = Ra | ~Rb_or_imm; }}); - 0x40: xor({{ Rc = Ra ^ Rb_or_imm; }}); - 0x48: eqv({{ Rc = Ra ^ ~Rb_or_imm; }}); - - // conditional moves - 0x14: cmovlbs({{ Rc = ((Ra & 1) == 1) ? Rb_or_imm : Rc; }}); - 0x16: cmovlbc({{ Rc = ((Ra & 1) == 0) ? Rb_or_imm : Rc; }}); - 0x24: cmoveq({{ Rc = (Ra == 0) ? Rb_or_imm : Rc; }}); - 0x26: cmovne({{ Rc = (Ra != 0) ? Rb_or_imm : Rc; }}); - 0x44: cmovlt({{ Rc = (Ra_sq < 0) ? Rb_or_imm : Rc; }}); - 0x46: cmovge({{ Rc = (Ra_sq >= 0) ? Rb_or_imm : Rc; }}); - 0x64: cmovle({{ Rc = (Ra_sq <= 0) ? Rb_or_imm : Rc; }}); - 0x66: cmovgt({{ Rc = (Ra_sq > 0) ? Rb_or_imm : Rc; }}); - - // For AMASK, RA must be R31. - 0x61: decode RA { - 31: amask({{ Rc = Rb_or_imm & ~ULL(0x17); }}); - } - - // For IMPLVER, RA must be R31 and the B operand - // must be the immediate value 1. - 0x6c: decode RA { - 31: decode IMM { - 1: decode INTIMM { - // return EV5 for FullSystem and EV6 otherwise - 1: implver({{ Rc = FullSystem ? 1 : 2 }}); - } - } - } - - // The mysterious 11.25... - 0x25: WarnUnimpl::eleven25(); - } - - 0x12: decode INTFUNC { - 0x39: sll({{ Rc = Ra << Rb_or_imm<5:0>; }}); - 0x34: srl({{ Rc = Ra_uq >> Rb_or_imm<5:0>; }}); - 0x3c: sra({{ Rc = Ra_sq >> Rb_or_imm<5:0>; }}); - - 0x02: mskbl({{ Rc = Ra & ~(mask( 8) << (Rb_or_imm<2:0> * 8)); }}); - 0x12: mskwl({{ Rc = Ra & ~(mask(16) << (Rb_or_imm<2:0> * 8)); }}); - 0x22: mskll({{ Rc = Ra & ~(mask(32) << (Rb_or_imm<2:0> * 8)); }}); - 0x32: mskql({{ Rc = Ra & ~(mask(64) << (Rb_or_imm<2:0> * 8)); }}); - - 0x52: mskwh({{ - int bv = Rb_or_imm<2:0>; - Rc = bv ? (Ra & ~(mask(16) >> (64 - 8 * bv))) : Ra; - }}); - 0x62: msklh({{ - int bv = Rb_or_imm<2:0>; - Rc = bv ? (Ra & ~(mask(32) >> (64 - 8 * bv))) : Ra; - }}); - 0x72: mskqh({{ - int bv = Rb_or_imm<2:0>; - Rc = bv ? (Ra & ~(mask(64) >> (64 - 8 * bv))) : Ra; - }}); - - 0x06: extbl({{ Rc = (Ra_uq >> (Rb_or_imm<2:0> * 8))< 7:0>; }}); - 0x16: extwl({{ Rc = (Ra_uq >> (Rb_or_imm<2:0> * 8))<15:0>; }}); - 0x26: extll({{ Rc = (Ra_uq >> (Rb_or_imm<2:0> * 8))<31:0>; }}); - 0x36: extql({{ Rc = (Ra_uq >> (Rb_or_imm<2:0> * 8)); }}); - - 0x5a: extwh({{ - Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<15:0>; }}); - 0x6a: extlh({{ - Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>)<31:0>; }}); - 0x7a: extqh({{ - Rc = (Ra << (64 - (Rb_or_imm<2:0> * 8))<5:0>); }}); - - 0x0b: insbl({{ Rc = Ra< 7:0> << (Rb_or_imm<2:0> * 8); }}); - 0x1b: inswl({{ Rc = Ra<15:0> << (Rb_or_imm<2:0> * 8); }}); - 0x2b: insll({{ Rc = Ra<31:0> << (Rb_or_imm<2:0> * 8); }}); - 0x3b: insql({{ Rc = Ra << (Rb_or_imm<2:0> * 8); }}); - - 0x57: inswh({{ - int bv = Rb_or_imm<2:0>; - Rc = bv ? (Ra_uq<15:0> >> (64 - 8 * bv)) : 0; - }}); - 0x67: inslh({{ - int bv = Rb_or_imm<2:0>; - Rc = bv ? (Ra_uq<31:0> >> (64 - 8 * bv)) : 0; - }}); - 0x77: insqh({{ - int bv = Rb_or_imm<2:0>; - Rc = bv ? (Ra_uq >> (64 - 8 * bv)) : 0; - }}); - - 0x30: zap({{ - uint64_t zapmask = 0; - for (int i = 0; i < 8; ++i) { - if (Rb_or_imm) - zapmask |= (mask(8) << (i * 8)); - } - Rc = Ra & ~zapmask; - }}); - 0x31: zapnot({{ - uint64_t zapmask = 0; - for (int i = 0; i < 8; ++i) { - if (!Rb_or_imm) - zapmask |= (mask(8) << (i * 8)); - } - Rc = Ra & ~zapmask; - }}); - } - - 0x13: decode INTFUNC { // integer multiplies - 0x00: mull({{ Rc_sl = Ra_sl * Rb_or_imm_sl; }}, IntMultOp); - 0x20: mulq({{ Rc = Ra * Rb_or_imm; }}, IntMultOp); - 0x30: umulh({{ - uint64_t hi, lo; - mul128(Ra, Rb_or_imm, hi, lo); - Rc = hi; - }}, IntMultOp); - 0x40: mullv({{ - // 32-bit multiply with trap on overflow - int64_t Rax = Ra_sl; // sign extended version of Ra_sl - int64_t Rbx = Rb_or_imm_sl; - int64_t tmp = Rax * Rbx; - // To avoid overflow, all the upper 32 bits must match - // the sign bit of the lower 32. We code this as - // checking the upper 33 bits for all 0s or all 1s. - uint64_t sign_bits = tmp<63:31>; - if (sign_bits != 0 && sign_bits != mask(33)) - fault = std::make_shared(); - Rc_sl = tmp<31:0>; - }}, IntMultOp); - 0x60: mulqv({{ - // 64-bit multiply with trap on overflow - uint64_t hi, lo; - mul128(Ra, Rb_or_imm, hi, lo); - // all the upper 64 bits must match the sign bit of - // the lower 64 - if (!((hi == 0 && lo<63:> == 0) || - (hi == mask(64) && lo<63:> == 1))) - fault = std::make_shared(); - Rc = lo; - }}, IntMultOp); - } - - 0x1c: decode INTFUNC { - 0x00: decode RA { 31: sextb({{ Rc_sb = Rb_or_imm< 7:0>; }}); } - 0x01: decode RA { 31: sextw({{ Rc_sw = Rb_or_imm<15:0>; }}); } - - 0x30: ctpop({{ - uint64_t count = 0; - for (int i = 0; Rb<63:i>; ++i) { - if (Rb == 0x1) - ++count; - } - Rc = count; - }}, IntAluOp); - - 0x31: perr({{ - uint64_t temp = 0; - int hi = 7; - int lo = 0; - for (int i = 0; i < 8; ++i) { - uint8_t ra_ub = Ra_uq; - uint8_t rb_ub = Rb_uq; - temp += (ra_ub >= rb_ub) ? - (ra_ub - rb_ub) : (rb_ub - ra_ub); - hi += 8; - lo += 8; - } - Rc = temp; - }}); - - 0x32: ctlz({{ - uint64_t count = 0; - uint64_t temp = Rb; - if (temp<63:32>) temp >>= 32; else count += 32; - if (temp<31:16>) temp >>= 16; else count += 16; - if (temp<15:8>) temp >>= 8; else count += 8; - if (temp<7:4>) temp >>= 4; else count += 4; - if (temp<3:2>) temp >>= 2; else count += 2; - if (temp<1:1>) temp >>= 1; else count += 1; - if ((temp<0:0>) != 0x1) count += 1; - Rc = count; - }}, IntAluOp); - - 0x33: cttz({{ - uint64_t count = 0; - uint64_t temp = Rb; - if (!(temp<31:0>)) { temp >>= 32; count += 32; } - if (!(temp<15:0>)) { temp >>= 16; count += 16; } - if (!(temp<7:0>)) { temp >>= 8; count += 8; } - if (!(temp<3:0>)) { temp >>= 4; count += 4; } - if (!(temp<1:0>)) { temp >>= 2; count += 2; } - if (!(temp<0:0> & ULL(0x1))) { - temp >>= 1; count += 1; - } - if (!(temp<0:0> & ULL(0x1))) count += 1; - Rc = count; - }}, IntAluOp); - - - 0x34: unpkbw({{ - Rc = (Rb_uq<7:0> - | (Rb_uq<15:8> << 16) - | (Rb_uq<23:16> << 32) - | (Rb_uq<31:24> << 48)); - }}, IntAluOp); - - 0x35: unpkbl({{ - Rc = (Rb_uq<7:0> | (Rb_uq<15:8> << 32)); - }}, IntAluOp); - - 0x36: pkwb({{ - Rc = (Rb_uq<7:0> - | (Rb_uq<23:16> << 8) - | (Rb_uq<39:32> << 16) - | (Rb_uq<55:48> << 24)); - }}, IntAluOp); - - 0x37: pklb({{ - Rc = (Rb_uq<7:0> | (Rb_uq<39:32> << 8)); - }}, IntAluOp); - - 0x38: minsb8({{ - uint64_t temp = 0; - int hi = 63; - int lo = 56; - for (int i = 7; i >= 0; --i) { - int8_t ra_sb = Ra_uq; - int8_t rb_sb = Rb_uq; - temp = ((temp << 8) - | ((ra_sb < rb_sb) ? Ra_uq - : Rb_uq)); - hi -= 8; - lo -= 8; - } - Rc = temp; - }}); - - 0x39: minsw4({{ - uint64_t temp = 0; - int hi = 63; - int lo = 48; - for (int i = 3; i >= 0; --i) { - int16_t ra_sw = Ra_uq; - int16_t rb_sw = Rb_uq; - temp = ((temp << 16) - | ((ra_sw < rb_sw) ? Ra_uq - : Rb_uq)); - hi -= 16; - lo -= 16; - } - Rc = temp; - }}); - - 0x3a: minub8({{ - uint64_t temp = 0; - int hi = 63; - int lo = 56; - for (int i = 7; i >= 0; --i) { - uint8_t ra_ub = Ra_uq; - uint8_t rb_ub = Rb_uq; - temp = ((temp << 8) - | ((ra_ub < rb_ub) ? Ra_uq - : Rb_uq)); - hi -= 8; - lo -= 8; - } - Rc = temp; - }}); - - 0x3b: minuw4({{ - uint64_t temp = 0; - int hi = 63; - int lo = 48; - for (int i = 3; i >= 0; --i) { - uint16_t ra_sw = Ra_uq; - uint16_t rb_sw = Rb_uq; - temp = ((temp << 16) - | ((ra_sw < rb_sw) ? Ra_uq - : Rb_uq)); - hi -= 16; - lo -= 16; - } - Rc = temp; - }}); - - 0x3c: maxub8({{ - uint64_t temp = 0; - int hi = 63; - int lo = 56; - for (int i = 7; i >= 0; --i) { - uint8_t ra_ub = Ra_uq; - uint8_t rb_ub = Rb_uq; - temp = ((temp << 8) - | ((ra_ub > rb_ub) ? Ra_uq - : Rb_uq)); - hi -= 8; - lo -= 8; - } - Rc = temp; - }}); - - 0x3d: maxuw4({{ - uint64_t temp = 0; - int hi = 63; - int lo = 48; - for (int i = 3; i >= 0; --i) { - uint16_t ra_uw = Ra_uq; - uint16_t rb_uw = Rb_uq; - temp = ((temp << 16) - | ((ra_uw > rb_uw) ? Ra_uq - : Rb_uq)); - hi -= 16; - lo -= 16; - } - Rc = temp; - }}); - - 0x3e: maxsb8({{ - uint64_t temp = 0; - int hi = 63; - int lo = 56; - for (int i = 7; i >= 0; --i) { - int8_t ra_sb = Ra_uq; - int8_t rb_sb = Rb_uq; - temp = ((temp << 8) - | ((ra_sb > rb_sb) ? Ra_uq - : Rb_uq)); - hi -= 8; - lo -= 8; - } - Rc = temp; - }}); - - 0x3f: maxsw4({{ - uint64_t temp = 0; - int hi = 63; - int lo = 48; - for (int i = 3; i >= 0; --i) { - int16_t ra_sw = Ra_uq; - int16_t rb_sw = Rb_uq; - temp = ((temp << 16) - | ((ra_sw > rb_sw) ? Ra_uq - : Rb_uq)); - hi -= 16; - lo -= 16; - } - Rc = temp; - }}); - - format BasicOperateWithNopCheck { - 0x70: decode RB { - 31: ftoit({{ Rc = Fa_uq; }}, FloatCvtOp); - } - 0x78: decode RB { - 31: ftois({{ Rc_sl = t_to_s(Fa_uq); }}, - FloatCvtOp); - } - } - } - } - - // Conditional branches. - format CondBranch { - 0x39: beq({{ cond = (Ra == 0); }}); - 0x3d: bne({{ cond = (Ra != 0); }}); - 0x3e: bge({{ cond = (Ra_sq >= 0); }}); - 0x3f: bgt({{ cond = (Ra_sq > 0); }}); - 0x3b: ble({{ cond = (Ra_sq <= 0); }}); - 0x3a: blt({{ cond = (Ra_sq < 0); }}); - 0x38: blbc({{ cond = ((Ra & 1) == 0); }}); - 0x3c: blbs({{ cond = ((Ra & 1) == 1); }}); - - 0x31: fbeq({{ cond = (Fa == 0); }}); - 0x35: fbne({{ cond = (Fa != 0); }}); - 0x36: fbge({{ cond = (Fa >= 0); }}); - 0x37: fbgt({{ cond = (Fa > 0); }}); - 0x33: fble({{ cond = (Fa <= 0); }}); - 0x32: fblt({{ cond = (Fa < 0); }}); - } - - // unconditional branches - format UncondBranch { - 0x30: br(); - 0x34: bsr(IsCall); - } - - // indirect branches - 0x1a: decode JMPFUNC { - format Jump { - 0: jmp(); - 1: jsr(IsCall); - 2: ret(IsReturn); - 3: jsr_coroutine(IsCall, IsReturn); - } - } - - // Square root and integer-to-FP moves - 0x14: decode FP_SHORTFUNC { - // Integer to FP register moves must have RB == 31 - 0x4: decode RB { - 31: decode FP_FULLFUNC { - format BasicOperateWithNopCheck { - 0x004: itofs({{ Fc_uq = s_to_t(Ra_ul); }}, FloatCvtOp); - 0x024: itoft({{ Fc_uq = Ra_uq; }}, FloatCvtOp); - 0x014: FailUnimpl::itoff(); // VAX-format conversion - } - } - } - - // Square root instructions must have FA == 31 - 0xb: decode FA { - 31: decode FP_TYPEFUNC { - format FloatingPointOperate { -#if SS_COMPATIBLE_FP - 0x0b: sqrts({{ - if (Fb < 0.0) - fault = std::make_shared(); - Fc = sqrt(Fb); - }}, FloatSqrtOp); -#else - 0x0b: sqrts({{ - if (Fb_sf < 0.0) - fault = std::make_shared(); - Fc_sf = sqrt(Fb_sf); - }}, FloatSqrtOp); -#endif - 0x2b: sqrtt({{ - if (Fb < 0.0) - fault = std::make_shared(); - Fc = sqrt(Fb); - }}, FloatSqrtOp); - } - } - } - - // VAX-format sqrtf and sqrtg are not implemented - 0xa: FailUnimpl::sqrtfg(); - } - - // IEEE floating point - 0x16: decode FP_SHORTFUNC_TOP2 { - // The top two bits of the short function code break this - // space into four groups: binary ops, compares, reserved, and - // conversions. See Table 4-12 of AHB. There are different - // special cases in these different groups, so we decode on - // these top two bits first just to select a decode strategy. - // Most of these instructions may have various trapping and - // rounding mode flags set; these are decoded in the - // FloatingPointDecode template used by the - // FloatingPointOperate format. - - // add/sub/mul/div: just decode on the short function code - // and source type. All valid trapping and rounding modes apply. - 0: decode FP_TRAPMODE { - // check for valid trapping modes here - 0,1,5,7: decode FP_TYPEFUNC { - format FloatingPointOperate { -#if SS_COMPATIBLE_FP - 0x00: adds({{ Fc = Fa + Fb; }}); - 0x01: subs({{ Fc = Fa - Fb; }}); - 0x02: muls({{ Fc = Fa * Fb; }}, FloatMultOp); - 0x03: divs({{ Fc = Fa / Fb; }}, FloatDivOp); -#else - 0x00: adds({{ Fc_sf = Fa_sf + Fb_sf; }}); - 0x01: subs({{ Fc_sf = Fa_sf - Fb_sf; }}); - 0x02: muls({{ Fc_sf = Fa_sf * Fb_sf; }}, FloatMultOp); - 0x03: divs({{ Fc_sf = Fa_sf / Fb_sf; }}, FloatDivOp); -#endif - - 0x20: addt({{ Fc = Fa + Fb; }}); - 0x21: subt({{ Fc = Fa - Fb; }}); - 0x22: mult({{ Fc = Fa * Fb; }}, FloatMultOp); - 0x23: divt({{ Fc = Fa / Fb; }}, FloatDivOp); - } - } - } - - // Floating-point compare instructions must have the default - // rounding mode, and may use the default trapping mode or - // /SU. Both trapping modes are treated the same by M5; the - // only difference on the real hardware (as far a I can tell) - // is that without /SU you'd get an imprecise trap if you - // tried to compare a NaN with something else (instead of an - // "unordered" result). - 1: decode FP_FULLFUNC { - format BasicOperateWithNopCheck { - 0x0a5, 0x5a5: cmpteq({{ Fc = (Fa == Fb) ? 2.0 : 0.0; }}, - FloatCmpOp); - 0x0a7, 0x5a7: cmptle({{ Fc = (Fa <= Fb) ? 2.0 : 0.0; }}, - FloatCmpOp); - 0x0a6, 0x5a6: cmptlt({{ Fc = (Fa < Fb) ? 2.0 : 0.0; }}, - FloatCmpOp); - 0x0a4, 0x5a4: cmptun({{ // unordered - Fc = (!(Fa < Fb) && !(Fa == Fb) && !(Fa > Fb)) ? 2.0 : 0.0; - }}, FloatCmpOp); - } - } - - // The FP-to-integer and integer-to-FP conversion insts - // require that FA be 31. - 3: decode FA { - 31: decode FP_TYPEFUNC { - format FloatingPointOperate { - 0x2f: decode FP_ROUNDMODE { - format FPFixedRounding { - // "chopped" i.e. round toward zero - 0: cvttq({{ Fc_sq = (int64_t)trunc(Fb); }}, - Chopped); - // round to minus infinity - 1: cvttq({{ Fc_sq = (int64_t)floor(Fb); }}, - MinusInfinity); - } - default: cvttq({{ Fc_sq = (int64_t)nearbyint(Fb); }}); - } - - // The cvtts opcode is overloaded to be cvtst if the trap - // mode is 2 or 6 (which are not valid otherwise) - 0x2c: decode FP_FULLFUNC { - format BasicOperateWithNopCheck { - // trap on denorm version "cvtst/s" is - // simulated same as cvtst - 0x2ac, 0x6ac: cvtst({{ Fc = Fb_sf; }}); - } - default: cvtts({{ Fc_sf = Fb; }}); - } - - // The trapping mode for integer-to-FP conversions - // must be /SUI or nothing; /U and /SU are not - // allowed. The full set of rounding modes are - // supported though. - 0x3c: decode FP_TRAPMODE { - 0,7: cvtqs({{ Fc_sf = Fb_sq; }}); - } - 0x3e: decode FP_TRAPMODE { - 0,7: cvtqt({{ Fc = Fb_sq; }}); - } - } - } - } - } - - // misc FP operate - 0x17: decode FP_FULLFUNC { - format BasicOperateWithNopCheck { - 0x010: cvtlq({{ - Fc_sl = (Fb_uq<63:62> << 30) | Fb_uq<58:29>; - }}); - 0x030: cvtql({{ - Fc_uq = (Fb_uq<31:30> << 62) | (Fb_uq<29:0> << 29); - }}); - - // We treat the precise & imprecise trapping versions of - // cvtql identically. - 0x130, 0x530: cvtqlv({{ - // To avoid overflow, all the upper 32 bits must match - // the sign bit of the lower 32. We code this as - // checking the upper 33 bits for all 0s or all 1s. - uint64_t sign_bits = Fb_uq<63:31>; - if (sign_bits != 0 && sign_bits != mask(33)) - fault = std::make_shared(); - Fc_uq = (Fb_uq<31:30> << 62) | (Fb_uq<29:0> << 29); - }}); - - 0x020: cpys({{ // copy sign - Fc_uq = (Fa_uq<63:> << 63) | Fb_uq<62:0>; - }}); - 0x021: cpysn({{ // copy sign negated - Fc_uq = (~Fa_uq<63:> << 63) | Fb_uq<62:0>; - }}); - 0x022: cpyse({{ // copy sign and exponent - Fc_uq = (Fa_uq<63:52> << 52) | Fb_uq<51:0>; - }}); - - 0x02a: fcmoveq({{ Fc = (Fa == 0) ? Fb : Fc; }}); - 0x02b: fcmovne({{ Fc = (Fa != 0) ? Fb : Fc; }}); - 0x02c: fcmovlt({{ Fc = (Fa < 0) ? Fb : Fc; }}); - 0x02d: fcmovge({{ Fc = (Fa >= 0) ? Fb : Fc; }}); - 0x02e: fcmovle({{ Fc = (Fa <= 0) ? Fb : Fc; }}); - 0x02f: fcmovgt({{ Fc = (Fa > 0) ? Fb : Fc; }}); - - 0x024: mt_fpcr({{ FPCR = Fa_uq; }}, IsIprAccess); - 0x025: mf_fpcr({{ Fa_uq = FPCR; }}, IsIprAccess); - } - } - - // miscellaneous mem-format ops - 0x18: decode MEMFUNC { - format WarnUnimpl { - 0x8000: fetch(); - 0xa000: fetch_m(); - 0xe800: ecb(); - } - - format MiscPrefetch { - 0xf800: wh64({{ EA = Rb & ~ULL(63); }}, - {{ ; }}, - mem_flags = PREFETCH); - } - - format BasicOperate { - 0xc000: rpcc({{ - /* Rb is a fake dependency so here is a fun way to get - * the parser to understand that. - */ - uint64_t unused_var M5_VAR_USED = Rb; - Ra = FullSystem ? xc->readMiscReg(IPR_CC) : curTick(); - }}, IsUnverifiable); - - // All of the barrier instructions below do nothing in - // their execute() methods (hence the empty code blocks). - // All of their functionality is hard-coded in the - // pipeline based on the flags IsSerializing, - // IsMemBarrier, and IsWriteBarrier. In the current - // detailed CPU model, the execute() function only gets - // called at fetch, so there's no way to generate pipeline - // behavior at any other stage. Once we go to an - // exec-in-exec CPU model we should be able to get rid of - // these flags and implement this behavior via the - // execute() methods. - - // trapb is just a barrier on integer traps, where excb is - // a barrier on integer and FP traps. "EXCB is thus a - // superset of TRAPB." (Alpha ARM, Sec 4.11.4) We treat - // them the same though. - 0x0000: trapb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass); - 0x0400: excb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass); - 0x4000: mb({{ }}, IsMemBarrier, MemReadOp); - 0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp); - } - - 0xe000: decode FullSystemInt { - 0: FailUnimpl::rc_se(); - default: BasicOperate::rc({{ - Ra = IntrFlag; - IntrFlag = 0; - }}, IsNonSpeculative, IsUnverifiable); - } - 0xf000: decode FullSystemInt { - 0: FailUnimpl::rs_se(); - default: BasicOperate::rs({{ - Ra = IntrFlag; - IntrFlag = 1; - }}, IsNonSpeculative, IsUnverifiable); - } - } - - 0x00: decode FullSystemInt { - 0: decode PALFUNC { - format EmulatedCallPal { - 0x00: halt ({{ - exitSimLoop("halt instruction encountered"); - }}, IsNonSpeculative); - 0x83: callsys({{ - xc->syscall(R0); - }}, IsSerializeAfter, IsNonSpeculative, IsSyscall); - // Read uniq reg into ABI return value register (r0) - 0x9e: rduniq({{ R0 = Runiq; }}, IsIprAccess); - // Write uniq reg with value from ABI arg register (r16) - 0x9f: wruniq({{ Runiq = R16; }}, IsIprAccess); - } - } - default: CallPal::call_pal({{ - if (!palValid || - (palPriv - && xc->readMiscReg(IPR_ICM) != mode_kernel)) { - // invalid pal function code, or attempt to do privileged - // PAL call in non-kernel mode - fault = std::make_shared(); - } else { - // check to see if simulator wants to do something special - // on this PAL call (including maybe suppress it) - bool dopal = xc->simPalCheck(palFunc); - - if (dopal) { - xc->setMiscReg(IPR_EXC_ADDR, NPC); - NPC = xc->readMiscReg(IPR_PAL_BASE) + palOffset; - } - } - }}, IsNonSpeculative); - } - - 0x1b: decode PALMODE { - 0: OpcdecFault::hw_st_quad(); - 1: decode HW_LDST_QUAD { - format HwLoad { - 0: hw_ld({{ EA = (Rb + disp) & ~3; }}, {{ Ra = Mem_ul; }}, - L, IsSerializing, IsSerializeBefore); - 1: hw_ld({{ EA = (Rb + disp) & ~7; }}, {{ Ra = Mem_uq; }}, - Q, IsSerializing, IsSerializeBefore); - } - } - } - - 0x1f: decode PALMODE { - 0: OpcdecFault::hw_st_cond(); - format HwStore { - 1: decode HW_LDST_COND { - 0: decode HW_LDST_QUAD { - 0: hw_st({{ EA = (Rb + disp) & ~3; }}, - {{ Mem_ul = Ra<31:0>; }}, L, IsSerializing, IsSerializeBefore); - 1: hw_st({{ EA = (Rb + disp) & ~7; }}, - {{ Mem_uq = Ra_uq; }}, Q, IsSerializing, IsSerializeBefore); - } - - 1: FailUnimpl::hw_st_cond(); - } - } - } - - 0x19: decode PALMODE { - 0: OpcdecFault::hw_mfpr(); - format HwMoveIPR { - 1: hw_mfpr({{ - int miscRegIndex = (ipr_index < MaxInternalProcRegs) ? - IprToMiscRegIndex[ipr_index] : -1; - if(miscRegIndex < 0 || !IprIsReadable(miscRegIndex) || - miscRegIndex >= NumInternalProcRegs) - fault = std::make_shared(); - else - Ra = xc->readMiscReg(miscRegIndex); - }}, IsIprAccess); - } - } - - 0x1d: decode PALMODE { - 0: OpcdecFault::hw_mtpr(); - format HwMoveIPR { - 1: hw_mtpr({{ - int miscRegIndex = (ipr_index < MaxInternalProcRegs) ? - IprToMiscRegIndex[ipr_index] : -1; - if(miscRegIndex < 0 || !IprIsWritable(miscRegIndex) || - miscRegIndex >= NumInternalProcRegs) - fault = std::make_shared(); - else - xc->setMiscReg(miscRegIndex, Ra); - if (traceData) { traceData->setData(Ra); } - }}, IsIprAccess); - } - } - - 0x1e: decode PALMODE { - 0: OpcdecFault::hw_rei(); - format BasicOperate { - 1: hw_rei({{ xc->hwrei(); }}, IsSerializing, IsSerializeBefore); - } - } - - format BasicOperate { - // M5 special opcodes use the reserved 0x01 opcode space - 0x01: decode M5FUNC { - 0x00: arm({{ - PseudoInst::arm(xc->tcBase()); - }}, IsNonSpeculative); - 0x01: quiesce({{ - // Don't sleep if (unmasked) interrupts are pending - Interrupts* interrupts = - xc->tcBase()->getCpuPtr()->getInterruptController(0); - if (interrupts->checkInterrupts(xc->tcBase())) { - PseudoInst::quiesceSkip(xc->tcBase()); - } else { - PseudoInst::quiesce(xc->tcBase()); - } - }}, IsNonSpeculative, IsQuiesce); - 0x02: quiesceNs({{ - PseudoInst::quiesceNs(xc->tcBase(), R16); - }}, IsNonSpeculative, IsQuiesce); - 0x03: quiesceCycles({{ - PseudoInst::quiesceCycles(xc->tcBase(), R16); - }}, IsNonSpeculative, IsQuiesce, IsUnverifiable); - 0x04: quiesceTime({{ - R0 = PseudoInst::quiesceTime(xc->tcBase()); - }}, IsNonSpeculative, IsUnverifiable); - 0x07: rpns({{ - R0 = PseudoInst::rpns(xc->tcBase()); - }}, IsNonSpeculative, IsUnverifiable); - 0x09: wakeCPU({{ - PseudoInst::wakeCPU(xc->tcBase(), R16); - }}, IsNonSpeculative, IsUnverifiable); - 0x10: deprecated_ivlb({{ - warn_once("Obsolete M5 ivlb instruction encountered.\n"); - }}); - 0x11: deprecated_ivle({{ - warn_once("Obsolete M5 ivlb instruction encountered.\n"); - }}); - 0x20: deprecated_exit ({{ - warn_once("deprecated M5 exit instruction encountered.\n"); - PseudoInst::m5exit(xc->tcBase(), 0); - }}, No_OpClass, IsNonSpeculative); - 0x21: m5exit({{ - PseudoInst::m5exit(xc->tcBase(), R16); - }}, No_OpClass, IsNonSpeculative); - 0x31: loadsymbol({{ - PseudoInst::loadsymbol(xc->tcBase()); - }}, No_OpClass, IsNonSpeculative); - 0x30: initparam({{ - Ra = PseudoInst::initParam(xc->tcBase(), R16, R17); - }}); - 0x40: resetstats({{ - PseudoInst::resetstats(xc->tcBase(), R16, R17); - }}, IsNonSpeculative); - 0x41: dumpstats({{ - PseudoInst::dumpstats(xc->tcBase(), R16, R17); - }}, IsNonSpeculative); - 0x42: dumpresetstats({{ - PseudoInst::dumpresetstats(xc->tcBase(), R16, R17); - }}, IsNonSpeculative); - 0x43: m5checkpoint({{ - PseudoInst::m5checkpoint(xc->tcBase(), R16, R17); - }}, IsNonSpeculative); - 0x50: m5readfile({{ - R0 = PseudoInst::readfile(xc->tcBase(), R16, R17, R18); - }}, IsNonSpeculative); - 0x51: m5break({{ - PseudoInst::debugbreak(xc->tcBase()); - }}, IsNonSpeculative); - 0x52: m5switchcpu({{ - PseudoInst::switchcpu(xc->tcBase()); - }}, IsNonSpeculative); - 0x53: m5addsymbol({{ - PseudoInst::addsymbol(xc->tcBase(), R16, R17); - }}, IsNonSpeculative); - 0x54: m5panic({{ - panic("M5 panic instruction called at pc = %#x.", PC); - }}, IsNonSpeculative); -#define CPANN(lbl) CPA::cpa()->lbl(xc->tcBase()) - 0x55: decode RA { - 0x00: m5a_old({{ - panic("Deprecated M5 annotate instruction executed " - "at pc = %#x\n", PC); - }}, IsNonSpeculative); - 0x01: m5a_bsm({{ - CPANN(swSmBegin); - }}, IsNonSpeculative); - 0x02: m5a_esm({{ - CPANN(swSmEnd); - }}, IsNonSpeculative); - 0x03: m5a_begin({{ - CPANN(swExplictBegin); - }}, IsNonSpeculative); - 0x04: m5a_end({{ - CPANN(swEnd); - }}, IsNonSpeculative); - 0x06: m5a_q({{ - CPANN(swQ); - }}, IsNonSpeculative); - 0x07: m5a_dq({{ - CPANN(swDq); - }}, IsNonSpeculative); - 0x08: m5a_wf({{ - CPANN(swWf); - }}, IsNonSpeculative); - 0x09: m5a_we({{ - CPANN(swWe); - }}, IsNonSpeculative); - 0x0C: m5a_sq({{ - CPANN(swSq); - }}, IsNonSpeculative); - 0x0D: m5a_aq({{ - CPANN(swAq); - }}, IsNonSpeculative); - 0x0E: m5a_pq({{ - CPANN(swPq); - }}, IsNonSpeculative); - 0x0F: m5a_l({{ - CPANN(swLink); - }}, IsNonSpeculative); - 0x10: m5a_identify({{ - CPANN(swIdentify); - }}, IsNonSpeculative); - 0x11: m5a_getid({{ - R0 = CPANN(swGetId); - }}, IsNonSpeculative); - 0x13: m5a_scl({{ - CPANN(swSyscallLink); - }}, IsNonSpeculative); - 0x14: m5a_rq({{ - CPANN(swRq); - }}, IsNonSpeculative); - } // M5 Annotate Operations -#undef CPANN - 0x56: m5reserved2({{ - warn("M5 reserved opcode ignored"); - }}, IsNonSpeculative); - 0x57: m5reserved3({{ - warn("M5 reserved opcode ignored"); - }}, IsNonSpeculative); - 0x58: m5reserved4({{ - warn("M5 reserved opcode ignored"); - }}, IsNonSpeculative); - 0x59: m5reserved5({{ - warn("M5 reserved opcode ignored"); - }}, IsNonSpeculative); - } - } -} diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/isa/fp.isa --- a/src/arch/alpha/isa/fp.isa Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,305 +0,0 @@ -// -*- mode:c++ -*- - -// Copyright (c) 2003-2005 The Regents of The University of Michigan -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are -// met: redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer; -// redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution; -// neither the name of the copyright holders nor the names of its -// contributors may be used to endorse or promote products derived from -// this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// Authors: Steve Reinhardt - -//////////////////////////////////////////////////////////////////// -// -// Floating-point instructions -// -// Note that many FP-type instructions which do not support all the -// various rounding & trapping modes use the simpler format -// BasicOperateWithNopCheck. -// - -output exec {{ - /// Check "FP enabled" machine status bit. Called when executing any FP - /// instruction in full-system mode. - /// @retval Full-system mode: NoFault if FP is enabled, FenFault - /// if not. Non-full-system mode: always returns NoFault. - inline Fault checkFpEnableFault(CPU_EXEC_CONTEXT *xc) - { - Fault fault = NoFault; // dummy... this ipr access should not fault - if (FullSystem && !ICSR_FPE(xc->readMiscReg(IPR_ICSR))) { - fault = std::make_shared(); - } - return fault; - } -}}; - -output header {{ - /** - * Base class for general floating-point instructions. Includes - * support for various Alpha rounding and trapping modes. Only FP - * instructions that require this support are derived from this - * class; the rest derive directly from AlphaStaticInst. - */ - class AlphaFP : public AlphaStaticInst - { - public: - /// Alpha FP rounding modes. - enum RoundingMode { - Chopped = 0, ///< round toward zero - Minus_Infinity = 1, ///< round toward minus infinity - Normal = 2, ///< round to nearest (default) - Dynamic = 3, ///< use FPCR setting (in instruction) - Plus_Infinity = 3 ///< round to plus inifinity (in FPCR) - }; - - /// Alpha FP trapping modes. - /// For instructions that produce integer results, the - /// "Underflow Enable" modes really mean "Overflow Enable", and - /// the assembly modifier is V rather than U. - enum TrappingMode { - /// default: nothing enabled - Imprecise = 0, ///< no modifier - /// underflow/overflow traps enabled, inexact disabled - Underflow_Imprecise = 1, ///< /U or /V - Underflow_Precise = 5, ///< /SU or /SV - /// underflow/overflow and inexact traps enabled - Underflow_Inexact_Precise = 7 ///< /SUI or /SVI - }; - - protected: - /// Map Alpha rounding mode to C99 constants from . - static const int alphaToC99RoundingMode[]; - - /// Map enum RoundingMode values to disassembly suffixes. - static const char *roundingModeSuffix[]; - /// Map enum TrappingMode values to FP disassembly suffixes. - static const char *fpTrappingModeSuffix[]; - /// Map enum TrappingMode values to integer disassembly suffixes. - static const char *intTrappingModeSuffix[]; - - /// This instruction's rounding mode. - RoundingMode roundingMode; - /// This instruction's trapping mode. - TrappingMode trappingMode; - - /// Have we warned about this instruction's unsupported - /// rounding mode (if applicable)? - mutable bool warnedOnRounding; - - /// Have we warned about this instruction's unsupported - /// trapping mode (if applicable)? - mutable bool warnedOnTrapping; - - /// Constructor - AlphaFP(const char *mnem, ExtMachInst _machInst, OpClass __opClass) - : AlphaStaticInst(mnem, _machInst, __opClass), - roundingMode((enum RoundingMode)FP_ROUNDMODE), - trappingMode((enum TrappingMode)FP_TRAPMODE), - warnedOnRounding(false), - warnedOnTrapping(false) - { - } - - int getC99RoundingMode(uint64_t fpcr_val) const; - - // This differs from the AlphaStaticInst version only in - // printing suffixes for non-default rounding & trapping modes. - std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const; - }; - -}}; - - -output decoder {{ - int - AlphaFP::getC99RoundingMode(uint64_t fpcr_val) const - { - if (roundingMode == Dynamic) { - return alphaToC99RoundingMode[bits(fpcr_val, 59, 58)]; - } - else { - return alphaToC99RoundingMode[roundingMode]; - } - } - - std::string - AlphaFP::generateDisassembly(Addr pc, const SymbolTable *symtab) const - { - std::string mnem_str(mnemonic); - -#ifndef SS_COMPATIBLE_DISASSEMBLY - std::string suffix(""); - suffix += ((_destRegIdx[0] >= FP_Reg_Base) - ? fpTrappingModeSuffix[trappingMode] - : intTrappingModeSuffix[trappingMode]); - suffix += roundingModeSuffix[roundingMode]; - - if (suffix != "") { - mnem_str = csprintf("%s/%s", mnemonic, suffix); - } -#endif - - std::stringstream ss; - ccprintf(ss, "%-10s ", mnem_str.c_str()); - - // just print the first two source regs... if there's - // a third one, it's a read-modify-write dest (Rc), - // e.g. for CMOVxx - if (_numSrcRegs > 0) { - printReg(ss, _srcRegIdx[0]); - } - if (_numSrcRegs > 1) { - ss << ","; - printReg(ss, _srcRegIdx[1]); - } - - // just print the first dest... if there's a second one, - // it's generally implicit - if (_numDestRegs > 0) { - if (_numSrcRegs > 0) - ss << ","; - printReg(ss, _destRegIdx[0]); - } - - return ss.str(); - } - - const int AlphaFP::alphaToC99RoundingMode[] = { - M5_FE_TOWARDZERO, // Chopped - M5_FE_DOWNWARD, // Minus_Infinity - M5_FE_TONEAREST, // Normal - M5_FE_UPWARD // Dynamic in inst, Plus_Infinity in FPCR - }; - - const char *AlphaFP::roundingModeSuffix[] = { "c", "m", "", "d" }; - // mark invalid trapping modes, but don't fail on them, because - // you could decode anything on a misspeculated path - const char *AlphaFP::fpTrappingModeSuffix[] = - { "", "u", "INVTM2", "INVTM3", "INVTM4", "su", "INVTM6", "sui" }; - const char *AlphaFP::intTrappingModeSuffix[] = - { "", "v", "INVTM2", "INVTM3", "INVTM4", "sv", "INVTM6", "svi" }; -}}; - -// FP instruction class execute method template. Handles non-standard -// rounding modes. -def template FloatingPointExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, - Trace::InstRecord *traceData) const - { - if (trappingMode != Imprecise && !warnedOnTrapping) { - warn("%s: non-standard trapping mode not supported", - generateDisassembly(0, NULL)); - warnedOnTrapping = true; - } - - Fault fault = NoFault; - - %(fp_enable_check)s; - %(op_decl)s; - %(op_rd)s; -#if USE_FENV - if (roundingMode == Normal) { - %(code)s; - } else { - m5_fesetround(getC99RoundingMode( - xc->readMiscReg(MISCREG_FPCR))); - %(code)s; - m5_fesetround(M5_FE_TONEAREST); - } -#else - if (roundingMode != Normal && !warnedOnRounding) { - warn("%s: non-standard rounding mode not supported", - generateDisassembly(0, NULL)); - warnedOnRounding = true; - } - %(code)s; -#endif - - if (fault == NoFault) { - %(op_wb)s; - } - - return fault; - } -}}; - -// FP instruction class execute method template where no dynamic -// rounding mode control is needed. Like BasicExecute, but includes -// check & warning for non-standard trapping mode. -def template FPFixedRoundingExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, - Trace::InstRecord *traceData) const - { - if (trappingMode != Imprecise && !warnedOnTrapping) { - warn("%s: non-standard trapping mode not supported", - generateDisassembly(0, NULL)); - warnedOnTrapping = true; - } - - Fault fault = NoFault; - - %(fp_enable_check)s; - %(op_decl)s; - %(op_rd)s; - %(code)s; - - if (fault == NoFault) { - %(op_wb)s; - } - - return fault; - } -}}; - -def template FloatingPointDecode {{ - { - AlphaStaticInst *i = new %(class_name)s(machInst); - if (FC == 31) { - i = makeNop(i); - } - return i; - } -}}; - -// General format for floating-point operate instructions: -// - Checks trapping and rounding mode flags. Trapping modes -// currently unimplemented (will fail). -// - Generates NOP if FC == 31. -def format FloatingPointOperate(code, *opt_args) {{ - iop = InstObjParams(name, Name, 'AlphaFP', code, opt_args) - decode_block = FloatingPointDecode.subst(iop) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - exec_output = FloatingPointExecute.subst(iop) -}}; - -// Special format for cvttq where rounding mode is pre-decoded -def format FPFixedRounding(code, class_suffix, *opt_args) {{ - Name += class_suffix - iop = InstObjParams(name, Name, 'AlphaFP', code, opt_args) - decode_block = FloatingPointDecode.subst(iop) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - exec_output = FPFixedRoundingExecute.subst(iop) -}}; - diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/isa/int.isa --- a/src/arch/alpha/isa/int.isa Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,133 +0,0 @@ -// -*- mode:c++ -*- - -// Copyright (c) 2003-2005 The Regents of The University of Michigan -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are -// met: redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer; -// redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution; -// neither the name of the copyright holders nor the names of its -// contributors may be used to endorse or promote products derived from -// this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// Authors: Steve Reinhardt - -//////////////////////////////////////////////////////////////////// -// -// Integer operate instructions -// - -output header {{ - /** - * Base class for integer immediate instructions. - */ - class IntegerImm : public AlphaStaticInst - { - protected: - /// Immediate operand value (unsigned 8-bit int). - uint8_t imm; - - /// Constructor - IntegerImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass) - : AlphaStaticInst(mnem, _machInst, __opClass), imm(INTIMM) - { - } - - std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const; - }; -}}; - -output decoder {{ - std::string - IntegerImm::generateDisassembly(Addr pc, const SymbolTable *symtab) const - { - std::stringstream ss; - - ccprintf(ss, "%-10s ", mnemonic); - - // just print the first source reg... if there's - // a second one, it's a read-modify-write dest (Rc), - // e.g. for CMOVxx - if (_numSrcRegs > 0) { - printReg(ss, _srcRegIdx[0]); - ss << ","; - } - - ss << (int)imm; - - if (_numDestRegs > 0) { - ss << ","; - printReg(ss, _destRegIdx[0]); - } - - return ss.str(); - } -}}; - - -def template RegOrImmDecode {{ - { - AlphaStaticInst *i = - (IMM) ? (AlphaStaticInst *)new %(class_name)sImm(machInst) - : (AlphaStaticInst *)new %(class_name)s(machInst); - if (RC == 31) { - i = makeNop(i); - } - return i; - } -}}; - -// Primary format for integer operate instructions: -// - Generates both reg-reg and reg-imm versions if Rb_or_imm is used. -// - Generates NOP if RC == 31. -def format IntegerOperate(code, *opt_flags) {{ - # If the code block contains 'Rb_or_imm', we define two instructions, - # one using 'Rb' and one using 'imm', and have the decoder select - # the right one. - uses_imm = (code.find('Rb_or_imm') != -1) - if uses_imm: - orig_code = code - # base code is reg version: - # rewrite by substituting 'Rb' for 'Rb_or_imm' - code = re.sub(r'Rb_or_imm', 'Rb', orig_code) - # generate immediate version by substituting 'imm' - # note that imm takes no extenstion, so we extend - # the regexp to replace any extension as well - imm_code = re.sub(r'Rb_or_imm(_\w+)?', 'imm', orig_code) - - # generate declaration for register version - iop = InstObjParams(name, Name, 'AlphaStaticInst', code, opt_flags) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - exec_output = BasicExecute.subst(iop) - - if uses_imm: - # append declaration for imm version - imm_iop = InstObjParams(name, Name + 'Imm', 'IntegerImm', imm_code, - opt_flags) - header_output += BasicDeclare.subst(imm_iop) - decoder_output += BasicConstructor.subst(imm_iop) - exec_output += BasicExecute.subst(imm_iop) - # decode checks IMM bit to pick correct version - decode_block = RegOrImmDecode.subst(iop) - else: - # no imm version: just check for nop - decode_block = OperateNopCheckDecode.subst(iop) -}}; diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/isa/main.isa --- a/src/arch/alpha/isa/main.isa Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,477 +0,0 @@ -// -*- mode:c++ -*- - -// Copyright (c) 2003-2005 The Regents of The University of Michigan -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are -// met: redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer; -// redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution; -// neither the name of the copyright holders nor the names of its -// contributors may be used to endorse or promote products derived from -// this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// Authors: Steve Reinhardt - -//////////////////////////////////////////////////////////////////// -// -// Alpha ISA description file. -// -//////////////////////////////////////////////////////////////////// - - -//////////////////////////////////////////////////////////////////// -// -// Output include file directives. -// - -output header {{ -#include -#include -#include - -#include "arch/alpha/faults.hh" -#include "arch/alpha/types.hh" -#include "config/ss_compatible_fp.hh" -#include "cpu/static_inst.hh" -#include "mem/packet.hh" -#include "mem/request.hh" // some constructors use MemReq flags -}}; - -output decoder {{ -#include - -#include "arch/alpha/decoder.hh" -#include "arch/alpha/registers.hh" -#include "arch/alpha/regredir.hh" -#include "base/loader/symtab.hh" -#include "base/cprintf.hh" -#include "base/fenv.hh" -#include "config/ss_compatible_fp.hh" -#include "cpu/thread_context.hh" // for Jump::branchTarget() -#include "mem/packet.hh" -#include "sim/full_system.hh" - -using namespace AlphaISA; -}}; - -output exec {{ -#include - -#include "arch/alpha/decoder.hh" -#include "arch/alpha/registers.hh" -#include "arch/alpha/regredir.hh" -#include "arch/generic/memhelpers.hh" -#include "base/cp_annotate.hh" -#include "base/fenv.hh" -#include "config/ss_compatible_fp.hh" -#include "cpu/base.hh" -#include "cpu/exetrace.hh" -#include "mem/packet.hh" -#include "mem/packet_access.hh" -#include "sim/full_system.hh" -#include "sim/pseudo_inst.hh" -#include "sim/sim_exit.hh" - -using namespace AlphaISA; -}}; - -//////////////////////////////////////////////////////////////////// -// -// Namespace statement. Everything below this line will be in the -// AlphaISAInst namespace. -// - - -namespace AlphaISA; - -//////////////////////////////////////////////////////////////////// -// -// Bitfield definitions. -// - -// Universal (format-independent) fields -def bitfield PALMODE <32:32>; -def bitfield OPCODE <31:26>; -def bitfield RA <25:21>; -def bitfield RB <20:16>; - -// Memory format -def signed bitfield MEMDISP <15: 0>; // displacement -def bitfield MEMFUNC <15: 0>; // function code (same field, unsigned) - -// Memory-format jumps -def bitfield JMPFUNC <15:14>; // function code (disp<15:14>) -def bitfield JMPHINT <13: 0>; // tgt Icache idx hint (disp<13:0>) - -// Branch format -def signed bitfield BRDISP <20: 0>; // displacement - -// Integer operate format(s>; -def bitfield INTIMM <20:13>; // integer immediate (literal) -def bitfield IMM <12:12>; // immediate flag -def bitfield INTFUNC <11: 5>; // function code -def bitfield RC < 4: 0>; // dest reg - -// Floating-point operate format -def bitfield FA <25:21>; -def bitfield FB <20:16>; -def bitfield FP_FULLFUNC <15: 5>; // complete function code - def bitfield FP_TRAPMODE <15:13>; // trapping mode - def bitfield FP_ROUNDMODE <12:11>; // rounding mode - def bitfield FP_TYPEFUNC <10: 5>; // type+func: handiest for decoding - def bitfield FP_SRCTYPE <10: 9>; // source reg type - def bitfield FP_SHORTFUNC < 8: 5>; // short function code - def bitfield FP_SHORTFUNC_TOP2 <8:7>; // top 2 bits of short func code -def bitfield FC < 4: 0>; // dest reg - -// PALcode format -def bitfield PALFUNC <25: 0>; // function code - -// EV5 PAL instructions: -// HW_LD/HW_ST -def bitfield HW_LDST_PHYS <15>; // address is physical -def bitfield HW_LDST_ALT <14>; // use ALT_MODE IPR -def bitfield HW_LDST_WRTCK <13>; // HW_LD only: fault if no write acc -def bitfield HW_LDST_QUAD <12>; // size: 0=32b, 1=64b -def bitfield HW_LDST_VPTE <11>; // HW_LD only: is PTE fetch -def bitfield HW_LDST_LOCK <10>; // HW_LD only: is load locked -def bitfield HW_LDST_COND <10>; // HW_ST only: is store conditional -def signed bitfield HW_LDST_DISP <9:0>; // signed displacement - -// HW_REI -def bitfield HW_REI_TYP <15:14>; // type: stalling vs. non-stallingk -def bitfield HW_REI_MBZ <13: 0>; // must be zero - -// HW_MTPR/MW_MFPR -def bitfield HW_IPR_IDX <15:0>; // IPR index - -// M5 instructions -def bitfield M5FUNC <7:0>; - -def operand_types {{ - 'sb' : 'int8_t', - 'ub' : 'uint8_t', - 'sw' : 'int16_t', - 'uw' : 'uint16_t', - 'sl' : 'int32_t', - 'ul' : 'uint32_t', - 'sq' : 'int64_t', - 'uq' : 'uint64_t', - 'sf' : 'float', - 'df' : 'double' -}}; - -def operands {{ - # Int regs default to unsigned, but code should not count on this. - # For clarity, descriptions that depend on unsigned behavior should - # explicitly specify '_uq'. - 'Ra': ('IntReg', 'uq', 'PALMODE ? reg_redir[RA] : RA', - 'IsInteger', 1), - 'Rb': ('IntReg', 'uq', 'PALMODE ? reg_redir[RB] : RB', - 'IsInteger', 2), - 'Rc': ('IntReg', 'uq', 'PALMODE ? reg_redir[RC] : RC', - 'IsInteger', 3), - 'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1), - 'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2), - 'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3), - 'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4), - 'PC': ('PCState', 'uq', 'pc', ( None, None, 'IsControl' ), 4), - 'NPC': ('PCState', 'uq', 'npc', ( None, None, 'IsControl' ), 4), - 'Runiq': ('ControlReg', 'uq', 'MISCREG_UNIQ', None, 1), - 'FPCR': ('ControlReg', 'uq', 'MISCREG_FPCR', None, 1), - 'IntrFlag': ('ControlReg', 'uq', 'MISCREG_INTR', None, 1), - # The next two are hacks for non-full-system call-pal emulation - 'R0': ('IntReg', 'uq', '0', None, 1), - 'R16': ('IntReg', 'uq', '16', None, 1), - 'R17': ('IntReg', 'uq', '17', None, 1), - 'R18': ('IntReg', 'uq', '18', None, 1) -}}; - -//////////////////////////////////////////////////////////////////// -// -// Basic instruction classes/templates/formats etc. -// - -output header {{ -// uncomment the following to get SimpleScalar-compatible disassembly -// (useful for diffing output traces). -// #define SS_COMPATIBLE_DISASSEMBLY - - /** - * Base class for all Alpha static instructions. - */ - class AlphaStaticInst : public StaticInst - { - protected: - - /// Make AlphaISA register dependence tags directly visible in - /// this class and derived classes. Maybe these should really - /// live here and not in the AlphaISA namespace. - enum DependenceTags { - FP_Reg_Base = AlphaISA::FP_Reg_Base - }; - - /// Constructor. - AlphaStaticInst(const char *mnem, ExtMachInst _machInst, - OpClass __opClass) - : StaticInst(mnem, _machInst, __opClass) - { - } - - /// Print a register name for disassembly given the unique - /// dependence tag number (FP or int). - void printReg(std::ostream &os, int reg) const; - - std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const; - - void - advancePC(AlphaISA::PCState &pcState) const - { - pcState.advance(); - } - }; -}}; - -output decoder {{ - void - AlphaStaticInst::printReg(std::ostream &os, int reg) const - { - if (reg < FP_Reg_Base) { - ccprintf(os, "r%d", reg); - } - else { - ccprintf(os, "f%d", reg - FP_Reg_Base); - } - } - - std::string - AlphaStaticInst::generateDisassembly(Addr pc, - const SymbolTable *symtab) const - { - std::stringstream ss; - - ccprintf(ss, "%-10s ", mnemonic); - - // just print the first two source regs... if there's - // a third one, it's a read-modify-write dest (Rc), - // e.g. for CMOVxx - if (_numSrcRegs > 0) { - printReg(ss, _srcRegIdx[0]); - } - if (_numSrcRegs > 1) { - ss << ","; - printReg(ss, _srcRegIdx[1]); - } - - // just print the first dest... if there's a second one, - // it's generally implicit - if (_numDestRegs > 0) { - if (_numSrcRegs > 0) - ss << ","; - printReg(ss, _destRegIdx[0]); - } - - return ss.str(); - } -}}; - -// Declarations for execute() methods. -def template BasicExecDeclare {{ - Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const; -}}; - -// Basic instruction class declaration template. -def template BasicDeclare {{ - /** - * Static instruction class for "%(mnemonic)s". - */ - class %(class_name)s : public %(base_class)s - { - public: - /// Constructor. - %(class_name)s(ExtMachInst machInst); - - %(BasicExecDeclare)s - }; -}}; - -// Basic instruction class constructor template. -def template BasicConstructor {{ - %(class_name)s::%(class_name)s(ExtMachInst machInst) - : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) - { - %(constructor)s; - } -}}; - -// Basic instruction class execute method template. -def template BasicExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, - Trace::InstRecord *traceData) const - { - Fault fault = NoFault; - - %(fp_enable_check)s; - %(op_decl)s; - %(op_rd)s; - %(code)s; - - if (fault == NoFault) { - %(op_wb)s; - } - - return fault; - } -}}; - -// Basic decode template. -def template BasicDecode {{ - return new %(class_name)s(machInst); -}}; - -// Basic decode template, passing mnemonic in as string arg to constructor. -def template BasicDecodeWithMnemonic {{ - return new %(class_name)s("%(mnemonic)s", machInst); -}}; - -// The most basic instruction format... used only for a few misc. insts -def format BasicOperate(code, *flags) {{ - iop = InstObjParams(name, Name, 'AlphaStaticInst', code, flags) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - decode_block = BasicDecode.subst(iop) - exec_output = BasicExecute.subst(iop) -}}; - - - -//////////////////////////////////////////////////////////////////// -// -// Nop -// - -output header {{ - /** - * Static instruction class for no-ops. This is a leaf class. - */ - class Nop : public AlphaStaticInst - { - /// Disassembly of original instruction. - const std::string originalDisassembly; - - public: - /// Constructor - Nop(const std::string _originalDisassembly, ExtMachInst _machInst) - : AlphaStaticInst("nop", _machInst, No_OpClass), - originalDisassembly(_originalDisassembly) - { - flags[IsNop] = true; - } - - ~Nop() { } - - std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const; - - %(BasicExecDeclare)s - }; - - /// Helper function for decoding nops. Substitute Nop object - /// for original inst passed in as arg (and delete latter). - static inline - AlphaStaticInst * - makeNop(AlphaStaticInst *inst) - { - AlphaStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst); - delete inst; - return nop; - } -}}; - -output decoder {{ - std::string Nop::generateDisassembly(Addr pc, - const SymbolTable *symtab) const - { -#ifdef SS_COMPATIBLE_DISASSEMBLY - return originalDisassembly; -#else - return csprintf("%-10s (%s)", "nop", originalDisassembly); -#endif - } -}}; - -output exec {{ - Fault - Nop::execute(CPU_EXEC_CONTEXT *, Trace::InstRecord *) const - { - return NoFault; - } -}}; - -// integer & FP operate instructions use Rc as dest, so check for -// Rc == 31 to detect nops -def template OperateNopCheckDecode {{ - { - AlphaStaticInst *i = new %(class_name)s(machInst); - if (RC == 31) { - i = makeNop(i); - } - return i; - } -}}; - -// Like BasicOperate format, but generates NOP if RC/FC == 31 -def format BasicOperateWithNopCheck(code, *opt_args) {{ - iop = InstObjParams(name, Name, 'AlphaStaticInst', code, opt_args) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - decode_block = OperateNopCheckDecode.subst(iop) - exec_output = BasicExecute.subst(iop) -}}; - -// Integer instruction templates, formats, etc. -##include "int.isa" - -// Floating-point instruction templates, formats, etc. -##include "fp.isa" - -// Memory instruction templates, formats, etc. -##include "mem.isa" - -// Branch/jump instruction templates, formats, etc. -##include "branch.isa" - -// PAL instruction templates, formats, etc. -##include "pal.isa" - -// Opcdec fault instruction templates, formats, etc. -##include "opcdec.isa" - -// Unimplemented instruction templates, formats, etc. -##include "unimp.isa" - -// Unknown instruction templates, formats, etc. -##include "unknown.isa" - -// Execution utility functions -##include "util.isa" - -// The actual decoder -##include "decoder.isa" diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/isa/mem.isa --- a/src/arch/alpha/isa/mem.isa Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,560 +0,0 @@ -// -*- mode:c++ -*- - -// Copyright (c) 2003-2005 The Regents of The University of Michigan -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are -// met: redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer; -// redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution; -// neither the name of the copyright holders nor the names of its -// contributors may be used to endorse or promote products derived from -// this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// Authors: Steve Reinhardt -// Kevin Lim - -//////////////////////////////////////////////////////////////////// -// -// Memory-format instructions: LoadAddress, Load, Store -// - -output header {{ - /** - * Base class for general Alpha memory-format instructions. - */ - class Memory : public AlphaStaticInst - { - protected: - - /// Memory request flags. See mem_req_base.hh. - Request::Flags memAccessFlags; - - /// Constructor - Memory(const char *mnem, ExtMachInst _machInst, OpClass __opClass) - : AlphaStaticInst(mnem, _machInst, __opClass) - { - } - - std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const; - }; - - /** - * Base class for memory-format instructions using a 32-bit - * displacement (i.e. most of them). - */ - class MemoryDisp32 : public Memory - { - protected: - /// Displacement for EA calculation (signed). - int32_t disp; - - /// Constructor. - MemoryDisp32(const char *mnem, ExtMachInst _machInst, OpClass __opClass) - : Memory(mnem, _machInst, __opClass), - disp(MEMDISP) - { - } - }; - - - /** - * Base class for a few miscellaneous memory-format insts - * that don't interpret the disp field: wh64, fetch, fetch_m, ecb. - * None of these instructions has a destination register either. - */ - class MemoryNoDisp : public Memory - { - protected: - /// Constructor - MemoryNoDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) - : Memory(mnem, _machInst, __opClass) - { - } - - std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const; - }; -}}; - - -output decoder {{ - std::string - Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const - { - return csprintf("%-10s %c%d,%d(r%d)", mnemonic, - flags[IsFloating] ? 'f' : 'r', RA, MEMDISP, RB); - } - - std::string - MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const - { - return csprintf("%-10s (r%d)", mnemonic, RB); - } -}}; - -def format LoadAddress(code) {{ - iop = InstObjParams(name, Name, 'MemoryDisp32', code) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - decode_block = BasicDecode.subst(iop) - exec_output = BasicExecute.subst(iop) -}}; - - -def template LoadStoreDeclare {{ - /** - * Static instruction class for "%(mnemonic)s". - */ - class %(class_name)s : public %(base_class)s - { - public: - - /// Constructor. - %(class_name)s(ExtMachInst machInst); - - %(BasicExecDeclare)s - - %(EACompDeclare)s - - %(InitiateAccDeclare)s - - %(CompleteAccDeclare)s - }; -}}; - - -def template EACompDeclare {{ - Fault eaComp(%(CPU_exec_context)s *, Trace::InstRecord *) const; -}}; - -def template InitiateAccDeclare {{ - Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; -}}; - - -def template CompleteAccDeclare {{ - Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, - Trace::InstRecord *) const; -}}; - -def template LoadStoreConstructor {{ - %(class_name)s::%(class_name)s(ExtMachInst machInst) - : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) - { - %(constructor)s; - } -}}; - -def template EACompExecute {{ - Fault %(class_name)s::eaComp(CPU_EXEC_CONTEXT *xc, - Trace::InstRecord *traceData) const - { - Addr EA; - Fault fault = NoFault; - - %(fp_enable_check)s; - %(op_decl)s; - %(op_rd)s; - %(ea_code)s; - - if (fault == NoFault) { - %(op_wb)s; - xc->setEA(EA); - } - - return fault; - } -}}; - - -def template LoadExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, - Trace::InstRecord *traceData) const - { - Addr EA; - Fault fault = NoFault; - - %(fp_enable_check)s; - %(op_decl)s; - %(op_rd)s; - %(ea_code)s; - - if (fault == NoFault) { - fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags); - %(memacc_code)s; - } - - if (fault == NoFault) { - %(op_wb)s; - } - - return fault; - } -}}; - - -def template LoadInitiateAcc {{ - Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc, - Trace::InstRecord *traceData) const - { - Addr EA; - Fault fault = NoFault; - - %(fp_enable_check)s; - %(op_src_decl)s; - %(op_rd)s; - %(ea_code)s; - - if (fault == NoFault) { - fault = initiateMemRead(xc, traceData, EA, Mem, memAccessFlags); - } - - return fault; - } -}}; - - -def template LoadCompleteAcc {{ - Fault %(class_name)s::completeAcc(PacketPtr pkt, - CPU_EXEC_CONTEXT *xc, - Trace::InstRecord *traceData) const - { - Fault fault = NoFault; - - %(fp_enable_check)s; - %(op_decl)s; - - getMem(pkt, Mem, traceData); - - if (fault == NoFault) { - %(memacc_code)s; - } - - if (fault == NoFault) { - %(op_wb)s; - } - - return fault; - } -}}; - - -def template StoreExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, - Trace::InstRecord *traceData) const - { - Addr EA; - Fault fault = NoFault; - - %(fp_enable_check)s; - %(op_decl)s; - %(op_rd)s; - %(ea_code)s; - - if (fault == NoFault) { - %(memacc_code)s; - } - - if (fault == NoFault) { - fault = writeMemAtomic(xc, traceData, Mem, EA, - memAccessFlags, NULL); - } - - if (fault == NoFault) { - %(postacc_code)s; - } - - if (fault == NoFault) { - %(op_wb)s; - } - - return fault; - } -}}; - -def template StoreCondExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, - Trace::InstRecord *traceData) const - { - Addr EA; - Fault fault = NoFault; - uint64_t write_result = 0; - - %(fp_enable_check)s; - %(op_decl)s; - %(op_rd)s; - %(ea_code)s; - - if (fault == NoFault) { - %(memacc_code)s; - } - - if (fault == NoFault) { - fault = writeMemAtomic(xc, traceData, Mem, EA, - memAccessFlags, &write_result); - } - - if (fault == NoFault) { - %(postacc_code)s; - } - - if (fault == NoFault) { - %(op_wb)s; - } - - return fault; - } -}}; - -def template StoreInitiateAcc {{ - Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc, - Trace::InstRecord *traceData) const - { - Addr EA; - Fault fault = NoFault; - - %(fp_enable_check)s; - %(op_decl)s; - %(op_rd)s; - %(ea_code)s; - - if (fault == NoFault) { - %(memacc_code)s; - } - - if (fault == NoFault) { - fault = writeMemTiming(xc, traceData, Mem, EA, - memAccessFlags, NULL); - } - - return fault; - } -}}; - - -def template StoreCompleteAcc {{ - Fault %(class_name)s::completeAcc(PacketPtr pkt, - CPU_EXEC_CONTEXT *xc, - Trace::InstRecord *traceData) const - { - return NoFault; - } -}}; - - -def template StoreCondCompleteAcc {{ - Fault %(class_name)s::completeAcc(PacketPtr pkt, - CPU_EXEC_CONTEXT *xc, - Trace::InstRecord *traceData) const - { - Fault fault = NoFault; - - %(fp_enable_check)s; - %(op_dest_decl)s; - - uint64_t write_result = pkt->req->getExtraData(); - - if (fault == NoFault) { - %(postacc_code)s; - } - - if (fault == NoFault) { - %(op_wb)s; - } - - return fault; - } -}}; - - -def template MiscExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, - Trace::InstRecord *traceData) const - { - Addr EA M5_VAR_USED; - Fault fault = NoFault; - - %(fp_enable_check)s; - %(op_decl)s; - %(op_rd)s; - %(ea_code)s; - - warn_once("Prefetch instructions in Alpha do not do anything\n"); - if (fault == NoFault) { - %(memacc_code)s; - } - - return NoFault; - } -}}; - -// Prefetches in Alpha don't actually do anything -// They just build an effective address and complete -def template MiscInitiateAcc {{ - Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc, - Trace::InstRecord *traceData) const - { - warn("initiateAcc undefined: Misc instruction does not support split " - "access method!"); - return NoFault; - } -}}; - - -def template MiscCompleteAcc {{ - Fault %(class_name)s::completeAcc(PacketPtr pkt, - CPU_EXEC_CONTEXT *xc, - Trace::InstRecord *traceData) const - { - warn("completeAcc undefined: Misc instruction does not support split " - "access method!"); - - return NoFault; - } -}}; - - -// load instructions use Ra as dest, so check for -// Ra == 31 to detect nops -def template LoadNopCheckDecode {{ - { - AlphaStaticInst *i = new %(class_name)s(machInst); - if (RA == 31) { - i = makeNop(i); - } - return i; - } -}}; - - -// for some load instructions, Ra == 31 indicates a prefetch (not a nop) -def template LoadPrefetchCheckDecode {{ - { - if (RA != 31) { - return new %(class_name)s(machInst); - } - else { - return new %(class_name)sPrefetch(machInst); - } - } -}}; - - -let {{ -def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, - postacc_code = '', base_class = 'MemoryDisp32', - decode_template = BasicDecode, exec_template_base = ''): - # Make sure flags are in lists (convert to lists if not). - mem_flags = makeList(mem_flags) - inst_flags = makeList(inst_flags) - - iop = InstObjParams(name, Name, base_class, - { 'ea_code':ea_code, 'memacc_code':memacc_code, 'postacc_code':postacc_code }, - inst_flags) - - if mem_flags: - mem_flags = [ 'Request::%s' % flag for flag in mem_flags ] - s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';' - iop.constructor += s - - # select templates - - # The InitiateAcc template is the same for StoreCond templates as the - # corresponding Store template.. - StoreCondInitiateAcc = StoreInitiateAcc - - fullExecTemplate = eval(exec_template_base + 'Execute') - initiateAccTemplate = eval(exec_template_base + 'InitiateAcc') - completeAccTemplate = eval(exec_template_base + 'CompleteAcc') - - # (header_output, decoder_output, decode_block, exec_output) - return (LoadStoreDeclare.subst(iop), - LoadStoreConstructor.subst(iop), - decode_template.subst(iop), - fullExecTemplate.subst(iop) - + EACompExecute.subst(iop) - + initiateAccTemplate.subst(iop) - + completeAccTemplate.subst(iop)) -}}; - -def format LoadOrNop(memacc_code, ea_code = {{ EA = Rb + disp; }}, - mem_flags = [], inst_flags = []) {{ - (header_output, decoder_output, decode_block, exec_output) = \ - LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, - decode_template = LoadNopCheckDecode, - exec_template_base = 'Load') -}}; - - -// Note that the flags passed in apply only to the prefetch version -def format LoadOrPrefetch(memacc_code, ea_code = {{ EA = Rb + disp; }}, - mem_flags = [], pf_flags = [], inst_flags = []) {{ - # declare the load instruction object and generate the decode block - (header_output, decoder_output, decode_block, exec_output) = \ - LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, - decode_template = LoadPrefetchCheckDecode, - exec_template_base = 'Load') - - # Declare the prefetch instruction object. - - # Make sure flag args are lists so we can mess with them. - mem_flags = makeList(mem_flags) - pf_flags = makeList(pf_flags) - inst_flags = makeList(inst_flags) - - pf_mem_flags = mem_flags + pf_flags + ['PREFETCH'] - pf_inst_flags = inst_flags - - (pf_header_output, pf_decoder_output, _, pf_exec_output) = \ - LoadStoreBase(name, Name + 'Prefetch', ea_code, ';', - pf_mem_flags, pf_inst_flags, exec_template_base = 'Misc') - - header_output += pf_header_output - decoder_output += pf_decoder_output - exec_output += pf_exec_output -}}; - - -def format Store(memacc_code, ea_code = {{ EA = Rb + disp; }}, - mem_flags = [], inst_flags = []) {{ - (header_output, decoder_output, decode_block, exec_output) = \ - LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, - exec_template_base = 'Store') -}}; - - -def format StoreCond(memacc_code, postacc_code, - ea_code = {{ EA = Rb + disp; }}, - mem_flags = [], inst_flags = []) {{ - (header_output, decoder_output, decode_block, exec_output) = \ - LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, - postacc_code, exec_template_base = 'StoreCond') -}}; - - -// Use 'MemoryNoDisp' as base: for wh64, fetch, ecb -def format MiscPrefetch(ea_code, memacc_code, - mem_flags = [], inst_flags = []) {{ - (header_output, decoder_output, decode_block, exec_output) = \ - LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, - base_class = 'MemoryNoDisp', exec_template_base = 'Misc') -}}; - - diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/isa/opcdec.isa --- a/src/arch/alpha/isa/opcdec.isa Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,79 +0,0 @@ -// -*- mode:c++ -*- - -// Copyright (c) 2003-2005 The Regents of The University of Michigan -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are -// met: redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer; -// redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution; -// neither the name of the copyright holders nor the names of its -// contributors may be used to endorse or promote products derived from -// this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// Authors: Kevin Lim - -//////////////////////////////////////////////////////////////////// -// -// OPCDEC fault instructions -// - -output header {{ - /** - * Static instruction class for instructions that cause an OPCDEC fault - * when executed. This is currently only for PAL mode instructions - * executed in non-PAL mode. - */ - class OpcdecFault : public AlphaStaticInst - { - public: - /// Constructor - OpcdecFault(ExtMachInst _machInst) - : AlphaStaticInst("opcdec fault", _machInst, No_OpClass) - { - } - - %(BasicExecDeclare)s - - std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const; - }; -}}; - -output decoder {{ - std::string - OpcdecFault::generateDisassembly(Addr pc, const SymbolTable *symtab) const - { - return csprintf("%-10s (inst 0x%x, opcode 0x%x)", - " OPCDEC fault", machInst, OPCODE); - } -}}; - -output exec {{ - Fault - OpcdecFault::execute(CPU_EXEC_CONTEXT *xc, - Trace::InstRecord *traceData) const - { - return std::make_shared(); - } -}}; - -def format OpcdecFault() {{ - decode_block = 'return new OpcdecFault(machInst);\n' -}}; - diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/isa/pal.isa --- a/src/arch/alpha/isa/pal.isa Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,274 +0,0 @@ -// -*- mode:c++ -*- - -// Copyright (c) 2003-2005 The Regents of The University of Michigan -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are -// met: redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer; -// redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution; -// neither the name of the copyright holders nor the names of its -// contributors may be used to endorse or promote products derived from -// this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// Authors: Steve Reinhardt - -//////////////////////////////////////////////////////////////////// -// -// PAL calls & PAL-specific instructions -// - -output header {{ - /** - * Base class for emulated call_pal calls (used only in - * non-full-system mode). - */ - class EmulatedCallPal : public AlphaStaticInst - { - protected: - - /// Constructor. - EmulatedCallPal(const char *mnem, ExtMachInst _machInst, - OpClass __opClass) - : AlphaStaticInst(mnem, _machInst, __opClass) - { - } - - std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const; - }; -}}; - -output decoder {{ - std::string - EmulatedCallPal::generateDisassembly(Addr pc, - const SymbolTable *symtab) const - { -#ifdef SS_COMPATIBLE_DISASSEMBLY - return csprintf("%s %s", "call_pal", mnemonic); -#else - return csprintf("%-10s %s", "call_pal", mnemonic); -#endif - } -}}; - -def format EmulatedCallPal(code, *flags) {{ - iop = InstObjParams(name, Name, 'EmulatedCallPal', code, flags) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - decode_block = BasicDecode.subst(iop) - exec_output = BasicExecute.subst(iop) -}}; - -output header {{ - /** - * Base class for full-system-mode call_pal instructions. - * Probably could turn this into a leaf class and get rid of the - * parser template. - */ - class CallPalBase : public AlphaStaticInst - { - protected: - int palFunc; ///< Function code part of instruction - int palOffset; ///< Target PC, offset from IPR_PAL_BASE - bool palValid; ///< is the function code valid? - bool palPriv; ///< is this call privileged? - - /// Constructor. - CallPalBase(const char *mnem, ExtMachInst _machInst, - OpClass __opClass); - - std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const; - }; -}}; - -output decoder {{ - inline - CallPalBase::CallPalBase(const char *mnem, ExtMachInst _machInst, - OpClass __opClass) - : AlphaStaticInst(mnem, _machInst, __opClass), - palFunc(PALFUNC) - { - // From the 21164 HRM (paraphrased): - // Bit 7 of the function code (mask 0x80) indicates - // whether the call is privileged (bit 7 == 0) or - // unprivileged (bit 7 == 1). The privileged call table - // starts at 0x2000, the unprivielged call table starts at - // 0x3000. Bits 5-0 (mask 0x3f) are used to calculate the - // offset. - const int palPrivMask = 0x80; - const int palOffsetMask = 0x3f; - - // Pal call is invalid unless all other bits are 0 - palValid = ((machInst & ~(palPrivMask | palOffsetMask)) == 0); - palPriv = ((machInst & palPrivMask) == 0); - int shortPalFunc = (machInst & palOffsetMask); - // Add 1 to base to set pal-mode bit - palOffset = (palPriv ? 0x2001 : 0x3001) + (shortPalFunc << 6); - } - - std::string - CallPalBase::generateDisassembly(Addr pc, const SymbolTable *symtab) const - { - return csprintf("%-10s %#x", "call_pal", palFunc); - } -}}; - -def format CallPal(code, *flags) {{ - iop = InstObjParams(name, Name, 'CallPalBase', code, flags) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - decode_block = BasicDecode.subst(iop) - exec_output = BasicExecute.subst(iop) -}}; - -//////////////////////////////////////////////////////////////////// -// -// hw_ld, hw_st -// - -output header {{ - /** - * Base class for hw_ld and hw_st. - */ - class HwLoadStore : public Memory - { - protected: - - /// Displacement for EA calculation (signed). - int16_t disp; - - /// Constructor - HwLoadStore(const char *mnem, ExtMachInst _machInst, OpClass __opClass); - - std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const; - }; -}}; - - -output decoder {{ - inline - HwLoadStore::HwLoadStore(const char *mnem, ExtMachInst _machInst, - OpClass __opClass) - : Memory(mnem, _machInst, __opClass), disp(HW_LDST_DISP) - { - memAccessFlags.clear(); - if (HW_LDST_PHYS) memAccessFlags.set(Request::PHYSICAL); - if (HW_LDST_ALT) memAccessFlags.set(AlphaRequestFlags::ALTMODE); - if (HW_LDST_VPTE) memAccessFlags.set(AlphaRequestFlags::VPTE); - if (HW_LDST_LOCK) memAccessFlags.set(Request::LLSC); - } - - std::string - HwLoadStore::generateDisassembly(Addr pc, const SymbolTable *symtab) const - { -#ifdef SS_COMPATIBLE_DISASSEMBLY - return csprintf("%-10s r%d,%d(r%d)", mnemonic, RA, disp, RB); -#else - // HW_LDST_LOCK and HW_LDST_COND are the same bit. - const char *lock_str = - (HW_LDST_LOCK) ? (flags[IsLoad] ? ",LOCK" : ",COND") : ""; - - return csprintf("%-10s r%d,%d(r%d)%s%s%s%s%s", - mnemonic, RA, disp, RB, - HW_LDST_PHYS ? ",PHYS" : "", - HW_LDST_ALT ? ",ALT" : "", - HW_LDST_QUAD ? ",QUAD" : "", - HW_LDST_VPTE ? ",VPTE" : "", - lock_str); -#endif - } -}}; - -def format HwLoad(ea_code, memacc_code, class_ext, *flags) {{ - (header_output, decoder_output, decode_block, exec_output) = \ - LoadStoreBase(name, Name + class_ext, ea_code, memacc_code, - mem_flags = [], inst_flags = flags, - base_class = 'HwLoadStore', exec_template_base = 'Load') -}}; - - -def format HwStore(ea_code, memacc_code, class_ext, *flags) {{ - (header_output, decoder_output, decode_block, exec_output) = \ - LoadStoreBase(name, Name + class_ext, ea_code, memacc_code, - mem_flags = [], inst_flags = flags, - base_class = 'HwLoadStore', exec_template_base = 'Store') -}}; - - -def format HwStoreCond(ea_code, memacc_code, postacc_code, class_ext, - *flags) {{ - (header_output, decoder_output, decode_block, exec_output) = \ - LoadStoreBase(name, Name + class_ext, ea_code, memacc_code, - postacc_code, mem_flags = [], inst_flags = flags, - base_class = 'HwLoadStore') -}}; - - -output header {{ - /** - * Base class for hw_mfpr and hw_mtpr. - */ - class HwMoveIPR : public AlphaStaticInst - { - protected: - /// Index of internal processor register. - int ipr_index; - - /// Constructor - HwMoveIPR(const char *mnem, ExtMachInst _machInst, OpClass __opClass) - : AlphaStaticInst(mnem, _machInst, __opClass), - ipr_index(HW_IPR_IDX) - { - } - - std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const; - }; -}}; - -output decoder {{ - std::string - HwMoveIPR::generateDisassembly(Addr pc, const SymbolTable *symtab) const - { - if (_numSrcRegs > 0) { - // must be mtpr - return csprintf("%-10s r%d,IPR(%#x)", - mnemonic, RA, ipr_index); - } - else { - // must be mfpr - return csprintf("%-10s IPR(%#x),r%d", - mnemonic, ipr_index, RA); - } - } -}}; - -def format HwMoveIPR(code, *flags) {{ - all_flags = ['IprAccessOp'] - all_flags += flags - iop = InstObjParams(name, Name, 'HwMoveIPR', code, all_flags) - header_output = BasicDeclare.subst(iop) - decoder_output = BasicConstructor.subst(iop) - decode_block = BasicDecode.subst(iop) - exec_output = BasicExecute.subst(iop) -}}; - - diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/isa/unimp.isa --- a/src/arch/alpha/isa/unimp.isa Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,172 +0,0 @@ -// -*- mode:c++ -*- - -// Copyright (c) 2003-2005 The Regents of The University of Michigan -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are -// met: redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer; -// redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution; -// neither the name of the copyright holders nor the names of its -// contributors may be used to endorse or promote products derived from -// this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// Authors: Steve Reinhardt - -//////////////////////////////////////////////////////////////////// -// -// Unimplemented instructions -// - -output header {{ - /** - * Static instruction class for unimplemented instructions that - * cause simulator termination. Note that these are recognized - * (legal) instructions that the simulator does not support; the - * 'Unknown' class is used for unrecognized/illegal instructions. - * This is a leaf class. - */ - class FailUnimplemented : public AlphaStaticInst - { - public: - /// Constructor - FailUnimplemented(const char *_mnemonic, ExtMachInst _machInst) - : AlphaStaticInst(_mnemonic, _machInst, No_OpClass) - { - // don't call execute() (which panics) if we're on a - // speculative path - flags[IsNonSpeculative] = true; - } - - %(BasicExecDeclare)s - - std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const; - }; - - /** - * Base class for unimplemented instructions that cause a warning - * to be printed (but do not terminate simulation). This - * implementation is a little screwy in that it will print a - * warning for each instance of a particular unimplemented machine - * instruction, not just for each unimplemented opcode. Should - * probably make the 'warned' flag a static member of the derived - * class. - */ - class WarnUnimplemented : public AlphaStaticInst - { - private: - /// Have we warned on this instruction yet? - mutable bool warned; - - public: - /// Constructor - WarnUnimplemented(const char *_mnemonic, ExtMachInst _machInst) - : AlphaStaticInst(_mnemonic, _machInst, No_OpClass), warned(false) - { - // don't call execute() (which panics) if we're on a - // speculative path - flags[IsNonSpeculative] = true; - } - - %(BasicExecDeclare)s - - std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const; - }; -}}; - -output decoder {{ - std::string - FailUnimplemented::generateDisassembly(Addr pc, - const SymbolTable *symtab) const - { - return csprintf("%-10s (unimplemented)", mnemonic); - } - - std::string - WarnUnimplemented::generateDisassembly(Addr pc, - const SymbolTable *symtab) const - { -#ifdef SS_COMPATIBLE_DISASSEMBLY - return csprintf("%-10s", mnemonic); -#else - return csprintf("%-10s (unimplemented)", mnemonic); -#endif - } -}}; - -output exec {{ - Fault - FailUnimplemented::execute(CPU_EXEC_CONTEXT *xc, - Trace::InstRecord *traceData) const - { - panic("attempt to execute unimplemented instruction '%s' " - "(inst 0x%08x, opcode 0x%x)", mnemonic, machInst, OPCODE); - return std::make_shared(); - } - - Fault - WarnUnimplemented::execute(CPU_EXEC_CONTEXT *xc, - Trace::InstRecord *traceData) const - { - if (!warned) { - warn("instruction '%s' unimplemented\n", mnemonic); - warned = true; - } - - return NoFault; - } -}}; - - -def format FailUnimpl() {{ - iop = InstObjParams(name, 'FailUnimplemented') - decode_block = BasicDecodeWithMnemonic.subst(iop) -}}; - -def format WarnUnimpl() {{ - iop = InstObjParams(name, 'WarnUnimplemented') - decode_block = BasicDecodeWithMnemonic.subst(iop) -}}; - -output header {{ - /** - * Static instruction class for unknown (illegal) instructions. - * These cause simulator termination if they are executed in a - * non-speculative mode. This is a leaf class. - */ - class Unknown : public AlphaStaticInst - { - public: - /// Constructor - Unknown(ExtMachInst _machInst) - : AlphaStaticInst("unknown", _machInst, No_OpClass) - { - // don't call execute() (which panics) if we're on a - // speculative path - flags[IsNonSpeculative] = true; - } - - %(BasicExecDeclare)s - - std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const; - }; -}}; - diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/isa/unknown.isa --- a/src/arch/alpha/isa/unknown.isa Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,59 +0,0 @@ -// -*- mode:c++ -*- - -// Copyright (c) 2003-2005 The Regents of The University of Michigan -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are -// met: redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer; -// redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution; -// neither the name of the copyright holders nor the names of its -// contributors may be used to endorse or promote products derived from -// this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// Authors: Steve Reinhardt - -//////////////////////////////////////////////////////////////////// -// -// Unknown instructions -// - -output decoder {{ - std::string - Unknown::generateDisassembly(Addr pc, const SymbolTable *symtab) const - { - return csprintf("%-10s (inst 0x%x, opcode 0x%x)", - "unknown", machInst, OPCODE); - } -}}; - -output exec {{ - Fault - Unknown::execute(CPU_EXEC_CONTEXT *xc, - Trace::InstRecord *traceData) const - { - panic("attempt to execute unknown instruction " - "(inst 0x%08x, opcode 0x%x)", machInst, OPCODE); - return std::make_shared(); - } -}}; - -def format Unknown() {{ - decode_block = 'return new Unknown(machInst);\n' -}}; - diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/isa/util.isa --- a/src/arch/alpha/isa/util.isa Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,119 +0,0 @@ -// -*- mode:c++ -*- - -// Copyright (c) 2003-2005 The Regents of The University of Michigan -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are -// met: redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer; -// redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution; -// neither the name of the copyright holders nor the names of its -// contributors may be used to endorse or promote products derived from -// this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// Authors: Steve Reinhardt - -//////////////////////////////////////////////////////////////////// -// -// Utility functions for execute methods -// - -output exec {{ - - /// Return opa + opb, summing carry into third arg. - inline uint64_t - addc(uint64_t opa, uint64_t opb, int &carry) - { - uint64_t res = opa + opb; - if (res < opa || res < opb) - ++carry; - return res; - } - - /// Multiply two 64-bit values (opa * opb), returning the 128-bit - /// product in res_hi and res_lo. - inline void - mul128(uint64_t opa, uint64_t opb, uint64_t &res_hi, uint64_t &res_lo) - { - // do a 64x64 --> 128 multiply using four 32x32 --> 64 multiplies - uint64_t opa_hi = opa<63:32>; - uint64_t opa_lo = opa<31:0>; - uint64_t opb_hi = opb<63:32>; - uint64_t opb_lo = opb<31:0>; - - res_lo = opa_lo * opb_lo; - - // The middle partial products logically belong in bit - // positions 95 to 32. Thus the lower 32 bits of each product - // sum into the upper 32 bits of the low result, while the - // upper 32 sum into the low 32 bits of the upper result. - uint64_t partial1 = opa_hi * opb_lo; - uint64_t partial2 = opa_lo * opb_hi; - - uint64_t partial1_lo = partial1<31:0> << 32; - uint64_t partial1_hi = partial1<63:32>; - uint64_t partial2_lo = partial2<31:0> << 32; - uint64_t partial2_hi = partial2<63:32>; - - // Add partial1_lo and partial2_lo to res_lo, keeping track - // of any carries out - int carry_out = 0; - res_lo = addc(partial1_lo, res_lo, carry_out); - res_lo = addc(partial2_lo, res_lo, carry_out); - - // Now calculate the high 64 bits... - res_hi = (opa_hi * opb_hi) + partial1_hi + partial2_hi + carry_out; - } - - /// Map 8-bit S-floating exponent to 11-bit T-floating exponent. - /// See Table 2-2 of Alpha AHB. - inline int - map_s(int old_exp) - { - int hibit = old_exp<7:>; - int lobits = old_exp<6:0>; - - if (hibit == 1) { - return (lobits == 0x7f) ? 0x7ff : (0x400 | lobits); - } - else { - return (lobits == 0) ? 0 : (0x380 | lobits); - } - } - - /// Convert a 32-bit S-floating value to the equivalent 64-bit - /// representation to be stored in an FP reg. - inline uint64_t - s_to_t(uint32_t s_val) - { - uint64_t tmp = s_val; - return (tmp<31:> << 63 // sign bit - | (uint64_t)map_s(tmp<30:23>) << 52 // exponent - | tmp<22:0> << 29); // fraction - } - - /// Convert a 64-bit T-floating value to the equivalent 32-bit - /// S-floating representation to be stored in memory. - inline int32_t - t_to_s(uint64_t t_val) - { - return (t_val<63:62> << 30 // sign bit & hi exp bit - | t_val<58:29>); // rest of exp & fraction - } -}}; - diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/isa_traits.hh --- a/src/arch/alpha/isa_traits.hh Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,126 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Steve Reinhardt - * Gabe Black - */ - -#ifndef __ARCH_ALPHA_ISA_TRAITS_HH__ -#define __ARCH_ALPHA_ISA_TRAITS_HH__ - -namespace LittleEndianGuest {} - -#include "arch/alpha/ipr.hh" -#include "arch/alpha/types.hh" -#include "base/types.hh" -#include "cpu/static_inst_fwd.hh" - -namespace AlphaISA { - -using namespace LittleEndianGuest; - -StaticInstPtr decodeInst(ExtMachInst); - -// Alpha Does NOT have a delay slot -#define ISA_HAS_DELAY_SLOT 0 - -const Addr PageShift = 13; -const Addr PageBytes = ULL(1) << PageShift; -const Addr PageMask = ~(PageBytes - 1); -const Addr PageOffset = PageBytes - 1; - -//////////////////////////////////////////////////////////////////////// -// -// Translation stuff -// - -const Addr PteShift = 3; -const Addr NPtePageShift = PageShift - PteShift; -const Addr NPtePage = ULL(1) << NPtePageShift; -const Addr PteMask = NPtePage - 1; - -// User Virtual -const Addr USegBase = ULL(0x0); -const Addr USegEnd = ULL(0x000003ffffffffff); - -// Kernel Direct Mapped -const Addr K0SegBase = ULL(0xfffffc0000000000); -const Addr K0SegEnd = ULL(0xfffffdffffffffff); - -// Kernel Virtual -const Addr K1SegBase = ULL(0xfffffe0000000000); -const Addr K1SegEnd = ULL(0xffffffffffffffff); - -//////////////////////////////////////////////////////////////////////// -// -// Interrupt levels -// -enum InterruptLevels -{ - INTLEVEL_SOFTWARE_MIN = 4, - INTLEVEL_SOFTWARE_MAX = 19, - - INTLEVEL_EXTERNAL_MIN = 20, - INTLEVEL_EXTERNAL_MAX = 34, - - INTLEVEL_IRQ0 = 20, - INTLEVEL_IRQ1 = 21, - INTINDEX_ETHERNET = 0, - INTINDEX_SCSI = 1, - INTLEVEL_IRQ2 = 22, - INTLEVEL_IRQ3 = 23, - - INTLEVEL_SERIAL = 33, - - NumInterruptLevels = INTLEVEL_EXTERNAL_MAX -}; - -// EV5 modes -enum mode_type -{ - mode_kernel = 0, // kernel - mode_executive = 1, // executive (unused by unix) - mode_supervisor = 2, // supervisor (unused by unix) - mode_user = 3, // user mode - mode_number // number of modes -}; - -const int MachineBytes = 8; - -// return a no-op instruction... used for instruction fetch faults -// Alpha UNOP (ldq_u r31,0(r0)) -const ExtMachInst NoopMachInst = 0x2ffe0000; - -// Memory accesses cannot be unaligned -const bool HasUnalignedMemAcc = false; - -const bool CurThreadInfoImplemented = true; -const int CurThreadInfoReg = AlphaISA::IPR_PALtemp23; - -} // namespace AlphaISA - -#endif // __ARCH_ALPHA_ISA_TRAITS_HH__ diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/kernel_stats.hh --- a/src/arch/alpha/kernel_stats.hh Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,96 +0,0 @@ -/* - * Copyright (c) 2004-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Lisa Hsu - * Nathan Binkert - */ - -#ifndef __ARCH_ALPHA_KERNEL_STATS_HH__ -#define __ARCH_ALPHA_KERNEL_STATS_HH__ - -#include -#include -#include -#include - -#include "cpu/static_inst.hh" -#include "kern/kernel_stats.hh" - -class BaseCPU; -class ThreadContext; -class FnEvent; -// What does kernel stats expect is included? -class System; - -namespace AlphaISA { -namespace Kernel { - -enum cpu_mode { kernel, user, idle, cpu_mode_num }; -extern const char *modestr[]; - -class Statistics : public ::Kernel::Statistics -{ - protected: - Addr idleProcess; - cpu_mode themode; - Tick lastModeTick; - - void changeMode(cpu_mode newmode, ThreadContext *tc); - - private: - Stats::Vector _callpal; -// Stats::Vector _faults; - - Stats::Vector _mode; - Stats::Vector _modeGood; - Stats::Formula _modeFraction; - Stats::Vector _modeTicks; - - Stats::Scalar _swap_context; - - public: - Statistics(System *system); - - void regStats(const std::string &name); - - public: - void mode(cpu_mode newmode, ThreadContext *tc); - void context(Addr oldpcbb, Addr newpcbb, ThreadContext *tc); - void callpal(int code, ThreadContext *tc); - void hwrei() { _hwrei++; } - - void setIdleProcess(Addr idle, ThreadContext *tc); - - public: - void serialize(CheckpointOut &cp) const override; - void unserialize(CheckpointIn &cp) override; -}; - -} // namespace Kernel -} // namespace AlphaISA - -#endif // __ARCH_ALPHA_KERNEL_STATS_HH__ diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/kernel_stats.cc --- a/src/arch/alpha/kernel_stats.cc Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,218 +0,0 @@ -/* - * Copyright (c) 2004-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Lisa Hsu - * Nathan Binkert - */ - -#include -#include -#include - -#include "arch/generic/linux/threadinfo.hh" -#include "arch/alpha/kernel_stats.hh" -#include "arch/alpha/osfpal.hh" -#include "base/trace.hh" -#include "cpu/thread_context.hh" -#include "debug/Context.hh" -#include "kern/tru64/tru64_syscalls.hh" -#include "sim/system.hh" - -using namespace std; -using namespace Stats; - -namespace AlphaISA { -namespace Kernel { - -const char *modestr[] = { "kernel", "user", "idle" }; - -Statistics::Statistics(System *system) - : ::Kernel::Statistics(system), - idleProcess((Addr)-1), themode(kernel), lastModeTick(0) -{ -} - -void -Statistics::regStats(const string &_name) -{ - ::Kernel::Statistics::regStats(_name); - - _callpal - .init(256) - .name(name() + ".callpal") - .desc("number of callpals executed") - .flags(total | pdf | nozero | nonan) - ; - - for (int i = 0; i < PAL::NumCodes; ++i) { - const char *str = PAL::name(i); - if (str) - _callpal.subname(i, str); - } - - _hwrei - .name(name() + ".inst.hwrei") - .desc("number of hwrei instructions executed") - ; - - _mode - .init(cpu_mode_num) - .name(name() + ".mode_switch") - .desc("number of protection mode switches") - ; - - for (int i = 0; i < cpu_mode_num; ++i) - _mode.subname(i, modestr[i]); - - _modeGood - .init(cpu_mode_num) - .name(name() + ".mode_good") - ; - - for (int i = 0; i < cpu_mode_num; ++i) - _modeGood.subname(i, modestr[i]); - - _modeFraction - .name(name() + ".mode_switch_good") - .desc("fraction of useful protection mode switches") - .flags(total) - ; - - for (int i = 0; i < cpu_mode_num; ++i) - _modeFraction.subname(i, modestr[i]); - - _modeFraction = _modeGood / _mode; - - _modeTicks - .init(cpu_mode_num) - .name(name() + ".mode_ticks") - .desc("number of ticks spent at the given mode") - .flags(pdf) - ; - for (int i = 0; i < cpu_mode_num; ++i) - _modeTicks.subname(i, modestr[i]); - - _swap_context - .name(name() + ".swap_context") - .desc("number of times the context was actually changed") - ; -} - -void -Statistics::setIdleProcess(Addr idlepcbb, ThreadContext *tc) -{ - assert(themode == kernel); - idleProcess = idlepcbb; - themode = idle; - changeMode(themode, tc); -} - -void -Statistics::changeMode(cpu_mode newmode, ThreadContext *tc) -{ - _mode[newmode]++; - - if (newmode == themode) - return; - - DPRINTF(Context, "old mode=%s new mode=%s pid=%d\n", - modestr[themode], modestr[newmode], - Linux::ThreadInfo(tc).curTaskPID()); - - _modeGood[newmode]++; - _modeTicks[themode] += curTick() - lastModeTick; - - lastModeTick = curTick(); - themode = newmode; -} - -void -Statistics::mode(cpu_mode newmode, ThreadContext *tc) -{ - Addr pcbb = tc->readMiscRegNoEffect(IPR_PALtemp23); - - if (newmode == kernel && pcbb == idleProcess) - newmode = idle; - - changeMode(newmode, tc); -} - -void -Statistics::context(Addr oldpcbb, Addr newpcbb, ThreadContext *tc) -{ - assert(themode != user); - - _swap_context++; - changeMode(newpcbb == idleProcess ? idle : kernel, tc); - - DPRINTF(Context, "Context Switch old pid=%d new pid=%d\n", - Linux::ThreadInfo(tc, oldpcbb).curTaskPID(), - Linux::ThreadInfo(tc, newpcbb).curTaskPID()); -} - -void -Statistics::callpal(int code, ThreadContext *tc) -{ - if (!PAL::name(code)) - return; - - _callpal[code]++; - - switch (code) { - case PAL::callsys: { - int number = tc->readIntReg(0); - if (SystemCalls::validSyscallNumber(number)) { - int cvtnum = SystemCalls::convert(number); - _syscall[cvtnum]++; - } - } break; - } -} - -void -Statistics::serialize(CheckpointOut &cp) const -{ - ::Kernel::Statistics::serialize(cp); - int exemode = themode; - SERIALIZE_SCALAR(exemode); - SERIALIZE_SCALAR(idleProcess); - SERIALIZE_SCALAR(lastModeTick); -} - -void -Statistics::unserialize(CheckpointIn &cp) -{ - ::Kernel::Statistics::unserialize(cp); - int exemode; - UNSERIALIZE_SCALAR(exemode); - UNSERIALIZE_SCALAR(idleProcess); - UNSERIALIZE_SCALAR(lastModeTick); - themode = (cpu_mode)exemode; -} - -} // namespace Kernel -} // namespace AlphaISA diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/linux/linux.hh --- a/src/arch/alpha/linux/linux.hh Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,201 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Korey Sewell - */ - -#ifndef __ALPHA_ALPHA_LINUX_LINUX_HH__ -#define __ALPHA_ALPHA_LINUX_LINUX_HH__ - -#include "kern/linux/linux.hh" - -/* AlphaLinux class contains static constants/definitions/misc. - * structures which are specific to the Linux OS AND the Alpha - * architecture - */ -class AlphaLinux : public Linux -{ - public: - - static const int TGT_SIGHUP = 0x000001; - static const int TGT_SIGINT = 0x000002; - static const int TGT_SIGQUIT = 0x000003; - static const int TGT_SIGILL = 0x000004; - static const int TGT_SIGTRAP = 0x000005; - static const int TGT_SIGABRT = 0x000006; - static const int TGT_SIGEMT = 0x000007; - static const int TGT_SIGFPE = 0x000008; - static const int TGT_SIGKILL = 0x000009; - static const int TGT_SIGBUS = 0x00000a; - static const int TGT_SIGSEGV = 0x00000b; - static const int TGT_SIGSYS = 0x00000c; - static const int TGT_SIGPIPE = 0x00000d; - static const int TGT_SIGALRM = 0x00000e; - static const int TGT_SIGTERM = 0x00000f; - static const int TGT_SIGURG = 0x000010; - static const int TGT_SIGSTOP = 0x000011; - static const int TGT_SIGTSTP = 0x000012; - static const int TGT_SIGCONT = 0x000013; - static const int TGT_SIGCHLD = 0x000014; - static const int TGT_SIGTTIN = 0x000015; - static const int TGT_SIGTTOU = 0x000016; - static const int TGT_SIGIO = 0x000017; - static const int TGT_SIGXCPU = 0x000018; - static const int TGT_SIGXFSZ = 0x000019; - static const int TGT_SIGVTALRM = 0x00001a; - static const int TGT_SIGPROF = 0x00001b; - static const int TGT_SIGWINCH = 0x00001c; - static const int TGT_SIGINFO = 0x00001d; - static const int TGT_SIGUSR1 = 0x00001e; - static const int TGT_SIGUSR2 = 0x00001f; - - /// This table maps the target open() flags to the corresponding - /// host open() flags. - static SyscallFlagTransTable openFlagTable[]; - - /// Number of entries in openFlagTable[]. - static const int NUM_OPEN_FLAGS; - - //@{ - /// open(2) flag values. - static const int TGT_O_RDONLY = 000000000; //!< O_RDONLY - static const int TGT_O_WRONLY = 000000001; //!< O_WRONLY - static const int TGT_O_RDWR = 000000002; //!< O_RDWR - static const int TGT_O_CREAT = 000001000; //!< O_CREAT - static const int TGT_O_EXCL = 000004000; //!< O_EXCL - static const int TGT_O_NOCTTY = 000010000; //!< O_NOCTTY - static const int TGT_O_TRUNC = 000002000; //!< O_TRUNC - static const int TGT_O_APPEND = 000000010; //!< O_APPEND - static const int TGT_O_NONBLOCK = 000000004; //!< O_NONBLOCK - static const int TGT_O_DSYNC = 000040000; //!< O_DSYNC - static const int TGT_FASYNC = 000020000; //!< FASYNC - static const int TGT_O_DIRECT = 002000000; //!< O_DIRECT - static const int TGT_O_LARGEFILE = 000400000; //!< O_LARGEFILE - static const int TGT_O_DIRECTORY = 000100000; //!< O_DIRECTORY - static const int TGT_O_NOFOLLOW = 000200000; //!< O_NOFOLLOW - static const int TGT_O_NOATIME = 004000000; //!< O_NOATIME - static const int TGT_O_CLOEXEC = 010000000; //!< O_CLOEXEC - static const int TGT_O_SYNC = 020040000; //!< O_SYNC - static const int TGT_O_PATH = 040000000; //!< O_PATH - //@} - - static const unsigned TGT_MAP_SHARED = 0x000001; - static const unsigned TGT_MAP_PRIVATE = 0x000002; - static const unsigned TGT_MAP_ANON = 0x000010; - static const unsigned TGT_MAP_DENYWRITE = 0x002000; - static const unsigned TGT_MAP_EXECUTABLE = 0x004000; - static const unsigned TGT_MAP_FILE = 0x000000; - static const unsigned TGT_MAP_GROWSDOWN = 0x001000; - static const unsigned TGT_MAP_HUGETLB = 0x100000; - static const unsigned TGT_MAP_LOCKED = 0x008000; - static const unsigned TGT_MAP_NONBLOCK = 0x040000; - static const unsigned TGT_MAP_NORESERVE = 0x010000; - static const unsigned TGT_MAP_POPULATE = 0x020000; - static const unsigned TGT_MAP_STACK = 0x080000; - static const unsigned TGT_MAP_ANONYMOUS = 0x000010; - static const unsigned TGT_MAP_FIXED = 0x000100; - - static const unsigned NUM_MMAP_FLAGS; - - //@{ - /// For getsysinfo(). - static const unsigned GSI_PLATFORM_NAME = 103; //!< platform name as string - static const unsigned GSI_CPU_INFO = 59; //!< CPU information - static const unsigned GSI_PROC_TYPE = 60; //!< get proc_type - static const unsigned GSI_MAX_CPU = 30; //!< max # CPUs on machine - static const unsigned GSI_CPUS_IN_BOX = 55; //!< number of CPUs in system - static const unsigned GSI_PHYSMEM = 19; //!< Physical memory in KB - static const unsigned GSI_CLK_TCK = 42; //!< clock freq in Hz - static const unsigned GSI_IEEE_FP_CONTROL = 45; - //@} - - //@{ - /// For setsysinfo(). - static const unsigned SSI_IEEE_FP_CONTROL = 14; //!< ieee_set_fp_control() - //@} - - //@{ - /// ioctl() command codes. - static const unsigned TGT_TIOCGETP = 0x40067408; - static const unsigned TGT_TIOCSETP = 0x80067409; - static const unsigned TGT_TIOCSETN = 0x8006740a; - static const unsigned TGT_TIOCSETC = 0x80067411; - static const unsigned TGT_TIOCGETC = 0x40067412; - static const unsigned TGT_FIONREAD = 0x4004667f; - static const unsigned TGT_TCGETS = 0x402c7413; - static const unsigned TGT_TCGETA = 0x40127417; - static const unsigned TGT_TCSETAW = 0x80147419; // 2.6.15 kernel - //@} - - static bool - isTtyReq(unsigned req) - { - switch (req) { - case TGT_TIOCGETP: - case TGT_TIOCSETP: - case TGT_TIOCSETN: - case TGT_TIOCSETC: - case TGT_TIOCGETC: - case TGT_TCGETS: - case TGT_TCGETA: - case TGT_TCSETAW: - return true; - default: - return false; - } - } - - /// For table(). - static const int TBL_SYSINFO = 12; - - /// Resource constants for getrlimit() (overide some generics). - static const unsigned TGT_RLIMIT_NPROC = 8; - static const unsigned TGT_RLIMIT_AS = 7; - static const unsigned TGT_RLIMIT_NOFILE = 6; - static const unsigned TGT_RLIMIT_MEMLOCK = 9; - - typedef struct { - int64_t uptime; /* Seconds since boot */ - uint64_t loads[3]; /* 1, 5, and 15 minute load averages */ - uint64_t totalram; /* Total usable main memory size */ - uint64_t freeram; /* Available memory size */ - uint64_t sharedram; /* Amount of shared memory */ - uint64_t bufferram; /* Memory used by buffers */ - uint64_t totalswap; /* Total swap space size */ - uint64_t freeswap; /* swap space still available */ - uint16_t procs; /* Number of current processes */ - uint64_t totalhigh; /* Total high memory size */ - uint64_t freehigh; /* Available high memory size */ - uint64_t mem_unit; /* Memory unit size in bytes */ - } tgt_sysinfo; - - // For futex system call - static const unsigned TGT_EAGAIN = 35; - static const unsigned TGT_EWOULDBLOCK = TGT_EAGAIN; -}; - -#endif // __ALPHA_ALPHA_LINUX_LINUX_HH__ diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/linux/linux.cc --- a/src/arch/alpha/linux/linux.cc Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,37 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Korey Sewell - */ - -#include "arch/alpha/linux/linux.hh" - -#include -#include - -#define TARGET AlphaLinux -#include "kern/linux/flag_tables.hh" diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/linux/process.hh --- a/src/arch/alpha/linux/process.hh Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,55 +0,0 @@ -/* - * Copyright (c) 2003-2004 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Steve Reinhardt - */ - -#ifndef __ALPHA_LINUX_PROCESS_HH__ -#define __ALPHA_LINUX_PROCESS_HH__ - -#include "arch/alpha/process.hh" - -namespace AlphaISA { - -/// A process with emulated Alpha/Linux syscalls. -class AlphaLinuxProcess : public AlphaLiveProcess -{ - public: - /// Constructor. - AlphaLinuxProcess(LiveProcessParams * params, ObjectFile *objFile); - - virtual SyscallDesc* getDesc(int callnum); - - /// Array of syscall descriptors, indexed by call number. - static SyscallDesc syscallDescs[]; - - const int Num_Syscall_Descs; -}; - -} // namespace AlphaISA - -#endif // __ALPHA_LINUX_PROCESS_HH__ diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/linux/process.cc --- a/src/arch/alpha/linux/process.cc Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,589 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Steve Reinhardt - * Ali Saidi - */ - -#include "arch/alpha/linux/linux.hh" -#include "arch/alpha/linux/process.hh" -#include "arch/alpha/isa_traits.hh" -#include "base/trace.hh" -#include "cpu/thread_context.hh" -#include "debug/SyscallVerbose.hh" -#include "kern/linux/linux.hh" -#include "sim/process.hh" -#include "sim/syscall_emul.hh" - -using namespace std; -using namespace AlphaISA; - -/// Target uname() handler. -static SyscallReturn -unameFunc(SyscallDesc *desc, int callnum, LiveProcess *process, - ThreadContext *tc) -{ - int index = 0; - TypedBufferArg name(process->getSyscallArg(tc, index)); - - strcpy(name->sysname, "Linux"); - strcpy(name->nodename, "sim.gem5.org"); - strcpy(name->release, "3.0.0"); - strcpy(name->version, "#1 Mon Aug 18 11:32:15 EDT 2003"); - strcpy(name->machine, "alpha"); - - name.copyOut(tc->getMemProxy()); - return 0; -} - -/// Target osf_getsysyinfo() handler. Even though this call is -/// borrowed from Tru64, the subcases that get used appear to be -/// different in practice from those used by Tru64 processes. -static SyscallReturn -osf_getsysinfoFunc(SyscallDesc *desc, int callnum, LiveProcess *process, - ThreadContext *tc) -{ - int index = 0; - unsigned op = process->getSyscallArg(tc, index); - Addr bufPtr = process->getSyscallArg(tc, index); - // unsigned nbytes = process->getSyscallArg(tc, 2); - - switch (op) { - - case 45: { // GSI_IEEE_FP_CONTROL - TypedBufferArg fpcr(bufPtr); - // I don't think this exactly matches the HW FPCR - *fpcr = 0; - fpcr.copyOut(tc->getMemProxy()); - return 0; - } - - default: - cerr << "osf_getsysinfo: unknown op " << op << endl; - abort(); - break; - } - - return 1; -} - -/// Target osf_setsysinfo() handler. -static SyscallReturn -osf_setsysinfoFunc(SyscallDesc *desc, int callnum, LiveProcess *process, - ThreadContext *tc) -{ - int index = 0; - unsigned op = process->getSyscallArg(tc, index); - Addr bufPtr = process->getSyscallArg(tc, index); - // unsigned nbytes = process->getSyscallArg(tc, 2); - - switch (op) { - - case 14: { // SSI_IEEE_FP_CONTROL - TypedBufferArg fpcr(bufPtr); - // I don't think this exactly matches the HW FPCR - fpcr.copyIn(tc->getMemProxy()); - DPRINTFR(SyscallVerbose, "osf_setsysinfo(SSI_IEEE_FP_CONTROL): " - " setting FPCR to 0x%x\n", gtoh(*(uint64_t*)fpcr)); - return 0; - } - - default: - cerr << "osf_setsysinfo: unknown op " << op << endl; - abort(); - break; - } - - return 1; -} - - -SyscallDesc AlphaLinuxProcess::syscallDescs[] = { - /* 0 */ SyscallDesc("osf_syscall", unimplementedFunc), - /* 1 */ SyscallDesc("exit", exitFunc), - /* 2 */ SyscallDesc("fork", unimplementedFunc), - /* 3 */ SyscallDesc("read", readFunc), - /* 4 */ SyscallDesc("write", writeFunc), - /* 5 */ SyscallDesc("osf_old_open", unimplementedFunc), - /* 6 */ SyscallDesc("close", closeFunc), - /* 7 */ SyscallDesc("osf_wait4", unimplementedFunc), - /* 8 */ SyscallDesc("osf_old_creat", unimplementedFunc), - /* 9 */ SyscallDesc("link", unimplementedFunc), - /* 10 */ SyscallDesc("unlink", unlinkFunc), - /* 11 */ SyscallDesc("osf_execve", unimplementedFunc), - /* 12 */ SyscallDesc("chdir", unimplementedFunc), - /* 13 */ SyscallDesc("fchdir", unimplementedFunc), - /* 14 */ SyscallDesc("mknod", unimplementedFunc), - /* 15 */ SyscallDesc("chmod", chmodFunc), - /* 16 */ SyscallDesc("chown", chownFunc), - /* 17 */ SyscallDesc("brk", brkFunc), - /* 18 */ SyscallDesc("osf_getfsstat", unimplementedFunc), - /* 19 */ SyscallDesc("lseek", lseekFunc), - /* 20 */ SyscallDesc("getxpid", getpidPseudoFunc), - /* 21 */ SyscallDesc("osf_mount", unimplementedFunc), - /* 22 */ SyscallDesc("umount", unimplementedFunc), - /* 23 */ SyscallDesc("setuid", setuidFunc), - /* 24 */ SyscallDesc("getxuid", getuidPseudoFunc), - /* 25 */ SyscallDesc("exec_with_loader", unimplementedFunc), - /* 26 */ SyscallDesc("osf_ptrace", unimplementedFunc), - /* 27 */ SyscallDesc("osf_nrecvmsg", unimplementedFunc), - /* 28 */ SyscallDesc("osf_nsendmsg", unimplementedFunc), - /* 29 */ SyscallDesc("osf_nrecvfrom", unimplementedFunc), - /* 30 */ SyscallDesc("osf_naccept", unimplementedFunc), - /* 31 */ SyscallDesc("osf_ngetpeername", unimplementedFunc), - /* 32 */ SyscallDesc("osf_ngetsockname", unimplementedFunc), - /* 33 */ SyscallDesc("access", unimplementedFunc), - /* 34 */ SyscallDesc("osf_chflags", unimplementedFunc), - /* 35 */ SyscallDesc("osf_fchflags", unimplementedFunc), - /* 36 */ SyscallDesc("sync", unimplementedFunc), - /* 37 */ SyscallDesc("kill", unimplementedFunc), - /* 38 */ SyscallDesc("osf_old_stat", unimplementedFunc), - /* 39 */ SyscallDesc("setpgid", unimplementedFunc), - /* 40 */ SyscallDesc("osf_old_lstat", unimplementedFunc), - /* 41 */ SyscallDesc("dup", dupFunc), - /* 42 */ SyscallDesc("pipe", pipePseudoFunc), - /* 43 */ SyscallDesc("osf_set_program_attributes", unimplementedFunc), - /* 44 */ SyscallDesc("osf_profil", unimplementedFunc), - /* 45 */ SyscallDesc("open", openFunc), - /* 46 */ SyscallDesc("osf_old_sigaction", unimplementedFunc), - /* 47 */ SyscallDesc("getxgid", getgidPseudoFunc), - /* 48 */ SyscallDesc("osf_sigprocmask", ignoreFunc), - /* 49 */ SyscallDesc("osf_getlogin", unimplementedFunc), - /* 50 */ SyscallDesc("osf_setlogin", unimplementedFunc), - /* 51 */ SyscallDesc("acct", unimplementedFunc), - /* 52 */ SyscallDesc("sigpending", unimplementedFunc), - /* 53 */ SyscallDesc("osf_classcntl", unimplementedFunc), - /* 54 */ SyscallDesc("ioctl", ioctlFunc), - /* 55 */ SyscallDesc("osf_reboot", unimplementedFunc), - /* 56 */ SyscallDesc("osf_revoke", unimplementedFunc), - /* 57 */ SyscallDesc("symlink", unimplementedFunc), - /* 58 */ SyscallDesc("readlink", readlinkFunc), - /* 59 */ SyscallDesc("execve", unimplementedFunc), - /* 60 */ SyscallDesc("umask", umaskFunc), - /* 61 */ SyscallDesc("chroot", unimplementedFunc), - /* 62 */ SyscallDesc("osf_old_fstat", unimplementedFunc), - /* 63 */ SyscallDesc("getpgrp", unimplementedFunc), - /* 64 */ SyscallDesc("getpagesize", getpagesizeFunc), - /* 65 */ SyscallDesc("osf_mremap", unimplementedFunc), - /* 66 */ SyscallDesc("vfork", unimplementedFunc), - /* 67 */ SyscallDesc("stat", statFunc), - /* 68 */ SyscallDesc("lstat", lstatFunc), - /* 69 */ SyscallDesc("osf_sbrk", unimplementedFunc), - /* 70 */ SyscallDesc("osf_sstk", unimplementedFunc), - /* 71 */ SyscallDesc("mmap", mmapFunc), - /* 72 */ SyscallDesc("osf_old_vadvise", unimplementedFunc), - /* 73 */ SyscallDesc("munmap", munmapFunc), - /* 74 */ SyscallDesc("mprotect", ignoreFunc), - /* 75 */ SyscallDesc("madvise", unimplementedFunc), - /* 76 */ SyscallDesc("vhangup", unimplementedFunc), - /* 77 */ SyscallDesc("osf_kmodcall", unimplementedFunc), - /* 78 */ SyscallDesc("osf_mincore", unimplementedFunc), - /* 79 */ SyscallDesc("getgroups", unimplementedFunc), - /* 80 */ SyscallDesc("setgroups", unimplementedFunc), - /* 81 */ SyscallDesc("osf_old_getpgrp", unimplementedFunc), - /* 82 */ SyscallDesc("setpgrp", unimplementedFunc), - /* 83 */ SyscallDesc("osf_setitimer", unimplementedFunc), - /* 84 */ SyscallDesc("osf_old_wait", unimplementedFunc), - /* 85 */ SyscallDesc("osf_table", unimplementedFunc), - /* 86 */ SyscallDesc("osf_getitimer", unimplementedFunc), - /* 87 */ SyscallDesc("gethostname", gethostnameFunc), - /* 88 */ SyscallDesc("sethostname", unimplementedFunc), - /* 89 */ SyscallDesc("getdtablesize", unimplementedFunc), - /* 90 */ SyscallDesc("dup2", unimplementedFunc), - /* 91 */ SyscallDesc("fstat", fstatFunc), - /* 92 */ SyscallDesc("fcntl", fcntlFunc), - /* 93 */ SyscallDesc("osf_select", unimplementedFunc), - /* 94 */ SyscallDesc("poll", unimplementedFunc), - /* 95 */ SyscallDesc("fsync", unimplementedFunc), - /* 96 */ SyscallDesc("setpriority", unimplementedFunc), - /* 97 */ SyscallDesc("socket", unimplementedFunc), - /* 98 */ SyscallDesc("connect", unimplementedFunc), - /* 99 */ SyscallDesc("accept", unimplementedFunc), - /* 100 */ SyscallDesc("getpriority", unimplementedFunc), - /* 101 */ SyscallDesc("send", unimplementedFunc), - /* 102 */ SyscallDesc("recv", unimplementedFunc), - /* 103 */ SyscallDesc("sigreturn", unimplementedFunc), - /* 104 */ SyscallDesc("bind", unimplementedFunc), - /* 105 */ SyscallDesc("setsockopt", unimplementedFunc), - /* 106 */ SyscallDesc("listen", unimplementedFunc), - /* 107 */ SyscallDesc("osf_plock", unimplementedFunc), - /* 108 */ SyscallDesc("osf_old_sigvec", unimplementedFunc), - /* 109 */ SyscallDesc("osf_old_sigblock", unimplementedFunc), - /* 110 */ SyscallDesc("osf_old_sigsetmask", unimplementedFunc), - /* 111 */ SyscallDesc("sigsuspend", unimplementedFunc), - /* 112 */ SyscallDesc("osf_sigstack", ignoreFunc), - /* 113 */ SyscallDesc("recvmsg", unimplementedFunc), - /* 114 */ SyscallDesc("sendmsg", unimplementedFunc), - /* 115 */ SyscallDesc("osf_old_vtrace", unimplementedFunc), - /* 116 */ SyscallDesc("osf_gettimeofday", unimplementedFunc), - /* 117 */ SyscallDesc("osf_getrusage", unimplementedFunc), - /* 118 */ SyscallDesc("getsockopt", unimplementedFunc), - /* 119 */ SyscallDesc("numa_syscalls", unimplementedFunc), - /* 120 */ SyscallDesc("readv", unimplementedFunc), - /* 121 */ SyscallDesc("writev", writevFunc), - /* 122 */ SyscallDesc("osf_settimeofday", unimplementedFunc), - /* 123 */ SyscallDesc("fchown", fchownFunc), - /* 124 */ SyscallDesc("fchmod", fchmodFunc), - /* 125 */ SyscallDesc("recvfrom", unimplementedFunc), - /* 126 */ SyscallDesc("setreuid", unimplementedFunc), - /* 127 */ SyscallDesc("setregid", unimplementedFunc), - /* 128 */ SyscallDesc("rename", renameFunc), - /* 129 */ SyscallDesc("truncate", truncateFunc), - /* 130 */ SyscallDesc("ftruncate", ftruncateFunc), - /* 131 */ SyscallDesc("flock", unimplementedFunc), - /* 132 */ SyscallDesc("setgid", unimplementedFunc), - /* 133 */ SyscallDesc("sendto", unimplementedFunc), - /* 134 */ SyscallDesc("shutdown", unimplementedFunc), - /* 135 */ SyscallDesc("socketpair", unimplementedFunc), - /* 136 */ SyscallDesc("mkdir", mkdirFunc), - /* 137 */ SyscallDesc("rmdir", unimplementedFunc), - /* 138 */ SyscallDesc("osf_utimes", unimplementedFunc), - /* 139 */ SyscallDesc("osf_old_sigreturn", unimplementedFunc), - /* 140 */ SyscallDesc("osf_adjtime", unimplementedFunc), - /* 141 */ SyscallDesc("getpeername", unimplementedFunc), - /* 142 */ SyscallDesc("osf_gethostid", unimplementedFunc), - /* 143 */ SyscallDesc("osf_sethostid", unimplementedFunc), - /* 144 */ SyscallDesc("getrlimit", getrlimitFunc), - /* 145 */ SyscallDesc("setrlimit", ignoreFunc), - /* 146 */ SyscallDesc("osf_old_killpg", unimplementedFunc), - /* 147 */ SyscallDesc("setsid", unimplementedFunc), - /* 148 */ SyscallDesc("quotactl", unimplementedFunc), - /* 149 */ SyscallDesc("osf_oldquota", unimplementedFunc), - /* 150 */ SyscallDesc("getsockname", unimplementedFunc), - /* 151 */ SyscallDesc("osf_pread", unimplementedFunc), - /* 152 */ SyscallDesc("osf_pwrite", unimplementedFunc), - /* 153 */ SyscallDesc("osf_pid_block", unimplementedFunc), - /* 154 */ SyscallDesc("osf_pid_unblock", unimplementedFunc), - /* 155 */ SyscallDesc("osf_signal_urti", unimplementedFunc), - /* 156 */ SyscallDesc("sigaction", ignoreFunc), - /* 157 */ SyscallDesc("osf_sigwaitprim", unimplementedFunc), - /* 158 */ SyscallDesc("osf_nfssvc", unimplementedFunc), - /* 159 */ SyscallDesc("osf_getdirentries", unimplementedFunc), - /* 160 */ SyscallDesc("osf_statfs", unimplementedFunc), - /* 161 */ SyscallDesc("osf_fstatfs", unimplementedFunc), - /* 162 */ SyscallDesc("unknown #162", unimplementedFunc), - /* 163 */ SyscallDesc("osf_async_daemon", unimplementedFunc), - /* 164 */ SyscallDesc("osf_getfh", unimplementedFunc), - /* 165 */ SyscallDesc("osf_getdomainname", unimplementedFunc), - /* 166 */ SyscallDesc("setdomainname", unimplementedFunc), - /* 167 */ SyscallDesc("unknown #167", unimplementedFunc), - /* 168 */ SyscallDesc("unknown #168", unimplementedFunc), - /* 169 */ SyscallDesc("osf_exportfs", unimplementedFunc), - /* 170 */ SyscallDesc("unknown #170", unimplementedFunc), - /* 171 */ SyscallDesc("unknown #171", unimplementedFunc), - /* 172 */ SyscallDesc("unknown #172", unimplementedFunc), - /* 173 */ SyscallDesc("unknown #173", unimplementedFunc), - /* 174 */ SyscallDesc("unknown #174", unimplementedFunc), - /* 175 */ SyscallDesc("unknown #175", unimplementedFunc), - /* 176 */ SyscallDesc("unknown #176", unimplementedFunc), - /* 177 */ SyscallDesc("unknown #177", unimplementedFunc), - /* 178 */ SyscallDesc("unknown #178", unimplementedFunc), - /* 179 */ SyscallDesc("unknown #179", unimplementedFunc), - /* 180 */ SyscallDesc("unknown #180", unimplementedFunc), - /* 181 */ SyscallDesc("osf_alt_plock", unimplementedFunc), - /* 182 */ SyscallDesc("unknown #182", unimplementedFunc), - /* 183 */ SyscallDesc("unknown #183", unimplementedFunc), - /* 184 */ SyscallDesc("osf_getmnt", unimplementedFunc), - /* 185 */ SyscallDesc("unknown #185", unimplementedFunc), - /* 186 */ SyscallDesc("unknown #186", unimplementedFunc), - /* 187 */ SyscallDesc("osf_alt_sigpending", unimplementedFunc), - /* 188 */ SyscallDesc("osf_alt_setsid", unimplementedFunc), - /* 189 */ SyscallDesc("unknown #189", unimplementedFunc), - /* 190 */ SyscallDesc("unknown #190", unimplementedFunc), - /* 191 */ SyscallDesc("unknown #191", unimplementedFunc), - /* 192 */ SyscallDesc("unknown #192", unimplementedFunc), - /* 193 */ SyscallDesc("unknown #193", unimplementedFunc), - /* 194 */ SyscallDesc("unknown #194", unimplementedFunc), - /* 195 */ SyscallDesc("unknown #195", unimplementedFunc), - /* 196 */ SyscallDesc("unknown #196", unimplementedFunc), - /* 197 */ SyscallDesc("unknown #197", unimplementedFunc), - /* 198 */ SyscallDesc("unknown #198", unimplementedFunc), - /* 199 */ SyscallDesc("osf_swapon", unimplementedFunc), - /* 200 */ SyscallDesc("msgctl", unimplementedFunc), - /* 201 */ SyscallDesc("msgget", unimplementedFunc), - /* 202 */ SyscallDesc("msgrcv", unimplementedFunc), - /* 203 */ SyscallDesc("msgsnd", unimplementedFunc), - /* 204 */ SyscallDesc("semctl", unimplementedFunc), - /* 205 */ SyscallDesc("semget", unimplementedFunc), - /* 206 */ SyscallDesc("semop", unimplementedFunc), - /* 207 */ SyscallDesc("osf_utsname", unimplementedFunc), - /* 208 */ SyscallDesc("lchown", unimplementedFunc), - /* 209 */ SyscallDesc("osf_shmat", unimplementedFunc), - /* 210 */ SyscallDesc("shmctl", unimplementedFunc), - /* 211 */ SyscallDesc("shmdt", unimplementedFunc), - /* 212 */ SyscallDesc("shmget", unimplementedFunc), - /* 213 */ SyscallDesc("osf_mvalid", unimplementedFunc), - /* 214 */ SyscallDesc("osf_getaddressconf", unimplementedFunc), - /* 215 */ SyscallDesc("osf_msleep", unimplementedFunc), - /* 216 */ SyscallDesc("osf_mwakeup", unimplementedFunc), - /* 217 */ SyscallDesc("msync", unimplementedFunc), - /* 218 */ SyscallDesc("osf_signal", unimplementedFunc), - /* 219 */ SyscallDesc("osf_utc_gettime", unimplementedFunc), - /* 220 */ SyscallDesc("osf_utc_adjtime", unimplementedFunc), - /* 221 */ SyscallDesc("unknown #221", unimplementedFunc), - /* 222 */ SyscallDesc("osf_security", unimplementedFunc), - /* 223 */ SyscallDesc("osf_kloadcall", unimplementedFunc), - /* 224 */ SyscallDesc("unknown #224", unimplementedFunc), - /* 225 */ SyscallDesc("unknown #225", unimplementedFunc), - /* 226 */ SyscallDesc("unknown #226", unimplementedFunc), - /* 227 */ SyscallDesc("unknown #227", unimplementedFunc), - /* 228 */ SyscallDesc("unknown #228", unimplementedFunc), - /* 229 */ SyscallDesc("unknown #229", unimplementedFunc), - /* 230 */ SyscallDesc("unknown #230", unimplementedFunc), - /* 231 */ SyscallDesc("unknown #231", unimplementedFunc), - /* 232 */ SyscallDesc("unknown #232", unimplementedFunc), - /* 233 */ SyscallDesc("getpgid", unimplementedFunc), - /* 234 */ SyscallDesc("getsid", unimplementedFunc), - /* 235 */ SyscallDesc("sigaltstack", ignoreFunc), - /* 236 */ SyscallDesc("osf_waitid", unimplementedFunc), - /* 237 */ SyscallDesc("osf_priocntlset", unimplementedFunc), - /* 238 */ SyscallDesc("osf_sigsendset", unimplementedFunc), - /* 239 */ SyscallDesc("osf_set_speculative", unimplementedFunc), - /* 240 */ SyscallDesc("osf_msfs_syscall", unimplementedFunc), - /* 241 */ SyscallDesc("osf_sysinfo", unimplementedFunc), - /* 242 */ SyscallDesc("osf_uadmin", unimplementedFunc), - /* 243 */ SyscallDesc("osf_fuser", unimplementedFunc), - /* 244 */ SyscallDesc("osf_proplist_syscall", unimplementedFunc), - /* 245 */ SyscallDesc("osf_ntp_adjtime", unimplementedFunc), - /* 246 */ SyscallDesc("osf_ntp_gettime", unimplementedFunc), - /* 247 */ SyscallDesc("osf_pathconf", unimplementedFunc), - /* 248 */ SyscallDesc("osf_fpathconf", unimplementedFunc), - /* 249 */ SyscallDesc("unknown #249", unimplementedFunc), - /* 250 */ SyscallDesc("osf_uswitch", unimplementedFunc), - /* 251 */ SyscallDesc("osf_usleep_thread", unimplementedFunc), - /* 252 */ SyscallDesc("osf_audcntl", unimplementedFunc), - /* 253 */ SyscallDesc("osf_audgen", unimplementedFunc), - /* 254 */ SyscallDesc("sysfs", unimplementedFunc), - /* 255 */ SyscallDesc("osf_subsys_info", unimplementedFunc), - /* 256 */ SyscallDesc("osf_getsysinfo", osf_getsysinfoFunc), - /* 257 */ SyscallDesc("osf_setsysinfo", osf_setsysinfoFunc), - /* 258 */ SyscallDesc("osf_afs_syscall", unimplementedFunc), - /* 259 */ SyscallDesc("osf_swapctl", unimplementedFunc), - /* 260 */ SyscallDesc("osf_memcntl", unimplementedFunc), - /* 261 */ SyscallDesc("osf_fdatasync", unimplementedFunc), - /* 262 */ SyscallDesc("unknown #262", unimplementedFunc), - /* 263 */ SyscallDesc("unknown #263", unimplementedFunc), - /* 264 */ SyscallDesc("unknown #264", unimplementedFunc), - /* 265 */ SyscallDesc("unknown #265", unimplementedFunc), - /* 266 */ SyscallDesc("unknown #266", unimplementedFunc), - /* 267 */ SyscallDesc("unknown #267", unimplementedFunc), - /* 268 */ SyscallDesc("unknown #268", unimplementedFunc), - /* 269 */ SyscallDesc("unknown #269", unimplementedFunc), - /* 270 */ SyscallDesc("unknown #270", unimplementedFunc), - /* 271 */ SyscallDesc("unknown #271", unimplementedFunc), - /* 272 */ SyscallDesc("unknown #272", unimplementedFunc), - /* 273 */ SyscallDesc("unknown #273", unimplementedFunc), - /* 274 */ SyscallDesc("unknown #274", unimplementedFunc), - /* 275 */ SyscallDesc("unknown #275", unimplementedFunc), - /* 276 */ SyscallDesc("unknown #276", unimplementedFunc), - /* 277 */ SyscallDesc("unknown #277", unimplementedFunc), - /* 278 */ SyscallDesc("unknown #278", unimplementedFunc), - /* 279 */ SyscallDesc("unknown #279", unimplementedFunc), - /* 280 */ SyscallDesc("unknown #280", unimplementedFunc), - /* 281 */ SyscallDesc("unknown #281", unimplementedFunc), - /* 282 */ SyscallDesc("unknown #282", unimplementedFunc), - /* 283 */ SyscallDesc("unknown #283", unimplementedFunc), - /* 284 */ SyscallDesc("unknown #284", unimplementedFunc), - /* 285 */ SyscallDesc("unknown #285", unimplementedFunc), - /* 286 */ SyscallDesc("unknown #286", unimplementedFunc), - /* 287 */ SyscallDesc("unknown #287", unimplementedFunc), - /* 288 */ SyscallDesc("unknown #288", unimplementedFunc), - /* 289 */ SyscallDesc("unknown #289", unimplementedFunc), - /* 290 */ SyscallDesc("unknown #290", unimplementedFunc), - /* 291 */ SyscallDesc("unknown #291", unimplementedFunc), - /* 292 */ SyscallDesc("unknown #292", unimplementedFunc), - /* 293 */ SyscallDesc("unknown #293", unimplementedFunc), - /* 294 */ SyscallDesc("unknown #294", unimplementedFunc), - /* 295 */ SyscallDesc("unknown #295", unimplementedFunc), - /* 296 */ SyscallDesc("unknown #296", unimplementedFunc), - /* 297 */ SyscallDesc("unknown #297", unimplementedFunc), - /* 298 */ SyscallDesc("unknown #298", unimplementedFunc), - /* 299 */ SyscallDesc("unknown #299", unimplementedFunc), -/* - * Linux-specific system calls begin at 300 - */ - /* 300 */ SyscallDesc("bdflush", unimplementedFunc), - /* 301 */ SyscallDesc("sethae", unimplementedFunc), - /* 302 */ SyscallDesc("mount", unimplementedFunc), - /* 303 */ SyscallDesc("old_adjtimex", unimplementedFunc), - /* 304 */ SyscallDesc("swapoff", unimplementedFunc), - /* 305 */ SyscallDesc("getdents", unimplementedFunc), - /* 306 */ SyscallDesc("create_module", unimplementedFunc), - /* 307 */ SyscallDesc("init_module", unimplementedFunc), - /* 308 */ SyscallDesc("delete_module", unimplementedFunc), - /* 309 */ SyscallDesc("get_kernel_syms", unimplementedFunc), - /* 310 */ SyscallDesc("syslog", unimplementedFunc), - /* 311 */ SyscallDesc("reboot", unimplementedFunc), - /* 312 */ SyscallDesc("clone", cloneFunc), - /* 313 */ SyscallDesc("uselib", unimplementedFunc), - /* 314 */ SyscallDesc("mlock", unimplementedFunc), - /* 315 */ SyscallDesc("munlock", unimplementedFunc), - /* 316 */ SyscallDesc("mlockall", unimplementedFunc), - /* 317 */ SyscallDesc("munlockall", unimplementedFunc), - /* 318 */ SyscallDesc("sysinfo", sysinfoFunc), - /* 319 */ SyscallDesc("_sysctl", unimplementedFunc), - /* 320 */ SyscallDesc("was sys_idle", unimplementedFunc), - /* 321 */ SyscallDesc("oldumount", unimplementedFunc), - /* 322 */ SyscallDesc("swapon", unimplementedFunc), - /* 323 */ SyscallDesc("times", ignoreFunc), - /* 324 */ SyscallDesc("personality", unimplementedFunc), - /* 325 */ SyscallDesc("setfsuid", unimplementedFunc), - /* 326 */ SyscallDesc("setfsgid", unimplementedFunc), - /* 327 */ SyscallDesc("ustat", unimplementedFunc), - /* 328 */ SyscallDesc("statfs", unimplementedFunc), - /* 329 */ SyscallDesc("fstatfs", unimplementedFunc), - /* 330 */ SyscallDesc("sched_setparam", unimplementedFunc), - /* 331 */ SyscallDesc("sched_getparam", unimplementedFunc), - /* 332 */ SyscallDesc("sched_setscheduler", unimplementedFunc), - /* 333 */ SyscallDesc("sched_getscheduler", unimplementedFunc), - /* 334 */ SyscallDesc("sched_yield", unimplementedFunc), - /* 335 */ SyscallDesc("sched_get_priority_max", unimplementedFunc), - /* 336 */ SyscallDesc("sched_get_priority_min", unimplementedFunc), - /* 337 */ SyscallDesc("sched_rr_get_interval", unimplementedFunc), - /* 338 */ SyscallDesc("afs_syscall", unimplementedFunc), - /* 339 */ SyscallDesc("uname", unameFunc), - /* 340 */ SyscallDesc("nanosleep", unimplementedFunc), - /* 341 */ SyscallDesc("mremap", mremapFunc), - /* 342 */ SyscallDesc("nfsservctl", unimplementedFunc), - /* 343 */ SyscallDesc("setresuid", unimplementedFunc), - /* 344 */ SyscallDesc("getresuid", unimplementedFunc), - /* 345 */ SyscallDesc("pciconfig_read", unimplementedFunc), - /* 346 */ SyscallDesc("pciconfig_write", unimplementedFunc), - /* 347 */ SyscallDesc("query_module", unimplementedFunc), - /* 348 */ SyscallDesc("prctl", unimplementedFunc), - /* 349 */ SyscallDesc("pread", unimplementedFunc), - /* 350 */ SyscallDesc("pwrite", unimplementedFunc), - /* 351 */ SyscallDesc("rt_sigreturn", unimplementedFunc), - /* 352 */ SyscallDesc("rt_sigaction", ignoreFunc), - /* 353 */ SyscallDesc("rt_sigprocmask", unimplementedFunc), - /* 354 */ SyscallDesc("rt_sigpending", unimplementedFunc), - /* 355 */ SyscallDesc("rt_sigtimedwait", unimplementedFunc), - /* 356 */ SyscallDesc("rt_sigqueueinfo", unimplementedFunc), - /* 357 */ SyscallDesc("rt_sigsuspend", unimplementedFunc), - /* 358 */ SyscallDesc("select", unimplementedFunc), - /* 359 */ SyscallDesc("gettimeofday", gettimeofdayFunc), - /* 360 */ SyscallDesc("settimeofday", unimplementedFunc), - /* 361 */ SyscallDesc("getitimer", unimplementedFunc), - /* 362 */ SyscallDesc("setitimer", unimplementedFunc), - /* 363 */ SyscallDesc("utimes", utimesFunc), - /* 364 */ SyscallDesc("getrusage", getrusageFunc), - /* 365 */ SyscallDesc("wait4", unimplementedFunc), - /* 366 */ SyscallDesc("adjtimex", unimplementedFunc), - /* 367 */ SyscallDesc("getcwd", getcwdFunc), - /* 368 */ SyscallDesc("capget", unimplementedFunc), - /* 369 */ SyscallDesc("capset", unimplementedFunc), - /* 370 */ SyscallDesc("sendfile", unimplementedFunc), - /* 371 */ SyscallDesc("setresgid", unimplementedFunc), - /* 372 */ SyscallDesc("getresgid", unimplementedFunc), - /* 373 */ SyscallDesc("dipc", unimplementedFunc), - /* 374 */ SyscallDesc("pivot_root", unimplementedFunc), - /* 375 */ SyscallDesc("mincore", unimplementedFunc), - /* 376 */ SyscallDesc("pciconfig_iobase", unimplementedFunc), - /* 377 */ SyscallDesc("getdents64", unimplementedFunc), - /* 378 */ SyscallDesc("gettid", unimplementedFunc), - /* 379 */ SyscallDesc("readahead", unimplementedFunc), - /* 380 */ SyscallDesc("security", unimplementedFunc), - /* 381 */ SyscallDesc("tkill", unimplementedFunc), - /* 382 */ SyscallDesc("setxattr", unimplementedFunc), - /* 383 */ SyscallDesc("lsetxattr", unimplementedFunc), - /* 384 */ SyscallDesc("fsetxattr", unimplementedFunc), - /* 385 */ SyscallDesc("getxattr", unimplementedFunc), - /* 386 */ SyscallDesc("lgetxattr", unimplementedFunc), - /* 387 */ SyscallDesc("fgetxattr", unimplementedFunc), - /* 388 */ SyscallDesc("listxattr", unimplementedFunc), - /* 389 */ SyscallDesc("llistxattr", unimplementedFunc), - /* 390 */ SyscallDesc("flistxattr", unimplementedFunc), - /* 391 */ SyscallDesc("removexattr", unimplementedFunc), - /* 392 */ SyscallDesc("lremovexattr", unimplementedFunc), - /* 393 */ SyscallDesc("fremovexattr", unimplementedFunc), - /* 394 */ SyscallDesc("futex", unimplementedFunc), - /* 395 */ SyscallDesc("sched_setaffinity", unimplementedFunc), - /* 396 */ SyscallDesc("sched_getaffinity", unimplementedFunc), - /* 397 */ SyscallDesc("tuxcall", unimplementedFunc), - /* 398 */ SyscallDesc("io_setup", unimplementedFunc), - /* 399 */ SyscallDesc("io_destroy", unimplementedFunc), - /* 400 */ SyscallDesc("io_getevents", unimplementedFunc), - /* 401 */ SyscallDesc("io_submit", unimplementedFunc), - /* 402 */ SyscallDesc("io_cancel", unimplementedFunc), - /* 403 */ SyscallDesc("unknown #403", unimplementedFunc), - /* 404 */ SyscallDesc("unknown #404", unimplementedFunc), - /* 405 */ SyscallDesc("exit_group", exitGroupFunc), // exit all threads... - /* 406 */ SyscallDesc("lookup_dcookie", unimplementedFunc), - /* 407 */ SyscallDesc("sys_epoll_create", unimplementedFunc), - /* 408 */ SyscallDesc("sys_epoll_ctl", unimplementedFunc), - /* 409 */ SyscallDesc("sys_epoll_wait", unimplementedFunc), - /* 410 */ SyscallDesc("remap_file_pages", unimplementedFunc), - /* 411 */ SyscallDesc("set_tid_address", unimplementedFunc), - /* 412 */ SyscallDesc("restart_syscall", unimplementedFunc), - /* 413 */ SyscallDesc("fadvise64", unimplementedFunc), - /* 414 */ SyscallDesc("timer_create", unimplementedFunc), - /* 415 */ SyscallDesc("timer_settime", unimplementedFunc), - /* 416 */ SyscallDesc("timer_gettime", unimplementedFunc), - /* 417 */ SyscallDesc("timer_getoverrun", unimplementedFunc), - /* 418 */ SyscallDesc("timer_delete", unimplementedFunc), - /* 419 */ SyscallDesc("clock_settime", unimplementedFunc), - /* 420 */ SyscallDesc("clock_gettime", unimplementedFunc), - /* 421 */ SyscallDesc("clock_getres", unimplementedFunc), - /* 422 */ SyscallDesc("clock_nanosleep", unimplementedFunc), - /* 423 */ SyscallDesc("semtimedop", unimplementedFunc), - /* 424 */ SyscallDesc("tgkill", unimplementedFunc), - /* 425 */ SyscallDesc("stat64", stat64Func), - /* 426 */ SyscallDesc("lstat64", lstat64Func), - /* 427 */ SyscallDesc("fstat64", fstat64Func), - /* 428 */ SyscallDesc("vserver", unimplementedFunc), - /* 429 */ SyscallDesc("mbind", unimplementedFunc), - /* 430 */ SyscallDesc("get_mempolicy", unimplementedFunc), - /* 431 */ SyscallDesc("set_mempolicy", unimplementedFunc), - /* 432 */ SyscallDesc("mq_open", unimplementedFunc), - /* 433 */ SyscallDesc("mq_unlink", unimplementedFunc), - /* 434 */ SyscallDesc("mq_timedsend", unimplementedFunc), - /* 435 */ SyscallDesc("mq_timedreceive", unimplementedFunc), - /* 436 */ SyscallDesc("mq_notify", unimplementedFunc), - /* 437 */ SyscallDesc("mq_getsetattr", unimplementedFunc), - /* 438 */ SyscallDesc("waitid", unimplementedFunc), - /* 439 */ SyscallDesc("add_key", unimplementedFunc), - /* 440 */ SyscallDesc("request_key", unimplementedFunc), - /* 441 */ SyscallDesc("keyctl", unimplementedFunc) -}; - -AlphaLinuxProcess::AlphaLinuxProcess(LiveProcessParams * params, - ObjectFile *objFile) - : AlphaLiveProcess(params, objFile), - Num_Syscall_Descs(sizeof(syscallDescs) / sizeof(SyscallDesc)) -{ - //init_regs->intRegFile[0] = 0; -} - - - -SyscallDesc* -AlphaLinuxProcess::getDesc(int callnum) -{ - if (callnum < 0 || callnum >= Num_Syscall_Descs) - return NULL; - return &syscallDescs[callnum]; -} diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/linux/system.hh --- a/src/arch/alpha/linux/system.hh Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,150 +0,0 @@ -/* - * Copyright (c) 2004-2006 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Ali Saidi - * Lisa Hsu - * Nathan Binkert - */ - -#ifndef __ARCH_ALPHA_LINUX_SYSTEM_HH__ -#define __ARCH_ALPHA_LINUX_SYSTEM_HH__ - -class ThreadContext; - -class BreakPCEvent; -class IdleStartEvent; - -#include "arch/alpha/idle_event.hh" -#include "arch/alpha/system.hh" -#include "kern/linux/events.hh" -#include "params/LinuxAlphaSystem.hh" - -/** - * This class contains linux specific system code (Loading, Events). - * It points to objects that are the system binaries to load and patches them - * appropriately to work in simulator. - */ -class LinuxAlphaSystem : public AlphaSystem -{ - private: - struct SkipDelayLoopEvent : public SkipFuncEvent - { - SkipDelayLoopEvent(PCEventQueue *q, const std::string &desc, Addr addr) - : SkipFuncEvent(q, desc, addr) {} - virtual void process(ThreadContext *tc); - }; - - struct PrintThreadInfo : public PCEvent - { - PrintThreadInfo(PCEventQueue *q, const std::string &desc, Addr addr) - : PCEvent(q, desc, addr) {} - virtual void process(ThreadContext *tc); - }; - - /** - * Addresses defining where the kernel bootloader places various - * elements. Details found in include/asm-alpha/system.h - */ - Addr KernelStart; // Lookup the symbol swapper_pg_dir - - public: - Addr InitStack() const { return KernelStart + 0x02000; } - Addr EmptyPGT() const { return KernelStart + 0x04000; } - Addr EmptyPGE() const { return KernelStart + 0x08000; } - Addr ZeroPGE() const { return KernelStart + 0x0A000; } - Addr StartAddr() const { return KernelStart + 0x10000; } - - Addr Param() const { return ZeroPGE() + 0x0; } - Addr CommandLine() const { return Param() + 0x0; } - Addr InitrdStart() const { return Param() + 0x100; } - Addr InitrdSize() const { return Param() + 0x108; } - static const int CommandLineSize = 256; - - private: -#ifndef NDEBUG - /** Event to halt the simulator if the kernel calls panic() */ - BreakPCEvent *kernelPanicEvent; - -#if 0 - /** Event to halt the simulator if the kernel calls die_if_kernel */ - BreakPCEvent *kernelDieEvent; -#endif - -#endif - - /** - * Event to skip determine_cpu_caches() because we don't support - * the IPRs that the code can access to figure out cache sizes - */ - SkipFuncEvent *skipCacheProbeEvent; - - /** PC based event to skip the ide_delay_50ms() call */ - SkipFuncEvent *skipIdeDelay50msEvent; - - /** - * PC based event to skip the dprink() call and emulate its - * functionality - */ - Linux::DebugPrintkEvent *debugPrintkEvent; - - /** - * Skip calculate_delay_loop() rather than waiting for this to be - * calculated - */ - SkipDelayLoopEvent *skipDelayLoopEvent; - - /** - * Event to print information about thread switches if the trace flag - * Thread is set - */ - PrintThreadInfo *printThreadEvent; - - /** Grab the PCBB of the idle process when it starts */ - IdleStartEvent *idleStartEvent; - - protected: - /** Setup all the function events. Must be done after init() for Alpha since - * fixFuncEvent() requires a function port - */ - virtual void setupFuncEvents(); - - public: - typedef LinuxAlphaSystemParams Params; - LinuxAlphaSystem(Params *p); - ~LinuxAlphaSystem(); - - /** - * Initialise the system - */ - virtual void initState(); - - void setDelayLoop(ThreadContext *tc); - - const Params *params() const { return (const Params *)_params; } -}; - -#endif // __ARCH_ALPHA_LINUX_SYSTEM_HH__ diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/linux/system.cc --- a/src/arch/alpha/linux/system.cc Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,208 +0,0 @@ -/* - * Copyright (c) 2004-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Ali Saidi - * Lisa Hsu - * Nathan Binkert - * Steve Reinhardt - */ - -/** - * @file - * This code loads the linux kernel, console, pal and patches certain - * functions. The symbol tables are loaded so that traces can show - * the executing function and we can skip functions. Various delay - * loops are skipped and their final values manually computed to speed - * up boot time. - */ - -#include "arch/alpha/linux/system.hh" -#include "arch/alpha/idle_event.hh" -#include "arch/alpha/system.hh" -#include "arch/generic/linux/threadinfo.hh" -#include "arch/vtophys.hh" -#include "base/loader/symtab.hh" -#include "cpu/base.hh" -#include "cpu/thread_context.hh" -#include "debug/Thread.hh" -#include "kern/linux/events.hh" -#include "kern/linux/printk.hh" -#include "mem/physical.hh" -#include "mem/port.hh" -#include "sim/arguments.hh" -#include "sim/byteswap.hh" - -using namespace std; -using namespace AlphaISA; -using namespace Linux; - -LinuxAlphaSystem::LinuxAlphaSystem(Params *p) - : AlphaSystem(p) -{ -} - -void -LinuxAlphaSystem::initState() -{ - // Moved from the constructor to here since it relies on the - // address map being resolved in the interconnect - - // Call the initialisation of the super class - AlphaSystem::initState(); - - Addr addr = 0; - - /** - * The symbol swapper_pg_dir marks the beginning of the kernel and - * the location of bootloader passed arguments - */ - if (!kernelSymtab->findAddress("swapper_pg_dir", KernelStart)) { - panic("Could not determine start location of kernel"); - } - - /** - * Since we aren't using a bootloader, we have to copy the - * kernel arguments directly into the kernel's memory. - */ - virtProxy.writeBlob(CommandLine(), - (uint8_t*)params()->boot_osflags.c_str(), - params()->boot_osflags.length()+1); - - /** - * find the address of the est_cycle_freq variable and insert it - * so we don't through the lengthly process of trying to - * calculated it by using the PIT, RTC, etc. - */ - if (kernelSymtab->findAddress("est_cycle_freq", addr)) - virtProxy.write(addr, (uint64_t)(SimClock::Frequency / - params()->boot_cpu_frequency)); - - - /** - * EV5 only supports 127 ASNs so we are going to tell the kernel that the - * paritiuclar EV6 we have only supports 127 asns. - * @todo At some point we should change ev5.hh and the palcode to support - * 255 ASNs. - */ - if (kernelSymtab->findAddress("dp264_mv", addr)) - virtProxy.write(addr + 0x18, LittleEndianGuest::htog((uint32_t)127)); - else - panic("could not find dp264_mv\n"); - -} - -void -LinuxAlphaSystem::setupFuncEvents() -{ - AlphaSystem::setupFuncEvents(); -#ifndef NDEBUG - kernelPanicEvent = addKernelFuncEventOrPanic("panic"); - -#if 0 - kernelDieEvent = addKernelFuncEventOrPanic("die_if_kernel"); -#endif - -#endif - - /** - * Any time ide_delay_50ms, calibarte_delay or - * determine_cpu_caches is called just skip the - * function. Currently determine_cpu_caches only is used put - * information in proc, however if that changes in the future we - * will have to fill in the cache size variables appropriately. - */ - - skipIdeDelay50msEvent = - addKernelFuncEvent("ide_delay_50ms"); - skipDelayLoopEvent = - addKernelFuncEvent("calibrate_delay"); - skipCacheProbeEvent = - addKernelFuncEvent("determine_cpu_caches"); - debugPrintkEvent = addKernelFuncEvent("dprintk"); - idleStartEvent = addKernelFuncEvent("cpu_idle"); - - // Disable for now as it runs into panic() calls in VPTr methods - // (see sim/vptr.hh). Once those bugs are fixed, we can - // re-enable, but we should find a better way to turn it on than - // using DTRACE(Thread), since looking at a trace flag at tick 0 - // leads to non-intuitive behavior with --trace-start. - Addr addr = 0; - if (false && kernelSymtab->findAddress("alpha_switch_to", addr)) { - printThreadEvent = new PrintThreadInfo(&pcEventQueue, "threadinfo", - addr + sizeof(MachInst) * 6); - } else { - printThreadEvent = NULL; - } -} - -LinuxAlphaSystem::~LinuxAlphaSystem() -{ -#ifndef NDEBUG - delete kernelPanicEvent; -#endif - delete skipIdeDelay50msEvent; - delete skipDelayLoopEvent; - delete skipCacheProbeEvent; - delete debugPrintkEvent; - delete idleStartEvent; - delete printThreadEvent; -} - -void -LinuxAlphaSystem::setDelayLoop(ThreadContext *tc) -{ - Addr addr = 0; - if (kernelSymtab->findAddress("loops_per_jiffy", addr)) { - Tick cpuFreq = tc->getCpuPtr()->frequency(); - assert(intrFreq); - FSTranslatingPortProxy &vp = tc->getVirtProxy(); - vp.writeHtoG(addr, (uint32_t)((cpuFreq / intrFreq) * 0.9988)); - } -} - -void -LinuxAlphaSystem::SkipDelayLoopEvent::process(ThreadContext *tc) -{ - SkipFuncEvent::process(tc); - // calculate and set loops_per_jiffy - ((LinuxAlphaSystem *)tc->getSystemPtr())->setDelayLoop(tc); -} - -void -LinuxAlphaSystem::PrintThreadInfo::process(ThreadContext *tc) -{ - Linux::ThreadInfo ti(tc); - - DPRINTF(Thread, "Currently Executing Thread %s, pid %d, started at: %d\n", - ti.curTaskName(), ti.curTaskPID(), ti.curTaskStart()); -} - -LinuxAlphaSystem * -LinuxAlphaSystemParams::create() -{ - return new LinuxAlphaSystem(this); -} diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/locked_mem.hh --- a/src/arch/alpha/locked_mem.hh Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,140 +0,0 @@ -/* - * Copyright (c) 2012 ARM Limited - * All rights reserved - * - * The license below extends only to copyright in the software and shall - * not be construed as granting a license to any other intellectual - * property including but not limited to intellectual property relating - * to a hardware implementation of the functionality of the software - * licensed hereunder. You may use the software subject to the license - * terms below provided that you ensure that this notice is replicated - * unmodified and in its entirety in all distributions of the software, - * modified or unmodified, in source code or in binary form. - * - * Copyright (c) 2006 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Steve Reinhardt - */ - -#ifndef __ARCH_ALPHA_LOCKED_MEM_HH__ -#define __ARCH_ALPHA_LOCKED_MEM_HH__ - -/** - * @file - * - * ISA-specific helper functions for locked memory accesses. - * - * Note that these functions are not embedded in the ISA description - * because they operate on the *physical* address rather than the - * virtual address. In the current M5 design, the physical address is - * not accessible from the ISA description, only from the CPU model. - * Thus the CPU is responsible for calling back to the ISA (here) - * after the address translation has been performed to allow the ISA - * to do these manipulations based on the physical address. - */ - -#include "arch/alpha/registers.hh" -#include "base/misc.hh" -#include "mem/packet.hh" -#include "mem/request.hh" - -namespace AlphaISA { - -template -inline void -handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask) -{ - // If we see a snoop come into the CPU and we currently have an LLSC - // operation pending we need to clear the lock flag if it is to the same - // cache line. - - if (!xc->readMiscReg(MISCREG_LOCKFLAG)) - return; - - Addr locked_addr = xc->readMiscReg(MISCREG_LOCKADDR) & cacheBlockMask; - Addr snoop_addr = pkt->getAddr() & cacheBlockMask; - - if (locked_addr == snoop_addr) - xc->setMiscReg(MISCREG_LOCKFLAG, false); -} - - -template -inline void -handleLockedRead(XC *xc, Request *req) -{ - xc->setMiscReg(MISCREG_LOCKADDR, req->getPaddr() & ~0xf); - xc->setMiscReg(MISCREG_LOCKFLAG, true); -} - -template -inline void -handleLockedSnoopHit(XC *xc) -{ -} - -template -inline bool -handleLockedWrite(XC *xc, Request *req, Addr cacheBlockMask) -{ - if (req->isUncacheable()) { - // Funky Turbolaser mailbox access...don't update - // result register (see stq_c in decoder.isa) - req->setExtraData(2); - } else { - // standard store conditional - bool lock_flag = xc->readMiscReg(MISCREG_LOCKFLAG); - Addr lock_addr = xc->readMiscReg(MISCREG_LOCKADDR); - if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) { - // Lock flag not set or addr mismatch in CPU; - // don't even bother sending to memory system - req->setExtraData(0); - xc->setMiscReg(MISCREG_LOCKFLAG, false); - // the rest of this code is not architectural; - // it's just a debugging aid to help detect - // livelock by warning on long sequences of failed - // store conditionals - int stCondFailures = xc->readStCondFailures(); - stCondFailures++; - xc->setStCondFailures(stCondFailures); - if (stCondFailures % 100000 == 0) { - warn("context %d: %d consecutive " - "store conditional failures\n", - xc->contextId(), stCondFailures); - } - - // store conditional failed already, so don't issue it to mem - return false; - } - } - - return true; -} - -} // namespace AlphaISA - -#endif // __ARCH_ALPHA_LOCKED_MEM_HH__ diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/microcode_rom.hh --- a/src/arch/alpha/microcode_rom.hh Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,41 +0,0 @@ -/* - * Copyright (c) 2008 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - */ - -#ifndef __ARCH_ALPHA_MICROCODE_ROM_HH__ -#define __ARCH_ALPHA_MICROCODE_ROM_HH__ - -#include "sim/microcode_rom.hh" - -namespace AlphaISA -{ - using ::MicrocodeRom; -} - -#endif // __ARCH_ALPHA_MICROCODE_ROM_HH__ diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/mmapped_ipr.hh --- a/src/arch/alpha/mmapped_ipr.hh Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,47 +0,0 @@ -/* - * Copyright (c) 2006 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Ali Saidi - */ - -#ifndef __ARCH_ALPHA_MMAPPED_IPR_HH__ -#define __ARCH_ALPHA_MMAPPED_IPR_HH__ - -/** - * @file - * - * ISA-specific helper functions for memory mapped IPR accesses. - */ - -#include "arch/generic/mmapped_ipr.hh" - -namespace AlphaISA { - using GenericISA::handleIprRead; - using GenericISA::handleIprWrite; -} // namespace AlphaISA - -#endif // __ARCH_ALPHA_MMAPPED_IPR_HH__ diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/mt.hh --- a/src/arch/alpha/mt.hh Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,70 +0,0 @@ -/* - * Copyright (c) 2009 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Korey Sewell - * - */ - -#ifndef __ARCH_ALPHA_MT_HH__ -#define __ARCH_ALPHA_MT_HH__ - -/** - * @file - * - * ISA-specific helper functions for multithreaded execution. - */ - -#include - -#include "arch/isa_traits.hh" -#include "base/bitfield.hh" -#include "base/misc.hh" -#include "base/trace.hh" - -namespace AlphaISA -{ - -template -inline unsigned -getVirtProcNum(TC *tc) -{ - fatal("Alpha is not setup for multithreaded ISA extensions"); - return 0; -} - - -template -inline unsigned -getTargetThread(TC *tc) -{ - fatal("Alpha is not setup for multithreaded ISA extensions"); - return 0; -} - -} // namespace AlphaISA - -#endif diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/osfpal.hh --- a/src/arch/alpha/osfpal.hh Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,82 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Nathan Binkert - */ - -#ifndef __ARCH_ALPHA_OSFPAL_HH__ -#define __ARCH_ALPHA_OSFPAL_HH__ - -struct PAL -{ - enum { - // Privileged PAL functions - halt = 0x00, - cflush = 0x01, - draina = 0x02, - cserve = 0x09, - swppal = 0x0a, - wripir = 0x0d, - rdmces = 0x10, - wrmces = 0x11, - wrfen = 0x2b, - wrvptptr = 0x2d, - swpctx = 0x30, - wrval = 0x31, - rdval = 0x32, - tbi = 0x33, - wrent = 0x34, - swpipl = 0x35, - rdps = 0x36, - wrkgp = 0x37, - wrusp = 0x38, - wrperfmon = 0x39, - rdusp = 0x3a, - whami = 0x3c, - retsys = 0x3d, - wtint = 0x3e, - rti = 0x3f, - - // unprivileged pal functions - bpt = 0x80, - bugchk = 0x81, - callsys = 0x83, - imb = 0x86, - urti = 0x92, - rdunique = 0x9e, - wrunique = 0x9f, - gentrap = 0xaa, - clrfen = 0xae, - nphalt = 0xbe, - copypal = 0xbf, - NumCodes - }; - - static const char *name(int index); -}; - -#endif // __ARCH_ALPHA_OSFPAL_HH__ diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/osfpal.cc --- a/src/arch/alpha/osfpal.cc Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,304 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Nathan Binkert - */ - -#include "arch/alpha/osfpal.hh" - -const char * -PAL::name(int index) -{ - static const char *strings[PAL::NumCodes] = { - // Priviledged PAL instructions - "halt", // 0x00 - "cflush", // 0x01 - "draina", // 0x02 - 0, // 0x03 - 0, // 0x04 - 0, // 0x05 - 0, // 0x06 - 0, // 0x07 - 0, // 0x08 - "cserve", // 0x09 - "swppal", // 0x0a - 0, // 0x0b - 0, // 0x0c - "wripir", // 0x0d - 0, // 0x0e - 0, // 0x0f - "rdmces", // 0x10 - "wrmces", // 0x11 - 0, // 0x12 - 0, // 0x13 - 0, // 0x14 - 0, // 0x15 - 0, // 0x16 - 0, // 0x17 - 0, // 0x18 - 0, // 0x19 - 0, // 0x1a - 0, // 0x1b - 0, // 0x1c - 0, // 0x1d - 0, // 0x1e - 0, // 0x1f - 0, // 0x20 - 0, // 0x21 - 0, // 0x22 - 0, // 0x23 - 0, // 0x24 - 0, // 0x25 - 0, // 0x26 - 0, // 0x27 - 0, // 0x28 - 0, // 0x29 - 0, // 0x2a - "wrfen", // 0x2b - 0, // 0x2c - "wrvptptr", // 0x2d - 0, // 0x2e - 0, // 0x2f - "swpctx", // 0x30 - "wrval", // 0x31 - "rdval", // 0x32 - "tbi", // 0x33 - "wrent", // 0x34 - "swpipl", // 0x35 - "rdps", // 0x36 - "wrkgp", // 0x37 - "wrusp", // 0x38 - "wrperfmon", // 0x39 - "rdusp", // 0x3a - 0, // 0x3b - "whami", // 0x3c - "retsys", // 0x3d - "wtint", // 0x3e - "rti", // 0x3f - 0, // 0x40 - 0, // 0x41 - 0, // 0x42 - 0, // 0x43 - 0, // 0x44 - 0, // 0x45 - 0, // 0x46 - 0, // 0x47 - 0, // 0x48 - 0, // 0x49 - 0, // 0x4a - 0, // 0x4b - 0, // 0x4c - 0, // 0x4d - 0, // 0x4e - 0, // 0x4f - 0, // 0x50 - 0, // 0x51 - 0, // 0x52 - 0, // 0x53 - 0, // 0x54 - 0, // 0x55 - 0, // 0x56 - 0, // 0x57 - 0, // 0x58 - 0, // 0x59 - 0, // 0x5a - 0, // 0x5b - 0, // 0x5c - 0, // 0x5d - 0, // 0x5e - 0, // 0x5f - 0, // 0x60 - 0, // 0x61 - 0, // 0x62 - 0, // 0x63 - 0, // 0x64 - 0, // 0x65 - 0, // 0x66 - 0, // 0x67 - 0, // 0x68 - 0, // 0x69 - 0, // 0x6a - 0, // 0x6b - 0, // 0x6c - 0, // 0x6d - 0, // 0x6e - 0, // 0x6f - 0, // 0x70 - 0, // 0x71 - 0, // 0x72 - 0, // 0x73 - 0, // 0x74 - 0, // 0x75 - 0, // 0x76 - 0, // 0x77 - 0, // 0x78 - 0, // 0x79 - 0, // 0x7a - 0, // 0x7b - 0, // 0x7c - 0, // 0x7d - 0, // 0x7e - 0, // 0x7f - - // Unpriviledged PAL instructions - "bpt", // 0x80 - "bugchk", // 0x81 - 0, // 0x82 - "callsys", // 0x83 - 0, // 0x84 - 0, // 0x85 - "imb", // 0x86 - 0, // 0x87 - 0, // 0x88 - 0, // 0x89 - 0, // 0x8a - 0, // 0x8b - 0, // 0x8c - 0, // 0x8d - 0, // 0x8e - 0, // 0x8f - 0, // 0x90 - 0, // 0x91 - "urti", // 0x92 - 0, // 0x93 - 0, // 0x94 - 0, // 0x95 - 0, // 0x96 - 0, // 0x97 - 0, // 0x98 - 0, // 0x99 - 0, // 0x9a - 0, // 0x9b - 0, // 0x9c - 0, // 0x9d - "rdunique", // 0x9e - "wrunique", // 0x9f - 0, // 0xa0 - 0, // 0xa1 - 0, // 0xa2 - 0, // 0xa3 - 0, // 0xa4 - 0, // 0xa5 - 0, // 0xa6 - 0, // 0xa7 - 0, // 0xa8 - 0, // 0xa9 - "gentrap", // 0xaa - 0, // 0xab - 0, // 0xac - 0, // 0xad - "clrfen", // 0xae - 0, // 0xaf - 0, // 0xb0 - 0, // 0xb1 - 0, // 0xb2 - 0, // 0xb3 - 0, // 0xb4 - 0, // 0xb5 - 0, // 0xb6 - 0, // 0xb7 - 0, // 0xb8 - 0, // 0xb9 - 0, // 0xba - 0, // 0xbb - 0, // 0xbc - 0, // 0xbd - "nphalt", // 0xbe - "copypal", // 0xbf -#if 0 - 0, // 0xc0 - 0, // 0xc1 - 0, // 0xc2 - 0, // 0xc3 - 0, // 0xc4 - 0, // 0xc5 - 0, // 0xc6 - 0, // 0xc7 - 0, // 0xc8 - 0, // 0xc9 - 0, // 0xca - 0, // 0xcb - 0, // 0xcc - 0, // 0xcd - 0, // 0xce - 0, // 0xcf - 0, // 0xd0 - 0, // 0xd1 - 0, // 0xd2 - 0, // 0xd3 - 0, // 0xd4 - 0, // 0xd5 - 0, // 0xd6 - 0, // 0xd7 - 0, // 0xd8 - 0, // 0xd9 - 0, // 0xda - 0, // 0xdb - 0, // 0xdc - 0, // 0xdd - 0, // 0xde - 0, // 0xdf - 0, // 0xe0 - 0, // 0xe1 - 0, // 0xe2 - 0, // 0xe3 - 0, // 0xe4 - 0, // 0xe5 - 0, // 0xe6 - 0, // 0xe7 - 0, // 0xe8 - 0, // 0xe9 - 0, // 0xea - 0, // 0xeb - 0, // 0xec - 0, // 0xed - 0, // 0xee - 0, // 0xef - 0, // 0xf0 - 0, // 0xf1 - 0, // 0xf2 - 0, // 0xf3 - 0, // 0xf4 - 0, // 0xf5 - 0, // 0xf6 - 0, // 0xf7 - 0, // 0xf8 - 0, // 0xf9 - 0, // 0xfa - 0, // 0xfb - 0, // 0xfc - 0, // 0xfd - 0, // 0xfe - 0 // 0xff -#endif - }; - - if (index > NumCodes || index < 0) - return 0; - - return strings[index]; -} diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/pagetable.hh --- a/src/arch/alpha/pagetable.hh Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,152 +0,0 @@ -/* - * Copyright (c) 2002-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Nathan Binkert - * Steve Reinhardt - */ - -#ifndef __ARCH_ALPHA_PAGETABLE_H__ -#define __ARCH_ALPHA_PAGETABLE_H__ - -#include "arch/alpha/isa_traits.hh" -#include "arch/alpha/utility.hh" - -namespace AlphaISA { - -struct VAddr -{ - static const int ImplBits = 43; - static const Addr ImplMask = (ULL(1) << ImplBits) - 1; - static const Addr UnImplMask = ~ImplMask; - - Addr addr; - - VAddr(Addr a) : addr(a) {} - operator Addr() const { return addr; } - const VAddr &operator=(Addr a) { addr = a; return *this; } - - Addr vpn() const { return (addr & ImplMask) >> PageShift; } - Addr page() const { return addr & PageMask; } - Addr offset() const { return addr & PageOffset; } - - Addr level3() const - { return PteAddr(addr >> PageShift); } - Addr level2() const - { return PteAddr(addr >> (NPtePageShift + PageShift)); } - Addr level1() const - { return PteAddr(addr >> (2 * NPtePageShift + PageShift)); } -}; - -struct PageTableEntry -{ - PageTableEntry(uint64_t e) : entry(e) {} - uint64_t entry; - operator uint64_t() const { return entry; } - const PageTableEntry &operator=(uint64_t e) { entry = e; return *this; } - const PageTableEntry &operator=(const PageTableEntry &e) - { entry = e.entry; return *this; } - - Addr _pfn() const { return (entry >> 32) & 0xffffffff; } - Addr _sw() const { return (entry >> 16) & 0xffff; } - int _rsv0() const { return (entry >> 14) & 0x3; } - bool _uwe() const { return (entry >> 13) & 0x1; } - bool _kwe() const { return (entry >> 12) & 0x1; } - int _rsv1() const { return (entry >> 10) & 0x3; } - bool _ure() const { return (entry >> 9) & 0x1; } - bool _kre() const { return (entry >> 8) & 0x1; } - bool _nomb() const { return (entry >> 7) & 0x1; } - int _gh() const { return (entry >> 5) & 0x3; } - bool _asm_() const { return (entry >> 4) & 0x1; } - bool _foe() const { return (entry >> 3) & 0x1; } - bool _fow() const { return (entry >> 2) & 0x1; } - bool _for() const { return (entry >> 1) & 0x1; } - bool valid() const { return (entry >> 0) & 0x1; } - - Addr paddr() const { return _pfn() << PageShift; } -}; - -// ITB/DTB table entry -struct TlbEntry : public Serializable -{ - Addr tag; // virtual page number tag - Addr ppn; // physical page number - uint8_t xre; // read permissions - VMEM_PERM_* mask - uint8_t xwe; // write permissions - VMEM_PERM_* mask - uint8_t asn; // address space number - bool asma; // address space match - bool fonr; // fault on read - bool fonw; // fault on write - bool valid; // valid page table entry - - - //Construct an entry that maps to physical address addr. - TlbEntry(Addr _asn, Addr _vaddr, Addr _paddr, - bool uncacheable, bool read_only) - { - VAddr vaddr(_vaddr); - VAddr paddr(_paddr); - tag = vaddr.vpn(); - ppn = paddr.vpn(); - xre = 15; - xwe = 15; - asn = _asn; - asma = false; - fonr = false; - fonw = false; - valid = true; - if (uncacheable || read_only) - warn("Alpha TlbEntry does not support uncacheable" - " or read-only mappings\n"); - } - - TlbEntry() - : tag(0), ppn(0), xre(0), xwe(0), asn(0), - asma(false), fonr(0), fonw(0), valid(0) - { - } - - void - updateVaddr(Addr new_vaddr) - { - VAddr vaddr(new_vaddr); - tag = vaddr.vpn(); - } - - Addr - pageStart() - { - return ppn << PageShift; - } - - void serialize(CheckpointOut &cp) const override; - void unserialize(CheckpointIn &cp) override; -}; - -} // namespace AlphaISA - -#endif // __ARCH_ALPHA_PAGETABLE_H__ - diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/pagetable.cc --- a/src/arch/alpha/pagetable.cc Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,64 +0,0 @@ -/* - * Copyright (c) 2006-2007 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - */ - -#include "arch/alpha/pagetable.hh" -#include "sim/serialize.hh" - -namespace AlphaISA { - -void -TlbEntry::serialize(CheckpointOut &cp) const -{ - SERIALIZE_SCALAR(tag); - SERIALIZE_SCALAR(ppn); - SERIALIZE_SCALAR(xre); - SERIALIZE_SCALAR(xwe); - SERIALIZE_SCALAR(asn); - SERIALIZE_SCALAR(asma); - SERIALIZE_SCALAR(fonr); - SERIALIZE_SCALAR(fonw); - SERIALIZE_SCALAR(valid); -} - -void -TlbEntry::unserialize(CheckpointIn &cp) -{ - UNSERIALIZE_SCALAR(tag); - UNSERIALIZE_SCALAR(ppn); - UNSERIALIZE_SCALAR(xre); - UNSERIALIZE_SCALAR(xwe); - UNSERIALIZE_SCALAR(asn); - UNSERIALIZE_SCALAR(asma); - UNSERIALIZE_SCALAR(fonr); - UNSERIALIZE_SCALAR(fonw); - UNSERIALIZE_SCALAR(valid); -} - -} // namespace AlphaISA diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/process.hh --- a/src/arch/alpha/process.hh Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,66 +0,0 @@ -/* - * Copyright (c) 2003-2004 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - * Ali Saidi - */ - -#ifndef __ARCH_ALPHA_PROCESS_HH__ -#define __ARCH_ALPHA_PROCESS_HH__ - -#include "sim/process.hh" - -class AlphaLiveProcess : public LiveProcess -{ - private: - void setupASNReg(); - - protected: - AlphaLiveProcess(LiveProcessParams *params, ObjectFile *objFile); - - void loadState(CheckpointIn &cp) override; - void initState() override; - - void argsInit(int intSize, int pageSize); - - public: - AlphaISA::IntReg getSyscallArg(ThreadContext *tc, int &i) override; - /// Explicitly import the otherwise hidden getSyscallArg - using LiveProcess::getSyscallArg; - void setSyscallArg(ThreadContext *tc, int i, AlphaISA::IntReg val) override; - void setSyscallReturn(ThreadContext *tc, - SyscallReturn return_value) override; - - // override default implementation in LiveProcess as the mmap - // region for Alpha platforms grows upward - virtual bool mmapGrowsDown() const override { return false; } -}; - -/* No architectural page table defined for this ISA */ -typedef NoArchPageTable ArchPageTable; - -#endif // __ARCH_ALPHA_PROCESS_HH__ diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/process.cc --- a/src/arch/alpha/process.cc Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,244 +0,0 @@ -/* - * Copyright (c) 2003-2004 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - * Ali Saidi - */ - -#include "arch/alpha/isa_traits.hh" -#include "arch/alpha/process.hh" -#include "base/loader/elf_object.hh" -#include "base/loader/object_file.hh" -#include "base/misc.hh" -#include "cpu/thread_context.hh" -#include "debug/Loader.hh" -#include "mem/page_table.hh" -#include "sim/byteswap.hh" -#include "sim/process_impl.hh" -#include "sim/system.hh" - -using namespace AlphaISA; -using namespace std; - -AlphaLiveProcess::AlphaLiveProcess(LiveProcessParams *params, - ObjectFile *objFile) - : LiveProcess(params, objFile) -{ - brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize(); - brk_point = roundUp(brk_point, PageBytes); - - // Set up stack. On Alpha, stack goes below text section. This - // code should get moved to some architecture-specific spot. - stack_base = objFile->textBase() - (409600+4096); - - // Set up region for mmaps. Tru64 seems to start just above 0 and - // grow up from there. - mmap_end = 0x10000; - - // Set pointer for next thread stack. Reserve 8M for main stack. - next_thread_stack_base = stack_base - (8 * 1024 * 1024); - -} - -void -AlphaLiveProcess::argsInit(int intSize, int pageSize) -{ - // Patch the ld_bias for dynamic executables. - updateBias(); - - objFile->loadSections(initVirtMem); - - typedef AuxVector auxv_t; - std::vector auxv; - - ElfObject * elfObject = dynamic_cast(objFile); - if (elfObject) - { - // modern glibc uses a bunch of auxiliary vectors to set up - // TLS as well as do a bunch of other stuff - // these vectors go on the bottom of the stack, below argc/argv/envp - // pointers but above actual arg strings - // I don't have all the ones glibc looks at here, but so far it doesn't - // seem to be a problem. - // check out _dl_aux_init() in glibc/elf/dl-support.c for details - // --Lisa - auxv.push_back(auxv_t(M5_AT_PAGESZ, AlphaISA::PageBytes)); - auxv.push_back(auxv_t(M5_AT_CLKTCK, 100)); - auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable())); - DPRINTF(Loader, "auxv at PHDR %08p\n", elfObject->programHeaderTable()); - auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount())); - // This is the base address of the ELF interpreter; it should be - // zero for static executables or contain the base address for - // dynamic executables. - auxv.push_back(auxv_t(M5_AT_BASE, getBias())); - auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint())); - auxv.push_back(auxv_t(M5_AT_UID, uid())); - auxv.push_back(auxv_t(M5_AT_EUID, euid())); - auxv.push_back(auxv_t(M5_AT_GID, gid())); - auxv.push_back(auxv_t(M5_AT_EGID, egid())); - - } - - // Calculate how much space we need for arg & env & auxv arrays. - int argv_array_size = intSize * (argv.size() + 1); - int envp_array_size = intSize * (envp.size() + 1); - int auxv_array_size = intSize * 2 * (auxv.size() + 1); - - int arg_data_size = 0; - for (vector::size_type i = 0; i < argv.size(); ++i) { - arg_data_size += argv[i].size() + 1; - } - int env_data_size = 0; - for (vector::size_type i = 0; i < envp.size(); ++i) { - env_data_size += envp[i].size() + 1; - } - - int space_needed = - argv_array_size + - envp_array_size + - auxv_array_size + - arg_data_size + - env_data_size; - - if (space_needed < 32*1024) - space_needed = 32*1024; - - // set bottom of stack - stack_min = stack_base - space_needed; - // align it - stack_min = roundDown(stack_min, pageSize); - stack_size = stack_base - stack_min; - // map memory - allocateMem(stack_min, roundUp(stack_size, pageSize)); - - // map out initial stack contents - Addr argv_array_base = stack_min + intSize; // room for argc - Addr envp_array_base = argv_array_base + argv_array_size; - Addr auxv_array_base = envp_array_base + envp_array_size; - Addr arg_data_base = auxv_array_base + auxv_array_size; - Addr env_data_base = arg_data_base + arg_data_size; - - // write contents to stack - uint64_t argc = argv.size(); - if (intSize == 8) - argc = htog((uint64_t)argc); - else if (intSize == 4) - argc = htog((uint32_t)argc); - else - panic("Unknown int size"); - - initVirtMem.writeBlob(stack_min, (uint8_t*)&argc, intSize); - - copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem); - copyStringArray(envp, envp_array_base, env_data_base, initVirtMem); - - //Copy the aux stuff - for (vector::size_type x = 0; x < auxv.size(); x++) { - initVirtMem.writeBlob(auxv_array_base + x * 2 * intSize, - (uint8_t*)&(auxv[x].a_type), intSize); - initVirtMem.writeBlob(auxv_array_base + (x * 2 + 1) * intSize, - (uint8_t*)&(auxv[x].a_val), intSize); - } - - ThreadContext *tc = system->getThreadContext(contextIds[0]); - - setSyscallArg(tc, 0, argc); - setSyscallArg(tc, 1, argv_array_base); - tc->setIntReg(StackPointerReg, stack_min); - - tc->pcState(getStartPC()); -} - -void -AlphaLiveProcess::setupASNReg() -{ - ThreadContext *tc = system->getThreadContext(contextIds[0]); - tc->setMiscRegNoEffect(IPR_DTB_ASN, M5_pid << 57); -} - - -void -AlphaLiveProcess::loadState(CheckpointIn &cp) -{ - LiveProcess::loadState(cp); - // need to set up ASN after unserialization since M5_pid value may - // come from checkpoint - setupASNReg(); -} - - -void -AlphaLiveProcess::initState() -{ - // need to set up ASN before further initialization since init - // will involve writing to virtual memory addresses - setupASNReg(); - - LiveProcess::initState(); - - argsInit(MachineBytes, PageBytes); - - ThreadContext *tc = system->getThreadContext(contextIds[0]); - tc->setIntReg(GlobalPointerReg, objFile->globalPointer()); - //Operate in user mode - tc->setMiscRegNoEffect(IPR_ICM, mode_user << 3); - tc->setMiscRegNoEffect(IPR_DTB_CM, mode_user << 3); - //No super page mapping - tc->setMiscRegNoEffect(IPR_MCSR, 0); -} - -AlphaISA::IntReg -AlphaLiveProcess::getSyscallArg(ThreadContext *tc, int &i) -{ - assert(i < 6); - return tc->readIntReg(FirstArgumentReg + i++); -} - -void -AlphaLiveProcess::setSyscallArg(ThreadContext *tc, - int i, AlphaISA::IntReg val) -{ - assert(i < 6); - tc->setIntReg(FirstArgumentReg + i, val); -} - -void -AlphaLiveProcess::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret) -{ - // check for error condition. Alpha syscall convention is to - // indicate success/failure in reg a3 (r19) and put the - // return value itself in the standard return value reg (v0). - if (sysret.successful()) { - // no error - tc->setIntReg(SyscallSuccessReg, 0); - tc->setIntReg(ReturnValueReg, sysret.returnValue()); - } else { - // got an error, return details - tc->setIntReg(SyscallSuccessReg, (IntReg)-1); - tc->setIntReg(ReturnValueReg, sysret.errnoValue()); - } -} diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/pseudo_inst.hh --- a/src/arch/alpha/pseudo_inst.hh Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,45 +0,0 @@ -/* - * Copyright (c) 2014 Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Alexandru Dutu - */ - -#ifndef __ARCH_ALPHA_PSEUDO_INST_HH__ -#define __ARCH_ALPHA_PSEUDO_INST_HH__ - -#include "arch/generic/pseudo_inst.hh" -#include "base/misc.hh" - -class ThreadContext; - -namespace AlphaISA { - using GenericISA::m5Syscall; - using GenericISA::m5PageFault; -} - -#endif // __ARCH_ALPHA_PSEUDO_INST_HH__ - diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/registers.hh --- a/src/arch/alpha/registers.hh Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,115 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - */ - -#ifndef __ARCH_ALPHA_REGISTERS_HH__ -#define __ARCH_ALPHA_REGISTERS_HH__ - -#include "arch/alpha/generated/max_inst_regs.hh" -#include "arch/alpha/ipr.hh" -#include "base/types.hh" - -namespace AlphaISA { - -using AlphaISAInst::MaxInstSrcRegs; -using AlphaISAInst::MaxInstDestRegs; - -// Locked read/write flags are can't be detected by the ISA parser -const int MaxMiscDestRegs = AlphaISAInst::MaxMiscDestRegs + 1; - -typedef uint8_t RegIndex; -typedef uint64_t IntReg; - -// floating point register file entry type -typedef double FloatReg; -typedef uint64_t FloatRegBits; - -// control register file contents -typedef uint64_t MiscReg; - -// dummy typedef since we don't have CC regs -typedef uint8_t CCReg; - -union AnyReg -{ - IntReg intreg; - FloatReg fpreg; - MiscReg ctrlreg; -}; - -enum MiscRegIndex -{ - MISCREG_FPCR = NumInternalProcRegs, - MISCREG_UNIQ, - MISCREG_LOCKFLAG, - MISCREG_LOCKADDR, - MISCREG_INTR, - NUM_MISCREGS -}; - -// semantically meaningful register indices -const RegIndex ZeroReg = 31; // architecturally meaningful -// the rest of these depend on the ABI -const RegIndex StackPointerReg = 30; -const RegIndex GlobalPointerReg = 29; -const RegIndex ProcedureValueReg = 27; -const RegIndex ReturnAddressReg = 26; -const RegIndex ReturnValueReg = 0; -const RegIndex FramePointerReg = 15; - -const RegIndex SyscallNumReg = 0; -const RegIndex FirstArgumentReg = 16; -const RegIndex SyscallPseudoReturnReg = 20; -const RegIndex SyscallSuccessReg = 19; - -const int NumIntArchRegs = 32; -const int NumPALShadowRegs = 8; -const int NumFloatArchRegs = 32; - -const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs; -const int NumFloatRegs = NumFloatArchRegs; -const int NumCCRegs = 0; -const int NumMiscRegs = NUM_MISCREGS; - -const int TotalNumRegs = - NumIntRegs + NumFloatRegs + NumMiscRegs; - -// These enumerate all the registers for dependence tracking. -enum DependenceTags { - // 0..31 are the integer regs 0..31 - // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Reg_Base) - FP_Reg_Base = NumIntRegs, - CC_Reg_Base = FP_Reg_Base + NumFloatRegs, - Misc_Reg_Base = CC_Reg_Base + NumCCRegs, // NumCCRegs == 0 - Max_Reg_Index = Misc_Reg_Base + NumMiscRegs + NumInternalProcRegs -}; - -} // namespace AlphaISA - -#endif // __ARCH_ALPHA_REGFILE_HH__ diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/regredir.hh --- a/src/arch/alpha/regredir.hh Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,43 +0,0 @@ -/* - * Copyright (c) 2003-2009 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - */ - -#ifndef __ARCH_ALPHA_REGREDIR_HH__ -#define __ARCH_ALPHA_REGREDIR_HH__ - -#include "arch/alpha/registers.hh" - -namespace AlphaISA { - -// redirected register map, really only used for the full system case. -extern const int reg_redir[NumIntRegs]; - -} // namespace AlphaISA - -#endif // __ARCH_ALPHA_REGREDIR_HH__ diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/regredir.cc --- a/src/arch/alpha/regredir.cc Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,43 +0,0 @@ -/* - * Copyright (c) 2003-2009 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Steve Reinhardt - * Gabe Black - * Kevin Lim - */ - -#include "arch/alpha/regredir.hh" - -namespace AlphaISA { - -const int reg_redir[NumIntRegs] = { - /* 0 */ 0, 1, 2, 3, 4, 5, 6, 7, - /* 8 */ 32, 33, 34, 35, 36, 37, 38, 15, - /* 16 */ 16, 17, 18, 19, 20, 21, 22, 23, - /* 24 */ 24, 39, 26, 27, 28, 29, 30, 31 }; - -} // namespace AlphaISA diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/remote_gdb.hh --- a/src/arch/alpha/remote_gdb.hh Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,83 +0,0 @@ -/* - * Copyright (c) 2015 LabWare - * Copyright (c) 2002-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Nathan Binkert - * Boris Shingarov - */ - -#ifndef __ARCH_ALPHA_REMOTE_GDB_HH__ -#define __ARCH_ALPHA_REMOTE_GDB_HH__ - -#include - -#include "arch/alpha/types.hh" -#include "base/pollevent.hh" -#include "base/remote_gdb.hh" -#include "base/socket.hh" -#include "cpu/pc_event.hh" - -class System; -class ThreadContext; - -namespace AlphaISA { - -class RemoteGDB : public BaseRemoteGDB -{ - protected: - // Machine memory - bool acc(Addr addr, size_t len); - bool write(Addr addr, size_t size, const char *data); - - bool insertHardBreak(Addr addr, size_t len); - - class AlphaGdbRegCache : public BaseGdbRegCache - { - using BaseGdbRegCache::BaseGdbRegCache; - private: - struct { - uint64_t gpr[32]; - uint64_t fpr[32]; - uint64_t pc; - uint64_t vfp; - } r; - public: - char *data() const { return (char *)&r; } - size_t size() const { return sizeof(r); } - void getRegs(ThreadContext*); - void setRegs(ThreadContext*) const; - const std::string name() const { return gdb->name() + ".AlphaGdbRegCache"; } - }; - - public: - RemoteGDB(System *system, ThreadContext *context); - BaseGdbRegCache *gdbRegs(); -}; - -} // namespace AlphaISA - -#endif // __ARCH_ALPHA_REMOTE_GDB_HH__ diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/remote_gdb.cc --- a/src/arch/alpha/remote_gdb.cc Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,277 +0,0 @@ -/* - * Copyright 2014 Google, Inc. - * Copyright (c) 2002-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Nathan Binkert - */ - -/* - * Copyright (c) 1990, 1993 The Regents of the University of California - * All rights reserved. - * - * This software was developed by the Computer Systems Engineering group - * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and - * contributed to Berkeley. - * - * All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by the University of - * California, Lawrence Berkeley Laboratories. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by the University of - * California, Berkeley and its contributors. - * 4. Neither the name of the University nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * @(#)kgdb_stub.c 8.4 (Berkeley) 1/12/94 - */ - -/*- - * Copyright (c) 2001 The NetBSD Foundation, Inc. - * All rights reserved. - * - * This code is derived from software contributed to The NetBSD Foundation - * by Jason R. Thorpe. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by the NetBSD - * Foundation, Inc. and its contributors. - * 4. Neither the name of The NetBSD Foundation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * $NetBSD: kgdb_stub.c,v 1.8 2001/07/07 22:58:00 wdk Exp $ - * - * Taken from NetBSD - * - * "Stub" to allow remote cpu to debug over a serial line using gdb. - */ - -#include -#include - -#include - - -#include "arch/alpha/decoder.hh" -#include "arch/alpha/regredir.hh" -#include "arch/alpha/remote_gdb.hh" -#include "arch/alpha/utility.hh" -#include "arch/alpha/vtophys.hh" -#include "base/intmath.hh" -#include "base/remote_gdb.hh" -#include "base/socket.hh" -#include "base/trace.hh" -#include "cpu/static_inst.hh" -#include "cpu/thread_context.hh" -#include "debug/GDBAcc.hh" -#include "debug/GDBMisc.hh" -#include "mem/physical.hh" -#include "mem/port.hh" -#include "sim/system.hh" -#include "sim/full_system.hh" - -using namespace std; -using namespace AlphaISA; - -RemoteGDB::RemoteGDB(System *_system, ThreadContext *tc) - : BaseRemoteGDB(_system, tc) -{ -} - -/* - * Determine if the mapping at va..(va+len) is valid. - */ -bool -RemoteGDB::acc(Addr va, size_t len) -{ - if (!FullSystem) - panic("acc function needs to be rewritten for SE mode\n"); - - Addr last_va; - - va = TruncPage(va); - last_va = RoundPage(va + len); - - do { - if (IsK0Seg(va)) { - if (va < (K0SegBase + system->memSize())) { - DPRINTF(GDBAcc, "acc: Mapping is valid K0SEG <= " - "%#x < K0SEG + size\n", va); - return true; - } else { - DPRINTF(GDBAcc, "acc: Mapping invalid %#x " - "> K0SEG + size\n", va); - return false; - } - } - - /** - * This code says that all accesses to palcode (instruction - * and data) are valid since there isn't a va->pa mapping - * because palcode is accessed physically. At some point this - * should probably be cleaned up but there is no easy way to - * do it. - */ - - if (PcPAL(va) || va < 0x10000) - return true; - - Addr ptbr = context->readMiscRegNoEffect(IPR_PALtemp20); - PageTableEntry pte = - kernel_pte_lookup(context->getPhysProxy(), ptbr, va); - if (!pte.valid()) { - DPRINTF(GDBAcc, "acc: %#x pte is invalid\n", va); - return false; - } - va += PageBytes; - } while (va < last_va); - - DPRINTF(GDBAcc, "acc: %#x mapping is valid\n", va); - return true; -} - -void -RemoteGDB::AlphaGdbRegCache::getRegs(ThreadContext *context) -{ - DPRINTF(GDBAcc, "getRegs in remotegdb \n"); - - r.pc = context->pcState().pc(); - - if (PcPAL(r.pc)) { - for (int i = 0; i < 32; ++i) - r.gpr[i] = context->readIntReg(reg_redir[i]); - } else { - for (int i = 0; i < 32; ++i) - r.gpr[i] = context->readIntReg(i); - } - - for (int i = 0; i < 32; ++i) -#ifdef KGDB_FP_REGS - r.fpr[i] = context->readFloatRegBits(i); -#else - r.fpr[i] = 0; -#endif -} - -void -RemoteGDB::AlphaGdbRegCache::setRegs(ThreadContext *context) const -{ - DPRINTF(GDBAcc, "setRegs in remotegdb \n"); - - if (PcPAL(r.pc)) { - for (int i = 0; i < 32; ++i) { - context->setIntReg(reg_redir[i], r.gpr[i]); - } - } else { - for (int i = 0; i < 32; ++i) { - context->setIntReg(i, r.gpr[i]); - } - } - -#ifdef KGDB_FP_REGS - for (int i = 0; i < NumFloatArchRegs; ++i) { - context->setFloatRegBits(i, gdbregs.regs64[i + KGDB_REG_F0]); - } -#endif - context->pcState(r.pc); -} - -// Write bytes to kernel address space for debugger. -bool -RemoteGDB::write(Addr vaddr, size_t size, const char *data) -{ - if (BaseRemoteGDB::write(vaddr, size, data)) { -#ifdef IMB - alpha_pal_imb(); -#endif - return true; - } else { - return false; - } -} - - -bool -RemoteGDB::insertHardBreak(Addr addr, size_t len) -{ - warn_once("Breakpoints do not work in Alpha PAL mode.\n" - " See PCEventQueue::doService() in cpu/pc_event.cc.\n"); - return BaseRemoteGDB::insertHardBreak(addr, len); -} - -RemoteGDB::BaseGdbRegCache* -RemoteGDB::gdbRegs() { - return new AlphaGdbRegCache(this); -} - diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/stacktrace.hh --- a/src/arch/alpha/stacktrace.hh Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,128 +0,0 @@ -/* - * Copyright (c) 2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Nathan Binkert - */ - -#ifndef __ARCH_ALPHA_STACKTRACE_HH__ -#define __ARCH_ALPHA_STACKTRACE_HH__ - -#include "base/trace.hh" -#include "cpu/static_inst.hh" -#include "debug/Stack.hh" - -class ThreadContext; - -namespace AlphaISA { - -class StackTrace; - -class ProcessInfo -{ - private: - ThreadContext *tc; - - int thread_info_size; - int task_struct_size; - int task_off; - int pid_off; - int name_off; - - public: - ProcessInfo(ThreadContext *_tc); - - Addr task(Addr ksp) const; - int pid(Addr ksp) const; - std::string name(Addr ksp) const; -}; - -class StackTrace -{ - private: - ThreadContext *tc; - std::vector stack; - - private: - bool isEntry(Addr addr); - bool decodePrologue(Addr sp, Addr callpc, Addr func, int &size, Addr &ra); - bool decodeSave(MachInst inst, int ®, int &disp); - bool decodeStack(MachInst inst, int &disp); - - void trace(ThreadContext *tc, bool is_call); - - public: - StackTrace(); - StackTrace(ThreadContext *tc, const StaticInstPtr &inst); - ~StackTrace(); - - void - clear() - { - tc = 0; - stack.clear(); - } - - bool valid() const { return tc != NULL; } - bool trace(ThreadContext *tc, const StaticInstPtr &inst); - - public: - const std::vector &getstack() const { return stack; } - - enum { - user = 1, - console = 2, - unknown = 3 - }; - -#if TRACING_ON - private: - void dump(); - - public: - void dprintf() { if (DTRACE(Stack)) dump(); } -#else - public: - void dprintf() {} -#endif -}; - -inline bool -StackTrace::trace(ThreadContext *tc, const StaticInstPtr &inst) -{ - if (!inst->isCall() && !inst->isReturn()) - return false; - - if (valid()) - clear(); - - trace(tc, !inst->isReturn()); - return true; -} - -} // namespace AlphaISA - -#endif // __ARCH_ALPHA_STACKTRACE_HH__ diff -r 9c673b990d5d -r e1835e5846b9 build_opts/ALPHA_MOESI_CMP_token --- a/build_opts/ALPHA_MOESI_CMP_token Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,3 +0,0 @@ -SS_COMPATIBLE_FP = 1 -CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,MinorCPU' -PROTOCOL = 'MOESI_CMP_token' diff -r 9c673b990d5d -r e1835e5846b9 build_opts/ALPHA_MOESI_hammer --- a/build_opts/ALPHA_MOESI_hammer Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,3 +0,0 @@ -SS_COMPATIBLE_FP = 1 -CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,MinorCPU' -PROTOCOL = 'MOESI_hammer' diff -r 9c673b990d5d -r e1835e5846b9 build_opts/Garnet_standalone --- a/build_opts/Garnet_standalone Mon Oct 24 21:38:48 2016 +0100 +++ b/build_opts/Garnet_standalone Mon Oct 24 21:40:04 2016 +0100 @@ -1,4 +1,3 @@ TARGET_ISA = 'alpha' -SS_COMPATIBLE_FP = 1 CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,MinorCPU' PROTOCOL = 'Garnet_standalone' diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/AlphaISA.py --- a/src/arch/alpha/AlphaISA.py Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,47 +0,0 @@ -# Copyright (c) 2012 ARM Limited -# All rights reserved. -# -# The license below extends only to copyright in the software and shall -# not be construed as granting a license to any other intellectual -# property including but not limited to intellectual property relating -# to a hardware implementation of the functionality of the software -# licensed hereunder. You may use the software subject to the license -# terms below provided that you ensure that this notice is replicated -# unmodified and in its entirety in all distributions of the software, -# modified or unmodified, in source code or in binary form. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer; -# redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution; -# neither the name of the copyright holders nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Authors: Andreas Sandberg - -from m5.params import * -from m5.proxy import * -from m5.SimObject import SimObject - -class AlphaISA(SimObject): - type = 'AlphaISA' - cxx_class = 'AlphaISA::ISA' - cxx_header = "arch/alpha/isa.hh" - - system = Param.System(Parent.any, "System this ISA object belongs to") diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/AlphaInterrupts.py --- a/src/arch/alpha/AlphaInterrupts.py Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,34 +0,0 @@ -# Copyright (c) 2008 The Regents of The University of Michigan -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer; -# redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution; -# neither the name of the copyright holders nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Authors: Gabe Black - -from m5.SimObject import SimObject - -class AlphaInterrupts(SimObject): - type = 'AlphaInterrupts' - cxx_class = 'AlphaISA::Interrupts' - cxx_header = "arch/alpha/interrupts.hh" diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/AlphaSystem.py --- a/src/arch/alpha/AlphaSystem.py Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,62 +0,0 @@ -# Copyright (c) 2007 The Regents of The University of Michigan -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer; -# redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution; -# neither the name of the copyright holders nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Authors: Nathan Binkert - -from m5.params import * -from m5.proxy import * -from System import System - -class AlphaSystem(System): - type = 'AlphaSystem' - cxx_header = "arch/alpha/system.hh" - console = Param.String("file that contains the console code") - pal = Param.String("file that contains palcode") - system_type = Param.UInt64("Type of system we are emulating") - system_rev = Param.UInt64("Revision of system we are emulating") - load_addr_mask = 0xffffffffff - -class LinuxAlphaSystem(AlphaSystem): - type = 'LinuxAlphaSystem' - cxx_header = "arch/alpha/linux/system.hh" - system_type = 34 - system_rev = 1 << 10 - - boot_cpu_frequency = Param.Frequency(Self.cpu[0].clk_domain.clock[0] - .frequency, - "boot processor frequency") - -class FreebsdAlphaSystem(AlphaSystem): - type = 'FreebsdAlphaSystem' - cxx_header = "arch/alpha/freebsd/system.hh" - system_type = 34 - system_rev = 1 << 10 - -class Tru64AlphaSystem(AlphaSystem): - type = 'Tru64AlphaSystem' - cxx_header = "arch/alpha/tru64/system.hh" - system_type = 12 - system_rev = 2<<1 diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/AlphaTLB.py --- a/src/arch/alpha/AlphaTLB.py Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,44 +0,0 @@ -# Copyright (c) 2005-2007 The Regents of The University of Michigan -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer; -# redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution; -# neither the name of the copyright holders nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Authors: Nathan Binkert - -from m5.SimObject import SimObject -from m5.params import * - -from BaseTLB import BaseTLB - -class AlphaTLB(BaseTLB): - type = 'AlphaTLB' - cxx_class = 'AlphaISA::TLB' - cxx_header = "arch/alpha/tlb.hh" - size = Param.Int("TLB size") - -class AlphaDTB(AlphaTLB): - size = 64 - -class AlphaITB(AlphaTLB): - size = 48 diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/SConscript --- a/src/arch/alpha/SConscript Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,67 +0,0 @@ -# -*- mode:python -*- - -# Copyright (c) 2004-2005 The Regents of The University of Michigan -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer; -# redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution; -# neither the name of the copyright holders nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Authors: Gabe Black -# Steve Reinhardt - -Import('*') - -if env['TARGET_ISA'] == 'alpha': - Source('decoder.cc') - Source('ev5.cc') - Source('faults.cc') - Source('freebsd/system.cc') - Source('idle_event.cc') - Source('interrupts.cc') - Source('ipr.cc') - Source('isa.cc') - Source('kernel_stats.cc') - Source('linux/linux.cc') - Source('linux/process.cc') - Source('linux/system.cc') - Source('osfpal.cc') - Source('pagetable.cc') - Source('process.cc') - Source('regredir.cc') - Source('remote_gdb.cc') - Source('stacktrace.cc') - Source('system.cc') - Source('tlb.cc') - Source('tru64/process.cc') - Source('tru64/system.cc') - Source('tru64/tru64.cc') - Source('utility.cc') - Source('vtophys.cc') - - SimObject('AlphaInterrupts.py') - SimObject('AlphaISA.py') - SimObject('AlphaSystem.py') - SimObject('AlphaTLB.py') - - # Add in files generated by the ISA description. - env.ISADesc('isa/main.isa') diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/SConsopts --- a/src/arch/alpha/SConsopts Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,33 +0,0 @@ -# -*- mode:python -*- - -# Copyright (c) 2004-2005 The Regents of The University of Michigan -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer; -# redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution; -# neither the name of the copyright holders nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Authors: Nathan Binkert - -Import('*') - -all_isa_list.append('alpha') diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/aout_machdep.h --- a/src/arch/alpha/aout_machdep.h Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,70 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Steve Reinhardt - * Nathan Binkert - */ - -#ifndef __AOUT_MACHDEP_H__ -#define __AOUT_MACHDEP_H__ - -/// -/// Funky Alpha 64-bit a.out header used for PAL code. -/// -struct aout_exechdr { - uint16_t magic; ///< magic number - uint16_t vstamp; ///< version stamp? - uint16_t bldrev; ///< ??? - uint16_t padcell; ///< padding - uint64_t tsize; ///< text segment size - uint64_t dsize; ///< data segment size - uint64_t bsize; ///< bss segment size - uint64_t entry; ///< entry point - uint64_t text_start; ///< text base address - uint64_t data_start; ///< data base address - uint64_t bss_start; ///< bss base address - uint32_t gprmask; ///< GPR mask (unused, AFAIK) - uint32_t fprmask; ///< FPR mask (unused, AFAIK) - uint64_t gp_value; ///< global pointer reg value -}; - -#define AOUT_LDPGSZ 8192 - -#define N_GETMAGIC(ex) ((ex).magic) - -#define N_BADMAX - -#define N_TXTADDR(ex) ((ex).text_start) -#define N_DATADDR(ex) ((ex).data_start) -#define N_BSSADDR(ex) ((ex).bss_start) - -#define N_TXTOFF(ex) \ - (N_GETMAGIC(ex) == ZMAGIC ? 0 : sizeof(struct aout_exechdr)) - -#define N_DATOFF(ex) N_ALIGN(ex, N_TXTOFF(ex) + (ex).tsize) - -#endif /* !__AOUT_MACHDEP_H__*/ diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/decoder.hh --- a/src/arch/alpha/decoder.hh Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,117 +0,0 @@ -/* - * Copyright (c) 2012 Google - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - */ - -#ifndef __ARCH_ALPHA_DECODER_HH__ -#define __ARCH_ALPHA_DECODER_HH__ - -#include "arch/generic/decode_cache.hh" -#include "arch/types.hh" -#include "cpu/static_inst.hh" -#include "sim/full_system.hh" - -namespace AlphaISA -{ - -class ISA; -class Decoder -{ - protected: - // The extended machine instruction being generated - ExtMachInst ext_inst; - bool instDone; - - public: - Decoder(ISA* isa = nullptr) : instDone(false) - {} - - void - process() - { } - - void - reset() - { - instDone = false; - } - - // Use this to give data to the predecoder. This should be used - // when there is control flow. - void - moreBytes(const PCState &pc, Addr fetchPC, MachInst inst) - { - ext_inst = inst; - instDone = true; - if (FullSystem) - ext_inst |= (static_cast(pc.pc() & 0x1) << 32); - } - - bool - needMoreBytes() - { - return true; - } - - bool - instReady() - { - return instDone; - } - - void takeOverFrom(Decoder * old) {} - - protected: - /// A cache of decoded instruction objects. - static GenericISA::BasicDecodeCache defaultCache; - - public: - StaticInstPtr decodeInst(ExtMachInst mach_inst); - - /// Decode a machine instruction. - /// @param mach_inst The binary instruction to decode. - /// @retval A pointer to the corresponding StaticInst object. - StaticInstPtr - decode(ExtMachInst mach_inst, Addr addr) - { - return defaultCache.decode(this, mach_inst, addr); - } - - StaticInstPtr - decode(AlphaISA::PCState &nextPC) - { - if (!instDone) - return NULL; - instDone = false; - return decode(ext_inst, nextPC.instAddr()); - } -}; - -} // namespace AlphaISA - -#endif // __ARCH_ALPHA_DECODER_HH__ diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/decoder.cc --- a/src/arch/alpha/decoder.cc Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,38 +0,0 @@ -/* - * Copyright (c) 2011 Google - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - */ - -#include "arch/alpha/decoder.hh" - -namespace AlphaISA -{ - -GenericISA::BasicDecodeCache Decoder::defaultCache; - -} diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/ecoff_machdep.h --- a/src/arch/alpha/ecoff_machdep.h Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,73 +0,0 @@ -/* - * Taken from NetBSD arch/alpha/ecoff_machdep.h - */ - -/* $NetBSD: ecoff_machdep.h,v 1.5 1999/04/27 02:32:33 cgd Exp $ */ - -/* - * Copyright (c) 1994 Adam Glass - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by Adam Glass. - * 4. The name of the Author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY Adam Glass ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL Adam Glass BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -// -// Define COFF/ECOFF integer type sizes -// -typedef int16_t coff_short; -typedef uint16_t coff_ushort; -typedef int32_t coff_int; -typedef uint32_t coff_uint; -typedef int64_t coff_long; -typedef uint64_t coff_ulong; -typedef uint64_t coff_addr; - -#define ECOFF_LDPGSZ 4096 - -#define ECOFF_PAD \ - coff_ushort bldrev; /* XXX */ - -#define ECOFF_MACHDEP \ - coff_uint gprmask; \ - coff_uint fprmask; \ - coff_ulong gp_value - -#define ECOFF_MAGIC_ALPHA 0603 -#define ECOFF_MAGIC_NETBSD_ALPHA 0605 -#define ECOFF_BADMAG(ep) \ - ((ep)->f.f_magic != ECOFF_MAGIC_ALPHA && \ - (ep)->f.f_magic != ECOFF_MAGIC_NETBSD_ALPHA) - -#define ECOFF_FLAG_EXEC 0002 -#define ECOFF_SEGMENT_ALIGNMENT(ep) \ - (((ep)->f.f_flags & ECOFF_FLAG_EXEC) == 0 ? 8 : 16) - -#define ECOFF_FLAG_OBJECT_TYPE_MASK 0x3000 -#define ECOFF_OBJECT_TYPE_NO_SHARED 0x1000 -#define ECOFF_OBJECT_TYPE_SHARABLE 0x2000 -#define ECOFF_OBJECT_TYPE_CALL_SHARED 0x3000 - diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/ev5.hh --- a/src/arch/alpha/ev5.hh Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,115 +0,0 @@ -/* - * Copyright (c) 2002-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Steve Reinhardt - * Nathan Binkert - * Ali Saidi - */ - -#ifndef __ARCH_ALPHA_EV5_HH__ -#define __ARCH_ALPHA_EV5_HH__ - -#include "arch/alpha/isa_traits.hh" - -class ThreadContext; - -namespace AlphaISA { - -const uint64_t AsnMask = ULL(0xff); -const int VAddrImplBits = 43; -const Addr VAddrImplMask = (ULL(1) << VAddrImplBits) - 1; -const Addr VAddrUnImplMask = ~VAddrImplMask; -inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; } -inline Addr VAddrVPN(Addr a) { return a >> PageShift; } -inline Addr VAddrOffset(Addr a) { return a & PageOffset; } -inline Addr VAddrSpaceEV5(Addr a) { return a >> 41 & 0x3; } -inline Addr VAddrSpaceEV6(Addr a) { return a >> 41 & 0x7f; } - -inline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFFF00000); } -const int PAddrImplBits = 44; // for Tsunami -const Addr PAddrImplMask = (ULL(1) << PAddrImplBits) - 1; -const Addr PAddrUncachedBit39 = ULL(0x8000000000); -const Addr PAddrUncachedBit40 = ULL(0x10000000000); -const Addr PAddrUncachedBit43 = ULL(0x80000000000); -const Addr PAddrUncachedMask = ULL(0x807ffffffff); // Clear PA<42:35> - -inline Addr -Phys2K0Seg(Addr addr) -{ - if (addr & PAddrUncachedBit43) { - addr &= PAddrUncachedMask; - addr |= PAddrUncachedBit40; - } - return addr | K0SegBase; -} - -inline int DTB_ASN_ASN(uint64_t reg) { return reg >> 57 & AsnMask; } -inline Addr DTB_PTE_PPN(uint64_t reg) -{ return reg >> 32 & ((ULL(1) << (PAddrImplBits - PageShift)) - 1); } -inline int DTB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; } -inline int DTB_PTE_XWE(uint64_t reg) { return reg >> 12 & 0xf; } -inline int DTB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; } -inline int DTB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; } -inline int DTB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; } -inline int DTB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; } - -inline int ITB_ASN_ASN(uint64_t reg) { return reg >> 4 & AsnMask; } -inline Addr ITB_PTE_PPN(uint64_t reg) -{ return reg >> 32 & ((ULL(1) << (PAddrImplBits - PageShift)) - 1); } -inline int ITB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; } -inline bool ITB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; } -inline bool ITB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; } -inline int ITB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; } -inline bool ITB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; } - -inline uint64_t MCSR_SP(uint64_t reg) { return reg >> 1 & 0x3; } - -inline bool ICSR_SDE(uint64_t reg) { return reg >> 30 & 0x1; } -inline int ICSR_SPE(uint64_t reg) { return reg >> 28 & 0x3; } -inline bool ICSR_FPE(uint64_t reg) { return reg >> 26 & 0x1; } - -inline uint64_t ALT_MODE_AM(uint64_t reg) { return reg >> 3 & 0x3; } -inline uint64_t DTB_CM_CM(uint64_t reg) { return reg >> 3 & 0x3; } -inline uint64_t ICM_CM(uint64_t reg) { return reg >> 3 & 0x3; } - -const uint64_t MM_STAT_BAD_VA_MASK = ULL(0x0020); -const uint64_t MM_STAT_DTB_MISS_MASK = ULL(0x0010); -const uint64_t MM_STAT_FONW_MASK = ULL(0x0008); -const uint64_t MM_STAT_FONR_MASK = ULL(0x0004); -const uint64_t MM_STAT_ACV_MASK = ULL(0x0002); -const uint64_t MM_STAT_WR_MASK = ULL(0x0001); -inline int Opcode(MachInst inst) { return inst >> 26 & 0x3f; } -inline int Ra(MachInst inst) { return inst >> 21 & 0x1f; } - -const Addr PalBase = 0x4000; -const Addr PalMax = 0x10000; - -void copyIprs(ThreadContext *src, ThreadContext *dest); - -} // namespace AlphaISA - -#endif // __ARCH_ALPHA_EV5_HH__ diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/ev5.cc --- a/src/arch/alpha/ev5.cc Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,510 +0,0 @@ -/* - * Copyright (c) 2002-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Steve Reinhardt - * Nathan Binkert - */ - -#include "arch/alpha/faults.hh" -#include "arch/alpha/isa_traits.hh" -#include "arch/alpha/kernel_stats.hh" -#include "arch/alpha/osfpal.hh" -#include "arch/alpha/tlb.hh" -#include "base/cp_annotate.hh" -#include "base/debug.hh" -#include "cpu/base.hh" -#include "cpu/simple_thread.hh" -#include "cpu/thread_context.hh" -#include "sim/sim_exit.hh" - -namespace AlphaISA { - -//////////////////////////////////////////////////////////////////////// -// -// Machine dependent functions -// -void -initCPU(ThreadContext *tc, int cpuId) -{ - initIPRs(tc, cpuId); - - tc->setIntReg(16, cpuId); - tc->setIntReg(0, cpuId); - - AlphaFault *reset = new ResetFault; - - tc->pcState(tc->readMiscRegNoEffect(IPR_PAL_BASE) + reset->vect()); - - delete reset; -} - -template -void -zeroRegisters(CPU *cpu) -{ - // Insure ISA semantics - // (no longer very clean due to the change in setIntReg() in the - // cpu model. Consider changing later.) - cpu->thread->setIntReg(ZeroReg, 0); - cpu->thread->setFloatReg(ZeroReg, 0.0); -} - -//////////////////////////////////////////////////////////////////////// -// -// -// -void -initIPRs(ThreadContext *tc, int cpuId) -{ - for (int i = 0; i < NumInternalProcRegs; ++i) { - tc->setMiscRegNoEffect(i, 0); - } - - tc->setMiscRegNoEffect(IPR_PAL_BASE, PalBase); - tc->setMiscRegNoEffect(IPR_MCSR, 0x6); - tc->setMiscRegNoEffect(IPR_PALtemp16, cpuId); -} - -MiscReg -ISA::readIpr(int idx, ThreadContext *tc) -{ - uint64_t retval = 0; // return value, default 0 - - switch (idx) { - case IPR_PALtemp0: - case IPR_PALtemp1: - case IPR_PALtemp2: - case IPR_PALtemp3: - case IPR_PALtemp4: - case IPR_PALtemp5: - case IPR_PALtemp6: - case IPR_PALtemp7: - case IPR_PALtemp8: - case IPR_PALtemp9: - case IPR_PALtemp10: - case IPR_PALtemp11: - case IPR_PALtemp12: - case IPR_PALtemp13: - case IPR_PALtemp14: - case IPR_PALtemp15: - case IPR_PALtemp16: - case IPR_PALtemp17: - case IPR_PALtemp18: - case IPR_PALtemp19: - case IPR_PALtemp20: - case IPR_PALtemp21: - case IPR_PALtemp22: - case IPR_PALtemp23: - case IPR_PAL_BASE: - - case IPR_IVPTBR: - case IPR_DC_MODE: - case IPR_MAF_MODE: - case IPR_ISR: - case IPR_EXC_ADDR: - case IPR_IC_PERR_STAT: - case IPR_DC_PERR_STAT: - case IPR_MCSR: - case IPR_ASTRR: - case IPR_ASTER: - case IPR_SIRR: - case IPR_ICSR: - case IPR_ICM: - case IPR_DTB_CM: - case IPR_IPLR: - case IPR_INTID: - case IPR_PMCTR: - // no side-effect - retval = ipr[idx]; - break; - - case IPR_CC: - retval |= ipr[idx] & ULL(0xffffffff00000000); - retval |= tc->getCpuPtr()->curCycle() & ULL(0x00000000ffffffff); - break; - - case IPR_VA: - retval = ipr[idx]; - break; - - case IPR_VA_FORM: - case IPR_MM_STAT: - case IPR_IFAULT_VA_FORM: - case IPR_EXC_MASK: - case IPR_EXC_SUM: - retval = ipr[idx]; - break; - - case IPR_DTB_PTE: - { - TlbEntry &entry = tc->getDTBPtr()->index(1); - - retval |= ((uint64_t)entry.ppn & ULL(0x7ffffff)) << 32; - retval |= ((uint64_t)entry.xre & ULL(0xf)) << 8; - retval |= ((uint64_t)entry.xwe & ULL(0xf)) << 12; - retval |= ((uint64_t)entry.fonr & ULL(0x1)) << 1; - retval |= ((uint64_t)entry.fonw & ULL(0x1))<< 2; - retval |= ((uint64_t)entry.asma & ULL(0x1)) << 4; - retval |= ((uint64_t)entry.asn & ULL(0x7f)) << 57; - } - break; - - // write only registers - case IPR_HWINT_CLR: - case IPR_SL_XMIT: - case IPR_DC_FLUSH: - case IPR_IC_FLUSH: - case IPR_ALT_MODE: - case IPR_DTB_IA: - case IPR_DTB_IAP: - case IPR_ITB_IA: - case IPR_ITB_IAP: - panic("Tried to read write only register %d\n", idx); - break; - - default: - // invalid IPR - panic("Tried to read from invalid ipr %d\n", idx); - break; - } - - return retval; -} - -// Cause the simulator to break when changing to the following IPL -int break_ipl = -1; - -void -ISA::setIpr(int idx, uint64_t val, ThreadContext *tc) -{ - switch (idx) { - case IPR_PALtemp0: - case IPR_PALtemp1: - case IPR_PALtemp2: - case IPR_PALtemp3: - case IPR_PALtemp4: - case IPR_PALtemp5: - case IPR_PALtemp6: - case IPR_PALtemp7: - case IPR_PALtemp8: - case IPR_PALtemp9: - case IPR_PALtemp10: - case IPR_PALtemp11: - case IPR_PALtemp12: - case IPR_PALtemp13: - case IPR_PALtemp14: - case IPR_PALtemp15: - case IPR_PALtemp16: - case IPR_PALtemp17: - case IPR_PALtemp18: - case IPR_PALtemp19: - case IPR_PALtemp20: - case IPR_PALtemp21: - case IPR_PALtemp22: - case IPR_PAL_BASE: - case IPR_IC_PERR_STAT: - case IPR_DC_PERR_STAT: - case IPR_PMCTR: - // write entire quad w/ no side-effect - ipr[idx] = val; - break; - - case IPR_CC_CTL: - // This IPR resets the cycle counter. We assume this only - // happens once... let's verify that. - assert(ipr[idx] == 0); - ipr[idx] = 1; - break; - - case IPR_CC: - // This IPR only writes the upper 64 bits. It's ok to write - // all 64 here since we mask out the lower 32 in rpcc (see - // isa_desc). - ipr[idx] = val; - break; - - case IPR_PALtemp23: - // write entire quad w/ no side-effect - if (tc->getKernelStats()) - tc->getKernelStats()->context(ipr[idx], val, tc); - ipr[idx] = val; - break; - - case IPR_DTB_PTE: - // write entire quad w/ no side-effect, tag is forthcoming - ipr[idx] = val; - break; - - case IPR_EXC_ADDR: - // second least significant bit in PC is always zero - ipr[idx] = val & ~2; - break; - - case IPR_ASTRR: - case IPR_ASTER: - // only write least significant four bits - privilege mask - ipr[idx] = val & 0xf; - break; - - case IPR_IPLR: - // only write least significant five bits - interrupt level - ipr[idx] = val & 0x1f; - if (tc->getKernelStats()) - tc->getKernelStats()->swpipl(ipr[idx]); - break; - - case IPR_DTB_CM: - if (val & 0x18) { - if (tc->getKernelStats()) - tc->getKernelStats()->mode(Kernel::user, tc); - } else { - if (tc->getKernelStats()) - tc->getKernelStats()->mode(Kernel::kernel, tc); - } - - case IPR_ICM: - // only write two mode bits - processor mode - ipr[idx] = val & 0x18; - break; - - case IPR_ALT_MODE: - // only write two mode bits - processor mode - ipr[idx] = val & 0x18; - break; - - case IPR_MCSR: - // more here after optimization... - ipr[idx] = val; - break; - - case IPR_SIRR: - // only write software interrupt mask - ipr[idx] = val & 0x7fff0; - break; - - case IPR_ICSR: - ipr[idx] = val & ULL(0xffffff0300); - break; - - case IPR_IVPTBR: - case IPR_MVPTBR: - ipr[idx] = val & ULL(0xffffffffc0000000); - break; - - case IPR_DC_TEST_CTL: - ipr[idx] = val & 0x1ffb; - break; - - case IPR_DC_MODE: - case IPR_MAF_MODE: - ipr[idx] = val & 0x3f; - break; - - case IPR_ITB_ASN: - ipr[idx] = val & 0x7f0; - break; - - case IPR_DTB_ASN: - ipr[idx] = val & ULL(0xfe00000000000000); - break; - - case IPR_EXC_SUM: - case IPR_EXC_MASK: - // any write to this register clears it - ipr[idx] = 0; - break; - - case IPR_INTID: - case IPR_SL_RCV: - case IPR_MM_STAT: - case IPR_ITB_PTE_TEMP: - case IPR_DTB_PTE_TEMP: - // read-only registers - panic("Tried to write read only ipr %d\n", idx); - - case IPR_HWINT_CLR: - case IPR_SL_XMIT: - case IPR_DC_FLUSH: - case IPR_IC_FLUSH: - // the following are write only - ipr[idx] = val; - break; - - case IPR_DTB_IA: - // really a control write - ipr[idx] = 0; - - tc->getDTBPtr()->flushAll(); - break; - - case IPR_DTB_IAP: - // really a control write - ipr[idx] = 0; - - tc->getDTBPtr()->flushProcesses(); - break; - - case IPR_DTB_IS: - // really a control write - ipr[idx] = val; - - tc->getDTBPtr()->flushAddr(val, DTB_ASN_ASN(ipr[IPR_DTB_ASN])); - break; - - case IPR_DTB_TAG: { - struct TlbEntry entry; - - // FIXME: granularity hints NYI... - if (DTB_PTE_GH(ipr[IPR_DTB_PTE]) != 0) - panic("PTE GH field != 0"); - - // write entire quad - ipr[idx] = val; - - // construct PTE for new entry - entry.ppn = DTB_PTE_PPN(ipr[IPR_DTB_PTE]); - entry.xre = DTB_PTE_XRE(ipr[IPR_DTB_PTE]); - entry.xwe = DTB_PTE_XWE(ipr[IPR_DTB_PTE]); - entry.fonr = DTB_PTE_FONR(ipr[IPR_DTB_PTE]); - entry.fonw = DTB_PTE_FONW(ipr[IPR_DTB_PTE]); - entry.asma = DTB_PTE_ASMA(ipr[IPR_DTB_PTE]); - entry.asn = DTB_ASN_ASN(ipr[IPR_DTB_ASN]); - - // insert new TAG/PTE value into data TLB - tc->getDTBPtr()->insert(val, entry); - } - break; - - case IPR_ITB_PTE: { - struct TlbEntry entry; - - // FIXME: granularity hints NYI... - if (ITB_PTE_GH(val) != 0) - panic("PTE GH field != 0"); - - // write entire quad - ipr[idx] = val; - - // construct PTE for new entry - entry.ppn = ITB_PTE_PPN(val); - entry.xre = ITB_PTE_XRE(val); - entry.xwe = 0; - entry.fonr = ITB_PTE_FONR(val); - entry.fonw = ITB_PTE_FONW(val); - entry.asma = ITB_PTE_ASMA(val); - entry.asn = ITB_ASN_ASN(ipr[IPR_ITB_ASN]); - - // insert new TAG/PTE value into data TLB - tc->getITBPtr()->insert(ipr[IPR_ITB_TAG], entry); - } - break; - - case IPR_ITB_IA: - // really a control write - ipr[idx] = 0; - - tc->getITBPtr()->flushAll(); - break; - - case IPR_ITB_IAP: - // really a control write - ipr[idx] = 0; - - tc->getITBPtr()->flushProcesses(); - break; - - case IPR_ITB_IS: - // really a control write - ipr[idx] = val; - - tc->getITBPtr()->flushAddr(val, ITB_ASN_ASN(ipr[IPR_ITB_ASN])); - break; - - default: - // invalid IPR - panic("Tried to write to invalid ipr %d\n", idx); - } - - // no error... -} - -void -copyIprs(ThreadContext *src, ThreadContext *dest) -{ - for (int i = 0; i < NumInternalProcRegs; ++i) - dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i)); -} - -} // namespace AlphaISA - -using namespace AlphaISA; - -Fault -SimpleThread::hwrei() -{ - PCState pc = pcState(); - if (!(pc.pc() & 0x3)) - return std::make_shared(); - - pc.npc(readMiscRegNoEffect(IPR_EXC_ADDR)); - pcState(pc); - - CPA::cpa()->swAutoBegin(tc, pc.npc()); - - if (kernelStats) - kernelStats->hwrei(); - - // FIXME: XXX check for interrupts? XXX - return NoFault; -} - -/** - * Check for special simulator handling of specific PAL calls. - * If return value is false, actual PAL call will be suppressed. - */ -bool -SimpleThread::simPalCheck(int palFunc) -{ - if (kernelStats) - kernelStats->callpal(palFunc, tc); - - switch (palFunc) { - case PAL::halt: - halt(); - if (--System::numSystemsRunning == 0) - exitSimLoop("all cpus halted"); - break; - - case PAL::bpt: - case PAL::bugchk: - if (system->breakpoint()) - return false; - break; - } - - return true; -} diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/faults.hh --- a/src/arch/alpha/faults.hh Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,333 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - * Kevin Lim - */ - -#ifndef __ARCH_ALPHA_FAULTS_HH__ -#define __ARCH_ALPHA_FAULTS_HH__ - -#include "arch/alpha/pagetable.hh" -#include "mem/request.hh" -#include "sim/faults.hh" - -// The design of the "name" and "vect" functions is in sim/faults.hh - -namespace AlphaISA { - -typedef Addr FaultVect; - -class AlphaFault : public FaultBase -{ - protected: - virtual bool skipFaultingInstruction() {return false;} - virtual bool setRestartAddress() {return true;} - public: - virtual ~AlphaFault() {} - void invoke(ThreadContext * tc, const StaticInstPtr &inst = - StaticInst::nullStaticInstPtr); - virtual FaultVect vect() = 0; - virtual FaultStat & countStat() = 0; -}; - -class MachineCheckFault : public AlphaFault -{ - private: - static FaultName _name; - static FaultVect _vect; - static FaultStat _count; - - public: - FaultName name() const {return _name;} - FaultVect vect() {return _vect;} - FaultStat & countStat() {return _count;} -}; - -class AlignmentFault : public AlphaFault -{ - private: - static FaultName _name; - static FaultVect _vect; - static FaultStat _count; - - public: - FaultName name() const {return _name;} - FaultVect vect() {return _vect;} - FaultStat & countStat() {return _count;} - bool isAlignmentFault() const {return true;} -}; - -class ResetFault : public AlphaFault -{ - private: - static FaultName _name; - static FaultVect _vect; - static FaultStat _count; - - public: - FaultName name() const {return _name;} - FaultVect vect() {return _vect;} - FaultStat & countStat() {return _count;} -}; - -class ArithmeticFault : public AlphaFault -{ - private: - static FaultName _name; - static FaultVect _vect; - static FaultStat _count; - - protected: - bool skipFaultingInstruction() {return true;} - - public: - FaultName name() const {return _name;} - FaultVect vect() {return _vect;} - FaultStat & countStat() {return _count;} - void invoke(ThreadContext * tc, const StaticInstPtr &inst = - StaticInst::nullStaticInstPtr); -}; - -class InterruptFault : public AlphaFault -{ - private: - static FaultName _name; - static FaultVect _vect; - static FaultStat _count; - - protected: - bool setRestartAddress() {return false;} - - public: - FaultName name() const {return _name;} - FaultVect vect() {return _vect;} - FaultStat & countStat() {return _count;} -}; - -class DtbFault : public AlphaFault -{ - protected: - VAddr vaddr; - Request::Flags reqFlags; - uint64_t flags; - - public: - DtbFault(VAddr _vaddr, Request::Flags _reqFlags, uint64_t _flags) - : vaddr(_vaddr), reqFlags(_reqFlags), flags(_flags) - { } - FaultName name() const = 0; - FaultVect vect() = 0; - FaultStat & countStat() = 0; - void invoke(ThreadContext * tc, const StaticInstPtr &inst = - StaticInst::nullStaticInstPtr); -}; - -class NDtbMissFault : public DtbFault -{ - private: - static FaultName _name; - static FaultVect _vect; - static FaultStat _count; - - public: - NDtbMissFault(VAddr vaddr, Request::Flags reqFlags, uint64_t flags) - : DtbFault(vaddr, reqFlags, flags) - { } - FaultName name() const {return _name;} - FaultVect vect() {return _vect;} - FaultStat & countStat() {return _count;} - void invoke(ThreadContext * tc, const StaticInstPtr &inst = - StaticInst::nullStaticInstPtr); -}; - -class PDtbMissFault : public DtbFault -{ - private: - static FaultName _name; - static FaultVect _vect; - static FaultStat _count; - - public: - PDtbMissFault(VAddr vaddr, Request::Flags reqFlags, uint64_t flags) - : DtbFault(vaddr, reqFlags, flags) - { } - FaultName name() const {return _name;} - FaultVect vect() {return _vect;} - FaultStat & countStat() {return _count;} -}; - -class DtbPageFault : public DtbFault -{ - private: - static FaultName _name; - static FaultVect _vect; - static FaultStat _count; - - public: - DtbPageFault(VAddr vaddr, Request::Flags reqFlags, uint64_t flags) - : DtbFault(vaddr, reqFlags, flags) - { } - FaultName name() const {return _name;} - FaultVect vect() {return _vect;} - FaultStat & countStat() {return _count;} -}; - -class DtbAcvFault : public DtbFault -{ - private: - static FaultName _name; - static FaultVect _vect; - static FaultStat _count; - - public: - DtbAcvFault(VAddr vaddr, Request::Flags reqFlags, uint64_t flags) - : DtbFault(vaddr, reqFlags, flags) - { } - FaultName name() const {return _name;} - FaultVect vect() {return _vect;} - FaultStat & countStat() {return _count;} -}; - -class DtbAlignmentFault : public DtbFault -{ - private: - static FaultName _name; - static FaultVect _vect; - static FaultStat _count; - - public: - DtbAlignmentFault(VAddr vaddr, Request::Flags reqFlags, uint64_t flags) - : DtbFault(vaddr, reqFlags, flags) - { } - FaultName name() const {return _name;} - FaultVect vect() {return _vect;} - FaultStat & countStat() {return _count;} -}; - -class ItbFault : public AlphaFault -{ - protected: - Addr pc; - - public: - ItbFault(Addr _pc) : pc(_pc) { } - FaultName name() const = 0; - FaultVect vect() = 0; - FaultStat & countStat() = 0; - void invoke(ThreadContext * tc, const StaticInstPtr &inst = - StaticInst::nullStaticInstPtr); -}; - -class ItbPageFault : public ItbFault -{ - private: - static FaultName _name; - static FaultVect _vect; - static FaultStat _count; - - public: - ItbPageFault(Addr pc) : ItbFault(pc) { } - FaultName name() const {return _name;} - FaultVect vect() {return _vect;} - FaultStat & countStat() {return _count;} - void invoke(ThreadContext * tc, const StaticInstPtr &inst = - StaticInst::nullStaticInstPtr); -}; - -class ItbAcvFault : public ItbFault -{ - private: - static FaultName _name; - static FaultVect _vect; - static FaultStat _count; - - public: - ItbAcvFault(Addr pc) : ItbFault(pc) { } - FaultName name() const {return _name;} - FaultVect vect() {return _vect;} - FaultStat & countStat() {return _count;} -}; - -class UnimplementedOpcodeFault : public AlphaFault -{ - private: - static FaultName _name; - static FaultVect _vect; - static FaultStat _count; - - public: - FaultName name() const {return _name;} - FaultVect vect() {return _vect;} - FaultStat & countStat() {return _count;} -}; - -class FloatEnableFault : public AlphaFault -{ - private: - static FaultName _name; - static FaultVect _vect; - static FaultStat _count; - - public: - FaultName name() const {return _name;} - FaultVect vect() {return _vect;} - FaultStat & countStat() {return _count;} -}; - -class PalFault : public AlphaFault -{ - private: - static FaultName _name; - static FaultVect _vect; - static FaultStat _count; - - protected: - bool skipFaultingInstruction() {return true;} - - public: - FaultName name() const {return _name;} - FaultVect vect() {return _vect;} - FaultStat & countStat() {return _count;} -}; - -class IntegerOverflowFault : public AlphaFault -{ - private: - static FaultName _name; - static FaultVect _vect; - static FaultStat _count; - - public: - FaultName name() const {return _name;} - FaultVect vect() {return _vect;} - FaultStat & countStat() {return _count;} -}; - -} // namespace AlphaISA - -#endif // __ARCH_ALPHA_FAULTS_HH__ diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/faults.cc --- a/src/arch/alpha/faults.cc Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,224 +0,0 @@ -/* - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Gabe Black - * Kevin Lim - */ - -#include "arch/alpha/ev5.hh" -#include "arch/alpha/faults.hh" -#include "arch/alpha/tlb.hh" -#include "base/trace.hh" -#include "cpu/base.hh" -#include "cpu/thread_context.hh" -#include "mem/page_table.hh" -#include "sim/process.hh" -#include "sim/full_system.hh" - -namespace AlphaISA { - -FaultName MachineCheckFault::_name = "mchk"; -FaultVect MachineCheckFault::_vect = 0x0401; -FaultStat MachineCheckFault::_count; - -FaultName AlignmentFault::_name = "unalign"; -FaultVect AlignmentFault::_vect = 0x0301; -FaultStat AlignmentFault::_count; - -FaultName ResetFault::_name = "reset"; -FaultVect ResetFault::_vect = 0x0001; -FaultStat ResetFault::_count; - -FaultName ArithmeticFault::_name = "arith"; -FaultVect ArithmeticFault::_vect = 0x0501; -FaultStat ArithmeticFault::_count; - -FaultName InterruptFault::_name = "interrupt"; -FaultVect InterruptFault::_vect = 0x0101; -FaultStat InterruptFault::_count; - -FaultName NDtbMissFault::_name = "dtb_miss_single"; -FaultVect NDtbMissFault::_vect = 0x0201; -FaultStat NDtbMissFault::_count; - -FaultName PDtbMissFault::_name = "dtb_miss_double"; -FaultVect PDtbMissFault::_vect = 0x0281; -FaultStat PDtbMissFault::_count; - -FaultName DtbPageFault::_name = "dtb_page_fault"; -FaultVect DtbPageFault::_vect = 0x0381; -FaultStat DtbPageFault::_count; - -FaultName DtbAcvFault::_name = "dtb_acv_fault"; -FaultVect DtbAcvFault::_vect = 0x0381; -FaultStat DtbAcvFault::_count; - -FaultName DtbAlignmentFault::_name = "unalign"; -FaultVect DtbAlignmentFault::_vect = 0x0301; -FaultStat DtbAlignmentFault::_count; - -FaultName ItbPageFault::_name = "itbmiss"; -FaultVect ItbPageFault::_vect = 0x0181; -FaultStat ItbPageFault::_count; - -FaultName ItbAcvFault::_name = "iaccvio"; -FaultVect ItbAcvFault::_vect = 0x0081; -FaultStat ItbAcvFault::_count; - -FaultName UnimplementedOpcodeFault::_name = "opdec"; -FaultVect UnimplementedOpcodeFault::_vect = 0x0481; -FaultStat UnimplementedOpcodeFault::_count; - -FaultName FloatEnableFault::_name = "fen"; -FaultVect FloatEnableFault::_vect = 0x0581; -FaultStat FloatEnableFault::_count; - -FaultName PalFault::_name = "pal"; -FaultVect PalFault::_vect = 0x2001; -FaultStat PalFault::_count; - -FaultName IntegerOverflowFault::_name = "intover"; -FaultVect IntegerOverflowFault::_vect = 0x0501; -FaultStat IntegerOverflowFault::_count; - -void -AlphaFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) -{ - FaultBase::invoke(tc); - if (!FullSystem) - return; - countStat()++; - - PCState pc = tc->pcState(); - - // exception restart address - if (setRestartAddress() || !(pc.pc() & 0x3)) - tc->setMiscRegNoEffect(IPR_EXC_ADDR, pc.pc()); - - if (skipFaultingInstruction()) { - // traps... skip faulting instruction. - tc->setMiscRegNoEffect(IPR_EXC_ADDR, - tc->readMiscRegNoEffect(IPR_EXC_ADDR) + 4); - } - - pc.set(tc->readMiscRegNoEffect(IPR_PAL_BASE) + vect()); - tc->pcState(pc); -} - -void -ArithmeticFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) -{ - FaultBase::invoke(tc); - if (!FullSystem) - return; - panic("Arithmetic traps are unimplemented!"); -} - -void -DtbFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) -{ - if (FullSystem) { - // Set fault address and flags. Even though we're modeling an - // EV5, we use the EV6 technique of not latching fault registers - // on VPTE loads (instead of locking the registers until IPR_VA is - // read, like the EV5). The EV6 approach is cleaner and seems to - // work with EV5 PAL code, but not the other way around. - if (reqFlags.noneSet(AlphaRequestFlags::VPTE | Request::PREFETCH)) { - // set VA register with faulting address - tc->setMiscRegNoEffect(IPR_VA, vaddr); - - // set MM_STAT register flags - MachInst machInst = inst->machInst; - tc->setMiscRegNoEffect(IPR_MM_STAT, - (((Opcode(machInst) & 0x3f) << 11) | - ((Ra(machInst) & 0x1f) << 6) | - (flags & 0x3f))); - - // set VA_FORM register with faulting formatted address - tc->setMiscRegNoEffect(IPR_VA_FORM, - tc->readMiscRegNoEffect(IPR_MVPTBR) | (vaddr.vpn() << 3)); - } - } - - AlphaFault::invoke(tc); -} - -void -ItbFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) -{ - if (FullSystem) { - tc->setMiscRegNoEffect(IPR_ITB_TAG, pc); - tc->setMiscRegNoEffect(IPR_IFAULT_VA_FORM, - tc->readMiscRegNoEffect(IPR_IVPTBR) | (VAddr(pc).vpn() << 3)); - } - - AlphaFault::invoke(tc); -} - -void -ItbPageFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) -{ - if (FullSystem) { - ItbFault::invoke(tc); - return; - } - - Process *p = tc->getProcessPtr(); - TlbEntry entry; - bool success = p->pTable->lookup(pc, entry); - if (!success) { - panic("Tried to execute unmapped address %#x.\n", pc); - } else { - VAddr vaddr(pc); - tc->getITBPtr()->insert(vaddr.page(), entry); - } -} - -void -NDtbMissFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) -{ - if (FullSystem) { - DtbFault::invoke(tc, inst); - return; - } - - Process *p = tc->getProcessPtr(); - TlbEntry entry; - bool success = p->pTable->lookup(vaddr, entry); - if (!success) { - if (p->fixupStackFault(vaddr)) - success = p->pTable->lookup(vaddr, entry); - } - if (!success) { - panic("Tried to access unmapped address %#x.\n", (Addr)vaddr); - } else { - tc->getDTBPtr()->insert(vaddr.page(), entry); - } -} - -} // namespace AlphaISA - diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/freebsd/system.hh --- a/src/arch/alpha/freebsd/system.hh Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,62 +0,0 @@ -/* - * Copyright (c) 2004-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Ben Nash - */ - -#ifndef __ARCH_ALPHA_FREEBSD_SYSTEM_HH__ -#define __ARCH_ALPHA_FREEBSD_SYSTEM_HH__ - -#include "arch/alpha/system.hh" -#include "kern/system_events.hh" -#include "params/FreebsdAlphaSystem.hh" -#include "sim/system.hh" - -class FreebsdAlphaSystem : public AlphaSystem -{ - private: - class SkipCalibrateClocksEvent : public SkipFuncEvent - { - public: - SkipCalibrateClocksEvent(PCEventQueue *q, const std::string &desc, - Addr addr) - : SkipFuncEvent(q, desc, addr) {} - virtual void process(ThreadContext *tc); - }; - - SkipFuncEvent *skipDelayEvent; - SkipCalibrateClocksEvent *skipCalibrateClocks; - - public: - typedef FreebsdAlphaSystemParams Params; - FreebsdAlphaSystem(Params *p); - ~FreebsdAlphaSystem(); - - void doCalibrateClocks(ThreadContext *tc); -}; - -#endif // __ARCH_ALPHA_FREEBSD_SYSTEM_HH__ diff -r 9c673b990d5d -r e1835e5846b9 src/arch/alpha/freebsd/system.cc --- a/src/arch/alpha/freebsd/system.cc Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,94 +0,0 @@ -/* - * Copyright (c) 2004-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Ben Nash - */ - -/** - * @file - * Modifications for the FreeBSD kernel. - * Based on kern/linux/linux_system.cc. - * - */ - -#include "arch/alpha/freebsd/system.hh" -#include "arch/alpha/system.hh" -#include "arch/isa_traits.hh" -#include "arch/vtophys.hh" -#include "base/loader/symtab.hh" -#include "cpu/thread_context.hh" -#include "mem/fs_translating_port_proxy.hh" -#include "sim/byteswap.hh" - -#define TIMER_FREQUENCY 1193180 - -using namespace std; -using namespace AlphaISA; - -FreebsdAlphaSystem::FreebsdAlphaSystem(Params *p) - : AlphaSystem(p) -{ - /** - * Any time DELAY is called just skip the function. - * Shouldn't we actually emulate the delay? - */ - skipDelayEvent = addKernelFuncEvent("DELAY"); - skipCalibrateClocks = - addKernelFuncEvent("calibrate_clocks"); -} - -FreebsdAlphaSystem::~FreebsdAlphaSystem() -{ - delete skipDelayEvent; - delete skipCalibrateClocks; -} - -void -FreebsdAlphaSystem::doCalibrateClocks(ThreadContext *tc) -{ - Addr ppc_vaddr = 0; - Addr timer_vaddr = 0; - - ppc_vaddr = (Addr)tc->readIntReg(17); - timer_vaddr = (Addr)tc->readIntReg(18); - - virtProxy.write(ppc_vaddr, (uint32_t)SimClock::Frequency); - virtProxy.write(timer_vaddr, (uint32_t)TIMER_FREQUENCY); -} - -void -FreebsdAlphaSystem::SkipCalibrateClocksEvent::process(ThreadContext *tc) -{ - SkipFuncEvent::process(tc); - ((FreebsdAlphaSystem *)tc->getSystemPtr())->doCalibrateClocks(tc); -} - -FreebsdAlphaSystem * -FreebsdAlphaSystemParams::create() -{ - return new FreebsdAlphaSystem(this); -} diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,14 +0,0 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:19:44 -gem5 executing on e108600-lin, pid 28054 -command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/50.vortex/alpha/tru64/o3-timing - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Exiting @ tick 22819771500 because target called exit() diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/smred.msg --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/smred.msg Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,158 +0,0 @@ - - SYSTEM TYPE... - __ZTC__ := False - __UNIX__ := True - __RISC__ := True - SPEC_CPU2000_LP64 := True - __MAC__ := False - __BCC__ := False - __BORLANDC__ := False - __GUI__ := False - __WTC__ := False - __HP__ := False - - CODE OPTIONS... - __MACROIZE_HM__ := True - __MACROIZE_MEM__ := True - ENV01 := True - USE_HPP_STYPE_HDRS := False - USE_H_STYPE_HDRS := False - - CODE INCLUSION PARAMETERS... - INCLUDE_ALL_CODE := False - INCLUDE_DELETE_CODE := True - __SWAP_GRP_POS__ := True - __INCLUDE_MTRX__ := False - __BAD_CODE__ := False - API_INCLUDE := False - BE_CAREFUL := False - OLDWAY := False - NOTUSED := False - - SYSTEM PARAMETERS... - EXT_ENUM := 999999999L - CHUNK_CONSTANT := 55555555 - CORE_CONSTANT := 55555555 - CORE_LIMIT := 20971520 - CorePage_Size := 384000 - ALIGN_BYTES := True - CORE_BLOCK_ALIGN := 8 - FAR_MEM := False - - MEMORY MANAGEMENT PARAMETERS... - SYSTEM_ALLOC := True - SYSTEM_FREESTORE := True - __NO_DISKCACHE__ := False - __FREEZE_VCHUNKS__ := True - __FREEZE_GRP_PACKETS__ := True - __MINIMIZE_TREE_CACHE__:= True - - SYSTEM STD PARAMETERS... - __STDOUT__ := False - NULL := 0 - LPTR := False - False_Status := 1 - True_Status := 0 - LARGE := True - TWOBYTE_BOOL := False - __NOSTR__ := False - - MEMORY VALIDATION PARAMETERS... - CORE_CRC_CHECK := False - VALIDATE_MEM_CHUNKS := False - - SYSTEM DEBUG OPTIONS... - DEBUG := False - MCSTAT := False - TRACKBACK := False - FLUSH_FILES := False - DEBUG_CORE0 := False - DEBUG_RISC := False - __TREE_BUG__ := False - __TRACK_FILE_READS__ := False - PAGE_SPACE := False - LEAVE_NO_TRACE := True - NULL_TRACE_STRS := False - - TIME PARAMETERS... - CLOCK_IS_LONG := False - __DISPLAY_TIME__ := False - __TREE_TIME__ := False - __DISPLAY_ERRORS__ := False - - API MACROS... - __BMT01__ := True - OPTIMIZE := True - - END OF DEFINES. - - - - ... IMPLODE MEMORY ... - - SWAP to DiskCache := False - - FREEZE_GRP_PACKETS:= True - - QueBug := 1000 - - sizeof(boolean) = 4 - sizeof(sizetype) = 4 - sizeof(chunkstruc) = 32 - - sizeof(shorttype ) = 2 - sizeof(idtype ) = 2 - sizeof(sizetype ) = 4 - sizeof(indextype ) = 4 - sizeof(numtype ) = 4 - sizeof(handletype) = 4 - sizeof(tokentype ) = 8 - - sizeof(short ) = 2 - sizeof(int ) = 4 - - sizeof(lt64 ) = 4 - sizeof(farlongtype) = 4 - sizeof(long ) = 8 - sizeof(longaddr ) = 8 - - sizeof(float ) = 4 - sizeof(double ) = 8 - - sizeof(addrtype ) = 8 - sizeof(char * ) = 8 - ALLOC CORE_1 :: 16 - BHOOLE NATH - - OPEN File ./input/lendian.rnv - *Status = 0 - DB HDR restored from FileVbn[ 0] - DB BlkDirOffset : @ 2030c0 - DB BlkDirChunk : Chunk[ 10] AT Vbn[3146] - DB BlkTknChunk : Chunk[ 11] AT Vbn[3147] - DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148] - DB Handle Chunk's StackPtr = 20797 - - DB[ 1] LOADED; Handles= 20797 - KERNEL in CORE[ 1] Restored @ 4005c800 - - OPEN File ./input/lendian.wnv - *Status = 0 - DB HDR restored from FileVbn[ 0] - DB BlkDirOffset : @ 21c40 - DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81] - DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82] - DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83] - DB Handle Chunk's StackPtr = 17 - - DB[ 2] LOADED; Handles= 17 - VORTEx_Status == -8 || fffffff8 - - BE HERE NOW !!! - - - - ... VORTEx ON LINE ... - - - ... END OF SESSION ... diff -r 9c673b990d5d -r e1835e5846b9 tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/smred.out --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/smred.out Mon Oct 24 21:38:48 2016 +0100 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,258 +0,0 @@ - CREATE Db Header and Db Primal ... - NEW DB [ 3] Created. - -VORTEX INPUT PARAMETERS:: - MESSAGE FileName: smred.msg - OUTPUT FileName: smred.out - DISK CACHE FileName: NULL - PART DB FileName: parts.db - DRAW DB FileName: draw.db - PERSON DB FileName: emp.db - PERSONS Data FileName: ./input/persons.250 - PARTS Count : 100 - OUTER Loops : 1 - INNER Loops : 1 - LOOKUP Parts : 25 - DELETE Parts : 10 - STUFF Parts : 10 - DEPTH Traverse: 5 - % DECREASE Parts : 0 - % INCREASE LookUps : 0 - % INCREASE Deletes : 0 - % INCREASE Stuffs : 0 - FREEZE_PACKETS : 1 - ALLOC_CHUNKS : 10000 - EXTEND_CHUNKS : 5000 - DELETE Draw objects : True - DELETE Part objects : False - QUE_BUG : 1000 - VOID_BOUNDARY : 67108864 - VOID_RESERVE : 1048576 - - COMMIT_DBS : False - - - - BMT TEST :: files... - EdbName := PartLib - EdbFileName := parts.db - DrwName := DrawLib - DrwFileName := draw.db - EmpName := PersonLib - EmpFileName := emp.db - - Swap to DiskCache := False - Freeze the cache := True - - - BMT TEST :: parms... - DeBug modulo := 1000 - Create Parts count:= 100 - Outer Loops := 1 - Inner Loops := 1 - Look Ups := 25 - Delete Parts := 10 - Stuff Parts := 10 - Traverse Limit := 5 - Delete Draws := True - Delete Parts := False - Delete ALL Parts := after every Outer Loop - - INITIALIZE LIBRARY :: - - INITIALIZE SCHEMA :: - Primal_CreateDb Accessed !!! - CREATE Db Header and Db Primal ... - NEW DB [ 4] Created. - PartLibCreate:: Db[ 4]; VpartsDir= 1 - - Part Count= 1 - - Initialize the Class maps - LIST HEADS loaded ... DbListHead_Class = 207 - DbListNode_Class = 206 - -...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated. - - -...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated. - - Primal_CreateDb Accessed !!! - CREATE Db Header and Db Primal ... - NEW DB [ 5] Created. - DrawLibCreate:: Db[ 5]; VpartsDir= 1 - - Initialize the Class maps of this schema. - Primal_CreateDb Accessed !!! - CREATE Db Header and Db Primal ... - NEW DB [ 6] Created. - - ***NOTE*** Persons Library Extended! - - Create <131072> Persons. - ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ; - - LAST Person Read:: - ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ; - - BUILD for class:: - - if (link[1].length >= 5) :: - - Build Query2 for
class:: - - if (State == CA || State == T*) - - Build Query1 for class:: - - if (LastName >= H* && LastName <= P* && Query0(Residence)) :: - - BUILD for class:: - - if (Id >= 3000 - && (Id >= 3000 && Id <= 3001) - && Id >= 3002) - - BUILD for class:: - - if (Nam == Pre* - || (Nam == ??Mid??? || == Pre??Mid?? || == ??Post - || == Pre??Post || == ??Mid???Post || == Pre??Mid???Post) - && Id <= 7) - SEED := 1008; Swap = False; RgnEntries = 135 - - OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10. - - Create 100 New Parts - Create Part 1. Token[ 4: 2]. - - < 100> Parts Created. CurrentId= 100 - - Connect each instantiated Part TO 3 unique Parts - Connect Part 1. Token[ 4: 2] - Connect Part 25. Token[ 4: 26] FromList= 26. - Connect Part 12. Token[ 4: 13] FromList= 13. - Connect Part 59. Token[ 4: 60] FromList= 60. - - SET entries:: - 1. [ 5: 5] := <1 >; @[: 6] - Iteration count = 100 - - SET entries:: - 1. [ 5: 39] := <14 >; - Iteration count = 12 - - SET entries:: - 1. [ 5: 23] := <8 >; @[: 24] - Iteration count = 12 - - LIST entries:: - 1. [ 5: 23] - Iteration count = 12 - - SET entries:: - Iteration count = 250 - - COMMIT All Image copies:: Release=; Max Parts= 100 - < 100> Part images' Committed. - < 0> are Named. - < 50> Point images' Committed. - < 81> Person images' Committed. - - COMMIT Parts(* 100) - - Commit TestObj_Class in DB. - ItNum 0. Token[ 0: 0]. TestObj Committed. - < 0> TestObj images' Committed. - - Commit CartesianPoint_Class in DB. - ItNum 0. Token[ 0: 0]. CartesianPoint Committed. - < 0> CartesianPoint images' Committed. - - BEGIN Inner Loop Sequence::. - - INNER LOOP [ 1: 1] : - - LOOK UP 25 Random Parts and Export each Part. - - LookUp for 26 parts; Asserts = 8 - Asserts = 2; NULL Asserts = 3. - Asserts = 0; NULL Asserts = 5. - Asserts = 0; NULL Asserts = 0. - Asserts = 0; NULL Asserts = 5. - Asserts = 60; NULL Asserts = 0. - - DELETE 10 Random Parts. - - PartDelete :: Token[ 4: 91]. - PartDisconnect:: Token[ 4: 91] id:= 90 for each link. - DisConnect link [ 0]:= 50; PartToken[ 51: 51]. - DisConnect link [ 1]:= 17; PartToken[ 18: 18]. - DisConnect link [ 2]:= 72; PartToken[ 73: 73]. - DeleteFromList:: Vchunk[ 4: 91]. (* 1) - DisConnect FromList[ 0]:= 56; Token[ 57: 57]. - Vlists[ 89] := 100; - - Delete for 11 parts; - - Traverse Count= 0 - - TRAVERSE PartId[ 6] and all Connections to 5 Levels - SEED In Traverse Part [ 4: 65] @ Level = 4. - - Traverse Count= 357 - Traverse Asserts = 5. True Tests = 1 - < 5> DrawObj objects DELETED. - < 2> are Named. - < 2> Point objects DELETED. - - CREATE 10 Additional Parts - - Create 10 New Parts - Create Part 101. Token[ 4: 102]. - - < 10> Parts Created. CurrentId= 110 - - Connect each instantiated Part TO 3 unique Parts - - COMMIT All Image copies:: Release=; Max Parts= 110 - < 81> Part images' Committed. - < 0> are Named. - < 38> Point images' Committed. - < 31> Person images' Committed. - - COMMIT Parts(* 100) - - Commit TestObj_Class in DB. - ItNum 0. Token[ 3: 4]. TestObj Committed. - < 15> TestObj images' Committed. - - Commit CartesianPoint_Class in DB. - ItNum 0. Token[ 3: 3]. CartesianPoint Committed. - < 16> CartesianPoint images' Committed. - - DELETE All TestObj objects; - - Delete TestObj_Class in DB. - ItNum 0. Token[ 3: 4]. TestObj Deleted. - < 15> TestObj objects Deleted. - - Commit CartesianPoint_Class in DB. - ItNum 0. Token[ 3: 3]. CartesianPoint Deleted. - < 16> CartesianPoint objects Deleted. - - DELETE TestObj and Point objects... - - END INNER LOOP [ 1: 1]. - - DELETE All TestObj objects; - - Delete TestObj_Class in DB. - < 0> TestObj objects Deleted. - - Commit CartesianPoint_Class in DB. - < 0> CartesianPoint objects Deleted. - - DELETE TestObj and Point objects... - STATUS= -201 -V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!