diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/config.json --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/config.json Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,1734 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1, + "memories": [ + "system.mem_ctrls" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [ + 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"device_rowbuffer_size": 1024, + "static_backend_latency": 10, + "max_accesses_per_row": 16, + "IDD3P12": "0.0", + "tREFI": 7800 + } + ], + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/simerr --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/simerr Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,11 @@ +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick +warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/simout --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/simout Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,51 @@ +Redirecting stdout to build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64m/simple-timing-ruby/simout +Redirecting stderr to build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64m/simple-timing-ruby/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 2 2016 20:34:02 +gem5 started Nov 3 2016 18:41:57 +gem5 executing on ubuntu1604, pid 21474 +command line: /home/ar4jc/gem5/build/RISCV/gem5.debug -d build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64m/simple-timing-ruby -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64m/simple-timing-ruby + +Global frequency set at 1000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +mul: PASS +mul, overflow: PASS +mulh: PASS +mulh, negative: PASS +mulh, all bits set: PASS +mulhsu, all bits set: PASS +mulhsu: PASS +mulhu: PASS +mulhu, all bits set: PASS +div: PASS +div/0: PASS +div, overflow: PASS +divu: PASS +divu/0: PASS +divu, "overflow": PASS +rem: PASS +rem/0: PASS +rem, overflow: PASS +remu: PASS +remu/0: PASS +remu, "overflow": PASS +mulw, truncate: PASS +mulw, overflow: PASS +divw, truncate: PASS +divw/0: PASS +divw, overflow: PASS +divuw, truncate: PASS +divuw/0: PASS +divuw, "overflow": PASS +divuw, sign extend: PASS +remw, truncate: PASS +remw/0: PASS +remw, overflow: PASS +remuw, truncate: PASS +remuw/0: PASS +remuw, "overflow": PASS +remuw, sign extend: PASS +Exiting @ tick 1894689 because target called exit() diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/stats.txt --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/stats.txt Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,644 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.001895 # Number of seconds simulated +sim_ticks 1894689 # Number of ticks simulated +final_tick 1894689 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000 # Frequency of simulated ticks +host_inst_rate 6558 # Simulator instruction rate (inst/s) +host_op_rate 6558 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 111776 # Simulator tick rate (ticks/s) +host_mem_usage 441636 # Number of bytes of host memory used +host_seconds 16.95 # Real time elapsed on the host +sim_insts 111163 # Number of instructions simulated +sim_ops 111163 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1 # Clock period in ticks +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 1894689 # Cumulative time (in ticks) in various power states +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 1965312 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 1965312 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 1965056 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 1965056 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 30708 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 30708 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 30704 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 30704 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 1037274191 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 1037274191 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 1037139077 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 1037139077 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 2074413268 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 2074413268 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 30708 # Number of read requests accepted +system.mem_ctrls.writeReqs 30704 # Number of write requests accepted +system.mem_ctrls.readBursts 30708 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 30704 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 840512 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 1124800 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 873600 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 1965312 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 1965056 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 17575 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 17031 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 266 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 451 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 46 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 637 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 186 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 76 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 11 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 839 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 3185 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 1937 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 880 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 899 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 1671 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 1852 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 196 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 1 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 275 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 450 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 46 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 659 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 196 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 82 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 12 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 837 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 3232 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 1974 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 946 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 914 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 1717 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 2109 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 200 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 1 # Per bank write bursts +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.totGap 1894603 # Total gap between requests +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 30708 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 30704 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 13133 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 64 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 84 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 741 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 855 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 858 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 863 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 899 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 881 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 843 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 841 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 841 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 841 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 841 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 841 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 841 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 842 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 841 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 841 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 4108 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 416.888023 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 289.138970 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 327.353669 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 590 14.36% 14.36% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 994 24.20% 38.56% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 655 15.94% 54.50% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 469 11.42% 65.92% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 315 7.67% 73.59% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 226 5.50% 79.09% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 171 4.16% 83.25% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 140 3.41% 86.66% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 548 13.34% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 4108 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 841 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 15.606421 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 15.546412 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 1.461704 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::12-13 22 2.62% 2.62% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::14-15 401 47.68% 50.30% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-17 357 42.45% 92.75% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::18-19 53 6.30% 99.05% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::20-21 7 0.83% 99.88% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::36-37 1 0.12% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 841 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 841 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.230678 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.215495 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 0.734562 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 757 90.01% 90.01% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 12 1.43% 91.44% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 38 4.52% 95.96% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 30 3.57% 99.52% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::20 4 0.48% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 841 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 254880 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 504407 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 65665 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 19.41 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 38.41 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 443.61 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 461.08 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 1037.27 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 1037.14 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 7.07 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 3.47 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 3.60 # Data bus utilization in percentage for writes +system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 26.07 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 9991 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 12677 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 76.08 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 92.72 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 30.85 # Average gap between requests +system.mem_ctrls.pageHitRate 84.56 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 7161420 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 3867864 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 28697088 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 21356064 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 130918320.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 171269040 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 3299712 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.actPowerDownEnergy 480380496 # Energy for active power-down per rank (pJ) +system.mem_ctrls_0.prePowerDownEnergy 68539392 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_0.selfRefreshEnergy 70165920 # Energy for self refresh per rank (pJ) +system.mem_ctrls_0.totalEnergy 985655316 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 520.220108 # Core power per rank (mW) +system.mem_ctrls_0.totalIdleTime 1510469 # Total Idle time Per DRAM Rank +system.mem_ctrls_0.memoryStateTime::IDLE 2680 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 55416 # Time in different power states +system.mem_ctrls_0.memoryStateTime::SREF 278552 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 178488 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 326087 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 1053466 # Time in different power states +system.mem_ctrls_1.actEnergy 22219680 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 12005448 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 121334304 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 92648736 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 151201440.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 222790200 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 4062720 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.actPowerDownEnergy 552170400 # Energy for active power-down per rank (pJ) +system.mem_ctrls_1.prePowerDownEnergy 48813312 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_1.selfRefreshEnergy 20056896 # Energy for self refresh per rank (pJ) +system.mem_ctrls_1.totalEnergy 1247455776 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 658.396062 # Core power per rank (mW) +system.mem_ctrls_1.totalIdleTime 1394963 # Total Idle time Per DRAM Rank +system.mem_ctrls_1.memoryStateTime::IDLE 4058 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 64026 # Time in different power states +system.mem_ctrls_1.memoryStateTime::SREF 57168 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 127118 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 431419 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 1210900 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 1894689 # Cumulative time (in ticks) in various power states +system.cpu.clk_domain.clock 1 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 46 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 1894689 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 1894689 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 111163 # Number of instructions committed +system.cpu.committedOps 111163 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 111164 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 8511 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 17403 # number of instructions that are conditional controls +system.cpu.num_int_insts 111164 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 148887 # number of times the integer registers were read +system.cpu.num_int_register_writes 73798 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 42301 # number of memory refs +system.cpu.num_load_insts 22338 # Number of load instructions +system.cpu.num_store_insts 19963 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 1894689 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 25914 # Number of branches fetched +system.cpu.op_class::No_OpClass 46 0.04% 0.04% # Class of executed instruction +system.cpu.op_class::IntAlu 68715 61.79% 61.83% # Class of executed instruction +system.cpu.op_class::IntMult 122 0.11% 61.94% # Class of executed instruction +system.cpu.op_class::IntDiv 26 0.02% 61.96% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::MemRead 22338 20.09% 82.05% # Class of executed instruction +system.cpu.op_class::MemWrite 19963 17.95% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 111210 # Class of executed instruction +system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.pwrStateResidencyTicks::UNDEFINED 1894689 # Cumulative time (in ticks) in various power states +system.ruby.delayHist::bucket_size 1 # delay histogram for all message +system.ruby.delayHist::max_bucket 9 # delay histogram for all message +system.ruby.delayHist::samples 61412 # delay histogram for all message +system.ruby.delayHist | 61412 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 61412 # delay histogram for all message +system.ruby.outstanding_req_hist_seqr::bucket_size 1 +system.ruby.outstanding_req_hist_seqr::max_bucket 9 +system.ruby.outstanding_req_hist_seqr::samples 153511 +system.ruby.outstanding_req_hist_seqr::mean 1 +system.ruby.outstanding_req_hist_seqr::gmean 1 +system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 153511 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 153511 +system.ruby.latency_hist_seqr::bucket_size 64 +system.ruby.latency_hist_seqr::max_bucket 639 +system.ruby.latency_hist_seqr::samples 153510 +system.ruby.latency_hist_seqr::mean 11.342447 +system.ruby.latency_hist_seqr::gmean 2.153034 +system.ruby.latency_hist_seqr::stdev 26.316023 +system.ruby.latency_hist_seqr | 140762 91.70% 91.70% | 11810 7.69% 99.39% | 622 0.41% 99.79% | 118 0.08% 99.87% | 89 0.06% 99.93% | 83 0.05% 99.98% | 7 0.00% 99.99% | 3 0.00% 99.99% | 1 0.00% 99.99% | 15 0.01% 100.00% +system.ruby.latency_hist_seqr::total 153510 +system.ruby.hit_latency_hist_seqr::bucket_size 1 +system.ruby.hit_latency_hist_seqr::max_bucket 9 +system.ruby.hit_latency_hist_seqr::samples 122802 +system.ruby.hit_latency_hist_seqr::mean 1 +system.ruby.hit_latency_hist_seqr::gmean 1 +system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 122802 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 122802 +system.ruby.miss_latency_hist_seqr::bucket_size 64 +system.ruby.miss_latency_hist_seqr::max_bucket 639 +system.ruby.miss_latency_hist_seqr::samples 30708 +system.ruby.miss_latency_hist_seqr::mean 52.702130 +system.ruby.miss_latency_hist_seqr::gmean 46.230601 +system.ruby.miss_latency_hist_seqr::stdev 36.381667 +system.ruby.miss_latency_hist_seqr | 17960 58.49% 58.49% | 11810 38.46% 96.95% | 622 2.03% 98.97% | 118 0.38% 99.36% | 89 0.29% 99.65% | 83 0.27% 99.92% | 7 0.02% 99.94% | 3 0.01% 99.95% | 1 0.00% 99.95% | 15 0.05% 100.00% +system.ruby.miss_latency_hist_seqr::total 30708 +system.ruby.Directory.incomplete_times_seqr 30707 +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 1894689 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.cacheMemory.demand_hits 122802 # Number of cache demand hits +system.ruby.l1_cntrl0.cacheMemory.demand_misses 30708 # Number of cache demand misses +system.ruby.l1_cntrl0.cacheMemory.demand_accesses 153510 # Number of cache demand accesses +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 1894689 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 1894689 # Cumulative time (in ticks) in various power states +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 1894689 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.percent_links_utilized 8.103177 +system.ruby.network.routers0.msg_count.Control::2 30708 +system.ruby.network.routers0.msg_count.Data::2 30704 +system.ruby.network.routers0.msg_count.Response_Data::4 30708 +system.ruby.network.routers0.msg_count.Writeback_Control::3 30704 +system.ruby.network.routers0.msg_bytes.Control::2 245664 +system.ruby.network.routers0.msg_bytes.Data::2 2210688 +system.ruby.network.routers0.msg_bytes.Response_Data::4 2210976 +system.ruby.network.routers0.msg_bytes.Writeback_Control::3 245632 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 1894689 # Cumulative time (in ticks) in various power states +system.ruby.network.routers1.percent_links_utilized 8.103177 +system.ruby.network.routers1.msg_count.Control::2 30708 +system.ruby.network.routers1.msg_count.Data::2 30704 +system.ruby.network.routers1.msg_count.Response_Data::4 30708 +system.ruby.network.routers1.msg_count.Writeback_Control::3 30704 +system.ruby.network.routers1.msg_bytes.Control::2 245664 +system.ruby.network.routers1.msg_bytes.Data::2 2210688 +system.ruby.network.routers1.msg_bytes.Response_Data::4 2210976 +system.ruby.network.routers1.msg_bytes.Writeback_Control::3 245632 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 1894689 # Cumulative time (in ticks) in various power states +system.ruby.network.routers2.percent_links_utilized 8.103177 +system.ruby.network.routers2.msg_count.Control::2 30708 +system.ruby.network.routers2.msg_count.Data::2 30704 +system.ruby.network.routers2.msg_count.Response_Data::4 30708 +system.ruby.network.routers2.msg_count.Writeback_Control::3 30704 +system.ruby.network.routers2.msg_bytes.Control::2 245664 +system.ruby.network.routers2.msg_bytes.Data::2 2210688 +system.ruby.network.routers2.msg_bytes.Response_Data::4 2210976 +system.ruby.network.routers2.msg_bytes.Writeback_Control::3 245632 +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 1894689 # Cumulative time (in ticks) in various power states +system.ruby.network.msg_count.Control 92124 +system.ruby.network.msg_count.Data 92112 +system.ruby.network.msg_count.Response_Data 92124 +system.ruby.network.msg_count.Writeback_Control 92112 +system.ruby.network.msg_byte.Control 736992 +system.ruby.network.msg_byte.Data 6632064 +system.ruby.network.msg_byte.Response_Data 6632928 +system.ruby.network.msg_byte.Writeback_Control 736896 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 1894689 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.throttle0.link_utilization 8.103599 +system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 30708 +system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 30704 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 2210976 +system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 245632 +system.ruby.network.routers0.throttle1.link_utilization 8.102755 +system.ruby.network.routers0.throttle1.msg_count.Control::2 30708 +system.ruby.network.routers0.throttle1.msg_count.Data::2 30704 +system.ruby.network.routers0.throttle1.msg_bytes.Control::2 245664 +system.ruby.network.routers0.throttle1.msg_bytes.Data::2 2210688 +system.ruby.network.routers1.throttle0.link_utilization 8.102755 +system.ruby.network.routers1.throttle0.msg_count.Control::2 30708 +system.ruby.network.routers1.throttle0.msg_count.Data::2 30704 +system.ruby.network.routers1.throttle0.msg_bytes.Control::2 245664 +system.ruby.network.routers1.throttle0.msg_bytes.Data::2 2210688 +system.ruby.network.routers1.throttle1.link_utilization 8.103599 +system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 30708 +system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 30704 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 2210976 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 245632 +system.ruby.network.routers2.throttle0.link_utilization 8.103599 +system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 30708 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 30704 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 2210976 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 245632 +system.ruby.network.routers2.throttle1.link_utilization 8.102755 +system.ruby.network.routers2.throttle1.msg_count.Control::2 30708 +system.ruby.network.routers2.throttle1.msg_count.Data::2 30704 +system.ruby.network.routers2.throttle1.msg_bytes.Control::2 245664 +system.ruby.network.routers2.throttle1.msg_bytes.Data::2 2210688 +system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::samples 30708 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1 | 30708 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::total 30708 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::samples 30704 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2 | 30704 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::total 30704 # delay histogram for vnet_2 +system.ruby.LD.latency_hist_seqr::bucket_size 64 +system.ruby.LD.latency_hist_seqr::max_bucket 639 +system.ruby.LD.latency_hist_seqr::samples 22338 +system.ruby.LD.latency_hist_seqr::mean 24.611022 +system.ruby.LD.latency_hist_seqr::gmean 6.137176 +system.ruby.LD.latency_hist_seqr::stdev 34.013289 +system.ruby.LD.latency_hist_seqr | 18464 82.66% 82.66% | 3596 16.10% 98.76% | 178 0.80% 99.55% | 29 0.13% 99.68% | 33 0.15% 99.83% | 37 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% +system.ruby.LD.latency_hist_seqr::total 22338 +system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 +system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 +system.ruby.LD.hit_latency_hist_seqr::samples 11656 +system.ruby.LD.hit_latency_hist_seqr::mean 1 +system.ruby.LD.hit_latency_hist_seqr::gmean 1 +system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 11656 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::total 11656 +system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 +system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 +system.ruby.LD.miss_latency_hist_seqr::samples 10682 +system.ruby.LD.miss_latency_hist_seqr::mean 50.374930 +system.ruby.LD.miss_latency_hist_seqr::gmean 44.441140 +system.ruby.LD.miss_latency_hist_seqr::stdev 33.870397 +system.ruby.LD.miss_latency_hist_seqr | 6808 63.73% 63.73% | 3596 33.66% 97.40% | 178 1.67% 99.06% | 29 0.27% 99.34% | 33 0.31% 99.64% | 37 0.35% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% +system.ruby.LD.miss_latency_hist_seqr::total 10682 +system.ruby.ST.latency_hist_seqr::bucket_size 64 +system.ruby.ST.latency_hist_seqr::max_bucket 639 +system.ruby.ST.latency_hist_seqr::samples 19962 +system.ruby.ST.latency_hist_seqr::mean 13.531760 +system.ruby.ST.latency_hist_seqr::gmean 2.877811 +system.ruby.ST.latency_hist_seqr::stdev 27.544646 +system.ruby.ST.latency_hist_seqr | 18555 92.95% 92.95% | 1306 6.54% 99.49% | 62 0.31% 99.80% | 14 0.07% 99.87% | 5 0.03% 99.90% | 9 0.05% 99.94% | 0 0.00% 99.94% | 1 0.01% 99.95% | 0 0.00% 99.95% | 10 0.05% 100.00% +system.ruby.ST.latency_hist_seqr::total 19962 +system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 +system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 +system.ruby.ST.hit_latency_hist_seqr::samples 14232 +system.ruby.ST.hit_latency_hist_seqr::mean 1 +system.ruby.ST.hit_latency_hist_seqr::gmean 1 +system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 14232 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist_seqr::total 14232 +system.ruby.ST.miss_latency_hist_seqr::bucket_size 64 +system.ruby.ST.miss_latency_hist_seqr::max_bucket 639 +system.ruby.ST.miss_latency_hist_seqr::samples 5730 +system.ruby.ST.miss_latency_hist_seqr::mean 44.657766 +system.ruby.ST.miss_latency_hist_seqr::gmean 39.743598 +system.ruby.ST.miss_latency_hist_seqr::stdev 35.837997 +system.ruby.ST.miss_latency_hist_seqr | 4323 75.45% 75.45% | 1306 22.79% 98.24% | 62 1.08% 99.32% | 14 0.24% 99.56% | 5 0.09% 99.65% | 9 0.16% 99.81% | 0 0.00% 99.81% | 1 0.02% 99.83% | 0 0.00% 99.83% | 10 0.17% 100.00% +system.ruby.ST.miss_latency_hist_seqr::total 5730 +system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.latency_hist_seqr::samples 111210 +system.ruby.IFETCH.latency_hist_seqr::mean 8.284300 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.655983 +system.ruby.IFETCH.latency_hist_seqr::stdev 23.277030 +system.ruby.IFETCH.latency_hist_seqr | 103743 93.29% 93.29% | 6908 6.21% 99.50% | 382 0.34% 99.84% | 75 0.07% 99.91% | 51 0.05% 99.95% | 37 0.03% 99.99% | 7 0.01% 99.99% | 2 0.00% 100.00% | 1 0.00% 100.00% | 4 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::total 111210 +system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 +system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 +system.ruby.IFETCH.hit_latency_hist_seqr::samples 96914 +system.ruby.IFETCH.hit_latency_hist_seqr::mean 1 +system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 +system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 96914 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist_seqr::total 96914 +system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.miss_latency_hist_seqr::samples 14296 +system.ruby.IFETCH.miss_latency_hist_seqr::mean 57.665291 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 50.589228 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 37.639680 +system.ruby.IFETCH.miss_latency_hist_seqr | 6829 47.77% 47.77% | 6908 48.32% 96.09% | 382 2.67% 98.76% | 75 0.52% 99.29% | 51 0.36% 99.64% | 37 0.26% 99.90% | 7 0.05% 99.95% | 2 0.01% 99.97% | 1 0.01% 99.97% | 4 0.03% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::total 14296 +system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 +system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 +system.ruby.Directory.miss_mach_latency_hist_seqr::samples 30708 +system.ruby.Directory.miss_mach_latency_hist_seqr::mean 52.702130 +system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 46.230601 +system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 36.381667 +system.ruby.Directory.miss_mach_latency_hist_seqr | 17960 58.49% 58.49% | 11810 38.46% 96.95% | 622 2.03% 98.97% | 118 0.38% 99.36% | 89 0.29% 99.65% | 83 0.27% 99.92% | 7 0.02% 99.94% | 3 0.01% 99.95% | 1 0.00% 99.95% | 15 0.05% 100.00% +system.ruby.Directory.miss_mach_latency_hist_seqr::total 30708 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::total 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total 1 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size 8 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 79 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean 75 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 75.000000 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 10682 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 50.374930 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 44.441140 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 33.870397 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 6808 63.73% 63.73% | 3596 33.66% 97.40% | 178 1.67% 99.06% | 29 0.27% 99.34% | 33 0.31% 99.64% | 37 0.35% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 10682 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 5730 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 44.657766 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 39.743598 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 35.837997 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 4323 75.45% 75.45% | 1306 22.79% 98.24% | 62 1.08% 99.32% | 14 0.24% 99.56% | 5 0.09% 99.65% | 9 0.16% 99.81% | 0 0.00% 99.81% | 1 0.02% 99.83% | 0 0.00% 99.83% | 10 0.17% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 5730 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 14296 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 57.665291 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 50.589228 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 37.639680 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 6829 47.77% 47.77% | 6908 48.32% 96.09% | 382 2.67% 98.76% | 75 0.52% 99.29% | 51 0.36% 99.64% | 37 0.26% 99.90% | 7 0.05% 99.95% | 2 0.01% 99.97% | 1 0.01% 99.97% | 4 0.03% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 14296 +system.ruby.Directory_Controller.GETX 30708 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 30704 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 30708 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 30704 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 30708 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 30704 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 30708 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 30704 0.00% 0.00% +system.ruby.L1Cache_Controller.Load 22338 0.00% 0.00% +system.ruby.L1Cache_Controller.Ifetch 111210 0.00% 0.00% +system.ruby.L1Cache_Controller.Store 19962 0.00% 0.00% +system.ruby.L1Cache_Controller.Data 30708 0.00% 0.00% +system.ruby.L1Cache_Controller.Replacement 30704 0.00% 0.00% +system.ruby.L1Cache_Controller.Writeback_Ack 30704 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Load 10682 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Ifetch 14296 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Store 5730 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Load 11656 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Ifetch 96914 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Store 14232 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Replacement 30704 0.00% 0.00% +system.ruby.L1Cache_Controller.MI.Writeback_Ack 30704 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Data 24978 0.00% 0.00% +system.ruby.L1Cache_Controller.IM.Data 5730 0.00% 0.00% + +---------- End Simulation Statistics ---------- diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing/config.ini --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing/config.ini Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,374 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=TimingSimpleCPU +children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +hit_latency=2 +is_read_only=false +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=262144 + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.icache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +hit_latency=2 +is_read_only=true +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tags=system.cpu.icache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=131072 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.l2cache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +hit_latency=20 +is_read_only=false +max_miss_count=0 +mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +hit_latency=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=2097152 + +[system.cpu.toL2Bus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=0 +frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null +response_latency=1 +snoop_filter=system.cpu.toL2Bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64m/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +eventq_index=0 +in_addr_map=true +kvm_map=true +latency=30000 +latency_var=0 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +range=0:134217727:0:0:0:0 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing/config.json --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing/config.json Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,502 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.l2cache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "physmem": { + "range": "0:134217727:0:0:0:0", + "latency": 30000, + "name": "physmem", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "kvm_map": true, + "clk_domain": "system.clk_domain", + "power_model": null, + "latency_var": 0, + "bandwidth": "73.000000", + "conf_table_reported": true, + "cxx_class": "SimpleMemory", + "p_state_clk_gate_max": 1000000000000, + "path": "system.physmem", + "null": false, + "type": "SimpleMemory", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "in_addr_map": true + }, + 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"Cache", + "size": 131072, + "tags": { + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.icache.tags", + "hit_latency": 2, + "block_size": 64, + "type": "LRU", + "size": 131072 + }, + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[0]", + "role": "MASTER" + }, + "type": "Cache", + "writeback_clean": true, + "p_state_clk_gate_min": 1000, + "hit_latency": 2, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": true, + "prefetch_on_access": false, + "path": "system.cpu.icache", + "mshrs": 4, + "name": "icache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "TimingSimpleCPU", + "max_loads_all_threads": 0, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "cpu_id": 0, + "checker": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "toL2Bus": { + "point_of_coherency": false, + "system": "system", + "response_latency": 1, + "cxx_class": "CoherentXBar", + "forward_latency": 0, + "clk_domain": "system.cpu_clk_domain", + "width": 32, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.cpu.l2cache.cpu_side" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 1, + "slave": { + "peer": [ + "system.cpu.icache.mem_side", + "system.cpu.dcache.mem_side" + ], + "role": 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"writeback_clean": false, + "p_state_clk_gate_min": 1000, + "hit_latency": 20, + "tgts_per_mshr": 12, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.l2cache", + "mshrs": 20, + "name": "l2cache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 8 + }, + "path": "system.cpu", + "max_loads_any_thread": 0, + "switched_out": false, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64m/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "progress_interval": 0, + "branchPred": null, + "dcache": { + "cpu_side": { + "peer": "system.cpu.dcache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 262144, + "tags": { + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.dcache.tags", + "hit_latency": 2, + "block_size": 64, + "type": "LRU", + "size": 262144 + }, + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[1]", + "role": "MASTER" + }, + "type": "Cache", + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "hit_latency": 2, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.dcache", + "mshrs": 4, + "name": "dcache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing/simerr --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing/simerr Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,3 @@ +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing/simout --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing/simout Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,51 @@ +Redirecting stdout to build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64m/simple-timing/simout +Redirecting stderr to build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64m/simple-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 2 2016 20:34:02 +gem5 started Nov 3 2016 18:41:54 +gem5 executing on ubuntu1604, pid 21473 +command line: /home/ar4jc/gem5/build/RISCV/gem5.debug -d build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64m/simple-timing -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64m/simple-timing + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +mul: PASS +mul, overflow: PASS +mulh: PASS +mulh, negative: PASS +mulh, all bits set: PASS +mulhsu, all bits set: PASS +mulhsu: PASS +mulhu: PASS +mulhu, all bits set: PASS +div: PASS +div/0: PASS +div, overflow: PASS +divu: PASS +divu/0: PASS +divu, "overflow": PASS +rem: PASS +rem/0: PASS +rem, overflow: PASS +remu: PASS +remu/0: PASS +remu, "overflow": PASS +mulw, truncate: PASS +mulw, overflow: PASS +divw, truncate: PASS +divw/0: PASS +divw, overflow: PASS +divuw, truncate: PASS +divuw/0: PASS +divuw, "overflow": PASS +divuw, sign extend: PASS +remw, truncate: PASS +remw/0: PASS +remw, overflow: PASS +remuw, truncate: PASS +remuw/0: PASS +remuw, "overflow": PASS +remuw, sign extend: PASS +Exiting @ tick 206567500 because target called exit() diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing/stats.txt --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing/stats.txt Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,521 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000207 # Number of seconds simulated +sim_ticks 206567500 # Number of ticks simulated +final_tick 206567500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 51015 # Simulator instruction rate (inst/s) +host_op_rate 51015 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 94796472 # Simulator tick rate (ticks/s) +host_mem_usage 275236 # Number of bytes of host memory used +host_seconds 2.18 # Real time elapsed on the host +sim_insts 111163 # Number of instructions simulated +sim_ops 111163 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 206567500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 37888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 16768 # Number of bytes read from this memory +system.physmem.bytes_read::total 54656 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 37888 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 37888 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 592 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 262 # Number of read requests responded to by this memory +system.physmem.num_reads::total 854 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 183417043 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 81174435 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 264591477 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 183417043 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 183417043 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 183417043 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 81174435 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 264591477 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 206567500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 46 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 206567500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 413135 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 111163 # Number of instructions committed +system.cpu.committedOps 111163 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 111164 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 8511 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 17403 # number of instructions that are conditional controls +system.cpu.num_int_insts 111164 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 148887 # number of times the integer registers were read +system.cpu.num_int_register_writes 73798 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 42301 # number of memory refs +system.cpu.num_load_insts 22338 # Number of load instructions +system.cpu.num_store_insts 19963 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 413135 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 25914 # Number of branches fetched +system.cpu.op_class::No_OpClass 46 0.04% 0.04% # Class of executed instruction +system.cpu.op_class::IntAlu 68715 61.79% 61.83% # Class of executed instruction +system.cpu.op_class::IntMult 122 0.11% 61.94% # Class of executed instruction +system.cpu.op_class::IntDiv 26 0.02% 61.96% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::MemRead 22338 20.09% 82.05% # Class of executed instruction +system.cpu.op_class::MemWrite 19963 17.95% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 111210 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 206567500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 217.180747 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42038 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 262 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 160.450382 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 217.180747 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.053023 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.053023 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 262 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 226 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.063965 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 84862 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 84862 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 206567500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 22275 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22275 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 19763 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 19763 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 42038 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42038 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42038 # number of overall hits +system.cpu.dcache.overall_hits::total 42038 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 63 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 63 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 199 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 199 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 262 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 262 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 262 # number of overall misses +system.cpu.dcache.overall_misses::total 262 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3969000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3969000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 12537000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 12537000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 16506000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16506000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16506000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16506000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22338 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22338 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19962 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19962 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 42300 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42300 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42300 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42300 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002820 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002820 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009969 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.009969 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.006194 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.006194 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.006194 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.006194 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 63 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 63 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 199 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 199 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 262 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 262 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 262 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 262 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3906000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3906000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12338000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12338000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16244000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16244000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16244000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16244000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002820 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002820 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009969 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009969 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006194 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006194 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006194 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006194 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 206567500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 28 # number of replacements +system.cpu.icache.tags.tagsinuse 299.272457 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 110610 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 601 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 184.043261 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 299.272457 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.146129 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.146129 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 573 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 218 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 317 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.279785 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 223023 # Number of tag accesses +system.cpu.icache.tags.data_accesses 223023 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 206567500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 110610 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 110610 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 110610 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 110610 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 110610 # number of overall hits +system.cpu.icache.overall_hits::total 110610 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 601 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 601 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 601 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 601 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 601 # number of overall misses +system.cpu.icache.overall_misses::total 601 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 37414500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 37414500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 37414500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 37414500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 37414500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 37414500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 111211 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 111211 # 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average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 62253.743760 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 62253.743760 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 62253.743760 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 62253.743760 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 62253.743760 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 28 # 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Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 217.194065 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009357 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.006628 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.015986 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 854 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 254 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 560 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.026062 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 7982 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 7982 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 206567500 # 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average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 199 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 199 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 592 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 592 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 63 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 63 # 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number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3181500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 29897000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13231000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 43128000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 29897000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13231000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 43128000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.985025 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.985025 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.985025 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.989571 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.985025 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.989571 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50501.689189 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50501.689189 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50501.689189 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.170960 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50501.689189 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.170960 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 891 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 28 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 206567500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 664 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 28 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 199 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 199 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 601 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 63 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1230 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 524 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1754 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40256 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16768 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 57024 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 863 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 863 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 863 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 473500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 901500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 393000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 854 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 206567500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 655 # Transaction distribution +system.membus.trans_dist::ReadExReq 199 # Transaction distribution +system.membus.trans_dist::ReadExResp 199 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 655 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1708 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1708 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 54656 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 54656 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 854 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 854 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 854 # Request fanout histogram +system.membus.reqLayer0.occupancy 855000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 4270000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 2.1 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff -r 8aec19bd88f8 -r ea40d2a41efb tests/test-progs/hello/bin/riscv/linux/hello Binary file tests/test-progs/hello/bin/riscv/linux/hello has changed diff -r 8aec19bd88f8 -r ea40d2a41efb tests/test-progs/insttest/src/riscv/Makefile --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/test-progs/insttest/src/riscv/Makefile Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,51 @@ +# Copyright (c) 2016 The University of Virginia +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Alec Roelke + +CXX=riscv64-unknown-elf-g++ +CFLAGS=--std=c++11 -O3 -static + +TARGETS=rv64i rv64m rv64a rv64f rv64d +PREFIX=../../bin/riscv/linux +BIN=insttest + +all: $(TARGETS) + +$(TARGETS): + -mkdir -p $(PREFIX)-$@ + $(CXX) $< $(CFLAGS) -o $(PREFIX)-$@/$(BIN) + +rv64i: rv64i.cpp +rv64m: rv64m.cpp +rv64a: rv64a.cpp +rv64f: rv64f.cpp +rv64d: rv64d.cpp + +clean: + -rm $(PREFIX)-*/$(BIN) + +.PHONY: all clean diff -r 8aec19bd88f8 -r ea40d2a41efb tests/test-progs/insttest/src/riscv/insttest.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/test-progs/insttest/src/riscv/insttest.h Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2016 The University of Virginia + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Alec Roelke + */ + +#pragma once + +#include +#include +#include +#include +#include + +#define IOP(inst, rd, rs1, imm) \ + asm volatile(inst " %0,%1,%2" : "=r" (rd) : "r" (rs1), "i" (imm)) + +#define ROP(inst, rd, rs1, rs2) \ + asm volatile(inst " %0,%1,%2" : "=r" (rd) : "r" (rs1), "r" (rs2)) + +#define FROP(inst, fd, fs1, fs2) \ + asm volatile(inst " %0,%1,%2" : "=f" (fd) : "f" (fs1), "f" (fs2)) + +#define FR4OP(inst, fd, fs1, fs2, fs3) \ + asm volatile(inst " %0,%1,%2,%3" \ + : "=f" (fd) \ + : "f" (fs1), "f" (fs2), "f" (fs3)) + +template std::ostream& +operator<<(std::ostream& os, const std::pair& p) +{ + return os << '(' << p.first << ", " << p.second << ')'; +} + +namespace insttest +{ + +template void +expect(const T& expected, std::function func, + const std::string& test) +{ + using namespace std; + + T result = func(); + cout << test << ": "; + if (result == expected) { + cout << "PASS" << endl; + } else { + cout << "\033[1;31mFAIL\033[0m (expected " << expected << "; found " << + result << ")" << endl; + exit(1); + } +} + +} // namespace insttest diff -r 8aec19bd88f8 -r ea40d2a41efb tests/test-progs/insttest/src/riscv/rv64a.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/test-progs/insttest/src/riscv/rv64a.h Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,299 @@ +/* + * Copyright (c) 2016 The University of Virginia + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Alec Roelke + */ + +#pragma once + +#include +#include + +#include "insttest.h" + +namespace A +{ + +inline int64_t +lr_w(int32_t& mem) +{ + int64_t r = 0; + uint64_t addr = (uint64_t)&mem; + asm volatile("lr.w %0,(%1)" : "=r" (r) : "r" (addr) : "memory"); + return r; +} + +inline std::pair +sc_w(int64_t rs2, int32_t& mem) +{ + uint64_t addr = (uint64_t)&mem; + uint64_t rd = -1; + asm volatile("sc.w %0,%2,(%1)" + : "=r" (rd) + : "r" (addr), "r" (rs2) + : "memory"); + return {mem, rd}; +} + +inline std::pair +amoswap_w(int64_t mem, int64_t rs2) +{ + int64_t rd = 0; + uint64_t addr = (uint64_t)&mem; + asm volatile("amoswap.w %0,%2,(%1)" + : "=r" (rd) + : "r" (addr), "r" (rs2) + : "memory"); + return {mem, rd}; +} + +inline std::pair +amoadd_w(int64_t mem, int64_t rs2) +{ + int64_t rd = 0; + uint64_t addr = (uint64_t)&mem; + asm volatile("amoadd.w %0,%2,(%1)" + : "=r" (rd) + : "r" (addr), "r" (rs2) + : "memory"); + return {mem, rd}; +} + +inline std::pair +amoxor_w(uint64_t mem, uint64_t rs2) +{ + uint64_t rd = 0; + uint64_t addr = (uint64_t)&mem; + asm volatile("amoxor.w %0,%2,(%1)" + : "=r" (rd) + : "r" (addr), "r" (rs2) + : "memory"); + return {mem, rd}; +} + +inline std::pair +amoand_w(uint64_t mem, uint64_t rs2) +{ + uint64_t rd = 0; + uint64_t addr = (uint64_t)&mem; + asm volatile("amoand.w %0,%2,(%1)" + : "=r" (rd) + : "r" (addr), "r" (rs2) + : "memory"); + return {mem, rd}; +} + +inline std::pair +amoor_w(uint64_t mem, uint64_t rs2) +{ + uint64_t rd = 0; + uint64_t addr = (uint64_t)&mem; + asm volatile("amoor.w %0,%2,(%1)" + : "=r" (rd) + : "r" (addr), "r" (rs2) + : "memory"); + return {mem, rd}; +} + +inline std::pair +amomin_w(int64_t mem, int64_t rs2) +{ + int64_t rd = 0; + uint64_t addr = (uint64_t)&mem; + asm volatile("amomin.w %0,%2,(%1)" + : "=r" (rd) + : "r" (addr), "r" (rs2) + : "memory"); + return {mem, rd}; +} + +inline std::pair +amomax_w(int64_t mem, int64_t rs2) +{ + int64_t rd = 0; + uint64_t addr = (uint64_t)&mem; + asm volatile("amomax.w %0,%2,(%1)" + : "=r" (rd) + : "r" (addr), "r" (rs2) + : "memory"); + return {mem, rd}; +} + +inline std::pair +amominu_w(uint64_t mem, uint64_t rs2) +{ + uint64_t rd = 0; + uint64_t addr = (uint64_t)&mem; + asm volatile("amominu.w %0,%2,(%1)" + : "=r" (rd) + : "r" (addr), "r" (rs2) + : "memory"); + return {mem, rd}; +} + +inline std::pair +amomaxu_w(uint64_t mem, uint64_t rs2) +{ + uint64_t rd = 0; + uint64_t addr = (uint64_t)&mem; + asm volatile("amomaxu.w %0,%2,(%1)" + : "=r" (rd) + : "r" (addr), "r" (rs2) + : "memory"); + return {mem, rd}; +} + +inline int64_t +lr_d(int64_t& mem) +{ + int64_t r = 0; + uint64_t addr = (uint64_t)&mem; + asm volatile("lr.d %0,(%1)" : "=r" (r) : "r" (addr) : "memory"); + return r; +} + +inline std::pair +sc_d(int64_t rs2, int64_t& mem) +{ + uint64_t addr = (uint64_t)&mem; + uint64_t rd = -1; + asm volatile("sc.d %0,%2,(%1)" + : "=r" (rd) + : "r" (addr), "r" (rs2) + : "memory"); + return {mem, rd}; +} + +inline std::pair +amoswap_d(int64_t mem, int64_t rs2) +{ + int64_t rd = 0; + uint64_t addr = (uint64_t)&mem; + asm volatile("amoswap.d %0,%2,(%1)" + : "=r" (rd) + : "r" (addr), "r" (rs2) + : "memory"); + return {mem, rd}; +} + +inline std::pair +amoadd_d(int64_t mem, int64_t rs2) +{ + int64_t rd = 0; + uint64_t addr = (uint64_t)&mem; + asm volatile("amoadd.d %0,%2,(%1)" + : "=r" (rd) + : "r" (addr), "r" (rs2) + : "memory"); + return {mem, rd}; +} + +inline std::pair +amoxor_d(uint64_t mem, uint64_t rs2) +{ + uint64_t rd = 0; + uint64_t addr = (uint64_t)&mem; + asm volatile("amoxor.d %0,%2,(%1)" + : "=r" (rd) + : "r" (addr), "r" (rs2) + : "memory"); + return {mem, rd}; +} + +inline std::pair +amoand_d(uint64_t mem, uint64_t rs2) +{ + uint64_t rd = 0; + uint64_t addr = (uint64_t)&mem; + asm volatile("amoand.d %0,%2,(%1)" + : "=r" (rd) + : "r" (addr), "r" (rs2) + : "memory"); + return {mem, rd}; +} + +inline std::pair +amoor_d(uint64_t mem, uint64_t rs2) +{ + uint64_t rd = 0; + uint64_t addr = (uint64_t)&mem; + asm volatile("amoor.d %0,%2,(%1)" + : "=r" (rd) + : "r" (addr), "r" (rs2) + : "memory"); + return {mem, rd}; +} + +inline std::pair +amomin_d(int64_t mem, int64_t rs2) +{ + int64_t rd = 0; + uint64_t addr = (uint64_t)&mem; + asm volatile("amomin.d %0,%2,(%1)" + : "=r" (rd) + : "r" (addr), "r" (rs2) + : "memory"); + return {mem, rd}; +} + +inline std::pair +amomax_d(int64_t mem, int64_t rs2) +{ + int64_t rd = 0; + uint64_t addr = (uint64_t)&mem; + asm volatile("amomax.d %0,%2,(%1)" + : "=r" (rd) + : "r" (addr), "r" (rs2) + : "memory"); + return {mem, rd}; +} + +inline std::pair +amominu_d(uint64_t mem, uint64_t rs2) +{ + uint64_t rd = 0; + uint64_t addr = (uint64_t)&mem; + asm volatile("amominu.d %0,%2,(%1)" + : "=r" (rd) + : "r" (addr), "r" (rs2) + : "memory"); + return {mem, rd}; +} + +inline std::pair +amomaxu_d(uint64_t mem, uint64_t rs2) +{ + uint64_t rd = 0; + uint64_t addr = (uint64_t)&mem; + asm volatile("amomaxu.d %0,%2,(%1)" + : "=r" (rd) + : "r" (addr), "r" (rs2) + : "memory"); + return {mem, rd}; +} + +} // namespace A diff -r 8aec19bd88f8 -r ea40d2a41efb tests/test-progs/insttest/src/riscv/rv64a.cpp --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/test-progs/insttest/src/riscv/rv64a.cpp Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,192 @@ +/* + * Copyright (c) 2016 The University of Virginia + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Alec Roelke + */ + +#include +#include + +#include "insttest.h" +#include "rv64a.h" + +int main() +{ + using namespace std; + using namespace insttest; + + // Memory (LR.W, SC.W) + expect>({-1, 0}, []{ + int32_t mem = -1; + int64_t rs2 = 256; + int64_t rd = A::lr_w(mem); + pair result = A::sc_w(rs2, mem); + return pair(rd, result.second); + }, "lr.w/sc.w"); + expect>({true, 200}, []{ + int32_t mem = 200; + pair result = A::sc_w(50, mem); + return pair(result.second == 1, mem); + }, "sc.w, no preceding lr.d"); + + // AMOSWAP.W + expect>({65535, 255}, + []{return A::amoswap_w(255, 65535);}, "amoswap.w"); + expect>({0xFFFFFFFF, -1}, + []{return A::amoswap_w(0xFFFFFFFF, 0xFFFFFFFF);}, + "amoswap.w, sign extend"); + expect>({0x0000000180000000LL, -1}, + []{return A::amoswap_w(0x00000001FFFFFFFFLL, + 0x7FFFFFFF80000000LL);}, + "amoswap.w, truncate"); + + // AMOADD.W + expect>({256, 255}, + []{return A::amoadd_w(255, 1);}, "amoadd.w"); + expect>({0, -1}, + []{return A::amoadd_w(0xFFFFFFFF, 1);}, + "amoadd.w, truncate/overflow"); + expect>({0xFFFFFFFF, 0x7FFFFFFF}, + []{return A::amoadd_w(0x7FFFFFFF, 0x80000000);}, + "amoadd.w, sign extend"); + + // AMOXOR.W + expect>({0xFFFFFFFFAAAAAAAALL, -1}, + []{return A::amoxor_w(-1, 0x5555555555555555LL);}, + "amoxor.w, truncate"); + expect>({0x80000000, -1}, + []{return A::amoxor_w(0xFFFFFFFF, 0x7FFFFFFF);}, + "amoxor.w, sign extend"); + + // AMOAND.W + expect>({0xFFFFFFFF00000000LL, -1}, + []{return A::amoand_w(-1, 0);}, "amoand.w, truncate"); + expect>({0x0000000080000000LL, -1}, + []{return A::amoand_w(0xFFFFFFFF,numeric_limits::min());}, + "amoand.w, sign extend"); + + // AMOOR.W + expect>({0x00000000FFFFFFFFLL, 0}, + []{return A::amoor_w(0, -1);}, "amoor.w, truncate"); + expect>({0x0000000080000000LL, 0}, + []{return A::amoor_w(0, numeric_limits::min());}, + "amoor.w, sign extend"); + + // AMOMIN.W + expect>({0x7FFFFFFF00000001LL, 1}, + []{return A::amomin_w(0x7FFFFFFF00000001LL, 0xFFFFFFFF000000FF);}, + "amomin.w, truncate"); + expect>({0x00000000FFFFFFFELL, -1}, + []{return A::amomin_w(0xFFFFFFFF, -2);}, "amomin.w, sign extend"); + + // AMOMAX.W + expect>({0x70000000000000FFLL, 1}, + []{return A::amomax_w(0x7000000000000001LL,0x7FFFFFFF000000FFLL);}, + "amomax.w, truncate"); + expect>({-1, numeric_limits::min()}, + []{return A::amomax_w(numeric_limits::min(), -1);}, + "amomax.w, sign extend"); + + // AMOMINU.W + expect>({0x0FFFFFFF000000FFLL, -1}, + []{return A::amominu_w(0x0FFFFFFFFFFFFFFFLL, 0xFFFFFFFF000000FF);}, + "amominu.w, truncate"); + expect>({0x0000000080000000LL, -1}, + []{return A::amominu_w(0x00000000FFFFFFFFLL, 0x80000000);}, + "amominu.w, sign extend"); + + // AMOMAXU.W + expect>({-1, 0}, + []{return A::amomaxu_w(0xFFFFFFFF00000000LL, + 0x00000000FFFFFFFFLL);}, + "amomaxu.w, truncate"); + expect>( + {0xFFFFFFFF, numeric_limits::min()}, + []{return A::amomaxu_w(0x80000000, 0xFFFFFFFF);}, + "amomaxu.w, sign extend"); + + // Memory (LR.D, SC.D) + expect>({-1, 0}, []{ + int64_t mem = -1; + int64_t rs2 = 256; + int64_t rd = A::lr_d(mem); + pair result = A::sc_d(rs2, mem); + return pair(rd, result.second); + }, "lr.d/sc.d"); + expect>({true, 200}, []{ + int64_t mem = 200; + pair result = A::sc_d(50, mem); + return pair(result.second == 1, mem); + }, "sc.d, no preceding lr.d"); + + // AMOSWAP.D + expect>({1, -1}, []{return A::amoswap_d(-1, 1);}, + "amoswap.d"); + + // AMOADD.D + expect>({0x7000000000000000LL,0x0FFFFFFFFFFFFFFFLL}, + []{return A::amoadd_d(0x0FFFFFFFFFFFFFFFLL,0x6000000000000001LL);}, + "amoadd.d"); + expect>({0, 0x7FFFFFFFFFFFFFFFLL}, + []{return A::amoadd_d(0x7FFFFFFFFFFFFFFFLL,0x8000000000000001LL);}, + "amoadd.d, overflow"); + + // AMOXOR.D + expect>({-1, 0xAAAAAAAAAAAAAAAALL}, + []{return A::amoxor_d(0xAAAAAAAAAAAAAAAALL,0x5555555555555555LL);}, + "amoxor.d (1)"); + expect>({0, 0xAAAAAAAAAAAAAAAALL}, + []{return A::amoxor_d(0xAAAAAAAAAAAAAAAALL,0xAAAAAAAAAAAAAAAALL);}, + "amoxor.d (0)"); + + // AMOAND.D + expect>({0xAAAAAAAAAAAAAAAALL, -1}, + []{return A::amoand_d(-1, 0xAAAAAAAAAAAAAAAALL);}, "amoand.d"); + + // AMOOR.D + expect>({-1, 0xAAAAAAAAAAAAAAAALL}, + []{return A::amoor_d(0xAAAAAAAAAAAAAAAALL, 0x5555555555555555LL);}, + "amoor.d"); + + // AMOMIN.D + expect>({-1, -1}, + []{return A::amomin_d(-1, 0);}, "amomin.d"); + + // AMOMAX.D + expect>({0, -1}, []{return A::amomax_d(-1, 0);}, + "amomax.d"); + + // AMOMINU.D + expect>({0, -1}, + []{return A::amominu_d(-1, 0);}, "amominu.d"); + + // AMOMAXU.D + expect>({-1, -1}, []{return A::amomaxu_d(-1, 0);}, + "amomaxu.d"); + + return 0; +} diff -r 8aec19bd88f8 -r ea40d2a41efb tests/test-progs/insttest/src/riscv/rv64d.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/test-progs/insttest/src/riscv/rv64d.h Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,323 @@ +/* + * Copyright (c) 2016 The University of Virginia + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Alec Roelke + */ + +#pragma once + +#include +#include + +#include "insttest.h" + +namespace D +{ + +constexpr inline uint64_t +bits(double d) +{ + return reinterpret_cast(d); +} + +constexpr inline double +number(uint64_t b) +{ + return reinterpret_cast(b); +} + +inline bool +isquietnan(double f) +{ + return std::isnan(f) && (bits(f)&0x0008000000000000ULL) != 0; +} + +inline bool +issignalingnan(double f) +{ + return std::isnan(f) && (bits(f)&0x0008000000000000ULL) == 0; +} + +inline double +load(double mem) +{ + double fd = std::numeric_limits::signaling_NaN(); + asm volatile("fld %0,%1" + : "=f" (fd) + : "m" (mem)); + return fd; +} + +inline double +store(double fs) +{ + double mem = std::numeric_limits::signaling_NaN(); + asm volatile("fsd %1,%0" : "=m" (mem) : "f" (fs)); + return mem; +} + +inline double +fmadd_d(double fs1, double fs2, double fs3) +{ + double fd = std::numeric_limits::signaling_NaN(); + FR4OP("fmadd.d", fd, fs1, fs2, fs3); + return fd; +} + +inline double +fmsub_d(double fs1, double fs2, double fs3) +{ + double fd = std::numeric_limits::signaling_NaN(); + FR4OP("fmsub.d", fd, fs1, fs2, fs3); + return fd; +} + +inline double +fnmsub_d(double fs1, double fs2, double fs3) +{ + double fd = std::numeric_limits::signaling_NaN(); + FR4OP("fnmsub.d", fd, fs1, fs2, fs3); + return fd; +} + +inline double +fnmadd_d(double fs1, double fs2, double fs3) +{ + double fd = std::numeric_limits::signaling_NaN(); + FR4OP("fnmadd.d", fd, fs1, fs2, fs3); + return fd; +} + +inline double +fadd_d(double fs1, double fs2) +{ + double fd = std::numeric_limits::signaling_NaN(); + FROP("fadd.d", fd, fs1, fs2); + return fd; +} + +inline double +fsub_d(double fs1, double fs2) +{ + double fd = std::numeric_limits::signaling_NaN(); + FROP("fsub.d", fd, fs1, fs2); + return fd; +} + +inline double +fmul_d(double fs1, double fs2) +{ + double fd = std::numeric_limits::signaling_NaN(); + FROP("fmul.d", fd, fs1, fs2); + return fd; +} + +inline double +fdiv_d(double fs1, double fs2) +{ + double fd = std::numeric_limits::signaling_NaN(); + FROP("fdiv.d", fd, fs1, fs2); + return fd; +} + +inline double +fsqrt_d(double fs1) +{ + double fd = std::numeric_limits::signaling_NaN(); + asm volatile("fsqrt.d %0,%1" : "=f" (fd) : "f" (fs1)); + return fd; +} + +inline double +fsgnj_d(double fs1, double fs2) +{ + double fd = std::numeric_limits::signaling_NaN(); + FROP("fsgnj.d", fd, fs1, fs2); + return fd; +} + +inline double +fsgnjn_d(double fs1, double fs2) +{ + double fd = std::numeric_limits::signaling_NaN(); + FROP("fsgnjn.d", fd, fs1, fs2); + return fd; +} + +inline double +fsgnjx_d(double fs1, double fs2) +{ + double fd = std::numeric_limits::signaling_NaN(); + FROP("fsgnjx.d", fd, fs1, fs2); + return fd; +} + +inline double +fmin_d(double fs1, double fs2) +{ + double fd = std::numeric_limits::signaling_NaN(); + FROP("fmin.d", fd, fs1, fs2); + return fd; +} + +inline double +fmax_d(double fs1, double fs2) +{ + double fd = std::numeric_limits::signaling_NaN(); + FROP("fmax.d", fd, fs1, fs2); + return fd; +} + +inline float +fcvt_s_d(double fs1) +{ + float fd = std::numeric_limits::signaling_NaN(); + asm volatile("fcvt.s.d %0,%1" : "=f" (fd) : "f" (fs1)); + return fd; +} + +inline double +fcvt_d_s(float fs1) +{ + double fd = std::numeric_limits::signaling_NaN(); + asm volatile("fcvt.d.s %0,%1" : "=f" (fd) : "f" (fs1)); + return fd; +} + +inline bool +feq_d(double fs1, double fs2) +{ + bool rd = false; + asm volatile("feq.d %0,%1,%2" : "=r" (rd) : "f" (fs1), "f" (fs2)); + return rd; +} + +inline bool +flt_d(double fs1, double fs2) +{ + bool rd = false; + asm volatile("flt.d %0,%1,%2" : "=r" (rd) : "f" (fs1), "f" (fs2)); + return rd; +} + +inline bool +fle_d(double fs1, double fs2) +{ + bool rd = false; + asm volatile("fle.d %0,%1,%2" : "=r" (rd) : "f" (fs1), "f" (fs2)); + return rd; +} + +inline uint64_t +fclass_d(double fs1) +{ + uint64_t rd = -1; + asm volatile("fclass.d %0,%1" : "=r" (rd) : "f" (fs1)); + return rd; +} + +inline int64_t +fcvt_w_d(double fs1) +{ + int64_t rd = 0; + asm volatile("fcvt.w.d %0,%1" : "=r" (rd) : "f" (fs1)); + return rd; +} + +inline uint64_t +fcvt_wu_d(double fs1) +{ + uint64_t rd = 0; + asm volatile("fcvt.wu.d %0,%1" : "=r" (rd) : "f" (fs1)); + return rd; +} + +inline float +fcvt_d_w(int64_t rs1) +{ + double fd = std::numeric_limits::signaling_NaN(); + asm volatile("fcvt.d.w %0,%1" : "=f" (fd) : "r" (rs1)); + return fd; +} + +inline double +fcvt_d_wu(uint64_t rs1) +{ + double fd = std::numeric_limits::signaling_NaN(); + asm volatile("fcvt.d.wu %0,%1" : "=f" (fd) : "r" (rs1)); + return fd; +} + +inline int64_t +fcvt_l_d(double fs1) +{ + int64_t rd = 0; + asm volatile("fcvt.l.d %0,%1" : "=r" (rd) : "f" (fs1)); + return rd; +} + +inline uint64_t +fcvt_lu_d(double fs1) +{ + uint64_t rd = 0; + asm volatile("fcvt.lu.d %0,%1" : "=r" (rd) : "f" (fs1)); + return rd; +} + +inline uint64_t +fmv_x_d(double fs1) +{ + uint64_t rd = 0; + asm volatile("fmv.x.d %0,%1" : "=r" (rd) : "f" (fs1)); + return rd; +} + +inline double +fcvt_d_l(int64_t rs1) +{ + double fd = std::numeric_limits::signaling_NaN(); + asm volatile("fcvt.d.l %0,%1" : "=f" (fd) : "r" (rs1)); + return fd; +} + +inline double +fcvt_d_lu(uint64_t rs1) +{ + double fd = std::numeric_limits::signaling_NaN(); + asm volatile("fcvt.d.lu %0,%1" : "=f" (fd) : "r" (rs1)); + return fd; +} + +inline double +fmv_d_x(uint64_t rs1) +{ + double fd = std::numeric_limits::signaling_NaN(); + asm volatile("fmv.d.x %0,%1" : "=f" (fd) : "r" (rs1)); + return fd; +} + +} // namespace D diff -r 8aec19bd88f8 -r ea40d2a41efb tests/test-progs/insttest/src/riscv/rv64d.cpp --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/test-progs/insttest/src/riscv/rv64d.cpp Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,708 @@ +/* + * Copyright (c) 2016 The University of Virginia + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Alec Roelke + */ + +#include +#include + +#include "insttest.h" +#include "rv64d.h" +#include "rv64f.h" + +int main() +{ + using namespace std; + using namespace insttest; + + // Memory (FLD, FSD) + expect(3.1415926, []{return D::load(3.1415926);}, "fld"); + expect(1.61803398875, []{return D::store(1.61803398875);}, "fsd"); + + // FMADD.D + expect(D::number(0x4019FD5AED13B1CEULL), + []{return D::fmadd_d(3.1415926, 1.61803398875,1.41421356237);}, + "fmadd.d"); + expect(true, []{ + double fd = D::fmadd_d(numeric_limits::quiet_NaN(), 3.14, + 1.816); + return D::isquietnan(fd); + }, "fmadd.d, quiet NaN"); + expect(true, []{ + double fd = D::fmadd_d(3.14, + numeric_limits::signaling_NaN(), 1.816); + return D::isquietnan(fd); + }, "fmadd.d, signaling NaN"); + expect(numeric_limits::infinity(), + []{return D::fmadd_d(3.14, numeric_limits::infinity(),1.414);}, + "fmadd.d, infinity"); + expect(-numeric_limits::infinity(), + []{return D::fmadd_d(3.14,-numeric_limits::infinity(),1.414);}, + "fmadd.d, -infinity"); + + // FMSUB.D + expect(D::number(0x400d5A1773A85E43ULL), + []{return D::fmsub_d(3.1415926, 1.61803398875, 1.41421356237);}, + "fmsub.d"); + expect(true, []{ + double fd = D::fmsub_d(3.14, numeric_limits::quiet_NaN(), + 1.414); + return D::isquietnan(fd); + }, "fmsub.d, quiet NaN"); + expect(true, []{ + double fd = D::fmsub_d(3.14, 1.816, + numeric_limits::signaling_NaN()); + return D::isquietnan(fd); + }, "fmsub.d, signaling NaN"); + expect(numeric_limits::infinity(), + []{return D::fmsub_d(numeric_limits::infinity(), 1.816, + 1.414);}, + "fmsub.d, infinity"); + expect(-numeric_limits::infinity(), + []{return D::fmsub_d(3.14, -numeric_limits::infinity(), + 1.414);}, + "fmsub.d, -infinity"); + expect(-numeric_limits::infinity(), + []{return D::fmsub_d(3.14, 1.816, + numeric_limits::infinity());}, + "fmsub.d, subtract infinity"); + + // FNMSUB.D + expect(D::number(0xC00D5A1773A85E43ULL), + []{return D::fnmsub_d(3.1415926, 1.61803398875, 1.41421356237);}, + "fnmsub.d"); + expect(true, []{ + double fd = D::fnmsub_d(3.14, 1.816, + numeric_limits::quiet_NaN()); + return D::isquietnan(fd); + }, "fnmsub.d, quiet NaN"); + expect(true, []{ + double fd = D::fnmsub_d(numeric_limits::signaling_NaN(), + 1.816, 1.414); + return D::isquietnan(fd); + }, "fnmsub.d, signaling NaN"); + expect(-numeric_limits::infinity(), + []{return D::fnmsub_d(numeric_limits::infinity(), 1.816, + 1.414);}, + "fnmsub.d, infinity"); + expect(numeric_limits::infinity(), + []{return D::fnmsub_d(3.14, -numeric_limits::infinity(), + 1.414);}, + "fnmsub.d, -infinity"); + expect(numeric_limits::infinity(), + []{return D::fnmsub_d(3.14, 1.816, + numeric_limits::infinity());}, + "fnmsub.d, subtract infinity"); + + // FNMADD.D + expect(D::number(0xC019FD5AED13B1CEULL), + []{return D::fnmadd_d(3.1415926, 1.61803398875, 1.41421356237);}, + "fnmadd.d"); + expect(true, []{ + double fd = D::fnmadd_d(numeric_limits::quiet_NaN(), 3.14, + 1.816); + return D::isquietnan(fd); + }, "fnmadd.d, quiet NaN"); + expect(true, []{ + double fd = D::fnmadd_d(3.14, + numeric_limits::signaling_NaN(), 1.816); + return D::isquietnan(fd); + }, "fnmadd.d, signaling NaN"); + expect(-numeric_limits::infinity(), + []{return D::fnmadd_d(3.14, numeric_limits::infinity(), + 1.414);}, + "fnmadd.d, infinity"); + expect(numeric_limits::infinity(), + []{return D::fnmadd_d(3.14, -numeric_limits::infinity(), + 1.414);}, + "fnmadd.d, -infinity"); + + // FADD.D + expect(D::number(0x4012392540292D7CULL), + []{return D::fadd_d(3.1415926, 1.41421356237);}, "fadd.d"); + expect(true, []{ + double fd = D::fadd_d(numeric_limits::quiet_NaN(), 1.414); + return D::isquietnan(fd); + }, "fadd.d, quiet NaN"); + expect(true, []{ + double fd = D::fadd_d(3.14, + numeric_limits::signaling_NaN()); + return D::isquietnan(fd); + }, "fadd.d, signaling NaN"); + expect(numeric_limits::infinity(), + []{return D::fadd_d(3.14, numeric_limits::infinity());}, + "fadd.d, infinity"); + expect(-numeric_limits::infinity(), + []{return D::fadd_d(-numeric_limits::infinity(), 1.816);}, + "fadd.d, -infinity"); + + // FSUB.D + expect(D::number(0xBFFBA35833AB7AAEULL), + []{return D::fsub_d(1.4142135623, 3.1415926);}, "fsub.d"); + expect(true, []{ + double fd = D::fsub_d(numeric_limits::quiet_NaN(), 1.414); + return D::isquietnan(fd); + }, "fsub.d, quiet NaN"); + expect(true, []{ + double fd = D::fsub_d(3.14, + numeric_limits::signaling_NaN()); + return D::isquietnan(fd); + }, "fsub.d, signaling NaN"); + expect(numeric_limits::infinity(), + []{return D::fsub_d(numeric_limits::infinity(), 3.14);}, + "fsub.d, infinity"); + expect(-numeric_limits::infinity(), + []{return D::fsub_d(-numeric_limits::infinity(), 3.14);}, + "fsub.d, -infinity"); + expect(-numeric_limits::infinity(), + []{return D::fsub_d(1.414, numeric_limits::infinity());}, + "fsub.d, subtract infinity"); + + // FMUL.D + expect(D::number(0x40024E53B708ED9AULL), + []{return D::fmul_d(1.61803398875, 1.4142135623);}, "fmul.d"); + expect(true, []{ + double fd = D::fmul_d(numeric_limits::quiet_NaN(), 1.414); + return D::isquietnan(fd); + }, "fmul.d, quiet NaN"); + expect(true, []{ + double fd = D::fmul_d(1.816, + numeric_limits::signaling_NaN()); + return D::isquietnan(fd); + }, "fmul.d, signaling NaN"); + expect(numeric_limits::infinity(), + []{return D::fmul_d(numeric_limits::infinity(), 2.718);}, + "fmul.d, infinity"); + expect(-numeric_limits::infinity(), + []{return D::fmul_d(2.5966, -numeric_limits::infinity());}, + "fmul.d, -infinity"); + expect(true, []{ + double fd = D::fmul_d(0.0, numeric_limits::infinity()); + return D::isquietnan(fd); + }, "fmul.d, 0*infinity"); + expect(numeric_limits::infinity(), + []{return D::fmul_d(numeric_limits::max(), 2.0);}, + "fmul.d, overflow"); + expect(0.0, + []{return D::fmul_d(numeric_limits::min(), + numeric_limits::min());}, + "fmul.d, underflow"); + + // FDIV.D + expect(2.5, []{return D::fdiv_d(10.0, 4.0);}, "fdiv.d"); + expect(true, []{ + double fd = D::fdiv_d(numeric_limits::quiet_NaN(), 4.0); + return D::isquietnan(fd); + }, "fdiv.d, quiet NaN"); + expect(true, []{ + double fd = D::fdiv_d(10.0, + numeric_limits::signaling_NaN()); + return D::isquietnan(fd); + }, "fdiv.d, signaling NaN"); + expect(numeric_limits::infinity(), + []{return D::fdiv_d(10.0, 0.0);}, "fdiv.d/0"); + expect(0.0, + []{return D::fdiv_d(10.0, numeric_limits::infinity());}, + "fdiv.d/infinity"); + expect(true, []{ + double fd = D::fdiv_d(numeric_limits::infinity(), + numeric_limits::infinity()); + return D::isquietnan(fd); + }, "fdiv.d, infinity/infinity"); + expect(true, []{ + double fd = D::fdiv_d(0.0, 0.0); + return D::isquietnan(fd); + }, "fdiv.d, 0/0"); + expect(numeric_limits::infinity(), + []{return D::fdiv_d(numeric_limits::infinity(), 0.0);}, + "fdiv.d, infinity/0"); + expect(0.0, + []{return D::fdiv_d(0.0, numeric_limits::infinity());}, + "fdiv.d, 0/infinity"); + expect(0.0, + []{return D::fdiv_d(numeric_limits::min(), + numeric_limits::max());}, + "fdiv.d, underflow"); + expect(numeric_limits::infinity(), + []{return D::fdiv_d(numeric_limits::max(), + numeric_limits::min());}, + "fdiv.d, overflow"); + + // FSQRT.D + expect(1e154, []{return D::fsqrt_d(1e308);}, "fsqrt.d"); + expect(true, []{ + double fd = D::fsqrt_d(-1.0); + return D::isquietnan(fd); + }, "fsqrt.d, NaN"); + expect(true, []{ + double fd = D::fsqrt_d(numeric_limits::quiet_NaN()); + return D::isquietnan(fd); + }, "fsqrt.d, quiet NaN"); + expect(true, []{ + double fd = D::fsqrt_d(numeric_limits::signaling_NaN()); + return D::isquietnan(fd); + }, "fsqrt.d, signaling NaN"); + expect(numeric_limits::infinity(), + []{return D::fsqrt_d(numeric_limits::infinity());}, + "fsqrt.d, infinity"); + + // FSGNJ.D + expect(1.0, []{return D::fsgnj_d(1.0, 25.0);}, "fsgnj.d, ++"); + expect(-1.0, []{return D::fsgnj_d(1.0, -25.0);}, "fsgnj.d, +-"); + expect(1.0, []{return D::fsgnj_d(-1.0, 25.0);}, "fsgnj.d, -+"); + expect(-1.0, []{return D::fsgnj_d(-1.0, -25.0);}, "fsgnj.d, --"); + expect(true, []{ + double fd = D::fsgnj_d(numeric_limits::quiet_NaN(), -4.0); + return D::isquietnan(fd); + }, "fsgnj.d, quiet NaN"); + expect(true, []{ + double fd = D::fsgnj_d(numeric_limits::signaling_NaN(), + -4.0); + return D::issignalingnan(fd); + }, "fsgnj.d, signaling NaN"); + expect(4.0, + []{return D::fsgnj_d(4.0, numeric_limits::quiet_NaN());}, + "fsgnj.d, inject NaN"); + expect(-4.0, + []{return D::fsgnj_d(4.0, -numeric_limits::quiet_NaN());}, + "fsgnj.d, inject -NaN"); + + // FSGNJN.D + expect(-1.0, []{return D::fsgnjn_d(1.0, 25.0);}, "fsgnjn.d, ++"); + expect(1.0, []{return D::fsgnjn_d(1.0, -25.0);}, "fsgnjn.d, +-"); + expect(-1.0, []{return D::fsgnjn_d(-1.0, 25.0);}, "fsgnjn.d, -+"); + expect(1.0, []{return D::fsgnjn_d(-1.0, -25.0);}, "fsgnjn.d, --"); + expect(true, []{ + double fd = D::fsgnjn_d(numeric_limits::quiet_NaN(), -4.0); + return D::isquietnan(fd); + }, "fsgnjn.d, quiet NaN"); + expect(true, []{ + double fd = D::fsgnjn_d(numeric_limits::signaling_NaN(), + -4.0); + return D::issignalingnan(fd); + }, "fsgnjn.d, signaling NaN"); + expect(-4.0, + []{return D::fsgnjn_d(4.0, numeric_limits::quiet_NaN());}, + "fsgnjn.d, inject NaN"); + expect(4.0, + []{return D::fsgnjn_d(4.0, -numeric_limits::quiet_NaN());}, + "fsgnjn.d, inject NaN"); + + // FSGNJX.D + expect(1.0, []{return D::fsgnjx_d(1.0, 25.0);}, "fsgnjx.d, ++"); + expect(-1.0, []{return D::fsgnjx_d(1.0, -25.0);}, "fsgnjx.d, +-"); + expect(-1.0, []{return D::fsgnjx_d(-1.0, 25.0);}, "fsgnjx.d, -+"); + expect(1.0, []{return D::fsgnjx_d(-1.0, -25.0);}, "fsgnjx.d, --"); + expect(true, []{ + double fd = D::fsgnjx_d(numeric_limits::quiet_NaN(), -4.0); + return D::isquietnan(fd); + }, "fsgnjx.d, quiet NaN"); + expect(true, []{ + double fd = D::fsgnjx_d(numeric_limits::signaling_NaN(), + -4.0); + return D::issignalingnan(fd); + }, "fsgnjx.d, signaling NaN"); + expect(4.0, + []{return D::fsgnjx_d(4.0, numeric_limits::quiet_NaN());}, + "fsgnjx.d, inject NaN"); + expect(-4.0, + []{return D::fsgnjx_d(4.0, -numeric_limits::quiet_NaN());}, + "fsgnjx.d, inject NaN"); + + // FMIN.D + expect(2.718, []{return D::fmin_d(3.14, 2.718);}, "fmin.d"); + expect(-numeric_limits::infinity(), + []{return D::fmin_d(-numeric_limits::infinity(), + numeric_limits::min());}, + "fmin.d, -infinity"); + expect(numeric_limits::max(), + []{return D::fmin_d(numeric_limits::infinity(), + numeric_limits::max());}, + "fmin.d, infinity"); + expect(-1.414, + []{return D::fmin_d(numeric_limits::quiet_NaN(), -1.414);}, + "fmin.d, quiet NaN first"); + expect(2.718, + []{return D::fmin_d(2.718, numeric_limits::quiet_NaN());}, + "fmin.d, quiet NaN second"); + expect(true, []{ + double fd = D::fmin_d(numeric_limits::quiet_NaN(), + numeric_limits::quiet_NaN()); + return D::isquietnan(fd); + }, "fmin.d, quiet NaN both"); + expect(3.14, + []{return D::fmin_d(numeric_limits::signaling_NaN(), + 3.14);}, + "fmin.d, signaling NaN first"); + expect(1.816, + []{return D::fmin_d(1.816, + numeric_limits::signaling_NaN());}, + "fmin.d, signaling NaN second"); + expect(true, []{ + double fd = D::fmin_d(numeric_limits::signaling_NaN(), + numeric_limits::signaling_NaN()); + return D::issignalingnan(fd); + }, "fmin.d, signaling NaN both"); + + // FMAX.D + expect(3.14, []{return D::fmax_d(3.14, 2.718);}, "fmax.d"); + expect(numeric_limits::min(), + []{return D::fmax_d(-numeric_limits::infinity(), + numeric_limits::min());}, + "fmax.d, -infinity"); + expect(numeric_limits::infinity(), + []{return D::fmax_d(numeric_limits::infinity(), + numeric_limits::max());}, + "fmax.d, infinity"); + expect(-1.414, + []{return D::fmax_d(numeric_limits::quiet_NaN(), -1.414);}, + "fmax.d, quiet NaN first"); + expect(2.718, + []{return D::fmax_d(2.718, numeric_limits::quiet_NaN());}, + "fmax.d, quiet NaN second"); + expect(true, []{ + double fd = D::fmax_d(numeric_limits::quiet_NaN(), + numeric_limits::quiet_NaN()); + return D::isquietnan(fd); + }, "fmax.d, quiet NaN both"); + expect(3.14, + []{return D::fmax_d(numeric_limits::signaling_NaN(), + 3.14);}, + "fmax.d, signaling NaN first"); + expect(1.816, + []{return D::fmax_d(1.816, + numeric_limits::signaling_NaN());}, + "fmax.d, signaling NaN second"); + expect(true, []{ + double fd = D::fmax_d(numeric_limits::signaling_NaN(), + numeric_limits::signaling_NaN()); + return D::issignalingnan(fd); + }, "fmax.d, signaling NaN both"); + + // FCVT.S.D + expect(4.0, []{return D::fcvt_s_d(4.0);}, "fcvt.s.d"); + expect(true, []{ + float fd = D::fcvt_s_d(numeric_limits::quiet_NaN()); + return F::isquietnan(fd); + }, "fcvt.s.d, quiet NaN"); + expect(true, []{ + float fd = D::fcvt_s_d(numeric_limits::signaling_NaN()); + return F::isquietnan(fd); + }, "fcvt.s.d, signaling NaN"); + expect(numeric_limits::infinity(), + []{return D::fcvt_s_d(numeric_limits::infinity());}, + "fcvt.s.d, infinity"); + expect(numeric_limits::infinity(), + []{return D::fcvt_s_d(numeric_limits::max());}, + "fcvt.s.d, overflow"); + expect(0.0, []{return D::fcvt_s_d(numeric_limits::min());}, + "fcvt.s.d, underflow"); + + // FCVT.D.S + expect(D::number(0x4005BE76C0000000), + []{return D::fcvt_d_s(2.718);}, "fcvt.d.s"); + expect(true, []{ + double fd = D::fcvt_d_s(numeric_limits::quiet_NaN()); + return D::isquietnan(fd); + }, "fcvt.d.s, quiet NaN"); + expect(true, []{ + double fd = D::fcvt_d_s(numeric_limits::signaling_NaN()); + return D::isquietnan(fd); + }, "fcvt.d.s, signaling NaN"); + expect(numeric_limits::infinity(), + []{return D::fcvt_d_s(numeric_limits::infinity());}, + "fcvt.d.s, infinity"); + + // FEQ.D + expect(true, []{return D::feq_d(1.414, 1.414);}, "feq.d, equal"); + expect(false,[]{return D::feq_d(2.718, 1.816);}, "feq.d, not equal"); + expect(true, []{return D::feq_d(0.0, -0.0);}, "feq.d, 0 == -0"); + expect(false, + []{return D::feq_d(numeric_limits::quiet_NaN(), -1.0);}, + "feq.d, quiet NaN first"); + expect(false, + []{return D::feq_d(2.0, numeric_limits::quiet_NaN());}, + "feq.d, quiet NaN second"); + expect(false, + []{return D::feq_d(numeric_limits::quiet_NaN(), + numeric_limits::quiet_NaN());}, + "feq.d, quiet NaN both"); + expect(false, + []{return D::feq_d(numeric_limits::signaling_NaN(),-1.0);}, + "feq.d, signaling NaN first"); + expect(false, + []{return D::feq_d(2.0, numeric_limits::signaling_NaN());}, + "feq.d, signaling NaN second"); + expect(false, + []{return D::feq_d(numeric_limits::signaling_NaN(), + numeric_limits::signaling_NaN());}, + "feq.d, signaling NaN both"); + + // FLT.D + expect(false, []{return D::flt_d(1.414, 1.414);}, "flt.d, equal"); + expect(true, []{return D::flt_d(1.816, 2.718);}, "flt.d, less"); + expect(false, []{return D::flt_d(2.718, 1.816);}, "flt.d, greater"); + expect(false, + []{return D::flt_d(numeric_limits::quiet_NaN(), -1.0);}, + "flt.d, quiet NaN first"); + expect(false, + []{return D::flt_d(2.0, numeric_limits::quiet_NaN());}, + "flt.d, quiet NaN second"); + expect(false, + []{return D::flt_d(numeric_limits::quiet_NaN(), + numeric_limits::quiet_NaN());}, + "flt.d, quiet NaN both"); + expect(false, + []{return D::flt_d(numeric_limits::signaling_NaN(),-1.0);}, + "flt.d, signaling NaN first"); + expect(false, + []{return D::flt_d(2.0, numeric_limits::signaling_NaN());}, + "flt.d, signaling NaN second"); + expect(false, + []{return D::flt_d(numeric_limits::signaling_NaN(), + numeric_limits::signaling_NaN());}, + "flt.d, signaling NaN both"); + + // FLE.D + expect(true, []{return D::fle_d(1.414, 1.414);}, "fle.d, equal"); + expect(true, []{return D::fle_d(1.816, 2.718);}, "fle.d, less"); + expect(false, []{return D::fle_d(2.718, 1.816);}, "fle.d, greater"); + expect(true, []{return D::fle_d(0.0, -0.0);}, "fle.d, 0 == -0"); + expect(false, + []{return D::fle_d(numeric_limits::quiet_NaN(), -1.0);}, + "fle.d, quiet NaN first"); + expect(false, + []{return D::fle_d(2.0, numeric_limits::quiet_NaN());}, + "fle.d, quiet NaN second"); + expect(false, + []{return D::fle_d(numeric_limits::quiet_NaN(), + numeric_limits::quiet_NaN());}, + "fle.d, quiet NaN both"); + expect(false, + []{return D::fle_d(numeric_limits::signaling_NaN(),-1.0);}, + "fle.d, signaling NaN first"); + expect(false, + []{return D::fle_d(2.0, numeric_limits::signaling_NaN());}, + "fle.d, signaling NaN second"); + expect(false, + []{return D::fle_d(numeric_limits::signaling_NaN(), + numeric_limits::signaling_NaN());}, + "fle.d, signaling NaN both"); + + // FCLASS.D + expect(0x1, + []{return D::fclass_d(-numeric_limits::infinity());}, + "fclass.d, -infinity"); + expect(0x2, + []{return D::fclass_d(-3.14);}, "fclass.d, -normal"); + expect(0x4, + []{return D::fclass_d(D::number(0x800FFFFFFFFFFFFFULL));}, + "fclass.d, -subnormal"); + expect(0x8, []{return D::fclass_d(-0.0);}, "fclass.d, -0.0"); + expect(0x10, []{return D::fclass_d(0.0);}, "fclass.d, 0.0"); + expect(0x20, + []{return D::fclass_d(D::number(0x000FFFFFFFFFFFFFULL));}, + "fclass.d, subnormal"); + expect(0x40, []{return D::fclass_d(1.816);}, "fclass.d, normal"); + expect(0x80, + []{return D::fclass_d(numeric_limits::infinity());}, + "fclass.d, infinity"); + expect(0x100, + []{return D::fclass_d(numeric_limits::signaling_NaN());}, + "fclass.d, signaling NaN"); + expect(0x200, + []{return D::fclass_d(numeric_limits::quiet_NaN());}, + "fclass.s, quiet NaN"); + + // FCVT.W.D + expect(256, []{return D::fcvt_w_d(256.3);}, + "fcvt.w.d, truncate positive"); + expect(-256, []{return D::fcvt_w_d(-256.2);}, + "fcvt.w.d, truncate negative"); + expect(0, []{return D::fcvt_w_d(0.0);}, "fcvt.w.d, 0.0"); + expect(0, []{return D::fcvt_w_d(-0.0);}, "fcvt.w.d, -0.0"); + expect(numeric_limits::max(), + []{return D::fcvt_w_d(numeric_limits::max());}, + "fcvt.w.d, overflow"); + expect(0, []{return D::fcvt_w_d(numeric_limits::min());}, + "fcvt.w.d, underflow"); + expect(numeric_limits::max(), + []{return D::fcvt_w_d(numeric_limits::infinity());}, + "fcvt.w.d, infinity"); + expect(numeric_limits::min(), + []{return D::fcvt_w_d(-numeric_limits::infinity());}, + "fcvt.w.d, -infinity"); + expect(numeric_limits::max(), + []{return D::fcvt_w_d(numeric_limits::quiet_NaN());}, + "fcvt.w.d, quiet NaN"); + expect(numeric_limits::max(), + []{return D::fcvt_w_d(-numeric_limits::quiet_NaN());}, + "fcvt.w.d, quiet -NaN"); + expect(numeric_limits::max(), + []{return D::fcvt_w_d(numeric_limits::signaling_NaN());}, + "fcvt.w.d, signaling NaN"); + + // FCVT.WU.D + expect(256, []{return D::fcvt_wu_d(256.3);}, + "fcvt.wu.d, truncate positive"); + expect(0, []{return D::fcvt_wu_d(-256.2);}, + "fcvt.wu.d, truncate negative"); + expect(0, []{return D::fcvt_wu_d(0.0);}, "fcvt.wu.d, 0.0"); + expect(0, []{return D::fcvt_wu_d(-0.0);}, "fcvt.wu.d, -0.0"); + expect(numeric_limits::max(), + []{return D::fcvt_wu_d(numeric_limits::max());}, + "fcvt.wu.d, overflow"); + expect(0,[]{return D::fcvt_wu_d(numeric_limits::min());}, + "fcvt.wu.d, underflow"); + expect(numeric_limits::max(), + []{return D::fcvt_wu_d(numeric_limits::infinity());}, + "fcvt.wu.d, infinity"); + expect(0, + []{return D::fcvt_wu_d(-numeric_limits::infinity());}, + "fcvt.wu.d, -infinity"); + expect(0xFFFFFFFFFFFFFFFFULL, + []{return D::fcvt_wu_d(numeric_limits::quiet_NaN());}, + "fcvt.wu.d, quiet NaN"); + expect(0xFFFFFFFFFFFFFFFFULL, + []{return D::fcvt_wu_d(-numeric_limits::quiet_NaN());}, + "fcvt.wu.d, quiet -NaN"); + expect(0xFFFFFFFFFFFFFFFFULL, + []{return D::fcvt_wu_d(numeric_limits::signaling_NaN());}, + "fcvt.wu.d, signaling NaN"); + + // FCVT.D.W + expect(0.0, []{return D::fcvt_d_w(0);}, "fcvt.d.w, 0"); + expect(-2147483648.0, + []{return D::fcvt_d_w(numeric_limits::min());}, + "fcvt.d.w, negative"); + expect(255.0, []{return D::fcvt_d_w(0xFFFFFFFF000000FFLL);}, + "fcvt.d.w, truncate"); + + // FCVT.D.WU + expect(0.0, []{return D::fcvt_d_wu(0);}, "fcvt.d.wu, 0"); + expect(2147483648.0, + []{return D::fcvt_d_wu(numeric_limits::min());}, + "fcvt.d.wu"); + expect(255.0, + []{return D::fcvt_d_wu(0xFFFFFFFF000000FFLL);}, + "fcvt.d.wu, truncate"); + + // FCVT.L.D + expect(256, []{return D::fcvt_l_d(256.3);}, + "fcvt.l.d, truncate positive"); + expect(-256, []{return D::fcvt_l_d(-256.2);}, + "fcvt.l.d, truncate negative"); + expect(0, []{return D::fcvt_l_d(0.0);}, "fcvt.l.d, 0.0"); + expect(0, []{return D::fcvt_l_d(-0.0);}, "fcvt.l.d, -0.0"); + expect(-8589934592LL, []{return D::fcvt_l_d(-8589934592.0);}, + "fcvt.l.d, 32-bit overflow"); + expect(numeric_limits::max(), + []{return D::fcvt_l_d(numeric_limits::max());}, + "fcvt.l.d, overflow"); + expect(0, []{return D::fcvt_l_d(numeric_limits::min());}, + "fcvt.l.d, underflow"); + expect(numeric_limits::max(), + []{return D::fcvt_l_d(numeric_limits::infinity());}, + "fcvt.l.d, infinity"); + expect(numeric_limits::min(), + []{return D::fcvt_l_d(-numeric_limits::infinity());}, + "fcvt.l.d, -infinity"); + expect(numeric_limits::max(), + []{return D::fcvt_l_d(numeric_limits::quiet_NaN());}, + "fcvt.l.d, quiet NaN"); + expect(numeric_limits::max(), + []{return D::fcvt_l_d(-numeric_limits::quiet_NaN());}, + "fcvt.l.d, quiet -NaN"); + expect(numeric_limits::max(), + []{return D::fcvt_l_d(numeric_limits::signaling_NaN());}, + "fcvt.l.d, signaling NaN"); + + // FCVT.LU.D + expect(256, []{return D::fcvt_lu_d(256.3);}, + "fcvt.lu.d, truncate positive"); + expect(0, []{return D::fcvt_lu_d(-256.2);}, + "fcvt.lu.d, truncate negative"); + expect(0, []{return D::fcvt_lu_d(0.0);}, "fcvt.lu.d, 0.0"); + expect(0, []{return D::fcvt_lu_d(-0.0);}, "fcvt.lu.d, -0.0"); + expect(8589934592LL, []{return D::fcvt_lu_d(8589934592.0);}, + "fcvt.lu.d, 32-bit overflow"); + expect(numeric_limits::max(), + []{return D::fcvt_lu_d(numeric_limits::max());}, + "fcvt.lu.d, overflow"); + expect(0,[]{return D::fcvt_lu_d(numeric_limits::min());}, + "fcvt.lu.d, underflow"); + expect(numeric_limits::max(), + []{return D::fcvt_lu_d(numeric_limits::infinity());}, + "fcvt.lu.d, infinity"); + expect(0, + []{return D::fcvt_lu_d(-numeric_limits::infinity());}, + "fcvt.lu.d, -infinity"); + expect(0xFFFFFFFFFFFFFFFFULL, + []{return D::fcvt_lu_d(numeric_limits::quiet_NaN());}, + "fcvt.lu.d, quiet NaN"); + expect(0xFFFFFFFFFFFFFFFFULL, + []{return D::fcvt_lu_d(-numeric_limits::quiet_NaN());}, + "fcvt.lu.d, quiet -NaN"); + expect(0xFFFFFFFFFFFFFFFFULL, + []{return D::fcvt_lu_d(numeric_limits::signaling_NaN());}, + "fcvt.lu.d, signaling NaN"); + + // FMV.X.D + expect(0x40091EB851EB851FULL, []{return D::fmv_x_d(3.14);}, + "fmv.x.d, positive"); + expect(0xC0091EB851EB851FULL, []{return D::fmv_x_d(-3.14);}, + "fmv.x.d, negative"); + expect(0x0000000000000000ULL, []{return D::fmv_x_d(0.0);}, + "fmv.x.d, 0.0"); + expect(0x8000000000000000ULL, []{return D::fmv_x_d(-0.0);}, + "fmv.x.d, -0.0"); + + // FCVT.D.L + expect(0.0, []{return D::fcvt_d_l(0);}, "fcvt.d.l, 0"); + expect(D::number(0xC3E0000000000000), + []{return D::fcvt_d_l(numeric_limits::min());}, + "fcvt.d.l, negative"); + expect(D::number(0xC1EFFFFFE0200000), + []{return D::fcvt_d_l(0xFFFFFFFF000000FFLL);}, + "fcvt.d.l, 32-bit truncate"); + + // FCVT.D.LU + expect(0.0, []{return D::fcvt_d_lu(0);}, "fcvt.d.lu, 0"); + expect(D::number(0x43E0000000000000), + []{return D::fcvt_d_lu(numeric_limits::min());}, + "fcvt.d.lu"); + expect(D::number(0x43EFFFFFFFE00000), + []{return D::fcvt_d_lu(0xFFFFFFFF000000FFLL);}, + "fcvt.d.lu, 32-bit truncate"); + + // FMV.D.X + expect(-numeric_limits::infinity(), + []{return D::fmv_d_x(0xFFF0000000000000ULL);}, "fmv.d.x"); + + return 0; +} diff -r 8aec19bd88f8 -r ea40d2a41efb tests/test-progs/insttest/src/riscv/rv64f.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/test-progs/insttest/src/riscv/rv64f.h Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,357 @@ +/* + * Copyright (c) 2016 The University of Virginia + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Alec Roelke + */ + +#pragma once + +#include +#include + +#include "insttest.h" + +namespace F +{ + +constexpr inline uint32_t +bits(float f) +{ + return reinterpret_cast(f); +} + +constexpr inline float +number(uint32_t b) +{ + return reinterpret_cast(b); +} + +inline bool +isquietnan(float f) +{ + return std::isnan(f) && (bits(f)&0x00400000) != 0; +} + +inline bool +issignalingnan(float f) +{ + return std::isnan(f) && (bits(f)&0x00400000) == 0; +} + +inline float +load(float mem) +{ + float fd = std::numeric_limits::signaling_NaN(); + asm volatile("flw %0,%1" + : "=f" (fd) + : "m" (mem)); + return fd; +} + +inline float +store(float fs) +{ + float mem = std::numeric_limits::signaling_NaN(); + asm volatile("fsw %1,%0" : "=m" (mem) : "f" (fs)); + return mem; +} + +inline uint64_t +frflags() +{ + uint64_t rd = -1; + asm volatile("frflags %0" : "=r" (rd)); + return rd; +} + +inline uint64_t +fsflags(uint64_t rs1) +{ + uint64_t rd = -1; + asm volatile("fsflags %0,%1" : "=r" (rd) : "r" (rs1)); + return rd; +} + +inline float +fmadd_s(float fs1, float fs2, float fs3) +{ + float fd = std::numeric_limits::signaling_NaN(); + FR4OP("fmadd.s", fd, fs1, fs2, fs3); + return fd; +} + +inline float +fmsub_s(float fs1, float fs2, float fs3) +{ + float fd = std::numeric_limits::signaling_NaN(); + FR4OP("fmsub.s", fd, fs1, fs2, fs3); + return fd; +} + +inline float +fnmsub_s(float fs1, float fs2, float fs3) +{ + float fd = std::numeric_limits::signaling_NaN(); + FR4OP("fnmsub.s", fd, fs1, fs2, fs3); + return fd; +} + +inline float +fnmadd_s(float fs1, float fs2, float fs3) +{ + float fd = std::numeric_limits::signaling_NaN(); + FR4OP("fnmadd.s", fd, fs1, fs2, fs3); + return fd; +} + +inline float +fadd_s(float fs1, float fs2) +{ + float fd = std::numeric_limits::signaling_NaN(); + FROP("fadd.s", fd, fs1, fs2); + return fd; +} + +inline float +fsub_s(float fs1, float fs2) +{ + float fd = std::numeric_limits::signaling_NaN(); + FROP("fsub.s", fd, fs1, fs2); + return fd; +} + +inline float +fmul_s(float fs1, float fs2) +{ + float fd = std::numeric_limits::signaling_NaN(); + FROP("fmul.s", fd, fs1, fs2); + return fd; +} + +inline float +fdiv_s(float fs1, float fs2) +{ + + float fd = 0.0; + FROP("fdiv.s", fd, fs1, fs2); + return fd; +} + +inline float +fsqrt_s(float fs1) +{ + float fd = std::numeric_limits::infinity(); + asm volatile("fsqrt.s %0,%1" : "=f" (fd) : "f" (fs1)); + return fd; +} + +inline float +fsgnj_s(float fs1, float fs2) +{ + float fd = std::numeric_limits::signaling_NaN(); + FROP("fsgnj.s", fd, fs1, fs2); + return fd; +} + +inline float +fsgnjn_s(float fs1, float fs2) +{ + float fd = std::numeric_limits::signaling_NaN(); + FROP("fsgnjn.s", fd, fs1, fs2); + return fd; +} + +inline float +fsgnjx_s(float fs1, float fs2) +{ + float fd = std::numeric_limits::signaling_NaN(); + FROP("fsgnjx.s", fd, fs1, fs2); + return fd; +} + +inline float +fmin_s(float fs1, float fs2) +{ + float fd = std::numeric_limits::signaling_NaN(); + FROP("fmin.s", fd, fs1, fs2); + return fd; +} + +inline float +fmax_s(float fs1, float fs2) +{ + float fd = std::numeric_limits::signaling_NaN(); + FROP("fmax.s", fd, fs1, fs2); + return fd; +} + +inline int64_t +fcvt_w_s(float fs1) +{ + int64_t rd = 0; + asm volatile("fcvt.w.s %0,%1" : "=r" (rd) : "f" (fs1)); + return rd; +} + +inline uint64_t +fcvt_wu_s(float fs1) +{ + uint64_t rd = 0; + asm volatile("fcvt.wu.s %0,%1" : "=r" (rd) : "f" (fs1)); + return rd; +} + +inline uint64_t +fmv_x_s(float fs1) +{ + uint64_t rd = 0; + asm volatile("fmv.x.s %0,%1" : "=r" (rd) : "f" (fs1)); + return rd; +} + +inline bool +feq_s(float fs1, float fs2) +{ + bool rd = false; + asm volatile("feq.s %0,%1,%2" : "=r" (rd) : "f" (fs1), "f" (fs2)); + return rd; +} + +inline bool +flt_s(float fs1, float fs2) +{ + bool rd = false; + asm volatile("flt.s %0,%1,%2" : "=r" (rd) : "f" (fs1), "f" (fs2)); + return rd; +} + +inline bool +fle_s(float fs1, float fs2) +{ + bool rd = false; + asm volatile("fle.s %0,%1,%2" : "=r" (rd) : "f" (fs1), "f" (fs2)); + return rd; +} + +inline uint64_t +fclass_s(float fs1) +{ + uint64_t rd = -1; + asm volatile("fclass.s %0,%1" : "=r" (rd) : "f" (fs1)); + return rd; +} + +inline float +fcvt_s_w(int64_t rs1) +{ + float fd = std::numeric_limits::signaling_NaN(); + asm volatile("fcvt.s.w %0,%1" : "=f" (fd) : "r" (rs1)); + return fd; +} + +inline float +fcvt_s_wu(uint64_t rs1) +{ + float fd = std::numeric_limits::signaling_NaN(); + asm volatile("fcvt.s.wu %0,%1" : "=f" (fd) : "r" (rs1)); + return fd; +} + +inline float +fmv_s_x(uint64_t rs1) +{ + float fd = std::numeric_limits::signaling_NaN(); + asm volatile("fmv.s.x %0,%1" : "=f" (fd) : "r" (rs1)); + return fd; +} + +inline uint64_t +frcsr() +{ + uint64_t rd = -1; + asm volatile("frcsr %0" : "=r" (rd)); + return rd; +} + +inline uint64_t +frrm() +{ + uint64_t rd = -1; + asm volatile("frrm %0" : "=r" (rd)); + return rd; +} + +inline uint64_t +fscsr(uint64_t rs1) +{ + uint64_t rd = -1; + asm volatile("fscsr %0,%1" : "=r" (rd) : "r" (rs1)); + return rd; +} + +inline uint64_t +fsrm(uint64_t rs1) +{ + uint64_t rd = -1; + asm volatile("fsrm %0,%1" : "=r" (rd) : "r" (rs1)); + return rd; +} + +inline int64_t +fcvt_l_s(float fs1) +{ + int64_t rd = 0; + asm volatile("fcvt.l.s %0,%1" : "=r" (rd) : "f" (fs1)); + return rd; +} + +inline uint64_t +fcvt_lu_s(float fs1) +{ + + int64_t rd = 0; + asm volatile("fcvt.lu.s %0,%1" : "=r" (rd) : "f" (fs1)); + return rd; +} + +inline float +fcvt_s_l(int64_t rs1) +{ + float fd = std::numeric_limits::signaling_NaN(); + asm volatile("fcvt.s.l %0,%1" : "=f" (fd) : "r" (rs1)); + return fd; +} + +inline float +fcvt_s_lu(uint64_t rs1) +{ + float fd = std::numeric_limits::signaling_NaN(); + asm volatile("fcvt.s.lu %0,%1" : "=f" (fd) : "r" (rs1)); + return fd; +} + +} // namespace F diff -r 8aec19bd88f8 -r ea40d2a41efb tests/test-progs/insttest/src/riscv/rv64f.cpp --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/test-progs/insttest/src/riscv/rv64f.cpp Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,694 @@ +/* + * Copyright (c) 2016 The University of Virginia + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Alec Roelke + */ + +#include +#include + +#include "insttest.h" +#include "rv64f.h" + +int main() +{ + using namespace std; + using namespace insttest; + + // FLAGS + expect(0, []{ + F::fsflags(0); + return F::frflags(); + }, "clear fsflags"); + + // Memory + expect(3.14, []{return F::load(3.14);}, "flw"); + expect(1.816, []{return F::store(1.816);}, "fsw"); + + // FMADD.S + expect(7.11624, []{return F::fmadd_s(3.14, 1.816, 1.414);}, + "fmadd.s"); + expect(true, []{ + float fd = F::fmadd_s(numeric_limits::quiet_NaN(), 3.14, + 1.816); + return F::isquietnan(fd); + }, "fmadd.s, quiet NaN"); + expect(true, []{ + float fd = F::fmadd_s(3.14, numeric_limits::signaling_NaN(), + 1.816); + return F::isquietnan(fd); + }, "fmadd.s, signaling NaN"); + expect(numeric_limits::infinity(), + []{return F::fmadd_s(3.14, numeric_limits::infinity(), + 1.414);}, + "fmadd.s, infinity"); + expect(-numeric_limits::infinity(), + []{return F::fmadd_s(3.14, -numeric_limits::infinity(), + 1.414);}, + "fmadd.s, -infinity"); + + // FMSUB.S + expect(4.28824, []{return F::fmsub_s(3.14, 1.816, 1.414);}, + "fmsub.s"); + expect(true, []{ + float fd = F::fmsub_s(3.14, numeric_limits::quiet_NaN(), + 1.816); + return F::isquietnan(fd); + }, "fmsub.s, quiet NaN"); + expect(true, []{ + float fd = F::fmsub_s(3.14, 1.816, + numeric_limits::signaling_NaN()); + return F::isquietnan(fd); + }, "fmsub.s, signaling NaN"); + expect(numeric_limits::infinity(), + []{return F::fmsub_s(numeric_limits::infinity(), 1.816, + 1.414);}, + "fmsub.s, infinity"); + expect(-numeric_limits::infinity(), + []{return F::fmsub_s(3.14, -numeric_limits::infinity(), + 1.414);}, + "fmsub.s, -infinity"); + expect(-numeric_limits::infinity(), + []{return F::fmsub_s(3.14, 1.816, + numeric_limits::infinity());}, + "fmsub.s, subtract infinity"); + + // FNMSUB.S + expect(-4.28824, []{return F::fnmsub_s(3.14, 1.816, 1.414);}, + "fnmsub.s"); + expect(true, []{ + float fd = F::fnmsub_s(3.14, 1.816, + numeric_limits::quiet_NaN()); + return F::isquietnan(fd); + }, "fnmsub.s, quiet NaN"); + expect(true, []{ + float fd = F::fnmsub_s(numeric_limits::signaling_NaN(), + 1.816, 1.414); + return F::isquietnan(fd); + }, "fnmsub.s, signaling NaN"); + expect(-numeric_limits::infinity(), + []{return F::fnmsub_s(numeric_limits::infinity(), + 1.816, 1.414);}, + "fnmsub.s, infinity"); + expect(numeric_limits::infinity(), + []{return F::fnmsub_s(3.14, -numeric_limits::infinity(), + 1.414);}, + "fnmsub.s, -infinity"); + expect(numeric_limits::infinity(), + []{return F::fnmsub_s(3.14, 1.816, + numeric_limits::infinity());}, + "fnmsub.s, subtract infinity"); + + // FNMADD.S + expect(-7.11624, []{return F::fnmadd_s(3.14, 1.816, 1.414);}, + "fnmadd.s"); + expect(true, []{ + float fd = F::fnmadd_s(numeric_limits::quiet_NaN(), 3.14, + 1.816); + return F::isquietnan(fd); + }, "fnmadd.s, quiet NaN"); + expect(true, []{ + float fd = F::fnmadd_s(3.14,numeric_limits::signaling_NaN(), + 1.816); + return F::isquietnan(fd); + }, "fnmadd.s, signaling NaN"); + expect(-numeric_limits::infinity(), + []{return F::fnmadd_s(3.14, numeric_limits::infinity(), + 1.414);}, + "fnmadd.s, infinity"); + expect(numeric_limits::infinity(), + []{return F::fnmadd_s(3.14, -numeric_limits::infinity(), + 1.414);}, + "fnmadd.s, -infinity"); + + // FADD.S + expect(4.554, []{return F::fadd_s(3.14, 1.414);}, "fadd.s"); + expect(true, []{ + float fd = F::fadd_s(numeric_limits::quiet_NaN(), 1.414); + return F::isquietnan(fd); + }, "fadd.s, quiet NaN"); + expect(true, []{ + float fd = F::fadd_s(3.14, numeric_limits::signaling_NaN()); + return F::isquietnan(fd); + }, "fadd.s, signaling NaN"); + expect(numeric_limits::infinity(), + []{return F::fadd_s(3.14, numeric_limits::infinity());}, + "fadd.s, infinity"); + expect(-numeric_limits::infinity(), + []{return F::fadd_s(-numeric_limits::infinity(), 1.816);}, + "fadd.s, -infinity"); + + // FSUB.S + expect(F::number(0xbfdced92), []{return F::fsub_s(1.414, 3.14);}, + "fsub.s"); + expect(true, []{ + float fd = F::fsub_s(numeric_limits::quiet_NaN(), 1.414); + return F::isquietnan(fd); + }, "fsub.s, quiet NaN"); + expect(true, []{ + float fd = F::fsub_s(3.14, numeric_limits::signaling_NaN()); + return F::isquietnan(fd); + }, "fsub.s, signaling NaN"); + expect(numeric_limits::infinity(), + []{return F::fsub_s(numeric_limits::infinity(), 3.14);}, + "fsub.s, infinity"); + expect(-numeric_limits::infinity(), + []{return F::fsub_s(-numeric_limits::infinity(), 3.14);}, + "fsub.s, -infinity"); + expect(-numeric_limits::infinity(), + []{return F::fsub_s(1.414, numeric_limits::infinity());}, + "fsub.s, subtract infinity"); + + // FMUL.S + expect(F::number(0x4024573b), []{return F::fmul_s(1.816, 1.414);}, + "fmul.s"); + expect(true, []{ + float fd = F::fmul_s(numeric_limits::quiet_NaN(), 1.414); + return F::isquietnan(fd); + }, "fmul.s, quiet NaN"); + expect(true, []{ + float fd = F::fmul_s(1.816, + numeric_limits::signaling_NaN()); + return F::isquietnan(fd); + }, "fmul.s, signaling NaN"); + expect(numeric_limits::infinity(), + []{return F::fmul_s(numeric_limits::infinity(), 2.718);}, + "fmul.s, infinity"); + expect(-numeric_limits::infinity(), + []{return F::fmul_s(2.5966, -numeric_limits::infinity());}, + "fmul.s, -infinity"); + expect(true, []{ + float fd = F::fmul_s(0.0, numeric_limits::infinity()); + return F::isquietnan(fd); + }, "fmul.s, 0*infinity"); + expect(numeric_limits::infinity(), + []{return F::fmul_s(numeric_limits::max(), 2.0);}, + "fmul.s, overflow"); + expect(0.0, + []{return F::fmul_s(numeric_limits::min(), + numeric_limits::min());}, + "fmul.s, underflow"); + + // FDIV.S + expect(2.5, []{return F::fdiv_s(10.0, 4.0);}, "fdiv.s"); + expect(true, []{ + float fd = F::fdiv_s(numeric_limits::quiet_NaN(), 4.0); + return F::isquietnan(fd); + }, "fdiv.s, quiet NaN"); + expect(true, []{ + float fd = F::fdiv_s(10.0, numeric_limits::signaling_NaN()); + return F::isquietnan(fd); + }, "fdiv.s, signaling NaN"); + expect(numeric_limits::infinity(), + []{return F::fdiv_s(10.0, 0.0);}, "fdiv.s/0"); + expect(0.0, + []{return F::fdiv_s(10.0, numeric_limits::infinity());}, + "fdiv.s/infinity"); + expect(true, []{ + float fd = F::fdiv_s(numeric_limits::infinity(), + numeric_limits::infinity()); + return F::isquietnan(fd); + }, "fdiv.s, infinity/infinity"); + expect(true, []{ + float fd = F::fdiv_s(0.0, 0.0); + return F::isquietnan(fd); + }, "fdiv.s, 0/0"); + expect(numeric_limits::infinity(), + []{return F::fdiv_s(numeric_limits::infinity(), 0.0);}, + "fdiv.s, infinity/0"); + expect(0.0, + []{return F::fdiv_s(0.0, numeric_limits::infinity());}, + "fdiv.s, 0/infinity"); + expect(0.0, + []{return F::fdiv_s(numeric_limits::min(), + numeric_limits::max());}, + "fdiv.s, underflow"); + expect(numeric_limits::infinity(), + []{return F::fdiv_s(numeric_limits::max(), + numeric_limits::min());}, + "fdiv.s, overflow"); + + // FSQRT.S + expect(0.3, []{return F::fsqrt_s(0.09);}, "fsqrt.s"); + expect(true, []{ + float fd = F::fsqrt_s(-1.0); + return F::isquietnan(fd); + }, "fsqrt.s, NaN"); + expect(true, []{ + float fd = F::fsqrt_s(numeric_limits::quiet_NaN()); + return F::isquietnan(fd); + }, "fsqrt.s, quiet NaN"); + expect(true, []{ + float fd = F::fsqrt_s(numeric_limits::signaling_NaN()); + return F::isquietnan(fd); + }, "fsqrt.s, signaling NaN"); + expect(numeric_limits::infinity(), + []{return F::fsqrt_s(numeric_limits::infinity());}, + "fsqrt.s, infinity"); + + // FSGNJ.S + expect(1.0, []{return F::fsgnj_s(1.0, 25.0);}, "fsgnj.s, ++"); + expect(-1.0, []{return F::fsgnj_s(1.0, -25.0);}, "fsgnj.s, +-"); + expect(1.0, []{return F::fsgnj_s(-1.0, 25.0);}, "fsgnj.s, -+"); + expect(-1.0, []{return F::fsgnj_s(-1.0, -25.0);}, "fsgnj.s, --"); + expect(true, []{ + float fd = F::fsgnj_s(numeric_limits::quiet_NaN(), -4.0); + return F::isquietnan(fd); + }, "fsgnj.s, quiet NaN"); + expect(true, []{ + float fd = F::fsgnj_s(numeric_limits::signaling_NaN(), + -4.0); + return F::issignalingnan(fd); + }, "fsgnj.s, signaling NaN"); + expect(4.0, []{return F::fsgnj_s(4.0, + numeric_limits::quiet_NaN());}, "fsgnj.s, inject NaN"); + expect(-4.0, + []{return F::fsgnj_s(4.0, -numeric_limits::quiet_NaN());}, + "fsgnj.s, inject -NaN"); + + // FSGNJN.S + expect(-1.0, []{return F::fsgnjn_s(1.0, 25.0);}, "fsgnjn.s, ++"); + expect(1.0, []{return F::fsgnjn_s(1.0, -25.0);}, "fsgnjn.s, +-"); + expect(-1.0, []{return F::fsgnjn_s(-1.0, 25.0);}, "fsgnjn.s, -+"); + expect(1.0, []{return F::fsgnjn_s(-1.0, -25.0);}, "fsgnjn.s, --"); + expect(true, []{ + float fd = F::fsgnjn_s(numeric_limits::quiet_NaN(), -4.0); + return F::isquietnan(fd); + }, "fsgnjn.s, quiet NaN"); + expect(true, []{ + float fd = F::fsgnjn_s(numeric_limits::signaling_NaN(), + -4.0); + return F::issignalingnan(fd); + }, "fsgnjn.s, signaling NaN"); + expect(-4.0, + []{return F::fsgnjn_s(4.0, numeric_limits::quiet_NaN());}, + "fsgnjn.s, inject NaN"); + expect(4.0, + []{return F::fsgnjn_s(4.0, -numeric_limits::quiet_NaN());}, + "fsgnjn.s, inject NaN"); + + // FSGNJX.S + expect(1.0, []{return F::fsgnjx_s(1.0, 25.0);}, "fsgnjx.s, ++"); + expect(-1.0, []{return F::fsgnjx_s(1.0, -25.0);}, "fsgnjx.s, +-"); + expect(-1.0, []{return F::fsgnjx_s(-1.0, 25.0);}, "fsgnjx.s, -+"); + expect(1.0, []{return F::fsgnjx_s(-1.0, -25.0);}, "fsgnjx.s, --"); + expect(true, []{ + float fd = F::fsgnjx_s(numeric_limits::quiet_NaN(), -4.0); + return F::isquietnan(fd); + }, "fsgnjx.s, quiet NaN"); + expect(true, []{ + float fd = F::fsgnjx_s(numeric_limits::signaling_NaN(), + -4.0); + return F::issignalingnan(fd); + }, "fsgnjx.s, signaling NaN"); + expect(4.0, + []{return F::fsgnjx_s(4.0, numeric_limits::quiet_NaN());}, + "fsgnjx.s, inject NaN"); + expect(-4.0, + []{return F::fsgnjx_s(4.0, -numeric_limits::quiet_NaN());}, + "fsgnjx.s, inject -NaN"); + + // FMIN.S + expect(2.718, []{return F::fmin_s(3.14, 2.718);}, "fmin.s"); + expect(-numeric_limits::infinity(), + []{return F::fmin_s(-numeric_limits::infinity(), + numeric_limits::min());}, + "fmin.s, -infinity"); + expect(numeric_limits::max(), + []{return F::fmin_s(numeric_limits::infinity(), + numeric_limits::max());}, + "fmin.s, infinity"); + expect(-1.414, + []{return F::fmin_s(numeric_limits::quiet_NaN(), -1.414);}, + "fmin.s, quiet NaN first"); + expect(2.718, + []{return F::fmin_s(2.718, numeric_limits::quiet_NaN());}, + "fmin.s, quiet NaN second"); + expect(true, []{ + float fd = F::fmin_s(numeric_limits::quiet_NaN(), + numeric_limits::quiet_NaN()); + return F::isquietnan(fd); + }, "fmin.s, quiet NaN both"); + expect(3.14, + []{return F::fmin_s(numeric_limits::signaling_NaN(), + 3.14);}, + "fmin.s, signaling NaN first"); + expect(1.816, + []{return F::fmin_s(1.816, + numeric_limits::signaling_NaN());}, + "fmin.s, signaling NaN second"); + expect(true, []{ + float fd = F::fmin_s(numeric_limits::signaling_NaN(), + numeric_limits::signaling_NaN()); + return F::issignalingnan(fd); + }, "fmin.s, signaling NaN both"); + + // FMAX.S + expect(3.14, []{return F::fmax_s(3.14, 2.718);}, "fmax.s"); + expect(numeric_limits::min(), + []{return F::fmax_s(-numeric_limits::infinity(), + numeric_limits::min());}, + "fmax.s, -infinity"); + expect(numeric_limits::infinity(), + []{return F::fmax_s(numeric_limits::infinity(), + numeric_limits::max());}, + "fmax.s, infinity"); + expect(-1.414, + []{return F::fmax_s(numeric_limits::quiet_NaN(), -1.414);}, + "fmax.s, quiet NaN first"); + expect(2.718, + []{return F::fmax_s(2.718, numeric_limits::quiet_NaN());}, + "fmax.s, quiet NaN second"); + expect(true, []{ + float fd = F::fmax_s(numeric_limits::quiet_NaN(), + numeric_limits::quiet_NaN()); + return F::isquietnan(fd); + }, "fmax.s, quiet NaN both"); + expect(3.14, + []{return F::fmax_s(numeric_limits::signaling_NaN(), + 3.14);}, + "fmax.s, signaling NaN first"); + expect(1.816, []{return F::fmax_s(1.816, + numeric_limits::signaling_NaN());}, + "fmax.s, signaling NaN second"); + expect(true, []{ + float fd = F::fmax_s(numeric_limits::signaling_NaN(), + numeric_limits::signaling_NaN()); + return F::issignalingnan(fd); + }, "fmax.s, signaling NaN both"); + + // FCVT.W.S + expect(256, []{return F::fcvt_w_s(256.3);}, + "fcvt.w.s, truncate positive"); + expect(-256, []{return F::fcvt_w_s(-256.2);}, + "fcvt.w.s, truncate negative"); + expect(0, []{return F::fcvt_w_s(0.0);}, "fcvt.w.s, 0.0"); + expect(0, []{return F::fcvt_w_s(-0.0);}, "fcvt.w.s, -0.0"); + expect(numeric_limits::max(), + []{return F::fcvt_w_s(numeric_limits::max());}, + "fcvt.w.s, overflow"); + expect(0, []{return F::fcvt_w_s(numeric_limits::min());}, + "fcvt.w.s, underflow"); + expect(numeric_limits::max(), + []{return F::fcvt_w_s(numeric_limits::infinity());}, + "fcvt.w.s, infinity"); + expect(numeric_limits::min(), + []{return F::fcvt_w_s(-numeric_limits::infinity());}, + "fcvt.w.s, -infinity"); + expect(numeric_limits::max(), + []{return F::fcvt_w_s(numeric_limits::quiet_NaN());}, + "fcvt.w.s, quiet NaN"); + expect(numeric_limits::max(), + []{return F::fcvt_w_s(-numeric_limits::quiet_NaN());}, + "fcvt.w.s, quiet -NaN"); + expect(numeric_limits::max(), + []{return F::fcvt_w_s(numeric_limits::signaling_NaN());}, + "fcvt.w.s, signaling NaN"); + + // FCVT.WU.S + expect(256, []{return F::fcvt_wu_s(256.3);}, + "fcvt.wu.s, truncate positive"); + expect(0, []{return F::fcvt_wu_s(-256.2);}, + "fcvt.wu.s, truncate negative"); + expect(0, []{return F::fcvt_wu_s(0.0);}, "fcvt.wu.s, 0.0"); + expect(0, []{return F::fcvt_wu_s(-0.0);}, "fcvt.wu.s, -0.0"); + expect(numeric_limits::max(), + []{return F::fcvt_wu_s(numeric_limits::max());}, + "fcvt.wu.s, overflow"); + expect(0, []{return F::fcvt_wu_s(numeric_limits::min());}, + "fcvt.wu.s, underflow"); + expect(numeric_limits::max(), + []{return F::fcvt_wu_s(numeric_limits::infinity());}, + "fcvt.wu.s, infinity"); + expect(0, + []{return F::fcvt_wu_s(-numeric_limits::infinity());}, + "fcvt.wu.s, -infinity"); + expect(0xFFFFFFFFFFFFFFFFULL, + []{return F::fcvt_wu_s(numeric_limits::quiet_NaN());}, + "fcvt.wu.s, quiet NaN"); + expect(0xFFFFFFFFFFFFFFFFULL, + []{return F::fcvt_wu_s(-numeric_limits::quiet_NaN());}, + "fcvt.wu.s, quiet -NaN"); + expect(0xFFFFFFFFFFFFFFFFULL, + []{return F::fcvt_wu_s(numeric_limits::signaling_NaN());}, + "fcvt.wu.s, signaling NaN"); + + // FMV.X.S + expect(0x000000004048F5C3ULL, []{return F::fmv_x_s(3.14);}, + "fmv.x.s, positive"); + expect(0xFFFFFFFFC048F5C3ULL, []{return F::fmv_x_s(-3.14);}, + "fmv.x.s, negative"); + expect(0x0000000000000000ULL, []{return F::fmv_x_s(0.0);}, + "fmv.x.s, 0.0"); + expect(0xFFFFFFFF80000000ULL, []{return F::fmv_x_s(-0.0);}, + "fmv.x.s, -0.0"); + + // FEQ.S + expect(true, []{return F::feq_s(1.414, 1.414);}, "feq.s, equal"); + expect(false, []{return F::feq_s(2.718, 1.816);}, + "feq.s, not equal"); + expect(true, []{return F::feq_s(0.0, -0.0);}, "feq.s, 0 == -0"); + expect(false, + []{return F::feq_s(numeric_limits::quiet_NaN(), -1.0);}, + "feq.s, quiet NaN first"); + expect(false, + []{return F::feq_s(2.0, numeric_limits::quiet_NaN());}, + "feq.s, quiet NaN second"); + expect(false, + []{return F::feq_s(numeric_limits::quiet_NaN(), + numeric_limits::quiet_NaN());}, + "feq.s, quiet NaN both"); + expect(false, + []{return F::feq_s(numeric_limits::signaling_NaN(), -1.0);}, + "feq.s, signaling NaN first"); + expect(false, + []{return F::feq_s(2.0, numeric_limits::signaling_NaN());}, + "feq.s, signaling NaN second"); + expect(false, + []{return F::feq_s(numeric_limits::signaling_NaN(), + numeric_limits::signaling_NaN());}, + "feq.s, signaling NaN both"); + + // FLT.S + expect(false, []{return F::flt_s(1.414, 1.414);}, "flt.s, equal"); + expect(true, []{return F::flt_s(1.816, 2.718);}, "flt.s, less"); + expect(false, []{return F::flt_s(2.718, 1.816);}, "flt.s, greater"); + expect(false, + []{return F::flt_s(numeric_limits::quiet_NaN(), -1.0);}, + "flt.s, quiet NaN first"); + expect(false, + []{return F::flt_s(2.0, numeric_limits::quiet_NaN());}, + "flt.s, quiet NaN second"); + expect(false, + []{return F::flt_s(numeric_limits::quiet_NaN(), + numeric_limits::quiet_NaN());}, + "flt.s, quiet NaN both"); + expect(false, + []{return F::flt_s(numeric_limits::signaling_NaN(), -1.0);}, + "flt.s, signaling NaN first"); + expect(false, + []{return F::flt_s(2.0, numeric_limits::signaling_NaN());}, + "flt.s, signaling NaN second"); + expect(false, + []{return F::flt_s(numeric_limits::signaling_NaN(), + numeric_limits::signaling_NaN());}, + "flt.s, signaling NaN both"); + + // FLE.S + expect(true, []{return F::fle_s(1.414, 1.414);}, "fle.s, equal"); + expect(true, []{return F::fle_s(1.816, 2.718);}, "fle.s, less"); + expect(false, []{return F::fle_s(2.718, 1.816);}, "fle.s, greater"); + expect(true, []{return F::fle_s(0.0, -0.0);}, "fle.s, 0 == -0"); + expect(false, + []{return F::fle_s(numeric_limits::quiet_NaN(), -1.0);}, + "fle.s, quiet NaN first"); + expect(false, + []{return F::fle_s(2.0, numeric_limits::quiet_NaN());}, + "fle.s, quiet NaN second"); + expect(false, + []{return F::fle_s(numeric_limits::quiet_NaN(), + numeric_limits::quiet_NaN());}, + "fle.s, quiet NaN both"); + expect(false, + []{return F::fle_s(numeric_limits::signaling_NaN(), -1.0);}, + "fle.s, signaling NaN first"); + expect(false, + []{return F::fle_s(2.0, numeric_limits::signaling_NaN());}, + "fle.s, signaling NaN second"); + expect(false, + []{return F::fle_s(numeric_limits::signaling_NaN(), + numeric_limits::signaling_NaN());}, + "fle.s, signaling NaN both"); + + // FCLASS.S + expect(0x1, + []{return F::fclass_s(-numeric_limits::infinity());}, + "fclass.s, -infinity"); + expect(0x2, []{return F::fclass_s(-3.14);}, "fclass.s, -normal"); + expect(0x4, []{return F::fclass_s(F::number(0x807FFFFF));}, + "fclass.s, -subnormal"); + expect(0x8, []{return F::fclass_s(-0.0);}, "fclass.s, -0.0"); + expect(0x10, []{return F::fclass_s(0.0);}, "fclass.s, 0.0"); + expect(0x20, []{return F::fclass_s(F::number(0x007FFFFF));}, + "fclass.s, subnormal"); + expect(0x40, []{return F::fclass_s(1.816);}, "fclass.s, normal"); + expect(0x80, + []{return F::fclass_s(numeric_limits::infinity());}, + "fclass.s, infinity"); + expect(0x100, + []{return F::fclass_s(numeric_limits::signaling_NaN());}, + "fclass.s, signaling NaN"); + expect(0x200, + []{return F::fclass_s(numeric_limits::quiet_NaN());}, + "fclass.s, quiet NaN"); + + // FCVT.S.W + expect(0.0, []{return F::fcvt_s_w(0);}, "fcvt.s.w, 0"); + expect(-2147483648.0, + []{return F::fcvt_s_w(numeric_limits::min());}, + "fcvt.s.w, negative"); + expect(255.0, []{return F::fcvt_s_w(0xFFFFFFFF000000FFLL);}, + "fcvt.s.w, truncate"); + + // FCVT.S.WU + expect(0.0, []{return F::fcvt_s_wu(0);}, "fcvt.s.wu, 0"); + expect(2147483648.0, + []{return F::fcvt_s_wu(numeric_limits::min());}, + "fcvt.s.wu"); + expect(255.0, []{return F::fcvt_s_wu(0xFFFFFFFF000000FFLL);}, + "fcvt.s.wu, truncate"); + + // FMV.S.X + expect(numeric_limits::infinity(), + []{return F::fmv_s_x(0x7F800000);}, "fmv.s.x"); + expect(-0.0, []{return F::fmv_s_x(0xFFFFFFFF80000000ULL);}, + "fmv.s.x, truncate"); + + // FCSR functions + int rm = F::frrm(); + expect(0x7, []{ // FSRM + F::fsrm(-1); + return F::frrm(); + }, "fsrm"); + expect(0x1F, []{ // FSFLAGS + F::fsflags(0); + F::fsflags(-1); + return F::frflags(); + }, "fsflags"); + expect(0xFF, []{ // FSCSR + F::fsflags(0); + F::fsrm(0); + F::fscsr(-1); + return F::frcsr(); + }, "fscsr"); + expect(rm << 5, [=]{ + F::fscsr(0); + F::fsrm(rm); + return F::frcsr(); + }, "restore initial round mode"); + + F::fsflags(0); + + // FCVT.L.S + expect(256, []{return F::fcvt_l_s(256.3);}, + "fcvt.l.s, truncate positive"); + expect(-256, []{return F::fcvt_l_s(-256.2);}, + "fcvt.l.s, truncate negative"); + expect(0, []{return F::fcvt_l_s(0.0);}, "fcvt.l.s, 0.0"); + expect(0, []{return F::fcvt_l_s(-0.0);}, "fcvt.l.s, -0.0"); + expect(-8589934592LL, []{return F::fcvt_l_s(-8589934592.0);}, + "fcvt.l.s, 32-bit overflow"); + expect(numeric_limits::max(), + []{return F::fcvt_l_s(numeric_limits::max());}, + "fcvt.l.s, overflow"); + expect(0, []{return F::fcvt_l_s(numeric_limits::min());}, + "fcvt.l.s, underflow"); + expect(numeric_limits::max(), + []{return F::fcvt_l_s(numeric_limits::infinity());}, + "fcvt.l.s, infinity"); + expect(numeric_limits::min(), + []{return F::fcvt_l_s(-numeric_limits::infinity());}, + "fcvt.l.s, -infinity"); + expect(numeric_limits::max(), + []{return F::fcvt_l_s(numeric_limits::quiet_NaN());}, + "fcvt.l.s, quiet NaN"); + expect(numeric_limits::max(), + []{return F::fcvt_l_s(-numeric_limits::quiet_NaN());}, + "fcvt.l.s, quiet -NaN"); + expect(numeric_limits::max(), + []{return F::fcvt_l_s(numeric_limits::signaling_NaN());}, + "fcvt.l.s, signaling NaN"); + + // FCVT.LU.S + expect(256, []{return F::fcvt_lu_s(256.3);}, + "fcvt.lu.s, truncate positive"); + expect(0, []{return F::fcvt_lu_s(-256.2);}, + "fcvt.lu.s, truncate negative"); + expect(0, []{return F::fcvt_lu_s(0.0);}, "fcvt.lu.s, 0.0"); + expect(0, []{return F::fcvt_lu_s(-0.0);}, "fcvt.lu.s, -0.0"); + expect(8589934592LL, + []{return F::fcvt_lu_s(8589934592.0);}, + "fcvt.lu.s, 32-bit overflow"); + expect(numeric_limits::max(), + []{return F::fcvt_lu_s(numeric_limits::max());}, + "fcvt.lu.s, overflow"); + expect(0, []{return F::fcvt_lu_s(numeric_limits::min());}, + "fcvt.lu.s, underflow"); + expect(numeric_limits::max(), + []{return F::fcvt_lu_s(numeric_limits::infinity());}, + "fcvt.lu.s, infinity"); + expect(0, + []{return F::fcvt_lu_s(-numeric_limits::infinity());}, + "fcvt.lu.s, -infinity"); + expect(0xFFFFFFFFFFFFFFFFULL, + []{return F::fcvt_lu_s(numeric_limits::quiet_NaN());}, + "fcvt.lu.s, quiet NaN"); + expect(0xFFFFFFFFFFFFFFFFULL, + []{return F::fcvt_lu_s(-numeric_limits::quiet_NaN());}, + "fcvt.lu.s, quiet -NaN"); + expect(0xFFFFFFFFFFFFFFFFULL, + []{return F::fcvt_lu_s(numeric_limits::signaling_NaN());}, + "fcvt.lu.s, signaling NaN"); + + // FCVT.S.L + expect(0.0, []{return F::fcvt_s_l(0);}, "fcvt.s.l, 0"); + expect(-9.223372e18, + []{return F::fcvt_s_l(numeric_limits::min());}, + "fcvt.s.l, negative"); + expect(-4.29496704e9, []{return F::fcvt_s_l(0xFFFFFFFF000000FFLL);}, + "fcvt.s.l, 32-bit truncate"); + + // FCVT.S.LU + expect(0.0, []{return F::fcvt_s_lu(0);}, "fcvt.s.lu, 0"); + expect(9.223372e18, + []{return F::fcvt_s_lu(numeric_limits::min());}, + "fcvt.s.lu"); + expect(1.8446744e19, []{return F::fcvt_s_lu(0xFFFFFFFF000000FFLL);}, + "fcvt.s.lu, 32-bit truncate"); + + return 0; +} diff -r 8aec19bd88f8 -r ea40d2a41efb tests/test-progs/insttest/src/riscv/rv64i.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/test-progs/insttest/src/riscv/rv64i.h Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,440 @@ +/* + * Copyright (c) 2016 The University of Virginia + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Alec Roelke + */ + +#pragma once + +#include +#include + +#include "insttest.h" + +namespace I +{ + +inline uint64_t +lui(const uint32_t imm) +{ + int64_t rd = -1; + asm volatile("lui %0,%1" : "=r" (rd) : "i" (imm)); + return rd; +} + +inline bool +auipc(const uint64_t imm) +{ + int64_t rd = -1; + asm volatile("auipc %0,%1" : "=r" (rd) : "i" (imm)); + std::cout << "auipc: 0x" << std::hex << std::uppercase << rd << + std::nouppercase << std::dec << std::endl; + return rd >= imm; +} + +inline bool +jal() +{ + asm volatile goto("jal zero,%l[jallabel]" : : : : jallabel); + return false; + jallabel: + return true; +} + +inline bool +jalr() +{ + int a = 0; + asm volatile("auipc %0,0;" + "jalr t0,%0,12;" + "addi %0,zero,0;" + "sub %0,t0,%0;" + : "+r" (a) + : + : "t0"); + return a == 8; +} + +inline bool +beq(int64_t a, int64_t b) +{ + asm volatile goto("beq %0,%1,%l[beqlabel]" + : + : "r" (a), "r" (b) + : + : beqlabel); + return false; + beqlabel: + return true; +} + +inline bool +bne(int64_t a, int64_t b) +{ + asm volatile goto("bne %0,%1,%l[bnelabel]" + : + : "r" (a), "r" (b) + : + : bnelabel); + return false; + bnelabel: + return true; +} + +inline bool +blt(int64_t a, int64_t b) +{ + asm volatile goto("blt %0,%1,%l[bltlabel]" + : + : "r" (a), "r" (b) + : + : bltlabel); + return false; + bltlabel: + return true; +} + +inline bool +bge(int64_t a, int64_t b) +{ + asm volatile goto("bge %0,%1,%l[bgelabel]" + : + : "r" (a), "r" (b) + : + : bgelabel); + return false; + bgelabel: + return true; +} + +inline bool +bltu(uint64_t a, uint64_t b) +{ + asm volatile goto("bltu %0,%1,%l[bltulabel]" + : + : "r" (a), "r" (b) + : + : bltulabel); + return false; + bltulabel: + return true; +} + +inline bool +bgeu(uint64_t a, uint64_t b) +{ + asm volatile goto("bgeu %0,%1,%l[bgeulabel]" + : + : "r" (a), "r" (b) + : + : bgeulabel); + return false; + bgeulabel: + return true; +} + +template inline R +load(const M& b) +{ + R a = 0; + switch(sizeof(M)) + { + case 1: + if (std::is_signed::value) { + asm volatile("lb %0,%1" : "=r" (a) : "m" (b)); + } else { + asm volatile("lbu %0,%1" : "=r" (a) : "m" (b)); + } + break; + case 2: + if (std::is_signed::value) { + asm volatile("lh %0,%1" : "=r" (a) : "m" (b)); + } else { + asm volatile("lhu %0,%1" : "=r" (a) : "m" (b)); + } + break; + case 4: + if (std::is_signed::value) { + asm volatile("lw %0,%1" : "=r" (a) : "m" (b)); + } else { + asm volatile("lwu %0,%1" : "=r" (a) : "m" (b)); + } + break; + case 8: + asm volatile("ld %0,%1" : "=r" (a) : "m" (b)); + break; + } + return a; +} + +template inline M +store(const M& rs2) +{ + M mem = 0; + switch (sizeof(M)) + { + case 1: + asm volatile("sb %1,%0" : "=m" (mem) : "r" (rs2)); + break; + case 2: + asm volatile("sh %1,%0" : "=m" (mem) : "r" (rs2)); + break; + case 4: + asm volatile("sw %1,%0" : "=m" (mem) : "r" (rs2)); + break; + case 8: + asm volatile("sd %1,%0" : "=m" (mem) : "r" (rs2)); + break; + } + return mem; +} + +inline int64_t +addi(int64_t rs1, const int16_t imm) +{ + int64_t rd = 0; + IOP("addi", rd, rs1, imm); + return rd; +} + +inline bool +slti(int64_t rs1, const int16_t imm) +{ + bool rd = false; + IOP("slti", rd, rs1, imm); + return rd; +} + +inline bool +sltiu(uint64_t rs1, const uint16_t imm) +{ + bool rd = false; + IOP("sltiu", rd, rs1, imm); + return rd; +} + +inline uint64_t +xori(uint64_t rs1, const uint16_t imm) +{ + uint64_t rd = 0; + IOP("xori", rd, rs1, imm); + return rd; +} + +inline uint64_t +ori(uint64_t rs1, const uint16_t imm) +{ + uint64_t rd = 0; + IOP("ori", rd, rs1, imm); + return rd; +} + +inline uint64_t +andi(uint64_t rs1, const uint16_t imm) +{ + uint64_t rd = 0; + IOP("andi", rd, rs1, imm); + return rd; +} + +inline int64_t +slli(int64_t rs1, const uint16_t imm) +{ + int64_t rd = 0; + IOP("slli", rd, rs1, imm); + return rd; +} + +inline uint64_t +srli(uint64_t rs1, const uint16_t imm) +{ + uint64_t rd = 0; + IOP("srli", rd, rs1, imm); + return rd; +} + +inline int64_t +srai(int64_t rs1, const uint16_t imm) +{ + int64_t rd = 0; + IOP("srai", rd, rs1, imm); + return rd; +} + +inline int64_t +add(int64_t rs1, int64_t rs2) +{ + int64_t rd = 0; + ROP("add", rd, rs1, rs2); + return rd; +} + +inline int64_t +sub(int64_t rs1, int64_t rs2) +{ + int64_t rd = 0; + ROP("sub", rd, rs1, rs2); + return rd; +} + +inline int64_t +sll(int64_t rs1, int64_t rs2) +{ + int64_t rd = 0; + ROP("sll", rd, rs1, rs2); + return rd; +} + +inline bool +slt(int64_t rs1, int64_t rs2) +{ + bool rd = false; + ROP("slt", rd, rs1, rs2); + return rd; +} + +inline bool +sltu(uint64_t rs1, uint64_t rs2) +{ + bool rd = false; + ROP("sltu", rd, rs1, rs2); + return rd; +} + +inline uint64_t +xor_inst(uint64_t rs1, uint64_t rs2) +{ + uint64_t rd = 0; + ROP("xor", rd, rs1, rs2); + return rd; +} + +inline uint64_t +srl(uint64_t rs1, uint64_t rs2) +{ + uint64_t rd = 0; + ROP("srl", rd, rs1, rs2); + return rd; +} + +inline int64_t +sra(int64_t rs1, int64_t rs2) +{ + int64_t rd = 0; + ROP("sra", rd, rs1, rs2); + return rd; +} + +inline uint64_t +or_inst(uint64_t rs1, uint64_t rs2) +{ + uint64_t rd = 0; + ROP("or", rd, rs1, rs2); + return rd; +} + +inline uint64_t +and_inst(uint64_t rs1, uint64_t rs2) +{ + uint64_t rd = 0; + ROP("and", rd, rs1, rs2); + return rd; +} + +inline int64_t +addiw(int64_t rs1, const int16_t imm) +{ + int64_t rd = 0; + IOP("addiw", rd, rs1, imm); + return rd; +} + +inline int64_t +slliw(int64_t rs1, const uint16_t imm) +{ + int64_t rd = 0; + IOP("slliw", rd, rs1, imm); + return rd; +} + +inline uint64_t +srliw(uint64_t rs1, const uint16_t imm) +{ + uint64_t rd = 0; + IOP("srliw", rd, rs1, imm); + return rd; +} + +inline int64_t +sraiw(int64_t rs1, const uint16_t imm) +{ + int64_t rd = 0; + IOP("sraiw", rd, rs1, imm); + return rd; +} + +inline int64_t +addw(int64_t rs1, int64_t rs2) +{ + int64_t rd = 0; + ROP("addw", rd, rs1, rs2); + return rd; +} + +inline int64_t +subw(int64_t rs1, int64_t rs2) +{ + int64_t rd = 0; + ROP("subw", rd, rs1, rs2); + return rd; +} + +inline int64_t +sllw(int64_t rs1, int64_t rs2) +{ + int64_t rd = 0; + ROP("sllw", rd, rs1, rs2); + return rd; +} + +inline uint64_t +srlw(uint64_t rs1, uint64_t rs2) +{ + uint64_t rd = 0; + ROP("srlw", rd, rs1, rs2); + return rd; +} + +inline int64_t +sraw(int64_t rs1, int64_t rs2) +{ + int64_t rd = 0; + ROP("sraw", rd, rs1, rs2); + return rd; +} + +} // namespace I diff -r 8aec19bd88f8 -r ea40d2a41efb tests/test-progs/insttest/src/riscv/rv64i.cpp --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/test-progs/insttest/src/riscv/rv64i.cpp Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,432 @@ +/* + * Copyright (c) 2016 The University of Virginia + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Alec Roelke + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "insttest.h" +#include "rv64i.h" + +int main() +{ + using namespace std; + using namespace insttest; + + // LUI + expect(4096, []{return I::lui(1);}, "lui"); + expect(numeric_limits::min(), + []{return I::lui(0x80000);}, "lui, negative"); + + // AUIPC + expect(true, []{return I::auipc(3);}, "auipc"); + + // Jump (JAL, JALR) + expect(true, []{return I::jal();}, "jal"); + expect(true, []{return I::jalr();}, "jalr"); + + // BEQ + expect(true, []{return I::beq(5, 5);}, "beq, equal"); + expect(false, []{return I::beq(numeric_limits::max(), + numeric_limits::min());}, "beq, not equal"); + + // BNE + expect(false, []{return I::bne(5, 5);}, "bne, equal"); + expect(true, []{return I::bne(numeric_limits::max(), + numeric_limits::min());}, "bne, not equal"); + + // BLT + expect(true, []{return I::blt(numeric_limits::min(), + numeric_limits::max());}, "blt, less"); + expect(false, []{return I::blt(numeric_limits::min(), + numeric_limits::min());}, "blt, equal"); + expect(false, []{return I::blt(numeric_limits::max(), + numeric_limits::min());}, "blt, greater"); + + // BGE + expect(false, []{return I::bge(numeric_limits::min(), + numeric_limits::max());}, "bge, less"); + expect(true, []{return I::bge(numeric_limits::min(), + numeric_limits::min());}, "bge, equal"); + expect(true, []{return I::bge(numeric_limits::max(), + numeric_limits::min());}, "bge, greater"); + + // BLTU + expect(true, []{return I::blt(numeric_limits::min(), + numeric_limits::max());}, "bltu, greater"); + expect(false, []{return I::blt(numeric_limits::min(), + numeric_limits::min());}, "bltu, equal"); + expect(false, []{return I::blt(numeric_limits::max(), + numeric_limits::min());}, "bltu, less"); + + // BGEU + expect(false, []{return I::bge(numeric_limits::min(), + numeric_limits::max());}, "bgeu, greater"); + expect(true, []{return I::bge(numeric_limits::min(), + numeric_limits::min());}, "bgeu, equal"); + expect(true, []{return I::bge(numeric_limits::max(), + numeric_limits::min());}, "bgeu, less"); + + // Load (LB, LH, LW, LBU, LHU) + expect(7, []{return I::load(0x07);}, + "lb, positive"); + expect(numeric_limits::min(), + []{return I::load(0x80);}, "lb, negative"); + expect(1792, []{return I::load(0x0700);}, + "lh, positive"); + expect(numeric_limits::min(), + []{return I::load(0x8000);}, "lh, negative"); + expect(458752, []{return I::load(0x00070000);}, + "lw, positive"); + expect(numeric_limits::min(), + []{return I::load(0x80000000);}, + "lw, negative"); + expect(128, []{return I::load(0x80);}, "lbu"); + expect(32768, []{return I::load(0x8000);}, + "lhu"); + + // Store (SB, SH, SW) + expect(0xFF, []{return I::store(-1);}, "sb"); + expect(0xFFFF, []{return I::store(-1);}, "sh"); + expect(0xFFFFFFFF, []{return I::store(-1);}, "sw"); + + // ADDI + expect(1073742078, []{return I::addi(0x3FFFFFFF, 255);}, + "addi"); + expect(1, []{return I::addi(-1, 2);}, "addi, overflow"); + + // SLTI + expect(true, []{return I::slti(-1, 0);}, "slti, true"); + expect(false, []{return I::slti(0, -1);}, "slti, false"); + + // SLTIU + expect(false, []{return I::sltiu(-1, 0);}, "sltiu, false"); + expect(true, []{return I::sltiu(0, -1);}, "sltiu, true"); + + // XORI + expect(0xFF, []{return I::xori(0xAA, 0x55);}, "xori (1)"); + expect(0, []{return I::xori(0xAA, 0xAA);}, "xori (0)"); + + // ORI + expect(0xFF, []{return I::ori(0xAA, 0x55);}, "ori (1)"); + expect(0xAA, []{return I::ori(0xAA, 0xAA);}, "ori (A)"); + + // ANDI + expect(0, []{return I::andi(-1, 0);}, "andi (0)"); + expect(0x1234567812345678ULL, + []{return I::andi(0x1234567812345678ULL, -1);}, "andi (1)"); + + // SLLI + expect(65280, []{return I::slli(255, 8);}, "slli, general"); + expect(numeric_limits::min(), + []{return I::slli(255, 63);}, "slli, erase"); + + // SRLI + expect(255, []{return I::srli(65280, 8);}, "srli, general"); + expect(0, []{return I::srli(255, 8);}, "srli, erase"); + expect(1, []{return I::srli(numeric_limits::min(), 63);}, + "srli, negative"); + + // SRAI + expect(255, []{return I::srai(65280, 8);}, "srai, general"); + expect(0, []{return I::srai(255, 8);}, "srai, erase"); + expect(-1, + []{return I::srai(numeric_limits::min(), 63);}, + "srai, negative"); + + // ADD + expect(1073742078, []{return I::add(0x3FFFFFFF, 255);}, "add"); + expect(-1, + []{return I::add(0x7FFFFFFFFFFFFFFFLL, 0x8000000000000000LL);}, + "add, overflow"); + + // SUB + expect(65535, []{return I::sub(65536, 1);}, "sub"); + expect(-1, + []{return I::sub(0x7FFFFFFFFFFFFFFFLL, 0x8000000000000000LL);}, + "sub, \"overflow\""); + + // SLL + expect(65280, []{return I::sll(255, 8);}, "sll, general"); + expect(numeric_limits::min(), + []{return I::sll(255, 63);}, "sll, erase"); + + // SLT + expect(true, []{return I::slt(-1, 0);}, "slt, true"); + expect(false, []{return I::slt(0, -1);}, "slt, false"); + + // SLTU + expect(false, []{return I::sltu(-1, 0);}, "sltu, false"); + expect(true, []{return I::sltu(0, -1);}, "sltu, true"); + + // XOR + expect(-1, + []{return I::xor_inst(0xAAAAAAAAAAAAAAAAULL, + 0x5555555555555555ULL);}, + "xor (1)"); + expect(0, + []{return I::xor_inst(0xAAAAAAAAAAAAAAAAULL, + 0xAAAAAAAAAAAAAAAAULL);}, + "xor (0)"); + + // SRL + expect(255, []{return I::srl(65280, 8);}, "srl, general"); + expect(0, []{return I::srl(255, 8);}, "srl, erase"); + expect(1, []{return I::srl(numeric_limits::min(), 63);}, + "srl, negative"); + + // SRA + expect(255, []{return I::sra(65280, 8);}, "sra, general"); + expect(0, []{return I::sra(255, 8);}, "sra, erase"); + expect(-1, []{return I::sra(numeric_limits::min(), 63);}, + "sra, negative"); + + // OR + expect(-1, + []{return I::or_inst(0xAAAAAAAAAAAAAAAAULL, + 0x5555555555555555ULL);}, + "or (1)"); + expect(0xAAAAAAAAAAAAAAAAULL, + []{return I::or_inst(0xAAAAAAAAAAAAAAAAULL, + 0xAAAAAAAAAAAAAAAAULL);}, + "or (A)"); + + // AND + expect(0, []{return I::and_inst(-1, 0);}, "and (0)"); + expect(0x1234567812345678ULL, + []{return I::and_inst(0x1234567812345678ULL, -1);}, "and (-1)"); + + // FENCE/FENCE.I + asm volatile("fence" : : ); + asm volatile("fence.i" : : ); + + // ECALL + char fname[] = "test.txt"; + char teststr[] = "this is a test"; + expect(true, [=]{ + int fd = open(fname, O_CREAT | O_WRONLY | O_TRUNC, 0644); + if (fd < 0) { + return false; + } + size_t n = write(fd, teststr, sizeof(teststr)); + cout << "Bytes written: " << n << endl; + return close(fd) >= 0 && n > 0; + }, "open, write"); + expect(0, [=]{return access(fname, F_OK);}, "access F_OK"); + expect(0, [=]{return access(fname, R_OK);}, "access R_OK"); + expect(0, [=]{return access(fname, W_OK);}, "access W_OK"); + // gem5's implementation of access is incorrect; it should return + // -1 on failure, not -errno. Account for this using an inequality. + expect(true, [=]{return access(fname, X_OK) != 0;}, "access X_OK"); + expect(true, [=]{ + struct stat stat_buf, fstat_buf; + int s = stat(fname, &stat_buf); + if (s < 0) { + return false; + } else { + cout << "stat:" << endl; + cout << "\tst_dev =\t" << stat_buf.st_dev << endl; + cout << "\tst_ino =\t" << stat_buf.st_ino << endl; + cout << "\tst_mode =\t" << stat_buf.st_mode << endl; + cout << "\tst_nlink =\t" << stat_buf.st_nlink << endl; + cout << "\tst_uid =\t" << stat_buf.st_uid << endl; + cout << "\tst_gid =\t" << stat_buf.st_gid << endl; + cout << "\tst_rdev =\t" << stat_buf.st_rdev << endl; + cout << "\tst_size =\t" << stat_buf.st_size << endl; + cout << "\tst_blksize =\t" << stat_buf.st_blksize << endl; + cout << "\tst_blocks =\t" << stat_buf.st_blocks << endl; + } + int fd = open(fname, O_RDONLY); + if (fd < 0) { + return false; + } + int f = fstat(fd, &fstat_buf); + if (f >= 0) { + cout << "fstat:" << endl; + cout << "\tst_dev =\t" << fstat_buf.st_dev << endl; + cout << "\tst_ino =\t" << fstat_buf.st_ino << endl; + cout << "\tst_mode =\t" << fstat_buf.st_mode << endl; + cout << "\tst_nlink =\t" << fstat_buf.st_nlink << endl; + cout << "\tst_uid =\t" << fstat_buf.st_uid << endl; + cout << "\tst_gid =\t" << fstat_buf.st_gid << endl; + cout << "\tst_rdev =\t" << fstat_buf.st_rdev << endl; + cout << "\tst_size =\t" << fstat_buf.st_size << endl; + cout << "\tst_blksize =\t" << fstat_buf.st_blksize << endl; + cout << "\tst_blocks =\t" << fstat_buf.st_blocks << endl; + } + return close(fd) >= 0 && f >= 0; + }, "open, stat"); + expect(true, [=]{ + int fd = open(fname, O_RDONLY); + if (fd < 0) { + return false; + } + char in[128]; + size_t n = read(fd, in, sizeof(in)); + cout << "Bytes read: " << n << endl; + cout << "String read: " << in << endl; + int cl = close(fd); + int un = unlink(fname); + return n > 0 && cl >= 0 && un >= 0 && strcmp(teststr, in) == 0; + }, "open, read, unlink"); + expect(true, []{ + struct tms buf; + clock_t t = times(&buf); + cout << "times:" << endl; + cout << "\ttms_utime =\t" << buf.tms_utime << endl; + cout << "\ttms_stime =\t" << buf.tms_stime << endl; + cout << "\ttms_cutime =\t" << buf.tms_cutime << endl; + cout << "\ttms_cstime =\t" << buf.tms_cstime << endl; + return t > 0; + }, "times"); + expect(0, []{ + struct timeval time; + int res = gettimeofday(&time, nullptr); + cout << "timeval:" << endl; + cout << "\ttv_sec =\t" << time.tv_sec << endl; + cout << "\ttv_usec =\t" << time.tv_usec << endl; + return res; + }, "gettimeofday"); + + // EBREAK not tested because it only makes sense in FS mode or when + // using gdb + + // ERET not tested because it only makes sense in FS mode and will cause + // a panic when used in SE mode + + // CSRs (RDCYCLE, RDTIME, RDINSTRET) + expect(true, []{ + uint64_t cycles = 0; + asm("rdcycle %0" : "=r" (cycles)); + cout << "Cycles: " << cycles << endl; + return cycles > 0; + }, "rdcycle"); + expect(true, []{ + uint64_t time = 0; + asm("rdtime %0" : "=r" (time)); + cout << "Time: " << time << endl; + return time > 0; + }, "rdtime"); + expect(true, []{ + uint64_t instret = 0; + asm("rdinstret %0" : "=r" (instret)); + cout << "Instructions Retired: " << instret << endl; + return instret > 0; + }, "rdinstret"); + + // 64-bit memory (LWU, LD, SD) + expect(0xFFFFFFFF, []{return I::load(-1);}, + "lwu"); + expect(30064771072, + []{return I::load(30064771072);}, "ld"); + expect(-1, []{return I::store(-1);}, "sd"); + + // ADDIW + expect(268435710, []{return I::addiw(0x0FFFFFFF, 255);}, "addiw"); + expect(-2147481602, []{return I::addiw(0x7FFFFFFF, 0x7FF);}, + "addiw, overflow"); + expect(0, []{return I::addiw(0x7FFFFFFFFFFFFFFFLL, 1);}, + "addiw, truncate"); + + // SLLIW + expect(65280, []{return I::slliw(255, 8);}, "slliw, general"); + expect(numeric_limits::min(), + []{return I::slliw(255, 31);}, "slliw, erase"); + expect(numeric_limits::min(), + []{return I::slliw(0xFFFFFFFF00800000LL, 8);}, "slliw, truncate"); + + // SRLIW + expect(255, []{return I::srliw(65280, 8);}, "srliw, general"); + expect(0, []{return I::srliw(255, 8);}, "srliw, erase"); + expect(1, + []{return I::srliw(numeric_limits::min(), 31);}, + "srliw, negative"); + expect(1, []{return I::srliw(0xFFFFFFFF80000000LL, 31);}, + "srliw, truncate"); + + // SRAIW + expect(255, []{return I::sraiw(65280, 8);}, "sraiw, general"); + expect(0, []{return I::sraiw(255, 8);}, "sraiw, erase"); + expect(-1, + []{return I::sraiw(numeric_limits::min(), 31);}, + "sraiw, negative"); + expect(-1, []{return I::sraiw(0x0000000180000000LL, 31);}, + "sraiw, truncate"); + + // ADDW + expect(1073742078, []{return I::addw(0x3FFFFFFF, 255);}, "addw"); + expect(-1, []{return I::addw(0x7FFFFFFF, 0x80000000);}, + "addw, overflow"); + expect(65536, []{return I::addw(0xFFFFFFFF0000FFFFLL, 1);}, + "addw, truncate"); + + // SUBW + expect(65535, []{return I::subw(65536, 1);}, "subw"); + expect(-1, []{return I::subw(0x7FFFFFFF, 0x80000000);}, + "subw, \"overflow\""); + expect(0, + []{return I::subw(0xAAAAAAAAFFFFFFFFULL, 0x55555555FFFFFFFFULL);}, + "subw, truncate"); + + // SLLW + expect(65280, []{return I::sllw(255, 8);}, "sllw, general"); + expect(numeric_limits::min(), + []{return I::sllw(255, 31);}, "sllw, erase"); + expect(numeric_limits::min(), + []{return I::sllw(0xFFFFFFFF00008000LL, 16);}, "sllw, truncate"); + + // SRLW + expect(255, []{return I::srlw(65280, 8);}, "srlw, general"); + expect(0, []{return I::srlw(255, 8);}, "srlw, erase"); + expect(1, + []{return I::srlw(numeric_limits::min(), 31);}, + "srlw, negative"); + expect(1, []{return I::srlw(0x0000000180000000LL, 31);}, + "srlw, truncate"); + + // SRAW + expect(255, []{return I::sraw(65280, 8);}, "sraw, general"); + expect(0, []{return I::sraw(255, 8);}, "sraw, erase"); + expect(-1, + []{return I::sraw(numeric_limits::min(), 31);}, + "sraw, negative"); + expect(1, []{return I::sraw(0xFFFFFFFF40000000LL, 30);}, + "sraw, truncate"); + + return 0; +} diff -r 8aec19bd88f8 -r ea40d2a41efb tests/test-progs/insttest/src/riscv/rv64m.h --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/test-progs/insttest/src/riscv/rv64m.h Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,144 @@ +/* + * Copyright (c) 2016 The University of Virginia + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Alec Roelke + */ + +#pragma once + +#include + +#include "insttest.h" + +namespace M +{ + +inline int64_t +mul(int64_t rs1, int64_t rs2) +{ + int64_t rd = 0; + ROP("mul", rd, rs1, rs2); + return rd; +} + +inline int64_t +mulh(int64_t rs1, int64_t rs2) +{ + int64_t rd = 0; + ROP("mulh", rd, rs1, rs2); + return rd; +} + +inline int64_t +mulhsu(int64_t rs1, uint64_t rs2) +{ + int64_t rd = 0; + ROP("mulhsu", rd, rs1, rs2); + return rd; +} + +inline uint64_t +mulhu(uint64_t rs1, uint64_t rs2) +{ + uint64_t rd = 0; + ROP("mulhu", rd, rs1, rs2); + return rd; +} + +inline int64_t +div(int64_t rs1, int64_t rs2) +{ + int64_t rd = 0; + ROP("div", rd, rs1, rs2); + return rd; +} + +inline uint64_t +divu(uint64_t rs1, uint64_t rs2) +{ + uint64_t rd = 0; + ROP("divu", rd, rs1, rs2); + return rd; +} + +inline int64_t +rem(int64_t rs1, int64_t rs2) +{ + int64_t rd = 0; + ROP("rem", rd, rs1, rs2); + return rd; +} + +inline uint64_t +remu(uint64_t rs1, uint64_t rs2) +{ + uint64_t rd = 0; + ROP("remu", rd, rs1, rs2); + return rd; +} + +inline int64_t +mulw(int64_t rs1, int64_t rs2) +{ + int64_t rd = 0; + ROP("mulw", rd, rs1, rs2); + return rd; +} + +inline int64_t +divw(int64_t rs1, int64_t rs2) +{ + int64_t rd = 0; + ROP("divw", rd, rs1, rs2); + return rd; +} + +inline uint64_t +divuw(uint64_t rs1, uint64_t rs2) +{ + uint64_t rd = 0; + ROP("divuw", rd, rs1, rs2); + return rd; +} + +inline int64_t +remw(int64_t rs1, int64_t rs2) +{ + int64_t rd = 0; + ROP("remw", rd, rs1, rs2); + return rd; +} + +inline uint64_t +remuw(uint64_t rs1, uint64_t rs2) +{ + uint64_t rd = 0; + ROP("remuw", rd, rs1, rs2); + return rd; +} + +} // namespace M diff -r 8aec19bd88f8 -r ea40d2a41efb tests/test-progs/insttest/src/riscv/rv64m.cpp --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/test-progs/insttest/src/riscv/rv64m.cpp Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,143 @@ +/* + * Copyright (c) 2016 The University of Virginia + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Alec Roelke + */ + +#include +#include + +#include "insttest.h" +#include "rv64m.h" + +int main() +{ + using namespace std; + using namespace insttest; + + // MUL + expect(39285, []{return M::mul(873, 45);}, "mul"); + expect(0, []{return M::mul(0x4000000000000000LL, 4);}, + "mul, overflow"); + + // MULH + expect(1, []{return M::mulh(0x4000000000000000LL, 4);}, "mulh"); + expect(-1, []{return M::mulh(numeric_limits::min(), 2);}, + "mulh, negative"); + expect(0, []{return M::mulh(-1, -1);}, "mulh, all bits set"); + + // MULHSU + expect(-1, []{return M::mulhsu(-1, -1);}, "mulhsu, all bits set"); + expect(-1, + []{return M::mulhsu(numeric_limits::min(), 2);},\ + "mulhsu"); + + // MULHU + expect(1, []{return M::mulhu(0x8000000000000000ULL, 2);}, + "mulhu"); + expect(0xFFFFFFFFFFFFFFFEULL, []{return M::mulhu(-1, -1);}, + "mulhu, all bits set"); + + // DIV + expect(-7, []{return M::div(-59, 8);}, "div"); + expect(-1, []{return M::div(255, 0);}, "div/0"); + expect(numeric_limits::min(), + []{return M::div(numeric_limits::min(), -1);}, + "div, overflow"); + + // DIVU + expect(2305843009213693944LL, []{return M::divu(-59, 8);}, + "divu"); + expect(numeric_limits::max(), + []{return M::divu(255, 0);}, "divu/0"); + expect(0, + []{return M::divu(numeric_limits::min(), -1);}, + "divu, \"overflow\""); + + // REM + expect(-3, []{return M::rem(-59, 8);}, "rem"); + expect(255, []{return M::rem(255, 0);}, "rem/0"); + expect(0, []{return M::rem(numeric_limits::min(), -1);}, + "rem, overflow"); + + // REMU + expect(5, []{return M::remu(-59, 8);}, "remu"); + expect(255, []{return M::remu(255, 0);}, "remu/0"); + expect(0x8000000000000000ULL, + []{return M::remu(0x8000000000000000ULL, -1);}, + "remu, \"overflow\""); + + // MULW + expect(-100, + []{return M::mulw(0x7FFFFFFF00000005LL, 0x80000000FFFFFFECLL);}, + "mulw, truncate"); + expect(0, []{return M::mulw(0x40000000, 4);}, "mulw, overflow"); + + // DIVW + expect(-7, + []{return M::divw(0x7FFFFFFFFFFFFFC5LL, 0xFFFFFFFF00000008LL);}, + "divw, truncate"); + expect(-1, []{return M::divw(65535, 0);}, "divw/0"); + expect(numeric_limits::min(), + []{return M::divw(numeric_limits::min(), -1);}, + "divw, overflow"); + + // DIVUW + expect(536870904, + []{return M::divuw(0x7FFFFFFFFFFFFFC5LL, 0xFFFFFFFF00000008LL);}, + "divuw, truncate"); + expect(numeric_limits::max(), + []{return M::divuw(65535, 0);}, "divuw/0"); + expect(0, + []{return M::divuw(numeric_limits::min(), -1);}, + "divuw, \"overflow\""); + expect(-1, + []{return M::divuw(numeric_limits::max(), 1);}, + "divuw, sign extend"); + + // REMW + expect(-3, + []{return M::remw(0x7FFFFFFFFFFFFFC5LL, 0xFFFFFFFF00000008LL);}, + "remw, truncate"); + expect(65535, []{return M::remw(65535, 0);}, "remw/0"); + expect(0, []{return M::remw(numeric_limits::min(), -1);}, + "remw, overflow"); + + // REMUW + expect(5, + []{return M::remuw(0x7FFFFFFFFFFFFFC5LL, 0xFFFFFFFF00000008LL);}, + "remuw, truncate"); + expect(65535, []{return M::remuw(65535, 0);}, "remuw/0"); + expect(numeric_limits::min(), + []{return M::remuw(numeric_limits::min(), -1);}, + "remuw, \"overflow\""); + expect(0xFFFFFFFF80000000, + []{return M::remuw(0x80000000, 0xFFFFFFFF);}, + "remuw, sign extend"); + + return 0; +} diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64i/o3-timing/simerr --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/o3-timing/simerr Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,40 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick +gem5.debug: build/RISCV/mem/page_table.cc:187: Fault PageTableBase::translate(RequestPtr): Assertion `pageAlign(req->getVaddr() + req->getSize() - 1) == pageAlign(req->getVaddr())' failed. +Program aborted at tick 64441500 +--- BEGIN LIBC BACKTRACE --- +/home/ar4jc/gem5/build/RISCV/gem5.debug(_Z15print_backtracev+0x32)[0xdabf60] +/home/ar4jc/gem5/build/RISCV/gem5.debug(_Z12abortHandleri+0x6e)[0xdc356a] +/lib/x86_64-linux-gnu/libpthread.so.0(+0x113e0)[0x7f76cc4193e0] +/lib/x86_64-linux-gnu/libc.so.6(gsignal+0x38)[0x7f76cadfd428] +/lib/x86_64-linux-gnu/libc.so.6(abort+0x16a)[0x7f76cadff02a] +/lib/x86_64-linux-gnu/libc.so.6(+0x2dbd7)[0x7f76cadf5bd7] +/lib/x86_64-linux-gnu/libc.so.6(+0x2dc82)[0x7f76cadf5c82] +/home/ar4jc/gem5/build/RISCV/gem5.debug(_ZN13PageTableBase9translateEP7Request+0x98)[0xc31106] +/home/ar4jc/gem5/build/RISCV/gem5.debug(_ZN8RiscvISA3TLB13translateDataEP7RequestP13ThreadContextb+0x98)[0xd63946] +/home/ar4jc/gem5/build/RISCV/gem5.debug(_ZN8RiscvISA3TLB15translateAtomicEP7RequestP13ThreadContextN7BaseTLB4ModeE+0x70)[0xd63a18] +/home/ar4jc/gem5/build/RISCV/gem5.debug(_ZN8RiscvISA3TLB15translateTimingEP7RequestP13ThreadContextPN7BaseTLB11TranslationENS5_4ModeE+0x78)[0xd63aaa] +/home/ar4jc/gem5/build/RISCV/gem5.debug(_ZN11BaseDynInstI9O3CPUImplE19initiateTranslationEP7RequestS3_S3_PmN7BaseTLB4ModeE+0xf9)[0xfa9001] +/home/ar4jc/gem5/build/RISCV/gem5.debug(_ZN11BaseDynInstI9O3CPUImplE8writeMemEPhjm5FlagsIjEPm+0x243)[0xfa8bc9] +/home/ar4jc/gem5/build/RISCV/gem5.debug(_Z14writeMemTimingI11ExecContextmESt10shared_ptrI9FaultBaseEPT_PN5Trace10InstRecordET0_m5FlagsIjEPm+0x9d)[0x189efc5] +/home/ar4jc/gem5/build/RISCV/gem5.debug(_ZNK12RiscvISAInst2Sd11initiateAccEP11ExecContextPN5Trace10InstRecordE+0x101)[0x187a159] +/home/ar4jc/gem5/build/RISCV/gem5.debug(_ZN13BaseO3DynInstI9O3CPUImplE11initiateAccEv+0x70)[0xfdac52] +/home/ar4jc/gem5/build/RISCV/gem5.debug(_ZN7LSQUnitI9O3CPUImplE12executeStoreER14RefCountingPtrI13BaseO3DynInstIS0_EE+0x191)[0x100de09] +/home/ar4jc/gem5/build/RISCV/gem5.debug(_ZN3LSQI9O3CPUImplE12executeStoreER14RefCountingPtrI13BaseO3DynInstIS0_EE+0x6b)[0x10094c7] +/home/ar4jc/gem5/build/RISCV/gem5.debug(_ZN10DefaultIEWI9O3CPUImplE12executeInstsEv+0x67c)[0xff59d2] +/home/ar4jc/gem5/build/RISCV/gem5.debug(_ZN10DefaultIEWI9O3CPUImplE4tickEv+0x1a9)[0xff7775] +/home/ar4jc/gem5/build/RISCV/gem5.debug(_ZN9FullO3CPUI9O3CPUImplE4tickEv+0x155)[0xfc37e3] +/home/ar4jc/gem5/build/RISCV/gem5.debug(_ZN9FullO3CPUI9O3CPUImplE9TickEvent7processEv+0x1c)[0xfc7b14] +/home/ar4jc/gem5/build/RISCV/gem5.debug(_ZN10EventQueue10serviceOneEv+0xe9)[0xdbbc1d] +/home/ar4jc/gem5/build/RISCV/gem5.debug(_Z9doSimLoopP10EventQueue+0x1fa)[0xde66e9] +/home/ar4jc/gem5/build/RISCV/gem5.debug(_Z8simulatem+0x301)[0xde6345] +/home/ar4jc/gem5/build/RISCV/gem5.debug[0x109ab70] +/home/ar4jc/gem5/build/RISCV/gem5.debug[0x109ad64] +/usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x7852)[0x7f76cc6e6552] +/usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCodeEx+0x85c)[0x7f76cc81001c] +/usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x6ffd)[0x7f76cc6e5cfd] +/usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCodeEx+0x85c)[0x7f76cc81001c] +/usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x6ffd)[0x7f76cc6e5cfd] +--- END LIBC BACKTRACE --- diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64i/o3-timing/simout --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/o3-timing/simout Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,44 @@ +Redirecting stdout to build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64i/o3-timing/simout +Redirecting stderr to build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64i/o3-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 22 2016 16:06:54 +gem5 started Nov 28 2016 14:57:51 +gem5 executing on ubuntu1604, pid 8413 +command line: /home/ar4jc/gem5/build/RISCV/gem5.debug -d build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64i/o3-timing -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64i/o3-timing + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +lui: PASS +lui, negative: PASS +auipc: 0x157CC +auipc: PASS +jal: PASS +jalr: PASS +beq, equal: PASS +beq, not equal: PASS +bne, equal: PASS +bne, not equal: PASS +blt, less: PASS +blt, equal: PASS +blt, greater: PASS +bge, less: PASS +bge, equal: PASS +bge, greater: PASS +bltu, greater: PASS +bltu, equal: PASS +bltu, less: PASS +bgeu, greater: PASS +bgeu, equal: PASS +bgeu, less: PASS +lb, positive: PASS +lb, negative: PASS +lh, positive: PASS +lh, negative: PASS +lw, positive: PASS +lw, negative: PASS +lbu: PASS +lhu: PASS +sb: PASS diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/config.ini --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/config.ini Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,211 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=atomic +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=AtomicSimpleCPU +children=dtb interrupts isa itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fastmem=false +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +simulate_data_stalls=false +simulate_inst_stalls=false +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +width=1 +workload=system.cpu.workload +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64i/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +eventq_index=0 +in_addr_map=true +kvm_map=true +latency=30000 +latency_var=0 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +range=0:134217727:0:0:0:0 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/config.json --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/config.json Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,289 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.icache_port", + "system.cpu.dcache_port" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "physmem": { + "range": "0:134217727:0:0:0:0", + "latency": 30000, + "name": "physmem", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "kvm_map": true, + "clk_domain": "system.clk_domain", + "power_model": null, + "latency_var": 0, + "bandwidth": "73.000000", + "conf_table_reported": true, + "cxx_class": "SimpleMemory", + "p_state_clk_gate_max": 1000000000000, + "path": "system.physmem", + "null": false, + "type": "SimpleMemory", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "in_addr_map": true + }, + "power_model": null, + "work_cpus_ckpt_count": 0, + "thermal_components": [], + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "work_end_ckpt_count": 0, + "mem_mode": "atomic", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": [ + { + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.itb", + "type": "RiscvTLB", + "size": 64 + }, + "simulate_data_stalls": false, + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "AtomicSimpleCPU", + "max_loads_all_threads": 0, + "system": "system", + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "cpu_id": 0, + "width": 1, + "checker": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "do_quiesce": true, + "type": "AtomicSimpleCPU", + "fastmem": false, + "profile": 0, + "icache_port": { + "peer": "system.membus.slave[1]", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "p_state_clk_gate_min": 1000, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "dcache_port": { + "peer": "system.membus.slave[2]", + "role": "MASTER" + }, + "socket_id": 0, + "power_model": null, + "max_insts_all_threads": 0, + "path": "system.cpu", + "max_loads_any_thread": 0, + "switched_out": false, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64i/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "simulate_inst_stalls": false, + "progress_interval": 0, + "branchPred": null, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/simerr --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/simerr Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,3 @@ +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/simout --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/simout Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,171 @@ +Redirecting stdout to build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64i/simple-atomic/simout +Redirecting stderr to build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64i/simple-atomic/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 2 2016 20:34:02 +gem5 started Nov 3 2016 18:35:14 +gem5 executing on ubuntu1604, pid 21240 +command line: /home/ar4jc/gem5/build/RISCV/gem5.debug -d build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64i/simple-atomic -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64i/simple-atomic + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +lui: PASS +lui, negative: PASS +auipc: 0x157CC +auipc: PASS +jal: PASS +jalr: PASS +beq, equal: PASS +beq, not equal: PASS +bne, equal: PASS +bne, not equal: PASS +blt, less: PASS +blt, equal: PASS +blt, greater: PASS +bge, less: PASS +bge, equal: PASS +bge, greater: PASS +bltu, greater: PASS +bltu, equal: PASS +bltu, less: PASS +bgeu, greater: PASS +bgeu, equal: PASS +bgeu, less: PASS +lb, positive: PASS +lb, negative: PASS +lh, positive: PASS +lh, negative: PASS +lw, positive: PASS +lw, negative: PASS +lbu: PASS +lhu: PASS +sb: PASS +sh: PASS +sw: PASS +addi: PASS +addi, overflow: PASS +slti, true: PASS +slti, false: PASS +sltiu, false: PASS +sltiu, true: PASS +xori (1): PASS +xori (0): PASS +ori (1): PASS +ori (A): PASS +andi (0): PASS +andi (1): PASS +slli, general: PASS +slli, erase: PASS +srli, general: PASS +srli, erase: PASS +srli, negative: PASS +srai, general: PASS +srai, erase: PASS +srai, negative: PASS +add: PASS +add, overflow: PASS +sub: PASS +sub, "overflow": PASS +sll, general: PASS +sll, erase: PASS +slt, true: PASS +slt, false: PASS +sltu, false: PASS +sltu, true: PASS +xor (1): PASS +xor (0): PASS +srl, general: PASS +srl, erase: PASS +srl, negative: PASS +sra, general: PASS +sra, erase: PASS +sra, negative: PASS +or (1): PASS +or (A): PASS +and (0): PASS +and (-1): PASS +Bytes written: 15 +open, write: PASS +access F_OK: PASS +access R_OK: PASS +access W_OK: PASS +access X_OK: PASS +stat: + st_dev = 1696642673 + st_ino = 676985 + st_mode = 33188 + st_nlink = 1 + st_uid = 503 + st_gid = 503 + st_rdev = 0 + st_size = 15 + st_blksize = 8192 + st_blocks = 8 +fstat: + st_dev = 1696642673 + st_ino = 676985 + st_mode = 33188 + st_nlink = 1 + st_uid = 503 + st_gid = 503 + st_rdev = 0 + st_size = 15 + st_blksize = 8192 + st_blocks = 8 +open, stat: PASS +Bytes read: 15 +String read: this is a test +open, read, unlink: PASS +times: + tms_utime = 0 + tms_stime = 0 + tms_cutime = 0 + tms_cstime = 0 +times: PASS +timeval: + tv_sec = 1000000000 + tv_usec = 101 +gettimeofday: PASS +Cycles: 208590 +rdcycle: PASS +Time: 1478198119 +rdtime: PASS +Instructions Retired: 213528 +rdinstret: PASS +lwu: PASS +ld: PASS +sd: PASS +addiw: PASS +addiw, overflow: PASS +addiw, truncate: PASS +slliw, general: PASS +slliw, erase: PASS +slliw, truncate: PASS +srliw, general: PASS +srliw, erase: PASS +srliw, negative: PASS +srliw, truncate: PASS +sraiw, general: PASS +sraiw, erase: PASS +sraiw, negative: PASS +sraiw, truncate: PASS +addw: PASS +addw, overflow: PASS +addw, truncate: PASS +subw: PASS +subw, "overflow": PASS +subw, truncate: PASS +sllw, general: PASS +sllw, erase: PASS +sllw, truncate: PASS +srlw, general: PASS +srlw, erase: PASS +srlw, negative: PASS +srlw, truncate: PASS +sraw, general: PASS +sraw, erase: PASS +sraw, negative: PASS +sraw, truncate: PASS +Exiting @ tick 132332500 because target called exit() diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/stats.txt --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/stats.txt Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,153 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000132 # Number of seconds simulated +sim_ticks 132332500 # Number of ticks simulated +final_tick 132332500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 37215 # Simulator instruction rate (inst/s) +host_op_rate 37215 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 18620215 # Simulator tick rate (ticks/s) +host_mem_usage 265060 # Number of bytes of host memory used +host_seconds 7.11 # Real time elapsed on the host +sim_insts 264481 # Number of instructions simulated +sim_ops 264481 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 132332500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 1058664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 401325 # Number of bytes read from this memory +system.physmem.bytes_read::total 1459989 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1058664 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1058664 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 277820 # Number of bytes written to this memory +system.physmem.bytes_written::total 277820 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 264666 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 61526 # Number of read requests responded to by this memory +system.physmem.num_reads::total 326192 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 44701 # Number of write requests responded to by this memory +system.physmem.num_writes::total 44701 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 8000030227 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3032701717 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 11032731944 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8000030227 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8000030227 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 2099408686 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2099408686 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8000030227 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5132110404 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13132140631 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 132332500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 184 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 132332500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 264666 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 264481 # Number of instructions committed +system.cpu.committedOps 264481 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 264480 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 18966 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 39588 # number of instructions that are conditional controls +system.cpu.num_int_insts 264480 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 350083 # number of times the integer registers were read +system.cpu.num_int_register_writes 180190 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 106228 # number of memory refs +system.cpu.num_load_insts 61526 # Number of load instructions +system.cpu.num_store_insts 44702 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 264666 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 58554 # Number of branches fetched +system.cpu.op_class::No_OpClass 189 0.07% 0.07% # Class of executed instruction +system.cpu.op_class::IntAlu 157588 59.54% 59.61% # Class of executed instruction +system.cpu.op_class::IntMult 431 0.16% 59.78% # Class of executed instruction +system.cpu.op_class::IntDiv 230 0.09% 59.86% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 59.86% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 59.86% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 59.86% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 59.86% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 59.86% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 59.86% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 59.86% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 59.86% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 59.86% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 59.86% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 59.86% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 59.86% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 59.86% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 59.86% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 59.86% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 59.86% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 59.86% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 59.86% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 59.86% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 59.86% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 59.86% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 59.86% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 59.86% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 59.86% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 59.86% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 59.86% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 59.86% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 59.86% # Class of executed instruction +system.cpu.op_class::MemRead 61526 23.25% 83.11% # Class of executed instruction +system.cpu.op_class::MemWrite 44702 16.89% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 264666 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 132332500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 326192 # Transaction distribution +system.membus.trans_dist::ReadResp 326192 # Transaction distribution +system.membus.trans_dist::WriteReq 44701 # Transaction distribution +system.membus.trans_dist::WriteResp 44701 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 529332 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 212454 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 741786 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1058664 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 679145 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1737809 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 370893 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 370893 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 370893 # Request fanout histogram + +---------- End Simulation Statistics ---------- diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/config.ini --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/config.ini Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,1265 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 + +[system] +type=System +children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges=0:268435455:0:0:0:0 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.sys_port_proxy.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=TimingSimpleCPU +children=clk_domain dtb interrupts isa itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu.clk_domain +cpu_id=0 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1] +icache_port=system.ruby.l1_cntrl0.sequencer.slave[0] + +[system.cpu.clk_domain] +type=SrcClockDomain +clock=1 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64i/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000 + +[system.mem_ctrls] +type=DRAMCtrl +IDD0=0.055000 +IDD02=0.000000 +IDD2N=0.032000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.032000 +IDD2P12=0.000000 +IDD3N=0.038000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.038000 +IDD3P12=0.000000 +IDD4R=0.157000 +IDD4R2=0.000000 +IDD4W=0.125000 +IDD4W2=0.000000 +IDD5=0.235000 +IDD52=0.000000 +IDD6=0.020000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +page_policy=open_adaptive +power_model=Null +range=0:268435455:5:19:0:0 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10 +static_frontend_latency=10 +tBURST=5 +tCCD_L=0 +tCK=1 +tCL=14 +tCS=3 +tRAS=35 +tRCD=14 +tREFI=7800 +tRFC=260 +tRP=14 +tRRD=6 +tRRD_L=0 +tRTP=8 +tRTW=3 +tWR=15 +tWTR=8 +tXAW=30 +tXP=6 +tXPDLL=0 +tXS=270 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.ruby.dir_cntrl0.memory + +[system.ruby] +type=RubySystem +children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network +access_backing_store=false +all_instructions=false +block_size_bytes=64 +clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +hot_lines=false +memory_size_bits=48 +num_of_sequencers=1 +number_of_virtual_networks=5 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +phys_mem=Null +power_model=Null +randomization=false + +[system.ruby.clk_domain] +type=SrcClockDomain +clock=1 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.ruby.dir_cntrl0] +type=Directory_Controller +children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir requestToDir responseFromDir responseFromMemory +buffer_size=0 +clk_domain=system.ruby.clk_domain +cluster_id=0 +default_p_state=UNDEFINED +directory=system.ruby.dir_cntrl0.directory +directory_latency=12 +dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir +dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir +eventq_index=0 +forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir +number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +recycle_latency=10 +requestToDir=system.ruby.dir_cntrl0.requestToDir +responseFromDir=system.ruby.dir_cntrl0.responseFromDir +responseFromMemory=system.ruby.dir_cntrl0.responseFromMemory +ruby_system=system.ruby +system=system +to_memory_controller_latency=1 +transitions_per_cycle=4 +version=0 +memory=system.mem_ctrls.port + +[system.ruby.dir_cntrl0.directory] +type=RubyDirectoryMemory +eventq_index=0 +numa_high_bit=5 +size=268435456 +version=0 + +[system.ruby.dir_cntrl0.dmaRequestToDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[3] + +[system.ruby.dir_cntrl0.dmaResponseFromDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[3] + +[system.ruby.dir_cntrl0.forwardFromDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[4] + +[system.ruby.dir_cntrl0.requestToDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[2] + +[system.ruby.dir_cntrl0.responseFromDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[2] + +[system.ruby.dir_cntrl0.responseFromMemory] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false + +[system.ruby.l1_cntrl0] +type=L1Cache_Controller +children=cacheMemory forwardToCache mandatoryQueue requestFromCache responseFromCache responseToCache sequencer +buffer_size=0 +cacheMemory=system.ruby.l1_cntrl0.cacheMemory +cache_response_latency=12 +clk_domain=system.cpu.clk_domain +cluster_id=0 +default_p_state=UNDEFINED +eventq_index=0 +forwardToCache=system.ruby.l1_cntrl0.forwardToCache +issue_latency=2 +mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue +number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +recycle_latency=10 +requestFromCache=system.ruby.l1_cntrl0.requestFromCache +responseFromCache=system.ruby.l1_cntrl0.responseFromCache +responseToCache=system.ruby.l1_cntrl0.responseToCache +ruby_system=system.ruby +send_evictions=false +sequencer=system.ruby.l1_cntrl0.sequencer +system=system +transitions_per_cycle=4 +version=0 + +[system.ruby.l1_cntrl0.cacheMemory] +type=RubyCache +children=replacement_policy +assoc=2 +block_size=0 +dataAccessLatency=1 +dataArrayBanks=1 +eventq_index=0 +is_icache=false +replacement_policy=system.ruby.l1_cntrl0.cacheMemory.replacement_policy +resourceStalls=false +ruby_system=system.ruby +size=256 +start_index_bit=6 +tagAccessLatency=1 +tagArrayBanks=1 + +[system.ruby.l1_cntrl0.cacheMemory.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=2 +block_size=64 +eventq_index=0 +size=256 + +[system.ruby.l1_cntrl0.forwardToCache] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[0] + +[system.ruby.l1_cntrl0.mandatoryQueue] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false + +[system.ruby.l1_cntrl0.requestFromCache] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[0] + +[system.ruby.l1_cntrl0.responseFromCache] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[1] + +[system.ruby.l1_cntrl0.responseToCache] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[1] + +[system.ruby.l1_cntrl0.sequencer] +type=RubySequencer +clk_domain=system.cpu.clk_domain +coreid=99 +dcache=system.ruby.l1_cntrl0.cacheMemory +dcache_hit_latency=1 +deadlock_threshold=500000 +default_p_state=UNDEFINED +eventq_index=0 +garnet_standalone=false +icache=system.ruby.l1_cntrl0.cacheMemory +icache_hit_latency=1 +is_cpu_sequencer=true +max_outstanding_requests=16 +no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_ruby_tester=false +version=0 +slave=system.cpu.icache_port system.cpu.dcache_port + +[system.ruby.memctrl_clk_domain] +type=DerivedClockDomain +clk_divider=3 +clk_domain=system.ruby.clk_domain +eventq_index=0 + +[system.ruby.network] +type=SimpleNetwork +children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_links0 int_links1 int_links2 int_links3 routers0 routers1 routers2 +adaptive_routing=false +buffer_size=0 +clk_domain=system.ruby.clk_domain +control_msg_size=8 +default_p_state=UNDEFINED +endpoint_bandwidth=1000 +eventq_index=0 +ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 +int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 +int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 +netifs= +number_of_virtual_networks=5 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 +ruby_system=system.ruby +topology=Crossbar +master=system.ruby.l1_cntrl0.forwardToCache.slave system.ruby.l1_cntrl0.responseToCache.slave system.ruby.dir_cntrl0.requestToDir.slave system.ruby.dir_cntrl0.dmaRequestToDir.slave +slave=system.ruby.l1_cntrl0.requestFromCache.master system.ruby.l1_cntrl0.responseFromCache.master system.ruby.dir_cntrl0.responseFromDir.master system.ruby.dir_cntrl0.dmaResponseFromDir.master system.ruby.dir_cntrl0.forwardFromDir.master + +[system.ruby.network.ext_links0] +type=SimpleExtLink +bandwidth_factor=16 +eventq_index=0 +ext_node=system.ruby.l1_cntrl0 +int_node=system.ruby.network.routers0 +latency=1 +link_id=0 +weight=1 + +[system.ruby.network.ext_links1] +type=SimpleExtLink +bandwidth_factor=16 +eventq_index=0 +ext_node=system.ruby.dir_cntrl0 +int_node=system.ruby.network.routers1 +latency=1 +link_id=1 +weight=1 + +[system.ruby.network.int_link_buffers00] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers01] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers02] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + 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+dst_node=system.ruby.network.routers2 +eventq_index=0 +latency=1 +link_id=2 +src_node=system.ruby.network.routers0 +src_outport= +weight=1 + +[system.ruby.network.int_links1] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers2 +eventq_index=0 +latency=1 +link_id=3 +src_node=system.ruby.network.routers1 +src_outport= +weight=1 + +[system.ruby.network.int_links2] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers0 +eventq_index=0 +latency=1 +link_id=4 +src_node=system.ruby.network.routers2 +src_outport= +weight=1 + +[system.ruby.network.int_links3] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers1 +eventq_index=0 +latency=1 +link_id=5 +src_node=system.ruby.network.routers2 +src_outport= +weight=1 + +[system.ruby.network.routers0] +type=Switch +children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 +clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 system.ruby.network.routers0.port_buffers12 system.ruby.network.routers0.port_buffers13 system.ruby.network.routers0.port_buffers14 +power_model=Null +router_id=0 +virt_nets=5 + +[system.ruby.network.routers0.port_buffers00] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers01] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers02] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers03] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers04] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers05] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers06] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers07] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers08] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers09] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers10] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers11] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers12] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers13] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers14] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1] +type=Switch +children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 +clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 system.ruby.network.routers1.port_buffers12 system.ruby.network.routers1.port_buffers13 system.ruby.network.routers1.port_buffers14 +power_model=Null +router_id=1 +virt_nets=5 + +[system.ruby.network.routers1.port_buffers00] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers01] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers02] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers03] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers04] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers05] 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+type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/config.json --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/config.json Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,1734 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1, + "memories": [ + "system.mem_ctrls" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": 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"system.ruby.network.slave[3]", + "role": "MASTER" + }, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.dmaResponseFromDir", + "type": "MessageBuffer" + }, + "name": "dir_cntrl0", + "p_state_clk_gate_bins": 20, + "directory": { + "name": "directory", + "version": 0, + "eventq_index": 0, + "cxx_class": "DirectoryMemory", + "path": "system.ruby.dir_cntrl0.directory", + "type": "RubyDirectoryMemory", + "numa_high_bit": 5, + "size": 268435456 + }, + "path": "system.ruby.dir_cntrl0" + } + }, + "work_end_ckpt_count": 0, + "mem_mode": "timing", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": { + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.itb", + "type": "RiscvTLB", + "size": 64 + }, + "system": "system", + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "TimingSimpleCPU", + "max_loads_all_threads": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "function_trace_start": 0, + "cpu_id": 0, + "checker": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "do_quiesce": true, + "type": "TimingSimpleCPU", + "profile": 0, + "icache_port": { + "peer": "system.ruby.l1_cntrl0.sequencer.slave[0]", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "p_state_clk_gate_min": 1, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "dcache_port": { + "peer": "system.ruby.l1_cntrl0.sequencer.slave[1]", + "role": "MASTER" + }, + "socket_id": 0, + "power_model": null, + "max_insts_all_threads": 0, + "path": "system.cpu", + "max_loads_any_thread": 0, + "switched_out": false, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64i/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "progress_interval": 0, + "branchPred": null, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + }, + "multi_thread": false, + "mem_ctrls": [ + { + "static_frontend_latency": 10, + "tRFC": 260, + "activation_limit": 4, + "in_addr_map": true, + "IDD3N2": "0.0", + "tWTR": 8, + "IDD52": "0.0", + "clk_domain": "system.clk_domain", + "channels": 1, + "write_buffer_size": 64, + "device_bus_width": 8, + "VDD": "1.5", + "write_high_thresh_perc": 85, + "cxx_class": "DRAMCtrl", + "bank_groups_per_rank": 0, + "IDD2N2": "0.0", + "port": { + "peer": "system.ruby.dir_cntrl0.memory", + "role": "SLAVE" + }, + "tCCD_L": 0, + "IDD2N": "0.032", + "p_state_clk_gate_min": 1, + "null": false, + "IDD2P1": "0.032", + "eventq_index": 0, + "tRRD": 6, + "tRTW": 3, + "IDD4R": "0.157", + "burst_length": 8, + "tRTP": 8, + "IDD4W": "0.125", + "tWR": 15, + "banks_per_rank": 8, + "devices_per_rank": 8, + "IDD2P02": "0.0", + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "IDD6": "0.02", + "IDD5": "0.235", + "tRCD": 14, + "type": "DRAMCtrl", + "IDD3P02": "0.0", + "tRRD_L": 0, + "IDD0": "0.055", + "IDD62": "0.0", + "min_writes_per_switch": 16, + "mem_sched_policy": "frfcfs", + "IDD02": "0.0", + "IDD2P0": "0.0", + "ranks_per_channel": 2, + "page_policy": "open_adaptive", + "IDD4W2": "0.0", + "tCS": 3, + "power_model": null, + "tCL": 14, + "read_buffer_size": 32, + "conf_table_reported": true, + "tCK": 1, + "tRAS": 35, + "tRP": 14, + "tBURST": 5, + "path": "system.mem_ctrls", + "tXP": 6, + "tXS": 270, + "addr_mapping": "RoRaBaCoCh", + "IDD3P0": "0.0", + "IDD3P1": "0.038", + "IDD3N": "0.038", + "name": "mem_ctrls", + "tXSDLL": 0, + "device_size": 536870912, + "kvm_map": true, + "dll": true, + "tXAW": 30, + "write_low_thresh_perc": 50, + "range": "0:268435455:5:19:0:0", + "VDD2": "0.0", + "IDD2P12": "0.0", + "p_state_clk_gate_bins": 20, + "tXPDLL": 0, + "IDD4R2": "0.0", + "device_rowbuffer_size": 1024, + "static_backend_latency": 10, + "max_accesses_per_row": 16, + "IDD3P12": "0.0", + "tREFI": 7800 + } + ], + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/simerr --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/simerr Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,11 @@ +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick +warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/simout --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/simout Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,171 @@ +Redirecting stdout to build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64i/simple-timing-ruby/simout +Redirecting stderr to build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64i/simple-timing-ruby/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 2 2016 20:34:02 +gem5 started Nov 3 2016 18:35:29 +gem5 executing on ubuntu1604, pid 21242 +command line: /home/ar4jc/gem5/build/RISCV/gem5.debug -d build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64i/simple-timing-ruby -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64i/simple-timing-ruby + +Global frequency set at 1000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +lui: PASS +lui, negative: PASS +auipc: 0x157CC +auipc: PASS +jal: PASS +jalr: PASS +beq, equal: PASS +beq, not equal: PASS +bne, equal: PASS +bne, not equal: PASS +blt, less: PASS +blt, equal: PASS +blt, greater: PASS +bge, less: PASS +bge, equal: PASS +bge, greater: PASS +bltu, greater: PASS +bltu, equal: PASS +bltu, less: PASS +bgeu, greater: PASS +bgeu, equal: PASS +bgeu, less: PASS +lb, positive: PASS +lb, negative: PASS +lh, positive: PASS +lh, negative: PASS +lw, positive: PASS +lw, negative: PASS +lbu: PASS +lhu: PASS +sb: PASS +sh: PASS +sw: PASS +addi: PASS +addi, overflow: PASS +slti, true: PASS +slti, false: PASS +sltiu, false: PASS +sltiu, true: PASS +xori (1): PASS +xori (0): PASS +ori (1): PASS +ori (A): PASS +andi (0): PASS +andi (1): PASS +slli, general: PASS +slli, erase: PASS +srli, general: PASS +srli, erase: PASS +srli, negative: PASS +srai, general: PASS +srai, erase: PASS +srai, negative: PASS +add: PASS +add, overflow: PASS +sub: PASS +sub, "overflow": PASS +sll, general: PASS +sll, erase: PASS +slt, true: PASS +slt, false: PASS +sltu, false: PASS +sltu, true: PASS +xor (1): PASS +xor (0): PASS +srl, general: PASS +srl, erase: PASS +srl, negative: PASS +sra, general: PASS +sra, erase: PASS +sra, negative: PASS +or (1): PASS +or (A): PASS +and (0): PASS +and (-1): PASS +Bytes written: 15 +open, write: PASS +access F_OK: PASS +access R_OK: PASS +access W_OK: PASS +access X_OK: PASS +stat: + st_dev = 1696642673 + st_ino = 676985 + st_mode = 33188 + st_nlink = 1 + st_uid = 503 + st_gid = 503 + st_rdev = 0 + st_size = 15 + st_blksize = 8192 + st_blocks = 8 +fstat: + st_dev = 1696642673 + st_ino = 676985 + st_mode = 33188 + st_nlink = 1 + st_uid = 503 + st_gid = 503 + st_rdev = 0 + st_size = 15 + st_blksize = 8192 + st_blocks = 8 +open, stat: PASS +Bytes read: 15 +String read: this is a test +open, read, unlink: PASS +times: + tms_utime = 0 + tms_stime = 0 + tms_cutime = 0 + tms_cstime = 0 +times: PASS +timeval: + tv_sec = 1000000000 + tv_usec = 3890 +gettimeofday: PASS +Cycles: 3991956 +rdcycle: PASS +Time: 1478198164 +rdtime: PASS +Instructions Retired: 213566 +rdinstret: PASS +lwu: PASS +ld: PASS +sd: PASS +addiw: PASS +addiw, overflow: PASS +addiw, truncate: PASS +slliw, general: PASS +slliw, erase: PASS +slliw, truncate: PASS +srliw, general: PASS +srliw, erase: PASS +srliw, negative: PASS +srliw, truncate: PASS +sraiw, general: PASS +sraiw, erase: PASS +sraiw, negative: PASS +sraiw, truncate: PASS +addw: PASS +addw, overflow: PASS +addw, truncate: PASS +subw: PASS +subw, "overflow": PASS +subw, truncate: PASS +sllw, general: PASS +sllw, erase: PASS +sllw, truncate: PASS +srlw, general: PASS +srlw, erase: PASS +srlw, negative: PASS +srlw, truncate: PASS +sraw, general: PASS +sraw, erase: PASS +sraw, negative: PASS +sraw, truncate: PASS +Exiting @ tick 5211903 because target called exit() diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/stats.txt --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/stats.txt Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,644 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.005212 # Number of seconds simulated +sim_ticks 5211903 # Number of ticks simulated +final_tick 5211903 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000 # Frequency of simulated ticks +host_inst_rate 5958 # Simulator instruction rate (inst/s) +host_op_rate 5958 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 117399 # Simulator tick rate (ticks/s) +host_mem_usage 442724 # Number of bytes of host memory used +host_seconds 44.39 # Real time elapsed on the host +sim_insts 264519 # Number of instructions simulated +sim_ops 264519 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1 # Clock period in ticks +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 5211903 # Cumulative time (in ticks) in various power states +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 5112640 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 5112640 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 5112384 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 5112384 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 79885 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 79885 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 79881 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 79881 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 980954557 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 980954557 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 980905439 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 980905439 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 1961859996 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1961859996 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 79885 # Number of read requests accepted +system.mem_ctrls.writeReqs 79881 # Number of write requests accepted +system.mem_ctrls.readBursts 79885 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 79881 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 2689408 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 2423232 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 2790272 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 5112640 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 5112384 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 37863 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 36256 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 3725 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 2522 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 5759 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 887 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 149 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 10 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 560 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 1914 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 2371 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 8238 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 4520 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 1562 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 5265 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 1218 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 412 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 2910 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 3798 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 2712 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 6371 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 907 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 150 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 10 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 590 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 1972 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 2436 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 8421 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 4570 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 1586 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 5319 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 1227 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 413 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 3116 # Per bank write bursts +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.totGap 5211831 # Total gap between requests +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 79885 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 79881 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 42022 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 293 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 352 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 2313 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 2724 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 2737 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 2766 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 2873 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 2821 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 2678 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 2674 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 2674 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 2673 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 2672 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 2672 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 2672 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 2672 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 2672 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 2672 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see 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an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 13246 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 413.487543 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 284.570842 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 329.688453 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 1985 14.99% 14.99% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 3313 25.01% 40.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 1980 14.95% 54.94% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 1515 11.44% 66.38% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 999 7.54% 73.92% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 671 5.07% 78.99% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 526 3.97% 82.96% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 439 3.31% 86.28% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 1818 13.72% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 13246 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 2672 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 15.723428 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 15.667792 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 1.363070 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::12-13 55 2.06% 2.06% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::14-15 1226 45.88% 47.94% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-17 1131 42.33% 90.27% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::18-19 245 9.17% 99.44% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::20-21 14 0.52% 99.96% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::36-37 1 0.04% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 2672 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 2672 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.316617 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.296411 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 0.845660 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 2314 86.60% 86.60% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 45 1.68% 88.29% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 141 5.28% 93.56% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 169 6.32% 99.89% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::20 3 0.11% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 2672 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 774964 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 1573382 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 210110 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 18.44 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 37.44 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 516.01 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 535.37 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 980.95 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 980.91 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 8.21 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 4.03 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 4.18 # Data bus utilization in percentage for writes +system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 25.81 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 32164 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 40201 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 76.54 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 92.15 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 32.62 # Average gap between requests +system.mem_ctrls.pageHitRate 84.49 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 51750720 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 27990816 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 177369024 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 137891520 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 410579520.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 515471520 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 10101888 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.actPowerDownEnergy 1694946528 # Energy for active power-down per rank (pJ) +system.mem_ctrls_0.prePowerDownEnergy 100601088 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_0.selfRefreshEnergy 23811840 # Energy for self refresh per rank (pJ) +system.mem_ctrls_0.totalEnergy 3150514464 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 604.484478 # Core power per rank (mW) +system.mem_ctrls_0.totalIdleTime 4055139 # Total Idle time Per DRAM Rank +system.mem_ctrls_0.memoryStateTime::IDLE 7055 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 173740 # Time in different power states +system.mem_ctrls_0.memoryStateTime::SREF 76206 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 261982 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 975932 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 3716988 # Time in different power states +system.mem_ctrls_1.actEnergy 42889980 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 23191728 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 302690304 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 226238976 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 391525680.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 619112112 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 11379456 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.actPowerDownEnergy 1577991192 # Energy for active power-down per rank (pJ) +system.mem_ctrls_1.prePowerDownEnergy 34210176 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_1.selfRefreshEnergy 68202000 # Energy for self refresh per rank (pJ) +system.mem_ctrls_1.totalEnergy 3297431604 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 632.673249 # Core power per rank (mW) +system.mem_ctrls_1.totalIdleTime 3824382 # Total Idle time Per DRAM Rank +system.mem_ctrls_1.memoryStateTime::IDLE 11814 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 165644 # Time in different power states +system.mem_ctrls_1.memoryStateTime::SREF 274971 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 89089 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 1209878 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 3460507 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 5211903 # Cumulative time (in ticks) in various power states +system.cpu.clk_domain.clock 1 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 184 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 5211903 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 5211903 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 264519 # Number of instructions committed +system.cpu.committedOps 264519 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 264518 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 18966 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 39598 # number of instructions that are conditional controls +system.cpu.num_int_insts 264518 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 350141 # number of times the integer registers were read +system.cpu.num_int_register_writes 180214 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 106238 # number of memory refs +system.cpu.num_load_insts 61532 # Number of load instructions +system.cpu.num_store_insts 44706 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 5211903 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 58564 # Number of branches fetched +system.cpu.op_class::No_OpClass 189 0.07% 0.07% # Class of executed instruction +system.cpu.op_class::IntAlu 157612 59.54% 59.61% # Class of executed instruction +system.cpu.op_class::IntMult 431 0.16% 59.78% # Class of executed instruction +system.cpu.op_class::IntDiv 234 0.09% 59.87% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 59.87% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 59.87% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 59.87% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 59.87% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 59.87% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 59.87% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 59.87% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 59.87% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 59.87% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 59.87% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 59.87% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 59.87% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 59.87% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 59.87% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 59.87% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 59.87% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 59.87% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 59.87% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 59.87% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 59.87% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 59.87% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 59.87% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 59.87% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 59.87% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 59.87% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 59.87% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 59.87% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 59.87% # Class of executed instruction +system.cpu.op_class::MemRead 61532 23.25% 83.11% # Class of executed instruction +system.cpu.op_class::MemWrite 44706 16.89% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 264704 # Class of executed instruction +system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.pwrStateResidencyTicks::UNDEFINED 5211903 # Cumulative time (in ticks) in various power states +system.ruby.delayHist::bucket_size 1 # delay histogram for all message +system.ruby.delayHist::max_bucket 9 # delay histogram for all message +system.ruby.delayHist::samples 159766 # delay histogram for all message +system.ruby.delayHist | 159766 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 159766 # delay histogram for all message +system.ruby.outstanding_req_hist_seqr::bucket_size 1 +system.ruby.outstanding_req_hist_seqr::max_bucket 9 +system.ruby.outstanding_req_hist_seqr::samples 370942 +system.ruby.outstanding_req_hist_seqr::mean 1 +system.ruby.outstanding_req_hist_seqr::gmean 1 +system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 370942 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 370942 +system.ruby.latency_hist_seqr::bucket_size 64 +system.ruby.latency_hist_seqr::max_bucket 639 +system.ruby.latency_hist_seqr::samples 370941 +system.ruby.latency_hist_seqr::mean 13.050491 +system.ruby.latency_hist_seqr::gmean 2.323715 +system.ruby.latency_hist_seqr::stdev 28.517895 +system.ruby.latency_hist_seqr | 330243 89.03% 89.03% | 37851 10.20% 99.23% | 1989 0.54% 99.77% | 255 0.07% 99.84% | 329 0.09% 99.93% | 245 0.07% 99.99% | 16 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 13 0.00% 100.00% +system.ruby.latency_hist_seqr::total 370941 +system.ruby.hit_latency_hist_seqr::bucket_size 1 +system.ruby.hit_latency_hist_seqr::max_bucket 9 +system.ruby.hit_latency_hist_seqr::samples 291056 +system.ruby.hit_latency_hist_seqr::mean 1 +system.ruby.hit_latency_hist_seqr::gmean 1 +system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 291056 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 291056 +system.ruby.miss_latency_hist_seqr::bucket_size 64 +system.ruby.miss_latency_hist_seqr::max_bucket 639 +system.ruby.miss_latency_hist_seqr::samples 79885 +system.ruby.miss_latency_hist_seqr::mean 56.955699 +system.ruby.miss_latency_hist_seqr::gmean 50.158814 +system.ruby.miss_latency_hist_seqr::stdev 36.326709 +system.ruby.miss_latency_hist_seqr | 39187 49.05% 49.05% | 37851 47.38% 96.44% | 1989 2.49% 98.93% | 255 0.32% 99.25% | 329 0.41% 99.66% | 245 0.31% 99.96% | 16 0.02% 99.98% | 0 0.00% 99.98% | 0 0.00% 99.98% | 13 0.02% 100.00% +system.ruby.miss_latency_hist_seqr::total 79885 +system.ruby.Directory.incomplete_times_seqr 79884 +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 5211903 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.cacheMemory.demand_hits 291056 # Number of cache demand hits +system.ruby.l1_cntrl0.cacheMemory.demand_misses 79885 # Number of cache demand misses +system.ruby.l1_cntrl0.cacheMemory.demand_accesses 370941 # Number of cache demand accesses +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 5211903 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 5211903 # Cumulative time (in ticks) in various power states +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 5211903 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.percent_links_utilized 7.663516 +system.ruby.network.routers0.msg_count.Control::2 79885 +system.ruby.network.routers0.msg_count.Data::2 79881 +system.ruby.network.routers0.msg_count.Response_Data::4 79885 +system.ruby.network.routers0.msg_count.Writeback_Control::3 79881 +system.ruby.network.routers0.msg_bytes.Control::2 639080 +system.ruby.network.routers0.msg_bytes.Data::2 5751432 +system.ruby.network.routers0.msg_bytes.Response_Data::4 5751720 +system.ruby.network.routers0.msg_bytes.Writeback_Control::3 639048 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 5211903 # Cumulative time (in ticks) in various power states +system.ruby.network.routers1.percent_links_utilized 7.663516 +system.ruby.network.routers1.msg_count.Control::2 79885 +system.ruby.network.routers1.msg_count.Data::2 79881 +system.ruby.network.routers1.msg_count.Response_Data::4 79885 +system.ruby.network.routers1.msg_count.Writeback_Control::3 79881 +system.ruby.network.routers1.msg_bytes.Control::2 639080 +system.ruby.network.routers1.msg_bytes.Data::2 5751432 +system.ruby.network.routers1.msg_bytes.Response_Data::4 5751720 +system.ruby.network.routers1.msg_bytes.Writeback_Control::3 639048 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 5211903 # Cumulative time (in ticks) in various power states +system.ruby.network.routers2.percent_links_utilized 7.663516 +system.ruby.network.routers2.msg_count.Control::2 79885 +system.ruby.network.routers2.msg_count.Data::2 79881 +system.ruby.network.routers2.msg_count.Response_Data::4 79885 +system.ruby.network.routers2.msg_count.Writeback_Control::3 79881 +system.ruby.network.routers2.msg_bytes.Control::2 639080 +system.ruby.network.routers2.msg_bytes.Data::2 5751432 +system.ruby.network.routers2.msg_bytes.Response_Data::4 5751720 +system.ruby.network.routers2.msg_bytes.Writeback_Control::3 639048 +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 5211903 # Cumulative time (in ticks) in various power states +system.ruby.network.msg_count.Control 239655 +system.ruby.network.msg_count.Data 239643 +system.ruby.network.msg_count.Response_Data 239655 +system.ruby.network.msg_count.Writeback_Control 239643 +system.ruby.network.msg_byte.Control 1917240 +system.ruby.network.msg_byte.Data 17254296 +system.ruby.network.msg_byte.Response_Data 17255160 +system.ruby.network.msg_byte.Writeback_Control 1917144 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 5211903 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.throttle0.link_utilization 7.663669 +system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 79885 +system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 79881 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 5751720 +system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 639048 +system.ruby.network.routers0.throttle1.link_utilization 7.663362 +system.ruby.network.routers0.throttle1.msg_count.Control::2 79885 +system.ruby.network.routers0.throttle1.msg_count.Data::2 79881 +system.ruby.network.routers0.throttle1.msg_bytes.Control::2 639080 +system.ruby.network.routers0.throttle1.msg_bytes.Data::2 5751432 +system.ruby.network.routers1.throttle0.link_utilization 7.663362 +system.ruby.network.routers1.throttle0.msg_count.Control::2 79885 +system.ruby.network.routers1.throttle0.msg_count.Data::2 79881 +system.ruby.network.routers1.throttle0.msg_bytes.Control::2 639080 +system.ruby.network.routers1.throttle0.msg_bytes.Data::2 5751432 +system.ruby.network.routers1.throttle1.link_utilization 7.663669 +system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 79885 +system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 79881 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 5751720 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 639048 +system.ruby.network.routers2.throttle0.link_utilization 7.663669 +system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 79885 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 79881 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 5751720 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 639048 +system.ruby.network.routers2.throttle1.link_utilization 7.663362 +system.ruby.network.routers2.throttle1.msg_count.Control::2 79885 +system.ruby.network.routers2.throttle1.msg_count.Data::2 79881 +system.ruby.network.routers2.throttle1.msg_bytes.Control::2 639080 +system.ruby.network.routers2.throttle1.msg_bytes.Data::2 5751432 +system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::samples 79885 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1 | 79885 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::total 79885 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::samples 79881 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2 | 79881 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::total 79881 # delay histogram for vnet_2 +system.ruby.LD.latency_hist_seqr::bucket_size 64 +system.ruby.LD.latency_hist_seqr::max_bucket 639 +system.ruby.LD.latency_hist_seqr::samples 61532 +system.ruby.LD.latency_hist_seqr::mean 25.694858 +system.ruby.LD.latency_hist_seqr::gmean 6.461824 +system.ruby.LD.latency_hist_seqr::stdev 34.184013 +system.ruby.LD.latency_hist_seqr | 49473 80.40% 80.40% | 11283 18.34% 98.74% | 534 0.87% 99.61% | 67 0.11% 99.72% | 94 0.15% 99.87% | 75 0.12% 99.99% | 6 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist_seqr::total 61532 +system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 +system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 +system.ruby.LD.hit_latency_hist_seqr::samples 31477 +system.ruby.LD.hit_latency_hist_seqr::mean 1 +system.ruby.LD.hit_latency_hist_seqr::gmean 1 +system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 31477 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::total 31477 +system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 +system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 +system.ruby.LD.miss_latency_hist_seqr::samples 30055 +system.ruby.LD.miss_latency_hist_seqr::mean 51.558110 +system.ruby.LD.miss_latency_hist_seqr::gmean 45.609027 +system.ruby.LD.miss_latency_hist_seqr::stdev 32.936019 +system.ruby.LD.miss_latency_hist_seqr | 17996 59.88% 59.88% | 11283 37.54% 97.42% | 534 1.78% 99.19% | 67 0.22% 99.42% | 94 0.31% 99.73% | 75 0.25% 99.98% | 6 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist_seqr::total 30055 +system.ruby.ST.latency_hist_seqr::bucket_size 64 +system.ruby.ST.latency_hist_seqr::max_bucket 639 +system.ruby.ST.latency_hist_seqr::samples 44705 +system.ruby.ST.latency_hist_seqr::mean 13.376781 +system.ruby.ST.latency_hist_seqr::gmean 2.781791 +system.ruby.ST.latency_hist_seqr::stdev 26.511206 +system.ruby.ST.latency_hist_seqr | 41546 92.93% 92.93% | 2860 6.40% 99.33% | 216 0.48% 99.81% | 38 0.09% 99.90% | 23 0.05% 99.95% | 12 0.03% 99.98% | 0 0.00% 99.98% | 0 0.00% 99.98% | 0 0.00% 99.98% | 10 0.02% 100.00% +system.ruby.ST.latency_hist_seqr::total 44705 +system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 +system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 +system.ruby.ST.hit_latency_hist_seqr::samples 32360 +system.ruby.ST.hit_latency_hist_seqr::mean 1 +system.ruby.ST.hit_latency_hist_seqr::gmean 1 +system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 32360 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist_seqr::total 32360 +system.ruby.ST.miss_latency_hist_seqr::bucket_size 64 +system.ruby.ST.miss_latency_hist_seqr::max_bucket 639 +system.ruby.ST.miss_latency_hist_seqr::samples 12345 +system.ruby.ST.miss_latency_hist_seqr::mean 45.820089 +system.ruby.ST.miss_latency_hist_seqr::gmean 40.647542 +system.ruby.ST.miss_latency_hist_seqr::stdev 33.032280 +system.ruby.ST.miss_latency_hist_seqr | 9186 74.41% 74.41% | 2860 23.17% 97.58% | 216 1.75% 99.33% | 38 0.31% 99.64% | 23 0.19% 99.82% | 12 0.10% 99.92% | 0 0.00% 99.92% | 0 0.00% 99.92% | 0 0.00% 99.92% | 10 0.08% 100.00% +system.ruby.ST.miss_latency_hist_seqr::total 12345 +system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.latency_hist_seqr::samples 264704 +system.ruby.IFETCH.latency_hist_seqr::mean 10.056127 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.777196 +system.ruby.IFETCH.latency_hist_seqr::stdev 26.517753 +system.ruby.IFETCH.latency_hist_seqr | 239224 90.37% 90.37% | 23708 8.96% 99.33% | 1239 0.47% 99.80% | 150 0.06% 99.86% | 212 0.08% 99.94% | 158 0.06% 100.00% | 10 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 3 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::total 264704 +system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 +system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 +system.ruby.IFETCH.hit_latency_hist_seqr::samples 227219 +system.ruby.IFETCH.hit_latency_hist_seqr::mean 1 +system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 +system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 227219 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist_seqr::total 227219 +system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.miss_latency_hist_seqr::samples 37485 +system.ruby.IFETCH.miss_latency_hist_seqr::mean 64.950727 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 58.013690 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 38.146090 +system.ruby.IFETCH.miss_latency_hist_seqr | 12005 32.03% 32.03% | 23708 63.25% 95.27% | 1239 3.31% 98.58% | 150 0.40% 98.98% | 212 0.57% 99.54% | 158 0.42% 99.97% | 10 0.03% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 3 0.01% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::total 37485 +system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 +system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 +system.ruby.Directory.miss_mach_latency_hist_seqr::samples 79885 +system.ruby.Directory.miss_mach_latency_hist_seqr::mean 56.955699 +system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 50.158814 +system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 36.326709 +system.ruby.Directory.miss_mach_latency_hist_seqr | 39187 49.05% 49.05% | 37851 47.38% 96.44% | 1989 2.49% 98.93% | 255 0.32% 99.25% | 329 0.41% 99.66% | 245 0.31% 99.96% | 16 0.02% 99.98% | 0 0.00% 99.98% | 0 0.00% 99.98% | 13 0.02% 100.00% +system.ruby.Directory.miss_mach_latency_hist_seqr::total 79885 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::total 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total 1 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size 8 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 79 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean 75 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 75.000000 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 30055 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 51.558110 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 45.609027 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 32.936019 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 17996 59.88% 59.88% | 11283 37.54% 97.42% | 534 1.78% 99.19% | 67 0.22% 99.42% | 94 0.31% 99.73% | 75 0.25% 99.98% | 6 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 30055 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 12345 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 45.820089 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 40.647542 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 33.032280 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 9186 74.41% 74.41% | 2860 23.17% 97.58% | 216 1.75% 99.33% | 38 0.31% 99.64% | 23 0.19% 99.82% | 12 0.10% 99.92% | 0 0.00% 99.92% | 0 0.00% 99.92% | 0 0.00% 99.92% | 10 0.08% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 12345 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 37485 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 64.950727 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 58.013690 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 38.146090 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 12005 32.03% 32.03% | 23708 63.25% 95.27% | 1239 3.31% 98.58% | 150 0.40% 98.98% | 212 0.57% 99.54% | 158 0.42% 99.97% | 10 0.03% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 3 0.01% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 37485 +system.ruby.Directory_Controller.GETX 79885 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 79881 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 79885 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 79881 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 79885 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 79881 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 79885 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 79881 0.00% 0.00% +system.ruby.L1Cache_Controller.Load 61532 0.00% 0.00% +system.ruby.L1Cache_Controller.Ifetch 264704 0.00% 0.00% +system.ruby.L1Cache_Controller.Store 44705 0.00% 0.00% +system.ruby.L1Cache_Controller.Data 79885 0.00% 0.00% +system.ruby.L1Cache_Controller.Replacement 79881 0.00% 0.00% +system.ruby.L1Cache_Controller.Writeback_Ack 79881 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Load 30055 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Ifetch 37485 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Store 12345 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Load 31477 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Ifetch 227219 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Store 32360 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Replacement 79881 0.00% 0.00% +system.ruby.L1Cache_Controller.MI.Writeback_Ack 79881 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Data 67540 0.00% 0.00% +system.ruby.L1Cache_Controller.IM.Data 12345 0.00% 0.00% + +---------- End Simulation Statistics ---------- diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/config.ini --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/config.ini Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,374 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=TimingSimpleCPU +children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +hit_latency=2 +is_read_only=false +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=262144 + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.icache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +hit_latency=2 +is_read_only=true +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tags=system.cpu.icache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=131072 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.l2cache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +hit_latency=20 +is_read_only=false +max_miss_count=0 +mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +hit_latency=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=2097152 + +[system.cpu.toL2Bus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=0 +frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null +response_latency=1 +snoop_filter=system.cpu.toL2Bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64i/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +eventq_index=0 +in_addr_map=true +kvm_map=true +latency=30000 +latency_var=0 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +range=0:134217727:0:0:0:0 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/config.json --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/config.json Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,502 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.l2cache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "physmem": { + "range": "0:134217727:0:0:0:0", + "latency": 30000, + "name": "physmem", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "kvm_map": true, + "clk_domain": "system.clk_domain", + "power_model": null, + "latency_var": 0, + "bandwidth": "73.000000", + "conf_table_reported": true, + "cxx_class": "SimpleMemory", + "p_state_clk_gate_max": 1000000000000, + "path": "system.physmem", + "null": false, + "type": "SimpleMemory", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "in_addr_map": true + }, + "power_model": null, + "work_cpus_ckpt_count": 0, + "thermal_components": [], + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "work_end_ckpt_count": 0, + "mem_mode": "timing", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": [ + { + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.itb", + "type": "RiscvTLB", + "size": 64 + }, + "system": "system", + "icache": { + "cpu_side": { + "peer": "system.cpu.icache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 131072, + "tags": { + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.icache.tags", + "hit_latency": 2, + "block_size": 64, + "type": "LRU", + "size": 131072 + }, + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[0]", + "role": "MASTER" + }, + "type": "Cache", + "writeback_clean": true, + "p_state_clk_gate_min": 1000, + "hit_latency": 2, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": true, + "prefetch_on_access": false, + "path": "system.cpu.icache", + "mshrs": 4, + "name": "icache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "TimingSimpleCPU", + "max_loads_all_threads": 0, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "cpu_id": 0, + "checker": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "toL2Bus": { + "point_of_coherency": false, + "system": "system", + "response_latency": 1, + "cxx_class": "CoherentXBar", + "forward_latency": 0, + "clk_domain": "system.cpu_clk_domain", + "width": 32, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.cpu.l2cache.cpu_side" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 1, + "slave": { + "peer": [ + "system.cpu.icache.mem_side", + "system.cpu.dcache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.cpu.toL2Bus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 0 + }, + "power_model": null, + "path": "system.cpu.toL2Bus", + "snoop_response_latency": 1, + "name": "toL2Bus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "do_quiesce": true, + "type": "TimingSimpleCPU", + "profile": 0, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "p_state_clk_gate_min": 1000, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "role": "MASTER" + }, + "socket_id": 0, + "power_model": null, + "max_insts_all_threads": 0, + "l2cache": { + "cpu_side": { + "peer": "system.cpu.toL2Bus.master[0]", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 20, + "cxx_class": "Cache", + "size": 2097152, + "tags": { + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 8, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.l2cache.tags", + "hit_latency": 20, + "block_size": 64, + "type": "LRU", + "size": 2097152 + }, + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.membus.slave[1]", + "role": "MASTER" + }, + "type": "Cache", + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "hit_latency": 20, + "tgts_per_mshr": 12, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.l2cache", + "mshrs": 20, + "name": "l2cache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 8 + }, + "path": "system.cpu", + "max_loads_any_thread": 0, + "switched_out": false, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64i/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "progress_interval": 0, + "branchPred": null, + "dcache": { + "cpu_side": { + "peer": "system.cpu.dcache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 262144, + "tags": { + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.dcache.tags", + "hit_latency": 2, + "block_size": 64, + "type": "LRU", + "size": 262144 + }, + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[1]", + "role": "MASTER" + }, + "type": "Cache", + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "hit_latency": 2, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.dcache", + "mshrs": 4, + "name": "dcache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/simerr --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/simerr Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,3 @@ +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/simout --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/simout Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,171 @@ +Redirecting stdout to build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64i/simple-timing/simout +Redirecting stderr to build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64i/simple-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 2 2016 20:34:02 +gem5 started Nov 3 2016 18:35:22 +gem5 executing on ubuntu1604, pid 21241 +command line: /home/ar4jc/gem5/build/RISCV/gem5.debug -d build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64i/simple-timing -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64i/simple-timing + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +lui: PASS +lui, negative: PASS +auipc: 0x157CC +auipc: PASS +jal: PASS +jalr: PASS +beq, equal: PASS +beq, not equal: PASS +bne, equal: PASS +bne, not equal: PASS +blt, less: PASS +blt, equal: PASS +blt, greater: PASS +bge, less: PASS +bge, equal: PASS +bge, greater: PASS +bltu, greater: PASS +bltu, equal: PASS +bltu, less: PASS +bgeu, greater: PASS +bgeu, equal: PASS +bgeu, less: PASS +lb, positive: PASS +lb, negative: PASS +lh, positive: PASS +lh, negative: PASS +lw, positive: PASS +lw, negative: PASS +lbu: PASS +lhu: PASS +sb: PASS +sh: PASS +sw: PASS +addi: PASS +addi, overflow: PASS +slti, true: PASS +slti, false: PASS +sltiu, false: PASS +sltiu, true: PASS +xori (1): PASS +xori (0): PASS +ori (1): PASS +ori (A): PASS +andi (0): PASS +andi (1): PASS +slli, general: PASS +slli, erase: PASS +srli, general: PASS +srli, erase: PASS +srli, negative: PASS +srai, general: PASS +srai, erase: PASS +srai, negative: PASS +add: PASS +add, overflow: PASS +sub: PASS +sub, "overflow": PASS +sll, general: PASS +sll, erase: PASS +slt, true: PASS +slt, false: PASS +sltu, false: PASS +sltu, true: PASS +xor (1): PASS +xor (0): PASS +srl, general: PASS +srl, erase: PASS +srl, negative: PASS +sra, general: PASS +sra, erase: PASS +sra, negative: PASS +or (1): PASS +or (A): PASS +and (0): PASS +and (-1): PASS +Bytes written: 15 +open, write: PASS +access F_OK: PASS +access R_OK: PASS +access W_OK: PASS +access X_OK: PASS +stat: + st_dev = 1696642673 + st_ino = 676985 + st_mode = 33188 + st_nlink = 1 + st_uid = 503 + st_gid = 503 + st_rdev = 0 + st_size = 15 + st_blksize = 8192 + st_blocks = 8 +fstat: + st_dev = 1696642673 + st_ino = 676985 + st_mode = 33188 + st_nlink = 1 + st_uid = 503 + st_gid = 503 + st_rdev = 0 + st_size = 15 + st_blksize = 8192 + st_blocks = 8 +open, stat: PASS +Bytes read: 15 +String read: this is a test +open, read, unlink: PASS +times: + tms_utime = 0 + tms_stime = 0 + tms_cutime = 0 + tms_cstime = 0 +times: PASS +timeval: + tv_sec = 1000000000 + tv_usec = 354 +gettimeofday: PASS +Cycles: 723151 +rdcycle: PASS +Time: 1478198127 +rdtime: PASS +Instructions Retired: 213528 +rdinstret: PASS +lwu: PASS +ld: PASS +sd: PASS +addiw: PASS +addiw, overflow: PASS +addiw, truncate: PASS +slliw, general: PASS +slliw, erase: PASS +slliw, truncate: PASS +srliw, general: PASS +srliw, erase: PASS +srliw, negative: PASS +srliw, truncate: PASS +sraiw, general: PASS +sraiw, erase: PASS +sraiw, negative: PASS +sraiw, truncate: PASS +addw: PASS +addw, overflow: PASS +addw, truncate: PASS +subw: PASS +subw, "overflow": PASS +subw, truncate: PASS +sllw, general: PASS +sllw, erase: PASS +sllw, truncate: PASS +srlw, general: PASS +srlw, erase: PASS +srlw, negative: PASS +srlw, truncate: PASS +sraw, general: PASS +sraw, erase: PASS +sraw, negative: PASS +sraw, truncate: PASS +Exiting @ tick 449273500 because target called exit() diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/stats.txt --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/stats.txt Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,521 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000449 # Number of seconds simulated +sim_ticks 449273500 # Number of ticks simulated +final_tick 449273500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 39133 # Simulator instruction rate (inst/s) +host_op_rate 39133 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 66474312 # Simulator tick rate (ticks/s) +host_mem_usage 276324 # Number of bytes of host memory used +host_seconds 6.76 # Real time elapsed on the host +sim_insts 264481 # Number of instructions simulated +sim_ops 264481 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 449273500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 62080 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18816 # Number of bytes read from this memory +system.physmem.bytes_read::total 80896 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 62080 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 62080 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 970 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 294 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1264 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 138178637 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 41880948 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 180059585 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 138178637 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 138178637 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 138178637 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 41880948 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 180059585 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 449273500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 184 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 449273500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 898547 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 264481 # Number of instructions committed +system.cpu.committedOps 264481 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 264480 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 18966 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 39588 # number of instructions that are conditional controls +system.cpu.num_int_insts 264480 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 350083 # number of times the integer registers were read +system.cpu.num_int_register_writes 180190 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 106228 # number of memory refs +system.cpu.num_load_insts 61526 # Number of load instructions +system.cpu.num_store_insts 44702 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 898547 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 58554 # Number of branches fetched +system.cpu.op_class::No_OpClass 189 0.07% 0.07% # Class of executed instruction +system.cpu.op_class::IntAlu 157588 59.54% 59.61% # Class of executed instruction +system.cpu.op_class::IntMult 431 0.16% 59.78% # Class of executed instruction +system.cpu.op_class::IntDiv 230 0.09% 59.86% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 59.86% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 59.86% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 59.86% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 59.86% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 59.86% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 59.86% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 59.86% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 59.86% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 59.86% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 59.86% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 59.86% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 59.86% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 59.86% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 59.86% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 59.86% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 59.86% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 59.86% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 59.86% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 59.86% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 59.86% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 59.86% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 59.86% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 59.86% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 59.86% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 59.86% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 59.86% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 59.86% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 59.86% # Class of executed instruction +system.cpu.op_class::MemRead 61526 23.25% 83.11% # Class of executed instruction +system.cpu.op_class::MemWrite 44702 16.89% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 264666 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 449273500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 249.353614 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 105933 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 294 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 360.316327 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 249.353614 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.060877 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.060877 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 294 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 281 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.071777 # Percentage of cache occupancy per task id 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for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.998970 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.998970 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.998970 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.999209 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.998970 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.999209 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60500.515464 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60500.515464 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60500.515464 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60500.395570 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60500.515464 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60500.395570 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 205 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 205 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 970 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 970 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 89 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 89 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 970 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 294 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1264 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 970 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 294 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1264 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10352500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10352500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 48985500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 48985500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4494500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4494500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 48985500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14847000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 63832500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 48985500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14847000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 63832500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.998970 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.998970 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.998970 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.999209 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.998970 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.999209 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50500.515464 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50500.515464 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50500.515464 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.395570 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50500.515464 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.395570 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1279 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 14 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 449273500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 1060 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 14 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 205 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 205 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 971 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 89 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1956 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 588 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2544 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63040 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 81856 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 1265 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1265 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1265 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 653500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1456500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 441000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 1264 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 449273500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1059 # Transaction distribution +system.membus.trans_dist::ReadExReq 205 # Transaction distribution +system.membus.trans_dist::ReadExResp 205 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1059 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2528 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2528 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 80896 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 80896 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1264 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1264 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1264 # Request fanout histogram +system.membus.reqLayer0.occupancy 1264500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 6320000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.4 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/config.ini --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/config.ini Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,896 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=MinorCPU +children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload +branchPred=system.cpu.branchPred +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +decodeCycleInput=true +decodeInputBufferSize=3 +decodeInputWidth=2 +decodeToExecuteForwardDelay=1 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +enableIdling=true +eventq_index=0 +executeAllowEarlyMemoryIssue=true +executeBranchDelay=1 +executeCommitLimit=2 +executeCycleInput=true +executeFuncUnits=system.cpu.executeFuncUnits +executeInputBufferSize=7 +executeInputWidth=2 +executeIssueLimit=2 +executeLSQMaxStoreBufferStoresPerCycle=2 +executeLSQRequestsQueueSize=1 +executeLSQStoreBufferSize=5 +executeLSQTransfersQueueSize=2 +executeMaxAccessesInMemory=2 +executeMemoryCommitLimit=1 +executeMemoryIssueLimit=1 +executeMemoryWidth=0 +executeSetTraceTimeOnCommit=true +executeSetTraceTimeOnIssue=false +fetch1FetchLimit=1 +fetch1LineSnapWidth=0 +fetch1LineWidth=0 +fetch1ToFetch2BackwardDelay=1 +fetch1ToFetch2ForwardDelay=1 +fetch2CycleInput=true +fetch2InputBufferSize=2 +fetch2ToDecodeForwardDelay=1 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +threadPolicy=RoundRobin +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TournamentBP +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +useIndirect=true + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +hit_latency=2 +is_read_only=false +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=262144 + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.executeFuncUnits] +type=MinorFUPool +children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 +eventq_index=0 +funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 + +[system.cpu.executeFuncUnits.funcUnits0] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits0.timings + +[system.cpu.executeFuncUnits.funcUnits0.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits0.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits1] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits1.timings + +[system.cpu.executeFuncUnits.funcUnits1.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits1.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits2] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits2.timings + +[system.cpu.executeFuncUnits.funcUnits2.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntMult + +[system.cpu.executeFuncUnits.funcUnits2.timings] +type=MinorFUTiming +children=opClasses +description=Mul +eventq_index=0 +extraAssumedLat=0 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"MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits5.timings.opClasses", + "type": "MinorOpClassSet" + }, + "cxx_class": "MinorFUTiming", + "path": "system.cpu.executeFuncUnits.funcUnits5.timings", + "extraCommitLatExpr": null, + "type": "MinorFUTiming", + "match": 0, + "name": "timings" + } + ], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits5", + "type": "MinorFU" + }, + { + "issueLat": 1, + "opLat": 1, + "name": "funcUnits6", + "cantForwardFromFUIndices": [], + "opClasses": { + "name": "opClasses", + "opClasses": [ + { + "opClass": "IprAccess", + "name": "opClasses0", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0", + "type": "MinorOpClass" + }, + { + "opClass": "InstPrefetch", + "name": "opClasses1", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1", + "type": "MinorOpClass" + } + ], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits6.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits6", + "type": "MinorFU" + } + ], + "type": "MinorFUPool" + }, + "switched_out": false, + "power_model": null, + "max_insts_all_threads": 0, + "executeSetTraceTimeOnIssue": false, + "fetch2InputBufferSize": 2, + "profile": 0, + "fetch2ToDecodeForwardDelay": 1, + "executeInputWidth": 2, + "decodeToExecuteForwardDelay": 1, + "executeLSQRequestsQueueSize": 1, + "fetch2CycleInput": true, + "executeMaxAccessesInMemory": 2, + "enableIdling": true, + "executeLSQStoreBufferSize": 5, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64m/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "executeSetTraceTimeOnCommit": true, + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + }, + "threadPolicy": "RoundRobin", + "executeCommitLimit": 2, + "fetch1LineWidth": 0, + "branchPred": { + "numThreads": 1, + "BTBEntries": 4096, + "cxx_class": "TournamentBP", + "indirectPathLength": 3, + "globalCtrBits": 2, + "choicePredictorSize": 8192, + "indirectHashGHR": true, + "eventq_index": 0, + "localHistoryTableSize": 2048, + "type": "TournamentBP", + "indirectSets": 256, + "indirectWays": 2, + "choiceCtrBits": 2, + "useIndirect": true, + "localCtrBits": 2, + "path": "system.cpu.branchPred", + "localPredictorSize": 2048, + "RASSize": 16, + "globalPredictorSize": 8192, + "name": "branchPred", + "indirectHashTargets": true, + "instShiftAmt": 2, + "indirectTagSize": 16, + "BTBTagSize": 16 + }, + "dcache": { + "cpu_side": { + "peer": "system.cpu.dcache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 262144, + "tags": { + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.dcache.tags", + "hit_latency": 2, + "block_size": 64, + "type": "LRU", + "size": 262144 + }, + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[1]", + "role": "MASTER" + }, + "type": "Cache", + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "hit_latency": 2, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.dcache", + "mshrs": 4, + "name": "dcache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "path": "system.cpu", + "fetch1ToFetch2ForwardDelay": 1, + "decodeInputBufferSize": 3 + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/simerr --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/simerr Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,4 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/simout --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/simout Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,51 @@ +Redirecting stdout to build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64m/minor-timing/simout +Redirecting stderr to build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64m/minor-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 2 2016 20:34:02 +gem5 started Nov 3 2016 18:41:36 +gem5 executing on ubuntu1604, pid 21470 +command line: /home/ar4jc/gem5/build/RISCV/gem5.debug -d build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64m/minor-timing -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64m/minor-timing + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +mul: PASS +mul, overflow: PASS +mulh: PASS +mulh, negative: PASS +mulh, all bits set: PASS +mulhsu, all bits set: PASS +mulhsu: PASS +mulhu: PASS +mulhu, all bits set: PASS +div: PASS +div/0: PASS +div, overflow: PASS +divu: PASS +divu/0: PASS +divu, "overflow": PASS +rem: PASS +rem/0: PASS +rem, overflow: PASS +remu: PASS +remu/0: PASS +remu, "overflow": PASS +mulw, truncate: PASS +mulw, overflow: PASS +divw, truncate: PASS +divw/0: PASS +divw, overflow: PASS +divuw, truncate: PASS +divuw/0: PASS +divuw, "overflow": PASS +divuw, sign extend: PASS +remw, truncate: PASS +remw/0: PASS +remw, overflow: PASS +remuw, truncate: PASS +remuw/0: PASS +remuw, "overflow": PASS +remuw, sign extend: PASS +Exiting @ tick 164974500 because target called exit() diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/stats.txt --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/stats.txt Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,765 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000165 # Number of seconds simulated +sim_ticks 164974500 # Number of ticks simulated +final_tick 164974500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 17511 # Simulator instruction rate (inst/s) +host_op_rate 17511 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 25976591 # Simulator tick rate (ticks/s) +host_mem_usage 276516 # Number of bytes of host memory used +host_seconds 6.35 # Real time elapsed on the host +sim_insts 111210 # Number of instructions simulated +sim_ops 111210 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 164974500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 50944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 16960 # Number of bytes read from this memory +system.physmem.bytes_read::total 67904 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 50944 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 50944 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 796 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 265 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1061 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 308799239 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 102803767 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 411603005 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 308799239 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 308799239 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 308799239 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 102803767 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 411603005 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1061 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 1061 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 67904 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 67904 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 65 # Per bank write bursts +system.physmem.perBankRdBursts::1 85 # Per bank write bursts +system.physmem.perBankRdBursts::2 31 # Per bank write bursts +system.physmem.perBankRdBursts::3 107 # Per bank write bursts +system.physmem.perBankRdBursts::4 52 # Per bank write bursts +system.physmem.perBankRdBursts::5 24 # Per bank write bursts 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+system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 191 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 348.146597 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 241.706671 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 288.954958 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 37 19.37% 19.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 48 25.13% 44.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 39 20.42% 64.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 18 9.42% 74.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 10 5.24% 79.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 15 7.85% 87.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7 3.66% 91.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 4 2.09% 93.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 13 6.81% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 191 # Bytes accessed per row activation +system.physmem.totQLat 13354250 # Total ticks spent queuing +system.physmem.totMemAccLat 33248000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5305000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12586.48 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 31336.48 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 411.60 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 411.60 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 3.22 # Data bus utilization in percentage +system.physmem.busUtilRead 3.22 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 864 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.43 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 155237.98 # Average gap between requests +system.physmem.pageHitRate 81.43 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 699720 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 364320 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3227280 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 12907440.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 8209140 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 279360 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 57994080 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 7320960 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 91002300 # Total energy per rank (pJ) +system.physmem_0.averagePower 551.612669 # Core power per rank (mW) +system.physmem_0.totalIdleTime 145865000 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 132000 # Time in different power states +system.physmem_0.memoryStateTime::REF 5460000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 0 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 19063250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 13121250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 127198000 # Time in different power states +system.physmem_1.actEnergy 706860 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 360525 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4348260 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 11063520.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 9770370 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 361920 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 44570580 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 6601920 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 7193340 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 84977295 # Total energy per rank (pJ) +system.physmem_1.averagePower 515.091953 # Core power per rank (mW) +system.physmem_1.totalIdleTime 142378500 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 453500 # Time in different power states +system.physmem_1.memoryStateTime::REF 4686000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 27670750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 17190750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 17226250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 97747250 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 164974500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 31666 # Number of BP lookups +system.cpu.branchPred.condPredicted 20087 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2257 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 29079 # Number of BTB lookups +system.cpu.branchPred.BTBHits 15010 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 51.618006 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 5805 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 3705 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 2100 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 1036 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 46 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 164974500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 329949 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 111210 # Number of instructions committed +system.cpu.committedOps 111210 # Number of ops (including micro ops) committed +system.cpu.discardedOps 6001 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 2.966900 # CPI: cycles per instruction +system.cpu.ipc 0.337052 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 46 0.04% 0.04% # Class of committed instruction +system.cpu.op_class_0::IntAlu 68715 61.79% 61.83% # Class of committed instruction +system.cpu.op_class_0::IntMult 122 0.11% 61.94% # Class of committed instruction +system.cpu.op_class_0::IntDiv 26 0.02% 61.96% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 0 0.00% 61.96% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 0 0.00% 61.96% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 0 0.00% 61.96% # Class of committed instruction +system.cpu.op_class_0::FloatMult 0 0.00% 61.96% # Class of committed instruction +system.cpu.op_class_0::FloatMultAcc 0 0.00% 61.96% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 0 0.00% 61.96% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 0 0.00% 61.96% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 61.96% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 61.96% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 61.96% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 61.96% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 61.96% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 61.96% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 61.96% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 61.96% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 61.96% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 61.96% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 61.96% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 61.96% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 61.96% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 61.96% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 61.96% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 0 0.00% 61.96% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 61.96% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 0 0.00% 61.96% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 61.96% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 61.96% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 61.96% # Class of committed instruction +system.cpu.op_class_0::MemRead 22338 20.09% 82.05% # Class of committed instruction +system.cpu.op_class_0::MemWrite 19963 17.95% 100.00% # Class of committed instruction +system.cpu.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::total 111210 # Class of committed instruction +system.cpu.tickCycles 173861 # Number of cycles that the object actually ticked +system.cpu.idleCycles 156088 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 164974500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 213.985704 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42747 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 266 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 160.703008 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 213.985704 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.052243 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.052243 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 266 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 58 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 203 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.064941 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 86682 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 86682 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 164974500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 23170 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23170 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 19577 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 19577 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 42747 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42747 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42747 # number of overall hits +system.cpu.dcache.overall_hits::total 42747 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 76 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 76 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 385 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 385 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 461 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 461 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 461 # number of overall misses +system.cpu.dcache.overall_misses::total 461 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6664500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6664500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 30785000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 30785000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 37449500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 37449500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 37449500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 37449500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23246 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23246 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19962 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19962 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 43208 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 43208 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 43208 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 43208 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003269 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003269 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019287 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.019287 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.010669 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.010669 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.010669 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.010669 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 87690.789474 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 87690.789474 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79961.038961 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 79961.038961 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 81235.357918 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 81235.357918 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 81235.357918 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 81235.357918 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 188 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 188 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 195 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 195 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 195 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 195 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 69 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 69 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 197 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 197 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 266 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 266 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 266 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 266 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6025500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6025500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 15724500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 15724500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21750000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 21750000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21750000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 21750000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002968 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002968 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009869 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009869 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006156 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006156 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006156 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006156 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 87326.086957 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 87326.086957 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79819.796954 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79819.796954 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81766.917293 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 81766.917293 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81766.917293 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 81766.917293 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 164974500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 102 # number of replacements +system.cpu.icache.tags.tagsinuse 375.605669 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 51138 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 844 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 60.590047 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 375.605669 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.183401 # Average percentage of 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72856.783920 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70520.754717 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72273.327050 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1212 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 103 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 164974500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 913 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 102 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 197 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 197 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 844 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 69 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1790 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 532 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2322 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 60544 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17024 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 77568 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 1110 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001802 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.042428 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1108 99.82% 99.82% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2 0.18% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1110 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 708000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1266000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 399000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 1061 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 164974500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 864 # Transaction distribution +system.membus.trans_dist::ReadExReq 197 # Transaction distribution +system.membus.trans_dist::ReadExResp 197 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 864 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2122 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2122 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 67904 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 67904 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1061 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1061 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1061 # Request fanout histogram +system.membus.reqLayer0.occupancy 1190000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 5627000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 3.4 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/config.ini --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/config.ini Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,866 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cachePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +default_p_state=UNDEFINED +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=0 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +system=system +tracer=system.cpu.tracer +trapLatency=13 +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TournamentBP +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +useIndirect=true + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +hit_latency=2 +is_read_only=false +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=262144 + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +eventq_index=0 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +opClass=IntAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +eventq_index=0 +opClass=IntMult +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +eventq_index=0 +opClass=IntDiv +opLat=20 +pipelined=false + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +eventq_index=0 +opClass=FloatAdd +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatCmp +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatCvt +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 opList3 opList4 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +eventq_index=0 +opClass=FloatMult +opLat=4 +pipelined=true + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMultAcc +opLat=5 +pipelined=true + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMisc +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList3.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatDiv +opLat=12 +pipelined=false + +[system.cpu.fuPool.FUList3.opList4] +type=OpDesc +eventq_index=0 +opClass=FloatSqrt +opLat=24 +pipelined=false + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList0 opList1 +count=0 +eventq_index=0 +opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +eventq_index=0 +opClass=MemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList4.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5] +type=FUDesc +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 + +[system.cpu.fuPool.FUList5.opList00] +type=OpDesc +eventq_index=0 +opClass=SimdAdd +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList01] +type=OpDesc +eventq_index=0 +opClass=SimdAddAcc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList02] +type=OpDesc +eventq_index=0 +opClass=SimdAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList03] +type=OpDesc +eventq_index=0 +opClass=SimdCmp +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList04] +type=OpDesc +eventq_index=0 +opClass=SimdCvt +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList05] +type=OpDesc +eventq_index=0 +opClass=SimdMisc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList06] +type=OpDesc +eventq_index=0 +opClass=SimdMult +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList07] +type=OpDesc +eventq_index=0 +opClass=SimdMultAcc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList08] +type=OpDesc +eventq_index=0 +opClass=SimdShift +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList09] +type=OpDesc +eventq_index=0 +opClass=SimdShiftAcc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList10] +type=OpDesc +eventq_index=0 +opClass=SimdSqrt +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList11] +type=OpDesc +eventq_index=0 +opClass=SimdFloatAdd +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList12] +type=OpDesc +eventq_index=0 +opClass=SimdFloatAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList13] +type=OpDesc +eventq_index=0 +opClass=SimdFloatCmp +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList14] +type=OpDesc +eventq_index=0 +opClass=SimdFloatCvt +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList15] +type=OpDesc +eventq_index=0 +opClass=SimdFloatDiv +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList16] +type=OpDesc +eventq_index=0 +opClass=SimdFloatMisc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList17] +type=OpDesc +eventq_index=0 +opClass=SimdFloatMult +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList18] +type=OpDesc +eventq_index=0 +opClass=SimdFloatMultAcc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList19] +type=OpDesc +eventq_index=0 +opClass=SimdFloatSqrt +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList6] +type=FUDesc +children=opList0 opList1 +count=0 +eventq_index=0 +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +eventq_index=0 +opClass=MemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7] +type=FUDesc +children=opList0 opList1 opList2 opList3 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +eventq_index=0 +opClass=MemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7.opList1] +type=OpDesc +eventq_index=0 +opClass=MemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList8] +type=FUDesc +children=opList +count=1 +eventq_index=0 +opList=system.cpu.fuPool.FUList8.opList + +[system.cpu.fuPool.FUList8.opList] +type=OpDesc +eventq_index=0 +opClass=IprAccess +opLat=3 +pipelined=false + +[system.cpu.icache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +hit_latency=2 +is_read_only=true +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tags=system.cpu.icache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=131072 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.l2cache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +hit_latency=20 +is_read_only=false +max_miss_count=0 +mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain 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b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/config.json Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,1145 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.l2cache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": 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"count": 0, + "opList": [ + { + "opClass": "MemWrite", + "opLat": 1, + "name": "opList0", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList6.opList0", + "type": "OpDesc" + }, + { + "opClass": "FloatMemWrite", + "opLat": 1, + "name": "opList1", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList6.opList1", + "type": "OpDesc" + } + ], + "name": "FUList6", + "eventq_index": 0, + "cxx_class": "FUDesc", + "path": "system.cpu.fuPool.FUList6", + "type": "FUDesc" + }, + { + "count": 4, + "opList": [ + { + "opClass": "MemRead", + "opLat": 1, + "name": "opList0", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList7.opList0", + "type": "OpDesc" + }, + { + "opClass": "MemWrite", + "opLat": 1, + "name": "opList1", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList7.opList1", + "type": "OpDesc" + }, + { + "opClass": "FloatMemRead", + "opLat": 1, + "name": "opList2", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList7.opList2", + "type": "OpDesc" + }, + { + "opClass": "FloatMemWrite", + "opLat": 1, + "name": "opList3", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList7.opList3", + "type": "OpDesc" + } + ], + "name": "FUList7", + "eventq_index": 0, + "cxx_class": "FUDesc", + "path": "system.cpu.fuPool.FUList7", + "type": "FUDesc" + }, + { + "count": 1, + "opList": [ + { + "opClass": "IprAccess", + "opLat": 3, + "name": "opList", + "pipelined": false, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList8.opList", + "type": "OpDesc" + } + ], + "name": "FUList8", + "eventq_index": 0, + "cxx_class": "FUDesc", + "path": "system.cpu.fuPool.FUList8", + "type": "FUDesc" + } + ], + "eventq_index": 0, + "cxx_class": "FUPool", + "path": "system.cpu.fuPool", + "type": "FUPool" + }, + "socket_id": 0, + "renameToFetchDelay": 1, + "icache": { + "cpu_side": { + "peer": "system.cpu.icache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 131072, + "tags": { + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.icache.tags", + "hit_latency": 2, + "block_size": 64, + "type": "LRU", + "size": 131072 + }, + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[0]", + "role": "MASTER" + }, + "type": "Cache", + "writeback_clean": true, + "p_state_clk_gate_min": 1000, + "hit_latency": 2, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": true, + "prefetch_on_access": false, + "path": "system.cpu.icache", + "mshrs": 4, + "name": "icache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "path": "system.cpu", + "numRobs": 1, + "switched_out": false, + "smtLSQPolicy": "Partitioned", + "fetchBufferSize": 64, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "smtROBThreshold": 100, + "numIQEntries": 64, + "branchPred": { + "numThreads": 1, + "BTBEntries": 4096, + "cxx_class": "TournamentBP", + "indirectPathLength": 3, + "globalCtrBits": 2, + "choicePredictorSize": 8192, + "indirectHashGHR": true, + "eventq_index": 0, + "localHistoryTableSize": 2048, + "type": "TournamentBP", + "indirectSets": 256, + "indirectWays": 2, + "choiceCtrBits": 2, + "useIndirect": true, + "localCtrBits": 2, + "path": "system.cpu.branchPred", + "localPredictorSize": 2048, + "RASSize": 16, + "globalPredictorSize": 8192, + "name": "branchPred", + "indirectHashTargets": true, + "instShiftAmt": 2, + "indirectTagSize": 16, + "BTBTagSize": 16 + }, + "LFSTSize": 1024, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "smtROBPolicy": "Partitioned", + "iewToFetchDelay": 1, + "do_statistics_insts": true, + "dispatchWidth": 8, + "dcache": { + "cpu_side": { + "peer": "system.cpu.dcache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 262144, + "tags": { + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.dcache.tags", + "hit_latency": 2, + "block_size": 64, + "type": "LRU", + "size": 262144 + }, + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[1]", + "role": "MASTER" + }, + "type": "Cache", + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "hit_latency": 2, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.dcache", + "mshrs": 4, + "name": "dcache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "commitToDecodeDelay": 1, + "smtIQPolicy": "Partitioned", + "issueWidth": 8, + "LSQCheckLoads": true, + "commitToRenameDelay": 1, + "cachePorts": 200, + "system": "system", + "checker": null, + "numPhysFloatRegs": 256, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "type": "DerivO3CPU", + "wbWidth": 8, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "smtCommitPolicy": "RoundRobin", + "issueToExecuteDelay": 1, + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "numROBEntries": 192, + "fetchQueueSize": 32, + "iewToCommitDelay": 1, + "smtNumFetchingThreads": 1, + "forwardComSize": 5, + "do_checkpoint_insts": true, + "cxx_class": "DerivO3CPU", + "commitToIEWDelay": 1, + "commitWidth": 8, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "smtFetchPolicy": "SingleThread", + "profile": 0, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "role": "MASTER" + }, + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "role": "MASTER" + }, + "LSQDepCheckShift": 4, + "trapLatency": 13, + "iewToDecodeDelay": 1, + "numPhysCCRegs": 0, + "renameToIEWDelay": 2, + "p_state_clk_gate_bins": 20, + "progress_interval": 0, + "LQEntries": 32 + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/simerr --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/simerr Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,4 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/simout --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/simout Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,51 @@ +Redirecting stdout to build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64m/o3-timing/simout +Redirecting stderr to build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64m/o3-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 2 2016 20:34:02 +gem5 started Nov 3 2016 18:41:43 +gem5 executing on ubuntu1604, pid 21471 +command line: /home/ar4jc/gem5/build/RISCV/gem5.debug -d build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64m/o3-timing -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64m/o3-timing + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +mul: PASS +mul, overflow: PASS +mulh: PASS +mulh, negative: PASS +mulh, all bits set: PASS +mulhsu, all bits set: PASS +mulhsu: PASS +mulhu: PASS +mulhu, all bits set: PASS +div: PASS +div/0: PASS +div, overflow: PASS +divu: PASS +divu/0: PASS +divu, "overflow": PASS +rem: PASS +rem/0: PASS +rem, overflow: PASS +remu: PASS +remu/0: PASS +remu, "overflow": PASS +mulw, truncate: PASS +mulw, overflow: PASS +divw, truncate: PASS +divw/0: PASS +divw, overflow: PASS +divuw, truncate: PASS +divuw/0: PASS +divuw, "overflow": PASS +divuw, sign extend: PASS +remw, truncate: PASS +remw/0: PASS +remw, overflow: PASS +remuw, truncate: PASS +remuw/0: PASS +remuw, "overflow": PASS +remuw, sign extend: PASS +Exiting @ tick 70271000 because target called exit() diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/stats.txt --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/o3-timing/stats.txt Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,1012 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000070 # Number of seconds simulated +sim_ticks 70271000 # Number of ticks simulated +final_tick 70271000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 16308 # Simulator instruction rate (inst/s) +host_op_rate 16307 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 10308608 # Simulator tick rate (ticks/s) +host_mem_usage 277040 # Number of bytes of host memory used +host_seconds 6.82 # Real time elapsed on the host +sim_insts 111163 # Number of instructions simulated +sim_ops 111163 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 70271000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 49408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 17024 # Number of bytes read from this memory +system.physmem.bytes_read::total 66432 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 49408 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 49408 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 772 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 266 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1038 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 703106545 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 242262100 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 945368644 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 703106545 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 703106545 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 703106545 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 242262100 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 945368644 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1039 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 1039 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 66432 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 66496 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 67 # Per bank write bursts +system.physmem.perBankRdBursts::1 84 # Per bank write bursts +system.physmem.perBankRdBursts::2 36 # Per bank write bursts +system.physmem.perBankRdBursts::3 108 # Per bank write bursts +system.physmem.perBankRdBursts::4 45 # Per bank write bursts +system.physmem.perBankRdBursts::5 23 # Per bank write bursts +system.physmem.perBankRdBursts::6 2 # Per bank write bursts +system.physmem.perBankRdBursts::7 79 # Per bank write bursts +system.physmem.perBankRdBursts::8 155 # Per bank write bursts +system.physmem.perBankRdBursts::9 96 # Per bank write bursts +system.physmem.perBankRdBursts::10 33 # Per bank write bursts +system.physmem.perBankRdBursts::11 138 # Per bank write bursts +system.physmem.perBankRdBursts::12 98 # Per bank write bursts +system.physmem.perBankRdBursts::13 59 # Per bank write bursts +system.physmem.perBankRdBursts::14 14 # Per bank write bursts +system.physmem.perBankRdBursts::15 1 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 70179000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 1039 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 592 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 297 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 104 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 41 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 183 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 358.120219 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 231.386170 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 323.291259 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 46 25.14% 25.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 37 20.22% 45.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 34 18.58% 63.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20 10.93% 74.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 7 3.83% 78.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 10 5.46% 84.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3 1.64% 85.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 4 2.19% 87.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22 12.02% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 183 # Bytes accessed per row activation +system.physmem.totQLat 12955000 # Total ticks spent queuing +system.physmem.totMemAccLat 32417500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5190000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12468.72 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 4995.19 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 31200.67 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 945.37 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 946.28 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 7.39 # Data bus utilization in percentage +system.physmem.busUtilRead 7.39 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.59 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 851 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.91 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 67544.75 # Average gap between requests +system.physmem.pageHitRate 81.91 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 635460 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 337755 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3170160 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 5531760.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 6236370 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 113280 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 23424720 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 1920480 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 41369985 # Total energy per rank (pJ) +system.physmem_0.averagePower 588.122188 # Core power per rank (mW) +system.physmem_0.totalIdleTime 56386500 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 47500 # Time in different power states +system.physmem_0.memoryStateTime::REF 2255000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 0 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 4999500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 11582000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 51387000 # Time in different power states +system.physmem_1.actEnergy 699720 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 356730 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4241160 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 5531760.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 6646200 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 297120 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 17089170 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 4747200 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 1772340 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 41381400 # Total energy per rank (pJ) +system.physmem_1.averagePower 588.880943 # Core power per rank (mW) +system.physmem_1.totalIdleTime 54863500 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 436500 # Time in different power states +system.physmem_1.memoryStateTime::REF 2346000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 5084000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 12361250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 12569250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 37474000 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 70271000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 38857 # Number of BP lookups +system.cpu.branchPred.condPredicted 24514 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2760 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 34900 # Number of BTB lookups +system.cpu.branchPred.BTBHits 18550 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 53.151862 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 7530 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 3964 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 3566 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 1262 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 46 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 70271000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 140543 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.fetch.icacheStallCycles 38418 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 164923 # Number of instructions fetch has processed +system.cpu.fetch.Branches 38857 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 22514 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 44767 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5660 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 465 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 196 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 27700 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1488 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 86676 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.902753 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.722389 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 48918 56.44% 56.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4664 5.38% 61.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 7545 8.70% 70.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5035 5.81% 76.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3693 4.26% 80.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4174 4.82% 85.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2248 2.59% 88.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2258 2.61% 90.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8141 9.39% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 86676 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.276478 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.173470 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 38728 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 10986 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 33822 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 875 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2265 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 6059 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 595 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 151531 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2059 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2265 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 40356 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3213 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1212 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 33017 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6613 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 144878 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 24 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 47 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 71 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 6284 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 98377 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 191284 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 191284 # Number of integer rename lookups +system.cpu.rename.CommittedMaps 73798 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 24579 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 63 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 61 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 3004 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26829 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22754 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 594 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 149 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 134049 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 60 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 128147 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 324 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 22942 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 12417 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 86676 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.478460 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.849163 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 39050 45.05% 45.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 15491 17.87% 62.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 11904 13.73% 76.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6669 7.69% 84.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4269 4.93% 89.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 5510 6.36% 95.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2639 3.04% 98.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 771 0.89% 99.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 373 0.43% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 86676 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 478 13.88% 13.88% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 13.88% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 13.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 13.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 13.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 13.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 13.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 13.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 13.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 13.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 13.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 13.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 13.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 13.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 13.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 13.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 13.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 13.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 13.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 13.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 13.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 13.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 13.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 13.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 13.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 13.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 13.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 13.88% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1408 40.87% 54.75% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1559 45.25% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 46 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 80574 62.88% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 128 0.10% 63.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 36 0.03% 63.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 63.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 63.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 63.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 63.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 63.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 63.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 63.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 63.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 63.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 63.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 63.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 63.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 63.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 63.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 63.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 63.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 63.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 63.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 63.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 63.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 63.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 63.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 63.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 63.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 63.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 63.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 63.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 63.04% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25773 20.11% 83.15% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21590 16.85% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 128147 # Type of FU issued +system.cpu.iq.rate 0.911799 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3445 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.026883 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 346739 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 157085 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 122594 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 131546 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2358 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 4491 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 65 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2792 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 68 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 2265 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2410 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 111 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 134106 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1236 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 26829 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22754 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 57 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 107 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 546 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1970 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2516 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 124201 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25144 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3946 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 0 # number of nop insts executed +system.cpu.iew.exec_refs 46226 # number of memory reference insts executed +system.cpu.iew.exec_branches 29006 # Number of branches executed +system.cpu.iew.exec_stores 21082 # Number of stores executed +system.cpu.iew.exec_rate 0.883722 # Inst execution rate +system.cpu.iew.wb_sent 123128 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 122594 # cumulative count of insts written-back +system.cpu.iew.wb_producers 44987 # num instructions producing a value +system.cpu.iew.wb_consumers 63150 # num instructions consuming a value +system.cpu.iew.wb_rate 0.872288 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.712383 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 22948 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 46 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 2195 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 82250 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.351526 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.100258 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 45647 55.50% 55.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13274 16.14% 71.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 5509 6.70% 78.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 5313 6.46% 84.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3111 3.78% 88.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4387 5.33% 93.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1339 1.63% 95.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 841 1.02% 96.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2829 3.44% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 82250 # Number of insts commited each cycle +system.cpu.commit.committedInsts 111163 # Number of instructions committed +system.cpu.commit.committedOps 111163 # Number of ops (including micro ops) committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.refs 42300 # Number of memory references committed +system.cpu.commit.loads 22338 # Number of loads committed +system.cpu.commit.membars 0 # Number of memory barriers committed +system.cpu.commit.branches 25914 # Number of branches committed +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.int_insts 111163 # Number of committed integer instructions. +system.cpu.commit.function_calls 8511 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 68715 61.81% 61.81% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 122 0.11% 61.92% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 26 0.02% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.95% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 22338 20.09% 82.04% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 19962 17.96% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 111163 # Class of committed instruction +system.cpu.commit.bw_lim_events 2829 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 212934 # The number of ROB reads +system.cpu.rob.rob_writes 272727 # The number of ROB writes +system.cpu.timesIdled 427 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 53867 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 111163 # Number of Instructions Simulated +system.cpu.committedOps 111163 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.264297 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.264297 # CPI: Total CPI of All Threads +system.cpu.ipc 0.790954 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.790954 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 163454 # number of integer regfile reads +system.cpu.int_regfile_writes 83246 # number of integer regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 70271000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 218.005978 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40946 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 266 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 153.932331 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 218.005978 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.053224 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.053224 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 266 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 258 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.064941 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 85540 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 85540 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 70271000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 22453 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22453 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18493 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18493 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 40946 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40946 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40946 # number of overall hits +system.cpu.dcache.overall_hits::total 40946 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 222 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 222 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1469 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1469 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1691 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1691 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1691 # number of overall misses +system.cpu.dcache.overall_misses::total 1691 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 16744000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 16744000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 96405432 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 96405432 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 113149432 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 113149432 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 113149432 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 113149432 # number of overall miss cycles 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0.968672 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.968672 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.968672 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.976548 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.968672 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.976548 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78114.213198 # average ReadExReq miss latency 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average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 82073.006724 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 197 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 197 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 773 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 773 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 71 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 71 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 773 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 268 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1041 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 773 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 268 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1041 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13418500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13418500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 56179000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 56179000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5460500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5460500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 56179000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18879000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 75058000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 56179000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18879000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 75058000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.968672 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.968672 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.968672 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.976548 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.968672 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.976548 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68114.213198 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68114.213198 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72676.584735 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72676.584735 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76908.450704 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76908.450704 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72676.584735 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70444.029851 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72101.825168 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72676.584735 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70444.029851 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72101.825168 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1142 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 76 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 70271000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 866 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 76 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 197 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 197 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 798 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 71 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1671 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 534 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2205 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 55872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17024 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 72896 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 1066 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1066 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1066 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 647000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1195500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 399000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 1039 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 70271000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 841 # Transaction distribution +system.membus.trans_dist::ReadExReq 197 # Transaction distribution +system.membus.trans_dist::ReadExResp 197 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 842 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2077 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2077 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 66432 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 66432 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1039 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1039 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1039 # Request fanout histogram +system.membus.reqLayer0.occupancy 1258500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 5465500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 7.8 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-atomic/config.ini --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-atomic/config.ini Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,211 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=atomic +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=AtomicSimpleCPU +children=dtb interrupts isa itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fastmem=false +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +simulate_data_stalls=false +simulate_inst_stalls=false +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +width=1 +workload=system.cpu.workload +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64m/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +eventq_index=0 +in_addr_map=true +kvm_map=true +latency=30000 +latency_var=0 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +range=0:134217727:0:0:0:0 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-atomic/config.json --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-atomic/config.json Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,289 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.icache_port", + "system.cpu.dcache_port" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "physmem": { + "range": "0:134217727:0:0:0:0", + "latency": 30000, + "name": "physmem", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "kvm_map": true, + "clk_domain": "system.clk_domain", + "power_model": null, + "latency_var": 0, + "bandwidth": "73.000000", + "conf_table_reported": true, + "cxx_class": "SimpleMemory", + "p_state_clk_gate_max": 1000000000000, + "path": "system.physmem", + "null": false, + "type": "SimpleMemory", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "in_addr_map": true + }, + "power_model": null, + "work_cpus_ckpt_count": 0, + "thermal_components": [], + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "work_end_ckpt_count": 0, + "mem_mode": "atomic", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": [ + { + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.itb", + "type": "RiscvTLB", + "size": 64 + }, + "simulate_data_stalls": false, + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "AtomicSimpleCPU", + "max_loads_all_threads": 0, + "system": "system", + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "cpu_id": 0, + "width": 1, + "checker": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "do_quiesce": true, + "type": "AtomicSimpleCPU", + "fastmem": false, + "profile": 0, + "icache_port": { + "peer": "system.membus.slave[1]", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "p_state_clk_gate_min": 1000, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "dcache_port": { + "peer": "system.membus.slave[2]", + "role": "MASTER" + }, + "socket_id": 0, + "power_model": null, + "max_insts_all_threads": 0, + "path": "system.cpu", + "max_loads_any_thread": 0, + "switched_out": false, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64m/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "simulate_inst_stalls": false, + "progress_interval": 0, + "branchPred": null, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-atomic/simerr --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-atomic/simerr Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,3 @@ +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-atomic/simout --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-atomic/simout Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,51 @@ +Redirecting stdout to build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64m/simple-atomic/simout +Redirecting stderr to build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64m/simple-atomic/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 2 2016 20:34:02 +gem5 started Nov 3 2016 18:41:51 +gem5 executing on ubuntu1604, pid 21472 +command line: /home/ar4jc/gem5/build/RISCV/gem5.debug -d build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64m/simple-atomic -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64m/simple-atomic + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +mul: PASS +mul, overflow: PASS +mulh: PASS +mulh, negative: PASS +mulh, all bits set: PASS +mulhsu, all bits set: PASS +mulhsu: PASS +mulhu: PASS +mulhu, all bits set: PASS +div: PASS +div/0: PASS +div, overflow: PASS +divu: PASS +divu/0: PASS +divu, "overflow": PASS +rem: PASS +rem/0: PASS +rem, overflow: PASS +remu: PASS +remu/0: PASS +remu, "overflow": PASS +mulw, truncate: PASS +mulw, overflow: PASS +divw, truncate: PASS +divw/0: PASS +divw, overflow: PASS +divuw, truncate: PASS +divuw/0: PASS +divuw, "overflow": PASS +divuw, sign extend: PASS +remw, truncate: PASS +remw/0: PASS +remw, overflow: PASS +remuw, truncate: PASS +remuw/0: PASS +remuw, "overflow": PASS +remuw, sign extend: PASS +Exiting @ tick 55604500 because target called exit() diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-atomic/stats.txt --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-atomic/stats.txt Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,153 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000056 # Number of seconds simulated +sim_ticks 55604500 # Number of ticks simulated +final_tick 55604500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 50713 # Simulator instruction rate (inst/s) +host_op_rate 50712 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 25366393 # Simulator tick rate (ticks/s) +host_mem_usage 265000 # Number of bytes of host memory used +host_seconds 2.19 # Real time elapsed on the host +sim_insts 111163 # Number of instructions simulated +sim_ops 111163 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 55604500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 444840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 144202 # Number of bytes read from this memory +system.physmem.bytes_read::total 589042 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 444840 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 444840 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 112141 # Number of bytes written to this memory +system.physmem.bytes_written::total 112141 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 111210 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 22338 # Number of read requests responded to by this memory +system.physmem.num_reads::total 133548 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 19962 # Number of write requests responded to by this memory +system.physmem.num_writes::total 19962 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 8000071937 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2593351258 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10593423194 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8000071937 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8000071937 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 2016761233 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2016761233 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8000071937 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4610112491 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 12610184428 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 55604500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 46 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 55604500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 111210 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 111163 # Number of instructions committed +system.cpu.committedOps 111163 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 111164 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 8511 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 17403 # number of instructions that are conditional controls +system.cpu.num_int_insts 111164 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 148887 # number of times the integer registers were read +system.cpu.num_int_register_writes 73798 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 42301 # number of memory refs +system.cpu.num_load_insts 22338 # Number of load instructions +system.cpu.num_store_insts 19963 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 111210 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 25914 # Number of branches fetched +system.cpu.op_class::No_OpClass 46 0.04% 0.04% # Class of executed instruction +system.cpu.op_class::IntAlu 68715 61.79% 61.83% # Class of executed instruction +system.cpu.op_class::IntMult 122 0.11% 61.94% # Class of executed instruction +system.cpu.op_class::IntDiv 26 0.02% 61.96% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.96% # Class of executed instruction +system.cpu.op_class::MemRead 22338 20.09% 82.05% # Class of executed instruction +system.cpu.op_class::MemWrite 19963 17.95% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 111210 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 55604500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 133548 # Transaction distribution +system.membus.trans_dist::ReadResp 133548 # Transaction distribution +system.membus.trans_dist::WriteReq 19962 # Transaction distribution +system.membus.trans_dist::WriteResp 19962 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 222420 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 84600 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 307020 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 444840 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 256343 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 701183 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 153510 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 153510 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 153510 # Request fanout histogram + +---------- End Simulation Statistics ---------- diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/config.ini --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/config.ini Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,1265 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 + +[system] +type=System +children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges=0:268435455:0:0:0:0 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.sys_port_proxy.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=TimingSimpleCPU +children=clk_domain dtb interrupts isa itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu.clk_domain +cpu_id=0 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1] +icache_port=system.ruby.l1_cntrl0.sequencer.slave[0] + +[system.cpu.clk_domain] +type=SrcClockDomain +clock=1 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64m/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000 + +[system.mem_ctrls] +type=DRAMCtrl +IDD0=0.055000 +IDD02=0.000000 +IDD2N=0.032000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.032000 +IDD2P12=0.000000 +IDD3N=0.038000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.038000 +IDD3P12=0.000000 +IDD4R=0.157000 +IDD4R2=0.000000 +IDD4W=0.125000 +IDD4W2=0.000000 +IDD5=0.235000 +IDD52=0.000000 +IDD6=0.020000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true 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int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_links0 int_links1 int_links2 int_links3 routers0 routers1 routers2 +adaptive_routing=false +buffer_size=0 +clk_domain=system.ruby.clk_domain +control_msg_size=8 +default_p_state=UNDEFINED +endpoint_bandwidth=1000 +eventq_index=0 +ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 +int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 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+virt_nets=5 + +[system.ruby.network.routers0.port_buffers00] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers01] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers02] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers03] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers04] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers05] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers06] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers07] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers08] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers09] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers10] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers11] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers12] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers13] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers14] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1] +type=Switch +children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 +clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 system.ruby.network.routers1.port_buffers12 system.ruby.network.routers1.port_buffers13 system.ruby.network.routers1.port_buffers14 +power_model=Null +router_id=1 +virt_nets=5 + +[system.ruby.network.routers1.port_buffers00] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers01] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers02] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers03] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers04] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers05] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers06] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers07] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers08] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers09] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers10] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers11] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers12] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers13] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers14] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2] +type=Switch +children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 +clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19 +power_model=Null +router_id=2 +virt_nets=5 + +[system.ruby.network.routers2.port_buffers00] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers01] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers02] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers03] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers04] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers05] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers06] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers07] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers08] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers09] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers10] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers11] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers12] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers13] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers14] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers15] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers16] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers17] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers18] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers19] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.sys_port_proxy] +type=RubyPortProxy +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +is_cpu_sequencer=true +no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_ruby_tester=false +version=0 +slave=system.system_port + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/simerr --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/simerr Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,3 @@ +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/simout --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/simout Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,222 @@ +Redirecting stdout to build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64f/simple-timing/simout +Redirecting stderr to build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64f/simple-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 2 2016 20:34:02 +gem5 started Nov 3 2016 19:02:16 +gem5 executing on ubuntu1604, pid 22156 +command line: /home/ar4jc/gem5/build/RISCV/gem5.debug -d build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64f/simple-timing -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64f/simple-timing + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +clear fsflags: PASS +flw: PASS +fsw: PASS +fmadd.s: PASS +fmadd.s, quiet NaN: PASS +fmadd.s, signaling NaN: PASS +fmadd.s, infinity: PASS +fmadd.s, -infinity: PASS +fmsub.s: PASS +fmsub.s, quiet NaN: PASS +fmsub.s, signaling NaN: PASS +fmsub.s, infinity: PASS +fmsub.s, -infinity: PASS +fmsub.s, subtract infinity: PASS +fnmsub.s: PASS +fnmsub.s, quiet NaN: PASS +fnmsub.s, signaling NaN: PASS +fnmsub.s, infinity: PASS +fnmsub.s, -infinity: PASS +fnmsub.s, subtract infinity: PASS +fnmadd.s: PASS +fnmadd.s, quiet NaN: PASS +fnmadd.s, signaling NaN: PASS +fnmadd.s, infinity: PASS +fnmadd.s, -infinity: PASS +fadd.s: PASS +fadd.s, quiet NaN: PASS +fadd.s, signaling NaN: PASS +fadd.s, infinity: PASS +fadd.s, -infinity: PASS +fsub.s: PASS +fsub.s, quiet NaN: PASS +fsub.s, signaling NaN: PASS +fsub.s, infinity: PASS +fsub.s, -infinity: PASS +fsub.s, subtract infinity: PASS +fmul.s: PASS +fmul.s, quiet NaN: PASS +fmul.s, signaling NaN: PASS +fmul.s, infinity: PASS +fmul.s, -infinity: PASS +fmul.s, 0*infinity: PASS +fmul.s, overflow: PASS +fmul.s, underflow: PASS +fdiv.s: PASS +fdiv.s, quiet NaN: PASS +fdiv.s, signaling NaN: PASS +fdiv.s/0: PASS +fdiv.s/infinity: PASS +fdiv.s, infinity/infinity: PASS +fdiv.s, 0/0: PASS +fdiv.s, infinity/0: PASS +fdiv.s, 0/infinity: PASS +fdiv.s, underflow: PASS +fdiv.s, overflow: PASS +fsqrt.s: PASS +fsqrt.s, NaN: PASS +fsqrt.s, quiet NaN: PASS +fsqrt.s, signaling NaN: PASS +fsqrt.s, infinity: PASS +fsgnj.s, ++: PASS +fsgnj.s, +-: PASS +fsgnj.s, -+: PASS +fsgnj.s, --: PASS +fsgnj.s, quiet NaN: PASS +fsgnj.s, signaling NaN: PASS +fsgnj.s, inject NaN: PASS +fsgnj.s, inject -NaN: PASS +fsgnjn.s, ++: PASS +fsgnjn.s, +-: PASS +fsgnjn.s, -+: PASS +fsgnjn.s, --: PASS +fsgnjn.s, quiet NaN: PASS +fsgnjn.s, signaling NaN: PASS +fsgnjn.s, inject NaN: PASS +fsgnjn.s, inject NaN: PASS +fsgnjx.s, ++: PASS +fsgnjx.s, +-: PASS +fsgnjx.s, -+: PASS +fsgnjx.s, --: PASS +fsgnjx.s, quiet NaN: PASS +fsgnjx.s, signaling NaN: PASS +fsgnjx.s, inject NaN: PASS +fsgnjx.s, inject -NaN: PASS +fmin.s: PASS +fmin.s, -infinity: PASS +fmin.s, infinity: PASS +fmin.s, quiet NaN first: PASS +fmin.s, quiet NaN second: PASS +fmin.s, quiet NaN both: PASS +fmin.s, signaling NaN first: PASS +fmin.s, signaling NaN second: PASS +fmin.s, signaling NaN both: PASS +fmax.s: PASS +fmax.s, -infinity: PASS +fmax.s, infinity: PASS +fmax.s, quiet NaN first: PASS +fmax.s, quiet NaN second: PASS +fmax.s, quiet NaN both: PASS +fmax.s, signaling NaN first: PASS +fmax.s, signaling NaN second: PASS +fmax.s, signaling NaN both: PASS +fcvt.w.s, truncate positive: PASS +fcvt.w.s, truncate negative: PASS +fcvt.w.s, 0.0: PASS +fcvt.w.s, -0.0: PASS +fcvt.w.s, overflow: PASS +fcvt.w.s, underflow: PASS +fcvt.w.s, infinity: PASS +fcvt.w.s, -infinity: PASS +fcvt.w.s, quiet NaN: PASS +fcvt.w.s, quiet -NaN: PASS +fcvt.w.s, signaling NaN: PASS +fcvt.wu.s, truncate positive: PASS +fcvt.wu.s, truncate negative: PASS +fcvt.wu.s, 0.0: PASS +fcvt.wu.s, -0.0: PASS +fcvt.wu.s, overflow: PASS +fcvt.wu.s, underflow: PASS +fcvt.wu.s, infinity: PASS +fcvt.wu.s, -infinity: PASS +fcvt.wu.s, quiet NaN: PASS +fcvt.wu.s, quiet -NaN: PASS +fcvt.wu.s, signaling NaN: PASS +fmv.x.s, positive: PASS +fmv.x.s, negative: PASS +fmv.x.s, 0.0: PASS +fmv.x.s, -0.0: PASS +feq.s, equal: PASS +feq.s, not equal: PASS +feq.s, 0 == -0: PASS +feq.s, quiet NaN first: PASS +feq.s, quiet NaN second: PASS +feq.s, quiet NaN both: PASS +feq.s, signaling NaN first: PASS +feq.s, signaling NaN second: PASS +feq.s, signaling NaN both: PASS +flt.s, equal: PASS +flt.s, less: PASS +flt.s, greater: PASS +flt.s, quiet NaN first: PASS +flt.s, quiet NaN second: PASS +flt.s, quiet NaN both: PASS +flt.s, signaling NaN first: PASS +flt.s, signaling NaN second: PASS +flt.s, signaling NaN both: PASS +fle.s, equal: PASS +fle.s, less: PASS +fle.s, greater: PASS +fle.s, 0 == -0: PASS +fle.s, quiet NaN first: PASS +fle.s, quiet NaN second: PASS +fle.s, quiet NaN both: PASS +fle.s, signaling NaN first: PASS +fle.s, signaling NaN second: PASS +fle.s, signaling NaN both: PASS +fclass.s, -infinity: PASS +fclass.s, -normal: PASS +fclass.s, -subnormal: PASS +fclass.s, -0.0: PASS +fclass.s, 0.0: PASS +fclass.s, subnormal: PASS +fclass.s, normal: PASS +fclass.s, infinity: PASS +fclass.s, signaling NaN: PASS +fclass.s, quiet NaN: PASS +fcvt.s.w, 0: PASS +fcvt.s.w, negative: PASS +fcvt.s.w, truncate: PASS +fcvt.s.wu, 0: PASS +fcvt.s.wu: PASS +fcvt.s.wu, truncate: PASS +fmv.s.x: PASS +fmv.s.x, truncate: PASS +fsrm: PASS +fsflags: PASS +fscsr: PASS +restore initial round mode: PASS +fcvt.l.s, truncate positive: PASS +fcvt.l.s, truncate negative: PASS +fcvt.l.s, 0.0: PASS +fcvt.l.s, -0.0: PASS +fcvt.l.s, 32-bit overflow: PASS +fcvt.l.s, overflow: PASS +fcvt.l.s, underflow: PASS +fcvt.l.s, infinity: PASS +fcvt.l.s, -infinity: PASS +fcvt.l.s, quiet NaN: PASS +fcvt.l.s, quiet -NaN: PASS +fcvt.l.s, signaling NaN: PASS +fcvt.lu.s, truncate positive: PASS +fcvt.lu.s, truncate negative: PASS +fcvt.lu.s, 0.0: PASS +fcvt.lu.s, -0.0: PASS +fcvt.lu.s, 32-bit overflow: PASS +fcvt.lu.s, overflow: PASS +fcvt.lu.s, underflow: PASS +fcvt.lu.s, infinity: PASS +fcvt.lu.s, -infinity: PASS +fcvt.lu.s, quiet NaN: PASS +fcvt.lu.s, quiet -NaN: PASS +fcvt.lu.s, signaling NaN: PASS +fcvt.s.l, 0: PASS +fcvt.s.l, negative: PASS +fcvt.s.l, 32-bit truncate: PASS +fcvt.s.lu, 0: PASS +fcvt.s.lu: PASS +fcvt.s.lu, 32-bit truncate: PASS +Exiting @ tick 617313500 because target called exit() diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/stats.txt --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/stats.txt Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,515 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000617 # Number of seconds simulated +sim_ticks 617313500 # Number of ticks simulated +final_tick 617313500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 40309 # Simulator instruction rate (inst/s) +host_op_rate 40309 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 65732644 # Simulator tick rate (ticks/s) +host_mem_usage 276392 # Number of bytes of host memory used +host_seconds 9.39 # Real time elapsed on the host +sim_insts 378553 # Number of instructions simulated +sim_ops 378553 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 617313500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 68864 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 21248 # Number of bytes read from this memory +system.physmem.bytes_read::total 90112 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 68864 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 68864 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 1076 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 332 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1408 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 111554339 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 34420112 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 145974452 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 111554339 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 111554339 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 111554339 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 34420112 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 145974452 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 617313500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 217 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 617313500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 1234627 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 378553 # Number of instructions committed +system.cpu.committedOps 378553 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 378372 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 1151 # Number of float alu accesses +system.cpu.num_func_calls 27446 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 56202 # number of instructions that are conditional controls +system.cpu.num_int_insts 378372 # number of integer instructions +system.cpu.num_fp_insts 1151 # number of float instructions +system.cpu.num_int_register_reads 498827 # number of times the integer registers were read +system.cpu.num_int_register_writes 259639 # number of times the integer registers were written +system.cpu.num_fp_register_reads 924 # number of times the floating registers were read +system.cpu.num_fp_register_writes 756 # number of times the floating registers were written +system.cpu.num_mem_refs 151246 # number of memory refs +system.cpu.num_load_insts 88835 # Number of load instructions +system.cpu.num_store_insts 62411 # Number of store instructions +system.cpu.num_idle_cycles -0 # Number of idle cycles +system.cpu.num_busy_cycles 1234627 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction -0 # Percentage of idle cycles +system.cpu.Branches 83648 # Number of branches fetched +system.cpu.op_class::No_OpClass 233 0.06% 0.06% # Class of executed instruction +system.cpu.op_class::IntAlu 226224 59.72% 59.78% # Class of executed instruction +system.cpu.op_class::IntMult 624 0.16% 59.95% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 59.95% # Class of executed instruction +system.cpu.op_class::FloatAdd 128 0.03% 59.98% # Class of executed instruction +system.cpu.op_class::FloatCmp 161 0.04% 60.02% # Class of executed instruction +system.cpu.op_class::FloatCvt 109 0.02% 60.05% # Class of executed instruction +system.cpu.op_class::FloatMult 30 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::FloatDiv 11 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::FloatSqrt 5 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::MemRead 88288 23.30% 83.37% # Class of executed instruction +system.cpu.op_class::MemWrite 62251 16.43% 99.81% # Class of executed instruction +system.cpu.op_class::FloatMemRead 547 0.14% 99.95% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 160 0.04% 99.99% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 99.99% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 99.99% # Class of executed instruction +system.cpu.op_class::total 378771 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 617313500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 272.814702 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 150913 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 332 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 454.557228 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 272.814702 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.066605 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.066605 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 332 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 316 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.081054 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 302822 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 302822 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 617313500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 88707 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 88707 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 62206 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 62206 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 150913 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 150913 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 150913 # number of overall hits +system.cpu.dcache.overall_hits::total 150913 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 128 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 128 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 204 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 204 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 332 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 332 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 332 # number of overall misses +system.cpu.dcache.overall_misses::total 332 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8064000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8064000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 12852000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 12852000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 20916000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 20916000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 20916000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 20916000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 88835 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 88835 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 62410 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 62410 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 151245 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 151245 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 151245 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 151245 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001440 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.001440 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003268 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.003268 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002195 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002195 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002195 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002195 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 128 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 128 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 204 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 204 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 332 # number of demand (read+write) MSHR misses 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# Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1076 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 351.018587 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 637.530373 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.311294 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.311294 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1039 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 900 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.507324 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 758620 # Number of tag accesses +system.cpu.icache.tags.data_accesses 758620 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 617313500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 377696 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 377696 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 377696 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 377696 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 377696 # number of overall hits +system.cpu.icache.overall_hits::total 377696 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1076 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1076 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1076 # number of demand (read+write) misses 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0.026278 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 652.358458 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 272.820349 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.019908 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.008325 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.028234 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 1408 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 115 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1253 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.042968 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 12968 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 12968 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 617313500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackClean_hits::writebacks 37 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 37 # number of WritebackClean hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 204 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 204 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1076 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 1076 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 128 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 128 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1076 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 332 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1408 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1076 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 332 # number of overall misses +system.cpu.l2cache.overall_misses::total 1408 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12342000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 12342000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 65099000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 65099000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7744000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 7744000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 65099000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 20086000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 85185000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 65099000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 20086000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 85185000 # number of overall miss cycles +system.cpu.l2cache.WritebackClean_accesses::writebacks 37 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 37 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 204 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 204 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1076 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1076 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 128 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 128 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1076 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 332 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1408 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1076 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 332 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1408 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60500.929368 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60500.929368 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60500.929368 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60500.710227 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60500.929368 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60500.710227 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 204 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 204 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1076 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1076 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 128 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 128 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1076 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 332 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1408 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1076 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 332 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1408 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10302000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10302000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 54339000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 54339000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6464000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6464000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 54339000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16766000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 71105000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 54339000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16766000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 71105000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50500.929368 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50500.929368 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50500.929368 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.710227 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50500.929368 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.710227 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1445 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 37 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 617313500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 1204 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 37 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 204 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 204 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1076 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 128 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2189 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 664 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2853 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 71232 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21248 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 92480 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 1408 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev -0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1408 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1408 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 759500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1614000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 498000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 1408 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 617313500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1204 # Transaction distribution +system.membus.trans_dist::ReadExReq 204 # Transaction distribution +system.membus.trans_dist::ReadExResp 204 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1204 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2816 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2816 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 90112 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 90112 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1408 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev -0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1408 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1408 # Request fanout histogram +system.membus.reqLayer0.occupancy 1409000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 7040000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.1 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/config.ini --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/config.ini Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,896 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=MinorCPU +children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload +branchPred=system.cpu.branchPred +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +decodeCycleInput=true +decodeInputBufferSize=3 +decodeInputWidth=2 +decodeToExecuteForwardDelay=1 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +enableIdling=true +eventq_index=0 +executeAllowEarlyMemoryIssue=true +executeBranchDelay=1 +executeCommitLimit=2 +executeCycleInput=true +executeFuncUnits=system.cpu.executeFuncUnits +executeInputBufferSize=7 +executeInputWidth=2 +executeIssueLimit=2 +executeLSQMaxStoreBufferStoresPerCycle=2 +executeLSQRequestsQueueSize=1 +executeLSQStoreBufferSize=5 +executeLSQTransfersQueueSize=2 +executeMaxAccessesInMemory=2 +executeMemoryCommitLimit=1 +executeMemoryIssueLimit=1 +executeMemoryWidth=0 +executeSetTraceTimeOnCommit=true +executeSetTraceTimeOnIssue=false +fetch1FetchLimit=1 +fetch1LineSnapWidth=0 +fetch1LineWidth=0 +fetch1ToFetch2BackwardDelay=1 +fetch1ToFetch2ForwardDelay=1 +fetch2CycleInput=true +fetch2InputBufferSize=2 +fetch2ToDecodeForwardDelay=1 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +threadPolicy=RoundRobin +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TournamentBP +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +useIndirect=true + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +hit_latency=2 +is_read_only=false +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=262144 + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.executeFuncUnits] +type=MinorFUPool +children=funcUnits0 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+sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=DRAMCtrl +IDD0=0.055000 +IDD02=0.000000 +IDD2N=0.032000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.032000 +IDD2P12=0.000000 +IDD3N=0.038000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.038000 +IDD3P12=0.000000 +IDD4R=0.157000 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+tWR=15000 +tWTR=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/config.json --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/config.json Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,1205 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ 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"system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15", + "type": "MinorOpClass" + }, + { + "opClass": "SimdShift", + "name": "opClasses16", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16", + "type": "MinorOpClass" + }, + { + "opClass": "SimdShiftAcc", + "name": "opClasses17", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17", + "type": "MinorOpClass" + }, + { + "opClass": "SimdSqrt", + "name": "opClasses18", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatAdd", + "name": "opClasses19", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatAlu", + "name": "opClasses20", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatCmp", + "name": "opClasses21", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatCvt", + "name": "opClasses22", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatDiv", + "name": "opClasses23", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatMisc", + "name": "opClasses24", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatMult", + "name": "opClasses25", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatMultAcc", + "name": "opClasses26", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26", + "type": "MinorOpClass" + }, + { + "opClass": "SimdFloatSqrt", + "name": "opClasses27", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27", + "type": "MinorOpClass" + } + ], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits4.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [ + { + "extraAssumedLat": 0, + "description": "FloatSimd", + "srcRegsRelativeLats": [ + 2 + ], + "suppress": false, + "mask": 0, + "extraCommitLat": 0, + "eventq_index": 0, + "opClasses": { + "name": "opClasses", + "opClasses": [], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits4.timings.opClasses", + "type": "MinorOpClassSet" + }, + "cxx_class": "MinorFUTiming", + "path": "system.cpu.executeFuncUnits.funcUnits4.timings", + "extraCommitLatExpr": null, + "type": "MinorFUTiming", + "match": 0, + "name": "timings" + } + ], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits4", + "type": "MinorFU" + }, + { + "issueLat": 1, + "opLat": 1, + "name": "funcUnits5", + "cantForwardFromFUIndices": [], + "opClasses": { + "name": "opClasses", + "opClasses": [ + { + "opClass": "MemRead", + "name": "opClasses0", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0", + "type": "MinorOpClass" + }, + { + "opClass": "MemWrite", + "name": "opClasses1", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1", + "type": "MinorOpClass" + }, + { + "opClass": "FloatMemRead", + "name": "opClasses2", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2", + "type": "MinorOpClass" + }, + { + "opClass": "FloatMemWrite", + "name": "opClasses3", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3", + "type": "MinorOpClass" + } + ], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits5.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [ + { + "extraAssumedLat": 2, + "description": "Mem", + "srcRegsRelativeLats": [ + 1 + ], + "suppress": false, + "mask": 0, + "extraCommitLat": 0, + "eventq_index": 0, + "opClasses": { + "name": "opClasses", + "opClasses": [], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits5.timings.opClasses", + "type": "MinorOpClassSet" + }, + "cxx_class": "MinorFUTiming", + "path": "system.cpu.executeFuncUnits.funcUnits5.timings", + "extraCommitLatExpr": null, + "type": "MinorFUTiming", + "match": 0, + "name": "timings" + } + ], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits5", + "type": "MinorFU" + }, + { + "issueLat": 1, + "opLat": 1, + "name": "funcUnits6", + "cantForwardFromFUIndices": [], + "opClasses": { + "name": "opClasses", + "opClasses": [ + { + "opClass": "IprAccess", + "name": "opClasses0", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0", + "type": "MinorOpClass" + }, + { + "opClass": "InstPrefetch", + "name": "opClasses1", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1", + "type": "MinorOpClass" + } + ], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits6.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits6", + "type": "MinorFU" + } + ], + "type": "MinorFUPool" + }, + "switched_out": false, + "power_model": null, + "max_insts_all_threads": 0, + "executeSetTraceTimeOnIssue": false, + "fetch2InputBufferSize": 2, + "profile": 0, + "fetch2ToDecodeForwardDelay": 1, + "executeInputWidth": 2, + "decodeToExecuteForwardDelay": 1, + "executeLSQRequestsQueueSize": 1, + "fetch2CycleInput": true, + "executeMaxAccessesInMemory": 2, + "enableIdling": true, + "executeLSQStoreBufferSize": 5, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64i/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "executeSetTraceTimeOnCommit": true, + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + }, + "threadPolicy": "RoundRobin", + "executeCommitLimit": 2, + "fetch1LineWidth": 0, + "branchPred": { + "numThreads": 1, + "BTBEntries": 4096, + "cxx_class": "TournamentBP", + "indirectPathLength": 3, + "globalCtrBits": 2, + "choicePredictorSize": 8192, + "indirectHashGHR": true, + "eventq_index": 0, + "localHistoryTableSize": 2048, + "type": "TournamentBP", + "indirectSets": 256, + "indirectWays": 2, + "choiceCtrBits": 2, + "useIndirect": true, + "localCtrBits": 2, + "path": "system.cpu.branchPred", + "localPredictorSize": 2048, + "RASSize": 16, + "globalPredictorSize": 8192, + "name": "branchPred", + "indirectHashTargets": true, + "instShiftAmt": 2, + "indirectTagSize": 16, + "BTBTagSize": 16 + }, + "dcache": { + "cpu_side": { + "peer": "system.cpu.dcache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 262144, + "tags": { + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.dcache.tags", + "hit_latency": 2, + "block_size": 64, + "type": "LRU", + "size": 262144 + }, + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[1]", + "role": "MASTER" + }, + "type": "Cache", + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "hit_latency": 2, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.dcache", + "mshrs": 4, + "name": "dcache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "path": "system.cpu", + "fetch1ToFetch2ForwardDelay": 1, + "decodeInputBufferSize": 3 + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/simerr --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/simerr Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,4 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/simout --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/simout Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,171 @@ +Redirecting stdout to build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64i/minor-timing/simout +Redirecting stderr to build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64i/minor-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 2 2016 20:34:02 +gem5 started Nov 3 2016 18:34:51 +gem5 executing on ubuntu1604, pid 21238 +command line: /home/ar4jc/gem5/build/RISCV/gem5.debug -d build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64i/minor-timing -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64i/minor-timing + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +lui: PASS +lui, negative: PASS +auipc: 0x157CC +auipc: PASS +jal: PASS +jalr: PASS +beq, equal: PASS +beq, not equal: PASS +bne, equal: PASS +bne, not equal: PASS +blt, less: PASS +blt, equal: PASS +blt, greater: PASS +bge, less: PASS +bge, equal: PASS +bge, greater: PASS +bltu, greater: PASS +bltu, equal: PASS +bltu, less: PASS +bgeu, greater: PASS +bgeu, equal: PASS +bgeu, less: PASS +lb, positive: PASS +lb, negative: PASS +lh, positive: PASS +lh, negative: PASS +lw, positive: PASS +lw, negative: PASS +lbu: PASS +lhu: PASS +sb: PASS +sh: PASS +sw: PASS +addi: PASS +addi, overflow: PASS +slti, true: PASS +slti, false: PASS +sltiu, false: PASS +sltiu, true: PASS +xori (1): PASS +xori (0): PASS +ori (1): PASS +ori (A): PASS +andi (0): PASS +andi (1): PASS +slli, general: PASS +slli, erase: PASS +srli, general: PASS +srli, erase: PASS +srli, negative: PASS +srai, general: PASS +srai, erase: PASS +srai, negative: PASS +add: PASS +add, overflow: PASS +sub: PASS +sub, "overflow": PASS +sll, general: PASS +sll, erase: PASS +slt, true: PASS +slt, false: PASS +sltu, false: PASS +sltu, true: PASS +xor (1): PASS +xor (0): PASS +srl, general: PASS +srl, erase: PASS +srl, negative: PASS +sra, general: PASS +sra, erase: PASS +sra, negative: PASS +or (1): PASS +or (A): PASS +and (0): PASS +and (-1): PASS +Bytes written: 15 +open, write: PASS +access F_OK: PASS +access R_OK: PASS +access W_OK: PASS +access X_OK: PASS +stat: + st_dev = 1696642673 + st_ino = 676985 + st_mode = 33188 + st_nlink = 1 + st_uid = 503 + st_gid = 503 + st_rdev = 0 + st_size = 15 + st_blksize = 8192 + st_blocks = 8 +fstat: + st_dev = 1696642673 + st_ino = 676985 + st_mode = 33188 + st_nlink = 1 + st_uid = 503 + st_gid = 503 + st_rdev = 0 + st_size = 15 + st_blksize = 8192 + st_blocks = 8 +open, stat: PASS +Bytes read: 15 +String read: this is a test +open, read, unlink: PASS +times: + tms_utime = 0 + tms_stime = 0 + tms_cutime = 0 + tms_cstime = 0 +times: PASS +timeval: + tv_sec = 1000000000 + tv_usec = 254 +gettimeofday: PASS +Cycles: 518409 +rdcycle: PASS +Time: 1478198103 +rdtime: PASS +Instructions Retired: 213673 +rdinstret: PASS +lwu: PASS +ld: PASS +sd: PASS +addiw: PASS +addiw, overflow: PASS +addiw, truncate: PASS +slliw, general: PASS +slliw, erase: PASS +slliw, truncate: PASS +srliw, general: PASS +srliw, erase: PASS +srliw, negative: PASS +srliw, truncate: PASS +sraiw, general: PASS +sraiw, erase: PASS +sraiw, negative: PASS +sraiw, truncate: PASS +addw: PASS +addw, overflow: PASS +addw, truncate: PASS +subw: PASS +subw, "overflow": PASS +subw, truncate: PASS +sllw, general: PASS +sllw, erase: PASS +sllw, truncate: PASS +srlw, general: PASS +srlw, erase: PASS +srlw, negative: PASS +srlw, truncate: PASS +sraw, general: PASS +sraw, erase: PASS +sraw, negative: PASS +sraw, truncate: PASS +Exiting @ tick 309817500 because target called exit() diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/stats.txt --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/stats.txt Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,761 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000310 # Number of seconds simulated +sim_ticks 309817500 # Number of ticks simulated +final_tick 309817500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 17114 # Simulator instruction rate (inst/s) +host_op_rate 17114 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 20034111 # Simulator tick rate (ticks/s) +host_mem_usage 276592 # Number of bytes of host memory used +host_seconds 15.46 # Real time elapsed on the host +sim_insts 264666 # Number of instructions simulated +sim_ops 264666 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 309817500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 76736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 19072 # Number of bytes read from this memory +system.physmem.bytes_read::total 95808 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 76736 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 76736 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 1199 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 298 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1497 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 247681296 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 61558821 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 309240117 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 247681296 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 247681296 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 247681296 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 61558821 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 309240117 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1497 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 1497 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 95808 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 95808 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 264 # Per bank write bursts +system.physmem.perBankRdBursts::1 145 # Per bank write bursts +system.physmem.perBankRdBursts::2 64 # Per bank write bursts +system.physmem.perBankRdBursts::3 150 # Per bank write bursts +system.physmem.perBankRdBursts::4 79 # Per bank write bursts +system.physmem.perBankRdBursts::5 12 # Per bank write bursts +system.physmem.perBankRdBursts::6 118 # Per bank write bursts +system.physmem.perBankRdBursts::7 73 # Per bank write bursts +system.physmem.perBankRdBursts::8 70 # Per bank write bursts +system.physmem.perBankRdBursts::9 116 # Per bank write bursts +system.physmem.perBankRdBursts::10 80 # Per bank write bursts +system.physmem.perBankRdBursts::11 58 # Per bank write bursts +system.physmem.perBankRdBursts::12 107 # Per bank write bursts +system.physmem.perBankRdBursts::13 48 # Per bank write bursts +system.physmem.perBankRdBursts::14 53 # Per bank write bursts +system.physmem.perBankRdBursts::15 60 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 309453000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 1497 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1433 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 59 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 288 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 324.222222 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 219.722725 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 278.014976 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 72 25.00% 25.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 69 23.96% 48.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 48 16.67% 65.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 26 9.03% 74.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 24 8.33% 82.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 23 7.99% 90.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4 1.39% 92.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 6 2.08% 94.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16 5.56% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 288 # Bytes accessed per row activation +system.physmem.totQLat 20011500 # Total ticks spent queuing +system.physmem.totMemAccLat 48080250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 7485000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13367.74 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 32117.74 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 309.24 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 309.24 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 2.42 # Data bus utilization in percentage +system.physmem.busUtilRead 2.42 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 1200 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.16 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 206715.43 # Average gap between requests +system.physmem.pageHitRate 80.16 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1306620 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 683100 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 6461700 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 23970960.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 16063170 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 528960 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 114421800 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 8558880 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 171995190 # Total energy per rank (pJ) +system.physmem_0.averagePower 555.150016 # Core power per rank (mW) +system.physmem_0.totalIdleTime 271012500 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 246000 # Time in different power states +system.physmem_0.memoryStateTime::REF 10140000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 0 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 22283250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 26206250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 250942000 # Time in different power states +system.physmem_1.actEnergy 813960 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 409860 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4226880 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 15366000.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 10297620 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 3474720 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 51181440 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 15441120 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 31280880 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 132492480 # Total energy per rank (pJ) +system.physmem_1.averagePower 427.646857 # Core power per rank (mW) +system.physmem_1.totalIdleTime 277859750 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 8416250 # Time in different power states +system.physmem_1.memoryStateTime::REF 6512000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 125733750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 40206500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 16701750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 112247250 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 309817500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 72654 # Number of BP lookups +system.cpu.branchPred.condPredicted 46839 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 5661 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 58329 # Number of BTB lookups +system.cpu.branchPred.BTBHits 32286 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 55.351540 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 11725 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 6856 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 4869 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 3049 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 184 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 309817500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 619635 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 264666 # Number of instructions committed +system.cpu.committedOps 264666 # Number of ops (including micro ops) committed +system.cpu.discardedOps 14033 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 2.341196 # CPI: cycles per instruction +system.cpu.ipc 0.427132 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 189 0.07% 0.07% # Class of committed instruction +system.cpu.op_class_0::IntAlu 157588 59.54% 59.61% # Class of committed instruction +system.cpu.op_class_0::IntMult 431 0.16% 59.78% # Class of committed instruction +system.cpu.op_class_0::IntDiv 230 0.09% 59.86% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 0 0.00% 59.86% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 0 0.00% 59.86% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 0 0.00% 59.86% # Class of committed instruction +system.cpu.op_class_0::FloatMult 0 0.00% 59.86% # Class of committed instruction +system.cpu.op_class_0::FloatMultAcc 0 0.00% 59.86% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 0 0.00% 59.86% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 0 0.00% 59.86% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 59.86% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 59.86% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 59.86% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 59.86% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 59.86% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 59.86% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 59.86% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 59.86% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 59.86% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 59.86% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 59.86% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 59.86% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 59.86% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 59.86% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 59.86% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 0 0.00% 59.86% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 59.86% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 0 0.00% 59.86% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 59.86% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 59.86% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 59.86% # Class of committed instruction +system.cpu.op_class_0::MemRead 61526 23.25% 83.11% # Class of committed instruction +system.cpu.op_class_0::MemWrite 44702 16.89% 100.00% # Class of committed instruction +system.cpu.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::total 264666 # Class of committed instruction +system.cpu.tickCycles 387177 # Number of cycles that the object actually ticked +system.cpu.idleCycles 232458 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 309817500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 245.350686 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 108100 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 298 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 362.751678 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 245.350686 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.059900 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.059900 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 298 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 274 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.072754 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 217486 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 217486 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 309817500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 63791 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 63791 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 44309 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 44309 # number of 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accesses +system.cpu.l2cache.demand_miss_rate::total 0.996671 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995847 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.996671 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78859.605911 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78859.605911 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82954.962469 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82954.962469 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 93800 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 93800 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82954.962469 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83622.483221 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 83087.842351 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82954.962469 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83622.483221 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 83087.842351 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 203 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 203 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1199 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1199 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 95 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 95 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1199 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 298 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1497 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1199 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 298 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1497 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13978500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13978500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 87473000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 87473000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7961000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7961000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 87473000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 21939500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 109412500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 87473000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 21939500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 109412500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.995847 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.995847 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995847 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.996671 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995847 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.996671 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68859.605911 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68859.605911 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72954.962469 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72954.962469 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 83800 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 83800 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72954.962469 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73622.483221 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73087.842351 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72954.962469 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73622.483221 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73087.842351 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1542 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 41 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 309817500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 1299 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 40 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 203 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 203 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1204 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 95 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2448 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 596 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3044 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 79616 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 19072 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 98688 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 1502 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000666 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.025803 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1501 99.93% 99.93% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1 0.07% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1502 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 811000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1806000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 447000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 1497 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 309817500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1294 # Transaction distribution +system.membus.trans_dist::ReadExReq 203 # Transaction distribution +system.membus.trans_dist::ReadExResp 203 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1294 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2994 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2994 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 95808 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 95808 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1497 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1497 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1497 # Request fanout histogram +system.membus.reqLayer0.occupancy 1726000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 7944500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 2.6 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64i/o3-timing/config.ini --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/o3-timing/config.ini Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,866 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cachePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +default_p_state=UNDEFINED +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=0 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +system=system +tracer=system.cpu.tracer +trapLatency=13 +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TournamentBP +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +useIndirect=true + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +hit_latency=2 +is_read_only=false +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=262144 + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +eventq_index=0 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +opClass=IntAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +eventq_index=0 +opClass=IntMult +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +eventq_index=0 +opClass=IntDiv +opLat=20 +pipelined=false + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +eventq_index=0 +opClass=FloatAdd +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatCmp +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatCvt +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 opList3 opList4 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +eventq_index=0 +opClass=FloatMult +opLat=4 +pipelined=true + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMultAcc +opLat=5 +pipelined=true + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMisc +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList3.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatDiv +opLat=12 +pipelined=false + +[system.cpu.fuPool.FUList3.opList4] +type=OpDesc +eventq_index=0 +opClass=FloatSqrt +opLat=24 +pipelined=false + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList0 opList1 +count=0 +eventq_index=0 +opList=system.cpu.fuPool.FUList4.opList0 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+addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +hit_latency=2 +is_read_only=true +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tags=system.cpu.icache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=131072 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.l2cache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +hit_latency=20 +is_read_only=false +max_miss_count=0 +mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +hit_latency=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=2097152 + +[system.cpu.toL2Bus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=0 +frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null +response_latency=1 +snoop_filter=system.cpu.toL2Bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64i/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=DRAMCtrl +IDD0=0.055000 +IDD02=0.000000 +IDD2N=0.032000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.032000 +IDD2P12=0.000000 +IDD3N=0.038000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.038000 +IDD3P12=0.000000 +IDD4R=0.157000 +IDD4R2=0.000000 +IDD4W=0.125000 +IDD4W2=0.000000 +IDD5=0.235000 +IDD52=0.000000 +IDD6=0.020000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +page_policy=open_adaptive +power_model=Null +range=0:134217727:0:0:0:0 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCCD_L=0 +tCK=1250 +tCL=13750 +tCS=2500 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64i/o3-timing/config.json --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/o3-timing/config.json Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,1145 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.l2cache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": 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"system.cpu.icache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 131072, + "tags": { + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.icache.tags", + "hit_latency": 2, + "block_size": 64, + "type": "LRU", + "size": 131072 + }, + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[0]", + "role": "MASTER" + }, + "type": "Cache", + "writeback_clean": true, + "p_state_clk_gate_min": 1000, + "hit_latency": 2, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": true, + "prefetch_on_access": false, + "path": "system.cpu.icache", + "mshrs": 4, + "name": "icache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "path": "system.cpu", + "numRobs": 1, + "switched_out": false, + "smtLSQPolicy": "Partitioned", + "fetchBufferSize": 64, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "smtROBThreshold": 100, + "numIQEntries": 64, + "branchPred": { + "numThreads": 1, + "BTBEntries": 4096, + "cxx_class": "TournamentBP", + "indirectPathLength": 3, + "globalCtrBits": 2, + "choicePredictorSize": 8192, + "indirectHashGHR": true, + "eventq_index": 0, + "localHistoryTableSize": 2048, + "type": "TournamentBP", + "indirectSets": 256, + "indirectWays": 2, + "choiceCtrBits": 2, + "useIndirect": true, + "localCtrBits": 2, + "path": "system.cpu.branchPred", + "localPredictorSize": 2048, + "RASSize": 16, + "globalPredictorSize": 8192, + "name": "branchPred", + "indirectHashTargets": true, + "instShiftAmt": 2, + "indirectTagSize": 16, + "BTBTagSize": 16 + }, + "LFSTSize": 1024, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "smtROBPolicy": "Partitioned", + "iewToFetchDelay": 1, + "do_statistics_insts": true, + "dispatchWidth": 8, + "dcache": { + "cpu_side": { + "peer": "system.cpu.dcache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 262144, + "tags": { + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.dcache.tags", + "hit_latency": 2, + "block_size": 64, + "type": "LRU", + "size": 262144 + }, + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[1]", + "role": "MASTER" + }, + "type": "Cache", + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "hit_latency": 2, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.dcache", + "mshrs": 4, + "name": "dcache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "commitToDecodeDelay": 1, + "smtIQPolicy": "Partitioned", + "issueWidth": 8, + "LSQCheckLoads": true, + "commitToRenameDelay": 1, + "cachePorts": 200, + "system": "system", + "checker": null, + "numPhysFloatRegs": 256, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "type": "DerivO3CPU", + "wbWidth": 8, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "smtCommitPolicy": "RoundRobin", + "issueToExecuteDelay": 1, + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "numROBEntries": 192, + "fetchQueueSize": 32, + "iewToCommitDelay": 1, + "smtNumFetchingThreads": 1, + "forwardComSize": 5, + "do_checkpoint_insts": true, + "cxx_class": "DerivO3CPU", + "commitToIEWDelay": 1, + "commitWidth": 8, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "smtFetchPolicy": "SingleThread", + "profile": 0, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "role": "MASTER" + }, + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "role": "MASTER" + }, + "LSQDepCheckShift": 4, + "trapLatency": 13, + "iewToDecodeDelay": 1, + "numPhysCCRegs": 0, + "renameToIEWDelay": 2, + "p_state_clk_gate_bins": 20, + "progress_interval": 0, + "LQEntries": 32 + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/simerr --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/simerr Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,4 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/simout --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/simout Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,222 @@ +Redirecting stdout to build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64f/o3-timing/simout +Redirecting stderr to build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64f/o3-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 2 2016 20:34:02 +gem5 started Nov 3 2016 19:01:39 +gem5 executing on ubuntu1604, pid 22153 +command line: /home/ar4jc/gem5/build/RISCV/gem5.debug -d build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64f/o3-timing -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64f/o3-timing + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +clear fsflags: PASS +flw: PASS +fsw: PASS +fmadd.s: PASS +fmadd.s, quiet NaN: PASS +fmadd.s, signaling NaN: PASS +fmadd.s, infinity: PASS +fmadd.s, -infinity: PASS +fmsub.s: PASS +fmsub.s, quiet NaN: PASS +fmsub.s, signaling NaN: PASS +fmsub.s, infinity: PASS +fmsub.s, -infinity: PASS +fmsub.s, subtract infinity: PASS +fnmsub.s: PASS +fnmsub.s, quiet NaN: PASS +fnmsub.s, signaling NaN: PASS +fnmsub.s, infinity: PASS +fnmsub.s, -infinity: PASS +fnmsub.s, subtract infinity: PASS +fnmadd.s: PASS +fnmadd.s, quiet NaN: PASS +fnmadd.s, signaling NaN: PASS +fnmadd.s, infinity: PASS +fnmadd.s, -infinity: PASS +fadd.s: PASS +fadd.s, quiet NaN: PASS +fadd.s, signaling NaN: PASS +fadd.s, infinity: PASS +fadd.s, -infinity: PASS +fsub.s: PASS +fsub.s, quiet NaN: PASS +fsub.s, signaling NaN: PASS +fsub.s, infinity: PASS +fsub.s, -infinity: PASS +fsub.s, subtract infinity: PASS +fmul.s: PASS +fmul.s, quiet NaN: PASS +fmul.s, signaling NaN: PASS +fmul.s, infinity: PASS +fmul.s, -infinity: PASS +fmul.s, 0*infinity: PASS +fmul.s, overflow: PASS +fmul.s, underflow: PASS +fdiv.s: PASS +fdiv.s, quiet NaN: PASS +fdiv.s, signaling NaN: PASS +fdiv.s/0: PASS +fdiv.s/infinity: PASS +fdiv.s, infinity/infinity: PASS +fdiv.s, 0/0: PASS +fdiv.s, infinity/0: PASS +fdiv.s, 0/infinity: PASS +fdiv.s, underflow: PASS +fdiv.s, overflow: PASS +fsqrt.s: PASS +fsqrt.s, NaN: PASS +fsqrt.s, quiet NaN: PASS +fsqrt.s, signaling NaN: PASS +fsqrt.s, infinity: PASS +fsgnj.s, ++: PASS +fsgnj.s, +-: PASS +fsgnj.s, -+: PASS +fsgnj.s, --: PASS +fsgnj.s, quiet NaN: PASS +fsgnj.s, signaling NaN: PASS +fsgnj.s, inject NaN: PASS +fsgnj.s, inject -NaN: PASS +fsgnjn.s, ++: PASS +fsgnjn.s, +-: PASS +fsgnjn.s, -+: PASS +fsgnjn.s, --: PASS +fsgnjn.s, quiet NaN: PASS +fsgnjn.s, signaling NaN: PASS +fsgnjn.s, inject NaN: PASS +fsgnjn.s, inject NaN: PASS +fsgnjx.s, ++: PASS +fsgnjx.s, +-: PASS +fsgnjx.s, -+: PASS +fsgnjx.s, --: PASS +fsgnjx.s, quiet NaN: PASS +fsgnjx.s, signaling NaN: PASS +fsgnjx.s, inject NaN: PASS +fsgnjx.s, inject -NaN: PASS +fmin.s: PASS +fmin.s, -infinity: PASS +fmin.s, infinity: PASS +fmin.s, quiet NaN first: PASS +fmin.s, quiet NaN second: PASS +fmin.s, quiet NaN both: PASS +fmin.s, signaling NaN first: PASS +fmin.s, signaling NaN second: PASS +fmin.s, signaling NaN both: PASS +fmax.s: PASS +fmax.s, -infinity: PASS +fmax.s, infinity: PASS +fmax.s, quiet NaN first: PASS +fmax.s, quiet NaN second: PASS +fmax.s, quiet NaN both: PASS +fmax.s, signaling NaN first: PASS +fmax.s, signaling NaN second: PASS +fmax.s, signaling NaN both: PASS +fcvt.w.s, truncate positive: PASS +fcvt.w.s, truncate negative: PASS +fcvt.w.s, 0.0: PASS +fcvt.w.s, -0.0: PASS +fcvt.w.s, overflow: PASS +fcvt.w.s, underflow: PASS +fcvt.w.s, infinity: PASS +fcvt.w.s, -infinity: PASS +fcvt.w.s, quiet NaN: PASS +fcvt.w.s, quiet -NaN: PASS +fcvt.w.s, signaling NaN: PASS +fcvt.wu.s, truncate positive: PASS +fcvt.wu.s, truncate negative: PASS +fcvt.wu.s, 0.0: PASS +fcvt.wu.s, -0.0: PASS +fcvt.wu.s, overflow: PASS +fcvt.wu.s, underflow: PASS +fcvt.wu.s, infinity: PASS +fcvt.wu.s, -infinity: PASS +fcvt.wu.s, quiet NaN: PASS +fcvt.wu.s, quiet -NaN: PASS +fcvt.wu.s, signaling NaN: PASS +fmv.x.s, positive: PASS +fmv.x.s, negative: PASS +fmv.x.s, 0.0: PASS +fmv.x.s, -0.0: PASS +feq.s, equal: PASS +feq.s, not equal: PASS +feq.s, 0 == -0: PASS +feq.s, quiet NaN first: PASS +feq.s, quiet NaN second: PASS +feq.s, quiet NaN both: PASS +feq.s, signaling NaN first: PASS +feq.s, signaling NaN second: PASS +feq.s, signaling NaN both: PASS +flt.s, equal: PASS +flt.s, less: PASS +flt.s, greater: PASS +flt.s, quiet NaN first: PASS +flt.s, quiet NaN second: PASS +flt.s, quiet NaN both: PASS +flt.s, signaling NaN first: PASS +flt.s, signaling NaN second: PASS +flt.s, signaling NaN both: PASS +fle.s, equal: PASS +fle.s, less: PASS +fle.s, greater: PASS +fle.s, 0 == -0: PASS +fle.s, quiet NaN first: PASS +fle.s, quiet NaN second: PASS +fle.s, quiet NaN both: PASS +fle.s, signaling NaN first: PASS +fle.s, signaling NaN second: PASS +fle.s, signaling NaN both: PASS +fclass.s, -infinity: PASS +fclass.s, -normal: PASS +fclass.s, -subnormal: PASS +fclass.s, -0.0: PASS +fclass.s, 0.0: PASS +fclass.s, subnormal: PASS +fclass.s, normal: PASS +fclass.s, infinity: PASS +fclass.s, signaling NaN: PASS +fclass.s, quiet NaN: PASS +fcvt.s.w, 0: PASS +fcvt.s.w, negative: PASS +fcvt.s.w, truncate: PASS +fcvt.s.wu, 0: PASS +fcvt.s.wu: PASS +fcvt.s.wu, truncate: PASS +fmv.s.x: PASS +fmv.s.x, truncate: PASS +fsrm: PASS +fsflags: PASS +fscsr: PASS +restore initial round mode: PASS +fcvt.l.s, truncate positive: PASS +fcvt.l.s, truncate negative: PASS +fcvt.l.s, 0.0: PASS +fcvt.l.s, -0.0: PASS +fcvt.l.s, 32-bit overflow: PASS +fcvt.l.s, overflow: PASS +fcvt.l.s, underflow: PASS +fcvt.l.s, infinity: PASS +fcvt.l.s, -infinity: PASS +fcvt.l.s, quiet NaN: PASS +fcvt.l.s, quiet -NaN: PASS +fcvt.l.s, signaling NaN: PASS +fcvt.lu.s, truncate positive: PASS +fcvt.lu.s, truncate negative: PASS +fcvt.lu.s, 0.0: PASS +fcvt.lu.s, -0.0: PASS +fcvt.lu.s, 32-bit overflow: PASS +fcvt.lu.s, overflow: PASS +fcvt.lu.s, underflow: PASS +fcvt.lu.s, infinity: PASS +fcvt.lu.s, -infinity: PASS +fcvt.lu.s, quiet NaN: PASS +fcvt.lu.s, quiet -NaN: PASS +fcvt.lu.s, signaling NaN: PASS +fcvt.s.l, 0: PASS +fcvt.s.l, negative: PASS +fcvt.s.l, 32-bit truncate: PASS +fcvt.s.lu, 0: PASS +fcvt.s.lu: PASS +fcvt.s.lu, 32-bit truncate: PASS +Exiting @ tick 155593000 because target called exit() diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/stats.txt --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/stats.txt Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,1020 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000155 # Number of seconds simulated +sim_ticks 155593000 # Number of ticks simulated +final_tick 155593000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 14861 # Simulator instruction rate (inst/s) +host_op_rate 14861 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6108492 # Simulator tick rate (ticks/s) +host_mem_usage 278180 # Number of bytes of host memory used +host_seconds 25.47 # Real time elapsed on the host +sim_insts 378553 # Number of instructions simulated +sim_ops 378553 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 155593000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 80448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 21504 # Number of bytes read from this memory +system.physmem.bytes_read::total 101952 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 80448 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 80448 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 1257 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 336 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1593 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 517041255 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 138206731 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 655247986 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 517041255 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 517041255 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 517041255 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 138206731 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 655247986 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1593 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 1593 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 101952 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 101952 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 164 # Per bank write bursts +system.physmem.perBankRdBursts::1 120 # Per bank write bursts +system.physmem.perBankRdBursts::2 56 # Per bank write bursts +system.physmem.perBankRdBursts::3 226 # Per bank write bursts +system.physmem.perBankRdBursts::4 232 # Per bank write bursts +system.physmem.perBankRdBursts::5 118 # Per bank write bursts +system.physmem.perBankRdBursts::6 6 # Per bank write bursts +system.physmem.perBankRdBursts::7 38 # Per bank write bursts +system.physmem.perBankRdBursts::8 134 # Per bank write bursts +system.physmem.perBankRdBursts::9 175 # Per bank write bursts +system.physmem.perBankRdBursts::10 85 # Per bank write bursts +system.physmem.perBankRdBursts::11 20 # Per bank write bursts +system.physmem.perBankRdBursts::12 28 # Per bank write bursts +system.physmem.perBankRdBursts::13 66 # Per bank write bursts +system.physmem.perBankRdBursts::14 116 # Per bank write bursts +system.physmem.perBankRdBursts::15 9 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 155404500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 1593 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 993 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 442 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 118 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 40 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 261 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 381.793103 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 249.248423 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 335.353274 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 58 22.22% 22.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 59 22.60% 44.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 44 16.85% 61.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 25 9.57% 71.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 18 6.89% 78.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7 2.68% 80.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 6 2.29% 83.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 6 2.29% 85.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 38 14.55% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 261 # Bytes accessed per row activation +system.physmem.totQLat 20177750 # Total ticks spent queuing +system.physmem.totMemAccLat 50046500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 7965000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12666.50 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 31416.50 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 655.24 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 655.24 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 5.11 # Data bus utilization in percentage +system.physmem.busUtilRead 5.11 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.50 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 1324 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.11 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 97554.61 # Average gap between requests +system.physmem.pageHitRate 83.11 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 985320 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 512325 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 6854400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 11678160 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 13343700 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 263520 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 56317140 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 822720 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 90777285 # Total energy per rank (pJ) +system.physmem_0.averagePower 583.425009 # Core power per rank (mW) +system.physmem_0.totalIdleTime 125406000 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 119500 # Time in different power states +system.physmem_0.memoryStateTime::REF 4940000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 0 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 2140500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 24888750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 123504250 # Time in different power states +system.physmem_1.actEnergy 935340 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 478170 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4519620 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 11678160 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 9130830 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 296160 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 58675800 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 2351520 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 88065600 # Total energy per rank (pJ) +system.physmem_1.averagePower 565.997027 # Core power per rank (mW) +system.physmem_1.totalIdleTime 134638500 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 198500 # Time in different power states +system.physmem_1.memoryStateTime::REF 4940000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 0 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 6122250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 15663750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 128668500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 155593000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 133103 # Number of BP lookups +system.cpu.branchPred.condPredicted 80999 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 8598 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 96701 # Number of BTB lookups +system.cpu.branchPred.BTBHits 61147 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 63.233058 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 25560 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 10801 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 14759 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 4791 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 217 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 155593000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 311187 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.fetch.icacheStallCycles 104087 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 573224 # Number of instructions fetch has processed +system.cpu.fetch.Branches 133103 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 71948 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 137442 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 17682 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 319 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 208 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 87873 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 3788 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 250897 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.284702 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.915260 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 127933 50.99% 50.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 13709 5.46% 56.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22733 9.06% 65.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 12194 4.86% 70.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 9155 3.64% 74.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 16495 6.57% 80.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 9540 3.80% 84.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 11971 4.77% 89.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 27167 10.82% 99.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 99.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 250897 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.427726 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.842056 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 102745 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 26731 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 112358 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1693 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 7370 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 23692 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 1498 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 525266 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 4796 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 7370 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 108148 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 13040 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 5800 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 108497 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 8042 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 497673 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 454 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 204 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1096 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 6407 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 347768 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 643115 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 640131 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 2984 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 259941 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 87827 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 748 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 748 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 6667 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 104662 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 72263 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1920 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 843 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 457061 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 366 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 438312 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 537 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 78859 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 41905 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 119 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 250897 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.746979 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.012222 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 97784 38.97% 38.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 51963 20.71% 59.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 28004 11.16% 70.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 19975 7.96% 78.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 18884 7.52% 86.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 18813 7.49% 93.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 9853 3.92% 97.75% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3271 1.30% 99.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2350 0.93% 99.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 99.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 250897 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 691 6.24% 6.24% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.24% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 6.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 6.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.24% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 6235 56.33% 62.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4035 36.45% 99.03% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 106 0.95% 99.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 1 0.00% 99.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 99.99% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 99.99% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 233 0.05% 0.05% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 266802 60.87% 60.92% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 624 0.14% 61.06% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 214 0.04% 61.11% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 167 0.03% 61.15% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 152 0.03% 61.18% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 33 0.00% 61.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 61.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 12 0.00% 61.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 61.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 6 0.00% 61.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.19% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 100230 22.86% 84.06% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 68654 15.66% 99.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 975 0.22% 99.95% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 210 0.04% 99.99% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 99.99% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 99.99% # Type of FU issued +system.cpu.iq.FU_type_0::total 438312 # Type of FU issued +system.cpu.iq.rate 1.408516 # Inst issue rate +system.cpu.iq.fu_busy_cnt 11068 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.025251 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1135480 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 532358 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 416658 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3646 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 3977 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1354 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 447271 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1876 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 9981 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 15827 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 18 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 35 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 9853 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 84 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 7370 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 10996 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 228 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 457413 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 3992 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 104662 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 72263 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 352 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 63 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 154 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 35 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 2282 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 5795 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8077 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 423435 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 98818 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 14877 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 0 # number of nop insts executed +system.cpu.iew.exec_refs 165478 # number of memory reference insts executed +system.cpu.iew.exec_branches 93981 # Number of branches executed +system.cpu.iew.exec_stores 66660 # Number of stores executed +system.cpu.iew.exec_rate 1.360709 # Inst execution rate +system.cpu.iew.wb_sent 419794 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 418012 # cumulative count of insts written-back +system.cpu.iew.wb_producers 161294 # num instructions producing a value +system.cpu.iew.wb_consumers 229408 # num instructions consuming a value +system.cpu.iew.wb_rate 1.343282 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.703087 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 78877 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 233 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 7127 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 236303 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.601981 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.343615 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 119780 50.68% 50.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 39244 16.60% 67.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 21780 9.21% 76.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 12143 5.13% 81.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 12392 5.24% 86.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7817 3.30% 90.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 5605 2.37% 92.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3299 1.39% 93.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 14243 6.02% 99.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 99.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 236303 # Number of insts commited each cycle +system.cpu.commit.committedInsts 378553 # Number of instructions committed +system.cpu.commit.committedOps 378553 # Number of ops (including micro ops) committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.refs 151245 # Number of memory references committed +system.cpu.commit.loads 88835 # Number of loads committed +system.cpu.commit.membars 0 # Number of memory barriers committed +system.cpu.commit.branches 83648 # Number of branches committed +system.cpu.commit.fp_insts 1151 # Number of committed floating point instructions. +system.cpu.commit.int_insts 378371 # Number of committed integer instructions. +system.cpu.commit.function_calls 27446 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 16 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 226224 59.76% 59.76% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 624 0.16% 59.92% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 59.92% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 128 0.03% 59.96% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 161 0.04% 60.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 109 0.02% 60.03% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 30 0.00% 60.04% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 60.04% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 11 0.00% 60.04% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 60.04% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 5 0.00% 60.04% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 60.04% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 60.04% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 60.04% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 60.04% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 60.04% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 60.04% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 60.04% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 60.04% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 60.04% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 60.04% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 60.04% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 60.04% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 60.04% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 60.04% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 60.04% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 60.04% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 60.04% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 60.04% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 60.04% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 60.04% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 88288 23.32% 83.36% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 62250 16.44% 99.81% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 547 0.14% 99.95% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 160 0.04% 99.99% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 99.99% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 99.99% # Class of committed instruction +system.cpu.commit.op_class_0::total 378553 # Class of committed instruction +system.cpu.commit.bw_lim_events 14243 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 676669 # The number of ROB reads +system.cpu.rob.rob_writes 929631 # The number of ROB writes +system.cpu.timesIdled 497 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 60290 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 378553 # Number of Instructions Simulated +system.cpu.committedOps 378553 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 0.822043 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.822043 # CPI: Total CPI of All Threads +system.cpu.ipc 1.216480 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.216480 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 546542 # number of integer regfile reads +system.cpu.int_regfile_writes 291715 # number of integer regfile writes +system.cpu.fp_regfile_reads 1137 # number of floating regfile reads +system.cpu.fp_regfile_writes 950 # number of floating regfile writes +system.cpu.misc_regfile_reads 684 # number of misc regfile reads +system.cpu.misc_regfile_writes 454 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 155593000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 264.955049 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 148363 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 336 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 441.556547 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 264.955049 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.064686 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.064686 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 336 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 262 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.082031 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 301540 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 301540 # Number of data accesses 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of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2239 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2239 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2239 # number of overall misses +system.cpu.dcache.overall_misses::total 2239 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 61030000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 61030000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 97521428 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 97521428 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 158551428 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 158551428 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 158551428 # number of overall miss cycles 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overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 70813.500669 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 70813.500669 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 70813.500669 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5467 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 152 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 72 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 75.930555 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 152 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 598 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 598 # number of 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in use +system.cpu.icache.tags.total_refs 86167 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1263 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 68.224069 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 699.515379 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.341560 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.341560 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1187 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 508 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 601 # Occupied blocks per task id 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average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 83517.022169 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 155593000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 987.924762 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 78 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1593 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.048964 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 722.947038 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 264.977724 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.022062 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.008086 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.030149 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 1593 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 86 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 569 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 938 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.048614 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 14961 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 14961 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 155593000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackClean_hits::writebacks 76 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 76 # number of WritebackClean hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits +system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits +system.cpu.l2cache.overall_hits::total 2 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 202 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 202 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1257 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 1257 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 134 # number of ReadSharedReq misses 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+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82794.642857 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 82472.065285 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82385.839299 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82794.642857 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 82472.065285 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 202 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 202 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1257 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1257 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 134 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 134 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1257 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 336 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1593 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1257 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 336 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1593 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13813500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13813500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 90989000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 90989000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 10645500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 10645500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 90989000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 24459000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 115448000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 90989000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 24459000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 115448000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.998411 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.998411 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.998411 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.998746 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.998411 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.998746 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68383.663366 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68383.663366 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72385.839299 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72385.839299 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79444.029850 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79444.029850 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72385.839299 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72794.642857 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72472.065285 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72385.839299 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72794.642857 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72472.065285 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1675 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 80 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 155593000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 1397 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 76 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 202 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 202 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1263 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 134 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2598 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 672 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3270 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 85440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21504 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 106944 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 4 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 256 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 1599 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.002501 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.049968 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1595 99.74% 99.74% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4 0.25% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1599 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 913500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1894500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 504000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 1593 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 155593000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1391 # Transaction distribution +system.membus.trans_dist::ReadExReq 202 # Transaction distribution +system.membus.trans_dist::ReadExResp 202 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1391 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3186 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3186 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 101952 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 101952 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1593 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev -0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1593 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1593 # Request fanout histogram +system.membus.reqLayer0.occupancy 1929500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 8395250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 5.3 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/config.ini --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/config.ini Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,211 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=atomic +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=AtomicSimpleCPU +children=dtb interrupts isa itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fastmem=false +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +simulate_data_stalls=false +simulate_inst_stalls=false +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +width=1 +workload=system.cpu.workload +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64f/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +eventq_index=0 +in_addr_map=true +kvm_map=true +latency=30000 +latency_var=0 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +range=0:134217727:0:0:0:0 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/config.json --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/config.json Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,289 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.icache_port", + "system.cpu.dcache_port" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "physmem": { + "range": "0:134217727:0:0:0:0", + "latency": 30000, + "name": "physmem", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "kvm_map": true, + "clk_domain": "system.clk_domain", + "power_model": null, + "latency_var": 0, + "bandwidth": "73.000000", + "conf_table_reported": true, + "cxx_class": "SimpleMemory", + "p_state_clk_gate_max": 1000000000000, + "path": "system.physmem", + "null": false, + "type": "SimpleMemory", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "in_addr_map": true + }, + "power_model": null, + "work_cpus_ckpt_count": 0, + "thermal_components": [], + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "work_end_ckpt_count": 0, + "mem_mode": "atomic", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": [ + { + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.itb", + "type": "RiscvTLB", + "size": 64 + }, + "simulate_data_stalls": false, + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "AtomicSimpleCPU", + "max_loads_all_threads": 0, + "system": "system", + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "cpu_id": 0, + "width": 1, + "checker": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "do_quiesce": true, + "type": "AtomicSimpleCPU", + "fastmem": false, + "profile": 0, + "icache_port": { + "peer": "system.membus.slave[1]", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "p_state_clk_gate_min": 1000, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "dcache_port": { + "peer": "system.membus.slave[2]", + "role": "MASTER" + }, + "socket_id": 0, + "power_model": null, + "max_insts_all_threads": 0, + "path": "system.cpu", + "max_loads_any_thread": 0, + "switched_out": false, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64f/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "simulate_inst_stalls": false, + "progress_interval": 0, + "branchPred": null, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/simerr --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/simerr Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,3 @@ +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/simout --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/simout Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,222 @@ +Redirecting stdout to build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64f/simple-atomic/simout +Redirecting stderr to build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64f/simple-atomic/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 2 2016 20:34:02 +gem5 started Nov 3 2016 19:02:06 +gem5 executing on ubuntu1604, pid 22154 +command line: /home/ar4jc/gem5/build/RISCV/gem5.debug -d build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64f/simple-atomic -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64f/simple-atomic + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +clear fsflags: PASS +flw: PASS +fsw: PASS +fmadd.s: PASS +fmadd.s, quiet NaN: PASS +fmadd.s, signaling NaN: PASS +fmadd.s, infinity: PASS +fmadd.s, -infinity: PASS +fmsub.s: PASS +fmsub.s, quiet NaN: PASS +fmsub.s, signaling NaN: PASS +fmsub.s, infinity: PASS +fmsub.s, -infinity: PASS +fmsub.s, subtract infinity: PASS +fnmsub.s: PASS +fnmsub.s, quiet NaN: PASS +fnmsub.s, signaling NaN: PASS +fnmsub.s, infinity: PASS +fnmsub.s, -infinity: PASS +fnmsub.s, subtract infinity: PASS +fnmadd.s: PASS +fnmadd.s, quiet NaN: PASS +fnmadd.s, signaling NaN: PASS +fnmadd.s, infinity: PASS +fnmadd.s, -infinity: PASS +fadd.s: PASS +fadd.s, quiet NaN: PASS +fadd.s, signaling NaN: PASS +fadd.s, infinity: PASS +fadd.s, -infinity: PASS +fsub.s: PASS +fsub.s, quiet NaN: PASS +fsub.s, signaling NaN: PASS +fsub.s, infinity: PASS +fsub.s, -infinity: PASS +fsub.s, subtract infinity: PASS +fmul.s: PASS +fmul.s, quiet NaN: PASS +fmul.s, signaling NaN: PASS +fmul.s, infinity: PASS +fmul.s, -infinity: PASS +fmul.s, 0*infinity: PASS +fmul.s, overflow: PASS +fmul.s, underflow: PASS +fdiv.s: PASS +fdiv.s, quiet NaN: PASS +fdiv.s, signaling NaN: PASS +fdiv.s/0: PASS +fdiv.s/infinity: PASS +fdiv.s, infinity/infinity: PASS +fdiv.s, 0/0: PASS +fdiv.s, infinity/0: PASS +fdiv.s, 0/infinity: PASS +fdiv.s, underflow: PASS +fdiv.s, overflow: PASS +fsqrt.s: PASS +fsqrt.s, NaN: PASS +fsqrt.s, quiet NaN: PASS +fsqrt.s, signaling NaN: PASS +fsqrt.s, infinity: PASS +fsgnj.s, ++: PASS +fsgnj.s, +-: PASS +fsgnj.s, -+: PASS +fsgnj.s, --: PASS +fsgnj.s, quiet NaN: PASS +fsgnj.s, signaling NaN: PASS +fsgnj.s, inject NaN: PASS +fsgnj.s, inject -NaN: PASS +fsgnjn.s, ++: PASS +fsgnjn.s, +-: PASS +fsgnjn.s, -+: PASS +fsgnjn.s, --: PASS +fsgnjn.s, quiet NaN: PASS +fsgnjn.s, signaling NaN: PASS +fsgnjn.s, inject NaN: PASS +fsgnjn.s, inject NaN: PASS +fsgnjx.s, ++: PASS +fsgnjx.s, +-: PASS +fsgnjx.s, -+: PASS +fsgnjx.s, --: PASS +fsgnjx.s, quiet NaN: PASS +fsgnjx.s, signaling NaN: PASS +fsgnjx.s, inject NaN: PASS +fsgnjx.s, inject -NaN: PASS +fmin.s: PASS +fmin.s, -infinity: PASS +fmin.s, infinity: PASS +fmin.s, quiet NaN first: PASS +fmin.s, quiet NaN second: PASS +fmin.s, quiet NaN both: PASS +fmin.s, signaling NaN first: PASS +fmin.s, signaling NaN second: PASS +fmin.s, signaling NaN both: PASS +fmax.s: PASS +fmax.s, -infinity: PASS +fmax.s, infinity: PASS +fmax.s, quiet NaN first: PASS +fmax.s, quiet NaN second: PASS +fmax.s, quiet NaN both: PASS +fmax.s, signaling NaN first: PASS +fmax.s, signaling NaN second: PASS +fmax.s, signaling NaN both: PASS +fcvt.w.s, truncate positive: PASS +fcvt.w.s, truncate negative: PASS +fcvt.w.s, 0.0: PASS +fcvt.w.s, -0.0: PASS +fcvt.w.s, overflow: PASS +fcvt.w.s, underflow: PASS +fcvt.w.s, infinity: PASS +fcvt.w.s, -infinity: PASS +fcvt.w.s, quiet NaN: PASS +fcvt.w.s, quiet -NaN: PASS +fcvt.w.s, signaling NaN: PASS +fcvt.wu.s, truncate positive: PASS +fcvt.wu.s, truncate negative: PASS +fcvt.wu.s, 0.0: PASS +fcvt.wu.s, -0.0: PASS +fcvt.wu.s, overflow: PASS +fcvt.wu.s, underflow: PASS +fcvt.wu.s, infinity: PASS +fcvt.wu.s, -infinity: PASS +fcvt.wu.s, quiet NaN: PASS +fcvt.wu.s, quiet -NaN: PASS +fcvt.wu.s, signaling NaN: PASS +fmv.x.s, positive: PASS +fmv.x.s, negative: PASS +fmv.x.s, 0.0: PASS +fmv.x.s, -0.0: PASS +feq.s, equal: PASS +feq.s, not equal: PASS +feq.s, 0 == -0: PASS +feq.s, quiet NaN first: PASS +feq.s, quiet NaN second: PASS +feq.s, quiet NaN both: PASS +feq.s, signaling NaN first: PASS +feq.s, signaling NaN second: PASS +feq.s, signaling NaN both: PASS +flt.s, equal: PASS +flt.s, less: PASS +flt.s, greater: PASS +flt.s, quiet NaN first: PASS +flt.s, quiet NaN second: PASS +flt.s, quiet NaN both: PASS +flt.s, signaling NaN first: PASS +flt.s, signaling NaN second: PASS +flt.s, signaling NaN both: PASS +fle.s, equal: PASS +fle.s, less: PASS +fle.s, greater: PASS +fle.s, 0 == -0: PASS +fle.s, quiet NaN first: PASS +fle.s, quiet NaN second: PASS +fle.s, quiet NaN both: PASS +fle.s, signaling NaN first: PASS +fle.s, signaling NaN second: PASS +fle.s, signaling NaN both: PASS +fclass.s, -infinity: PASS +fclass.s, -normal: PASS +fclass.s, -subnormal: PASS +fclass.s, -0.0: PASS +fclass.s, 0.0: PASS +fclass.s, subnormal: PASS +fclass.s, normal: PASS +fclass.s, infinity: PASS +fclass.s, signaling NaN: PASS +fclass.s, quiet NaN: PASS +fcvt.s.w, 0: PASS +fcvt.s.w, negative: PASS +fcvt.s.w, truncate: PASS +fcvt.s.wu, 0: PASS +fcvt.s.wu: PASS +fcvt.s.wu, truncate: PASS +fmv.s.x: PASS +fmv.s.x, truncate: PASS +fsrm: PASS +fsflags: PASS +fscsr: PASS +restore initial round mode: PASS +fcvt.l.s, truncate positive: PASS +fcvt.l.s, truncate negative: PASS +fcvt.l.s, 0.0: PASS +fcvt.l.s, -0.0: PASS +fcvt.l.s, 32-bit overflow: PASS +fcvt.l.s, overflow: PASS +fcvt.l.s, underflow: PASS +fcvt.l.s, infinity: PASS +fcvt.l.s, -infinity: PASS +fcvt.l.s, quiet NaN: PASS +fcvt.l.s, quiet -NaN: PASS +fcvt.l.s, signaling NaN: PASS +fcvt.lu.s, truncate positive: PASS +fcvt.lu.s, truncate negative: PASS +fcvt.lu.s, 0.0: PASS +fcvt.lu.s, -0.0: PASS +fcvt.lu.s, 32-bit overflow: PASS +fcvt.lu.s, overflow: PASS +fcvt.lu.s, underflow: PASS +fcvt.lu.s, infinity: PASS +fcvt.lu.s, -infinity: PASS +fcvt.lu.s, quiet NaN: PASS +fcvt.lu.s, quiet -NaN: PASS +fcvt.lu.s, signaling NaN: PASS +fcvt.s.l, 0: PASS +fcvt.s.l, negative: PASS +fcvt.s.l, 32-bit truncate: PASS +fcvt.s.lu, 0: PASS +fcvt.s.lu: PASS +fcvt.s.lu, 32-bit truncate: PASS +Exiting @ tick 189385000 because target called exit() diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/stats.txt --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-atomic/stats.txt Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,153 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000189 # Number of seconds simulated +sim_ticks 189385000 # Number of ticks simulated +final_tick 189385000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 41907 # Simulator instruction rate (inst/s) +host_op_rate 41906 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 20965439 # Simulator tick rate (ticks/s) +host_mem_usage 265112 # Number of bytes of host memory used +host_seconds 9.03 # Real time elapsed on the host +sim_insts 378553 # Number of instructions simulated +sim_ops 378553 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 189385000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 1515084 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 580670 # Number of bytes read from this memory +system.physmem.bytes_read::total 2095754 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1515084 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1515084 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 394340 # Number of bytes written to this memory +system.physmem.bytes_written::total 394340 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 378771 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 88835 # Number of read requests responded to by this memory +system.physmem.num_reads::total 467606 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 62410 # Number of write requests responded to by this memory +system.physmem.num_writes::total 62410 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 8000021120 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3066082319 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 11066103440 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8000021120 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8000021120 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 2082213480 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2082213480 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8000021120 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5148295799 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13148316920 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 189385000 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 217 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 189385000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 378771 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 378553 # Number of instructions committed +system.cpu.committedOps 378553 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 378372 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 1151 # Number of float alu accesses +system.cpu.num_func_calls 27446 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 56202 # number of instructions that are conditional controls +system.cpu.num_int_insts 378372 # number of integer instructions +system.cpu.num_fp_insts 1151 # number of float instructions +system.cpu.num_int_register_reads 498827 # number of times the integer registers were read +system.cpu.num_int_register_writes 259639 # number of times the integer registers were written +system.cpu.num_fp_register_reads 924 # number of times the floating registers were read +system.cpu.num_fp_register_writes 756 # number of times the floating registers were written +system.cpu.num_mem_refs 151246 # number of memory refs +system.cpu.num_load_insts 88835 # Number of load instructions +system.cpu.num_store_insts 62411 # Number of store instructions +system.cpu.num_idle_cycles -0 # Number of idle cycles +system.cpu.num_busy_cycles 378771 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction -0 # Percentage of idle cycles +system.cpu.Branches 83648 # Number of branches fetched +system.cpu.op_class::No_OpClass 233 0.06% 0.06% # Class of executed instruction +system.cpu.op_class::IntAlu 226224 59.72% 59.78% # Class of executed instruction +system.cpu.op_class::IntMult 624 0.16% 59.95% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 59.95% # Class of executed instruction +system.cpu.op_class::FloatAdd 128 0.03% 59.98% # Class of executed instruction +system.cpu.op_class::FloatCmp 161 0.04% 60.02% # Class of executed instruction +system.cpu.op_class::FloatCvt 109 0.02% 60.05% # Class of executed instruction +system.cpu.op_class::FloatMult 30 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::FloatDiv 11 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::FloatSqrt 5 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::MemRead 88288 23.30% 83.37% # Class of executed instruction +system.cpu.op_class::MemWrite 62251 16.43% 99.81% # Class of executed instruction +system.cpu.op_class::FloatMemRead 547 0.14% 99.95% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 160 0.04% 99.99% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 99.99% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 99.99% # Class of executed instruction +system.cpu.op_class::total 378771 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 189385000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 467606 # Transaction distribution +system.membus.trans_dist::ReadResp 467606 # Transaction distribution +system.membus.trans_dist::WriteReq 62410 # Transaction distribution +system.membus.trans_dist::WriteResp 62410 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 757542 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 302490 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1060032 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1515084 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 975010 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 2490094 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 530016 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev -0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 530016 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 530016 # Request fanout histogram + +---------- End Simulation Statistics ---------- diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/config.ini --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/config.ini Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,1265 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 + +[system] +type=System +children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges=0:268435455:0:0:0:0 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.sys_port_proxy.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=TimingSimpleCPU +children=clk_domain dtb interrupts isa itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu.clk_domain +cpu_id=0 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1] +icache_port=system.ruby.l1_cntrl0.sequencer.slave[0] + +[system.cpu.clk_domain] +type=SrcClockDomain +clock=1 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64f/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000 + +[system.mem_ctrls] +type=DRAMCtrl +IDD0=0.055000 +IDD02=0.000000 +IDD2N=0.032000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.032000 +IDD2P12=0.000000 +IDD3N=0.038000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.038000 +IDD3P12=0.000000 +IDD4R=0.157000 +IDD4R2=0.000000 +IDD4W=0.125000 +IDD4W2=0.000000 +IDD5=0.235000 +IDD52=0.000000 +IDD6=0.020000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +page_policy=open_adaptive +power_model=Null +range=0:268435455:5:19:0:0 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10 +static_frontend_latency=10 +tBURST=5 +tCCD_L=0 +tCK=1 +tCL=14 +tCS=3 +tRAS=35 +tRCD=14 +tREFI=7800 +tRFC=260 +tRP=14 +tRRD=6 +tRRD_L=0 +tRTP=8 +tRTW=3 +tWR=15 +tWTR=8 +tXAW=30 +tXP=6 +tXPDLL=0 +tXS=270 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.ruby.dir_cntrl0.memory + +[system.ruby] +type=RubySystem +children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network +access_backing_store=false +all_instructions=false +block_size_bytes=64 +clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +hot_lines=false +memory_size_bits=48 +num_of_sequencers=1 +number_of_virtual_networks=5 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +phys_mem=Null +power_model=Null +randomization=false + +[system.ruby.clk_domain] +type=SrcClockDomain +clock=1 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.ruby.dir_cntrl0] +type=Directory_Controller +children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir requestToDir responseFromDir responseFromMemory +buffer_size=0 +clk_domain=system.ruby.clk_domain +cluster_id=0 +default_p_state=UNDEFINED +directory=system.ruby.dir_cntrl0.directory +directory_latency=12 +dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir +dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir +eventq_index=0 +forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir +number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +recycle_latency=10 +requestToDir=system.ruby.dir_cntrl0.requestToDir +responseFromDir=system.ruby.dir_cntrl0.responseFromDir +responseFromMemory=system.ruby.dir_cntrl0.responseFromMemory +ruby_system=system.ruby +system=system +to_memory_controller_latency=1 +transitions_per_cycle=4 +version=0 +memory=system.mem_ctrls.port + +[system.ruby.dir_cntrl0.directory] +type=RubyDirectoryMemory +eventq_index=0 +numa_high_bit=5 +size=268435456 +version=0 + +[system.ruby.dir_cntrl0.dmaRequestToDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[3] + +[system.ruby.dir_cntrl0.dmaResponseFromDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[3] + +[system.ruby.dir_cntrl0.forwardFromDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[4] + +[system.ruby.dir_cntrl0.requestToDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[2] + +[system.ruby.dir_cntrl0.responseFromDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[2] + +[system.ruby.dir_cntrl0.responseFromMemory] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false + +[system.ruby.l1_cntrl0] +type=L1Cache_Controller +children=cacheMemory forwardToCache mandatoryQueue requestFromCache responseFromCache responseToCache sequencer +buffer_size=0 +cacheMemory=system.ruby.l1_cntrl0.cacheMemory +cache_response_latency=12 +clk_domain=system.cpu.clk_domain +cluster_id=0 +default_p_state=UNDEFINED +eventq_index=0 +forwardToCache=system.ruby.l1_cntrl0.forwardToCache +issue_latency=2 +mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue +number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +recycle_latency=10 +requestFromCache=system.ruby.l1_cntrl0.requestFromCache +responseFromCache=system.ruby.l1_cntrl0.responseFromCache +responseToCache=system.ruby.l1_cntrl0.responseToCache +ruby_system=system.ruby +send_evictions=false +sequencer=system.ruby.l1_cntrl0.sequencer +system=system +transitions_per_cycle=4 +version=0 + +[system.ruby.l1_cntrl0.cacheMemory] +type=RubyCache +children=replacement_policy +assoc=2 +block_size=0 +dataAccessLatency=1 +dataArrayBanks=1 +eventq_index=0 +is_icache=false +replacement_policy=system.ruby.l1_cntrl0.cacheMemory.replacement_policy +resourceStalls=false +ruby_system=system.ruby +size=256 +start_index_bit=6 +tagAccessLatency=1 +tagArrayBanks=1 + +[system.ruby.l1_cntrl0.cacheMemory.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=2 +block_size=64 +eventq_index=0 +size=256 + +[system.ruby.l1_cntrl0.forwardToCache] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[0] + +[system.ruby.l1_cntrl0.mandatoryQueue] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false + +[system.ruby.l1_cntrl0.requestFromCache] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[0] + +[system.ruby.l1_cntrl0.responseFromCache] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[1] + +[system.ruby.l1_cntrl0.responseToCache] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[1] + +[system.ruby.l1_cntrl0.sequencer] +type=RubySequencer +clk_domain=system.cpu.clk_domain +coreid=99 +dcache=system.ruby.l1_cntrl0.cacheMemory +dcache_hit_latency=1 +deadlock_threshold=500000 +default_p_state=UNDEFINED +eventq_index=0 +garnet_standalone=false +icache=system.ruby.l1_cntrl0.cacheMemory +icache_hit_latency=1 +is_cpu_sequencer=true +max_outstanding_requests=16 +no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_ruby_tester=false +version=0 +slave=system.cpu.icache_port system.cpu.dcache_port + +[system.ruby.memctrl_clk_domain] +type=DerivedClockDomain +clk_divider=3 +clk_domain=system.ruby.clk_domain +eventq_index=0 + +[system.ruby.network] +type=SimpleNetwork +children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_links0 int_links1 int_links2 int_links3 routers0 routers1 routers2 +adaptive_routing=false +buffer_size=0 +clk_domain=system.ruby.clk_domain +control_msg_size=8 +default_p_state=UNDEFINED +endpoint_bandwidth=1000 +eventq_index=0 +ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 +int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 +int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 +netifs= +number_of_virtual_networks=5 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 +ruby_system=system.ruby +topology=Crossbar +master=system.ruby.l1_cntrl0.forwardToCache.slave system.ruby.l1_cntrl0.responseToCache.slave system.ruby.dir_cntrl0.requestToDir.slave system.ruby.dir_cntrl0.dmaRequestToDir.slave +slave=system.ruby.l1_cntrl0.requestFromCache.master system.ruby.l1_cntrl0.responseFromCache.master system.ruby.dir_cntrl0.responseFromDir.master system.ruby.dir_cntrl0.dmaResponseFromDir.master system.ruby.dir_cntrl0.forwardFromDir.master + +[system.ruby.network.ext_links0] +type=SimpleExtLink +bandwidth_factor=16 +eventq_index=0 +ext_node=system.ruby.l1_cntrl0 +int_node=system.ruby.network.routers0 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+[system.ruby.network.int_links2] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers0 +eventq_index=0 +latency=1 +link_id=4 +src_node=system.ruby.network.routers2 +src_outport= +weight=1 + +[system.ruby.network.int_links3] +type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers1 +eventq_index=0 +latency=1 +link_id=5 +src_node=system.ruby.network.routers2 +src_outport= +weight=1 + +[system.ruby.network.routers0] +type=Switch +children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 +clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +port_buffers=system.ruby.network.routers0.port_buffers00 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+ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers19] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.sys_port_proxy] +type=RubyPortProxy +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +is_cpu_sequencer=true +no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_ruby_tester=false +version=0 +slave=system.system_port + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/config.json --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/config.json Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,1734 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1, + "memories": [ + "system.mem_ctrls" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [ + "0:268435455:0:0:0:0" + ], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + 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"name": "port_buffers02", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers02", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers03", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers03", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers04", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers04", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers05", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers05", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers06", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers06", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers07", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers07", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers08", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers08", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers09", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers09", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers10", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers10", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers11", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers11", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers12", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers12", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers13", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers13", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers14", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers1.port_buffers14", + "type": "MessageBuffer" + } + ] + }, + { + "router_id": 2, + "latency": 1, + "name": "routers2", + "p_state_clk_gate_min": 1, + "virt_nets": 5, + "p_state_clk_gate_bins": 20, + "cxx_class": "Switch", + "clk_domain": "system.ruby.clk_domain", + "power_model": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "path": "system.ruby.network.routers2", + "type": "Switch", + "port_buffers": [ + { + "ordered": true, + "name": "port_buffers00", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers00", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers01", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers01", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers02", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers02", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers03", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers03", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers04", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers04", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers05", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers05", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers06", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers06", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers07", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers07", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers08", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers08", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers09", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers09", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers10", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers10", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers11", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers11", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers12", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers12", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers13", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers13", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers14", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers14", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers15", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers15", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers16", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers16", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers17", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers17", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers18", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers18", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers19", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers19", + "type": "MessageBuffer" + } + ] + } + ], + "power_model": null, + "netifs": [], + "control_msg_size": 8, + "buffer_size": 0, + "endpoint_bandwidth": 1000, + "ruby_system": "system.ruby", + "name": "network", + "p_state_clk_gate_bins": 20, + "ext_links": [ + { + "latency": 1, + "name": "ext_links0", + "weight": 1, + "ext_node": "system.ruby.l1_cntrl0", + "link_id": 0, + "eventq_index": 0, + "cxx_class": "SimpleExtLink", + "path": "system.ruby.network.ext_links0", + "int_node": "system.ruby.network.routers0", + "type": "SimpleExtLink", + "bandwidth_factor": 16 + }, + { + "latency": 1, + "name": "ext_links1", + "weight": 1, + "ext_node": "system.ruby.dir_cntrl0", + "link_id": 1, + "eventq_index": 0, + "cxx_class": "SimpleExtLink", + "path": "system.ruby.network.ext_links1", + "int_node": "system.ruby.network.routers1", + "type": "SimpleExtLink", + "bandwidth_factor": 16 + } + ], + "number_of_virtual_networks": 5, + "path": "system.ruby.network" + }, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.ruby.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "randomization": false, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "phys_mem": null, + "type": "RubySystem", + "p_state_clk_gate_min": 1, + "hot_lines": false, + "power_model": null, + "path": "system.ruby", + "memctrl_clk_domain": { + "name": "memctrl_clk_domain", + "clk_domain": "system.ruby.clk_domain", + "eventq_index": 0, + "cxx_class": "DerivedClockDomain", + "path": "system.ruby.memctrl_clk_domain", + "type": "DerivedClockDomain", + "clk_divider": 3 + }, + "name": "ruby", + "p_state_clk_gate_bins": 20, + "block_size_bytes": 64, + "access_backing_store": false, + "number_of_virtual_networks": 5, + "num_of_sequencers": 1, + "dir_cntrl0": { + "system": "system", + "cluster_id": 0, + "responseFromMemory": { + "ordered": false, + "name": "responseFromMemory", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.responseFromMemory", + "type": "MessageBuffer" + }, + "cxx_class": "Directory_Controller", + "forwardFromDir": { + "ordered": false, + "name": "forwardFromDir", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "master": { + "peer": "system.ruby.network.slave[4]", + "role": "MASTER" + }, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.forwardFromDir", + "type": "MessageBuffer" + }, + "dmaRequestToDir": { + "ordered": true, + "name": "dmaRequestToDir", + "cxx_class": "MessageBuffer", + "slave": { + "peer": "system.ruby.network.master[3]", + "role": "SLAVE" + }, + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.dmaRequestToDir", + "type": "MessageBuffer" + }, + "type": "Directory_Controller", + "recycle_latency": 10, + "clk_domain": "system.ruby.clk_domain", + "version": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "directory_latency": 12, + "number_of_TBEs": 256, + "to_memory_controller_latency": 1, + "p_state_clk_gate_min": 1, + "responseFromDir": { + "ordered": false, + "name": "responseFromDir", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "master": { + "peer": "system.ruby.network.slave[2]", + "role": "MASTER" + }, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.responseFromDir", + "type": "MessageBuffer" + }, + "transitions_per_cycle": 4, + "memory": { + "peer": "system.mem_ctrls.port", + "role": "MASTER" + }, + "power_model": null, + "buffer_size": 0, + "ruby_system": "system.ruby", + "requestToDir": { + "ordered": true, + "name": "requestToDir", + "cxx_class": "MessageBuffer", + "slave": { + "peer": "system.ruby.network.master[2]", + "role": "SLAVE" + }, + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.requestToDir", + "type": "MessageBuffer" + }, + "dmaResponseFromDir": { + "ordered": true, + "name": "dmaResponseFromDir", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "master": { + "peer": "system.ruby.network.slave[3]", + "role": "MASTER" + }, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.dmaResponseFromDir", + "type": "MessageBuffer" + }, + "name": "dir_cntrl0", + "p_state_clk_gate_bins": 20, + "directory": { + "name": "directory", + "version": 0, + "eventq_index": 0, + "cxx_class": "DirectoryMemory", + "path": "system.ruby.dir_cntrl0.directory", + "type": "RubyDirectoryMemory", + "numa_high_bit": 5, + "size": 268435456 + }, + "path": "system.ruby.dir_cntrl0" + } + }, + "work_end_ckpt_count": 0, + "mem_mode": "timing", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": { + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.itb", + "type": "RiscvTLB", + "size": 64 + }, + "system": "system", + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "TimingSimpleCPU", + "max_loads_all_threads": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "function_trace_start": 0, + "cpu_id": 0, + "checker": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "do_quiesce": true, + "type": "TimingSimpleCPU", + "profile": 0, + "icache_port": { + "peer": "system.ruby.l1_cntrl0.sequencer.slave[0]", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "p_state_clk_gate_min": 1, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "dcache_port": { + "peer": "system.ruby.l1_cntrl0.sequencer.slave[1]", + "role": "MASTER" + }, + "socket_id": 0, + "power_model": null, + "max_insts_all_threads": 0, + "path": "system.cpu", + "max_loads_any_thread": 0, + "switched_out": false, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64f/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "progress_interval": 0, + "branchPred": null, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + }, + "multi_thread": false, + "mem_ctrls": [ + { + "static_frontend_latency": 10, + "tRFC": 260, + "activation_limit": 4, + "in_addr_map": true, + "IDD3N2": "0.0", + "tWTR": 8, + "IDD52": "0.0", + "clk_domain": "system.clk_domain", + "channels": 1, + "write_buffer_size": 64, + "device_bus_width": 8, + "VDD": "1.5", + "write_high_thresh_perc": 85, + "cxx_class": "DRAMCtrl", + "bank_groups_per_rank": 0, + "IDD2N2": "0.0", + "port": { + "peer": "system.ruby.dir_cntrl0.memory", + "role": "SLAVE" + }, + "tCCD_L": 0, + "IDD2N": "0.032", + "p_state_clk_gate_min": 1, + "null": false, + "IDD2P1": "0.032", + "eventq_index": 0, + "tRRD": 6, + "tRTW": 3, + "IDD4R": "0.157", + "burst_length": 8, + "tRTP": 8, + "IDD4W": "0.125", + "tWR": 15, + "banks_per_rank": 8, + "devices_per_rank": 8, + "IDD2P02": "0.0", + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "IDD6": "0.02", + "IDD5": "0.235", + "tRCD": 14, + "type": "DRAMCtrl", + "IDD3P02": "0.0", + "tRRD_L": 0, + "IDD0": "0.055", + "IDD62": "0.0", + "min_writes_per_switch": 16, + "mem_sched_policy": "frfcfs", + "IDD02": "0.0", + "IDD2P0": "0.0", + "ranks_per_channel": 2, + "page_policy": "open_adaptive", + "IDD4W2": "0.0", + "tCS": 3, + "power_model": null, + "tCL": 14, + "read_buffer_size": 32, + "conf_table_reported": true, + "tCK": 1, + "tRAS": 35, + "tRP": 14, + "tBURST": 5, + "path": "system.mem_ctrls", + "tXP": 6, + "tXS": 270, + "addr_mapping": "RoRaBaCoCh", + "IDD3P0": "0.0", + "IDD3P1": "0.038", + "IDD3N": "0.038", + "name": "mem_ctrls", + "tXSDLL": 0, + "device_size": 536870912, + "kvm_map": true, + "dll": true, + "tXAW": 30, + "write_low_thresh_perc": 50, + "range": "0:268435455:5:19:0:0", + "VDD2": "0.0", + "IDD2P12": "0.0", + "p_state_clk_gate_bins": 20, + "tXPDLL": 0, + "IDD4R2": "0.0", + "device_rowbuffer_size": 1024, + "static_backend_latency": 10, + "max_accesses_per_row": 16, + "IDD3P12": "0.0", + "tREFI": 7800 + } + ], + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/simerr --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/simerr Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,11 @@ +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick +warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/simout --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/simout Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,222 @@ +Redirecting stdout to build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64f/simple-timing-ruby/simout +Redirecting stderr to build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64f/simple-timing-ruby/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 2 2016 20:34:02 +gem5 started Nov 3 2016 19:02:26 +gem5 executing on ubuntu1604, pid 22158 +command line: /home/ar4jc/gem5/build/RISCV/gem5.debug -d build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64f/simple-timing-ruby -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64f/simple-timing-ruby + +Global frequency set at 1000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +clear fsflags: PASS +flw: PASS +fsw: PASS +fmadd.s: PASS +fmadd.s, quiet NaN: PASS +fmadd.s, signaling NaN: PASS +fmadd.s, infinity: PASS +fmadd.s, -infinity: PASS +fmsub.s: PASS +fmsub.s, quiet NaN: PASS +fmsub.s, signaling NaN: PASS +fmsub.s, infinity: PASS +fmsub.s, -infinity: PASS +fmsub.s, subtract infinity: PASS +fnmsub.s: PASS +fnmsub.s, quiet NaN: PASS +fnmsub.s, signaling NaN: PASS +fnmsub.s, infinity: PASS +fnmsub.s, -infinity: PASS +fnmsub.s, subtract infinity: PASS +fnmadd.s: PASS +fnmadd.s, quiet NaN: PASS +fnmadd.s, signaling NaN: PASS +fnmadd.s, infinity: PASS +fnmadd.s, -infinity: PASS +fadd.s: PASS +fadd.s, quiet NaN: PASS +fadd.s, signaling NaN: PASS +fadd.s, infinity: PASS +fadd.s, -infinity: PASS +fsub.s: PASS +fsub.s, quiet NaN: PASS +fsub.s, signaling NaN: PASS +fsub.s, infinity: PASS +fsub.s, -infinity: PASS +fsub.s, subtract infinity: PASS +fmul.s: PASS +fmul.s, quiet NaN: PASS +fmul.s, signaling NaN: PASS +fmul.s, infinity: PASS +fmul.s, -infinity: PASS +fmul.s, 0*infinity: PASS +fmul.s, overflow: PASS +fmul.s, underflow: PASS +fdiv.s: PASS +fdiv.s, quiet NaN: PASS +fdiv.s, signaling NaN: PASS +fdiv.s/0: PASS +fdiv.s/infinity: PASS +fdiv.s, infinity/infinity: PASS +fdiv.s, 0/0: PASS +fdiv.s, infinity/0: PASS +fdiv.s, 0/infinity: PASS +fdiv.s, underflow: PASS +fdiv.s, overflow: PASS +fsqrt.s: PASS +fsqrt.s, NaN: PASS +fsqrt.s, quiet NaN: PASS +fsqrt.s, signaling NaN: PASS +fsqrt.s, infinity: PASS +fsgnj.s, ++: PASS +fsgnj.s, +-: PASS +fsgnj.s, -+: PASS +fsgnj.s, --: PASS +fsgnj.s, quiet NaN: PASS +fsgnj.s, signaling NaN: PASS +fsgnj.s, inject NaN: PASS +fsgnj.s, inject -NaN: PASS +fsgnjn.s, ++: PASS +fsgnjn.s, +-: PASS +fsgnjn.s, -+: PASS +fsgnjn.s, --: PASS +fsgnjn.s, quiet NaN: PASS +fsgnjn.s, signaling NaN: PASS +fsgnjn.s, inject NaN: PASS +fsgnjn.s, inject NaN: PASS +fsgnjx.s, ++: PASS +fsgnjx.s, +-: PASS +fsgnjx.s, -+: PASS +fsgnjx.s, --: PASS +fsgnjx.s, quiet NaN: PASS +fsgnjx.s, signaling NaN: PASS +fsgnjx.s, inject NaN: PASS +fsgnjx.s, inject -NaN: PASS +fmin.s: PASS +fmin.s, -infinity: PASS +fmin.s, infinity: PASS +fmin.s, quiet NaN first: PASS +fmin.s, quiet NaN second: PASS +fmin.s, quiet NaN both: PASS +fmin.s, signaling NaN first: PASS +fmin.s, signaling NaN second: PASS +fmin.s, signaling NaN both: PASS +fmax.s: PASS +fmax.s, -infinity: PASS +fmax.s, infinity: PASS +fmax.s, quiet NaN first: PASS +fmax.s, quiet NaN second: PASS +fmax.s, quiet NaN both: PASS +fmax.s, signaling NaN first: PASS +fmax.s, signaling NaN second: PASS +fmax.s, signaling NaN both: PASS +fcvt.w.s, truncate positive: PASS +fcvt.w.s, truncate negative: PASS +fcvt.w.s, 0.0: PASS +fcvt.w.s, -0.0: PASS +fcvt.w.s, overflow: PASS +fcvt.w.s, underflow: PASS +fcvt.w.s, infinity: PASS +fcvt.w.s, -infinity: PASS +fcvt.w.s, quiet NaN: PASS +fcvt.w.s, quiet -NaN: PASS +fcvt.w.s, signaling NaN: PASS +fcvt.wu.s, truncate positive: PASS +fcvt.wu.s, truncate negative: PASS +fcvt.wu.s, 0.0: PASS +fcvt.wu.s, -0.0: PASS +fcvt.wu.s, overflow: PASS +fcvt.wu.s, underflow: PASS +fcvt.wu.s, infinity: PASS +fcvt.wu.s, -infinity: PASS +fcvt.wu.s, quiet NaN: PASS +fcvt.wu.s, quiet -NaN: PASS +fcvt.wu.s, signaling NaN: PASS +fmv.x.s, positive: PASS +fmv.x.s, negative: PASS +fmv.x.s, 0.0: PASS +fmv.x.s, -0.0: PASS +feq.s, equal: PASS +feq.s, not equal: PASS +feq.s, 0 == -0: PASS +feq.s, quiet NaN first: PASS +feq.s, quiet NaN second: PASS +feq.s, quiet NaN both: PASS +feq.s, signaling NaN first: PASS +feq.s, signaling NaN second: PASS +feq.s, signaling NaN both: PASS +flt.s, equal: PASS +flt.s, less: PASS +flt.s, greater: PASS +flt.s, quiet NaN first: PASS +flt.s, quiet NaN second: PASS +flt.s, quiet NaN both: PASS +flt.s, signaling NaN first: PASS +flt.s, signaling NaN second: PASS +flt.s, signaling NaN both: PASS +fle.s, equal: PASS +fle.s, less: PASS +fle.s, greater: PASS +fle.s, 0 == -0: PASS +fle.s, quiet NaN first: PASS +fle.s, quiet NaN second: PASS +fle.s, quiet NaN both: PASS +fle.s, signaling NaN first: PASS +fle.s, signaling NaN second: PASS +fle.s, signaling NaN both: PASS +fclass.s, -infinity: PASS +fclass.s, -normal: PASS +fclass.s, -subnormal: PASS +fclass.s, -0.0: PASS +fclass.s, 0.0: PASS +fclass.s, subnormal: PASS +fclass.s, normal: PASS +fclass.s, infinity: PASS +fclass.s, signaling NaN: PASS +fclass.s, quiet NaN: PASS +fcvt.s.w, 0: PASS +fcvt.s.w, negative: PASS +fcvt.s.w, truncate: PASS +fcvt.s.wu, 0: PASS +fcvt.s.wu: PASS +fcvt.s.wu, truncate: PASS +fmv.s.x: PASS +fmv.s.x, truncate: PASS +fsrm: PASS +fsflags: PASS +fscsr: PASS +restore initial round mode: PASS +fcvt.l.s, truncate positive: PASS +fcvt.l.s, truncate negative: PASS +fcvt.l.s, 0.0: PASS +fcvt.l.s, -0.0: PASS +fcvt.l.s, 32-bit overflow: PASS +fcvt.l.s, overflow: PASS +fcvt.l.s, underflow: PASS +fcvt.l.s, infinity: PASS +fcvt.l.s, -infinity: PASS +fcvt.l.s, quiet NaN: PASS +fcvt.l.s, quiet -NaN: PASS +fcvt.l.s, signaling NaN: PASS +fcvt.lu.s, truncate positive: PASS +fcvt.lu.s, truncate negative: PASS +fcvt.lu.s, 0.0: PASS +fcvt.lu.s, -0.0: PASS +fcvt.lu.s, 32-bit overflow: PASS +fcvt.lu.s, overflow: PASS +fcvt.lu.s, underflow: PASS +fcvt.lu.s, infinity: PASS +fcvt.lu.s, -infinity: PASS +fcvt.lu.s, quiet NaN: PASS +fcvt.lu.s, quiet -NaN: PASS +fcvt.lu.s, signaling NaN: PASS +fcvt.s.l, 0: PASS +fcvt.s.l, negative: PASS +fcvt.s.l, 32-bit truncate: PASS +fcvt.s.lu, 0: PASS +fcvt.s.lu: PASS +fcvt.s.lu, 32-bit truncate: PASS +Exiting @ tick 7919377 because target called exit() diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/stats.txt --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing-ruby/stats.txt Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,644 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.007919 # Number of seconds simulated +sim_ticks 7919377 # Number of ticks simulated +final_tick 7919377 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000 # Frequency of simulated ticks +host_inst_rate 5726 # Simulator instruction rate (inst/s) +host_op_rate 5726 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 119800 # Simulator tick rate (ticks/s) +host_mem_usage 442780 # Number of bytes of host memory used +host_seconds 66.10 # Real time elapsed on the host +sim_insts 378553 # Number of instructions simulated +sim_ops 378553 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1 # Clock period in ticks +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 7919377 # Cumulative time (in ticks) in various power states +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 7632704 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 7632704 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 7632448 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 7632448 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 119261 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 119261 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 119257 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 119257 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 963801066 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 963801066 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 963768740 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 963768740 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 1927569807 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1927569807 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 119261 # Number of read requests accepted +system.mem_ctrls.writeReqs 119257 # Number of write requests accepted +system.mem_ctrls.readBursts 119261 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 119257 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 4231552 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 3401152 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 4399872 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 7632704 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 7632448 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 53143 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 50483 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 331 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 1407 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 3614 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 3934 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 6590 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 8573 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 1342 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 180 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 2917 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 14618 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 7928 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 1394 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 893 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 2252 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 10138 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 7 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 334 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 1501 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 3971 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 4004 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 6857 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 9587 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 1408 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 181 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 2991 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 15036 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 8016 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 1395 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 923 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 2265 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 10272 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 7 # Per bank write bursts +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.totGap 7919311 # Total gap between requests +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 119261 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 119257 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 66118 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see 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4628 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 4389 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 4233 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 4232 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 4232 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 4228 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 4229 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 4229 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 4228 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 4228 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 4228 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 4228 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 22261 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 387.682853 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 256.105531 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 340.190166 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 3568 16.02% 16.02% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 7204 32.36% 48.38% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 3120 14.01% 62.40% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 1657 7.44% 69.84% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 1114 5.00% 74.85% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 799 3.58% 78.44% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 815 3.66% 82.10% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 793 3.56% 85.66% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 3191 14.33% 99.99% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 22261 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 4228 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 15.635998 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 15.577585 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 1.374064 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::12-13 166 3.92% 3.92% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::14-15 1843 43.59% 47.51% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-17 1871 44.25% 91.76% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::18-19 323 7.63% 99.40% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::20-21 24 0.56% 99.97% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::36-37 1 0.02% 99.99% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 4228 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 4228 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.260170 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.241962 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 0.805677 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 3797 89.80% 89.80% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 37 0.87% 90.68% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 140 3.31% 93.99% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 233 5.51% 99.50% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::20 21 0.49% 99.99% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 4228 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 1244848 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 2501090 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 330590 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 18.82 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 37.82 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 534.32 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 555.58 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 963.80 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 963.76 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 8.51 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 4.17 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 4.34 # Data bus utilization in percentage for writes +system.mem_ctrls.avgRdQLen 0.99 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 25.96 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 50099 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 62502 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 75.77 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 90.88 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 33.20 # Average gap between requests +system.mem_ctrls.pageHitRate 83.47 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 75391260 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 40799976 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 296692704 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 232544736 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 626932800 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 818517720 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 14451072 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.actPowerDownEnergy 2641953648 # Energy for active power-down per rank (pJ) +system.mem_ctrls_0.prePowerDownEnergy 90566400 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_0.selfRefreshEnergy 19847520 # Energy for self refresh per rank (pJ) +system.mem_ctrls_0.totalEnergy 4857697836 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 613.374883 # Core power per rank (mW) +system.mem_ctrls_0.totalIdleTime 6086995 # Total Idle time Per DRAM Rank +system.mem_ctrls_0.memoryStateTime::IDLE 8924 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 265006 # Time in different power states +system.mem_ctrls_0.memoryStateTime::SREF 57387 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 235850 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 1558452 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 5793758 # Time in different power states +system.mem_ctrls_1.actEnergy 83580840 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 45216528 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 458639328 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 341638560 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 607264320 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 975395400 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 15982464 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.actPowerDownEnergy 2457900192 # Energy for active power-down per rank (pJ) +system.mem_ctrls_1.prePowerDownEnergy 34965504 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_1.selfRefreshEnergy 64571520 # Energy for self refresh per rank (pJ) +system.mem_ctrls_1.totalEnergy 5085154656 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 642.115491 # Core power per rank (mW) +system.mem_ctrls_1.totalIdleTime 5737592 # Total Idle time Per DRAM Rank +system.mem_ctrls_1.memoryStateTime::IDLE 13720 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 256910 # Time in different power states +system.mem_ctrls_1.memoryStateTime::SREF 257543 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 91056 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 1910016 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 5390132 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 7919377 # Cumulative time (in ticks) in various power states +system.cpu.clk_domain.clock 1 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 217 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 7919377 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 7919377 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 378553 # Number of instructions committed +system.cpu.committedOps 378553 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 378372 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 1151 # Number of float alu accesses +system.cpu.num_func_calls 27446 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 56202 # number of instructions that are conditional controls +system.cpu.num_int_insts 378372 # number of integer instructions +system.cpu.num_fp_insts 1151 # number of float instructions +system.cpu.num_int_register_reads 498827 # number of times the integer registers were read +system.cpu.num_int_register_writes 259639 # number of times the integer registers were written +system.cpu.num_fp_register_reads 924 # number of times the floating registers were read +system.cpu.num_fp_register_writes 756 # number of times the floating registers were written +system.cpu.num_mem_refs 151246 # number of memory refs +system.cpu.num_load_insts 88835 # Number of load instructions +system.cpu.num_store_insts 62411 # Number of store instructions +system.cpu.num_idle_cycles -0 # Number of idle cycles +system.cpu.num_busy_cycles 7919377 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction -0 # Percentage of idle cycles +system.cpu.Branches 83648 # Number of branches fetched +system.cpu.op_class::No_OpClass 233 0.06% 0.06% # Class of executed instruction +system.cpu.op_class::IntAlu 226224 59.72% 59.78% # Class of executed instruction +system.cpu.op_class::IntMult 624 0.16% 59.95% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 59.95% # Class of executed instruction +system.cpu.op_class::FloatAdd 128 0.03% 59.98% # Class of executed instruction +system.cpu.op_class::FloatCmp 161 0.04% 60.02% # Class of executed instruction +system.cpu.op_class::FloatCvt 109 0.02% 60.05% # Class of executed instruction +system.cpu.op_class::FloatMult 30 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::FloatDiv 11 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::FloatSqrt 5 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::MemRead 88288 23.30% 83.37% # Class of executed instruction +system.cpu.op_class::MemWrite 62251 16.43% 99.81% # Class of executed instruction +system.cpu.op_class::FloatMemRead 547 0.14% 99.95% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 160 0.04% 99.99% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 99.99% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 99.99% # Class of executed instruction +system.cpu.op_class::total 378771 # Class of executed instruction +system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.pwrStateResidencyTicks::UNDEFINED 7919377 # Cumulative time (in ticks) in various power states +system.ruby.delayHist::bucket_size 1 # delay histogram for all message +system.ruby.delayHist::max_bucket 9 # delay histogram for all message +system.ruby.delayHist::samples 238518 # delay histogram for all message +system.ruby.delayHist | 238518 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 238518 # delay histogram for all message +system.ruby.outstanding_req_hist_seqr::bucket_size 1 +system.ruby.outstanding_req_hist_seqr::max_bucket 9 +system.ruby.outstanding_req_hist_seqr::samples 530017 +system.ruby.outstanding_req_hist_seqr::mean 1 +system.ruby.outstanding_req_hist_seqr::gmean 1 +system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 530017 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 530017 +system.ruby.latency_hist_seqr::bucket_size 64 +system.ruby.latency_hist_seqr::max_bucket 639 +system.ruby.latency_hist_seqr::samples 530016 +system.ruby.latency_hist_seqr::mean 13.941769 +system.ruby.latency_hist_seqr::gmean 2.427563 +system.ruby.latency_hist_seqr::stdev 29.776069 +system.ruby.latency_hist_seqr | 466449 88.00% 88.00% | 58934 11.11% 99.12% | 3161 0.59% 99.72% | 523 0.09% 99.82% | 518 0.09% 99.91% | 376 0.07% 99.98% | 35 0.00% 99.99% | 4 0.00% 99.99% | 1 0.00% 99.99% | 15 0.00% 99.99% +system.ruby.latency_hist_seqr::total 530016 +system.ruby.hit_latency_hist_seqr::bucket_size 1 +system.ruby.hit_latency_hist_seqr::max_bucket 9 +system.ruby.hit_latency_hist_seqr::samples 410755 +system.ruby.hit_latency_hist_seqr::mean 1 +system.ruby.hit_latency_hist_seqr::gmean 1 +system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 410755 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 410755 +system.ruby.miss_latency_hist_seqr::bucket_size 64 +system.ruby.miss_latency_hist_seqr::max_bucket 639 +system.ruby.miss_latency_hist_seqr::samples 119261 +system.ruby.miss_latency_hist_seqr::mean 58.515407 +system.ruby.miss_latency_hist_seqr::gmean 51.494728 +system.ruby.miss_latency_hist_seqr::stdev 37.102517 +system.ruby.miss_latency_hist_seqr | 55694 46.69% 46.69% | 58934 49.41% 96.11% | 3161 2.65% 98.76% | 523 0.43% 99.20% | 518 0.43% 99.63% | 376 0.31% 99.95% | 35 0.02% 99.98% | 4 0.00% 99.98% | 1 0.00% 99.98% | 15 0.01% 99.99% +system.ruby.miss_latency_hist_seqr::total 119261 +system.ruby.Directory.incomplete_times_seqr 119260 +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 7919377 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.cacheMemory.demand_hits 410755 # Number of cache demand hits +system.ruby.l1_cntrl0.cacheMemory.demand_misses 119261 # Number of cache demand misses +system.ruby.l1_cntrl0.cacheMemory.demand_accesses 530016 # Number of cache demand accesses +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 7919377 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 7919377 # Cumulative time (in ticks) in various power states +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 7919377 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.percent_links_utilized 7.529569 +system.ruby.network.routers0.msg_count.Control::2 119261 +system.ruby.network.routers0.msg_count.Data::2 119257 +system.ruby.network.routers0.msg_count.Response_Data::4 119261 +system.ruby.network.routers0.msg_count.Writeback_Control::3 119257 +system.ruby.network.routers0.msg_bytes.Control::2 954088 +system.ruby.network.routers0.msg_bytes.Data::2 8586504 +system.ruby.network.routers0.msg_bytes.Response_Data::4 8586792 +system.ruby.network.routers0.msg_bytes.Writeback_Control::3 954056 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 7919377 # Cumulative time (in ticks) in various power states +system.ruby.network.routers1.percent_links_utilized 7.529569 +system.ruby.network.routers1.msg_count.Control::2 119261 +system.ruby.network.routers1.msg_count.Data::2 119257 +system.ruby.network.routers1.msg_count.Response_Data::4 119261 +system.ruby.network.routers1.msg_count.Writeback_Control::3 119257 +system.ruby.network.routers1.msg_bytes.Control::2 954088 +system.ruby.network.routers1.msg_bytes.Data::2 8586504 +system.ruby.network.routers1.msg_bytes.Response_Data::4 8586792 +system.ruby.network.routers1.msg_bytes.Writeback_Control::3 954056 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 7919377 # Cumulative time (in ticks) in various power states +system.ruby.network.routers2.percent_links_utilized 7.529569 +system.ruby.network.routers2.msg_count.Control::2 119261 +system.ruby.network.routers2.msg_count.Data::2 119257 +system.ruby.network.routers2.msg_count.Response_Data::4 119261 +system.ruby.network.routers2.msg_count.Writeback_Control::3 119257 +system.ruby.network.routers2.msg_bytes.Control::2 954088 +system.ruby.network.routers2.msg_bytes.Data::2 8586504 +system.ruby.network.routers2.msg_bytes.Response_Data::4 8586792 +system.ruby.network.routers2.msg_bytes.Writeback_Control::3 954056 +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 7919377 # Cumulative time (in ticks) in various power states +system.ruby.network.msg_count.Control 357783 +system.ruby.network.msg_count.Data 357771 +system.ruby.network.msg_count.Response_Data 357783 +system.ruby.network.msg_count.Writeback_Control 357771 +system.ruby.network.msg_byte.Control 2862264 +system.ruby.network.msg_byte.Data 25759512 +system.ruby.network.msg_byte.Response_Data 25760376 +system.ruby.network.msg_byte.Writeback_Control 2862168 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 7919377 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.throttle0.link_utilization 7.529670 +system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 119261 +system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 119257 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 8586792 +system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 954056 +system.ruby.network.routers0.throttle1.link_utilization 7.529468 +system.ruby.network.routers0.throttle1.msg_count.Control::2 119261 +system.ruby.network.routers0.throttle1.msg_count.Data::2 119257 +system.ruby.network.routers0.throttle1.msg_bytes.Control::2 954088 +system.ruby.network.routers0.throttle1.msg_bytes.Data::2 8586504 +system.ruby.network.routers1.throttle0.link_utilization 7.529468 +system.ruby.network.routers1.throttle0.msg_count.Control::2 119261 +system.ruby.network.routers1.throttle0.msg_count.Data::2 119257 +system.ruby.network.routers1.throttle0.msg_bytes.Control::2 954088 +system.ruby.network.routers1.throttle0.msg_bytes.Data::2 8586504 +system.ruby.network.routers1.throttle1.link_utilization 7.529670 +system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 119261 +system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 119257 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 8586792 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 954056 +system.ruby.network.routers2.throttle0.link_utilization 7.529670 +system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 119261 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 119257 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 8586792 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 954056 +system.ruby.network.routers2.throttle1.link_utilization 7.529468 +system.ruby.network.routers2.throttle1.msg_count.Control::2 119261 +system.ruby.network.routers2.throttle1.msg_count.Data::2 119257 +system.ruby.network.routers2.throttle1.msg_bytes.Control::2 954088 +system.ruby.network.routers2.throttle1.msg_bytes.Data::2 8586504 +system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::samples 119261 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1 | 119261 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::total 119261 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::samples 119257 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2 | 119257 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::total 119257 # delay histogram for vnet_2 +system.ruby.LD.latency_hist_seqr::bucket_size 64 +system.ruby.LD.latency_hist_seqr::max_bucket 639 +system.ruby.LD.latency_hist_seqr::samples 88835 +system.ruby.LD.latency_hist_seqr::mean 27.163505 +system.ruby.LD.latency_hist_seqr::gmean 7.015696 +system.ruby.LD.latency_hist_seqr::stdev 35.575384 +system.ruby.LD.latency_hist_seqr | 71130 80.06% 80.06% | 16324 18.37% 98.44% | 937 1.05% 99.50% | 169 0.19% 99.69% | 163 0.18% 99.87% | 97 0.10% 99.98% | 13 0.01% 99.99% | 2 0.00% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% +system.ruby.LD.latency_hist_seqr::total 88835 +system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 +system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 +system.ruby.LD.hit_latency_hist_seqr::samples 43632 +system.ruby.LD.hit_latency_hist_seqr::mean 1 +system.ruby.LD.hit_latency_hist_seqr::gmean 1 +system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 43632 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::total 43632 +system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 +system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 +system.ruby.LD.miss_latency_hist_seqr::samples 45203 +system.ruby.LD.miss_latency_hist_seqr::mean 52.417715 +system.ruby.LD.miss_latency_hist_seqr::gmean 45.997787 +system.ruby.LD.miss_latency_hist_seqr::stdev 34.477748 +system.ruby.LD.miss_latency_hist_seqr | 27498 60.83% 60.83% | 16324 36.11% 96.94% | 937 2.07% 99.01% | 169 0.37% 99.39% | 163 0.36% 99.75% | 97 0.21% 99.96% | 13 0.02% 99.99% | 2 0.00% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% +system.ruby.LD.miss_latency_hist_seqr::total 45203 +system.ruby.ST.latency_hist_seqr::bucket_size 64 +system.ruby.ST.latency_hist_seqr::max_bucket 639 +system.ruby.ST.latency_hist_seqr::samples 62410 +system.ruby.ST.latency_hist_seqr::mean 15.050873 +system.ruby.ST.latency_hist_seqr::gmean 3.184795 +system.ruby.ST.latency_hist_seqr::stdev 27.802318 +system.ruby.ST.latency_hist_seqr | 57280 91.78% 91.78% | 4643 7.43% 99.21% | 356 0.57% 99.79% | 44 0.07% 99.86% | 40 0.06% 99.92% | 29 0.04% 99.97% | 6 0.00% 99.98% | 1 0.00% 99.98% | 1 0.00% 99.98% | 10 0.01% 99.99% +system.ruby.ST.latency_hist_seqr::total 62410 +system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 +system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 +system.ruby.ST.hit_latency_hist_seqr::samples 42926 +system.ruby.ST.hit_latency_hist_seqr::mean 1 +system.ruby.ST.hit_latency_hist_seqr::gmean 1 +system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 42926 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist_seqr::total 42926 +system.ruby.ST.miss_latency_hist_seqr::bucket_size 64 +system.ruby.ST.miss_latency_hist_seqr::max_bucket 639 +system.ruby.ST.miss_latency_hist_seqr::samples 19484 +system.ruby.ST.miss_latency_hist_seqr::mean 46.006928 +system.ruby.ST.miss_latency_hist_seqr::gmean 40.873431 +system.ruby.ST.miss_latency_hist_seqr::stdev 32.904517 +system.ruby.ST.miss_latency_hist_seqr | 14354 73.67% 73.67% | 4643 23.82% 97.50% | 356 1.82% 99.32% | 44 0.22% 99.55% | 40 0.20% 99.75% | 29 0.14% 99.90% | 6 0.03% 99.93% | 1 0.00% 99.94% | 1 0.00% 99.94% | 10 0.05% 99.99% +system.ruby.ST.miss_latency_hist_seqr::total 19484 +system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.latency_hist_seqr::samples 378771 +system.ruby.IFETCH.latency_hist_seqr::mean 10.658065 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.809860 +system.ruby.IFETCH.latency_hist_seqr::stdev 27.649087 +system.ruby.IFETCH.latency_hist_seqr | 338039 89.24% 89.24% | 37967 10.02% 99.27% | 1868 0.49% 99.76% | 310 0.08% 99.84% | 315 0.08% 99.92% | 250 0.06% 99.99% | 16 0.00% 99.99% | 1 0.00% 99.99% | 0 0.00% 99.99% | 5 0.00% 99.99% +system.ruby.IFETCH.latency_hist_seqr::total 378771 +system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 +system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 +system.ruby.IFETCH.hit_latency_hist_seqr::samples 324197 +system.ruby.IFETCH.hit_latency_hist_seqr::mean 1 +system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 +system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 324197 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist_seqr::total 324197 +system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.miss_latency_hist_seqr::samples 54574 +system.ruby.IFETCH.miss_latency_hist_seqr::mean 68.031828 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 61.402651 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 38.209487 +system.ruby.IFETCH.miss_latency_hist_seqr | 13842 25.36% 25.36% | 37967 69.56% 94.93% | 1868 3.42% 98.35% | 310 0.56% 98.92% | 315 0.57% 99.50% | 250 0.45% 99.95% | 16 0.02% 99.98% | 1 0.00% 99.99% | 0 0.00% 99.99% | 5 0.00% 99.99% +system.ruby.IFETCH.miss_latency_hist_seqr::total 54574 +system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 +system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 +system.ruby.Directory.miss_mach_latency_hist_seqr::samples 119261 +system.ruby.Directory.miss_mach_latency_hist_seqr::mean 58.515407 +system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 51.494728 +system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 37.102517 +system.ruby.Directory.miss_mach_latency_hist_seqr | 55694 46.69% 46.69% | 58934 49.41% 96.11% | 3161 2.65% 98.76% | 523 0.43% 99.20% | 518 0.43% 99.63% | 376 0.31% 99.95% | 35 0.02% 99.98% | 4 0.00% 99.98% | 1 0.00% 99.98% | 15 0.01% 99.99% +system.ruby.Directory.miss_mach_latency_hist_seqr::total 119261 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::total 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total 1 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size 8 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 79 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean 75 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 74.999999 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 45203 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 52.417715 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 45.997787 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 34.477748 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 27498 60.83% 60.83% | 16324 36.11% 96.94% | 937 2.07% 99.01% | 169 0.37% 99.39% | 163 0.36% 99.75% | 97 0.21% 99.96% | 13 0.02% 99.99% | 2 0.00% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 45203 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 19484 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 46.006928 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 40.873431 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 32.904517 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 14354 73.67% 73.67% | 4643 23.82% 97.50% | 356 1.82% 99.32% | 44 0.22% 99.55% | 40 0.20% 99.75% | 29 0.14% 99.90% | 6 0.03% 99.93% | 1 0.00% 99.94% | 1 0.00% 99.94% | 10 0.05% 99.99% +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 19484 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 54574 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 68.031828 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 61.402651 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 38.209487 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 13842 25.36% 25.36% | 37967 69.56% 94.93% | 1868 3.42% 98.35% | 310 0.56% 98.92% | 315 0.57% 99.50% | 250 0.45% 99.95% | 16 0.02% 99.98% | 1 0.00% 99.99% | 0 0.00% 99.99% | 5 0.00% 99.99% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 54574 +system.ruby.Directory_Controller.GETX 119261 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 119257 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 119261 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 119257 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 119261 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 119257 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 119261 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 119257 0.00% 0.00% +system.ruby.L1Cache_Controller.Load 88835 0.00% 0.00% +system.ruby.L1Cache_Controller.Ifetch 378771 0.00% 0.00% +system.ruby.L1Cache_Controller.Store 62410 0.00% 0.00% +system.ruby.L1Cache_Controller.Data 119261 0.00% 0.00% +system.ruby.L1Cache_Controller.Replacement 119257 0.00% 0.00% +system.ruby.L1Cache_Controller.Writeback_Ack 119257 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Load 45203 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Ifetch 54574 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Store 19484 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Load 43632 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Ifetch 324197 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Store 42926 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Replacement 119257 0.00% 0.00% +system.ruby.L1Cache_Controller.MI.Writeback_Ack 119257 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Data 99777 0.00% 0.00% +system.ruby.L1Cache_Controller.IM.Data 19484 0.00% 0.00% + +---------- End Simulation Statistics ---------- diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/config.ini --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/config.ini Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,374 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=TimingSimpleCPU +children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +hit_latency=2 +is_read_only=false +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=262144 + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.icache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +hit_latency=2 +is_read_only=true +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tags=system.cpu.icache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=131072 + +[system.cpu.interrupts] +type=RiscvInterrupts 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+p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=2097152 + +[system.cpu.toL2Bus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=0 +frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null +response_latency=1 +snoop_filter=system.cpu.toL2Bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 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+master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +eventq_index=0 +in_addr_map=true +kvm_map=true +latency=30000 +latency_var=0 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +range=0:134217727:0:0:0:0 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/config.json --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/simple-timing/config.json Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,502 @@ +{ + "name": null, + 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"errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "progress_interval": 0, + "branchPred": null, + "dcache": { + "cpu_side": { + "peer": "system.cpu.dcache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 262144, + "tags": { + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.dcache.tags", + "hit_latency": 2, + "block_size": 64, + "type": "LRU", + "size": 262144 + }, + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[1]", + "role": "MASTER" + }, + "type": "Cache", + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "hit_latency": 2, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.dcache", + "mshrs": 4, + "name": "dcache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/stats.txt --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/stats.txt Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,765 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000392 # Number of seconds simulated +sim_ticks 392627500 # Number of ticks simulated +final_tick 392627500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 17210 # Simulator instruction rate (inst/s) +host_op_rate 17210 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 17840135 # Simulator tick rate (ticks/s) +host_mem_usage 276648 # Number of bytes of host memory used +host_seconds 22.00 # Real time elapsed on the host +sim_insts 378771 # Number of instructions simulated +sim_ops 378771 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 392627500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 81600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 21440 # Number of bytes read from this memory +system.physmem.bytes_read::total 103040 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 81600 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 81600 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 1275 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 335 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1610 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 207830577 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 54606465 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 262437042 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 207830577 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 207830577 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 207830577 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 54606465 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 262437042 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1610 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 1610 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 103040 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 103040 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 165 # Per bank write bursts +system.physmem.perBankRdBursts::1 123 # Per bank write bursts +system.physmem.perBankRdBursts::2 57 # Per bank write bursts +system.physmem.perBankRdBursts::3 229 # Per bank write bursts +system.physmem.perBankRdBursts::4 232 # Per bank write bursts +system.physmem.perBankRdBursts::5 116 # Per bank write bursts +system.physmem.perBankRdBursts::6 3 # Per bank write bursts +system.physmem.perBankRdBursts::7 31 # Per bank write bursts +system.physmem.perBankRdBursts::8 139 # Per bank write bursts +system.physmem.perBankRdBursts::9 183 # Per bank write bursts +system.physmem.perBankRdBursts::10 88 # Per bank write bursts +system.physmem.perBankRdBursts::11 21 # Per bank write bursts +system.physmem.perBankRdBursts::12 27 # Per bank write bursts +system.physmem.perBankRdBursts::13 67 # Per bank write bursts +system.physmem.perBankRdBursts::14 120 # Per bank write bursts +system.physmem.perBankRdBursts::15 9 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 392268000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 1610 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1546 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 61 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 306 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 332.130718 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 240.890586 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 257.073331 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 51 16.66% 16.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 86 28.10% 44.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 48 15.68% 60.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 47 15.35% 75.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 32 10.45% 86.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 22 7.18% 93.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 0.65% 94.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 0.65% 94.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16 5.22% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 306 # Bytes accessed per row activation +system.physmem.totQLat 20944750 # Total ticks spent queuing +system.physmem.totMemAccLat 51132250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 8050000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13009.16 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 31759.16 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 262.43 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 262.43 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 2.05 # Data bus utilization in percentage +system.physmem.busUtilRead 2.05 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 1299 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.68 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 243644.72 # Average gap between requests +system.physmem.pageHitRate 80.68 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1113840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 588225 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 6825840 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 30732000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 17463660 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 730560 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 146703180 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 11792640 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 215949945 # Total energy per rank (pJ) +system.physmem_0.averagePower 550.012276 # Core power per rank (mW) +system.physmem_0.totalIdleTime 352027500 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 330000 # Time in different power states +system.physmem_0.memoryStateTime::REF 13000000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 0 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 30702750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 26827250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 321767500 # Time in different power states +system.physmem_1.actEnergy 1106700 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 573045 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4669560 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 30732000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 14265960 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 3627840 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 125034630 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 29835360 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 209845095 # Total energy per rank (pJ) +system.physmem_1.averagePower 534.463569 # Core power per rank (mW) +system.physmem_1.totalIdleTime 351575750 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 8062250 # Time in different power states +system.physmem_1.memoryStateTime::REF 13000000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 0 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 77685500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 19666750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 274213000 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 392627500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 102535 # Number of BP lookups +system.cpu.branchPred.condPredicted 65255 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7538 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 78716 # Number of BTB lookups +system.cpu.branchPred.BTBHits 46757 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 59.399613 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 16985 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 9501 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 7484 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 4244 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 217 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 392627500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 785255 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 378771 # Number of instructions committed +system.cpu.committedOps 378771 # Number of ops (including micro ops) committed +system.cpu.discardedOps 18106 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 2.073165 # CPI: cycles per instruction +system.cpu.ipc 0.482354 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 233 0.06% 0.06% # Class of committed instruction +system.cpu.op_class_0::IntAlu 226224 59.72% 59.78% # Class of committed instruction +system.cpu.op_class_0::IntMult 624 0.16% 59.95% # Class of committed instruction +system.cpu.op_class_0::IntDiv 0 0.00% 59.95% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 128 0.03% 59.98% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 161 0.04% 60.02% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 109 0.02% 60.05% # Class of committed instruction +system.cpu.op_class_0::FloatMult 30 0.00% 60.06% # Class of committed instruction +system.cpu.op_class_0::FloatMultAcc 0 0.00% 60.06% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 11 0.00% 60.06% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 0 0.00% 60.06% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 5 0.00% 60.06% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 60.06% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 60.06% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 60.06% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 60.06% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 60.06% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 60.06% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 60.06% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 60.06% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 60.06% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 60.06% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 60.06% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 60.06% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 60.06% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 60.06% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 0 0.00% 60.06% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 60.06% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 0 0.00% 60.06% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 60.06% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 60.06% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 60.06% # Class of committed instruction +system.cpu.op_class_0::MemRead 88288 23.30% 83.37% # Class of committed instruction +system.cpu.op_class_0::MemWrite 62251 16.43% 99.81% # Class of committed instruction +system.cpu.op_class_0::FloatMemRead 547 0.14% 99.95% # Class of committed instruction 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references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 266.141708 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.064976 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.064976 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 336 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 307 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.082031 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 308834 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 308834 # Number of data accesses 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WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 530 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 530 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 530 # number of overall misses +system.cpu.dcache.overall_misses::total 530 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12829000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12829000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 31700500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 31700500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 44529500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 44529500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 44529500 # number of overall miss cycles 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accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006248 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006248 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.003436 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.003436 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.003436 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.003436 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 91635.714285 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 91635.714285 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81283.333333 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 81283.333333 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 84017.924528 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 84017.924528 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 84017.924528 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 84017.924528 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits 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demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 336 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 336 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12112000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12112000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 16385000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 16385000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28497000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 28497000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28497000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28497000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001459 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001459 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003236 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003236 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002178 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002178 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002178 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002178 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 90388.059701 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 90388.059701 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81113.861386 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81113.861386 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84812.500000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 84812.500000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84812.500000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 84812.500000 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 392627500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 88 # number of replacements +system.cpu.icache.tags.tagsinuse 723.556165 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 161587 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1276 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 126.635579 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 723.556165 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.353298 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.353298 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1188 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 182 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 960 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.580078 # Percentage of cache occupancy per task id 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number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1276 # number of overall misses +system.cpu.icache.overall_misses::total 1276 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 108438000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 108438000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 108438000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 108438000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 108438000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 108438000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 162863 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 162863 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 162863 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 162863 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 162863 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 162863 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007834 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.007834 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.007834 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.007834 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.007834 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.007834 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 84982.758620 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 84982.758620 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 84982.758620 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 84982.758620 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 84982.758620 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 84982.758620 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 88 # number 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(read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 107162000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 107162000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.007834 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.007834 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.007834 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.007834 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.007834 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.007834 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83982.758620 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83982.758620 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83982.758620 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 83982.758620 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83982.758620 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 83982.758620 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 392627500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 1020.438760 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 90 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1610 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.055900 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 755.044389 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 265.394371 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.023042 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.008099 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.031141 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 1610 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1354 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.049133 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 15210 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 15210 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 392627500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackClean_hits::writebacks 88 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 88 # number of WritebackClean hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits 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demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 133216000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 105237500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 27978500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 133216000 # number of overall miss cycles +system.cpu.l2cache.WritebackClean_accesses::writebacks 88 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 88 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 202 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 202 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1276 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1276 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 134 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 134 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1276 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 336 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1612 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1276 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 336 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1612 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.999216 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.999216 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.992537 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.992537 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.999216 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.997023 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.998759 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.999216 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.997023 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.998759 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79611.386138 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79611.386138 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82539.215686 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82539.215686 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 89451.127819 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 89451.127819 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82539.215686 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83517.910447 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 82742.857142 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82539.215686 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83517.910447 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 82742.857142 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 202 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 202 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1275 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1275 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 133 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 133 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1275 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 335 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1610 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1275 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 335 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1610 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14061500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14061500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 92487500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 92487500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 10567000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 10567000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 92487500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 24628500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 117116000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 92487500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 24628500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 117116000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.999216 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.999216 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.992537 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.992537 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.999216 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.997023 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.998759 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.999216 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.997023 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.998759 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69611.386138 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69611.386138 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72539.215686 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72539.215686 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79451.127819 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79451.127819 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72539.215686 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73517.910447 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72742.857142 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72539.215686 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73517.910447 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72742.857142 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1700 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 89 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 392627500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 1410 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 88 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 202 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 202 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1276 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 134 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2640 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 672 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3312 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 87296 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21504 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 108800 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 1612 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000620 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.024906 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1611 99.93% 99.93% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1 0.06% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1612 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 938000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1914000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 504000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 1610 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 392627500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1408 # Transaction distribution +system.membus.trans_dist::ReadExReq 202 # Transaction distribution +system.membus.trans_dist::ReadExResp 202 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1408 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3220 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3220 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 103040 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 103040 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1610 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev -0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1610 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1610 # Request fanout histogram +system.membus.reqLayer0.occupancy 1891000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 8540250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 2.1 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/config.ini --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/config.ini Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,866 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cachePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +default_p_state=UNDEFINED +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=0 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +system=system +tracer=system.cpu.tracer +trapLatency=13 +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TournamentBP +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +useIndirect=true + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +hit_latency=2 +is_read_only=false +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=262144 + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +eventq_index=0 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +opClass=IntAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +eventq_index=0 +opClass=IntMult +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +eventq_index=0 +opClass=IntDiv +opLat=20 +pipelined=false + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +eventq_index=0 +opClass=FloatAdd +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatCmp +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatCvt +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 opList3 opList4 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +eventq_index=0 +opClass=FloatMult +opLat=4 +pipelined=true + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMultAcc +opLat=5 +pipelined=true + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMisc +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList3.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatDiv +opLat=12 +pipelined=false + +[system.cpu.fuPool.FUList3.opList4] +type=OpDesc +eventq_index=0 +opClass=FloatSqrt +opLat=24 +pipelined=false + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList0 opList1 +count=0 +eventq_index=0 +opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +eventq_index=0 +opClass=MemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList4.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5] +type=FUDesc +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 + +[system.cpu.fuPool.FUList5.opList00] +type=OpDesc +eventq_index=0 +opClass=SimdAdd +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList01] +type=OpDesc +eventq_index=0 +opClass=SimdAddAcc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList02] +type=OpDesc +eventq_index=0 +opClass=SimdAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList03] +type=OpDesc +eventq_index=0 +opClass=SimdCmp +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList04] +type=OpDesc +eventq_index=0 +opClass=SimdCvt +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList05] +type=OpDesc +eventq_index=0 +opClass=SimdMisc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList06] +type=OpDesc +eventq_index=0 +opClass=SimdMult +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList07] +type=OpDesc +eventq_index=0 +opClass=SimdMultAcc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList08] +type=OpDesc +eventq_index=0 +opClass=SimdShift +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList09] +type=OpDesc +eventq_index=0 +opClass=SimdShiftAcc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList10] +type=OpDesc +eventq_index=0 +opClass=SimdSqrt +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList11] +type=OpDesc +eventq_index=0 +opClass=SimdFloatAdd +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList12] +type=OpDesc +eventq_index=0 +opClass=SimdFloatAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList13] +type=OpDesc +eventq_index=0 +opClass=SimdFloatCmp +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList14] +type=OpDesc +eventq_index=0 +opClass=SimdFloatCvt +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList15] +type=OpDesc +eventq_index=0 +opClass=SimdFloatDiv +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList16] +type=OpDesc +eventq_index=0 +opClass=SimdFloatMisc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList17] +type=OpDesc +eventq_index=0 +opClass=SimdFloatMult +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList18] +type=OpDesc +eventq_index=0 +opClass=SimdFloatMultAcc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList19] +type=OpDesc +eventq_index=0 +opClass=SimdFloatSqrt +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList6] +type=FUDesc +children=opList0 opList1 +count=0 +eventq_index=0 +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +eventq_index=0 +opClass=MemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7] +type=FUDesc +children=opList0 opList1 opList2 opList3 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +eventq_index=0 +opClass=MemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7.opList1] +type=OpDesc +eventq_index=0 +opClass=MemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList8] +type=FUDesc +children=opList +count=1 +eventq_index=0 +opList=system.cpu.fuPool.FUList8.opList + +[system.cpu.fuPool.FUList8.opList] +type=OpDesc +eventq_index=0 +opClass=IprAccess +opLat=3 +pipelined=false + +[system.cpu.icache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +hit_latency=2 +is_read_only=true +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tags=system.cpu.icache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=131072 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.l2cache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +hit_latency=20 +is_read_only=false +max_miss_count=0 +mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +hit_latency=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=2097152 + +[system.cpu.toL2Bus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=0 +frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null +response_latency=1 +snoop_filter=system.cpu.toL2Bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64f/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=DRAMCtrl +IDD0=0.055000 +IDD02=0.000000 +IDD2N=0.032000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.032000 +IDD2P12=0.000000 +IDD3N=0.038000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.038000 +IDD3P12=0.000000 +IDD4R=0.157000 +IDD4R2=0.000000 +IDD4W=0.125000 +IDD4W2=0.000000 +IDD5=0.235000 +IDD52=0.000000 +IDD6=0.020000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +page_policy=open_adaptive +power_model=Null +range=0:134217727:0:0:0:0 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCCD_L=0 +tCK=1250 +tCL=13750 +tCS=2500 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/config.ini --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/config.ini Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,896 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=MinorCPU +children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload +branchPred=system.cpu.branchPred +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +decodeCycleInput=true +decodeInputBufferSize=3 +decodeInputWidth=2 +decodeToExecuteForwardDelay=1 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +enableIdling=true +eventq_index=0 +executeAllowEarlyMemoryIssue=true +executeBranchDelay=1 +executeCommitLimit=2 +executeCycleInput=true +executeFuncUnits=system.cpu.executeFuncUnits +executeInputBufferSize=7 +executeInputWidth=2 +executeIssueLimit=2 +executeLSQMaxStoreBufferStoresPerCycle=2 +executeLSQRequestsQueueSize=1 +executeLSQStoreBufferSize=5 +executeLSQTransfersQueueSize=2 +executeMaxAccessesInMemory=2 +executeMemoryCommitLimit=1 +executeMemoryIssueLimit=1 +executeMemoryWidth=0 +executeSetTraceTimeOnCommit=true +executeSetTraceTimeOnIssue=false +fetch1FetchLimit=1 +fetch1LineSnapWidth=0 +fetch1LineWidth=0 +fetch1ToFetch2BackwardDelay=1 +fetch1ToFetch2ForwardDelay=1 +fetch2CycleInput=true +fetch2InputBufferSize=2 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+executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64f/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=DRAMCtrl +IDD0=0.055000 +IDD02=0.000000 +IDD2N=0.032000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.032000 +IDD2P12=0.000000 +IDD3N=0.038000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.038000 +IDD3P12=0.000000 +IDD4R=0.157000 +IDD4R2=0.000000 +IDD4W=0.125000 +IDD4W2=0.000000 +IDD5=0.235000 +IDD52=0.000000 +IDD6=0.020000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +page_policy=open_adaptive +power_model=Null +range=0:134217727:0:0:0:0 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCCD_L=0 +tCK=1250 +tCL=13750 +tCS=2500 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/config.json --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/config.json Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,1205 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.l2cache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": 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}, + "type": "Cache", + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "hit_latency": 2, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.dcache", + "mshrs": 4, + "name": "dcache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "path": "system.cpu", + "fetch1ToFetch2ForwardDelay": 1, + "decodeInputBufferSize": 3 + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/simerr --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/simerr Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,4 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/simout --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/minor-timing/simout Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,222 @@ +Redirecting stdout to build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64f/minor-timing/simout +Redirecting stderr to build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64f/minor-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 2 2016 20:34:02 +gem5 started Nov 3 2016 19:01:16 +gem5 executing on ubuntu1604, pid 22151 +command line: /home/ar4jc/gem5/build/RISCV/gem5.debug -d build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64f/minor-timing -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64f/minor-timing + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +clear fsflags: PASS +flw: PASS +fsw: PASS +fmadd.s: PASS +fmadd.s, quiet NaN: PASS +fmadd.s, signaling NaN: PASS +fmadd.s, infinity: PASS +fmadd.s, -infinity: PASS +fmsub.s: PASS +fmsub.s, quiet NaN: PASS +fmsub.s, signaling NaN: PASS +fmsub.s, infinity: PASS +fmsub.s, -infinity: PASS +fmsub.s, subtract infinity: PASS +fnmsub.s: PASS +fnmsub.s, quiet NaN: PASS +fnmsub.s, signaling NaN: PASS +fnmsub.s, infinity: PASS +fnmsub.s, -infinity: PASS +fnmsub.s, subtract infinity: PASS +fnmadd.s: PASS +fnmadd.s, quiet NaN: PASS +fnmadd.s, signaling NaN: PASS +fnmadd.s, infinity: PASS +fnmadd.s, -infinity: PASS +fadd.s: PASS +fadd.s, quiet NaN: PASS +fadd.s, signaling NaN: PASS +fadd.s, infinity: PASS +fadd.s, -infinity: PASS +fsub.s: PASS +fsub.s, quiet NaN: PASS +fsub.s, signaling NaN: PASS +fsub.s, infinity: PASS +fsub.s, -infinity: PASS +fsub.s, subtract infinity: PASS +fmul.s: PASS +fmul.s, quiet NaN: PASS +fmul.s, signaling NaN: PASS +fmul.s, infinity: PASS +fmul.s, -infinity: PASS +fmul.s, 0*infinity: PASS +fmul.s, overflow: PASS +fmul.s, underflow: PASS +fdiv.s: PASS +fdiv.s, quiet NaN: PASS +fdiv.s, signaling NaN: PASS +fdiv.s/0: PASS +fdiv.s/infinity: PASS +fdiv.s, infinity/infinity: PASS +fdiv.s, 0/0: PASS +fdiv.s, infinity/0: PASS +fdiv.s, 0/infinity: PASS +fdiv.s, underflow: PASS +fdiv.s, overflow: PASS +fsqrt.s: PASS +fsqrt.s, NaN: PASS +fsqrt.s, quiet NaN: PASS +fsqrt.s, signaling NaN: PASS +fsqrt.s, infinity: PASS +fsgnj.s, ++: PASS +fsgnj.s, +-: PASS +fsgnj.s, -+: PASS +fsgnj.s, --: PASS +fsgnj.s, quiet NaN: PASS +fsgnj.s, signaling NaN: PASS +fsgnj.s, inject NaN: PASS +fsgnj.s, inject -NaN: PASS +fsgnjn.s, ++: PASS +fsgnjn.s, +-: PASS +fsgnjn.s, -+: PASS +fsgnjn.s, --: PASS +fsgnjn.s, quiet NaN: PASS +fsgnjn.s, signaling NaN: PASS +fsgnjn.s, inject NaN: PASS +fsgnjn.s, inject NaN: PASS +fsgnjx.s, ++: PASS +fsgnjx.s, +-: PASS +fsgnjx.s, -+: PASS +fsgnjx.s, --: PASS +fsgnjx.s, quiet NaN: PASS +fsgnjx.s, signaling NaN: PASS +fsgnjx.s, inject NaN: PASS +fsgnjx.s, inject -NaN: PASS +fmin.s: PASS +fmin.s, -infinity: PASS +fmin.s, infinity: PASS +fmin.s, quiet NaN first: PASS +fmin.s, quiet NaN second: PASS +fmin.s, quiet NaN both: PASS +fmin.s, signaling NaN first: PASS +fmin.s, signaling NaN second: PASS +fmin.s, signaling NaN both: PASS +fmax.s: PASS +fmax.s, -infinity: PASS +fmax.s, infinity: PASS +fmax.s, quiet NaN first: PASS +fmax.s, quiet NaN second: PASS +fmax.s, quiet NaN both: PASS +fmax.s, signaling NaN first: PASS +fmax.s, signaling NaN second: PASS +fmax.s, signaling NaN both: PASS +fcvt.w.s, truncate positive: PASS +fcvt.w.s, truncate negative: PASS +fcvt.w.s, 0.0: PASS +fcvt.w.s, -0.0: PASS +fcvt.w.s, overflow: PASS +fcvt.w.s, underflow: PASS +fcvt.w.s, infinity: PASS +fcvt.w.s, -infinity: PASS +fcvt.w.s, quiet NaN: PASS +fcvt.w.s, quiet -NaN: PASS +fcvt.w.s, signaling NaN: PASS +fcvt.wu.s, truncate positive: PASS +fcvt.wu.s, truncate negative: PASS +fcvt.wu.s, 0.0: PASS +fcvt.wu.s, -0.0: PASS +fcvt.wu.s, overflow: PASS +fcvt.wu.s, underflow: PASS +fcvt.wu.s, infinity: PASS +fcvt.wu.s, -infinity: PASS +fcvt.wu.s, quiet NaN: PASS +fcvt.wu.s, quiet -NaN: PASS +fcvt.wu.s, signaling NaN: PASS +fmv.x.s, positive: PASS +fmv.x.s, negative: PASS +fmv.x.s, 0.0: PASS +fmv.x.s, -0.0: PASS +feq.s, equal: PASS +feq.s, not equal: PASS +feq.s, 0 == -0: PASS +feq.s, quiet NaN first: PASS +feq.s, quiet NaN second: PASS +feq.s, quiet NaN both: PASS +feq.s, signaling NaN first: PASS +feq.s, signaling NaN second: PASS +feq.s, signaling NaN both: PASS +flt.s, equal: PASS +flt.s, less: PASS +flt.s, greater: PASS +flt.s, quiet NaN first: PASS +flt.s, quiet NaN second: PASS +flt.s, quiet NaN both: PASS +flt.s, signaling NaN first: PASS +flt.s, signaling NaN second: PASS +flt.s, signaling NaN both: PASS +fle.s, equal: PASS +fle.s, less: PASS +fle.s, greater: PASS +fle.s, 0 == -0: PASS +fle.s, quiet NaN first: PASS +fle.s, quiet NaN second: PASS +fle.s, quiet NaN both: PASS +fle.s, signaling NaN first: PASS +fle.s, signaling NaN second: PASS +fle.s, signaling NaN both: PASS +fclass.s, -infinity: PASS +fclass.s, -normal: PASS +fclass.s, -subnormal: PASS +fclass.s, -0.0: PASS +fclass.s, 0.0: PASS +fclass.s, subnormal: PASS +fclass.s, normal: PASS +fclass.s, infinity: PASS +fclass.s, signaling NaN: PASS +fclass.s, quiet NaN: PASS +fcvt.s.w, 0: PASS +fcvt.s.w, negative: PASS +fcvt.s.w, truncate: PASS +fcvt.s.wu, 0: PASS +fcvt.s.wu: PASS +fcvt.s.wu, truncate: PASS +fmv.s.x: PASS +fmv.s.x, truncate: PASS +fsrm: PASS +fsflags: PASS +fscsr: PASS +restore initial round mode: PASS +fcvt.l.s, truncate positive: PASS +fcvt.l.s, truncate negative: PASS +fcvt.l.s, 0.0: PASS +fcvt.l.s, -0.0: PASS +fcvt.l.s, 32-bit overflow: PASS +fcvt.l.s, overflow: PASS +fcvt.l.s, underflow: PASS +fcvt.l.s, infinity: PASS +fcvt.l.s, -infinity: PASS +fcvt.l.s, quiet NaN: PASS +fcvt.l.s, quiet -NaN: PASS +fcvt.l.s, signaling NaN: PASS +fcvt.lu.s, truncate positive: PASS +fcvt.lu.s, truncate negative: PASS +fcvt.lu.s, 0.0: PASS +fcvt.lu.s, -0.0: PASS +fcvt.lu.s, 32-bit overflow: PASS +fcvt.lu.s, overflow: PASS +fcvt.lu.s, underflow: PASS +fcvt.lu.s, infinity: PASS +fcvt.lu.s, -infinity: PASS +fcvt.lu.s, quiet NaN: PASS +fcvt.lu.s, quiet -NaN: PASS +fcvt.lu.s, signaling NaN: PASS +fcvt.s.l, 0: PASS +fcvt.s.l, negative: PASS +fcvt.s.l, 32-bit truncate: PASS +fcvt.s.lu, 0: PASS +fcvt.s.lu: PASS +fcvt.s.lu, 32-bit truncate: PASS +Exiting @ tick 392627500 because target called exit() diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/simerr --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/simerr Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,3 @@ +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/simout --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/simout Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,226 @@ +Redirecting stdout to build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64d/simple-timing/simout +Redirecting stderr to build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64d/simple-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 2 2016 20:34:02 +gem5 started Nov 3 2016 19:09:12 +gem5 executing on ubuntu1604, pid 22244 +command line: /home/ar4jc/gem5/build/RISCV/gem5.debug -d build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64d/simple-timing -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64d/simple-timing + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +fld: PASS +fsd: PASS +fmadd.d: PASS +fmadd.d, quiet NaN: PASS +fmadd.d, signaling NaN: PASS +fmadd.d, infinity: PASS +fmadd.d, -infinity: PASS +fmsub.d: PASS +fmsub.d, quiet NaN: PASS +fmsub.d, signaling NaN: PASS +fmsub.d, infinity: PASS +fmsub.d, -infinity: PASS +fmsub.d, subtract infinity: PASS +fnmsub.d: PASS +fnmsub.d, quiet NaN: PASS +fnmsub.d, signaling NaN: PASS +fnmsub.d, infinity: PASS +fnmsub.d, -infinity: PASS +fnmsub.d, subtract infinity: PASS +fnmadd.d: PASS +fnmadd.d, quiet NaN: PASS +fnmadd.d, signaling NaN: PASS +fnmadd.d, infinity: PASS +fnmadd.d, -infinity: PASS +fadd.d: PASS +fadd.d, quiet NaN: PASS +fadd.d, signaling NaN: PASS +fadd.d, infinity: PASS +fadd.d, -infinity: PASS +fsub.d: PASS +fsub.d, quiet NaN: PASS +fsub.d, signaling NaN: PASS +fsub.d, infinity: PASS +fsub.d, -infinity: PASS +fsub.d, subtract infinity: PASS +fmul.d: PASS +fmul.d, quiet NaN: PASS +fmul.d, signaling NaN: PASS +fmul.d, infinity: PASS +fmul.d, -infinity: PASS +fmul.d, 0*infinity: PASS +fmul.d, overflow: PASS +fmul.d, underflow: PASS +fdiv.d: PASS +fdiv.d, quiet NaN: PASS +fdiv.d, signaling NaN: PASS +fdiv.d/0: PASS +fdiv.d/infinity: PASS +fdiv.d, infinity/infinity: PASS +fdiv.d, 0/0: PASS +fdiv.d, infinity/0: PASS +fdiv.d, 0/infinity: PASS +fdiv.d, underflow: PASS +fdiv.d, overflow: PASS +fsqrt.d: PASS +fsqrt.d, NaN: PASS +fsqrt.d, quiet NaN: PASS +fsqrt.d, signaling NaN: PASS +fsqrt.d, infinity: PASS +fsgnj.d, ++: PASS +fsgnj.d, +-: PASS +fsgnj.d, -+: PASS +fsgnj.d, --: PASS +fsgnj.d, quiet NaN: PASS +fsgnj.d, signaling NaN: PASS +fsgnj.d, inject NaN: PASS +fsgnj.d, inject -NaN: PASS +fsgnjn.d, ++: PASS +fsgnjn.d, +-: PASS +fsgnjn.d, -+: PASS +fsgnjn.d, --: PASS +fsgnjn.d, quiet NaN: PASS +fsgnjn.d, signaling NaN: PASS +fsgnjn.d, inject NaN: PASS +fsgnjn.d, inject NaN: PASS +fsgnjx.d, ++: PASS +fsgnjx.d, +-: PASS +fsgnjx.d, -+: PASS +fsgnjx.d, --: PASS +fsgnjx.d, quiet NaN: PASS +fsgnjx.d, signaling NaN: PASS +fsgnjx.d, inject NaN: PASS +fsgnjx.d, inject NaN: PASS +fmin.d: PASS +fmin.d, -infinity: PASS +fmin.d, infinity: PASS +fmin.d, quiet NaN first: PASS +fmin.d, quiet NaN second: PASS +fmin.d, quiet NaN both: PASS +fmin.d, signaling NaN first: PASS +fmin.d, signaling NaN second: PASS +fmin.d, signaling NaN both: PASS +fmax.d: PASS +fmax.d, -infinity: PASS +fmax.d, infinity: PASS +fmax.d, quiet NaN first: PASS +fmax.d, quiet NaN second: PASS +fmax.d, quiet NaN both: PASS +fmax.d, signaling NaN first: PASS +fmax.d, signaling NaN second: PASS +fmax.d, signaling NaN both: PASS +fcvt.s.d: PASS +fcvt.s.d, quiet NaN: PASS +fcvt.s.d, signaling NaN: PASS +fcvt.s.d, infinity: PASS +fcvt.s.d, overflow: PASS +fcvt.s.d, underflow: PASS +fcvt.d.s: PASS +fcvt.d.s, quiet NaN: PASS +fcvt.d.s, signaling NaN: PASS +fcvt.d.s, infinity: PASS +feq.d, equal: PASS +feq.d, not equal: PASS +feq.d, 0 == -0: PASS +feq.d, quiet NaN first: PASS +feq.d, quiet NaN second: PASS +feq.d, quiet NaN both: PASS +feq.d, signaling NaN first: PASS +feq.d, signaling NaN second: PASS +feq.d, signaling NaN both: PASS +flt.d, equal: PASS +flt.d, less: PASS +flt.d, greater: PASS +flt.d, quiet NaN first: PASS +flt.d, quiet NaN second: PASS +flt.d, quiet NaN both: PASS +flt.d, signaling NaN first: PASS +flt.d, signaling NaN second: PASS +flt.d, signaling NaN both: PASS +fle.d, equal: PASS +fle.d, less: PASS +fle.d, greater: PASS +fle.d, 0 == -0: PASS +fle.d, quiet NaN first: PASS +fle.d, quiet NaN second: PASS +fle.d, quiet NaN both: PASS +fle.d, signaling NaN first: PASS +fle.d, signaling NaN second: PASS +fle.d, signaling NaN both: PASS +fclass.d, -infinity: PASS +fclass.d, -normal: PASS +fclass.d, -subnormal: PASS +fclass.d, -0.0: PASS +fclass.d, 0.0: PASS +fclass.d, subnormal: PASS +fclass.d, normal: PASS +fclass.d, infinity: PASS +fclass.d, signaling NaN: PASS +fclass.s, quiet NaN: PASS +fcvt.w.d, truncate positive: PASS +fcvt.w.d, truncate negative: PASS +fcvt.w.d, 0.0: PASS +fcvt.w.d, -0.0: PASS +fcvt.w.d, overflow: PASS +fcvt.w.d, underflow: PASS +fcvt.w.d, infinity: PASS +fcvt.w.d, -infinity: PASS +fcvt.w.d, quiet NaN: PASS +fcvt.w.d, quiet -NaN: PASS +fcvt.w.d, signaling NaN: PASS +fcvt.wu.d, truncate positive: PASS +fcvt.wu.d, truncate negative: PASS +fcvt.wu.d, 0.0: PASS +fcvt.wu.d, -0.0: PASS +fcvt.wu.d, overflow: PASS +fcvt.wu.d, underflow: PASS +fcvt.wu.d, infinity: PASS +fcvt.wu.d, -infinity: PASS +fcvt.wu.d, quiet NaN: PASS +fcvt.wu.d, quiet -NaN: PASS +fcvt.wu.d, signaling NaN: PASS +fcvt.d.w, 0: PASS +fcvt.d.w, negative: PASS +fcvt.d.w, truncate: PASS +fcvt.d.wu, 0: PASS +fcvt.d.wu: PASS +fcvt.d.wu, truncate: PASS +fcvt.l.d, truncate positive: PASS +fcvt.l.d, truncate negative: PASS +fcvt.l.d, 0.0: PASS +fcvt.l.d, -0.0: PASS +fcvt.l.d, 32-bit overflow: PASS +fcvt.l.d, overflow: PASS +fcvt.l.d, underflow: PASS +fcvt.l.d, infinity: PASS +fcvt.l.d, -infinity: PASS +fcvt.l.d, quiet NaN: PASS +fcvt.l.d, quiet -NaN: PASS +fcvt.l.d, signaling NaN: PASS +fcvt.lu.d, truncate positive: PASS +fcvt.lu.d, truncate negative: PASS +fcvt.lu.d, 0.0: PASS +fcvt.lu.d, -0.0: PASS +fcvt.lu.d, 32-bit overflow: PASS +fcvt.lu.d, overflow: PASS +fcvt.lu.d, underflow: PASS +fcvt.lu.d, infinity: PASS +fcvt.lu.d, -infinity: PASS +fcvt.lu.d, quiet NaN: PASS +fcvt.lu.d, quiet -NaN: PASS +fcvt.lu.d, signaling NaN: PASS +fmv.x.d, positive: PASS +fmv.x.d, negative: PASS +fmv.x.d, 0.0: PASS +fmv.x.d, -0.0: PASS +fcvt.d.l, 0: PASS +fcvt.d.l, negative: PASS +fcvt.d.l, 32-bit truncate: PASS +fcvt.d.lu, 0: PASS +fcvt.d.lu: PASS +fcvt.d.lu, 32-bit truncate: PASS +fmv.d.x: PASS +Exiting @ tick 627108500 because target called exit() diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/stats.txt --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/stats.txt Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,521 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000627 # Number of seconds simulated +sim_ticks 627108500 # Number of ticks simulated +final_tick 627108500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 40790 # Simulator instruction rate (inst/s) +host_op_rate 40790 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 66378861 # Simulator tick rate (ticks/s) +host_mem_usage 276384 # Number of bytes of host memory used +host_seconds 9.44 # Real time elapsed on the host +sim_insts 385362 # Number of instructions simulated +sim_ops 385362 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 627108500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 68992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 21376 # Number of bytes read from this memory +system.physmem.bytes_read::total 90368 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 68992 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 68992 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 1078 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 334 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1412 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 110016049 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 34086605 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 144102655 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 110016049 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 110016049 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 110016049 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 34086605 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 144102655 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 627108500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 221 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 627108500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 1254217 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 385362 # Number of instructions committed +system.cpu.committedOps 385362 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 385160 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 1217 # Number of float alu accesses +system.cpu.num_func_calls 27940 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 57164 # number of instructions that are conditional controls +system.cpu.num_int_insts 385160 # number of integer instructions +system.cpu.num_fp_insts 1217 # number of float instructions +system.cpu.num_int_register_reads 507652 # number of times the integer registers were read +system.cpu.num_int_register_writes 264394 # number of times the integer registers were written +system.cpu.num_fp_register_reads 976 # number of times the floating registers were read +system.cpu.num_fp_register_writes 800 # number of times the floating registers were written +system.cpu.num_mem_refs 153968 # number of memory refs +system.cpu.num_load_insts 90486 # Number of load instructions +system.cpu.num_store_insts 63482 # Number of store instructions +system.cpu.num_idle_cycles -0 # Number of idle cycles +system.cpu.num_busy_cycles 1254217 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction -0 # Percentage of idle cycles +system.cpu.Branches 85104 # Number of branches fetched +system.cpu.op_class::No_OpClass 221 0.05% 0.05% # Class of executed instruction +system.cpu.op_class::IntAlu 230282 59.72% 59.78% # Class of executed instruction +system.cpu.op_class::IntMult 636 0.16% 59.94% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 59.94% # Class of executed instruction +system.cpu.op_class::FloatAdd 133 0.03% 59.97% # Class of executed instruction +system.cpu.op_class::FloatCmp 170 0.04% 60.02% # Class of executed instruction +system.cpu.op_class::FloatCvt 128 0.03% 60.05% # Class of executed instruction +system.cpu.op_class::FloatMult 30 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::FloatDiv 11 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::FloatSqrt 5 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::MemRead 89915 23.31% 83.38% # Class of executed instruction +system.cpu.op_class::MemWrite 63313 16.42% 99.80% # Class of executed instruction +system.cpu.op_class::FloatMemRead 571 0.14% 99.95% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 169 0.04% 99.99% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 99.99% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 99.99% # Class of executed instruction +system.cpu.op_class::total 385584 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 627108500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 272.423272 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 153633 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 334 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 459.979041 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 272.423272 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.066509 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.066509 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 334 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 315 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.081542 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 308268 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 308268 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 627108500 # Cumulative time (in ticks) in various power states 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+system.cpu.dcache.demand_misses::total 334 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 334 # number of overall misses +system.cpu.dcache.overall_misses::total 334 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8379000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8379000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 12663000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 12663000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 21042000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 21042000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 21042000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 21042000 # number of overall miss cycles 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ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60500.927643 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60500.927643 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60500.927643 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60500.708215 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60500.927643 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60500.708215 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 201 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 201 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1078 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1078 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 133 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 133 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1078 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 334 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1412 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1078 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 334 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1412 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10150500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10150500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 54440000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 54440000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6716500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6716500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 54440000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16867000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 71307000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 54440000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16867000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 71307000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.999073 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.999073 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.999073 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.999292 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.999073 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.999292 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50500.927643 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50500.927643 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50500.927643 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.708215 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50500.927643 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.708215 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1457 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 44 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 627108500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 1212 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 44 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 201 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 201 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1079 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 133 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2202 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 668 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2870 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 71872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21376 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 93248 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 1413 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev -0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1413 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1413 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 772500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1618500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 501000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 1412 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 627108500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1211 # Transaction distribution +system.membus.trans_dist::ReadExReq 201 # Transaction distribution +system.membus.trans_dist::ReadExResp 201 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1211 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2824 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2824 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 90368 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 90368 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1412 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev -0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1412 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1412 # Request fanout histogram +system.membus.reqLayer0.occupancy 1413000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 7060000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.1 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/config.ini --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/config.ini Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,374 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=TimingSimpleCPU +children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +hit_latency=2 +is_read_only=false +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=262144 + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.icache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +hit_latency=2 +is_read_only=true +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tags=system.cpu.icache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=131072 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.l2cache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +hit_latency=20 +is_read_only=false +max_miss_count=0 +mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +hit_latency=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=2097152 + +[system.cpu.toL2Bus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=0 +frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null +response_latency=1 +snoop_filter=system.cpu.toL2Bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64d/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +eventq_index=0 +in_addr_map=true +kvm_map=true +latency=30000 +latency_var=0 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +range=0:134217727:0:0:0:0 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/config.json --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing/config.json Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,502 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.l2cache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "physmem": { + "range": "0:134217727:0:0:0:0", + "latency": 30000, + "name": "physmem", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "kvm_map": true, + "clk_domain": "system.clk_domain", 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"cxx_class": "RiscvISA::TLB", + "path": "system.cpu.itb", + "type": "RiscvTLB", + "size": 64 + }, + "system": "system", + "icache": { + "cpu_side": { + "peer": "system.cpu.icache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 131072, + "tags": { + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.icache.tags", + "hit_latency": 2, + "block_size": 64, + "type": "LRU", + "size": 131072 + }, + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[0]", + "role": "MASTER" + }, + "type": "Cache", + "writeback_clean": true, + "p_state_clk_gate_min": 1000, + "hit_latency": 2, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": true, + "prefetch_on_access": false, + "path": "system.cpu.icache", + "mshrs": 4, + "name": "icache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "TimingSimpleCPU", + "max_loads_all_threads": 0, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "cpu_id": 0, + "checker": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "toL2Bus": { + "point_of_coherency": false, + "system": "system", + "response_latency": 1, + "cxx_class": "CoherentXBar", + "forward_latency": 0, + "clk_domain": "system.cpu_clk_domain", + "width": 32, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.cpu.l2cache.cpu_side" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 1, + "slave": { + "peer": [ + "system.cpu.icache.mem_side", + "system.cpu.dcache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.cpu.toL2Bus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 0 + }, + "power_model": null, + "path": "system.cpu.toL2Bus", + "snoop_response_latency": 1, + "name": "toL2Bus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "do_quiesce": true, + "type": "TimingSimpleCPU", + "profile": 0, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "p_state_clk_gate_min": 1000, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "role": "MASTER" + }, + "socket_id": 0, + "power_model": null, + "max_insts_all_threads": 0, + "l2cache": { + "cpu_side": { + "peer": "system.cpu.toL2Bus.master[0]", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 20, + "cxx_class": "Cache", + "size": 2097152, + "tags": { + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 8, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.l2cache.tags", + "hit_latency": 20, + "block_size": 64, + "type": "LRU", + "size": 2097152 + }, + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.membus.slave[1]", + "role": "MASTER" + }, + "type": "Cache", + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "hit_latency": 20, + "tgts_per_mshr": 12, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.l2cache", + "mshrs": 20, + "name": "l2cache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 8 + }, + "path": "system.cpu", + "max_loads_any_thread": 0, + "switched_out": false, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64d/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "progress_interval": 0, + "branchPred": null, + "dcache": { + "cpu_side": { + "peer": "system.cpu.dcache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 262144, + "tags": { + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.dcache.tags", + "hit_latency": 2, + "block_size": 64, + "type": "LRU", + "size": 262144 + }, + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[1]", + "role": "MASTER" + }, + "type": "Cache", + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "hit_latency": 2, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.dcache", + "mshrs": 4, + "name": "dcache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/simout --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/simout Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,226 @@ +Redirecting stdout to build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64d/simple-timing-ruby/simout +Redirecting stderr to build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64d/simple-timing-ruby/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 2 2016 20:34:02 +gem5 started Nov 3 2016 19:09:23 +gem5 executing on ubuntu1604, pid 22245 +command line: /home/ar4jc/gem5/build/RISCV/gem5.debug -d build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64d/simple-timing-ruby -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64d/simple-timing-ruby + +Global frequency set at 1000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +fld: PASS +fsd: PASS +fmadd.d: PASS +fmadd.d, quiet NaN: PASS +fmadd.d, signaling NaN: PASS +fmadd.d, infinity: PASS +fmadd.d, -infinity: PASS +fmsub.d: PASS +fmsub.d, quiet NaN: PASS +fmsub.d, signaling NaN: PASS +fmsub.d, infinity: PASS +fmsub.d, -infinity: PASS +fmsub.d, subtract infinity: PASS +fnmsub.d: PASS +fnmsub.d, quiet NaN: PASS +fnmsub.d, signaling NaN: PASS +fnmsub.d, infinity: PASS +fnmsub.d, -infinity: PASS +fnmsub.d, subtract infinity: PASS +fnmadd.d: PASS +fnmadd.d, quiet NaN: PASS +fnmadd.d, signaling NaN: PASS +fnmadd.d, infinity: PASS +fnmadd.d, -infinity: PASS +fadd.d: PASS +fadd.d, quiet NaN: PASS +fadd.d, signaling NaN: PASS +fadd.d, infinity: PASS +fadd.d, -infinity: PASS +fsub.d: PASS +fsub.d, quiet NaN: PASS +fsub.d, signaling NaN: PASS +fsub.d, infinity: PASS +fsub.d, -infinity: PASS +fsub.d, subtract infinity: PASS +fmul.d: PASS +fmul.d, quiet NaN: PASS +fmul.d, signaling NaN: PASS +fmul.d, infinity: PASS +fmul.d, -infinity: PASS +fmul.d, 0*infinity: PASS +fmul.d, overflow: PASS +fmul.d, underflow: PASS +fdiv.d: PASS +fdiv.d, quiet NaN: PASS +fdiv.d, signaling NaN: PASS +fdiv.d/0: PASS +fdiv.d/infinity: PASS +fdiv.d, infinity/infinity: PASS +fdiv.d, 0/0: PASS +fdiv.d, infinity/0: PASS +fdiv.d, 0/infinity: PASS +fdiv.d, underflow: PASS +fdiv.d, overflow: PASS +fsqrt.d: PASS +fsqrt.d, NaN: PASS +fsqrt.d, quiet NaN: PASS +fsqrt.d, signaling NaN: PASS +fsqrt.d, infinity: PASS +fsgnj.d, ++: PASS +fsgnj.d, +-: PASS +fsgnj.d, -+: PASS +fsgnj.d, --: PASS +fsgnj.d, quiet NaN: PASS +fsgnj.d, signaling NaN: PASS +fsgnj.d, inject NaN: PASS +fsgnj.d, inject -NaN: PASS +fsgnjn.d, ++: PASS +fsgnjn.d, +-: PASS +fsgnjn.d, -+: PASS +fsgnjn.d, --: PASS +fsgnjn.d, quiet NaN: PASS +fsgnjn.d, signaling NaN: PASS +fsgnjn.d, inject NaN: PASS +fsgnjn.d, inject NaN: PASS +fsgnjx.d, ++: PASS +fsgnjx.d, +-: PASS +fsgnjx.d, -+: PASS +fsgnjx.d, --: PASS +fsgnjx.d, quiet NaN: PASS +fsgnjx.d, signaling NaN: PASS +fsgnjx.d, inject NaN: PASS +fsgnjx.d, inject NaN: PASS +fmin.d: PASS +fmin.d, -infinity: PASS +fmin.d, infinity: PASS +fmin.d, quiet NaN first: PASS +fmin.d, quiet NaN second: PASS +fmin.d, quiet NaN both: PASS +fmin.d, signaling NaN first: PASS +fmin.d, signaling NaN second: PASS +fmin.d, signaling NaN both: PASS +fmax.d: PASS +fmax.d, -infinity: PASS +fmax.d, infinity: PASS +fmax.d, quiet NaN first: PASS +fmax.d, quiet NaN second: PASS +fmax.d, quiet NaN both: PASS +fmax.d, signaling NaN first: PASS +fmax.d, signaling NaN second: PASS +fmax.d, signaling NaN both: PASS +fcvt.s.d: PASS +fcvt.s.d, quiet NaN: PASS +fcvt.s.d, signaling NaN: PASS +fcvt.s.d, infinity: PASS +fcvt.s.d, overflow: PASS +fcvt.s.d, underflow: PASS +fcvt.d.s: PASS +fcvt.d.s, quiet NaN: PASS +fcvt.d.s, signaling NaN: PASS +fcvt.d.s, infinity: PASS +feq.d, equal: PASS +feq.d, not equal: PASS +feq.d, 0 == -0: PASS +feq.d, quiet NaN first: PASS +feq.d, quiet NaN second: PASS +feq.d, quiet NaN both: PASS +feq.d, signaling NaN first: PASS +feq.d, signaling NaN second: PASS +feq.d, signaling NaN both: PASS +flt.d, equal: PASS +flt.d, less: PASS +flt.d, greater: PASS +flt.d, quiet NaN first: PASS +flt.d, quiet NaN second: PASS +flt.d, quiet NaN both: PASS +flt.d, signaling NaN first: PASS +flt.d, signaling NaN second: PASS +flt.d, signaling NaN both: PASS +fle.d, equal: PASS +fle.d, less: PASS +fle.d, greater: PASS +fle.d, 0 == -0: PASS +fle.d, quiet NaN first: PASS +fle.d, quiet NaN second: PASS +fle.d, quiet NaN both: PASS +fle.d, signaling NaN first: PASS +fle.d, signaling NaN second: PASS +fle.d, signaling NaN both: PASS +fclass.d, -infinity: PASS +fclass.d, -normal: PASS +fclass.d, -subnormal: PASS +fclass.d, -0.0: PASS +fclass.d, 0.0: PASS +fclass.d, subnormal: PASS +fclass.d, normal: PASS +fclass.d, infinity: PASS +fclass.d, signaling NaN: PASS +fclass.s, quiet NaN: PASS +fcvt.w.d, truncate positive: PASS +fcvt.w.d, truncate negative: PASS +fcvt.w.d, 0.0: PASS +fcvt.w.d, -0.0: PASS +fcvt.w.d, overflow: PASS +fcvt.w.d, underflow: PASS +fcvt.w.d, infinity: PASS +fcvt.w.d, -infinity: PASS +fcvt.w.d, quiet NaN: PASS +fcvt.w.d, quiet -NaN: PASS +fcvt.w.d, signaling NaN: PASS +fcvt.wu.d, truncate positive: PASS +fcvt.wu.d, truncate negative: PASS +fcvt.wu.d, 0.0: PASS +fcvt.wu.d, -0.0: PASS +fcvt.wu.d, overflow: PASS +fcvt.wu.d, underflow: PASS +fcvt.wu.d, infinity: PASS +fcvt.wu.d, -infinity: PASS +fcvt.wu.d, quiet NaN: PASS +fcvt.wu.d, quiet -NaN: PASS +fcvt.wu.d, signaling NaN: PASS +fcvt.d.w, 0: PASS +fcvt.d.w, negative: PASS +fcvt.d.w, truncate: PASS +fcvt.d.wu, 0: PASS +fcvt.d.wu: PASS +fcvt.d.wu, truncate: PASS +fcvt.l.d, truncate positive: PASS +fcvt.l.d, truncate negative: PASS +fcvt.l.d, 0.0: PASS +fcvt.l.d, -0.0: PASS +fcvt.l.d, 32-bit overflow: PASS +fcvt.l.d, overflow: PASS +fcvt.l.d, underflow: PASS +fcvt.l.d, infinity: PASS +fcvt.l.d, -infinity: PASS +fcvt.l.d, quiet NaN: PASS +fcvt.l.d, quiet -NaN: PASS +fcvt.l.d, signaling NaN: PASS +fcvt.lu.d, truncate positive: PASS +fcvt.lu.d, truncate negative: PASS +fcvt.lu.d, 0.0: PASS +fcvt.lu.d, -0.0: PASS +fcvt.lu.d, 32-bit overflow: PASS +fcvt.lu.d, overflow: PASS +fcvt.lu.d, underflow: PASS +fcvt.lu.d, infinity: PASS +fcvt.lu.d, -infinity: PASS +fcvt.lu.d, quiet NaN: PASS +fcvt.lu.d, quiet -NaN: PASS +fcvt.lu.d, signaling NaN: PASS +fmv.x.d, positive: PASS +fmv.x.d, negative: PASS +fmv.x.d, 0.0: PASS +fmv.x.d, -0.0: PASS +fcvt.d.l, 0: PASS +fcvt.d.l, negative: PASS +fcvt.d.l, 32-bit truncate: PASS +fcvt.d.lu, 0: PASS +fcvt.d.lu: PASS +fcvt.d.lu, 32-bit truncate: PASS +fmv.d.x: PASS +Exiting @ tick 8442878 because target called exit() diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/stats.txt --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/stats.txt Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,644 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.008442 # Number of seconds simulated +sim_ticks 8442878 # Number of ticks simulated +final_tick 8442878 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000 # Frequency of simulated ticks +host_inst_rate 5463 # Simulator instruction rate (inst/s) +host_op_rate 5463 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 119690 # Simulator tick rate (ticks/s) +host_mem_usage 442780 # Number of bytes of host memory used +host_seconds 70.53 # Real time elapsed on the host +sim_insts 385362 # Number of instructions simulated +sim_ops 385362 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1 # Clock period in ticks +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 8442878 # Cumulative time (in ticks) in various power states +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 8298304 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 8298304 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 8298048 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 8298048 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 129661 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 129661 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 129657 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 129657 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 982876218 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 982876218 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 982845896 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 982845896 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 1965722115 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1965722115 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 129661 # Number of read requests accepted +system.mem_ctrls.writeReqs 129657 # Number of write requests accepted +system.mem_ctrls.readBursts 129661 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 129657 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 4423808 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 3874496 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 4625408 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 8298304 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 8298048 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 60539 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 57353 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 323 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 1443 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 2294 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 6295 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 6954 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 458 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 10094 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 167 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 2712 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 14230 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 9482 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 1400 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 312 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 2122 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 10807 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 29 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 325 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 1494 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 2325 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 6604 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 7208 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 460 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 11602 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 167 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 2795 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 14585 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 9772 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 1399 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 335 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 2148 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 11022 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 31 # Per bank write bursts +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.totGap 8442808 # Total gap between requests +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 129661 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 129657 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 69122 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 381 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 440 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 3725 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 4490 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 4517 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 4662 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 4884 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 4666 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 4459 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 4455 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 4453 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 4452 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 4451 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 4451 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 4451 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 4451 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 4451 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 4450 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 23882 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 378.902939 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 239.668306 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 341.939990 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 5321 22.28% 22.28% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 6688 28.00% 50.28% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 2609 10.92% 61.20% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 1768 7.40% 68.61% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 1433 6.00% 74.61% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 1151 4.81% 79.43% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 912 3.81% 83.25% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 847 3.54% 86.79% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 3153 13.20% 99.99% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 23882 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 4450 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 15.529213 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 15.481471 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 1.241623 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::12-13 134 3.01% 3.01% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::14-15 2130 47.86% 50.87% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-17 1941 43.61% 94.49% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::18-19 236 5.30% 99.79% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::20-21 8 0.17% 99.97% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::36-37 1 0.02% 99.99% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 4450 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 4450 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.240898 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.224355 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 0.767360 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 4015 90.22% 90.22% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 45 1.01% 91.23% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 162 3.64% 94.87% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 209 4.69% 99.57% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::20 19 0.42% 99.99% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 4450 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 1339763 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 2653081 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 345610 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 19.38 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 38.38 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 523.96 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 547.84 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 982.87 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 982.84 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 8.37 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 4.09 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 4.28 # Data bus utilization in percentage for writes +system.mem_ctrls.avgRdQLen 0.99 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 25.85 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 51465 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 66044 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 74.45 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 91.34 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 32.55 # Average gap between requests +system.mem_ctrls.pageHitRate 83.08 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 72242520 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 39084360 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 320191872 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 252105120 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 665655120 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 872801328 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 14793600 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.actPowerDownEnergy 2800042008 # Energy for active power-down per rank (pJ) +system.mem_ctrls_0.prePowerDownEnergy 108372864 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_0.selfRefreshEnergy 20654160 # Energy for self refresh per rank (pJ) +system.mem_ctrls_0.totalEnergy 5165942952 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 611.869904 # Core power per rank (mW) +system.mem_ctrls_0.totalIdleTime 6490280 # Total Idle time Per DRAM Rank +system.mem_ctrls_0.memoryStateTime::IDLE 7971 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 281628 # Time in different power states +system.mem_ctrls_0.memoryStateTime::SREF 67651 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 282221 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 1662964 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 6140443 # Time in different power states +system.mem_ctrls_1.actEnergy 98296380 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 53195688 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 469457856 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 351510624 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 649059840 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 997872096 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 17535360 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.actPowerDownEnergy 2664643752 # Energy for active power-down per rank (pJ) +system.mem_ctrls_1.prePowerDownEnergy 41677056 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_1.selfRefreshEnergy 64442160 # Energy for self refresh per rank (pJ) +system.mem_ctrls_1.totalEnergy 5407690812 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 640.491265 # Core power per rank (mW) +system.mem_ctrls_1.totalIdleTime 6209055 # Total Idle time Per DRAM Rank +system.mem_ctrls_1.memoryStateTime::IDLE 14747 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 274424 # Time in different power states +system.mem_ctrls_1.memoryStateTime::SREF 257004 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 108534 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 1944652 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 5843517 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 8442878 # Cumulative time (in ticks) in various power states +system.cpu.clk_domain.clock 1 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 221 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 8442878 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 8442878 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 385362 # Number of instructions committed +system.cpu.committedOps 385362 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 385160 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 1217 # Number of float alu accesses +system.cpu.num_func_calls 27940 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 57164 # number of instructions that are conditional controls +system.cpu.num_int_insts 385160 # number of integer instructions +system.cpu.num_fp_insts 1217 # number of float instructions +system.cpu.num_int_register_reads 507652 # number of times the integer registers were read +system.cpu.num_int_register_writes 264394 # number of times the integer registers were written +system.cpu.num_fp_register_reads 976 # number of times the floating registers were read +system.cpu.num_fp_register_writes 800 # number of times the floating registers were written +system.cpu.num_mem_refs 153968 # number of memory refs +system.cpu.num_load_insts 90486 # Number of load instructions +system.cpu.num_store_insts 63482 # Number of store instructions +system.cpu.num_idle_cycles -0 # Number of idle cycles +system.cpu.num_busy_cycles 8442878 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction -0 # Percentage of idle cycles +system.cpu.Branches 85104 # Number of branches fetched +system.cpu.op_class::No_OpClass 221 0.05% 0.05% # Class of executed instruction +system.cpu.op_class::IntAlu 230282 59.72% 59.78% # Class of executed instruction +system.cpu.op_class::IntMult 636 0.16% 59.94% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 59.94% # Class of executed instruction +system.cpu.op_class::FloatAdd 133 0.03% 59.97% # Class of executed instruction +system.cpu.op_class::FloatCmp 170 0.04% 60.02% # Class of executed instruction +system.cpu.op_class::FloatCvt 128 0.03% 60.05% # Class of executed instruction +system.cpu.op_class::FloatMult 30 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::FloatDiv 11 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::FloatSqrt 5 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::MemRead 89915 23.31% 83.38% # Class of executed instruction +system.cpu.op_class::MemWrite 63313 16.42% 99.80% # Class of executed instruction +system.cpu.op_class::FloatMemRead 571 0.14% 99.95% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 169 0.04% 99.99% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 99.99% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 99.99% # Class of executed instruction +system.cpu.op_class::total 385584 # Class of executed instruction +system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.pwrStateResidencyTicks::UNDEFINED 8442878 # Cumulative time (in ticks) in various power states +system.ruby.delayHist::bucket_size 1 # delay histogram for all message +system.ruby.delayHist::max_bucket 9 # delay histogram for all message +system.ruby.delayHist::samples 259318 # delay histogram for all message +system.ruby.delayHist | 259318 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 259318 # delay histogram for all message +system.ruby.outstanding_req_hist_seqr::bucket_size 1 +system.ruby.outstanding_req_hist_seqr::max_bucket 9 +system.ruby.outstanding_req_hist_seqr::samples 539552 +system.ruby.outstanding_req_hist_seqr::mean 1 +system.ruby.outstanding_req_hist_seqr::gmean 1 +system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 539552 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 539552 +system.ruby.latency_hist_seqr::bucket_size 64 +system.ruby.latency_hist_seqr::max_bucket 639 +system.ruby.latency_hist_seqr::samples 539551 +system.ruby.latency_hist_seqr::mean 14.647970 +system.ruby.latency_hist_seqr::gmean 2.569011 +system.ruby.latency_hist_seqr::stdev 30.345318 +system.ruby.latency_hist_seqr | 473100 87.68% 87.68% | 61546 11.40% 99.09% | 3308 0.61% 99.70% | 574 0.10% 99.81% | 568 0.10% 99.91% | 404 0.07% 99.99% | 32 0.00% 99.99% | 7 0.00% 99.99% | 0 0.00% 99.99% | 12 0.00% 99.99% +system.ruby.latency_hist_seqr::total 539551 +system.ruby.hit_latency_hist_seqr::bucket_size 1 +system.ruby.hit_latency_hist_seqr::max_bucket 9 +system.ruby.hit_latency_hist_seqr::samples 409890 +system.ruby.hit_latency_hist_seqr::mean 1 +system.ruby.hit_latency_hist_seqr::gmean 1 +system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 409890 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 409890 +system.ruby.miss_latency_hist_seqr::bucket_size 64 +system.ruby.miss_latency_hist_seqr::max_bucket 639 +system.ruby.miss_latency_hist_seqr::samples 129661 +system.ruby.miss_latency_hist_seqr::mean 57.792528 +system.ruby.miss_latency_hist_seqr::gmean 50.714986 +system.ruby.miss_latency_hist_seqr::stdev 37.169176 +system.ruby.miss_latency_hist_seqr | 63210 48.75% 48.75% | 61546 47.46% 96.21% | 3308 2.55% 98.76% | 574 0.44% 99.21% | 568 0.43% 99.64% | 404 0.31% 99.96% | 32 0.02% 99.98% | 7 0.00% 99.99% | 0 0.00% 99.99% | 12 0.00% 99.99% +system.ruby.miss_latency_hist_seqr::total 129661 +system.ruby.Directory.incomplete_times_seqr 129660 +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 8442878 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.cacheMemory.demand_hits 409890 # Number of cache demand hits +system.ruby.l1_cntrl0.cacheMemory.demand_misses 129661 # Number of cache demand misses +system.ruby.l1_cntrl0.cacheMemory.demand_accesses 539551 # Number of cache demand accesses +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 8442878 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 8442878 # Cumulative time (in ticks) in various power states +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 8442878 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.percent_links_utilized 7.678602 +system.ruby.network.routers0.msg_count.Control::2 129661 +system.ruby.network.routers0.msg_count.Data::2 129657 +system.ruby.network.routers0.msg_count.Response_Data::4 129661 +system.ruby.network.routers0.msg_count.Writeback_Control::3 129657 +system.ruby.network.routers0.msg_bytes.Control::2 1037288 +system.ruby.network.routers0.msg_bytes.Data::2 9335304 +system.ruby.network.routers0.msg_bytes.Response_Data::4 9335592 +system.ruby.network.routers0.msg_bytes.Writeback_Control::3 1037256 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 8442878 # Cumulative time (in ticks) in various power states +system.ruby.network.routers1.percent_links_utilized 7.678602 +system.ruby.network.routers1.msg_count.Control::2 129661 +system.ruby.network.routers1.msg_count.Data::2 129657 +system.ruby.network.routers1.msg_count.Response_Data::4 129661 +system.ruby.network.routers1.msg_count.Writeback_Control::3 129657 +system.ruby.network.routers1.msg_bytes.Control::2 1037288 +system.ruby.network.routers1.msg_bytes.Data::2 9335304 +system.ruby.network.routers1.msg_bytes.Response_Data::4 9335592 +system.ruby.network.routers1.msg_bytes.Writeback_Control::3 1037256 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 8442878 # Cumulative time (in ticks) in various power states +system.ruby.network.routers2.percent_links_utilized 7.678602 +system.ruby.network.routers2.msg_count.Control::2 129661 +system.ruby.network.routers2.msg_count.Data::2 129657 +system.ruby.network.routers2.msg_count.Response_Data::4 129661 +system.ruby.network.routers2.msg_count.Writeback_Control::3 129657 +system.ruby.network.routers2.msg_bytes.Control::2 1037288 +system.ruby.network.routers2.msg_bytes.Data::2 9335304 +system.ruby.network.routers2.msg_bytes.Response_Data::4 9335592 +system.ruby.network.routers2.msg_bytes.Writeback_Control::3 1037256 +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 8442878 # Cumulative time (in ticks) in various power states +system.ruby.network.msg_count.Control 388983 +system.ruby.network.msg_count.Data 388971 +system.ruby.network.msg_count.Response_Data 388983 +system.ruby.network.msg_count.Writeback_Control 388971 +system.ruby.network.msg_byte.Control 3111864 +system.ruby.network.msg_byte.Data 28005912 +system.ruby.network.msg_byte.Response_Data 28006776 +system.ruby.network.msg_byte.Writeback_Control 3111768 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 8442878 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.throttle0.link_utilization 7.678696 +system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 129661 +system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 129657 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 9335592 +system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 1037256 +system.ruby.network.routers0.throttle1.link_utilization 7.678507 +system.ruby.network.routers0.throttle1.msg_count.Control::2 129661 +system.ruby.network.routers0.throttle1.msg_count.Data::2 129657 +system.ruby.network.routers0.throttle1.msg_bytes.Control::2 1037288 +system.ruby.network.routers0.throttle1.msg_bytes.Data::2 9335304 +system.ruby.network.routers1.throttle0.link_utilization 7.678507 +system.ruby.network.routers1.throttle0.msg_count.Control::2 129661 +system.ruby.network.routers1.throttle0.msg_count.Data::2 129657 +system.ruby.network.routers1.throttle0.msg_bytes.Control::2 1037288 +system.ruby.network.routers1.throttle0.msg_bytes.Data::2 9335304 +system.ruby.network.routers1.throttle1.link_utilization 7.678696 +system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 129661 +system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 129657 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 9335592 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 1037256 +system.ruby.network.routers2.throttle0.link_utilization 7.678696 +system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 129661 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 129657 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 9335592 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 1037256 +system.ruby.network.routers2.throttle1.link_utilization 7.678507 +system.ruby.network.routers2.throttle1.msg_count.Control::2 129661 +system.ruby.network.routers2.throttle1.msg_count.Data::2 129657 +system.ruby.network.routers2.throttle1.msg_bytes.Control::2 1037288 +system.ruby.network.routers2.throttle1.msg_bytes.Data::2 9335304 +system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::samples 129661 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1 | 129661 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::total 129661 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::samples 129657 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2 | 129657 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::total 129657 # delay histogram for vnet_2 +system.ruby.LD.latency_hist_seqr::bucket_size 64 +system.ruby.LD.latency_hist_seqr::max_bucket 639 +system.ruby.LD.latency_hist_seqr::samples 90486 +system.ruby.LD.latency_hist_seqr::mean 29.273788 +system.ruby.LD.latency_hist_seqr::gmean 8.454153 +system.ruby.LD.latency_hist_seqr::stdev 35.485603 +system.ruby.LD.latency_hist_seqr | 71478 78.99% 78.99% | 17660 19.51% 98.51% | 896 0.99% 99.50% | 167 0.18% 99.68% | 158 0.17% 99.85% | 119 0.13% 99.99% | 5 0.00% 99.99% | 2 0.00% 99.99% | 0 0.00% 99.99% | 1 0.00% 99.99% +system.ruby.LD.latency_hist_seqr::total 90486 +system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 +system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 +system.ruby.LD.hit_latency_hist_seqr::samples 39847 +system.ruby.LD.hit_latency_hist_seqr::mean 1 +system.ruby.LD.hit_latency_hist_seqr::gmean 1 +system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 39847 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::total 39847 +system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 +system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 +system.ruby.LD.miss_latency_hist_seqr::samples 50639 +system.ruby.LD.miss_latency_hist_seqr::mean 51.521969 +system.ruby.LD.miss_latency_hist_seqr::gmean 45.348870 +system.ruby.LD.miss_latency_hist_seqr::stdev 33.556959 +system.ruby.LD.miss_latency_hist_seqr | 31631 62.46% 62.46% | 17660 34.87% 97.33% | 896 1.76% 99.10% | 167 0.32% 99.43% | 158 0.31% 99.74% | 119 0.23% 99.98% | 5 0.00% 99.99% | 2 0.00% 99.99% | 0 0.00% 99.99% | 1 0.00% 99.99% +system.ruby.LD.miss_latency_hist_seqr::total 50639 +system.ruby.ST.latency_hist_seqr::bucket_size 64 +system.ruby.ST.latency_hist_seqr::max_bucket 639 +system.ruby.ST.latency_hist_seqr::samples 63481 +system.ruby.ST.latency_hist_seqr::mean 15.162899 +system.ruby.ST.latency_hist_seqr::gmean 3.255620 +system.ruby.ST.latency_hist_seqr::stdev 26.886809 +system.ruby.ST.latency_hist_seqr | 57998 91.36% 91.36% | 5092 8.02% 99.38% | 258 0.40% 99.79% | 53 0.08% 99.87% | 43 0.06% 99.94% | 25 0.03% 99.98% | 4 0.00% 99.98% | 1 0.00% 99.98% | 0 0.00% 99.98% | 7 0.01% 99.99% +system.ruby.ST.latency_hist_seqr::total 63481 +system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 +system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 +system.ruby.ST.hit_latency_hist_seqr::samples 43284 +system.ruby.ST.hit_latency_hist_seqr::mean 1 +system.ruby.ST.hit_latency_hist_seqr::gmean 1 +system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 43284 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist_seqr::total 43284 +system.ruby.ST.miss_latency_hist_seqr::bucket_size 64 +system.ruby.ST.miss_latency_hist_seqr::max_bucket 639 +system.ruby.ST.miss_latency_hist_seqr::samples 20197 +system.ruby.ST.miss_latency_hist_seqr::mean 45.515274 +system.ruby.ST.miss_latency_hist_seqr::gmean 40.855844 +system.ruby.ST.miss_latency_hist_seqr::stdev 30.348101 +system.ruby.ST.miss_latency_hist_seqr | 14714 72.85% 72.85% | 5092 25.21% 98.06% | 258 1.27% 99.34% | 53 0.26% 99.60% | 43 0.21% 99.81% | 25 0.12% 99.94% | 4 0.01% 99.96% | 1 0.00% 99.96% | 0 0.00% 99.96% | 7 0.03% 99.99% +system.ruby.ST.miss_latency_hist_seqr::total 20197 +system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.latency_hist_seqr::samples 385584 +system.ruby.IFETCH.latency_hist_seqr::mean 11.130915 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.868242 +system.ruby.IFETCH.latency_hist_seqr::stdev 28.485204 +system.ruby.IFETCH.latency_hist_seqr | 343624 89.11% 89.11% | 38794 10.06% 99.17% | 2154 0.55% 99.73% | 354 0.09% 99.82% | 367 0.09% 99.92% | 260 0.06% 99.99% | 23 0.00% 99.99% | 4 0.00% 99.99% | 0 0.00% 99.99% | 4 0.00% 99.99% +system.ruby.IFETCH.latency_hist_seqr::total 385584 +system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 +system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 +system.ruby.IFETCH.hit_latency_hist_seqr::samples 326759 +system.ruby.IFETCH.hit_latency_hist_seqr::mean 1 +system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 +system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 326759 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist_seqr::total 326759 +system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.miss_latency_hist_seqr::samples 58825 +system.ruby.IFETCH.miss_latency_hist_seqr::mean 67.405762 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 60.142402 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 39.769582 +system.ruby.IFETCH.miss_latency_hist_seqr | 16865 28.66% 28.66% | 38794 65.94% 94.61% | 2154 3.66% 98.27% | 354 0.60% 98.88% | 367 0.62% 99.50% | 260 0.44% 99.94% | 23 0.03% 99.98% | 4 0.00% 99.99% | 0 0.00% 99.99% | 4 0.00% 99.99% +system.ruby.IFETCH.miss_latency_hist_seqr::total 58825 +system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 +system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 +system.ruby.Directory.miss_mach_latency_hist_seqr::samples 129661 +system.ruby.Directory.miss_mach_latency_hist_seqr::mean 57.792528 +system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 50.714986 +system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 37.169176 +system.ruby.Directory.miss_mach_latency_hist_seqr | 63210 48.75% 48.75% | 61546 47.46% 96.21% | 3308 2.55% 98.76% | 574 0.44% 99.21% | 568 0.43% 99.64% | 404 0.31% 99.96% | 32 0.02% 99.98% | 7 0.00% 99.99% | 0 0.00% 99.99% | 12 0.00% 99.99% +system.ruby.Directory.miss_mach_latency_hist_seqr::total 129661 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::total 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total 1 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size 8 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 79 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean 75 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 74.999999 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 50639 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 51.521969 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 45.348870 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 33.556959 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 31631 62.46% 62.46% | 17660 34.87% 97.33% | 896 1.76% 99.10% | 167 0.32% 99.43% | 158 0.31% 99.74% | 119 0.23% 99.98% | 5 0.00% 99.99% | 2 0.00% 99.99% | 0 0.00% 99.99% | 1 0.00% 99.99% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 50639 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 20197 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 45.515274 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 40.855844 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 30.348101 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 14714 72.85% 72.85% | 5092 25.21% 98.06% | 258 1.27% 99.34% | 53 0.26% 99.60% | 43 0.21% 99.81% | 25 0.12% 99.94% | 4 0.01% 99.96% | 1 0.00% 99.96% | 0 0.00% 99.96% | 7 0.03% 99.99% +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 20197 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 58825 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 67.405762 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 60.142402 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 39.769582 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 16865 28.66% 28.66% | 38794 65.94% 94.61% | 2154 3.66% 98.27% | 354 0.60% 98.88% | 367 0.62% 99.50% | 260 0.44% 99.94% | 23 0.03% 99.98% | 4 0.00% 99.99% | 0 0.00% 99.99% | 4 0.00% 99.99% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 58825 +system.ruby.Directory_Controller.GETX 129661 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 129657 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 129661 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 129657 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 129661 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 129657 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 129661 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 129657 0.00% 0.00% +system.ruby.L1Cache_Controller.Load 90486 0.00% 0.00% +system.ruby.L1Cache_Controller.Ifetch 385584 0.00% 0.00% +system.ruby.L1Cache_Controller.Store 63481 0.00% 0.00% +system.ruby.L1Cache_Controller.Data 129661 0.00% 0.00% +system.ruby.L1Cache_Controller.Replacement 129657 0.00% 0.00% +system.ruby.L1Cache_Controller.Writeback_Ack 129657 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Load 50639 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Ifetch 58825 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Store 20197 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Load 39847 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Ifetch 326759 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Store 43284 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Replacement 129657 0.00% 0.00% +system.ruby.L1Cache_Controller.MI.Writeback_Ack 129657 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Data 109464 0.00% 0.00% +system.ruby.L1Cache_Controller.IM.Data 20197 0.00% 0.00% + +---------- End Simulation Statistics ---------- diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/stats.txt --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/stats.txt Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,153 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000192 # Number of seconds simulated +sim_ticks 192791500 # Number of ticks simulated +final_tick 192791500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 40212 # Simulator instruction rate (inst/s) +host_op_rate 40212 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 20117511 # Simulator tick rate (ticks/s) +host_mem_usage 265112 # Number of bytes of host memory used +host_seconds 9.58 # Real time elapsed on the host +sim_insts 385362 # Number of instructions simulated +sim_ops 385362 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 192791500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 1542336 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 593554 # Number of bytes read from this memory +system.physmem.bytes_read::total 2135890 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1542336 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1542336 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 401792 # Number of bytes written to this memory +system.physmem.bytes_written::total 401792 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 385584 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 90486 # Number of read requests responded to by this memory +system.physmem.num_reads::total 476070 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 63481 # Number of write requests responded to by this memory +system.physmem.num_writes::total 63481 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 8000020747 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3078735317 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 11078756065 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8000020747 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8000020747 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 2084075283 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2084075283 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8000020747 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5162810601 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13162831348 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 192791500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 221 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 192791500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 385584 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 385362 # Number of instructions committed +system.cpu.committedOps 385362 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 385160 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 1217 # Number of float alu accesses +system.cpu.num_func_calls 27940 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 57164 # number of instructions that are conditional controls +system.cpu.num_int_insts 385160 # number of integer instructions +system.cpu.num_fp_insts 1217 # number of float instructions +system.cpu.num_int_register_reads 507652 # number of times the integer registers were read +system.cpu.num_int_register_writes 264394 # number of times the integer registers were written +system.cpu.num_fp_register_reads 976 # number of times the floating registers were read +system.cpu.num_fp_register_writes 800 # number of times the floating registers were written +system.cpu.num_mem_refs 153968 # number of memory refs +system.cpu.num_load_insts 90486 # Number of load instructions +system.cpu.num_store_insts 63482 # Number of store instructions +system.cpu.num_idle_cycles -0 # Number of idle cycles +system.cpu.num_busy_cycles 385584 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction -0 # Percentage of idle cycles +system.cpu.Branches 85104 # Number of branches fetched +system.cpu.op_class::No_OpClass 221 0.05% 0.05% # Class of executed instruction +system.cpu.op_class::IntAlu 230282 59.72% 59.78% # Class of executed instruction +system.cpu.op_class::IntMult 636 0.16% 59.94% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 59.94% # Class of executed instruction +system.cpu.op_class::FloatAdd 133 0.03% 59.97% # Class of executed instruction +system.cpu.op_class::FloatCmp 170 0.04% 60.02% # Class of executed instruction +system.cpu.op_class::FloatCvt 128 0.03% 60.05% # Class of executed instruction +system.cpu.op_class::FloatMult 30 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::FloatDiv 11 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::FloatSqrt 5 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.06% # Class of executed instruction +system.cpu.op_class::MemRead 89915 23.31% 83.38% # Class of executed instruction +system.cpu.op_class::MemWrite 63313 16.42% 99.80% # Class of executed instruction +system.cpu.op_class::FloatMemRead 571 0.14% 99.95% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 169 0.04% 99.99% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 99.99% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 99.99% # Class of executed instruction +system.cpu.op_class::total 385584 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 192791500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 476070 # Transaction distribution +system.membus.trans_dist::ReadResp 476070 # Transaction distribution +system.membus.trans_dist::WriteReq 63481 # Transaction distribution +system.membus.trans_dist::WriteResp 63481 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 771168 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 307934 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1079102 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1542336 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 995346 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 2537682 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 539551 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev -0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 539551 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 539551 # Request fanout histogram + +---------- End Simulation Statistics ---------- diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/config.ini --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/config.ini Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,1265 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 + +[system] +type=System +children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges=0:268435455:0:0:0:0 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.sys_port_proxy.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=TimingSimpleCPU +children=clk_domain dtb interrupts isa itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu.clk_domain +cpu_id=0 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1] +icache_port=system.ruby.l1_cntrl0.sequencer.slave[0] + +[system.cpu.clk_domain] +type=SrcClockDomain +clock=1 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64d/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000 + +[system.mem_ctrls] +type=DRAMCtrl +IDD0=0.055000 +IDD02=0.000000 +IDD2N=0.032000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.032000 +IDD2P12=0.000000 +IDD3N=0.038000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.038000 +IDD3P12=0.000000 +IDD4R=0.157000 +IDD4R2=0.000000 +IDD4W=0.125000 +IDD4W2=0.000000 +IDD5=0.235000 +IDD52=0.000000 +IDD6=0.020000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +page_policy=open_adaptive +power_model=Null +range=0:268435455:5:19:0:0 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10 +static_frontend_latency=10 +tBURST=5 +tCCD_L=0 +tCK=1 +tCL=14 +tCS=3 +tRAS=35 +tRCD=14 +tREFI=7800 +tRFC=260 +tRP=14 +tRRD=6 +tRRD_L=0 +tRTP=8 +tRTW=3 +tWR=15 +tWTR=8 +tXAW=30 +tXP=6 +tXPDLL=0 +tXS=270 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.ruby.dir_cntrl0.memory + +[system.ruby] +type=RubySystem +children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network +access_backing_store=false +all_instructions=false +block_size_bytes=64 +clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +hot_lines=false +memory_size_bits=48 +num_of_sequencers=1 +number_of_virtual_networks=5 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +phys_mem=Null +power_model=Null +randomization=false + +[system.ruby.clk_domain] +type=SrcClockDomain +clock=1 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.ruby.dir_cntrl0] +type=Directory_Controller +children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir requestToDir responseFromDir responseFromMemory +buffer_size=0 +clk_domain=system.ruby.clk_domain +cluster_id=0 +default_p_state=UNDEFINED +directory=system.ruby.dir_cntrl0.directory +directory_latency=12 +dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir +dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir +eventq_index=0 +forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir +number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +recycle_latency=10 +requestToDir=system.ruby.dir_cntrl0.requestToDir +responseFromDir=system.ruby.dir_cntrl0.responseFromDir +responseFromMemory=system.ruby.dir_cntrl0.responseFromMemory +ruby_system=system.ruby +system=system +to_memory_controller_latency=1 +transitions_per_cycle=4 +version=0 +memory=system.mem_ctrls.port + +[system.ruby.dir_cntrl0.directory] +type=RubyDirectoryMemory +eventq_index=0 +numa_high_bit=5 +size=268435456 +version=0 + +[system.ruby.dir_cntrl0.dmaRequestToDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[3] + +[system.ruby.dir_cntrl0.dmaResponseFromDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[3] + +[system.ruby.dir_cntrl0.forwardFromDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[4] + +[system.ruby.dir_cntrl0.requestToDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[2] + +[system.ruby.dir_cntrl0.responseFromDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[2] + +[system.ruby.dir_cntrl0.responseFromMemory] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false + +[system.ruby.l1_cntrl0] +type=L1Cache_Controller +children=cacheMemory forwardToCache mandatoryQueue requestFromCache responseFromCache responseToCache sequencer +buffer_size=0 +cacheMemory=system.ruby.l1_cntrl0.cacheMemory +cache_response_latency=12 +clk_domain=system.cpu.clk_domain +cluster_id=0 +default_p_state=UNDEFINED +eventq_index=0 +forwardToCache=system.ruby.l1_cntrl0.forwardToCache +issue_latency=2 +mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue +number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +recycle_latency=10 +requestFromCache=system.ruby.l1_cntrl0.requestFromCache +responseFromCache=system.ruby.l1_cntrl0.responseFromCache +responseToCache=system.ruby.l1_cntrl0.responseToCache +ruby_system=system.ruby +send_evictions=false +sequencer=system.ruby.l1_cntrl0.sequencer +system=system +transitions_per_cycle=4 +version=0 + +[system.ruby.l1_cntrl0.cacheMemory] +type=RubyCache +children=replacement_policy +assoc=2 +block_size=0 +dataAccessLatency=1 +dataArrayBanks=1 +eventq_index=0 +is_icache=false +replacement_policy=system.ruby.l1_cntrl0.cacheMemory.replacement_policy +resourceStalls=false +ruby_system=system.ruby +size=256 +start_index_bit=6 +tagAccessLatency=1 +tagArrayBanks=1 + +[system.ruby.l1_cntrl0.cacheMemory.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=2 +block_size=64 +eventq_index=0 +size=256 + +[system.ruby.l1_cntrl0.forwardToCache] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[0] + +[system.ruby.l1_cntrl0.mandatoryQueue] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false + +[system.ruby.l1_cntrl0.requestFromCache] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[0] + +[system.ruby.l1_cntrl0.responseFromCache] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[1] + +[system.ruby.l1_cntrl0.responseToCache] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[1] + +[system.ruby.l1_cntrl0.sequencer] +type=RubySequencer +clk_domain=system.cpu.clk_domain +coreid=99 +dcache=system.ruby.l1_cntrl0.cacheMemory +dcache_hit_latency=1 +deadlock_threshold=500000 +default_p_state=UNDEFINED +eventq_index=0 +garnet_standalone=false +icache=system.ruby.l1_cntrl0.cacheMemory +icache_hit_latency=1 +is_cpu_sequencer=true +max_outstanding_requests=16 +no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_ruby_tester=false +version=0 +slave=system.cpu.icache_port system.cpu.dcache_port + +[system.ruby.memctrl_clk_domain] +type=DerivedClockDomain +clk_divider=3 +clk_domain=system.ruby.clk_domain +eventq_index=0 + +[system.ruby.network] +type=SimpleNetwork +children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_links0 int_links1 int_links2 int_links3 routers0 routers1 routers2 +adaptive_routing=false +buffer_size=0 +clk_domain=system.ruby.clk_domain +control_msg_size=8 +default_p_state=UNDEFINED +endpoint_bandwidth=1000 +eventq_index=0 +ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 +int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 +int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 +netifs= +number_of_virtual_networks=5 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 +ruby_system=system.ruby +topology=Crossbar +master=system.ruby.l1_cntrl0.forwardToCache.slave system.ruby.l1_cntrl0.responseToCache.slave system.ruby.dir_cntrl0.requestToDir.slave system.ruby.dir_cntrl0.dmaRequestToDir.slave +slave=system.ruby.l1_cntrl0.requestFromCache.master system.ruby.l1_cntrl0.responseFromCache.master system.ruby.dir_cntrl0.responseFromDir.master system.ruby.dir_cntrl0.dmaResponseFromDir.master system.ruby.dir_cntrl0.forwardFromDir.master + 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b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/config.json Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,1734 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1, + "memories": [ + "system.mem_ctrls" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [ + "0:268435455:0:0:0:0" + ], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "dvfs_handler": { + "enable": false, + "name": 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"type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers14", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers14", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers15", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers15", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers16", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers16", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers17", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers17", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers18", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers18", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers19", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers19", + "type": "MessageBuffer" + } + ] + } + ], + "power_model": null, + "netifs": [], + "control_msg_size": 8, + "buffer_size": 0, + "endpoint_bandwidth": 1000, + "ruby_system": "system.ruby", + "name": "network", + "p_state_clk_gate_bins": 20, + "ext_links": [ + { + "latency": 1, + "name": "ext_links0", + "weight": 1, + "ext_node": "system.ruby.l1_cntrl0", + "link_id": 0, + "eventq_index": 0, + "cxx_class": "SimpleExtLink", + "path": "system.ruby.network.ext_links0", + "int_node": "system.ruby.network.routers0", + "type": "SimpleExtLink", + "bandwidth_factor": 16 + }, + { + "latency": 1, + "name": "ext_links1", + "weight": 1, + "ext_node": "system.ruby.dir_cntrl0", + "link_id": 1, + "eventq_index": 0, + "cxx_class": "SimpleExtLink", + "path": "system.ruby.network.ext_links1", + "int_node": "system.ruby.network.routers1", + "type": "SimpleExtLink", + "bandwidth_factor": 16 + } + ], + "number_of_virtual_networks": 5, + "path": "system.ruby.network" + }, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.ruby.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "randomization": false, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "phys_mem": null, + "type": "RubySystem", + "p_state_clk_gate_min": 1, + "hot_lines": false, + "power_model": null, + "path": "system.ruby", + "memctrl_clk_domain": { + "name": "memctrl_clk_domain", + "clk_domain": "system.ruby.clk_domain", + "eventq_index": 0, + "cxx_class": "DerivedClockDomain", + "path": "system.ruby.memctrl_clk_domain", + "type": "DerivedClockDomain", + "clk_divider": 3 + }, + "name": "ruby", + "p_state_clk_gate_bins": 20, + "block_size_bytes": 64, + "access_backing_store": false, + "number_of_virtual_networks": 5, + "num_of_sequencers": 1, + "dir_cntrl0": { + "system": "system", + "cluster_id": 0, + "responseFromMemory": { + "ordered": false, + "name": "responseFromMemory", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.responseFromMemory", + "type": "MessageBuffer" + }, + "cxx_class": "Directory_Controller", + "forwardFromDir": { + "ordered": false, + "name": "forwardFromDir", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "master": { + "peer": "system.ruby.network.slave[4]", + "role": "MASTER" + }, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.forwardFromDir", + "type": "MessageBuffer" + }, + "dmaRequestToDir": { + "ordered": true, + "name": "dmaRequestToDir", + "cxx_class": "MessageBuffer", + "slave": { + "peer": "system.ruby.network.master[3]", + "role": "SLAVE" + }, + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.dmaRequestToDir", + "type": "MessageBuffer" + }, + "type": "Directory_Controller", + "recycle_latency": 10, + "clk_domain": "system.ruby.clk_domain", + "version": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "directory_latency": 12, + "number_of_TBEs": 256, + "to_memory_controller_latency": 1, + "p_state_clk_gate_min": 1, + "responseFromDir": { + "ordered": false, + "name": "responseFromDir", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "master": { + "peer": "system.ruby.network.slave[2]", + "role": "MASTER" + }, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.responseFromDir", + "type": "MessageBuffer" + }, + "transitions_per_cycle": 4, + "memory": { + "peer": "system.mem_ctrls.port", + "role": "MASTER" + }, + "power_model": null, + "buffer_size": 0, + "ruby_system": "system.ruby", + "requestToDir": { + "ordered": true, + "name": "requestToDir", + "cxx_class": "MessageBuffer", + "slave": { + "peer": "system.ruby.network.master[2]", + "role": "SLAVE" + }, + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.requestToDir", + "type": "MessageBuffer" + }, + "dmaResponseFromDir": { + "ordered": true, + "name": "dmaResponseFromDir", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "master": { + "peer": "system.ruby.network.slave[3]", + "role": "MASTER" + }, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.dmaResponseFromDir", + "type": "MessageBuffer" + }, + "name": "dir_cntrl0", + "p_state_clk_gate_bins": 20, + "directory": { + "name": "directory", + "version": 0, + "eventq_index": 0, + "cxx_class": "DirectoryMemory", + "path": "system.ruby.dir_cntrl0.directory", + "type": "RubyDirectoryMemory", + "numa_high_bit": 5, + "size": 268435456 + }, + "path": "system.ruby.dir_cntrl0" + } + }, + "work_end_ckpt_count": 0, + "mem_mode": "timing", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": { + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.itb", + "type": "RiscvTLB", + "size": 64 + }, + "system": "system", + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "TimingSimpleCPU", + "max_loads_all_threads": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "function_trace_start": 0, + "cpu_id": 0, + "checker": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "do_quiesce": true, + "type": "TimingSimpleCPU", + "profile": 0, + "icache_port": { + "peer": "system.ruby.l1_cntrl0.sequencer.slave[0]", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "p_state_clk_gate_min": 1, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "dcache_port": { + "peer": "system.ruby.l1_cntrl0.sequencer.slave[1]", + "role": "MASTER" + }, + "socket_id": 0, + "power_model": null, + "max_insts_all_threads": 0, + "path": "system.cpu", + "max_loads_any_thread": 0, + "switched_out": false, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64d/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "progress_interval": 0, + "branchPred": null, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + }, + "multi_thread": false, + "mem_ctrls": [ + { + "static_frontend_latency": 10, + "tRFC": 260, + "activation_limit": 4, + "in_addr_map": true, + "IDD3N2": "0.0", + "tWTR": 8, + "IDD52": "0.0", + "clk_domain": "system.clk_domain", + "channels": 1, + "write_buffer_size": 64, + "device_bus_width": 8, + "VDD": "1.5", + "write_high_thresh_perc": 85, + "cxx_class": "DRAMCtrl", + "bank_groups_per_rank": 0, + "IDD2N2": "0.0", + "port": { + "peer": "system.ruby.dir_cntrl0.memory", + "role": "SLAVE" + }, + "tCCD_L": 0, + "IDD2N": "0.032", + "p_state_clk_gate_min": 1, + "null": false, + "IDD2P1": "0.032", + "eventq_index": 0, + "tRRD": 6, + "tRTW": 3, + "IDD4R": "0.157", + "burst_length": 8, + "tRTP": 8, + "IDD4W": "0.125", + "tWR": 15, + "banks_per_rank": 8, + "devices_per_rank": 8, + "IDD2P02": "0.0", + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "IDD6": "0.02", + "IDD5": "0.235", + "tRCD": 14, + "type": "DRAMCtrl", + "IDD3P02": "0.0", + "tRRD_L": 0, + "IDD0": "0.055", + "IDD62": "0.0", + "min_writes_per_switch": 16, + "mem_sched_policy": "frfcfs", + "IDD02": "0.0", + "IDD2P0": "0.0", + "ranks_per_channel": 2, + "page_policy": "open_adaptive", + "IDD4W2": "0.0", + "tCS": 3, + "power_model": null, + "tCL": 14, + "read_buffer_size": 32, + "conf_table_reported": true, + "tCK": 1, + "tRAS": 35, + "tRP": 14, + "tBURST": 5, + "path": "system.mem_ctrls", + "tXP": 6, + "tXS": 270, + "addr_mapping": "RoRaBaCoCh", + "IDD3P0": "0.0", + "IDD3P1": "0.038", + "IDD3N": "0.038", + "name": "mem_ctrls", + "tXSDLL": 0, + "device_size": 536870912, + "kvm_map": true, + "dll": true, + "tXAW": 30, + "write_low_thresh_perc": 50, + "range": "0:268435455:5:19:0:0", + "VDD2": "0.0", + "IDD2P12": "0.0", + "p_state_clk_gate_bins": 20, + "tXPDLL": 0, + "IDD4R2": "0.0", + "device_rowbuffer_size": 1024, + "static_backend_latency": 10, + "max_accesses_per_row": 16, + "IDD3P12": "0.0", + "tREFI": 7800 + } + ], + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/simerr --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-timing-ruby/simerr Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,11 @@ +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick +warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/simerr --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/simerr Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,4 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/simout --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/simout Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,226 @@ +Redirecting stdout to build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64d/minor-timing/simout +Redirecting stderr to build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64d/minor-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 2 2016 20:34:02 +gem5 started Nov 3 2016 19:08:39 +gem5 executing on ubuntu1604, pid 22242 +command line: /home/ar4jc/gem5/build/RISCV/gem5.debug -d build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64d/minor-timing -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64d/minor-timing + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +fld: PASS +fsd: PASS +fmadd.d: PASS +fmadd.d, quiet NaN: PASS +fmadd.d, signaling NaN: PASS +fmadd.d, infinity: PASS +fmadd.d, -infinity: PASS +fmsub.d: PASS +fmsub.d, quiet NaN: PASS +fmsub.d, signaling NaN: PASS +fmsub.d, infinity: PASS +fmsub.d, -infinity: PASS +fmsub.d, subtract infinity: PASS +fnmsub.d: PASS +fnmsub.d, quiet NaN: PASS +fnmsub.d, signaling NaN: PASS +fnmsub.d, infinity: PASS +fnmsub.d, -infinity: PASS +fnmsub.d, subtract infinity: PASS +fnmadd.d: PASS +fnmadd.d, quiet NaN: PASS +fnmadd.d, signaling NaN: PASS +fnmadd.d, infinity: PASS +fnmadd.d, -infinity: PASS +fadd.d: PASS +fadd.d, quiet NaN: PASS +fadd.d, signaling NaN: PASS +fadd.d, infinity: PASS +fadd.d, -infinity: PASS +fsub.d: PASS +fsub.d, quiet NaN: PASS +fsub.d, signaling NaN: PASS +fsub.d, infinity: PASS +fsub.d, -infinity: PASS +fsub.d, subtract infinity: PASS +fmul.d: PASS +fmul.d, quiet NaN: PASS +fmul.d, signaling NaN: PASS +fmul.d, infinity: PASS +fmul.d, -infinity: PASS +fmul.d, 0*infinity: PASS +fmul.d, overflow: PASS +fmul.d, underflow: PASS +fdiv.d: PASS +fdiv.d, quiet NaN: PASS +fdiv.d, signaling NaN: PASS +fdiv.d/0: PASS +fdiv.d/infinity: PASS +fdiv.d, infinity/infinity: PASS +fdiv.d, 0/0: PASS +fdiv.d, infinity/0: PASS +fdiv.d, 0/infinity: PASS +fdiv.d, underflow: PASS +fdiv.d, overflow: PASS +fsqrt.d: PASS +fsqrt.d, NaN: PASS +fsqrt.d, quiet NaN: PASS +fsqrt.d, signaling NaN: PASS +fsqrt.d, infinity: PASS +fsgnj.d, ++: PASS +fsgnj.d, +-: PASS +fsgnj.d, -+: PASS +fsgnj.d, --: PASS +fsgnj.d, quiet NaN: PASS +fsgnj.d, signaling NaN: PASS +fsgnj.d, inject NaN: PASS +fsgnj.d, inject -NaN: PASS +fsgnjn.d, ++: PASS +fsgnjn.d, +-: PASS +fsgnjn.d, -+: PASS +fsgnjn.d, --: PASS +fsgnjn.d, quiet NaN: PASS +fsgnjn.d, signaling NaN: PASS +fsgnjn.d, inject NaN: PASS +fsgnjn.d, inject NaN: PASS +fsgnjx.d, ++: PASS +fsgnjx.d, +-: PASS +fsgnjx.d, -+: PASS +fsgnjx.d, --: PASS +fsgnjx.d, quiet NaN: PASS +fsgnjx.d, signaling NaN: PASS +fsgnjx.d, inject NaN: PASS +fsgnjx.d, inject NaN: PASS +fmin.d: PASS +fmin.d, -infinity: PASS +fmin.d, infinity: PASS +fmin.d, quiet NaN first: PASS +fmin.d, quiet NaN second: PASS +fmin.d, quiet NaN both: PASS +fmin.d, signaling NaN first: PASS +fmin.d, signaling NaN second: PASS +fmin.d, signaling NaN both: PASS +fmax.d: PASS +fmax.d, -infinity: PASS +fmax.d, infinity: PASS +fmax.d, quiet NaN first: PASS +fmax.d, quiet NaN second: PASS +fmax.d, quiet NaN both: PASS +fmax.d, signaling NaN first: PASS +fmax.d, signaling NaN second: PASS +fmax.d, signaling NaN both: PASS +fcvt.s.d: PASS +fcvt.s.d, quiet NaN: PASS +fcvt.s.d, signaling NaN: PASS +fcvt.s.d, infinity: PASS +fcvt.s.d, overflow: PASS +fcvt.s.d, underflow: PASS +fcvt.d.s: PASS +fcvt.d.s, quiet NaN: PASS +fcvt.d.s, signaling NaN: PASS +fcvt.d.s, infinity: PASS +feq.d, equal: PASS +feq.d, not equal: PASS +feq.d, 0 == -0: PASS +feq.d, quiet NaN first: PASS +feq.d, quiet NaN second: PASS +feq.d, quiet NaN both: PASS +feq.d, signaling NaN first: PASS +feq.d, signaling NaN second: PASS +feq.d, signaling NaN both: PASS +flt.d, equal: PASS +flt.d, less: PASS +flt.d, greater: PASS +flt.d, quiet NaN first: PASS +flt.d, quiet NaN second: PASS +flt.d, quiet NaN both: PASS +flt.d, signaling NaN first: PASS +flt.d, signaling NaN second: PASS +flt.d, signaling NaN both: PASS +fle.d, equal: PASS +fle.d, less: PASS +fle.d, greater: PASS +fle.d, 0 == -0: PASS +fle.d, quiet NaN first: PASS +fle.d, quiet NaN second: PASS +fle.d, quiet NaN both: PASS +fle.d, signaling NaN first: PASS +fle.d, signaling NaN second: PASS +fle.d, signaling NaN both: PASS +fclass.d, -infinity: PASS +fclass.d, -normal: PASS +fclass.d, -subnormal: PASS +fclass.d, -0.0: PASS +fclass.d, 0.0: PASS +fclass.d, subnormal: PASS +fclass.d, normal: PASS +fclass.d, infinity: PASS +fclass.d, signaling NaN: PASS +fclass.s, quiet NaN: PASS +fcvt.w.d, truncate positive: PASS +fcvt.w.d, truncate negative: PASS +fcvt.w.d, 0.0: PASS +fcvt.w.d, -0.0: PASS +fcvt.w.d, overflow: PASS +fcvt.w.d, underflow: PASS +fcvt.w.d, infinity: PASS +fcvt.w.d, -infinity: PASS +fcvt.w.d, quiet NaN: PASS +fcvt.w.d, quiet -NaN: PASS +fcvt.w.d, signaling NaN: PASS +fcvt.wu.d, truncate positive: PASS +fcvt.wu.d, truncate negative: PASS +fcvt.wu.d, 0.0: PASS +fcvt.wu.d, -0.0: PASS +fcvt.wu.d, overflow: PASS +fcvt.wu.d, underflow: PASS +fcvt.wu.d, infinity: PASS +fcvt.wu.d, -infinity: PASS +fcvt.wu.d, quiet NaN: PASS +fcvt.wu.d, quiet -NaN: PASS +fcvt.wu.d, signaling NaN: PASS +fcvt.d.w, 0: PASS +fcvt.d.w, negative: PASS +fcvt.d.w, truncate: PASS +fcvt.d.wu, 0: PASS +fcvt.d.wu: PASS +fcvt.d.wu, truncate: PASS +fcvt.l.d, truncate positive: PASS +fcvt.l.d, truncate negative: PASS +fcvt.l.d, 0.0: PASS +fcvt.l.d, -0.0: PASS +fcvt.l.d, 32-bit overflow: PASS +fcvt.l.d, overflow: PASS +fcvt.l.d, underflow: PASS +fcvt.l.d, infinity: PASS +fcvt.l.d, -infinity: PASS +fcvt.l.d, quiet NaN: PASS +fcvt.l.d, quiet -NaN: PASS +fcvt.l.d, signaling NaN: PASS +fcvt.lu.d, truncate positive: PASS +fcvt.lu.d, truncate negative: PASS +fcvt.lu.d, 0.0: PASS +fcvt.lu.d, -0.0: PASS +fcvt.lu.d, 32-bit overflow: PASS +fcvt.lu.d, overflow: PASS +fcvt.lu.d, underflow: PASS +fcvt.lu.d, infinity: PASS +fcvt.lu.d, -infinity: PASS +fcvt.lu.d, quiet NaN: PASS +fcvt.lu.d, quiet -NaN: PASS +fcvt.lu.d, signaling NaN: PASS +fmv.x.d, positive: PASS +fmv.x.d, negative: PASS +fmv.x.d, 0.0: PASS +fmv.x.d, -0.0: PASS +fcvt.d.l, 0: PASS +fcvt.d.l, negative: PASS +fcvt.d.l, 32-bit truncate: PASS +fcvt.d.lu, 0: PASS +fcvt.d.lu: PASS +fcvt.d.lu, 32-bit truncate: PASS +fmv.d.x: PASS +Exiting @ tick 403564500 because target called exit() diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/stats.txt --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/stats.txt Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,765 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000403 # Number of seconds simulated +sim_ticks 403564500 # Number of ticks simulated +final_tick 403564500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 17121 # Simulator instruction rate (inst/s) +host_op_rate 17121 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 17919764 # Simulator tick rate (ticks/s) +host_mem_usage 276644 # Number of bytes of host memory used +host_seconds 22.52 # Real time elapsed on the host +sim_insts 385584 # Number of instructions simulated +sim_ops 385584 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 403564500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 81920 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 21440 # Number of bytes read from this memory +system.physmem.bytes_read::total 103360 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 81920 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 81920 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 1280 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 335 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1615 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 202991095 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 53126575 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 256117671 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 202991095 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 202991095 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 202991095 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 53126575 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 256117671 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1615 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 1615 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 103360 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 103360 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 164 # Per bank write bursts +system.physmem.perBankRdBursts::1 128 # Per bank write bursts +system.physmem.perBankRdBursts::2 36 # Per bank write bursts +system.physmem.perBankRdBursts::3 216 # Per bank write bursts +system.physmem.perBankRdBursts::4 256 # Per bank write bursts +system.physmem.perBankRdBursts::5 117 # Per bank write bursts +system.physmem.perBankRdBursts::6 16 # Per bank write bursts +system.physmem.perBankRdBursts::7 17 # Per bank write bursts +system.physmem.perBankRdBursts::8 135 # Per bank write bursts +system.physmem.perBankRdBursts::9 191 # Per bank write bursts +system.physmem.perBankRdBursts::10 98 # Per bank write bursts +system.physmem.perBankRdBursts::11 23 # Per bank write bursts +system.physmem.perBankRdBursts::12 14 # Per bank write bursts +system.physmem.perBankRdBursts::13 74 # Per bank write bursts +system.physmem.perBankRdBursts::14 120 # Per bank write bursts +system.physmem.perBankRdBursts::15 10 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 403293000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 1615 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1553 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 57 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 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+system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 306 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 331.712418 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 237.889331 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 258.551264 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 57 18.62% 18.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 81 26.47% 45.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 45 14.70% 59.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 49 16.01% 75.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 33 10.78% 86.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 16 5.22% 91.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7 2.28% 94.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 4 1.30% 95.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 14 4.57% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 306 # Bytes accessed per row activation +system.physmem.totQLat 20676250 # Total ticks spent queuing +system.physmem.totMemAccLat 50957500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 8075000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12802.63 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 31552.63 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 256.11 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 256.11 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 2.00 # Data bus utilization in percentage +system.physmem.busUtilRead 2.00 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 1301 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.55 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 249717.02 # Average gap between requests +system.physmem.pageHitRate 80.55 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1128120 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 588225 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 6783000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 31346640 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 17473350 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 717600 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 152831250 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 10836960 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 221705145 # Total energy per rank (pJ) +system.physmem_0.averagePower 549.366632 # Core power per rank (mW) +system.physmem_0.totalIdleTime 363165000 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 348000 # Time in different power states +system.physmem_0.memoryStateTime::REF 13260000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 0 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 28214250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 26561000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 335181250 # Time in different power states +system.physmem_1.actEnergy 1113840 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 573045 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4748100 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 31346640 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 14570340 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 3642720 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 126937860 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 32161440 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 215093985 # Total energy per rank (pJ) +system.physmem_1.averagePower 532.984736 # Core power per rank (mW) +system.physmem_1.totalIdleTime 361930500 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 8092250 # Time in different power states +system.physmem_1.memoryStateTime::REF 13260000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 0 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 83742750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 20058750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 278410750 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 403564500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 102981 # Number of BP lookups +system.cpu.branchPred.condPredicted 65571 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7488 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 79852 # Number of BTB lookups +system.cpu.branchPred.BTBHits 47288 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 59.219556 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 16893 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 9910 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 6983 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 4142 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 221 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 403564500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 807129 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 385584 # Number of instructions committed +system.cpu.committedOps 385584 # Number of ops (including micro ops) committed +system.cpu.discardedOps 18946 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 2.093263 # CPI: cycles per instruction +system.cpu.ipc 0.477722 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 221 0.05% 0.05% # Class of committed instruction +system.cpu.op_class_0::IntAlu 230282 59.72% 59.78% # Class of committed instruction +system.cpu.op_class_0::IntMult 636 0.16% 59.94% # Class of committed instruction +system.cpu.op_class_0::IntDiv 0 0.00% 59.94% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 133 0.03% 59.97% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 170 0.04% 60.02% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 128 0.03% 60.05% # Class of committed instruction +system.cpu.op_class_0::FloatMult 30 0.00% 60.06% # Class of committed instruction +system.cpu.op_class_0::FloatMultAcc 0 0.00% 60.06% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 11 0.00% 60.06% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 0 0.00% 60.06% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 5 0.00% 60.06% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 60.06% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 60.06% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 60.06% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 60.06% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 60.06% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 60.06% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 60.06% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 60.06% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 60.06% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 60.06% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 60.06% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 60.06% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 60.06% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 60.06% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 0 0.00% 60.06% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 60.06% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 0 0.00% 60.06% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 60.06% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 60.06% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 60.06% # Class of committed instruction +system.cpu.op_class_0::MemRead 89915 23.31% 83.38% # Class of committed instruction +system.cpu.op_class_0::MemWrite 63313 16.42% 99.80% # Class of committed instruction +system.cpu.op_class_0::FloatMemRead 571 0.14% 99.95% # Class of committed instruction +system.cpu.op_class_0::FloatMemWrite 169 0.04% 99.99% # Class of committed instruction +system.cpu.op_class_0::IprAccess 0 0.00% 99.99% # Class of committed instruction +system.cpu.op_class_0::InstPrefetch 0 0.00% 99.99% # Class of committed instruction +system.cpu.op_class_0::total 385584 # Class of committed instruction +system.cpu.tickCycles 558011 # Number of cycles that the object actually ticked +system.cpu.idleCycles 249118 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 403564500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 265.329920 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 156238 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 336 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 464.994047 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 265.329920 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.064777 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.064777 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 336 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 306 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.082031 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 313870 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 313870 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 403564500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 93142 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 93142 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 63096 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 63096 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 156238 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 156238 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 156238 # number of overall hits +system.cpu.dcache.overall_hits::total 156238 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 144 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 144 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 385 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 385 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 529 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 529 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 529 # number of overall misses +system.cpu.dcache.overall_misses::total 529 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12931500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12931500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 30702500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 30702500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 43634000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 43634000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 43634000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 43634000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 93286 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 93286 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 63481 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 63481 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 156767 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 156767 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 156767 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 156767 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001543 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.001543 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006064 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006064 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.003374 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.003374 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.003374 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.003374 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 89802.083333 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 89802.083333 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79746.753246 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 79746.753246 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 82483.931947 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 82483.931947 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 82483.931947 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 82483.931947 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 186 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 186 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 193 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 193 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 193 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 193 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 137 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 137 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 199 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 199 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 336 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 336 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 336 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 336 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12211000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12211000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 15869500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 15869500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28080500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 28080500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28080500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28080500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001468 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001468 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003134 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003134 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002143 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002143 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002143 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002143 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89131.386861 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89131.386861 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79746.231155 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79746.231155 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83572.916666 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 83572.916666 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83572.916666 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 83572.916666 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 403564500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 88 # number of replacements +system.cpu.icache.tags.tagsinuse 728.987124 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 168584 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1284 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 131.295950 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 728.987124 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.355950 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.355950 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1196 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 973 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.583984 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 341020 # Number of tag accesses +system.cpu.icache.tags.data_accesses 341020 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 403564500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 168584 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 168584 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 168584 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 168584 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 168584 # number of overall hits +system.cpu.icache.overall_hits::total 168584 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1284 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1284 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1284 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1284 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1284 # number of overall misses +system.cpu.icache.overall_misses::total 1284 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 108989000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 108989000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 108989000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 108989000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 108989000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 108989000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 169868 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 169868 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 169868 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 169868 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 169868 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 169868 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007558 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.007558 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.007558 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.007558 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.007558 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.007558 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 84882.398753 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 84882.398753 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 84882.398753 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 84882.398753 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 84882.398753 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 84882.398753 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 88 # number of writebacks +system.cpu.icache.writebacks::total 88 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1284 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1284 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1284 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1284 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1284 # number of overall MSHR misses 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Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 0 # number of replacements +system.cpu.l2cache.tags.tagsinuse 1023.680613 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 93 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1615 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.057585 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::cpu.inst 759.106218 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 264.574395 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.023166 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.008074 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.031240 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 1615 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 202 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1363 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.049285 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 15279 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 15279 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 403564500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackClean_hits::writebacks 88 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 88 # number of WritebackClean hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 4 # number of ReadCleanReq hits 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miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82607.031250 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82277.611940 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 82538.699690 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82607.031250 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82277.611940 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 82538.699690 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 199 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 199 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1280 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1280 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 136 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 136 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1280 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 335 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1615 # number of demand (read+write) MSHR misses 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(read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 24213000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 117150000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 92937000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 24213000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 117150000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996884 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996884 # mshr miss rate for ReadCleanReq accesses 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average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72607.031250 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72607.031250 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78176.470588 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78176.470588 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72607.031250 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72277.611940 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72538.699690 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72607.031250 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72277.611940 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72538.699690 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1708 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 89 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 403564500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 1421 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 88 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 199 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 199 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1284 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 137 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2656 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 672 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3328 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 87808 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21504 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 109312 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 1620 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000617 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.024845 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1619 99.93% 99.93% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1 0.06% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1620 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 942000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1926000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 504000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 1615 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 403564500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1416 # Transaction distribution +system.membus.trans_dist::ReadExReq 199 # Transaction distribution +system.membus.trans_dist::ReadExResp 199 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1416 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3230 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3230 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 103360 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 103360 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1615 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev -0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1615 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1615 # Request fanout histogram +system.membus.reqLayer0.occupancy 1893500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 8567500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 2.1 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64d/o3-timing/config.ini --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/o3-timing/config.ini Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,866 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cachePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +default_p_state=UNDEFINED +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=0 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +system=system +tracer=system.cpu.tracer +trapLatency=13 +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TournamentBP +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +useIndirect=true + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +hit_latency=2 +is_read_only=false +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=262144 + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +eventq_index=0 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +opClass=IntAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +eventq_index=0 +opClass=IntMult +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +eventq_index=0 +opClass=IntDiv +opLat=20 +pipelined=false + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +eventq_index=0 +opClass=FloatAdd +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatCmp +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatCvt +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 opList3 opList4 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +eventq_index=0 +opClass=FloatMult +opLat=4 +pipelined=true + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMultAcc +opLat=5 +pipelined=true + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMisc +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList3.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatDiv +opLat=12 +pipelined=false + +[system.cpu.fuPool.FUList3.opList4] +type=OpDesc +eventq_index=0 +opClass=FloatSqrt +opLat=24 +pipelined=false + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList0 opList1 +count=0 +eventq_index=0 +opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +eventq_index=0 +opClass=MemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList4.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5] +type=FUDesc +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 + +[system.cpu.fuPool.FUList5.opList00] +type=OpDesc +eventq_index=0 +opClass=SimdAdd +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList01] +type=OpDesc +eventq_index=0 +opClass=SimdAddAcc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList02] +type=OpDesc +eventq_index=0 +opClass=SimdAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList03] +type=OpDesc +eventq_index=0 +opClass=SimdCmp +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList04] +type=OpDesc +eventq_index=0 +opClass=SimdCvt +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList05] +type=OpDesc +eventq_index=0 +opClass=SimdMisc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList06] +type=OpDesc +eventq_index=0 +opClass=SimdMult +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList07] +type=OpDesc +eventq_index=0 +opClass=SimdMultAcc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList08] +type=OpDesc +eventq_index=0 +opClass=SimdShift +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList09] +type=OpDesc +eventq_index=0 +opClass=SimdShiftAcc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList10] +type=OpDesc +eventq_index=0 +opClass=SimdSqrt +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList11] +type=OpDesc +eventq_index=0 +opClass=SimdFloatAdd +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList12] +type=OpDesc +eventq_index=0 +opClass=SimdFloatAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList13] +type=OpDesc +eventq_index=0 +opClass=SimdFloatCmp +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList14] +type=OpDesc +eventq_index=0 +opClass=SimdFloatCvt +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList15] +type=OpDesc +eventq_index=0 +opClass=SimdFloatDiv +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList16] +type=OpDesc +eventq_index=0 +opClass=SimdFloatMisc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList17] +type=OpDesc +eventq_index=0 +opClass=SimdFloatMult +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList18] +type=OpDesc +eventq_index=0 +opClass=SimdFloatMultAcc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList19] +type=OpDesc +eventq_index=0 +opClass=SimdFloatSqrt +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList6] +type=FUDesc +children=opList0 opList1 +count=0 +eventq_index=0 +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +eventq_index=0 +opClass=MemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7] +type=FUDesc +children=opList0 opList1 opList2 opList3 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +eventq_index=0 +opClass=MemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7.opList1] +type=OpDesc +eventq_index=0 +opClass=MemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList8] +type=FUDesc +children=opList +count=1 +eventq_index=0 +opList=system.cpu.fuPool.FUList8.opList + +[system.cpu.fuPool.FUList8.opList] +type=OpDesc +eventq_index=0 +opClass=IprAccess +opLat=3 +pipelined=false + +[system.cpu.icache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +hit_latency=2 +is_read_only=true +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tags=system.cpu.icache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=131072 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.l2cache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +hit_latency=20 +is_read_only=false +max_miss_count=0 +mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +hit_latency=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=2097152 + +[system.cpu.toL2Bus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=0 +frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null +response_latency=1 +snoop_filter=system.cpu.toL2Bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64d/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=DRAMCtrl +IDD0=0.055000 +IDD02=0.000000 +IDD2N=0.032000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.032000 +IDD2P12=0.000000 +IDD3N=0.038000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.038000 +IDD3P12=0.000000 +IDD4R=0.157000 +IDD4R2=0.000000 +IDD4W=0.125000 +IDD4W2=0.000000 +IDD5=0.235000 +IDD52=0.000000 +IDD6=0.020000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +page_policy=open_adaptive +power_model=Null +range=0:134217727:0:0:0:0 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCCD_L=0 +tCK=1250 +tCL=13750 +tCS=2500 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64d/o3-timing/config.json --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/o3-timing/config.json Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,1145 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.l2cache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": 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"count": 0, + "opList": [ + { + "opClass": "MemWrite", + "opLat": 1, + "name": "opList0", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList6.opList0", + "type": "OpDesc" + }, + { + "opClass": "FloatMemWrite", + "opLat": 1, + "name": "opList1", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList6.opList1", + "type": "OpDesc" + } + ], + "name": "FUList6", + "eventq_index": 0, + "cxx_class": "FUDesc", + "path": "system.cpu.fuPool.FUList6", + "type": "FUDesc" + }, + { + "count": 4, + "opList": [ + { + "opClass": "MemRead", + "opLat": 1, + "name": "opList0", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList7.opList0", + "type": "OpDesc" + }, + { + "opClass": "MemWrite", + "opLat": 1, + "name": "opList1", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList7.opList1", + "type": "OpDesc" + }, + { + "opClass": "FloatMemRead", + "opLat": 1, + "name": "opList2", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList7.opList2", + "type": "OpDesc" + }, + { + "opClass": "FloatMemWrite", + "opLat": 1, + "name": "opList3", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList7.opList3", + "type": "OpDesc" + } + ], + "name": "FUList7", + "eventq_index": 0, + "cxx_class": "FUDesc", + "path": "system.cpu.fuPool.FUList7", + "type": "FUDesc" + }, + { + "count": 1, + "opList": [ + { + "opClass": "IprAccess", + "opLat": 3, + "name": "opList", + "pipelined": false, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList8.opList", + "type": "OpDesc" + } + ], + "name": "FUList8", + "eventq_index": 0, + "cxx_class": "FUDesc", + "path": "system.cpu.fuPool.FUList8", + "type": "FUDesc" + } + ], + "eventq_index": 0, + "cxx_class": "FUPool", + "path": "system.cpu.fuPool", + "type": "FUPool" + }, + "socket_id": 0, + "renameToFetchDelay": 1, + "icache": { + "cpu_side": { + "peer": "system.cpu.icache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 131072, + "tags": { + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.icache.tags", + "hit_latency": 2, + "block_size": 64, + "type": "LRU", + "size": 131072 + }, + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[0]", + "role": "MASTER" + }, + "type": "Cache", + "writeback_clean": true, + "p_state_clk_gate_min": 1000, + "hit_latency": 2, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": true, + "prefetch_on_access": false, + "path": "system.cpu.icache", + "mshrs": 4, + "name": "icache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "path": "system.cpu", + "numRobs": 1, + "switched_out": false, + "smtLSQPolicy": "Partitioned", + "fetchBufferSize": 64, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "smtROBThreshold": 100, + "numIQEntries": 64, + "branchPred": { + "numThreads": 1, + "BTBEntries": 4096, + "cxx_class": "TournamentBP", + "indirectPathLength": 3, + "globalCtrBits": 2, + "choicePredictorSize": 8192, + "indirectHashGHR": true, + "eventq_index": 0, + "localHistoryTableSize": 2048, + "type": "TournamentBP", + "indirectSets": 256, + "indirectWays": 2, + "choiceCtrBits": 2, + "useIndirect": true, + "localCtrBits": 2, + "path": "system.cpu.branchPred", + "localPredictorSize": 2048, + "RASSize": 16, + "globalPredictorSize": 8192, + "name": "branchPred", + "indirectHashTargets": true, + "instShiftAmt": 2, + "indirectTagSize": 16, + "BTBTagSize": 16 + }, + "LFSTSize": 1024, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "smtROBPolicy": "Partitioned", + "iewToFetchDelay": 1, + "do_statistics_insts": true, + "dispatchWidth": 8, + "dcache": { + "cpu_side": { + "peer": "system.cpu.dcache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 262144, + "tags": { + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.dcache.tags", + "hit_latency": 2, + "block_size": 64, + "type": "LRU", + "size": 262144 + }, + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[1]", + "role": "MASTER" + }, + "type": "Cache", + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "hit_latency": 2, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.dcache", + "mshrs": 4, + "name": "dcache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "commitToDecodeDelay": 1, + "smtIQPolicy": "Partitioned", + "issueWidth": 8, + "LSQCheckLoads": true, + "commitToRenameDelay": 1, + "cachePorts": 200, + "system": "system", + "checker": null, + "numPhysFloatRegs": 256, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "type": "DerivO3CPU", + "wbWidth": 8, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "smtCommitPolicy": "RoundRobin", + "issueToExecuteDelay": 1, + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "numROBEntries": 192, + "fetchQueueSize": 32, + "iewToCommitDelay": 1, + "smtNumFetchingThreads": 1, + "forwardComSize": 5, + "do_checkpoint_insts": true, + "cxx_class": "DerivO3CPU", + "commitToIEWDelay": 1, + "commitWidth": 8, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "smtFetchPolicy": "SingleThread", + "profile": 0, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "role": "MASTER" + }, + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "role": "MASTER" + }, + "LSQDepCheckShift": 4, + "trapLatency": 13, + "iewToDecodeDelay": 1, + "numPhysCCRegs": 0, + "renameToIEWDelay": 2, + "p_state_clk_gate_bins": 20, + "progress_interval": 0, + "LQEntries": 32 + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64d/o3-timing/simerr --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/o3-timing/simerr Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,40 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick +gem5.debug: build/RISCV/mem/cache/cache.cc:162: void Cache::satisfyRequest(PacketPtr, CacheBlk*, bool, bool): Assertion `pkt->getOffset(blkSize) + pkt->getSize() <= blkSize' failed. +Program aborted at tick 46280000 +--- BEGIN LIBC BACKTRACE --- +/home/ar4jc/gem5/build/RISCV/gem5.debug(_Z15print_backtracev+0x32)[0xdabf60] +/home/ar4jc/gem5/build/RISCV/gem5.debug(_Z12abortHandleri+0x6e)[0xdc356a] +/lib/x86_64-linux-gnu/libpthread.so.0(+0x113e0)[0x7f10fe8013e0] +/lib/x86_64-linux-gnu/libc.so.6(gsignal+0x38)[0x7f10fd1e5428] +/lib/x86_64-linux-gnu/libc.so.6(abort+0x16a)[0x7f10fd1e702a] +/lib/x86_64-linux-gnu/libc.so.6(+0x2dbd7)[0x7f10fd1ddbd7] +/lib/x86_64-linux-gnu/libc.so.6(+0x2dc82)[0x7f10fd1ddc82] +/home/ar4jc/gem5/build/RISCV/gem5.debug(_ZN5Cache14satisfyRequestEP6PacketP8CacheBlkbb+0xf3)[0xd27d11] +/home/ar4jc/gem5/build/RISCV/gem5.debug(_ZN5Cache6accessEP6PacketRP8CacheBlkR6CyclesRNSt7__cxx114listIS1_SaIS1_EEE+0xde4)[0xd290f8] +/home/ar4jc/gem5/build/RISCV/gem5.debug(_ZN5Cache13recvTimingReqEP6Packet+0x428)[0xd29f18] +/home/ar4jc/gem5/build/RISCV/gem5.debug(_ZN5Cache11CpuSidePort13recvTimingReqEP6Packet+0xdc)[0xd323a8] +/home/ar4jc/gem5/build/RISCV/gem5.debug(_ZN10MasterPort13sendTimingReqEP6Packet+0x5f)[0xbff495] +/home/ar4jc/gem5/build/RISCV/gem5.debug(_ZN7LSQUnitI9O3CPUImplE4readEP7RequestS3_S3_i+0x105c)[0xfae7f2] +/home/ar4jc/gem5/build/RISCV/gem5.debug(_ZN3LSQI9O3CPUImplE4readEP7RequestS3_S3_i+0x93)[0xfacfcd] +/home/ar4jc/gem5/build/RISCV/gem5.debug(_ZN9FullO3CPUI9O3CPUImplE4readERP7RequestS4_S4_i+0x65)[0xfac4cd] +/home/ar4jc/gem5/build/RISCV/gem5.debug(_ZN11BaseDynInstI9O3CPUImplE15initiateMemReadEmj5FlagsIjE+0x397)[0xfa88a3] +/home/ar4jc/gem5/build/RISCV/gem5.debug(_Z15initiateMemReadI11ExecContextlESt10shared_ptrI9FaultBaseEPT_PN5Trace10InstRecordEmRT0_5FlagsIjE+0x5c)[0x189df93] +/home/ar4jc/gem5/build/RISCV/gem5.debug(_ZNK12RiscvISAInst2Ld11initiateAccEP11ExecContextPN5Trace10InstRecordE+0xb6)[0x1876742] +/home/ar4jc/gem5/build/RISCV/gem5.debug(_ZN13BaseO3DynInstI9O3CPUImplE11initiateAccEv+0x70)[0xfdac52] +/home/ar4jc/gem5/build/RISCV/gem5.debug(_ZN7LSQUnitI9O3CPUImplE11executeLoadER14RefCountingPtrI13BaseO3DynInstIS0_EE+0x144)[0x100d89e] +/home/ar4jc/gem5/build/RISCV/gem5.debug(_ZN3LSQI9O3CPUImplE11executeLoadER14RefCountingPtrI13BaseO3DynInstIS0_EE+0x6b)[0x1009441] +/home/ar4jc/gem5/build/RISCV/gem5.debug(_ZN10DefaultIEWI9O3CPUImplE12executeInstsEv+0x4a9)[0xff57ff] +/home/ar4jc/gem5/build/RISCV/gem5.debug(_ZN10DefaultIEWI9O3CPUImplE4tickEv+0x1a9)[0xff7775] +/home/ar4jc/gem5/build/RISCV/gem5.debug(_ZN9FullO3CPUI9O3CPUImplE4tickEv+0x155)[0xfc37e3] +/home/ar4jc/gem5/build/RISCV/gem5.debug(_ZN9FullO3CPUI9O3CPUImplE9TickEvent7processEv+0x1c)[0xfc7b14] +/home/ar4jc/gem5/build/RISCV/gem5.debug(_ZN10EventQueue10serviceOneEv+0xe9)[0xdbbc1d] +/home/ar4jc/gem5/build/RISCV/gem5.debug(_Z9doSimLoopP10EventQueue+0x1fa)[0xde66e9] +/home/ar4jc/gem5/build/RISCV/gem5.debug(_Z8simulatem+0x301)[0xde6345] +/home/ar4jc/gem5/build/RISCV/gem5.debug[0x109ab70] +/home/ar4jc/gem5/build/RISCV/gem5.debug[0x109ad64] +/usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x7852)[0x7f10feace552] +/usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCodeEx+0x85c)[0x7f10febf801c] +--- END LIBC BACKTRACE --- diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64d/o3-timing/simout --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/o3-timing/simout Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,13 @@ +Redirecting stdout to build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64d/o3-timing/simout +Redirecting stderr to build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64d/o3-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 22 2016 16:06:54 +gem5 started Nov 28 2016 15:02:06 +gem5 executing on ubuntu1604, pid 8569 +command line: /home/ar4jc/gem5/build/RISCV/gem5.debug -d build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64d/o3-timing -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64d/o3-timing + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/config.ini --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/config.ini Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,211 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=atomic +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=AtomicSimpleCPU +children=dtb interrupts isa itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fastmem=false +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +simulate_data_stalls=false +simulate_inst_stalls=false +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +width=1 +workload=system.cpu.workload +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64d/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +eventq_index=0 +in_addr_map=true +kvm_map=true +latency=30000 +latency_var=0 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +range=0:134217727:0:0:0:0 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/config.json --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/config.json Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,289 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.icache_port", + "system.cpu.dcache_port" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "physmem": { + "range": "0:134217727:0:0:0:0", + "latency": 30000, + "name": "physmem", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "kvm_map": true, + "clk_domain": "system.clk_domain", + "power_model": null, + "latency_var": 0, + "bandwidth": "73.000000", + "conf_table_reported": true, + "cxx_class": "SimpleMemory", + "p_state_clk_gate_max": 1000000000000, + "path": "system.physmem", + "null": false, + "type": "SimpleMemory", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "in_addr_map": true + }, + "power_model": null, + "work_cpus_ckpt_count": 0, + "thermal_components": [], + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "work_end_ckpt_count": 0, + "mem_mode": "atomic", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": [ + { + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.itb", + "type": "RiscvTLB", + "size": 64 + }, + "simulate_data_stalls": false, + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "AtomicSimpleCPU", + "max_loads_all_threads": 0, + "system": "system", + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "cpu_id": 0, + "width": 1, + "checker": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "do_quiesce": true, + "type": "AtomicSimpleCPU", + "fastmem": false, + "profile": 0, + "icache_port": { + "peer": "system.membus.slave[1]", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "p_state_clk_gate_min": 1000, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "dcache_port": { + "peer": "system.membus.slave[2]", + "role": "MASTER" + }, + "socket_id": 0, + "power_model": null, + "max_insts_all_threads": 0, + "path": "system.cpu", + "max_loads_any_thread": 0, + "switched_out": false, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64d/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "simulate_inst_stalls": false, + "progress_interval": 0, + "branchPred": null, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/simerr --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/simerr Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,3 @@ +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/simout --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/simple-atomic/simout Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,226 @@ +Redirecting stdout to build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64d/simple-atomic/simout +Redirecting stderr to build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64d/simple-atomic/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 2 2016 20:34:02 +gem5 started Nov 3 2016 19:09:02 +gem5 executing on ubuntu1604, pid 22243 +command line: /home/ar4jc/gem5/build/RISCV/gem5.debug -d build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64d/simple-atomic -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64d/simple-atomic + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +fld: PASS +fsd: PASS +fmadd.d: PASS +fmadd.d, quiet NaN: PASS +fmadd.d, signaling NaN: PASS +fmadd.d, infinity: PASS +fmadd.d, -infinity: PASS +fmsub.d: PASS +fmsub.d, quiet NaN: PASS +fmsub.d, signaling NaN: PASS +fmsub.d, infinity: PASS +fmsub.d, -infinity: PASS +fmsub.d, subtract infinity: PASS +fnmsub.d: PASS +fnmsub.d, quiet NaN: PASS +fnmsub.d, signaling NaN: PASS +fnmsub.d, infinity: PASS +fnmsub.d, -infinity: PASS +fnmsub.d, subtract infinity: PASS +fnmadd.d: PASS +fnmadd.d, quiet NaN: PASS +fnmadd.d, signaling NaN: PASS +fnmadd.d, infinity: PASS +fnmadd.d, -infinity: PASS +fadd.d: PASS +fadd.d, quiet NaN: PASS +fadd.d, signaling NaN: PASS +fadd.d, infinity: PASS +fadd.d, -infinity: PASS +fsub.d: PASS +fsub.d, quiet NaN: PASS +fsub.d, signaling NaN: PASS +fsub.d, infinity: PASS +fsub.d, -infinity: PASS +fsub.d, subtract infinity: PASS +fmul.d: PASS +fmul.d, quiet NaN: PASS +fmul.d, signaling NaN: PASS +fmul.d, infinity: PASS +fmul.d, -infinity: PASS +fmul.d, 0*infinity: PASS +fmul.d, overflow: PASS +fmul.d, underflow: PASS +fdiv.d: PASS +fdiv.d, quiet NaN: PASS +fdiv.d, signaling NaN: PASS +fdiv.d/0: PASS +fdiv.d/infinity: PASS +fdiv.d, infinity/infinity: PASS +fdiv.d, 0/0: PASS +fdiv.d, infinity/0: PASS +fdiv.d, 0/infinity: PASS +fdiv.d, underflow: PASS +fdiv.d, overflow: PASS +fsqrt.d: PASS +fsqrt.d, NaN: PASS +fsqrt.d, quiet NaN: PASS +fsqrt.d, signaling NaN: PASS +fsqrt.d, infinity: PASS +fsgnj.d, ++: PASS +fsgnj.d, +-: PASS +fsgnj.d, -+: PASS +fsgnj.d, --: PASS +fsgnj.d, quiet NaN: PASS +fsgnj.d, signaling NaN: PASS +fsgnj.d, inject NaN: PASS +fsgnj.d, inject -NaN: PASS +fsgnjn.d, ++: PASS +fsgnjn.d, +-: PASS +fsgnjn.d, -+: PASS +fsgnjn.d, --: PASS +fsgnjn.d, quiet NaN: PASS +fsgnjn.d, signaling NaN: PASS +fsgnjn.d, inject NaN: PASS +fsgnjn.d, inject NaN: PASS +fsgnjx.d, ++: PASS +fsgnjx.d, +-: PASS +fsgnjx.d, -+: PASS +fsgnjx.d, --: PASS +fsgnjx.d, quiet NaN: PASS +fsgnjx.d, signaling NaN: PASS +fsgnjx.d, inject NaN: PASS +fsgnjx.d, inject NaN: PASS +fmin.d: PASS +fmin.d, -infinity: PASS +fmin.d, infinity: PASS +fmin.d, quiet NaN first: PASS +fmin.d, quiet NaN second: PASS +fmin.d, quiet NaN both: PASS +fmin.d, signaling NaN first: PASS +fmin.d, signaling NaN second: PASS +fmin.d, signaling NaN both: PASS +fmax.d: PASS +fmax.d, -infinity: PASS +fmax.d, infinity: PASS +fmax.d, quiet NaN first: PASS +fmax.d, quiet NaN second: PASS +fmax.d, quiet NaN both: PASS +fmax.d, signaling NaN first: PASS +fmax.d, signaling NaN second: PASS +fmax.d, signaling NaN both: PASS +fcvt.s.d: PASS +fcvt.s.d, quiet NaN: PASS +fcvt.s.d, signaling NaN: PASS +fcvt.s.d, infinity: PASS +fcvt.s.d, overflow: PASS +fcvt.s.d, underflow: PASS +fcvt.d.s: PASS +fcvt.d.s, quiet NaN: PASS +fcvt.d.s, signaling NaN: PASS +fcvt.d.s, infinity: PASS +feq.d, equal: PASS +feq.d, not equal: PASS +feq.d, 0 == -0: PASS +feq.d, quiet NaN first: PASS +feq.d, quiet NaN second: PASS +feq.d, quiet NaN both: PASS +feq.d, signaling NaN first: PASS +feq.d, signaling NaN second: PASS +feq.d, signaling NaN both: PASS +flt.d, equal: PASS +flt.d, less: PASS +flt.d, greater: PASS +flt.d, quiet NaN first: PASS +flt.d, quiet NaN second: PASS +flt.d, quiet NaN both: PASS +flt.d, signaling NaN first: PASS +flt.d, signaling NaN second: PASS +flt.d, signaling NaN both: PASS +fle.d, equal: PASS +fle.d, less: PASS +fle.d, greater: PASS +fle.d, 0 == -0: PASS +fle.d, quiet NaN first: PASS +fle.d, quiet NaN second: PASS +fle.d, quiet NaN both: PASS +fle.d, signaling NaN first: PASS +fle.d, signaling NaN second: PASS +fle.d, signaling NaN both: PASS +fclass.d, -infinity: PASS +fclass.d, -normal: PASS +fclass.d, -subnormal: PASS +fclass.d, -0.0: PASS +fclass.d, 0.0: PASS +fclass.d, subnormal: PASS +fclass.d, normal: PASS +fclass.d, infinity: PASS +fclass.d, signaling NaN: PASS +fclass.s, quiet NaN: PASS +fcvt.w.d, truncate positive: PASS +fcvt.w.d, truncate negative: PASS +fcvt.w.d, 0.0: PASS +fcvt.w.d, -0.0: PASS +fcvt.w.d, overflow: PASS +fcvt.w.d, underflow: PASS +fcvt.w.d, infinity: PASS +fcvt.w.d, -infinity: PASS +fcvt.w.d, quiet NaN: PASS +fcvt.w.d, quiet -NaN: PASS +fcvt.w.d, signaling NaN: PASS +fcvt.wu.d, truncate positive: PASS +fcvt.wu.d, truncate negative: PASS +fcvt.wu.d, 0.0: PASS +fcvt.wu.d, -0.0: PASS +fcvt.wu.d, overflow: PASS +fcvt.wu.d, underflow: PASS +fcvt.wu.d, infinity: PASS +fcvt.wu.d, -infinity: PASS +fcvt.wu.d, quiet NaN: PASS +fcvt.wu.d, quiet -NaN: PASS +fcvt.wu.d, signaling NaN: PASS +fcvt.d.w, 0: PASS +fcvt.d.w, negative: PASS +fcvt.d.w, truncate: PASS +fcvt.d.wu, 0: PASS +fcvt.d.wu: PASS +fcvt.d.wu, truncate: PASS +fcvt.l.d, truncate positive: PASS +fcvt.l.d, truncate negative: PASS +fcvt.l.d, 0.0: PASS +fcvt.l.d, -0.0: PASS +fcvt.l.d, 32-bit overflow: PASS +fcvt.l.d, overflow: PASS +fcvt.l.d, underflow: PASS +fcvt.l.d, infinity: PASS +fcvt.l.d, -infinity: PASS +fcvt.l.d, quiet NaN: PASS +fcvt.l.d, quiet -NaN: PASS +fcvt.l.d, signaling NaN: PASS +fcvt.lu.d, truncate positive: PASS +fcvt.lu.d, truncate negative: PASS +fcvt.lu.d, 0.0: PASS +fcvt.lu.d, -0.0: PASS +fcvt.lu.d, 32-bit overflow: PASS +fcvt.lu.d, overflow: PASS +fcvt.lu.d, underflow: PASS +fcvt.lu.d, infinity: PASS +fcvt.lu.d, -infinity: PASS +fcvt.lu.d, quiet NaN: PASS +fcvt.lu.d, quiet -NaN: PASS +fcvt.lu.d, signaling NaN: PASS +fmv.x.d, positive: PASS +fmv.x.d, negative: PASS +fmv.x.d, 0.0: PASS +fmv.x.d, -0.0: PASS +fcvt.d.l, 0: PASS +fcvt.d.l, negative: PASS +fcvt.d.l, 32-bit truncate: PASS +fcvt.d.lu, 0: PASS +fcvt.d.lu: PASS +fcvt.d.lu, 32-bit truncate: PASS +fmv.d.x: PASS +Exiting @ tick 192791500 because target called exit() diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/config.json --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/config.json Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,502 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.l2cache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "physmem": { + "range": "0:134217727:0:0:0:0", + "latency": 30000, + "name": "physmem", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "kvm_map": true, + "clk_domain": "system.clk_domain", + "power_model": null, + "latency_var": 0, + "bandwidth": "73.000000", + "conf_table_reported": true, + "cxx_class": "SimpleMemory", + "p_state_clk_gate_max": 1000000000000, + "path": "system.physmem", + "null": false, + "type": "SimpleMemory", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "in_addr_map": true + }, + "power_model": null, + "work_cpus_ckpt_count": 0, + "thermal_components": [], + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "work_end_ckpt_count": 0, + "mem_mode": "timing", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": [ + { + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.itb", + "type": "RiscvTLB", + "size": 64 + }, + "system": "system", + "icache": { + "cpu_side": { + "peer": "system.cpu.icache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 131072, + "tags": { + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.icache.tags", + "hit_latency": 2, + "block_size": 64, + "type": "LRU", + "size": 131072 + }, + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[0]", + "role": "MASTER" + }, + "type": "Cache", + "writeback_clean": true, + "p_state_clk_gate_min": 1000, + "hit_latency": 2, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": true, + "prefetch_on_access": false, + "path": "system.cpu.icache", + "mshrs": 4, + "name": "icache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "TimingSimpleCPU", + "max_loads_all_threads": 0, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "cpu_id": 0, + "checker": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "toL2Bus": { + "point_of_coherency": false, + "system": "system", + "response_latency": 1, + "cxx_class": "CoherentXBar", + "forward_latency": 0, + "clk_domain": "system.cpu_clk_domain", + "width": 32, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.cpu.l2cache.cpu_side" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 1, + "slave": { + "peer": [ + "system.cpu.icache.mem_side", + "system.cpu.dcache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.cpu.toL2Bus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 0 + }, + "power_model": null, + "path": "system.cpu.toL2Bus", + "snoop_response_latency": 1, + "name": "toL2Bus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "do_quiesce": true, + "type": "TimingSimpleCPU", + "profile": 0, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "p_state_clk_gate_min": 1000, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "role": "MASTER" + }, + "socket_id": 0, + "power_model": null, + "max_insts_all_threads": 0, + "l2cache": { + "cpu_side": { + "peer": "system.cpu.toL2Bus.master[0]", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 20, + "cxx_class": "Cache", + "size": 2097152, + "tags": { + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 8, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.l2cache.tags", + "hit_latency": 20, + "block_size": 64, + "type": "LRU", + "size": 2097152 + }, + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.membus.slave[1]", + "role": "MASTER" + }, + "type": "Cache", + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "hit_latency": 20, + "tgts_per_mshr": 12, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.l2cache", + "mshrs": 20, + "name": "l2cache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 8 + }, + "path": "system.cpu", + "max_loads_any_thread": 0, + "switched_out": false, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64a/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "progress_interval": 0, + "branchPred": null, + "dcache": { + "cpu_side": { + "peer": "system.cpu.dcache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 262144, + "tags": { + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.dcache.tags", + "hit_latency": 2, + "block_size": 64, + "type": "LRU", + "size": 262144 + }, + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[1]", + "role": "MASTER" + }, + "type": "Cache", + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "hit_latency": 2, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.dcache", + "mshrs": 4, + "name": "dcache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/simerr --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/simerr Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,3 @@ +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/simout --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/simout Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,49 @@ +Redirecting stdout to build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64a/simple-timing/simout +Redirecting stderr to build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64a/simple-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 2 2016 20:34:02 +gem5 started Nov 3 2016 18:48:07 +gem5 executing on ubuntu1604, pid 21740 +command line: /home/ar4jc/gem5/build/RISCV/gem5.debug -d build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64a/simple-timing -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64a/simple-timing + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +lr.w/sc.w: PASS +sc.w, no preceding lr.d: PASS +amoswap.w: PASS +amoswap.w, sign extend: PASS +amoswap.w, truncate: PASS +amoadd.w: PASS +amoadd.w, truncate/overflow: PASS +amoadd.w, sign extend: PASS +amoxor.w, truncate: PASS +amoxor.w, sign extend: PASS +amoand.w, truncate: PASS +amoand.w, sign extend: PASS +amoor.w, truncate: PASS +amoor.w, sign extend: PASS +amomin.w, truncate: PASS +amomin.w, sign extend: PASS +amomax.w, truncate: PASS +amomax.w, sign extend: PASS +amominu.w, truncate: PASS +amominu.w, sign extend: PASS +amomaxu.w, truncate: PASS +amomaxu.w, sign extend: PASS +lr.d/sc.d: PASS +sc.d, no preceding lr.d: PASS +amoswap.d: PASS +amoadd.d: PASS +amoadd.d, overflow: PASS +amoxor.d (1): PASS +amoxor.d (0): PASS +amoand.d: PASS +amoor.d: PASS +amomin.d: PASS +amomax.d: PASS +amominu.d: PASS +amomaxu.d: PASS +Exiting @ tick 210277500 because target called exit() diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/stats.txt --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/stats.txt Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,529 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000210 # Number of seconds simulated +sim_ticks 210277500 # Number of ticks simulated +final_tick 210277500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 52840 # Simulator instruction rate (inst/s) +host_op_rate 52854 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 99272161 # Simulator tick rate (ticks/s) +host_mem_usage 275248 # Number of bytes of host memory used +host_seconds 2.12 # Real time elapsed on the host +sim_insts 111923 # Number of instructions simulated +sim_ops 111954 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 210277500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 40384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 17152 # Number of bytes read from this memory +system.physmem.bytes_read::total 57536 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 40384 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 40384 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 631 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 268 # Number of read requests responded to by this memory +system.physmem.num_reads::total 899 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 192050980 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 81568404 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 273619384 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 192050980 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 192050980 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 192050980 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 81568404 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 273619384 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 210277500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 45 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 210277500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 420555 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 111923 # Number of instructions committed +system.cpu.committedOps 111954 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 111955 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 8590 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 17351 # number of instructions that are conditional controls +system.cpu.num_int_insts 111955 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 149947 # number of times the integer registers were read +system.cpu.num_int_register_writes 74477 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 42510 # number of memory refs +system.cpu.num_load_insts 22348 # Number of load instructions +system.cpu.num_store_insts 20162 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 420555 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 25941 # Number of branches fetched +system.cpu.op_class::No_OpClass 45 0.04% 0.04% # Class of executed instruction +system.cpu.op_class::IntAlu 69340 61.91% 61.95% # Class of executed instruction +system.cpu.op_class::IntMult 105 0.09% 62.04% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 62.04% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 62.04% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 62.04% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 62.04% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 62.04% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 62.04% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 62.04% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 62.04% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 62.04% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 62.04% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 62.04% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 62.04% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 62.04% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 62.04% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 62.04% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 62.04% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 62.04% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 62.04% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 62.04% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 62.04% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 62.04% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 62.04% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 62.04% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 62.04% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 62.04% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 62.04% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 62.04% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 62.04% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 62.04% # Class of executed instruction +system.cpu.op_class::MemRead 22348 19.95% 82.00% # Class of executed instruction +system.cpu.op_class::MemWrite 20162 18.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 112000 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 210277500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 219.655926 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42241 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 268 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 157.615672 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 219.655926 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.053627 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.053627 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 268 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.065430 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 85286 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 85286 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 210277500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 22281 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22281 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 19954 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 19954 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 2 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 2 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 4 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 4 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 42235 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42235 # number of 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ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 65 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 636 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 268 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 904 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 636 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 268 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 904 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.992138 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.992138 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992138 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.994469 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992138 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.994469 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60501.584786 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60501.584786 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60501.584786 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60501.112347 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60501.584786 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60501.112347 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 203 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 203 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 631 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 631 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 65 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 65 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 631 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 268 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 899 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 631 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 268 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 899 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10251500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10251500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 31866500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 31866500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3282500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3282500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31866500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13534000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 45400500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31866500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13534000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 45400500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.992138 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.992138 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992138 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.994469 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992138 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.994469 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50501.584786 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50501.584786 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50501.584786 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.112347 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50501.584786 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.112347 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 935 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 31 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 210277500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 701 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 31 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 203 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 203 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 636 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 65 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1303 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 536 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1839 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 42688 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17152 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 59840 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 904 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 904 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 904 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 498500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 954000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 402000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 899 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 210277500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 696 # Transaction distribution +system.membus.trans_dist::ReadExReq 203 # Transaction distribution +system.membus.trans_dist::ReadExResp 203 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 696 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1798 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1798 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 57536 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 57536 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 899 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 899 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 899 # Request fanout histogram +system.membus.reqLayer0.occupancy 900000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 4495000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 2.1 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/config.ini --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/config.ini Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,896 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=MinorCPU +children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload +branchPred=system.cpu.branchPred +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +decodeCycleInput=true +decodeInputBufferSize=3 +decodeInputWidth=2 +decodeToExecuteForwardDelay=1 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +enableIdling=true +eventq_index=0 +executeAllowEarlyMemoryIssue=true +executeBranchDelay=1 +executeCommitLimit=2 +executeCycleInput=true +executeFuncUnits=system.cpu.executeFuncUnits +executeInputBufferSize=7 +executeInputWidth=2 +executeIssueLimit=2 +executeLSQMaxStoreBufferStoresPerCycle=2 +executeLSQRequestsQueueSize=1 +executeLSQStoreBufferSize=5 +executeLSQTransfersQueueSize=2 +executeMaxAccessesInMemory=2 +executeMemoryCommitLimit=1 +executeMemoryIssueLimit=1 +executeMemoryWidth=0 +executeSetTraceTimeOnCommit=true +executeSetTraceTimeOnIssue=false +fetch1FetchLimit=1 +fetch1LineSnapWidth=0 +fetch1LineWidth=0 +fetch1ToFetch2BackwardDelay=1 +fetch1ToFetch2ForwardDelay=1 +fetch2CycleInput=true +fetch2InputBufferSize=2 +fetch2ToDecodeForwardDelay=1 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +threadPolicy=RoundRobin +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TournamentBP +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +useIndirect=true + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +hit_latency=2 +is_read_only=false +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=262144 + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.executeFuncUnits] +type=MinorFUPool +children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 +eventq_index=0 +funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 + +[system.cpu.executeFuncUnits.funcUnits0] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits0.timings + +[system.cpu.executeFuncUnits.funcUnits0.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits0.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits1] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits1.timings + +[system.cpu.executeFuncUnits.funcUnits1.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits1.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits2] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits2.timings + +[system.cpu.executeFuncUnits.funcUnits2.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntMult + +[system.cpu.executeFuncUnits.funcUnits2.timings] +type=MinorFUTiming +children=opClasses +description=Mul +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses +srcRegsRelativeLats=0 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits3] +type=MinorFU +children=opClasses +cantForwardFromFUIndices= +eventq_index=0 +issueLat=9 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses +opLat=9 +timings= + +[system.cpu.executeFuncUnits.funcUnits3.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntDiv + +[system.cpu.executeFuncUnits.funcUnits4] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses +opLat=6 +timings=system.cpu.executeFuncUnits.funcUnits4.timings + +[system.cpu.executeFuncUnits.funcUnits4.opClasses] +type=MinorOpClassSet +children=opClasses00 opClasses01 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+write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/config.json --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64d/minor-timing/config.json Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,1205 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.l2cache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + 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"opClasses2", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2", + "type": "MinorOpClass" + }, + { + "opClass": "FloatMemWrite", + "name": "opClasses3", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3", + "type": "MinorOpClass" + } + ], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits5.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [ + { + "extraAssumedLat": 2, + "description": "Mem", + "srcRegsRelativeLats": [ + 1 + ], + "suppress": false, + "mask": 0, + "extraCommitLat": 0, + "eventq_index": 0, + "opClasses": { + "name": "opClasses", + "opClasses": [], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits5.timings.opClasses", + "type": "MinorOpClassSet" + }, + "cxx_class": "MinorFUTiming", + "path": "system.cpu.executeFuncUnits.funcUnits5.timings", + "extraCommitLatExpr": null, + "type": "MinorFUTiming", + "match": 0, + "name": "timings" + } + ], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits5", + "type": "MinorFU" + }, + { + "issueLat": 1, + "opLat": 1, + "name": "funcUnits6", + "cantForwardFromFUIndices": [], + "opClasses": { + "name": "opClasses", + "opClasses": [ + { + "opClass": "IprAccess", + "name": "opClasses0", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses0", + "type": "MinorOpClass" + }, + { + "opClass": "InstPrefetch", + "name": "opClasses1", + "eventq_index": 0, + "cxx_class": "MinorOpClass", + "path": "system.cpu.executeFuncUnits.funcUnits6.opClasses.opClasses1", + "type": "MinorOpClass" + } + ], + "eventq_index": 0, + "cxx_class": "MinorOpClassSet", + "path": "system.cpu.executeFuncUnits.funcUnits6.opClasses", + "type": "MinorOpClassSet" + }, + "eventq_index": 0, + "timings": [], + "cxx_class": "MinorFU", + "path": "system.cpu.executeFuncUnits.funcUnits6", + "type": "MinorFU" + } + ], + "type": "MinorFUPool" + }, + "switched_out": false, + "power_model": null, + "max_insts_all_threads": 0, + "executeSetTraceTimeOnIssue": false, + "fetch2InputBufferSize": 2, + "profile": 0, + "fetch2ToDecodeForwardDelay": 1, + "executeInputWidth": 2, + "decodeToExecuteForwardDelay": 1, + "executeLSQRequestsQueueSize": 1, + "fetch2CycleInput": true, + "executeMaxAccessesInMemory": 2, + "enableIdling": true, + "executeLSQStoreBufferSize": 5, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64d/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "executeSetTraceTimeOnCommit": true, + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + }, + "threadPolicy": "RoundRobin", + "executeCommitLimit": 2, + "fetch1LineWidth": 0, + "branchPred": { + "numThreads": 1, + "BTBEntries": 4096, + "cxx_class": "TournamentBP", + "indirectPathLength": 3, + "globalCtrBits": 2, + "choicePredictorSize": 8192, + "indirectHashGHR": true, + "eventq_index": 0, + "localHistoryTableSize": 2048, + "type": "TournamentBP", + "indirectSets": 256, + "indirectWays": 2, + "choiceCtrBits": 2, + "useIndirect": true, + "localCtrBits": 2, + "path": "system.cpu.branchPred", + "localPredictorSize": 2048, + "RASSize": 16, + "globalPredictorSize": 8192, + "name": "branchPred", + "indirectHashTargets": true, + "instShiftAmt": 2, + "indirectTagSize": 16, + "BTBTagSize": 16 + }, + "dcache": { + "cpu_side": { + "peer": "system.cpu.dcache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 262144, + "tags": { + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.dcache.tags", + "hit_latency": 2, + "block_size": 64, + "type": "LRU", + "size": 262144 + }, + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[1]", + "role": "MASTER" + }, + "type": "Cache", + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "hit_latency": 2, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.dcache", + "mshrs": 4, + "name": "dcache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "path": "system.cpu", + "fetch1ToFetch2ForwardDelay": 1, + "decodeInputBufferSize": 3 + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/stats.txt --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/stats.txt Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,156 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000056 # Number of seconds simulated +sim_ticks 55999500 # Number of ticks simulated +final_tick 55999500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 55865 # Simulator instruction rate (inst/s) +host_op_rate 55880 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 27950647 # Simulator tick rate (ticks/s) +host_mem_usage 264992 # Number of bytes of host memory used +host_seconds 2.00 # Real time elapsed on the host +sim_insts 111923 # Number of instructions simulated +sim_ops 111954 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 55999500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 447876 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 145094 # Number of bytes read from this memory +system.physmem.bytes_read::total 592970 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 447876 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 447876 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 113319 # Number of bytes written to this memory +system.physmem.bytes_written::total 113319 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 111969 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 22348 # Number of read requests responded to by this memory +system.physmem.num_reads::total 134317 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 20159 # Number of write requests responded to by this memory +system.physmem.num_writes::total 20159 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 7997857124 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2590987420 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10588844543 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7997857124 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7997857124 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 2023571639 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2023571639 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7997857124 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4614559059 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 12612416182 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 55999500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 45 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 55999500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 112000 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 111923 # Number of instructions committed +system.cpu.committedOps 111954 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 111955 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 8590 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 17351 # number of instructions that are conditional controls +system.cpu.num_int_insts 111955 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 149947 # number of times the integer registers were read +system.cpu.num_int_register_writes 74477 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 42510 # number of memory refs +system.cpu.num_load_insts 22348 # Number of load instructions +system.cpu.num_store_insts 20162 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 112000 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 25941 # Number of branches fetched +system.cpu.op_class::No_OpClass 45 0.04% 0.04% # Class of executed instruction +system.cpu.op_class::IntAlu 69340 61.91% 61.95% # Class of executed instruction +system.cpu.op_class::IntMult 105 0.09% 62.04% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 62.04% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 62.04% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 62.04% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 62.04% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 62.04% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 62.04% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 62.04% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 62.04% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 62.04% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 62.04% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 62.04% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 62.04% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 62.04% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 62.04% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 62.04% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 62.04% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 62.04% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 62.04% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 62.04% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 62.04% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 62.04% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 62.04% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 62.04% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 62.04% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 62.04% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 62.04% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 62.04% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 62.04% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 62.04% # Class of executed instruction +system.cpu.op_class::MemRead 22348 19.95% 82.00% # Class of executed instruction +system.cpu.op_class::MemWrite 20162 18.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 112000 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 55999500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 134315 # Transaction distribution +system.membus.trans_dist::ReadResp 134317 # Transaction distribution +system.membus.trans_dist::WriteReq 20157 # Transaction distribution +system.membus.trans_dist::WriteResp 20157 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 2 # Transaction distribution +system.membus.trans_dist::StoreCondReq 4 # Transaction distribution +system.membus.trans_dist::StoreCondResp 4 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 223938 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 85018 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 308956 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 447876 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 258425 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 706301 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 154478 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 154478 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 154478 # Request fanout histogram + +---------- End Simulation Statistics ---------- diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/config.ini --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/config.ini Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,1265 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 + +[system] +type=System +children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges=0:268435455:0:0:0:0 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.sys_port_proxy.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=TimingSimpleCPU +children=clk_domain dtb interrupts isa itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu.clk_domain +cpu_id=0 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1] +icache_port=system.ruby.l1_cntrl0.sequencer.slave[0] + +[system.cpu.clk_domain] +type=SrcClockDomain +clock=1 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64a/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000 + +[system.mem_ctrls] +type=DRAMCtrl +IDD0=0.055000 +IDD02=0.000000 +IDD2N=0.032000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.032000 +IDD2P12=0.000000 +IDD3N=0.038000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.038000 +IDD3P12=0.000000 +IDD4R=0.157000 +IDD4R2=0.000000 +IDD4W=0.125000 +IDD4W2=0.000000 +IDD5=0.235000 +IDD52=0.000000 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int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_links0 int_links1 int_links2 int_links3 routers0 routers1 routers2 +adaptive_routing=false +buffer_size=0 +clk_domain=system.ruby.clk_domain +control_msg_size=8 +default_p_state=UNDEFINED +endpoint_bandwidth=1000 +eventq_index=0 +ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 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+p_state_clk_gate_min=1 +power_model=Null +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_ruby_tester=false +version=0 +slave=system.system_port + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/config.json --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/config.json Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,1734 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1, + "memories": [ + "system.mem_ctrls" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + 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"MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers16", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers17", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers17", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers18", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers18", + "type": "MessageBuffer" + }, + { + "ordered": true, + "name": "port_buffers19", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.network.routers2.port_buffers19", + "type": "MessageBuffer" + } + ] + } + ], + "power_model": null, + "netifs": [], + "control_msg_size": 8, + "buffer_size": 0, + "endpoint_bandwidth": 1000, + "ruby_system": "system.ruby", + "name": "network", + "p_state_clk_gate_bins": 20, + "ext_links": [ + { + "latency": 1, + "name": "ext_links0", + "weight": 1, + "ext_node": "system.ruby.l1_cntrl0", + "link_id": 0, + "eventq_index": 0, + "cxx_class": "SimpleExtLink", + "path": "system.ruby.network.ext_links0", + "int_node": "system.ruby.network.routers0", + "type": "SimpleExtLink", + "bandwidth_factor": 16 + }, + { + "latency": 1, + "name": "ext_links1", + "weight": 1, + "ext_node": "system.ruby.dir_cntrl0", + "link_id": 1, + "eventq_index": 0, + "cxx_class": "SimpleExtLink", + "path": "system.ruby.network.ext_links1", + "int_node": "system.ruby.network.routers1", + "type": "SimpleExtLink", + "bandwidth_factor": 16 + } + ], + "number_of_virtual_networks": 5, + "path": "system.ruby.network" + }, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.ruby.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "randomization": false, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "phys_mem": null, + "type": "RubySystem", + "p_state_clk_gate_min": 1, + "hot_lines": false, + "power_model": null, + "path": "system.ruby", + "memctrl_clk_domain": { + "name": "memctrl_clk_domain", + "clk_domain": "system.ruby.clk_domain", + "eventq_index": 0, + "cxx_class": "DerivedClockDomain", + "path": "system.ruby.memctrl_clk_domain", + "type": "DerivedClockDomain", + "clk_divider": 3 + }, + "name": "ruby", + "p_state_clk_gate_bins": 20, + "block_size_bytes": 64, + "access_backing_store": false, + "number_of_virtual_networks": 5, + "num_of_sequencers": 1, + "dir_cntrl0": { + "system": "system", + "cluster_id": 0, + "responseFromMemory": { + "ordered": false, + "name": "responseFromMemory", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.responseFromMemory", + "type": "MessageBuffer" + }, + "cxx_class": "Directory_Controller", + "forwardFromDir": { + "ordered": false, + "name": "forwardFromDir", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "master": { + "peer": "system.ruby.network.slave[4]", + "role": "MASTER" + }, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.forwardFromDir", + "type": "MessageBuffer" + }, + "dmaRequestToDir": { + "ordered": true, + "name": "dmaRequestToDir", + "cxx_class": "MessageBuffer", + "slave": { + "peer": "system.ruby.network.master[3]", + "role": "SLAVE" + }, + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.dmaRequestToDir", + "type": "MessageBuffer" + }, + "type": "Directory_Controller", + "recycle_latency": 10, + "clk_domain": "system.ruby.clk_domain", + "version": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "directory_latency": 12, + "number_of_TBEs": 256, + "to_memory_controller_latency": 1, + "p_state_clk_gate_min": 1, + "responseFromDir": { + "ordered": false, + "name": "responseFromDir", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "master": { + "peer": "system.ruby.network.slave[2]", + "role": "MASTER" + }, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.responseFromDir", + "type": "MessageBuffer" + }, + "transitions_per_cycle": 4, + "memory": { + "peer": "system.mem_ctrls.port", + "role": "MASTER" + }, + "power_model": null, + "buffer_size": 0, + "ruby_system": "system.ruby", + "requestToDir": { + "ordered": true, + "name": "requestToDir", + "cxx_class": "MessageBuffer", + "slave": { + "peer": "system.ruby.network.master[2]", + "role": "SLAVE" + }, + "randomization": false, + "eventq_index": 0, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.requestToDir", + "type": "MessageBuffer" + }, + "dmaResponseFromDir": { + "ordered": true, + "name": "dmaResponseFromDir", + "cxx_class": "MessageBuffer", + "randomization": false, + "eventq_index": 0, + "master": { + "peer": "system.ruby.network.slave[3]", + "role": "MASTER" + }, + "buffer_size": 0, + "path": "system.ruby.dir_cntrl0.dmaResponseFromDir", + "type": "MessageBuffer" + }, + "name": "dir_cntrl0", + "p_state_clk_gate_bins": 20, + "directory": { + "name": "directory", + "version": 0, + "eventq_index": 0, + "cxx_class": "DirectoryMemory", + "path": "system.ruby.dir_cntrl0.directory", + "type": "RubyDirectoryMemory", + "numa_high_bit": 5, + "size": 268435456 + }, + "path": "system.ruby.dir_cntrl0" + } + }, + "work_end_ckpt_count": 0, + "mem_mode": "timing", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": { + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.itb", + "type": "RiscvTLB", + "size": 64 + }, + "system": "system", + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "TimingSimpleCPU", + "max_loads_all_threads": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "function_trace_start": 0, + "cpu_id": 0, + "checker": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "do_quiesce": true, + "type": "TimingSimpleCPU", + "profile": 0, + "icache_port": { + "peer": "system.ruby.l1_cntrl0.sequencer.slave[0]", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "p_state_clk_gate_min": 1, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "dcache_port": { + "peer": "system.ruby.l1_cntrl0.sequencer.slave[1]", + "role": "MASTER" + }, + "socket_id": 0, + "power_model": null, + "max_insts_all_threads": 0, + "path": "system.cpu", + "max_loads_any_thread": 0, + "switched_out": false, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64a/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "progress_interval": 0, + "branchPred": null, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + }, + "multi_thread": false, + "mem_ctrls": [ + { + "static_frontend_latency": 10, + "tRFC": 260, + "activation_limit": 4, + "in_addr_map": true, + "IDD3N2": "0.0", + "tWTR": 8, + "IDD52": "0.0", + "clk_domain": "system.clk_domain", + "channels": 1, + "write_buffer_size": 64, + "device_bus_width": 8, + "VDD": "1.5", + "write_high_thresh_perc": 85, + "cxx_class": "DRAMCtrl", + "bank_groups_per_rank": 0, + "IDD2N2": "0.0", + "port": { + "peer": "system.ruby.dir_cntrl0.memory", + "role": "SLAVE" + }, + "tCCD_L": 0, + "IDD2N": "0.032", + "p_state_clk_gate_min": 1, + "null": false, + "IDD2P1": "0.032", + "eventq_index": 0, + "tRRD": 6, + "tRTW": 3, + "IDD4R": "0.157", + "burst_length": 8, + "tRTP": 8, + "IDD4W": "0.125", + "tWR": 15, + "banks_per_rank": 8, + "devices_per_rank": 8, + "IDD2P02": "0.0", + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "IDD6": "0.02", + "IDD5": "0.235", + "tRCD": 14, + "type": "DRAMCtrl", + "IDD3P02": "0.0", + "tRRD_L": 0, + "IDD0": "0.055", + "IDD62": "0.0", + "min_writes_per_switch": 16, + "mem_sched_policy": "frfcfs", + "IDD02": "0.0", + "IDD2P0": "0.0", + "ranks_per_channel": 2, + "page_policy": "open_adaptive", + "IDD4W2": "0.0", + "tCS": 3, + "power_model": null, + "tCL": 14, + "read_buffer_size": 32, + "conf_table_reported": true, + "tCK": 1, + "tRAS": 35, + "tRP": 14, + "tBURST": 5, + "path": "system.mem_ctrls", + "tXP": 6, + "tXS": 270, + "addr_mapping": "RoRaBaCoCh", + "IDD3P0": "0.0", + "IDD3P1": "0.038", + "IDD3N": "0.038", + "name": "mem_ctrls", + "tXSDLL": 0, + "device_size": 536870912, + "kvm_map": true, + "dll": true, + "tXAW": 30, + "write_low_thresh_perc": 50, + "range": "0:268435455:5:19:0:0", + "VDD2": "0.0", + "IDD2P12": "0.0", + "p_state_clk_gate_bins": 20, + "tXPDLL": 0, + "IDD4R2": "0.0", + "device_rowbuffer_size": 1024, + "static_backend_latency": 10, + "max_accesses_per_row": 16, + "IDD3P12": "0.0", + "tREFI": 7800 + } + ], + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/simerr --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/simerr Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,11 @@ +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick +warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/simout --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/simout Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,16 @@ +Redirecting stdout to build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64a/simple-timing-ruby/simout +Redirecting stderr to build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64a/simple-timing-ruby/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 2 2016 20:34:02 +gem5 started Nov 3 2016 18:48:10 +gem5 executing on ubuntu1604, pid 21741 +command line: /home/ar4jc/gem5/build/RISCV/gem5.debug -d build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64a/simple-timing-ruby -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64a/simple-timing-ruby + +Global frequency set at 1000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +lr.w/sc.w: PASS +sc.w, no preceding lr.d: FAIL (expected (1, 200); found (1, 50)) +Exiting @ tick 859601 because target called exit() diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/stats.txt --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing-ruby/stats.txt Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,674 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000860 # Number of seconds simulated +sim_ticks 859601 # Number of ticks simulated +final_tick 859601 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000 # Frequency of simulated ticks +host_inst_rate 8765 # Simulator instruction rate (inst/s) +host_op_rate 8765 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 114515 # Simulator tick rate (ticks/s) +host_mem_usage 441644 # Number of bytes of host memory used +host_seconds 7.51 # Real time elapsed on the host +sim_insts 65796 # Number of instructions simulated +sim_ops 65796 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1 # Clock period in ticks +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 859601 # Cumulative time (in ticks) in various power states +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 982912 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 982912 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 982656 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 982656 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 15358 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 15358 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 15354 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 15354 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 1143451439 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 1143451439 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 1143153626 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 1143153626 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 2286605064 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 2286605064 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 15358 # Number of read requests accepted +system.mem_ctrls.writeReqs 15354 # Number of write requests accepted +system.mem_ctrls.readBursts 15358 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 15354 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 266816 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 716096 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 276992 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 982912 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 982656 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 11189 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 10997 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 46 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 57 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 10 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 221 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 233 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 74 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 112 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 199 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 773 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 423 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 114 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 613 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 720 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 536 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 38 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 50 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 55 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 10 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 228 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 241 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 77 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 113 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 190 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 798 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 430 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 117 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 636 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 740 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 604 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 39 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.totGap 859529 # Total gap between requests +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 15358 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 15354 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 4169 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 41 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 52 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 239 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 267 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 269 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 273 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 289 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 276 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 264 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 264 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 264 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 264 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 264 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 264 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 263 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 263 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 263 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 263 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 1408 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 385.272727 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 251.738502 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 337.085623 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 275 19.53% 19.53% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 389 27.63% 47.16% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 189 13.42% 60.58% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 133 9.45% 70.03% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 71 5.04% 75.07% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 66 4.69% 79.76% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 54 3.84% 83.59% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 28 1.99% 85.58% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 203 14.42% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 1408 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 263 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 15.806084 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 15.711677 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 1.919278 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::12-13 13 4.94% 4.94% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::14-15 101 38.40% 43.35% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-17 117 44.49% 87.83% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::18-19 30 11.41% 99.24% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::20-21 1 0.38% 99.62% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::36-37 1 0.38% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 263 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 263 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.456274 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.427772 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 1.006178 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 215 81.75% 81.75% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 3 1.14% 82.89% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 19 7.22% 90.11% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 25 9.51% 99.62% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::20 1 0.38% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 263 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 83882 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 163093 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 20845 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 20.12 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 39.12 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 310.40 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 322.23 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 1143.45 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 1143.15 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 4.94 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 2.42 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 2.52 # Data bus utilization in percentage for writes +system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 26.06 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 3094 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 3987 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 74.21 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 91.51 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 27.99 # Average gap between requests +system.mem_ctrls.pageHitRate 83.05 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 2934540 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 1580376 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 10875648 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 8051328 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 49171200.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 53605080 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 1521408 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.actPowerDownEnergy 172427736 # Energy for active power-down per rank (pJ) +system.mem_ctrls_0.prePowerDownEnergy 33896448 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_0.selfRefreshEnergy 67964640 # Energy for self refresh per rank (pJ) +system.mem_ctrls_0.totalEnergy 402028404 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 467.691876 # Core power per rank (mW) +system.mem_ctrls_0.totalIdleTime 738047 # Total Idle time Per DRAM Rank +system.mem_ctrls_0.memoryStateTime::IDLE 1720 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 20830 # Time in different power states +system.mem_ctrls_0.memoryStateTime::SREF 271681 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 88272 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 98967 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 378131 # Time in different power states +system.mem_ctrls_1.actEnergy 7175700 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 3860136 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 36751008 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 28096128 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 65766480.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 76176168 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 2087424 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.actPowerDownEnergy 225232992 # Energy for active power-down per rank (pJ) +system.mem_ctrls_1.prePowerDownEnergy 45732480 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_1.selfRefreshEnergy 21646080 # Energy for self refresh per rank (pJ) +system.mem_ctrls_1.totalEnergy 512524596 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 596.235458 # Core power per rank (mW) +system.mem_ctrls_1.totalIdleTime 686903 # Total Idle time Per DRAM Rank +system.mem_ctrls_1.memoryStateTime::IDLE 2426 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 27862 # Time in different power states +system.mem_ctrls_1.memoryStateTime::SREF 74085 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 119095 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 142201 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 493932 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 859601 # Cumulative time (in ticks) in various power states +system.cpu.clk_domain.clock 1 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 12 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 859601 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 859601 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 65796 # Number of instructions committed +system.cpu.committedOps 65796 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 65797 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 5286 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 10678 # number of instructions that are conditional controls +system.cpu.num_int_insts 65797 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 89529 # number of times the integer registers were read +system.cpu.num_int_register_writes 42335 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 23560 # number of memory refs +system.cpu.num_load_insts 10774 # Number of load instructions +system.cpu.num_store_insts 12786 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 859601 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 15964 # Number of branches fetched +system.cpu.op_class::No_OpClass 12 0.02% 0.02% # Class of executed instruction +system.cpu.op_class::IntAlu 42205 64.13% 64.15% # Class of executed instruction +system.cpu.op_class::IntMult 18 0.03% 64.18% # Class of executed instruction +system.cpu.op_class::IntDiv 14 0.02% 64.20% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.20% # Class of executed instruction +system.cpu.op_class::MemRead 10774 16.37% 80.57% # Class of executed instruction +system.cpu.op_class::MemWrite 12786 19.43% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 65809 # Class of executed instruction +system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.pwrStateResidencyTicks::UNDEFINED 859601 # Cumulative time (in ticks) in various power states +system.ruby.delayHist::bucket_size 1 # delay histogram for all message +system.ruby.delayHist::max_bucket 9 # delay histogram for all message +system.ruby.delayHist::samples 30712 # delay histogram for all message +system.ruby.delayHist | 30712 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 30712 # delay histogram for all message +system.ruby.outstanding_req_hist_seqr::bucket_size 1 +system.ruby.outstanding_req_hist_seqr::max_bucket 9 +system.ruby.outstanding_req_hist_seqr::samples 89369 +system.ruby.outstanding_req_hist_seqr::mean 1 +system.ruby.outstanding_req_hist_seqr::gmean 1 +system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 89369 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 89369 +system.ruby.latency_hist_seqr::bucket_size 64 +system.ruby.latency_hist_seqr::max_bucket 639 +system.ruby.latency_hist_seqr::samples 89368 +system.ruby.latency_hist_seqr::mean 8.618667 +system.ruby.latency_hist_seqr::gmean 1.888843 +system.ruby.latency_hist_seqr::stdev 21.338548 +system.ruby.latency_hist_seqr | 85319 95.47% 95.47% | 3770 4.22% 99.69% | 171 0.19% 99.88% | 37 0.04% 99.92% | 34 0.04% 99.96% | 27 0.03% 99.99% | 1 0.00% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 9 0.01% 100.00% +system.ruby.latency_hist_seqr::total 89368 +system.ruby.hit_latency_hist_seqr::bucket_size 1 +system.ruby.hit_latency_hist_seqr::max_bucket 9 +system.ruby.hit_latency_hist_seqr::samples 74010 +system.ruby.hit_latency_hist_seqr::mean 1 +system.ruby.hit_latency_hist_seqr::gmean 1 +system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 74010 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 74010 +system.ruby.miss_latency_hist_seqr::bucket_size 64 +system.ruby.miss_latency_hist_seqr::max_bucket 639 +system.ruby.miss_latency_hist_seqr::samples 15358 +system.ruby.miss_latency_hist_seqr::mean 45.332921 +system.ruby.miss_latency_hist_seqr::gmean 40.474352 +system.ruby.miss_latency_hist_seqr::stdev 31.968222 +system.ruby.miss_latency_hist_seqr | 11309 73.64% 73.64% | 3770 24.55% 98.18% | 171 1.11% 99.30% | 37 0.24% 99.54% | 34 0.22% 99.76% | 27 0.18% 99.93% | 1 0.01% 99.94% | 0 0.00% 99.94% | 0 0.00% 99.94% | 9 0.06% 100.00% +system.ruby.miss_latency_hist_seqr::total 15358 +system.ruby.Directory.incomplete_times_seqr 15357 +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 859601 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.cacheMemory.demand_hits 74010 # Number of cache demand hits +system.ruby.l1_cntrl0.cacheMemory.demand_misses 15358 # Number of cache demand misses +system.ruby.l1_cntrl0.cacheMemory.demand_accesses 89368 # Number of cache demand accesses +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 859601 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 859601 # Cumulative time (in ticks) in various power states +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 859601 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.percent_links_utilized 8.932051 +system.ruby.network.routers0.msg_count.Control::2 15358 +system.ruby.network.routers0.msg_count.Data::2 15354 +system.ruby.network.routers0.msg_count.Response_Data::4 15358 +system.ruby.network.routers0.msg_count.Writeback_Control::3 15354 +system.ruby.network.routers0.msg_bytes.Control::2 122864 +system.ruby.network.routers0.msg_bytes.Data::2 1105488 +system.ruby.network.routers0.msg_bytes.Response_Data::4 1105776 +system.ruby.network.routers0.msg_bytes.Writeback_Control::3 122832 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 859601 # Cumulative time (in ticks) in various power states +system.ruby.network.routers1.percent_links_utilized 8.932051 +system.ruby.network.routers1.msg_count.Control::2 15358 +system.ruby.network.routers1.msg_count.Data::2 15354 +system.ruby.network.routers1.msg_count.Response_Data::4 15358 +system.ruby.network.routers1.msg_count.Writeback_Control::3 15354 +system.ruby.network.routers1.msg_bytes.Control::2 122864 +system.ruby.network.routers1.msg_bytes.Data::2 1105488 +system.ruby.network.routers1.msg_bytes.Response_Data::4 1105776 +system.ruby.network.routers1.msg_bytes.Writeback_Control::3 122832 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 859601 # Cumulative time (in ticks) in various power states +system.ruby.network.routers2.percent_links_utilized 8.932051 +system.ruby.network.routers2.msg_count.Control::2 15358 +system.ruby.network.routers2.msg_count.Data::2 15354 +system.ruby.network.routers2.msg_count.Response_Data::4 15358 +system.ruby.network.routers2.msg_count.Writeback_Control::3 15354 +system.ruby.network.routers2.msg_bytes.Control::2 122864 +system.ruby.network.routers2.msg_bytes.Data::2 1105488 +system.ruby.network.routers2.msg_bytes.Response_Data::4 1105776 +system.ruby.network.routers2.msg_bytes.Writeback_Control::3 122832 +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 859601 # Cumulative time (in ticks) in various power states +system.ruby.network.msg_count.Control 46074 +system.ruby.network.msg_count.Data 46062 +system.ruby.network.msg_count.Response_Data 46074 +system.ruby.network.msg_count.Writeback_Control 46062 +system.ruby.network.msg_byte.Control 368592 +system.ruby.network.msg_byte.Data 3316464 +system.ruby.network.msg_byte.Response_Data 3317328 +system.ruby.network.msg_byte.Writeback_Control 368496 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 859601 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.throttle0.link_utilization 8.932982 +system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 15358 +system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 15354 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 1105776 +system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 122832 +system.ruby.network.routers0.throttle1.link_utilization 8.931120 +system.ruby.network.routers0.throttle1.msg_count.Control::2 15358 +system.ruby.network.routers0.throttle1.msg_count.Data::2 15354 +system.ruby.network.routers0.throttle1.msg_bytes.Control::2 122864 +system.ruby.network.routers0.throttle1.msg_bytes.Data::2 1105488 +system.ruby.network.routers1.throttle0.link_utilization 8.931120 +system.ruby.network.routers1.throttle0.msg_count.Control::2 15358 +system.ruby.network.routers1.throttle0.msg_count.Data::2 15354 +system.ruby.network.routers1.throttle0.msg_bytes.Control::2 122864 +system.ruby.network.routers1.throttle0.msg_bytes.Data::2 1105488 +system.ruby.network.routers1.throttle1.link_utilization 8.932982 +system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 15358 +system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 15354 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 1105776 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 122832 +system.ruby.network.routers2.throttle0.link_utilization 8.932982 +system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 15358 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 15354 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 1105776 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 122832 +system.ruby.network.routers2.throttle1.link_utilization 8.931120 +system.ruby.network.routers2.throttle1.msg_count.Control::2 15358 +system.ruby.network.routers2.throttle1.msg_count.Data::2 15354 +system.ruby.network.routers2.throttle1.msg_bytes.Control::2 122864 +system.ruby.network.routers2.throttle1.msg_bytes.Data::2 1105488 +system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::samples 15358 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1 | 15358 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::total 15358 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::samples 15354 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2 | 15354 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::total 15354 # delay histogram for vnet_2 +system.ruby.LD.latency_hist_seqr::bucket_size 64 +system.ruby.LD.latency_hist_seqr::max_bucket 639 +system.ruby.LD.latency_hist_seqr::samples 10773 +system.ruby.LD.latency_hist_seqr::mean 19.602432 +system.ruby.LD.latency_hist_seqr::gmean 4.753143 +system.ruby.LD.latency_hist_seqr::stdev 29.028323 +system.ruby.LD.latency_hist_seqr | 9584 88.96% 88.96% | 1108 10.28% 99.25% | 53 0.49% 99.74% | 6 0.06% 99.80% | 14 0.13% 99.93% | 8 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist_seqr::total 10773 +system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 +system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 +system.ruby.LD.hit_latency_hist_seqr::samples 6235 +system.ruby.LD.hit_latency_hist_seqr::mean 1 +system.ruby.LD.hit_latency_hist_seqr::gmean 1 +system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 6235 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::total 6235 +system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 +system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 +system.ruby.LD.miss_latency_hist_seqr::samples 4538 +system.ruby.LD.miss_latency_hist_seqr::mean 45.161305 +system.ruby.LD.miss_latency_hist_seqr::gmean 40.468869 +system.ruby.LD.miss_latency_hist_seqr::stdev 29.524391 +system.ruby.LD.miss_latency_hist_seqr | 3349 73.80% 73.80% | 1108 24.42% 98.22% | 53 1.17% 99.38% | 6 0.13% 99.52% | 14 0.31% 99.82% | 8 0.18% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist_seqr::total 4538 +system.ruby.ST.latency_hist_seqr::bucket_size 64 +system.ruby.ST.latency_hist_seqr::max_bucket 639 +system.ruby.ST.latency_hist_seqr::samples 12783 +system.ruby.ST.latency_hist_seqr::mean 12.152937 +system.ruby.ST.latency_hist_seqr::gmean 2.610081 +system.ruby.ST.latency_hist_seqr::stdev 26.071652 +system.ruby.ST.latency_hist_seqr | 12053 94.29% 94.29% | 671 5.25% 99.54% | 33 0.26% 99.80% | 12 0.09% 99.89% | 2 0.02% 99.91% | 6 0.05% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 6 0.05% 100.00% +system.ruby.ST.latency_hist_seqr::total 12783 +system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 +system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 +system.ruby.ST.hit_latency_hist_seqr::samples 9433 +system.ruby.ST.hit_latency_hist_seqr::mean 1 +system.ruby.ST.hit_latency_hist_seqr::gmean 1 +system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 9433 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist_seqr::total 9433 +system.ruby.ST.miss_latency_hist_seqr::bucket_size 64 +system.ruby.ST.miss_latency_hist_seqr::max_bucket 639 +system.ruby.ST.miss_latency_hist_seqr::samples 3350 +system.ruby.ST.miss_latency_hist_seqr::mean 43.557612 +system.ruby.ST.miss_latency_hist_seqr::gmean 38.893505 +system.ruby.ST.miss_latency_hist_seqr::stdev 35.459785 +system.ruby.ST.miss_latency_hist_seqr | 2620 78.21% 78.21% | 671 20.03% 98.24% | 33 0.99% 99.22% | 12 0.36% 99.58% | 2 0.06% 99.64% | 6 0.18% 99.82% | 0 0.00% 99.82% | 0 0.00% 99.82% | 0 0.00% 99.82% | 6 0.18% 100.00% +system.ruby.ST.miss_latency_hist_seqr::total 3350 +system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.latency_hist_seqr::samples 65809 +system.ruby.IFETCH.latency_hist_seqr::mean 6.134450 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.525163 +system.ruby.IFETCH.latency_hist_seqr::stdev 17.889520 +system.ruby.IFETCH.latency_hist_seqr | 63679 96.76% 96.76% | 1991 3.03% 99.79% | 85 0.13% 99.92% | 19 0.03% 99.95% | 18 0.03% 99.97% | 13 0.02% 99.99% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 3 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::total 65809 +system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 +system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 +system.ruby.IFETCH.hit_latency_hist_seqr::samples 58339 +system.ruby.IFETCH.hit_latency_hist_seqr::mean 1 +system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 +system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 58339 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist_seqr::total 58339 +system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.miss_latency_hist_seqr::samples 7470 +system.ruby.IFETCH.miss_latency_hist_seqr::mean 46.233333 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 41.207407 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 31.713096 +system.ruby.IFETCH.miss_latency_hist_seqr | 5340 71.49% 71.49% | 1991 26.65% 98.14% | 85 1.14% 99.28% | 19 0.25% 99.53% | 18 0.24% 99.77% | 13 0.17% 99.95% | 1 0.01% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 3 0.04% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::total 7470 +system.ruby.Load_Linked.latency_hist_seqr::bucket_size 1 +system.ruby.Load_Linked.latency_hist_seqr::max_bucket 9 +system.ruby.Load_Linked.latency_hist_seqr::samples 1 +system.ruby.Load_Linked.latency_hist_seqr::mean 1 +system.ruby.Load_Linked.latency_hist_seqr::gmean 1 +system.ruby.Load_Linked.latency_hist_seqr::stdev nan +system.ruby.Load_Linked.latency_hist_seqr | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Load_Linked.latency_hist_seqr::total 1 +system.ruby.Load_Linked.hit_latency_hist_seqr::bucket_size 1 +system.ruby.Load_Linked.hit_latency_hist_seqr::max_bucket 9 +system.ruby.Load_Linked.hit_latency_hist_seqr::samples 1 +system.ruby.Load_Linked.hit_latency_hist_seqr::mean 1 +system.ruby.Load_Linked.hit_latency_hist_seqr::gmean 1 +system.ruby.Load_Linked.hit_latency_hist_seqr::stdev nan +system.ruby.Load_Linked.hit_latency_hist_seqr | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Load_Linked.hit_latency_hist_seqr::total 1 +system.ruby.Store_Conditional.latency_hist_seqr::bucket_size 1 +system.ruby.Store_Conditional.latency_hist_seqr::max_bucket 9 +system.ruby.Store_Conditional.latency_hist_seqr::samples 2 +system.ruby.Store_Conditional.latency_hist_seqr::mean 1 +system.ruby.Store_Conditional.latency_hist_seqr::gmean 1 +system.ruby.Store_Conditional.latency_hist_seqr | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Store_Conditional.latency_hist_seqr::total 2 +system.ruby.Store_Conditional.hit_latency_hist_seqr::bucket_size 1 +system.ruby.Store_Conditional.hit_latency_hist_seqr::max_bucket 9 +system.ruby.Store_Conditional.hit_latency_hist_seqr::samples 2 +system.ruby.Store_Conditional.hit_latency_hist_seqr::mean 1 +system.ruby.Store_Conditional.hit_latency_hist_seqr::gmean 1 +system.ruby.Store_Conditional.hit_latency_hist_seqr | 0 0.00% 0.00% | 2 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Store_Conditional.hit_latency_hist_seqr::total 2 +system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 +system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 +system.ruby.Directory.miss_mach_latency_hist_seqr::samples 15358 +system.ruby.Directory.miss_mach_latency_hist_seqr::mean 45.332921 +system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 40.474352 +system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 31.968222 +system.ruby.Directory.miss_mach_latency_hist_seqr | 11309 73.64% 73.64% | 3770 24.55% 98.18% | 171 1.11% 99.30% | 37 0.24% 99.54% | 34 0.22% 99.76% | 27 0.18% 99.93% | 1 0.01% 99.94% | 0 0.00% 99.94% | 0 0.00% 99.94% | 9 0.06% 100.00% +system.ruby.Directory.miss_mach_latency_hist_seqr::total 15358 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::total 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total 1 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size 8 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 79 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean 75 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 75.000000 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 4538 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 45.161305 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 40.468869 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 29.524391 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 3349 73.80% 73.80% | 1108 24.42% 98.22% | 53 1.17% 99.38% | 6 0.13% 99.52% | 14 0.31% 99.82% | 8 0.18% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 4538 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 3350 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 43.557612 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 38.893505 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 35.459785 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 2620 78.21% 78.21% | 671 20.03% 98.24% | 33 0.99% 99.22% | 12 0.36% 99.58% | 2 0.06% 99.64% | 6 0.18% 99.82% | 0 0.00% 99.82% | 0 0.00% 99.82% | 0 0.00% 99.82% | 6 0.18% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 3350 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 7470 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 46.233333 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 41.207407 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 31.713096 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 5340 71.49% 71.49% | 1991 26.65% 98.14% | 85 1.14% 99.28% | 19 0.25% 99.53% | 18 0.24% 99.77% | 13 0.17% 99.95% | 1 0.01% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 3 0.04% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 7470 +system.ruby.Directory_Controller.GETX 15358 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 15354 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 15358 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 15354 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 15358 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 15354 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 15358 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 15354 0.00% 0.00% +system.ruby.L1Cache_Controller.Load 10773 0.00% 0.00% +system.ruby.L1Cache_Controller.Ifetch 65809 0.00% 0.00% +system.ruby.L1Cache_Controller.Store 12786 0.00% 0.00% +system.ruby.L1Cache_Controller.Data 15358 0.00% 0.00% +system.ruby.L1Cache_Controller.Replacement 15354 0.00% 0.00% +system.ruby.L1Cache_Controller.Writeback_Ack 15354 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Load 4538 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Ifetch 7470 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Store 3350 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Load 6235 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Ifetch 58339 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Store 9436 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Replacement 15354 0.00% 0.00% +system.ruby.L1Cache_Controller.MI.Writeback_Ack 15354 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Data 12008 0.00% 0.00% +system.ruby.L1Cache_Controller.IM.Data 3350 0.00% 0.00% + +---------- End Simulation Statistics ---------- diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/config.ini --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-timing/config.ini Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,374 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=TimingSimpleCPU +children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +hit_latency=2 +is_read_only=false +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=262144 + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.icache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +hit_latency=2 +is_read_only=true +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tags=system.cpu.icache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=131072 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.l2cache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +hit_latency=20 +is_read_only=false +max_miss_count=0 +mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +hit_latency=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=2097152 + +[system.cpu.toL2Bus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=0 +frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null +response_latency=1 +snoop_filter=system.cpu.toL2Bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64a/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +eventq_index=0 +in_addr_map=true +kvm_map=true +latency=30000 +latency_var=0 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +range=0:134217727:0:0:0:0 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64a/o3-timing/config.ini --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/o3-timing/config.ini Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,866 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cachePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +default_p_state=UNDEFINED +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=0 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +system=system +tracer=system.cpu.tracer +trapLatency=13 +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TournamentBP +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +useIndirect=true + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +hit_latency=2 +is_read_only=false +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=262144 + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +eventq_index=0 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +opClass=IntAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +eventq_index=0 +opClass=IntMult +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +eventq_index=0 +opClass=IntDiv +opLat=20 +pipelined=false + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +eventq_index=0 +opClass=FloatAdd +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatCmp +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatCvt +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 opList3 opList4 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +eventq_index=0 +opClass=FloatMult +opLat=4 +pipelined=true + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMultAcc +opLat=5 +pipelined=true + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMisc +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList3.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatDiv +opLat=12 +pipelined=false + +[system.cpu.fuPool.FUList3.opList4] +type=OpDesc +eventq_index=0 +opClass=FloatSqrt +opLat=24 +pipelined=false + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList0 opList1 +count=0 +eventq_index=0 +opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +eventq_index=0 +opClass=MemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList4.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5] +type=FUDesc +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 + +[system.cpu.fuPool.FUList5.opList00] +type=OpDesc +eventq_index=0 +opClass=SimdAdd +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList01] +type=OpDesc +eventq_index=0 +opClass=SimdAddAcc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList02] +type=OpDesc +eventq_index=0 +opClass=SimdAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList03] +type=OpDesc +eventq_index=0 +opClass=SimdCmp +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList04] +type=OpDesc +eventq_index=0 +opClass=SimdCvt +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList05] +type=OpDesc +eventq_index=0 +opClass=SimdMisc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList06] +type=OpDesc +eventq_index=0 +opClass=SimdMult +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList07] +type=OpDesc +eventq_index=0 +opClass=SimdMultAcc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList08] +type=OpDesc +eventq_index=0 +opClass=SimdShift +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList09] +type=OpDesc +eventq_index=0 +opClass=SimdShiftAcc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList10] +type=OpDesc +eventq_index=0 +opClass=SimdSqrt +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList11] +type=OpDesc +eventq_index=0 +opClass=SimdFloatAdd +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList12] +type=OpDesc +eventq_index=0 +opClass=SimdFloatAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList13] +type=OpDesc +eventq_index=0 +opClass=SimdFloatCmp +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList14] +type=OpDesc +eventq_index=0 +opClass=SimdFloatCvt +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList15] +type=OpDesc +eventq_index=0 +opClass=SimdFloatDiv +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList16] +type=OpDesc +eventq_index=0 +opClass=SimdFloatMisc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList17] +type=OpDesc +eventq_index=0 +opClass=SimdFloatMult +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList18] +type=OpDesc +eventq_index=0 +opClass=SimdFloatMultAcc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList19] +type=OpDesc +eventq_index=0 +opClass=SimdFloatSqrt +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList6] +type=FUDesc +children=opList0 opList1 +count=0 +eventq_index=0 +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +eventq_index=0 +opClass=MemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7] +type=FUDesc +children=opList0 opList1 opList2 opList3 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +eventq_index=0 +opClass=MemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7.opList1] +type=OpDesc +eventq_index=0 +opClass=MemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList8] +type=FUDesc +children=opList +count=1 +eventq_index=0 +opList=system.cpu.fuPool.FUList8.opList + +[system.cpu.fuPool.FUList8.opList] +type=OpDesc +eventq_index=0 +opClass=IprAccess +opLat=3 +pipelined=false + +[system.cpu.icache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +hit_latency=2 +is_read_only=true +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tags=system.cpu.icache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=131072 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.l2cache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +hit_latency=20 +is_read_only=false +max_miss_count=0 +mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +hit_latency=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=2097152 + +[system.cpu.toL2Bus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=0 +frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null +response_latency=1 +snoop_filter=system.cpu.toL2Bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64a/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=DRAMCtrl +IDD0=0.055000 +IDD02=0.000000 +IDD2N=0.032000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.032000 +IDD2P12=0.000000 +IDD3N=0.038000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.038000 +IDD3P12=0.000000 +IDD4R=0.157000 +IDD4R2=0.000000 +IDD4W=0.125000 +IDD4W2=0.000000 +IDD5=0.235000 +IDD52=0.000000 +IDD6=0.020000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +page_policy=open_adaptive +power_model=Null +range=0:134217727:0:0:0:0 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCCD_L=0 +tCK=1250 +tCL=13750 +tCS=2500 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64a/o3-timing/config.json --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/o3-timing/config.json Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,1145 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.l2cache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": 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"type": "Cache", + "writeback_clean": true, + "p_state_clk_gate_min": 1000, + "hit_latency": 2, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": true, + "prefetch_on_access": false, + "path": "system.cpu.icache", + "mshrs": 4, + "name": "icache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "path": "system.cpu", + "numRobs": 1, + "switched_out": false, + "smtLSQPolicy": "Partitioned", + "fetchBufferSize": 64, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "smtROBThreshold": 100, + "numIQEntries": 64, + "branchPred": { + "numThreads": 1, + "BTBEntries": 4096, + "cxx_class": "TournamentBP", + "indirectPathLength": 3, + "globalCtrBits": 2, + "choicePredictorSize": 8192, + "indirectHashGHR": true, + "eventq_index": 0, + "localHistoryTableSize": 2048, + "type": "TournamentBP", + "indirectSets": 256, + "indirectWays": 2, + "choiceCtrBits": 2, + "useIndirect": true, + "localCtrBits": 2, + "path": "system.cpu.branchPred", + "localPredictorSize": 2048, + "RASSize": 16, + "globalPredictorSize": 8192, + "name": "branchPred", + "indirectHashTargets": true, + "instShiftAmt": 2, + "indirectTagSize": 16, + "BTBTagSize": 16 + }, + "LFSTSize": 1024, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "smtROBPolicy": "Partitioned", + "iewToFetchDelay": 1, + "do_statistics_insts": true, + "dispatchWidth": 8, + "dcache": { + "cpu_side": { + "peer": "system.cpu.dcache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 262144, + "tags": { + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.dcache.tags", + "hit_latency": 2, + "block_size": 64, + "type": "LRU", + "size": 262144 + }, + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[1]", + "role": "MASTER" + }, + "type": "Cache", + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "hit_latency": 2, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.dcache", + "mshrs": 4, + "name": "dcache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "commitToDecodeDelay": 1, + "smtIQPolicy": "Partitioned", + "issueWidth": 8, + "LSQCheckLoads": true, + "commitToRenameDelay": 1, + "cachePorts": 200, + "system": "system", + "checker": null, + "numPhysFloatRegs": 256, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "type": "DerivO3CPU", + "wbWidth": 8, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "smtCommitPolicy": "RoundRobin", + "issueToExecuteDelay": 1, + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "numROBEntries": 192, + "fetchQueueSize": 32, + "iewToCommitDelay": 1, + "smtNumFetchingThreads": 1, + "forwardComSize": 5, + "do_checkpoint_insts": true, + "cxx_class": "DerivO3CPU", + "commitToIEWDelay": 1, + "commitWidth": 8, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "smtFetchPolicy": "SingleThread", + "profile": 0, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "role": "MASTER" + }, + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "role": "MASTER" + }, + "LSQDepCheckShift": 4, + "trapLatency": 13, + "iewToDecodeDelay": 1, + "numPhysCCRegs": 0, + "renameToIEWDelay": 2, + "p_state_clk_gate_bins": 20, + "progress_interval": 0, + "LQEntries": 32 + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64a/o3-timing/simerr --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/o3-timing/simerr Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,40 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick +gem5.debug: build/RISCV/mem/page_table.cc:187: Fault PageTableBase::translate(RequestPtr): Assertion `pageAlign(req->getVaddr() + req->getSize() - 1) == pageAlign(req->getVaddr())' failed. +Program aborted at tick 42339500 +--- BEGIN LIBC BACKTRACE --- +/home/ar4jc/gem5/build/RISCV/gem5.debug(_Z15print_backtracev+0x32)[0xdabf60] +/home/ar4jc/gem5/build/RISCV/gem5.debug(_Z12abortHandleri+0x6e)[0xdc356a] +/lib/x86_64-linux-gnu/libpthread.so.0(+0x113e0)[0x7f64be0213e0] +/lib/x86_64-linux-gnu/libc.so.6(gsignal+0x38)[0x7f64bca05428] +/lib/x86_64-linux-gnu/libc.so.6(abort+0x16a)[0x7f64bca0702a] +/lib/x86_64-linux-gnu/libc.so.6(+0x2dbd7)[0x7f64bc9fdbd7] +/lib/x86_64-linux-gnu/libc.so.6(+0x2dc82)[0x7f64bc9fdc82] +/home/ar4jc/gem5/build/RISCV/gem5.debug(_ZN13PageTableBase9translateEP7Request+0x98)[0xc31106] +/home/ar4jc/gem5/build/RISCV/gem5.debug(_ZN8RiscvISA3TLB13translateDataEP7RequestP13ThreadContextb+0x98)[0xd63946] +/home/ar4jc/gem5/build/RISCV/gem5.debug(_ZN8RiscvISA3TLB15translateAtomicEP7RequestP13ThreadContextN7BaseTLB4ModeE+0x70)[0xd63a18] +/home/ar4jc/gem5/build/RISCV/gem5.debug(_ZN8RiscvISA3TLB15translateTimingEP7RequestP13ThreadContextPN7BaseTLB11TranslationENS5_4ModeE+0x78)[0xd63aaa] +/home/ar4jc/gem5/build/RISCV/gem5.debug(_ZN11BaseDynInstI9O3CPUImplE19initiateTranslationEP7RequestS3_S3_PmN7BaseTLB4ModeE+0xf9)[0xfa9001] +/home/ar4jc/gem5/build/RISCV/gem5.debug(_ZN11BaseDynInstI9O3CPUImplE8writeMemEPhjm5FlagsIjEPm+0x243)[0xfa8bc9] +/home/ar4jc/gem5/build/RISCV/gem5.debug(_Z14writeMemTimingI11ExecContextmESt10shared_ptrI9FaultBaseEPT_PN5Trace10InstRecordET0_m5FlagsIjEPm+0x9d)[0x189efc5] +/home/ar4jc/gem5/build/RISCV/gem5.debug(_ZNK12RiscvISAInst2Sd11initiateAccEP11ExecContextPN5Trace10InstRecordE+0x101)[0x187a159] +/home/ar4jc/gem5/build/RISCV/gem5.debug(_ZN13BaseO3DynInstI9O3CPUImplE11initiateAccEv+0x70)[0xfdac52] +/home/ar4jc/gem5/build/RISCV/gem5.debug(_ZN7LSQUnitI9O3CPUImplE12executeStoreER14RefCountingPtrI13BaseO3DynInstIS0_EE+0x191)[0x100de09] +/home/ar4jc/gem5/build/RISCV/gem5.debug(_ZN3LSQI9O3CPUImplE12executeStoreER14RefCountingPtrI13BaseO3DynInstIS0_EE+0x6b)[0x10094c7] +/home/ar4jc/gem5/build/RISCV/gem5.debug(_ZN10DefaultIEWI9O3CPUImplE12executeInstsEv+0x67c)[0xff59d2] +/home/ar4jc/gem5/build/RISCV/gem5.debug(_ZN10DefaultIEWI9O3CPUImplE4tickEv+0x1a9)[0xff7775] +/home/ar4jc/gem5/build/RISCV/gem5.debug(_ZN9FullO3CPUI9O3CPUImplE4tickEv+0x155)[0xfc37e3] +/home/ar4jc/gem5/build/RISCV/gem5.debug(_ZN9FullO3CPUI9O3CPUImplE9TickEvent7processEv+0x1c)[0xfc7b14] +/home/ar4jc/gem5/build/RISCV/gem5.debug(_ZN10EventQueue10serviceOneEv+0xe9)[0xdbbc1d] +/home/ar4jc/gem5/build/RISCV/gem5.debug(_Z9doSimLoopP10EventQueue+0x1fa)[0xde66e9] +/home/ar4jc/gem5/build/RISCV/gem5.debug(_Z8simulatem+0x301)[0xde6345] +/home/ar4jc/gem5/build/RISCV/gem5.debug[0x109ab70] +/home/ar4jc/gem5/build/RISCV/gem5.debug[0x109ad64] +/usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x7852)[0x7f64be2ee552] +/usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCodeEx+0x85c)[0x7f64be41801c] +/usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x6ffd)[0x7f64be2edcfd] +/usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalCodeEx+0x85c)[0x7f64be41801c] +/usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0(PyEval_EvalFrameEx+0x6ffd)[0x7f64be2edcfd] +--- END LIBC BACKTRACE --- diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64a/o3-timing/simout --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/o3-timing/simout Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,13 @@ +Redirecting stdout to build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64a/o3-timing/simout +Redirecting stderr to build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64a/o3-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 22 2016 16:06:54 +gem5 started Nov 28 2016 15:22:03 +gem5 executing on ubuntu1604, pid 8753 +command line: /home/ar4jc/gem5/build/RISCV/gem5.debug -d build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64a/o3-timing -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64a/o3-timing + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/config.ini --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/config.ini Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,211 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=atomic +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=AtomicSimpleCPU +children=dtb interrupts isa itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fastmem=false +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +simulate_data_stalls=false +simulate_inst_stalls=false +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +width=1 +workload=system.cpu.workload +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64a/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +eventq_index=0 +in_addr_map=true +kvm_map=true +latency=30000 +latency_var=0 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +range=0:134217727:0:0:0:0 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/config.json --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/config.json Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,289 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.icache_port", + "system.cpu.dcache_port" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "physmem": { + "range": "0:134217727:0:0:0:0", + "latency": 30000, + "name": "physmem", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "kvm_map": true, + "clk_domain": "system.clk_domain", + "power_model": null, + "latency_var": 0, + "bandwidth": "73.000000", + "conf_table_reported": true, + "cxx_class": "SimpleMemory", + "p_state_clk_gate_max": 1000000000000, + "path": "system.physmem", + "null": false, + "type": "SimpleMemory", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "in_addr_map": true + }, + "power_model": null, + "work_cpus_ckpt_count": 0, + "thermal_components": [], + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "work_end_ckpt_count": 0, + "mem_mode": "atomic", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": [ + { + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.itb", + "type": "RiscvTLB", + "size": 64 + }, + "simulate_data_stalls": false, + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "AtomicSimpleCPU", + "max_loads_all_threads": 0, + "system": "system", + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "cpu_id": 0, + "width": 1, + "checker": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "do_quiesce": true, + "type": "AtomicSimpleCPU", + "fastmem": false, + "profile": 0, + "icache_port": { + "peer": "system.membus.slave[1]", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "p_state_clk_gate_min": 1000, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "dcache_port": { + "peer": "system.membus.slave[2]", + "role": "MASTER" + }, + "socket_id": 0, + "power_model": null, + "max_insts_all_threads": 0, + "path": "system.cpu", + "max_loads_any_thread": 0, + "switched_out": false, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64a/insttest", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "insttest" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "simulate_inst_stalls": false, + "progress_interval": 0, + "branchPred": null, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/simerr --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/simerr Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,3 @@ +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/simout --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/simple-atomic/simout Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,49 @@ +Redirecting stdout to build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64a/simple-atomic/simout +Redirecting stderr to build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64a/simple-atomic/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 2 2016 20:34:02 +gem5 started Nov 3 2016 18:48:05 +gem5 executing on ubuntu1604, pid 21739 +command line: /home/ar4jc/gem5/build/RISCV/gem5.debug -d build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64a/simple-atomic -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64a/simple-atomic + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +lr.w/sc.w: PASS +sc.w, no preceding lr.d: PASS +amoswap.w: PASS +amoswap.w, sign extend: PASS +amoswap.w, truncate: PASS +amoadd.w: PASS +amoadd.w, truncate/overflow: PASS +amoadd.w, sign extend: PASS +amoxor.w, truncate: PASS +amoxor.w, sign extend: PASS +amoand.w, truncate: PASS +amoand.w, sign extend: PASS +amoor.w, truncate: PASS +amoor.w, sign extend: PASS +amomin.w, truncate: PASS +amomin.w, sign extend: PASS +amomax.w, truncate: PASS +amomax.w, sign extend: PASS +amominu.w, truncate: PASS +amominu.w, sign extend: PASS +amomaxu.w, truncate: PASS +amomaxu.w, sign extend: PASS +lr.d/sc.d: PASS +sc.d, no preceding lr.d: PASS +amoswap.d: PASS +amoadd.d: PASS +amoadd.d, overflow: PASS +amoxor.d (1): PASS +amoxor.d (0): PASS +amoand.d: PASS +amoor.d: PASS +amomin.d: PASS +amomax.d: PASS +amominu.d: PASS +amomaxu.d: PASS +Exiting @ tick 55999500 because target called exit() diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/00.hello/ref/riscv/linux/simple-timing/simerr --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing/simerr Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,3 @@ +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/00.hello/ref/riscv/linux/simple-timing/simout --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing/simout Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,15 @@ +Redirecting stdout to build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/simple-timing/simout +Redirecting stderr to build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/simple-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Oct 28 2016 00:48:50 +gem5 started Oct 28 2016 16:29:19 +gem5 executing on ubuntu1604, pid 10509 +command line: /home/ar4jc/gem5/build/RISCV/gem5.debug -d build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/simple-timing -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/00.hello/riscv/linux/simple-timing + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Hello world! +Exiting @ tick 12177500 because target called exit() diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/00.hello/ref/riscv/linux/simple-timing/stats.txt --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing/stats.txt Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,511 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000012 # Number of seconds simulated +sim_ticks 12177500 # Number of ticks simulated +final_tick 12177500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 12803 # Simulator instruction rate (inst/s) +host_op_rate 12801 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 90296662 # Simulator tick rate (ticks/s) +host_mem_usage 262564 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host +sim_insts 1726 # Number of instructions simulated +sim_ops 1726 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 12177500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 8064 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 2048 # Number of bytes read from this memory +system.physmem.bytes_read::total 10112 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 8064 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 8064 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 126 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 32 # Number of read requests responded to by this memory +system.physmem.num_reads::total 158 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 662204886 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 168179019 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 830383905 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 662204886 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 662204886 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 662204886 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 168179019 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 830383905 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 12177500 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 10 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 12177500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 24355 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 1726 # Number of instructions committed +system.cpu.committedOps 1726 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1727 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 155 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 240 # number of instructions that are conditional controls +system.cpu.num_int_insts 1727 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 2243 # number of times the integer registers were read +system.cpu.num_int_register_writes 1171 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 632 # number of memory refs +system.cpu.num_load_insts 316 # Number of load instructions +system.cpu.num_store_insts 316 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 24355 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 395 # Number of branches fetched +system.cpu.op_class::No_OpClass 10 0.58% 0.58% # Class of executed instruction +system.cpu.op_class::IntAlu 1095 63.04% 63.62% # Class of executed instruction +system.cpu.op_class::IntMult 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::MemRead 316 18.19% 81.81% # Class of executed instruction +system.cpu.op_class::MemWrite 316 18.19% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 1737 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 12177500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 23.218313 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 599 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 32 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 18.718750 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 23.218313 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.005669 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.005669 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 32 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.007812 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1294 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1294 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 12177500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 303 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 303 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 296 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 296 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 599 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 599 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 599 # number of overall hits +system.cpu.dcache.overall_hits::total 599 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 13 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 13 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 19 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 32 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 32 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 32 # number of overall misses +system.cpu.dcache.overall_misses::total 32 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 819000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 819000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1197000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1197000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 2016000 # number of demand (read+write) miss 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number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 158 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 959500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 959500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 6363500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 6363500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 656500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 656500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6363500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1616000 # number of demand (read+write) MSHR miss cycles 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ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992126 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.993711 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992126 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.993711 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50503.968254 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50503.968254 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50503.968254 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50503.164557 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50503.968254 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50503.164557 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 159 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 12177500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 140 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 19 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 19 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 127 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 13 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 254 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 64 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 318 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8128 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2048 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 10176 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 159 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.006289 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.079305 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 158 99.37% 99.37% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1 0.63% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 159 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 79500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 190500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 48000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 158 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 12177500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 139 # Transaction distribution +system.membus.trans_dist::ReadExReq 19 # Transaction distribution +system.membus.trans_dist::ReadExResp 19 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 139 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 316 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 316 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 10112 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 10112 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 158 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 158 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 158 # Request fanout histogram +system.membus.reqLayer0.occupancy 158500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 790000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 6.5 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/config.ini --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/config.ini Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,896 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=MinorCPU +children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload +branchPred=system.cpu.branchPred +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +decodeCycleInput=true +decodeInputBufferSize=3 +decodeInputWidth=2 +decodeToExecuteForwardDelay=1 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +enableIdling=true +eventq_index=0 +executeAllowEarlyMemoryIssue=true +executeBranchDelay=1 +executeCommitLimit=2 +executeCycleInput=true +executeFuncUnits=system.cpu.executeFuncUnits +executeInputBufferSize=7 +executeInputWidth=2 +executeIssueLimit=2 +executeLSQMaxStoreBufferStoresPerCycle=2 +executeLSQRequestsQueueSize=1 +executeLSQStoreBufferSize=5 +executeLSQTransfersQueueSize=2 +executeMaxAccessesInMemory=2 +executeMemoryCommitLimit=1 +executeMemoryIssueLimit=1 +executeMemoryWidth=0 +executeSetTraceTimeOnCommit=true +executeSetTraceTimeOnIssue=false +fetch1FetchLimit=1 +fetch1LineSnapWidth=0 +fetch1LineWidth=0 +fetch1ToFetch2BackwardDelay=1 +fetch1ToFetch2ForwardDelay=1 +fetch2CycleInput=true +fetch2InputBufferSize=2 +fetch2ToDecodeForwardDelay=1 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +threadPolicy=RoundRobin +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TournamentBP +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +useIndirect=true + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +hit_latency=2 +is_read_only=false +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=262144 + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.executeFuncUnits] +type=MinorFUPool +children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 +eventq_index=0 +funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 + +[system.cpu.executeFuncUnits.funcUnits0] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits0.timings + +[system.cpu.executeFuncUnits.funcUnits0.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits0.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits1] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits1.timings + +[system.cpu.executeFuncUnits.funcUnits1.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits1.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits2] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits2.timings + +[system.cpu.executeFuncUnits.funcUnits2.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntMult + +[system.cpu.executeFuncUnits.funcUnits2.timings] +type=MinorFUTiming +children=opClasses +description=Mul +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses +srcRegsRelativeLats=0 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits3] +type=MinorFU +children=opClasses +cantForwardFromFUIndices= +eventq_index=0 +issueLat=9 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses +opLat=9 +timings= + +[system.cpu.executeFuncUnits.funcUnits3.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntDiv + +[system.cpu.executeFuncUnits.funcUnits4] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses +opLat=6 +timings=system.cpu.executeFuncUnits.funcUnits4.timings + +[system.cpu.executeFuncUnits.funcUnits4.opClasses] +type=MinorOpClassSet +children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 opClasses26 opClasses27 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27 + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] +type=MinorOpClass +eventq_index=0 +opClass=FloatAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01] +type=MinorOpClass +eventq_index=0 +opClass=FloatCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02] +type=MinorOpClass +eventq_index=0 +opClass=FloatCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] +type=MinorOpClass +eventq_index=0 +opClass=FloatMisc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] +type=MinorOpClass +eventq_index=0 +opClass=FloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] +type=MinorOpClass +eventq_index=0 +opClass=FloatMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] +type=MinorOpClass +eventq_index=0 +opClass=FloatDiv + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] +type=MinorOpClass +eventq_index=0 +opClass=FloatSqrt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] +type=MinorOpClass +eventq_index=0 +opClass=SimdAdd + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] +type=MinorOpClass +eventq_index=0 +opClass=SimdAddAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] +type=MinorOpClass +eventq_index=0 +opClass=SimdAlu + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] +type=MinorOpClass +eventq_index=0 +opClass=SimdCmp + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] +type=MinorOpClass +eventq_index=0 +opClass=SimdCvt + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] +type=MinorOpClass +eventq_index=0 +opClass=SimdMisc + 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+snoop_filter=system.cpu.toL2Bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=insttest +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64a/insttest +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=DRAMCtrl +IDD0=0.055000 +IDD02=0.000000 +IDD2N=0.032000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.032000 +IDD2P12=0.000000 +IDD3N=0.038000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.038000 +IDD3P12=0.000000 +IDD4R=0.157000 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+tWR=15000 +tWTR=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/config.json --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/config.json Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,1205 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ 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"eventq_index": 0, + "localHistoryTableSize": 2048, + "type": "TournamentBP", + "indirectSets": 256, + "indirectWays": 2, + "choiceCtrBits": 2, + "useIndirect": true, + "localCtrBits": 2, + "path": "system.cpu.branchPred", + "localPredictorSize": 2048, + "RASSize": 16, + "globalPredictorSize": 8192, + "name": "branchPred", + "indirectHashTargets": true, + "instShiftAmt": 2, + "indirectTagSize": 16, + "BTBTagSize": 16 + }, + "dcache": { + "cpu_side": { + "peer": "system.cpu.dcache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 262144, + "tags": { + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.dcache.tags", + "hit_latency": 2, + "block_size": 64, + "type": "LRU", + "size": 262144 + }, + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[1]", + "role": "MASTER" + }, + "type": "Cache", + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "hit_latency": 2, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.dcache", + "mshrs": 4, + "name": "dcache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "path": "system.cpu", + "fetch1ToFetch2ForwardDelay": 1, + "decodeInputBufferSize": 3 + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/simerr --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/simerr Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,4 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/simout --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/simout Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,49 @@ +Redirecting stdout to build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64a/minor-timing/simout +Redirecting stderr to build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64a/minor-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Nov 2 2016 20:34:02 +gem5 started Nov 3 2016 18:47:58 +gem5 executing on ubuntu1604, pid 21738 +command line: /home/ar4jc/gem5/build/RISCV/gem5.debug -d build/RISCV/tests/debug/quick/se/02.insttest/riscv/linux-rv64a/minor-timing -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64a/minor-timing + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +lr.w/sc.w: PASS +sc.w, no preceding lr.d: PASS +amoswap.w: PASS +amoswap.w, sign extend: PASS +amoswap.w, truncate: PASS +amoadd.w: PASS +amoadd.w, truncate/overflow: PASS +amoadd.w, sign extend: PASS +amoxor.w, truncate: PASS +amoxor.w, sign extend: PASS +amoand.w, truncate: PASS +amoand.w, sign extend: PASS +amoor.w, truncate: PASS +amoor.w, sign extend: PASS +amomin.w, truncate: PASS +amomin.w, sign extend: PASS +amomax.w, truncate: PASS +amomax.w, sign extend: PASS +amominu.w, truncate: PASS +amominu.w, sign extend: PASS +amomaxu.w, truncate: PASS +amomaxu.w, sign extend: PASS +lr.d/sc.d: PASS +sc.d, no preceding lr.d: PASS +amoswap.d: PASS +amoadd.d: PASS +amoadd.d, overflow: PASS +amoxor.d (1): PASS +amoxor.d (0): PASS +amoand.d: PASS +amoor.d: PASS +amomin.d: PASS +amomax.d: PASS +amominu.d: PASS +amomaxu.d: PASS +Exiting @ tick 172412000 because target called exit() diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/stats.txt --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64a/minor-timing/stats.txt Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,773 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000172 # Number of seconds simulated +sim_ticks 172412000 # Number of ticks simulated +final_tick 172412000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 17589 # Simulator instruction rate (inst/s) +host_op_rate 17594 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 27083537 # Simulator tick rate (ticks/s) +host_mem_usage 276524 # Number of bytes of host memory used +host_seconds 6.37 # Real time elapsed on the host +sim_insts 111969 # Number of instructions simulated +sim_ops 112000 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 172412000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 53376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 17344 # Number of bytes read from this memory +system.physmem.bytes_read::total 70720 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 53376 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 53376 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 834 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 271 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1105 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 309584020 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 100596246 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 410180266 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 309584020 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 309584020 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 309584020 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 100596246 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 410180266 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1105 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 1105 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 70720 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 70720 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 75 # Per bank write bursts +system.physmem.perBankRdBursts::1 82 # Per bank write bursts +system.physmem.perBankRdBursts::2 38 # Per bank write bursts +system.physmem.perBankRdBursts::3 121 # Per bank write bursts +system.physmem.perBankRdBursts::4 55 # Per bank write bursts +system.physmem.perBankRdBursts::5 25 # Per bank write bursts +system.physmem.perBankRdBursts::6 10 # Per bank write bursts +system.physmem.perBankRdBursts::7 65 # Per bank write bursts +system.physmem.perBankRdBursts::8 146 # Per bank write bursts +system.physmem.perBankRdBursts::9 127 # Per bank write bursts +system.physmem.perBankRdBursts::10 24 # Per bank write bursts +system.physmem.perBankRdBursts::11 115 # Per bank write bursts +system.physmem.perBankRdBursts::12 141 # Per bank write bursts +system.physmem.perBankRdBursts::13 65 # Per bank write bursts +system.physmem.perBankRdBursts::14 16 # Per bank write bursts +system.physmem.perBankRdBursts::15 0 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 172126500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) 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+system.physmem.bytesPerActivate::gmean 231.543341 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 312.586766 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 43 21.72% 21.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 58 29.29% 51.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 28 14.14% 65.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 15 7.58% 72.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 11 5.56% 78.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 10 5.05% 83.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 10 5.05% 88.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 6 3.03% 91.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 17 8.59% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 198 # Bytes accessed per row activation +system.physmem.totQLat 14633000 # Total ticks spent queuing +system.physmem.totMemAccLat 35351750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5525000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13242.53 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 31992.53 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 410.18 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 410.18 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 3.20 # Data bus utilization in percentage +system.physmem.busUtilRead 3.20 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 900 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.45 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 155770.59 # Average gap between requests +system.physmem.pageHitRate 81.45 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 671160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 349140 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3362940 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 13522080.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 8624670 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 294240 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 60064890 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 8068320 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 94957440 # Total energy per rank (pJ) +system.physmem_0.averagePower 550.757283 # Core power per rank (mW) +system.physmem_0.totalIdleTime 152312250 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 144000 # Time in different power states +system.physmem_0.memoryStateTime::REF 5720000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 0 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 21008000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 13822000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 131718000 # Time in different power states +system.physmem_1.actEnergy 792540 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 402270 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4526760 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 12907440.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 10281660 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 517440 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 46847160 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 10329600 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 5665485 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 92308695 # Total energy per rank (pJ) +system.physmem_1.averagePower 535.394446 # Core power per rank (mW) +system.physmem_1.totalIdleTime 148210250 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 771500 # Time in different power states +system.physmem_1.memoryStateTime::REF 5472000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 18796250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 26899500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 17723250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 102749500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 172412000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 31216 # Number of BP lookups +system.cpu.branchPred.condPredicted 19719 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2267 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 28919 # Number of BTB lookups +system.cpu.branchPred.BTBHits 15185 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 52.508731 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 5724 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 3662 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 2062 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 1112 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 45 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 172412000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 344824 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 111969 # Number of instructions committed +system.cpu.committedOps 112000 # Number of ops (including micro ops) committed +system.cpu.discardedOps 6045 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 3.079638 # CPI: cycles per instruction +system.cpu.ipc 0.324713 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 45 0.04% 0.04% # Class of committed instruction +system.cpu.op_class_0::IntAlu 69340 61.91% 61.95% # Class of committed instruction +system.cpu.op_class_0::IntMult 105 0.09% 62.04% # Class of committed instruction +system.cpu.op_class_0::IntDiv 0 0.00% 62.04% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 0 0.00% 62.04% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 0 0.00% 62.04% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 0 0.00% 62.04% # Class of committed instruction +system.cpu.op_class_0::FloatMult 0 0.00% 62.04% # Class of committed instruction +system.cpu.op_class_0::FloatMultAcc 0 0.00% 62.04% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 0 0.00% 62.04% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 0 0.00% 62.04% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 62.04% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 62.04% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 62.04% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 62.04% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 62.04% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 62.04% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 62.04% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 62.04% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 62.04% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 62.04% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 62.04% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 62.04% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 62.04% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 62.04% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 62.04% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 0 0.00% 62.04% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 62.04% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 0 0.00% 62.04% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 62.04% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 62.04% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 62.04% # Class of committed instruction +system.cpu.op_class_0::MemRead 22348 19.95% 82.00% # Class of committed instruction +system.cpu.op_class_0::MemWrite 20162 18.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::total 112000 # Class of committed instruction +system.cpu.tickCycles 178647 # Number of cycles that the object actually ticked +system.cpu.idleCycles 166177 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 172412000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 216.406463 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42886 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 272 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 157.669118 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 216.406463 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.052834 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.052834 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 272 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 64 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 203 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.066406 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 86976 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 86976 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 172412000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 23112 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23112 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 19768 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 19768 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 2 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 2 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 4 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 4 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 42880 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42880 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42880 # number of overall hits +system.cpu.dcache.overall_hits::total 42880 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 77 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 77 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 389 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 389 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 466 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 466 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 466 # number of overall misses +system.cpu.dcache.overall_misses::total 466 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6810000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6810000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 31318000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 31318000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 38128000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 38128000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 38128000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 38128000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23189 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23189 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 20157 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 20157 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 2 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 4 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 4 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 43346 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 43346 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 43346 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 43346 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003321 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003321 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019299 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.019299 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.010751 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.010751 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.010751 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.010751 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 88441.558442 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 88441.558442 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80508.997429 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 80508.997429 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 81819.742489 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 81819.742489 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 81819.742489 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 81819.742489 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 188 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 188 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 194 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 194 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 194 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 194 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 71 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 71 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 201 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 201 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 272 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 272 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 272 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 272 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6167000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6167000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 16191000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 16191000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22358000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 22358000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22358000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 22358000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003062 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003062 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009972 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009972 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006275 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006275 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006275 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006275 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 86859.154930 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 86859.154930 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80552.238806 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80552.238806 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82198.529412 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 82198.529412 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82198.529412 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 82198.529412 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 172412000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 194 # number of replacements +system.cpu.icache.tags.tagsinuse 392.602869 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 52173 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 967 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 53.953464 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 392.602869 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.191701 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.191701 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 773 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 477 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 245 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.377441 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 107247 # Number of tag accesses +system.cpu.icache.tags.data_accesses 107247 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 172412000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 52173 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 52173 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 52173 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 52173 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 52173 # number of overall hits +system.cpu.icache.overall_hits::total 52173 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 967 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 967 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 967 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 967 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 967 # number of overall misses +system.cpu.icache.overall_misses::total 967 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 73518500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 73518500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 73518500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 73518500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 73518500 # number of overall miss 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# number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 80591000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 61363500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19227500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 80591000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.862461 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.862461 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.985915 # mshr miss rate for ReadSharedReq accesses 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distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 194 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 201 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 201 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 967 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 71 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2128 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 544 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2672 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 74304 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17408 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 91712 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 1239 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.001614 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.040161 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1237 99.84% 99.84% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 2 0.16% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1239 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 910500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1450500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 408000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 1105 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 172412000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 904 # Transaction distribution +system.membus.trans_dist::ReadExReq 201 # Transaction distribution +system.membus.trans_dist::ReadExResp 201 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 904 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2210 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2210 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 70720 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 70720 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1105 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1105 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 1105 # Request fanout histogram +system.membus.reqLayer0.occupancy 1245500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 5860500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 3.4 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/stats.txt --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/stats.txt Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,153 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000001 # Number of seconds simulated +sim_ticks 868000 # Number of ticks simulated +final_tick 868000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 14491 # Simulator instruction rate (inst/s) +host_op_rate 14487 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7283586 # Simulator tick rate (ticks/s) +host_mem_usage 251284 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host +sim_insts 1726 # Number of instructions simulated +sim_ops 1726 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 868000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 6948 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 2032 # Number of bytes read from this memory +system.physmem.bytes_read::total 8980 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 6948 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6948 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 2006 # Number of bytes written to this memory +system.physmem.bytes_written::total 2006 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1737 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 316 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2053 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 315 # Number of write requests responded to by this memory +system.physmem.num_writes::total 315 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 8004608295 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2341013825 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10345622120 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8004608295 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8004608295 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 2311059908 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2311059908 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8004608295 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4652073733 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 12656682028 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 868000 # Cumulative time (in ticks) in various power states +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 10 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 868000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 1737 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 1726 # Number of instructions committed +system.cpu.committedOps 1726 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1727 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 155 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 240 # number of instructions that are conditional controls +system.cpu.num_int_insts 1727 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 2243 # number of times the integer registers were read +system.cpu.num_int_register_writes 1171 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 632 # number of memory refs +system.cpu.num_load_insts 316 # Number of load instructions +system.cpu.num_store_insts 316 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 1737 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 395 # Number of branches fetched +system.cpu.op_class::No_OpClass 10 0.58% 0.58% # Class of executed instruction +system.cpu.op_class::IntAlu 1095 63.04% 63.62% # Class of executed instruction +system.cpu.op_class::IntMult 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::MemRead 316 18.19% 81.81% # Class of executed instruction +system.cpu.op_class::MemWrite 316 18.19% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 1737 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 868000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 2053 # Transaction distribution +system.membus.trans_dist::ReadResp 2053 # Transaction distribution +system.membus.trans_dist::WriteReq 315 # Transaction distribution +system.membus.trans_dist::WriteResp 315 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 3474 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1262 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4736 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 6948 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 4038 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 10986 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 2368 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 2368 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 2368 # Request fanout histogram + +---------- End Simulation Statistics ---------- diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/config.ini --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/config.ini Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,1265 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 + +[system] +type=System +children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges=0:268435455:0:0:0:0 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.sys_port_proxy.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=TimingSimpleCPU +children=clk_domain dtb interrupts isa itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu.clk_domain +cpu_id=0 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1] +icache_port=system.ruby.l1_cntrl0.sequencer.slave[0] + +[system.cpu.clk_domain] +type=SrcClockDomain +clock=1 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=hello +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/ar4jc/gem5/tests/testing/../test-progs/hello/bin/riscv/linux/hello +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000 + +[system.mem_ctrls] +type=DRAMCtrl +IDD0=0.055000 +IDD02=0.000000 +IDD2N=0.032000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.032000 +IDD2P12=0.000000 +IDD3N=0.038000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.038000 +IDD3P12=0.000000 +IDD4R=0.157000 +IDD4R2=0.000000 +IDD4W=0.125000 +IDD4W2=0.000000 +IDD5=0.235000 +IDD52=0.000000 +IDD6=0.020000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +page_policy=open_adaptive +power_model=Null +range=0:268435455:5:19:0:0 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10 +static_frontend_latency=10 +tBURST=5 +tCCD_L=0 +tCK=1 +tCL=14 +tCS=3 +tRAS=35 +tRCD=14 +tREFI=7800 +tRFC=260 +tRP=14 +tRRD=6 +tRRD_L=0 +tRTP=8 +tRTW=3 +tWR=15 +tWTR=8 +tXAW=30 +tXP=6 +tXPDLL=0 +tXS=270 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.ruby.dir_cntrl0.memory + +[system.ruby] +type=RubySystem +children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network +access_backing_store=false +all_instructions=false +block_size_bytes=64 +clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +hot_lines=false +memory_size_bits=48 +num_of_sequencers=1 +number_of_virtual_networks=5 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +phys_mem=Null +power_model=Null +randomization=false + +[system.ruby.clk_domain] +type=SrcClockDomain +clock=1 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.ruby.dir_cntrl0] +type=Directory_Controller +children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir requestToDir responseFromDir responseFromMemory +buffer_size=0 +clk_domain=system.ruby.clk_domain +cluster_id=0 +default_p_state=UNDEFINED +directory=system.ruby.dir_cntrl0.directory +directory_latency=12 +dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir +dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir +eventq_index=0 +forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir +number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +recycle_latency=10 +requestToDir=system.ruby.dir_cntrl0.requestToDir +responseFromDir=system.ruby.dir_cntrl0.responseFromDir +responseFromMemory=system.ruby.dir_cntrl0.responseFromMemory +ruby_system=system.ruby +system=system +to_memory_controller_latency=1 +transitions_per_cycle=4 +version=0 +memory=system.mem_ctrls.port + +[system.ruby.dir_cntrl0.directory] +type=RubyDirectoryMemory +eventq_index=0 +numa_high_bit=5 +size=268435456 +version=0 + +[system.ruby.dir_cntrl0.dmaRequestToDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[3] + +[system.ruby.dir_cntrl0.dmaResponseFromDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[3] + +[system.ruby.dir_cntrl0.forwardFromDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[4] + +[system.ruby.dir_cntrl0.requestToDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[2] + +[system.ruby.dir_cntrl0.responseFromDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[2] + +[system.ruby.dir_cntrl0.responseFromMemory] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false + +[system.ruby.l1_cntrl0] +type=L1Cache_Controller +children=cacheMemory forwardToCache mandatoryQueue requestFromCache responseFromCache responseToCache sequencer +buffer_size=0 +cacheMemory=system.ruby.l1_cntrl0.cacheMemory +cache_response_latency=12 +clk_domain=system.cpu.clk_domain +cluster_id=0 +default_p_state=UNDEFINED +eventq_index=0 +forwardToCache=system.ruby.l1_cntrl0.forwardToCache +issue_latency=2 +mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue +number_of_TBEs=256 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +recycle_latency=10 +requestFromCache=system.ruby.l1_cntrl0.requestFromCache +responseFromCache=system.ruby.l1_cntrl0.responseFromCache +responseToCache=system.ruby.l1_cntrl0.responseToCache +ruby_system=system.ruby +send_evictions=false +sequencer=system.ruby.l1_cntrl0.sequencer +system=system +transitions_per_cycle=4 +version=0 + +[system.ruby.l1_cntrl0.cacheMemory] +type=RubyCache +children=replacement_policy +assoc=2 +block_size=0 +dataAccessLatency=1 +dataArrayBanks=1 +eventq_index=0 +is_icache=false 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ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_links0 int_links1 int_links2 int_links3 routers0 routers1 routers2 +adaptive_routing=false +buffer_size=0 +clk_domain=system.ruby.clk_domain +control_msg_size=8 +default_p_state=UNDEFINED +endpoint_bandwidth=1000 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+type=SimpleIntLink +bandwidth_factor=16 +dst_inport= +dst_node=system.ruby.network.routers1 +eventq_index=0 +latency=1 +link_id=5 +src_node=system.ruby.network.routers2 +src_outport= +weight=1 + +[system.ruby.network.routers0] +type=Switch +children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 +clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 system.ruby.network.routers0.port_buffers12 system.ruby.network.routers0.port_buffers13 system.ruby.network.routers0.port_buffers14 +power_model=Null +router_id=0 +virt_nets=5 + +[system.ruby.network.routers0.port_buffers00] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers01] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers02] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers03] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers0.port_buffers04] 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system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 system.ruby.network.routers1.port_buffers12 system.ruby.network.routers1.port_buffers13 system.ruby.network.routers1.port_buffers14 +power_model=Null +router_id=1 +virt_nets=5 + +[system.ruby.network.routers1.port_buffers00] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers01] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers1.port_buffers02] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true 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port_buffers18 port_buffers19 +clk_domain=system.ruby.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19 +power_model=Null +router_id=2 +virt_nets=5 + +[system.ruby.network.routers2.port_buffers00] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers01] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers02] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers03] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers04] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.routers2.port_buffers05] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + 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+eventq_index=0 +is_cpu_sequencer=true +no_retry_on_stall=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000 +p_state_clk_gate_min=1 +power_model=Null +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_ruby_tester=false +version=0 +slave=system.system_port + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/config.json --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/config.json Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,1734 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + 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true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.itb", + "type": "RiscvTLB", + "size": 64 + }, + "system": "system", + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "TimingSimpleCPU", + "max_loads_all_threads": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "function_trace_start": 0, + "cpu_id": 0, + "checker": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "do_quiesce": true, + "type": "TimingSimpleCPU", + "profile": 0, + "icache_port": { + "peer": "system.ruby.l1_cntrl0.sequencer.slave[0]", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "p_state_clk_gate_min": 1, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "dcache_port": { + "peer": "system.ruby.l1_cntrl0.sequencer.slave[1]", + "role": "MASTER" + }, + "socket_id": 0, + "power_model": null, + "max_insts_all_threads": 0, + "path": "system.cpu", + "max_loads_any_thread": 0, + "switched_out": false, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/hello/bin/riscv/linux/hello", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "hello" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "progress_interval": 0, + "branchPred": null, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + }, + "multi_thread": false, + "mem_ctrls": [ + { + "static_frontend_latency": 10, + "tRFC": 260, + "activation_limit": 4, + "in_addr_map": true, + "IDD3N2": "0.0", + "tWTR": 8, + "IDD52": "0.0", + "clk_domain": "system.clk_domain", + "channels": 1, + "write_buffer_size": 64, + "device_bus_width": 8, + "VDD": "1.5", + "write_high_thresh_perc": 85, + "cxx_class": "DRAMCtrl", + "bank_groups_per_rank": 0, + "IDD2N2": "0.0", + "port": { + "peer": "system.ruby.dir_cntrl0.memory", + "role": "SLAVE" + }, + "tCCD_L": 0, + "IDD2N": "0.032", + "p_state_clk_gate_min": 1, + "null": false, + "IDD2P1": "0.032", + "eventq_index": 0, + "tRRD": 6, + "tRTW": 3, + "IDD4R": "0.157", + "burst_length": 8, + "tRTP": 8, + "IDD4W": "0.125", + "tWR": 15, + "banks_per_rank": 8, + "devices_per_rank": 8, + "IDD2P02": "0.0", + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000, + "IDD6": "0.02", + "IDD5": "0.235", + "tRCD": 14, + "type": "DRAMCtrl", + "IDD3P02": "0.0", + "tRRD_L": 0, + "IDD0": "0.055", + "IDD62": "0.0", + "min_writes_per_switch": 16, + "mem_sched_policy": "frfcfs", + "IDD02": "0.0", + "IDD2P0": "0.0", + "ranks_per_channel": 2, + "page_policy": "open_adaptive", + "IDD4W2": "0.0", + "tCS": 3, + "power_model": null, + "tCL": 14, + "read_buffer_size": 32, + "conf_table_reported": true, + "tCK": 1, + "tRAS": 35, + "tRP": 14, + "tBURST": 5, + "path": "system.mem_ctrls", + "tXP": 6, + "tXS": 270, + "addr_mapping": "RoRaBaCoCh", + "IDD3P0": "0.0", + "IDD3P1": "0.038", + "IDD3N": "0.038", + "name": "mem_ctrls", + "tXSDLL": 0, + "device_size": 536870912, + "kvm_map": true, + "dll": true, + "tXAW": 30, + "write_low_thresh_perc": 50, + "range": "0:268435455:5:19:0:0", + "VDD2": "0.0", + "IDD2P12": "0.0", + "p_state_clk_gate_bins": 20, + "tXPDLL": 0, + "IDD4R2": "0.0", + "device_rowbuffer_size": 1024, + "static_backend_latency": 10, + "max_accesses_per_row": 16, + "IDD3P12": "0.0", + "tREFI": 7800 + } + ], + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/simerr --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/simerr Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,11 @@ +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick +warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/simout --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/simout Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,15 @@ +Redirecting stdout to build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/simple-timing-ruby/simout +Redirecting stderr to build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/simple-timing-ruby/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Oct 28 2016 00:48:50 +gem5 started Oct 28 2016 16:39:17 +gem5 executing on ubuntu1604, pid 11226 +command line: /home/ar4jc/gem5/build/RISCV/gem5.debug -d build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/simple-timing-ruby -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/00.hello/riscv/linux/simple-timing-ruby + +Global frequency set at 1000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Hello world! +Exiting @ tick 31501 because target called exit() diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/stats.txt --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing-ruby/stats.txt Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,640 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000032 # Number of seconds simulated +sim_ticks 31501 # Number of ticks simulated +final_tick 31501 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000 # Frequency of simulated ticks +host_inst_rate 4797 # Simulator instruction rate (inst/s) +host_op_rate 4797 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 87535 # Simulator tick rate (ticks/s) +host_mem_usage 420760 # Number of bytes of host memory used +host_seconds 0.36 # Real time elapsed on the host +sim_insts 1726 # Number of instructions simulated +sim_ops 1726 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1 # Clock period in ticks +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 31501 # Cumulative time (in ticks) in various power states +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 32768 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 32768 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 32512 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 32512 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 512 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 512 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 508 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 508 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 1040220945 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 1040220945 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 1032094219 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 1032094219 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 2072315165 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 2072315165 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 512 # Number of read requests accepted +system.mem_ctrls.writeReqs 508 # Number of write requests accepted +system.mem_ctrls.readBursts 512 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 508 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 16384 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 16384 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 15168 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 32768 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 32512 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 256 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 246 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 105 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 72 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 55 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 24 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 102 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 59 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 53 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 23 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.totGap 31149 # Total gap between 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does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 36 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 874.666667 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 764.477013 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 297.445121 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 1 2.78% 2.78% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 2 5.56% 8.33% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 2 5.56% 13.89% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 1 2.78% 16.67% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 1 2.78% 19.44% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 1 2.78% 22.22% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 3 8.33% 30.56% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 25 69.44% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 36 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 14 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 17.500000 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 16.942538 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 5.585007 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::12-13 1 7.14% 7.14% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::14-15 4 28.57% 35.71% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-17 4 28.57% 64.29% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::18-19 4 28.57% 92.86% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::36-37 1 7.14% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 14 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 14 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.928571 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.881864 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 1.328057 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 9 64.29% 64.29% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 2 14.29% 78.57% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 3 21.43% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 14 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 3485 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 8349 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 1280 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 13.61 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 32.61 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 520.11 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 481.51 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 1040.22 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 1032.09 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 7.83 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 4.06 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 3.76 # Data bus utilization in percentage for writes +system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 24.19 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 224 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 232 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 87.50 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 88.55 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 30.54 # Average gap between requests +system.mem_ctrls.pageHitRate 88.03 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 264180 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 139104 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 2924544 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 1979424 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 2458560.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 4828128 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 51456 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.actPowerDownEnergy 9474312 # Energy for active power-down per rank (pJ) +system.mem_ctrls_0.prePowerDownEnergy 768 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.mem_ctrls_0.totalEnergy 22120476 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 702.215041 # Core power per rank (mW) +system.mem_ctrls_0.totalIdleTime 20742 # Total Idle time Per DRAM Rank +system.mem_ctrls_0.memoryStateTime::IDLE 22 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 1040 # Time in different power states +system.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 2 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 9660 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 20777 # Time in different power states +system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 224352 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 3002880 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.mem_ctrls_1.prePowerDownEnergy 2889984 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_1.selfRefreshEnergy 3759120 # Energy for self refresh per rank (pJ) +system.mem_ctrls_1.totalEnergy 11105616 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 352.548046 # Core power per rank (mW) +system.mem_ctrls_1.totalIdleTime 7526 # Total Idle time Per DRAM Rank +system.mem_ctrls_1.memoryStateTime::IDLE 7786 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 526 # Time in different power states +system.mem_ctrls_1.memoryStateTime::SREF 15663 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 7526 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 31501 # Cumulative time (in ticks) in various power states +system.cpu.clk_domain.clock 1 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 10 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 31501 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 31501 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 1726 # Number of instructions committed +system.cpu.committedOps 1726 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1727 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 155 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 240 # number of instructions that are conditional controls +system.cpu.num_int_insts 1727 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 2243 # number of times the integer registers were read +system.cpu.num_int_register_writes 1171 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 632 # number of memory refs +system.cpu.num_load_insts 316 # Number of load instructions +system.cpu.num_store_insts 316 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 31501 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 395 # Number of branches fetched +system.cpu.op_class::No_OpClass 10 0.58% 0.58% # Class of executed instruction +system.cpu.op_class::IntAlu 1095 63.04% 63.62% # Class of executed instruction +system.cpu.op_class::IntMult 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.62% # Class of executed instruction +system.cpu.op_class::MemRead 316 18.19% 81.81% # Class of executed instruction +system.cpu.op_class::MemWrite 316 18.19% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 1737 # Class of executed instruction +system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.pwrStateResidencyTicks::UNDEFINED 31501 # Cumulative time (in ticks) in various power states +system.ruby.delayHist::bucket_size 1 # delay histogram for all message +system.ruby.delayHist::max_bucket 9 # delay histogram for all message +system.ruby.delayHist::samples 1020 # delay histogram for all message +system.ruby.delayHist | 1020 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 1020 # delay histogram for all message +system.ruby.outstanding_req_hist_seqr::bucket_size 1 +system.ruby.outstanding_req_hist_seqr::max_bucket 9 +system.ruby.outstanding_req_hist_seqr::samples 2369 +system.ruby.outstanding_req_hist_seqr::mean 1 +system.ruby.outstanding_req_hist_seqr::gmean 1 +system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 2369 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 2369 +system.ruby.latency_hist_seqr::bucket_size 64 +system.ruby.latency_hist_seqr::max_bucket 639 +system.ruby.latency_hist_seqr::samples 2368 +system.ruby.latency_hist_seqr::mean 12.302787 +system.ruby.latency_hist_seqr::gmean 2.308257 +system.ruby.latency_hist_seqr::stdev 25.747612 +system.ruby.latency_hist_seqr | 2125 89.74% 89.74% | 231 9.76% 99.49% | 9 0.38% 99.87% | 1 0.04% 99.92% | 1 0.04% 99.96% | 1 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist_seqr::total 2368 +system.ruby.hit_latency_hist_seqr::bucket_size 1 +system.ruby.hit_latency_hist_seqr::max_bucket 9 +system.ruby.hit_latency_hist_seqr::samples 1856 +system.ruby.hit_latency_hist_seqr::mean 1 +system.ruby.hit_latency_hist_seqr::gmean 1 +system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 1856 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 1856 +system.ruby.miss_latency_hist_seqr::bucket_size 64 +system.ruby.miss_latency_hist_seqr::max_bucket 639 +system.ruby.miss_latency_hist_seqr::samples 512 +system.ruby.miss_latency_hist_seqr::mean 53.275391 +system.ruby.miss_latency_hist_seqr::gmean 47.883882 +system.ruby.miss_latency_hist_seqr::stdev 30.409668 +system.ruby.miss_latency_hist_seqr | 269 52.54% 52.54% | 231 45.12% 97.66% | 9 1.76% 99.41% | 1 0.20% 99.61% | 1 0.20% 99.80% | 1 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist_seqr::total 512 +system.ruby.Directory.incomplete_times_seqr 511 +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 31501 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.cacheMemory.demand_hits 1856 # Number of cache demand hits +system.ruby.l1_cntrl0.cacheMemory.demand_misses 512 # Number of cache demand misses +system.ruby.l1_cntrl0.cacheMemory.demand_accesses 2368 # Number of cache demand accesses +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 31501 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 31501 # Cumulative time (in ticks) in various power states +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 31501 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.percent_links_utilized 8.094981 +system.ruby.network.routers0.msg_count.Control::2 512 +system.ruby.network.routers0.msg_count.Data::2 508 +system.ruby.network.routers0.msg_count.Response_Data::4 512 +system.ruby.network.routers0.msg_count.Writeback_Control::3 508 +system.ruby.network.routers0.msg_bytes.Control::2 4096 +system.ruby.network.routers0.msg_bytes.Data::2 36576 +system.ruby.network.routers0.msg_bytes.Response_Data::4 36864 +system.ruby.network.routers0.msg_bytes.Writeback_Control::3 4064 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 31501 # Cumulative time (in ticks) in various power states +system.ruby.network.routers1.percent_links_utilized 8.094981 +system.ruby.network.routers1.msg_count.Control::2 512 +system.ruby.network.routers1.msg_count.Data::2 508 +system.ruby.network.routers1.msg_count.Response_Data::4 512 +system.ruby.network.routers1.msg_count.Writeback_Control::3 508 +system.ruby.network.routers1.msg_bytes.Control::2 4096 +system.ruby.network.routers1.msg_bytes.Data::2 36576 +system.ruby.network.routers1.msg_bytes.Response_Data::4 36864 +system.ruby.network.routers1.msg_bytes.Writeback_Control::3 4064 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 31501 # Cumulative time (in ticks) in various power states +system.ruby.network.routers2.percent_links_utilized 8.094981 +system.ruby.network.routers2.msg_count.Control::2 512 +system.ruby.network.routers2.msg_count.Data::2 508 +system.ruby.network.routers2.msg_count.Response_Data::4 512 +system.ruby.network.routers2.msg_count.Writeback_Control::3 508 +system.ruby.network.routers2.msg_bytes.Control::2 4096 +system.ruby.network.routers2.msg_bytes.Data::2 36576 +system.ruby.network.routers2.msg_bytes.Response_Data::4 36864 +system.ruby.network.routers2.msg_bytes.Writeback_Control::3 4064 +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 31501 # Cumulative time (in ticks) in various power states +system.ruby.network.msg_count.Control 1536 +system.ruby.network.msg_count.Data 1524 +system.ruby.network.msg_count.Response_Data 1536 +system.ruby.network.msg_count.Writeback_Control 1524 +system.ruby.network.msg_byte.Control 12288 +system.ruby.network.msg_byte.Data 109728 +system.ruby.network.msg_byte.Response_Data 110592 +system.ruby.network.msg_byte.Writeback_Control 12192 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 31501 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.throttle0.link_utilization 8.120377 +system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 512 +system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 508 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 36864 +system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 4064 +system.ruby.network.routers0.throttle1.link_utilization 8.069585 +system.ruby.network.routers0.throttle1.msg_count.Control::2 512 +system.ruby.network.routers0.throttle1.msg_count.Data::2 508 +system.ruby.network.routers0.throttle1.msg_bytes.Control::2 4096 +system.ruby.network.routers0.throttle1.msg_bytes.Data::2 36576 +system.ruby.network.routers1.throttle0.link_utilization 8.069585 +system.ruby.network.routers1.throttle0.msg_count.Control::2 512 +system.ruby.network.routers1.throttle0.msg_count.Data::2 508 +system.ruby.network.routers1.throttle0.msg_bytes.Control::2 4096 +system.ruby.network.routers1.throttle0.msg_bytes.Data::2 36576 +system.ruby.network.routers1.throttle1.link_utilization 8.120377 +system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 512 +system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 508 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 36864 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 4064 +system.ruby.network.routers2.throttle0.link_utilization 8.120377 +system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 512 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 508 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 36864 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 4064 +system.ruby.network.routers2.throttle1.link_utilization 8.069585 +system.ruby.network.routers2.throttle1.msg_count.Control::2 512 +system.ruby.network.routers2.throttle1.msg_count.Data::2 508 +system.ruby.network.routers2.throttle1.msg_bytes.Control::2 4096 +system.ruby.network.routers2.throttle1.msg_bytes.Data::2 36576 +system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::samples 512 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1 | 512 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::total 512 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::samples 508 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2 | 508 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::total 508 # delay histogram for vnet_2 +system.ruby.LD.latency_hist_seqr::bucket_size 32 +system.ruby.LD.latency_hist_seqr::max_bucket 319 +system.ruby.LD.latency_hist_seqr::samples 316 +system.ruby.LD.latency_hist_seqr::mean 21.898734 +system.ruby.LD.latency_hist_seqr::gmean 5.918634 +system.ruby.LD.latency_hist_seqr::stdev 26.171156 +system.ruby.LD.latency_hist_seqr | 165 52.22% 52.22% | 108 34.18% 86.39% | 41 12.97% 99.37% | 1 0.32% 99.68% | 0 0.00% 99.68% | 1 0.32% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist_seqr::total 316 +system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 +system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 +system.ruby.LD.hit_latency_hist_seqr::samples 165 +system.ruby.LD.hit_latency_hist_seqr::mean 1 +system.ruby.LD.hit_latency_hist_seqr::gmean 1 +system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 165 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::total 165 +system.ruby.LD.miss_latency_hist_seqr::bucket_size 32 +system.ruby.LD.miss_latency_hist_seqr::max_bucket 319 +system.ruby.LD.miss_latency_hist_seqr::samples 151 +system.ruby.LD.miss_latency_hist_seqr::mean 44.735099 +system.ruby.LD.miss_latency_hist_seqr::gmean 41.308523 +system.ruby.LD.miss_latency_hist_seqr::stdev 20.807275 +system.ruby.LD.miss_latency_hist_seqr | 0 0.00% 0.00% | 108 71.52% 71.52% | 41 27.15% 98.68% | 1 0.66% 99.34% | 0 0.00% 99.34% | 1 0.66% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist_seqr::total 151 +system.ruby.ST.latency_hist_seqr::bucket_size 32 +system.ruby.ST.latency_hist_seqr::max_bucket 319 +system.ruby.ST.latency_hist_seqr::samples 315 +system.ruby.ST.latency_hist_seqr::mean 14.952381 +system.ruby.ST.latency_hist_seqr::gmean 3.255165 +system.ruby.ST.latency_hist_seqr::stdev 23.992321 +system.ruby.ST.latency_hist_seqr | 215 68.25% 68.25% | 70 22.22% 90.48% | 28 8.89% 99.37% | 1 0.32% 99.68% | 0 0.00% 99.68% | 1 0.32% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist_seqr::total 315 +system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 +system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 +system.ruby.ST.hit_latency_hist_seqr::samples 215 +system.ruby.ST.hit_latency_hist_seqr::mean 1 +system.ruby.ST.hit_latency_hist_seqr::gmean 1 +system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 215 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist_seqr::total 215 +system.ruby.ST.miss_latency_hist_seqr::bucket_size 32 +system.ruby.ST.miss_latency_hist_seqr::max_bucket 319 +system.ruby.ST.miss_latency_hist_seqr::samples 100 +system.ruby.ST.miss_latency_hist_seqr::mean 44.950000 +system.ruby.ST.miss_latency_hist_seqr::gmean 41.172297 +system.ruby.ST.miss_latency_hist_seqr::stdev 22.226736 +system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 70 70.00% 70.00% | 28 28.00% 98.00% | 1 1.00% 99.00% | 0 0.00% 99.00% | 1 1.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist_seqr::total 100 +system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.latency_hist_seqr::samples 1737 +system.ruby.IFETCH.latency_hist_seqr::mean 10.076569 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.827326 +system.ruby.IFETCH.latency_hist_seqr::stdev 25.544292 +system.ruby.IFETCH.latency_hist_seqr | 1567 90.21% 90.21% | 160 9.21% 99.42% | 7 0.40% 99.83% | 1 0.06% 99.88% | 1 0.06% 99.94% | 1 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::total 1737 +system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 +system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 +system.ruby.IFETCH.hit_latency_hist_seqr::samples 1476 +system.ruby.IFETCH.hit_latency_hist_seqr::mean 1 +system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 +system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 1476 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist_seqr::total 1476 +system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.miss_latency_hist_seqr::samples 261 +system.ruby.IFETCH.miss_latency_hist_seqr::mean 61.406130 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 55.262538 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 35.273489 +system.ruby.IFETCH.miss_latency_hist_seqr | 91 34.87% 34.87% | 160 61.30% 96.17% | 7 2.68% 98.85% | 1 0.38% 99.23% | 1 0.38% 99.62% | 1 0.38% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::total 261 +system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 +system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 +system.ruby.Directory.miss_mach_latency_hist_seqr::samples 512 +system.ruby.Directory.miss_mach_latency_hist_seqr::mean 53.275391 +system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 47.883882 +system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 30.409668 +system.ruby.Directory.miss_mach_latency_hist_seqr | 269 52.54% 52.54% | 231 45.12% 97.66% | 9 1.76% 99.41% | 1 0.20% 99.61% | 1 0.20% 99.80% | 1 0.20% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist_seqr::total 512 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::total 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::bucket_size 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::max_bucket 9 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.forward_to_first_response::total 1 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::bucket_size 8 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::max_bucket 79 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::samples 1 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean 75 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 75.000000 +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% +system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 151 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 44.735099 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 41.308523 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 20.807275 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 108 71.52% 71.52% | 41 27.15% 98.68% | 1 0.66% 99.34% | 0 0.00% 99.34% | 1 0.66% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 151 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 100 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 44.950000 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 41.172297 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 22.226736 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 70 70.00% 70.00% | 28 28.00% 98.00% | 1 1.00% 99.00% | 0 0.00% 99.00% | 1 1.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 100 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 261 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 61.406130 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 55.262538 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 35.273489 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 91 34.87% 34.87% | 160 61.30% 96.17% | 7 2.68% 98.85% | 1 0.38% 99.23% | 1 0.38% 99.62% | 1 0.38% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 261 +system.ruby.Directory_Controller.GETX 512 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 508 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 512 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 508 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 512 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 508 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 512 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 508 0.00% 0.00% +system.ruby.L1Cache_Controller.Load 316 0.00% 0.00% +system.ruby.L1Cache_Controller.Ifetch 1737 0.00% 0.00% +system.ruby.L1Cache_Controller.Store 315 0.00% 0.00% +system.ruby.L1Cache_Controller.Data 512 0.00% 0.00% +system.ruby.L1Cache_Controller.Replacement 508 0.00% 0.00% +system.ruby.L1Cache_Controller.Writeback_Ack 508 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Load 151 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Ifetch 261 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Store 100 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Load 165 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Ifetch 1476 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Store 215 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Replacement 508 0.00% 0.00% +system.ruby.L1Cache_Controller.MI.Writeback_Ack 508 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Data 412 0.00% 0.00% +system.ruby.L1Cache_Controller.IM.Data 100 0.00% 0.00% + +---------- End Simulation Statistics ---------- diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/00.hello/ref/riscv/linux/simple-timing/config.ini --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing/config.ini Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,374 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=TimingSimpleCPU +children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +hit_latency=2 +is_read_only=false +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=262144 + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.icache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +hit_latency=2 +is_read_only=true +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tags=system.cpu.icache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=131072 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.l2cache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +hit_latency=20 +is_read_only=false +max_miss_count=0 +mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +hit_latency=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=2097152 + +[system.cpu.toL2Bus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=0 +frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null +response_latency=1 +snoop_filter=system.cpu.toL2Bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=hello +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/ar4jc/gem5/tests/testing/../test-progs/hello/bin/riscv/linux/hello +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +eventq_index=0 +in_addr_map=true +kvm_map=true +latency=30000 +latency_var=0 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +range=0:134217727:0:0:0:0 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/00.hello/ref/riscv/linux/simple-timing/config.json --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-timing/config.json Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,502 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.l2cache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "physmem": { + "range": "0:134217727:0:0:0:0", + "latency": 30000, + "name": "physmem", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "kvm_map": true, + "clk_domain": "system.clk_domain", + "power_model": null, + "latency_var": 0, + "bandwidth": "73.000000", + "conf_table_reported": true, + "cxx_class": "SimpleMemory", + "p_state_clk_gate_max": 1000000000000, + "path": "system.physmem", + "null": false, + "type": "SimpleMemory", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "in_addr_map": true + }, + "power_model": null, + "work_cpus_ckpt_count": 0, + "thermal_components": [], + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "work_end_ckpt_count": 0, + "mem_mode": "timing", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": [ + { + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.itb", + "type": "RiscvTLB", + "size": 64 + }, + "system": "system", + "icache": { + "cpu_side": { + "peer": "system.cpu.icache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 131072, + "tags": { + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.icache.tags", + "hit_latency": 2, + "block_size": 64, + "type": "LRU", + "size": 131072 + }, + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[0]", + "role": "MASTER" + }, + "type": "Cache", + "writeback_clean": true, + "p_state_clk_gate_min": 1000, + "hit_latency": 2, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": true, + "prefetch_on_access": false, + "path": "system.cpu.icache", + "mshrs": 4, + "name": "icache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "TimingSimpleCPU", + "max_loads_all_threads": 0, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "cpu_id": 0, + "checker": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "toL2Bus": { + "point_of_coherency": false, + "system": "system", + "response_latency": 1, + "cxx_class": "CoherentXBar", + "forward_latency": 0, + "clk_domain": "system.cpu_clk_domain", + "width": 32, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.cpu.l2cache.cpu_side" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 1, + "slave": { + "peer": [ + "system.cpu.icache.mem_side", + "system.cpu.dcache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.cpu.toL2Bus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 0 + }, + "power_model": null, + "path": "system.cpu.toL2Bus", + "snoop_response_latency": 1, + "name": "toL2Bus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "do_quiesce": true, + "type": "TimingSimpleCPU", + "profile": 0, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "p_state_clk_gate_min": 1000, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "role": "MASTER" + }, + "socket_id": 0, + "power_model": null, + "max_insts_all_threads": 0, + "l2cache": { + "cpu_side": { + "peer": "system.cpu.toL2Bus.master[0]", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 20, + "cxx_class": "Cache", + "size": 2097152, + "tags": { + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 8, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.l2cache.tags", + "hit_latency": 20, + "block_size": 64, + "type": "LRU", + "size": 2097152 + }, + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.membus.slave[1]", + "role": "MASTER" + }, + "type": "Cache", + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "hit_latency": 20, + "tgts_per_mshr": 12, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.l2cache", + "mshrs": 20, + "name": "l2cache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 8 + }, + "path": "system.cpu", + "max_loads_any_thread": 0, + "switched_out": false, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/hello/bin/riscv/linux/hello", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "hello" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "progress_interval": 0, + "branchPred": null, + "dcache": { + "cpu_side": { + "peer": "system.cpu.dcache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 262144, + "tags": { + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.dcache.tags", + "hit_latency": 2, + "block_size": 64, + "type": "LRU", + "size": 262144 + }, + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[1]", + "role": "MASTER" + }, + "type": "Cache", + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "hit_latency": 2, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.dcache", + "mshrs": 4, + "name": "dcache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/00.hello/ref/riscv/linux/o3-timing/simerr --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/simerr Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,4 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/00.hello/ref/riscv/linux/o3-timing/simout --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/simout Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,15 @@ +Redirecting stdout to build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/o3-timing/simout +Redirecting stderr to build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/o3-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Oct 28 2016 00:48:50 +gem5 started Oct 28 2016 16:35:04 +gem5 executing on ubuntu1604, pid 11007 +command line: /home/ar4jc/gem5/build/RISCV/gem5.debug -d build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/o3-timing -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/00.hello/riscv/linux/o3-timing + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Hello world! +Exiting @ tick 8508000 because target called exit() diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/00.hello/ref/riscv/linux/o3-timing/stats.txt --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/stats.txt Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,994 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000009 # Number of seconds simulated +sim_ticks 8508000 # Number of ticks simulated +final_tick 8508000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 5512 # Simulator instruction rate (inst/s) +host_op_rate 5512 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 27166098 # Simulator tick rate (ticks/s) +host_mem_usage 264352 # Number of bytes of host memory used +host_seconds 0.31 # Real time elapsed on the host +sim_insts 1726 # Number of instructions simulated +sim_ops 1726 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 8508000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 10368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 2240 # Number of bytes read from this memory +system.physmem.bytes_read::total 12608 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 10368 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 10368 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 162 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 35 # Number of read requests responded to by this memory +system.physmem.num_reads::total 197 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1218617772 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 263281617 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1481899389 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1218617772 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1218617772 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1218617772 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 263281617 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1481899389 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 197 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 197 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12608 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12608 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 96 # Per bank write bursts +system.physmem.perBankRdBursts::1 67 # Per bank write bursts +system.physmem.perBankRdBursts::2 23 # Per bank write bursts +system.physmem.perBankRdBursts::3 11 # Per bank write bursts +system.physmem.perBankRdBursts::4 0 # Per bank write bursts +system.physmem.perBankRdBursts::5 0 # Per bank write bursts +system.physmem.perBankRdBursts::6 0 # Per bank write bursts +system.physmem.perBankRdBursts::7 0 # Per bank write bursts +system.physmem.perBankRdBursts::8 0 # Per bank write bursts +system.physmem.perBankRdBursts::9 0 # Per bank write bursts +system.physmem.perBankRdBursts::10 0 # Per bank write bursts +system.physmem.perBankRdBursts::11 0 # Per bank write bursts +system.physmem.perBankRdBursts::12 0 # Per bank write bursts +system.physmem.perBankRdBursts::13 0 # Per bank write bursts +system.physmem.perBankRdBursts::14 0 # Per bank write bursts +system.physmem.perBankRdBursts::15 0 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 8403000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 197 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 97 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 66 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 24 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 13 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 925.538462 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 900.458833 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 194.850633 # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1 7.69% 7.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 15.38% 23.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10 76.92% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 13 # Bytes accessed per row activation +system.physmem.totQLat 1880750 # Total ticks spent queuing +system.physmem.totMemAccLat 5574500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 985000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9546.95 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 28296.95 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1481.90 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1481.90 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 11.58 # Data bus utilization in percentage +system.physmem.busUtilRead 11.58 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.92 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 183 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 92.89 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 42654.82 # Average gap between requests +system.physmem.pageHitRate 92.89 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 99960 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 49335 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1406580 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 614640.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1680360 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 15360 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 2181390 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 6047625 # Total energy per rank (pJ) +system.physmem_0.averagePower 710.753636 # Core power per rank (mW) +system.physmem_0.totalIdleTime 4713000 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 11500 # Time in different power states +system.physmem_0.memoryStateTime::REF 260000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 0 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 3454750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 4781750 # Time in different power states +system.physmem_1.actEnergy 0 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 0 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 0 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 614640.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 112290 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2995200 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 177600 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 3899730 # Total energy per rank (pJ) +system.physmem_1.averagePower 458.319965 # Core power per rank (mW) +system.physmem_1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 7786250 # Time in different power states +system.physmem_1.memoryStateTime::REF 260000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 0 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 461750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 8508000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 1312 # Number of BP lookups +system.cpu.branchPred.condPredicted 705 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 273 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 1246 # Number of BTB lookups +system.cpu.branchPred.BTBHits 302 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 24.237560 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 272 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 16 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 256 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 76 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 10 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 8508000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 17017 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.fetch.icacheStallCycles 3223 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 5546 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1312 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 318 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1022 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 570 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 4 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 51 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 847 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 201 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 4590 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.208279 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.638241 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 3592 78.26% 78.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 147 3.20% 81.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 89 1.94% 83.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 80 1.74% 85.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 47 1.02% 86.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 32 0.70% 86.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 70 1.53% 88.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 51 1.11% 89.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 482 10.50% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 4590 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.077099 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.325909 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 3137 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 411 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 821 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 25 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 196 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 207 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 90 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 4348 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 352 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 196 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 3249 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 130 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 279 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 734 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3996 # Number of instructions processed by rename +system.cpu.rename.LQFullEvents 3 # Number of times rename has blocked due to LQ full +system.cpu.rename.RenamedOperands 2831 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5087 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 5087 # Number of integer rename lookups +system.cpu.rename.CommittedMaps 1171 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 1660 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 19 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 19 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 87 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 637 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 556 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 3448 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 21 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 3057 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 18 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1742 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 912 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 4590 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.666013 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.517602 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 3583 78.06% 78.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 291 6.34% 84.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 168 3.66% 88.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 145 3.16% 91.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 177 3.86% 95.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 121 2.64% 97.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 65 1.42% 99.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 28 0.61% 99.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 12 0.26% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 4590 # Number of insts issued each cycle +system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8 10.96% 10.96% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 10.96% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 10.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 10.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 10.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 10.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 10.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 10.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.96% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 35 47.95% 58.90% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 30 41.10% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.FU_type_0::No_OpClass 10 0.33% 0.33% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1994 65.23% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.03% 65.59% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 65.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 65.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 65.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.59% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 590 19.30% 84.89% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 462 15.11% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::total 3057 # Type of FU issued +system.cpu.iq.rate 0.179644 # Inst issue rate +system.cpu.iq.fu_busy_cnt 73 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023880 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 10795 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 5212 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2665 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 3120 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 25 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu.iew.lsq.thread0.squashedLoads 321 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 241 # Number of stores squashed +system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu.iew.iewSquashCycles 196 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 131 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 3469 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 85 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 637 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 556 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 21 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 11 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 216 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 227 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2825 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 542 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 232 # Number of squashed instructions skipped in execute +system.cpu.iew.exec_swp 0 # number of swp insts executed +system.cpu.iew.exec_nop 0 # number of nop insts executed +system.cpu.iew.exec_refs 973 # number of memory reference insts executed +system.cpu.iew.exec_branches 639 # Number of branches executed +system.cpu.iew.exec_stores 431 # Number of stores executed +system.cpu.iew.exec_rate 0.166010 # Inst execution rate +system.cpu.iew.wb_sent 2722 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2665 # cumulative count of insts written-back +system.cpu.iew.wb_producers 916 # num instructions producing a value +system.cpu.iew.wb_consumers 1300 # num instructions consuming a value +system.cpu.iew.wb_rate 0.156608 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.704615 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 1742 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 184 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 4263 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.404879 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.213986 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 3621 84.94% 84.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 229 5.37% 90.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 147 3.45% 93.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 102 2.39% 96.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 58 1.36% 97.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 39 0.91% 98.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 22 0.52% 98.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 22 0.52% 99.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 23 0.54% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 4263 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1726 # Number of instructions committed +system.cpu.commit.committedOps 1726 # Number of ops (including micro ops) committed +system.cpu.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu.commit.refs 631 # Number of memory references committed +system.cpu.commit.loads 316 # Number of loads committed +system.cpu.commit.membars 0 # Number of memory barriers committed +system.cpu.commit.branches 395 # Number of branches committed +system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu.commit.int_insts 1726 # Number of committed integer instructions. +system.cpu.commit.function_calls 155 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 1095 63.44% 63.44% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 0 0.00% 63.44% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 63.44% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 63.44% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.44% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.44% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 63.44% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 63.44% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.44% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMisc 0 0.00% 63.44% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 63.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.44% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.44% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 316 18.31% 81.75% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 315 18.25% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 1726 # Class of committed instruction +system.cpu.commit.bw_lim_events 23 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 7578 # The number of ROB reads +system.cpu.rob.rob_writes 7270 # The number of ROB writes +system.cpu.timesIdled 98 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 12427 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1726 # Number of Instructions Simulated +system.cpu.committedOps 1726 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 9.859212 # CPI: Cycles Per Instruction +system.cpu.cpi_total 9.859212 # CPI: Total CPI of All Threads +system.cpu.ipc 0.101428 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.101428 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3523 # number of integer regfile reads +system.cpu.int_regfile_writes 1930 # number of integer regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 8508000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 24.761696 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 716 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 35 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 20.457143 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 24.761696 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.006045 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.006045 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 35 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.008545 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1683 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1683 # Number of data accesses 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199 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.993865 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.993865 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993865 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.994975 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993865 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.994975 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76973.684211 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76973.684211 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79922.839506 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79922.839506 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73588.235294 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73588.235294 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79922.839506 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75375 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 79095.959596 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79922.839506 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75375 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 79095.959596 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 19 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 19 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 162 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 162 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 17 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 17 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 162 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 36 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 198 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 162 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 36 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 198 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1272500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1272500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11327500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11327500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1091000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1091000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11327500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2363500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 13691000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11327500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2363500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 13691000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.993865 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.993865 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993865 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.994975 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993865 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.994975 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66973.684211 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66973.684211 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69922.839506 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69922.839506 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64176.470588 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64176.470588 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69922.839506 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65652.777778 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69146.464646 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69922.839506 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65652.777778 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69146.464646 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 199 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 8508000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 179 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 19 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 19 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 163 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 17 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 326 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 71 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 397 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10432 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2240 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 12672 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 199 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.005025 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.070888 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 198 99.50% 99.50% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1 0.50% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 199 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 99500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 244500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 52500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 197 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 8508000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 178 # Transaction distribution +system.membus.trans_dist::ReadExReq 19 # Transaction distribution +system.membus.trans_dist::ReadExResp 19 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 178 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 394 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 12608 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 12608 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 197 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 197 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 197 # Request fanout histogram +system.membus.reqLayer0.occupancy 245000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 1026250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 12.1 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/config.ini --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/config.ini Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,211 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=atomic +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=AtomicSimpleCPU +children=dtb interrupts isa itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fastmem=false +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +simulate_data_stalls=false +simulate_inst_stalls=false +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +width=1 +workload=system.cpu.workload +dcache_port=system.membus.slave[2] +icache_port=system.membus.slave[1] + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=hello +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/ar4jc/gem5/tests/testing/../test-progs/hello/bin/riscv/linux/hello +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.icache_port system.cpu.dcache_port + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +eventq_index=0 +in_addr_map=true +kvm_map=true +latency=30000 +latency_var=0 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +range=0:134217727:0:0:0:0 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/config.json --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/config.json Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,289 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.icache_port", + "system.cpu.dcache_port" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + "type": "SnoopFilter", + "lookup_latency": 1 + }, + "power_model": null, + "path": "system.membus", + "snoop_response_latency": 4, + "name": "membus", + "p_state_clk_gate_bins": 20, + "use_default_range": false + }, + "symbolfile": "", + "readfile": "", + "thermal_model": null, + "cxx_class": "System", + "work_begin_cpu_id_exit": -1, + "load_offset": 0, + "work_begin_exit_count": 0, + "p_state_clk_gate_min": 1000, + "memories": [ + "system.physmem" + ], + "work_begin_ckpt_count": 0, + "clk_domain": { + "name": "clk_domain", + "clock": [ + 1000 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "mem_ranges": [], + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "dvfs_handler": { + "enable": false, + "name": "dvfs_handler", + "sys_clk_domain": "system.clk_domain", + "transition_latency": 100000000, + "eventq_index": 0, + "cxx_class": "DVFSHandler", + "domains": [], + "path": "system.dvfs_handler", + "type": "DVFSHandler" + }, + "work_end_exit_count": 0, + "type": "System", + "voltage_domain": { + "name": "voltage_domain", + "eventq_index": 0, + "voltage": [ + "1.0" + ], + "cxx_class": "VoltageDomain", + "path": "system.voltage_domain", + "type": "VoltageDomain" + }, + "cache_line_size": 64, + "boot_osflags": "a", + "system_port": { + "peer": "system.membus.slave[0]", + "role": "MASTER" + }, + "physmem": { + "range": "0:134217727:0:0:0:0", + "latency": 30000, + "name": "physmem", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "kvm_map": true, + "clk_domain": "system.clk_domain", + "power_model": null, + "latency_var": 0, + "bandwidth": "73.000000", + "conf_table_reported": true, + "cxx_class": "SimpleMemory", + "p_state_clk_gate_max": 1000000000000, + "path": "system.physmem", + "null": false, + "type": "SimpleMemory", + "port": { + "peer": "system.membus.master[0]", + "role": "SLAVE" + }, + "in_addr_map": true + }, + "power_model": null, + "work_cpus_ckpt_count": 0, + "thermal_components": [], + "path": "system", + "cpu_clk_domain": { + "name": "cpu_clk_domain", + "clock": [ + 500 + ], + "init_perf_level": 0, + "voltage_domain": "system.voltage_domain", + "eventq_index": 0, + "cxx_class": "SrcClockDomain", + "path": "system.cpu_clk_domain", + "type": "SrcClockDomain", + "domain_id": -1 + }, + "work_end_ckpt_count": 0, + "mem_mode": "atomic", + "name": "system", + "init_param": 0, + "p_state_clk_gate_bins": 20, + "load_addr_mask": 1099511627775, + "cpu": [ + { + "do_statistics_insts": true, + "numThreads": 1, + "itb": { + "name": "itb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.itb", + "type": "RiscvTLB", + "size": 64 + }, + "simulate_data_stalls": false, + "function_trace": false, + "do_checkpoint_insts": true, + "cxx_class": "AtomicSimpleCPU", + "max_loads_all_threads": 0, + "system": "system", + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "cpu_id": 0, + "width": 1, + "checker": null, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "do_quiesce": true, + "type": "AtomicSimpleCPU", + "fastmem": false, + "profile": 0, + "icache_port": { + "peer": "system.membus.slave[1]", + "role": "MASTER" + }, + "p_state_clk_gate_bins": 20, + "p_state_clk_gate_min": 1000, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "dcache_port": { + "peer": "system.membus.slave[2]", + "role": "MASTER" + }, + "socket_id": 0, + "power_model": null, + "max_insts_all_threads": 0, + "path": "system.cpu", + "max_loads_any_thread": 0, + "switched_out": false, + "workload": [ + { + "uid": 100, + "pid": 100, + "kvmInSE": false, + "cxx_class": "LiveProcess", + "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/hello/bin/riscv/linux/hello", + "drivers": [], + "system": "system", + "gid": 100, + "eventq_index": 0, + "env": [], + "input": "cin", + "ppid": 99, + "type": "LiveProcess", + "cwd": "", + "simpoint": 0, + "euid": 100, + "path": "system.cpu.workload", + "max_stack_size": 67108864, + "name": "workload", + "cmd": [ + "hello" + ], + "errout": "cerr", + "useArchPT": false, + "egid": 100, + "output": "cout" + } + ], + "name": "cpu", + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "simulate_inst_stalls": false, + "progress_interval": 0, + "branchPred": null, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "tracer": { + "eventq_index": 0, + "path": "system.cpu.tracer", + "type": "ExeTracer", + "name": "tracer", + "cxx_class": "Trace::ExeTracer" + } + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/simerr --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/simerr Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,3 @@ +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/simout --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/00.hello/ref/riscv/linux/simple-atomic/simout Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,15 @@ +Redirecting stdout to build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/simple-atomic/simout +Redirecting stderr to build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/simple-atomic/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Oct 28 2016 00:48:50 +gem5 started Oct 28 2016 01:10:06 +gem5 executing on ubuntu1604, pid 9506 +command line: /home/ar4jc/gem5/build/RISCV/gem5.debug -d build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/simple-atomic -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/00.hello/riscv/linux/simple-atomic + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Hello world! +Exiting @ tick 868000 because target called exit() diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/00.hello/ref/riscv/linux/minor-timing/simout --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/simout Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,15 @@ +Redirecting stdout to build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/minor-timing/simout +Redirecting stderr to build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/minor-timing/simerr +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Oct 28 2016 00:48:50 +gem5 started Oct 28 2016 16:32:24 +gem5 executing on ubuntu1604, pid 10798 +command line: /home/ar4jc/gem5/build/RISCV/gem5.debug -d build/RISCV/tests/debug/quick/se/00.hello/riscv/linux/minor-timing -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/00.hello/riscv/linux/minor-timing + +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Hello world! +Exiting @ tick 15452000 because target called exit() diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/00.hello/ref/riscv/linux/minor-timing/stats.txt --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/stats.txt Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,744 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000015 # Number of seconds simulated +sim_ticks 15452000 # Number of ticks simulated +final_tick 15452000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 8128 # Simulator instruction rate (inst/s) +host_op_rate 8127 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 72286676 # Simulator tick rate (ticks/s) +host_mem_usage 262812 # Number of bytes of host memory used +host_seconds 0.21 # Real time elapsed on the host +sim_insts 1737 # Number of instructions simulated +sim_ops 1737 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 15452000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 10624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 2304 # Number of bytes read from this memory +system.physmem.bytes_read::total 12928 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 10624 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 10624 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 166 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 36 # Number of read requests responded to by this memory +system.physmem.num_reads::total 202 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 687548537 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 149106912 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 836655449 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 687548537 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 687548537 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 687548537 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 149106912 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 836655449 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 202 # Number of read requests accepted +system.physmem.writeReqs 0 # Number of write requests accepted +system.physmem.readBursts 202 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12928 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 0 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12928 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 99 # Per bank write bursts +system.physmem.perBankRdBursts::1 68 # Per bank write bursts +system.physmem.perBankRdBursts::2 24 # Per bank write bursts +system.physmem.perBankRdBursts::3 11 # Per bank write bursts +system.physmem.perBankRdBursts::4 0 # Per bank write bursts +system.physmem.perBankRdBursts::5 0 # Per bank write bursts +system.physmem.perBankRdBursts::6 0 # Per bank write bursts +system.physmem.perBankRdBursts::7 0 # Per bank write bursts +system.physmem.perBankRdBursts::8 0 # Per bank write bursts +system.physmem.perBankRdBursts::9 0 # Per bank write bursts +system.physmem.perBankRdBursts::10 0 # Per bank write bursts +system.physmem.perBankRdBursts::11 0 # Per bank write bursts +system.physmem.perBankRdBursts::12 0 # Per bank write bursts +system.physmem.perBankRdBursts::13 0 # Per bank write bursts +system.physmem.perBankRdBursts::14 0 # Per bank write bursts +system.physmem.perBankRdBursts::15 0 # Per bank write bursts +system.physmem.perBankWrBursts::0 0 # Per bank write bursts +system.physmem.perBankWrBursts::1 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::3 0 # Per bank write bursts +system.physmem.perBankWrBursts::4 0 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 0 # Per bank write bursts +system.physmem.perBankWrBursts::7 0 # Per bank write bursts +system.physmem.perBankWrBursts::8 0 # Per bank write bursts +system.physmem.perBankWrBursts::9 0 # Per bank write bursts +system.physmem.perBankWrBursts::10 0 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 0 # Per bank write bursts +system.physmem.perBankWrBursts::13 0 # Per bank write bursts +system.physmem.perBankWrBursts::14 0 # Per bank write bursts +system.physmem.perBankWrBursts::15 0 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 15211000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 0 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 202 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 0 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 0 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 174 # What read 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+system.physmem.bytesPerActivate::mean 836.571429 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 720.747106 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.665031 # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 2 14.29% 14.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1 7.14% 21.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1 7.14% 28.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10 71.43% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 14 # Bytes accessed per row activation +system.physmem.totQLat 1617500 # Total ticks spent queuing +system.physmem.totMemAccLat 5405000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1010000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8007.43 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 26757.43 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 836.66 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 836.66 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 6.54 # Data bus utilization in percentage +system.physmem.busUtilRead 6.54 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.14 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing +system.physmem.readRowHits 184 # Number of row buffer hits during reads +system.physmem.writeRowHits 0 # Number of row buffer hits during writes +system.physmem.readRowHitRate 91.09 # Row buffer hit rate for reads +system.physmem.writeRowHitRate nan # Row buffer hit rate for writes +system.physmem.avgGap 75301.98 # Average gap between requests +system.physmem.pageHitRate 91.09 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 128520 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 53130 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1442280 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 614640.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2436750 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 15360 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 4591350 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 9282030 # Total energy per rank (pJ) +system.physmem_0.averagePower 600.681443 # Core power per rank (mW) +system.physmem_0.totalIdleTime 9861500 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 12000 # Time in different power states +system.physmem_0.memoryStateTime::REF 260000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 0 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 5114250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 10065750 # Time in different power states +system.physmem_1.actEnergy 0 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 0 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 0 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 614640.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 112290 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2995200 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 2844000 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 6566130 # Total energy per rank (pJ) +system.physmem_1.averagePower 424.923475 # Core power per rank (mW) +system.physmem_1.totalIdleTime 0 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 7786250 # Time in different power states +system.physmem_1.memoryStateTime::REF 260000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 0 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 7405750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 15452000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 1050 # Number of BP lookups +system.cpu.branchPred.condPredicted 574 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 238 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 995 # Number of BTB lookups +system.cpu.branchPred.BTBHits 88 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 8.844221 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 217 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 13 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 204 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 70 # Number of mispredicted indirect branches. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 10 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 15452000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 30904 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 1737 # Number of instructions committed +system.cpu.committedOps 1737 # Number of ops (including micro ops) committed +system.cpu.discardedOps 783 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching +system.cpu.cpi 17.791595 # CPI: cycles per instruction +system.cpu.ipc 0.056206 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 10 0.58% 0.58% # Class of committed instruction +system.cpu.op_class_0::IntAlu 1095 63.04% 63.62% # Class of committed instruction +system.cpu.op_class_0::IntMult 0 0.00% 63.62% # Class of committed instruction +system.cpu.op_class_0::IntDiv 0 0.00% 63.62% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 0 0.00% 63.62% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 0 0.00% 63.62% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 0 0.00% 63.62% # Class of committed instruction +system.cpu.op_class_0::FloatMult 0 0.00% 63.62% # Class of committed instruction +system.cpu.op_class_0::FloatMultAcc 0 0.00% 63.62% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 0 0.00% 63.62% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 0 0.00% 63.62% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 63.62% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 63.62% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 63.62% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 63.62% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 63.62% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 63.62% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 63.62% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 63.62% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 63.62% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 63.62% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 63.62% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 63.62% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 63.62% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 63.62% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 63.62% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 0 0.00% 63.62% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 63.62% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 0 0.00% 63.62% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 63.62% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 63.62% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 63.62% # Class of committed instruction +system.cpu.op_class_0::MemRead 316 18.19% 81.81% # Class of committed instruction +system.cpu.op_class_0::MemWrite 316 18.19% 100.00% # Class of committed instruction +system.cpu.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::total 1737 # Class of committed instruction +system.cpu.tickCycles 4374 # Number of cycles that the object actually ticked +system.cpu.idleCycles 26530 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 15452000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 25.327596 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 712 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 36 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 19.777778 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 25.327596 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.006183 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.006183 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 36 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.008789 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1556 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1556 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 15452000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 427 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 427 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 285 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 285 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 712 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 712 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 712 # number of overall hits +system.cpu.dcache.overall_hits::total 712 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 18 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 18 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 30 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 30 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 48 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 48 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 48 # number of overall misses +system.cpu.dcache.overall_misses::total 48 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1471500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1471500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2374500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2374500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 3846000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 3846000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 3846000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 3846000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 445 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 445 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 315 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 315 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 760 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 760 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 760 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 760 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040449 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040449 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.095238 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.095238 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.063158 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.063158 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.063158 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.063158 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 81750 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 81750 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79150 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 79150 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 80125 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 80125 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 80125 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 80125 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 12 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 12 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 12 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 12 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 12 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 12 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 18 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 18 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 18 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 18 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 36 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 36 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 36 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 36 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1453500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1453500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1415500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1415500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 2869000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 2869000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 2869000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 2869000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040449 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040449 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057143 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057143 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.047368 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.047368 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.047368 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.047368 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80750 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80750 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78638.888889 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78638.888889 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 79694.444444 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 79694.444444 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 79694.444444 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 79694.444444 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 15452000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 0 # number of replacements +system.cpu.icache.tags.tagsinuse 85.636913 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 730 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 167 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 4.371257 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 85.636913 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.041815 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.041815 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 167 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.081543 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 1961 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1961 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 15452000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 730 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 730 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 730 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 730 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 730 # number of overall hits +system.cpu.icache.overall_hits::total 730 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 167 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 167 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 167 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 167 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 167 # number of overall misses +system.cpu.icache.overall_misses::total 167 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13301500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13301500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13301500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13301500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13301500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13301500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 897 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 897 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 897 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 897 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 897 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 897 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.186176 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.186176 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.186176 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.186176 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.186176 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.186176 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 79649.700599 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 79649.700599 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 79649.700599 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 79649.700599 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 79649.700599 # average overall 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average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 79250 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 79250 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77545.180723 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78194.444444 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77660.891089 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77545.180723 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78194.444444 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77660.891089 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 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(read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 36 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 202 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 166 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 36 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 202 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1208500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1208500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11212500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11212500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1246500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1246500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11212500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2455000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 13667500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11212500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2455000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 13667500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.994012 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.994012 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994012 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.995074 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994012 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.995074 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67138.888889 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67138.888889 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67545.180723 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67545.180723 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69250 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69250 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67545.180723 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68194.444444 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67660.891089 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67545.180723 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68194.444444 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67660.891089 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 203 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 15452000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 185 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 18 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 18 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 167 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 18 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 334 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 72 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 406 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10688 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2304 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 12992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 203 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.004926 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.070186 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 202 99.51% 99.51% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1 0.49% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 203 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 101500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 250500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 54000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 202 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 15452000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 184 # Transaction distribution +system.membus.trans_dist::ReadExReq 18 # Transaction distribution +system.membus.trans_dist::ReadExResp 18 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 184 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 404 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 404 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 12928 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 12928 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoopTraffic 0 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 202 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 202 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 202 # Request fanout histogram +system.membus.reqLayer0.occupancy 221000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 1063250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 6.9 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/00.hello/ref/riscv/linux/o3-timing/config.ini --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/config.ini Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,866 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=DerivO3CPU +children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +branchPred=system.cpu.branchPred +cachePorts=200 +checker=Null +clk_domain=system.cpu_clk_domain +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +default_p_state=UNDEFINED +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 +fetchQueueSize=32 +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu.fuPool +function_trace=false +function_trace_start=0 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +needsTSO=false +numIQEntries=64 +numPhysCCRegs=0 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +simpoint_start_insts= +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +socket_id=0 +squashWidth=8 +store_set_clear_period=250000 +switched_out=false +system=system +tracer=system.cpu.tracer +trapLatency=13 +wbWidth=8 +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TournamentBP +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +useIndirect=true + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +hit_latency=2 +is_read_only=false +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=262144 + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 + +[system.cpu.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +eventq_index=0 +opList=system.cpu.fuPool.FUList0.opList + +[system.cpu.fuPool.FUList0.opList] +type=OpDesc +eventq_index=0 +opClass=IntAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 + +[system.cpu.fuPool.FUList1.opList0] +type=OpDesc +eventq_index=0 +opClass=IntMult +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList1.opList1] +type=OpDesc +eventq_index=0 +opClass=IntDiv +opLat=20 +pipelined=false + +[system.cpu.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 + +[system.cpu.fuPool.FUList2.opList0] +type=OpDesc +eventq_index=0 +opClass=FloatAdd +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList2.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatCmp +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList2.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatCvt +opLat=2 +pipelined=true + +[system.cpu.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 opList3 opList4 +count=2 +eventq_index=0 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4 + +[system.cpu.fuPool.FUList3.opList0] +type=OpDesc +eventq_index=0 +opClass=FloatMult +opLat=4 +pipelined=true + +[system.cpu.fuPool.FUList3.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMultAcc +opLat=5 +pipelined=true + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMisc +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList3.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatDiv +opLat=12 +pipelined=false + +[system.cpu.fuPool.FUList3.opList4] +type=OpDesc +eventq_index=0 +opClass=FloatSqrt +opLat=24 +pipelined=false + +[system.cpu.fuPool.FUList4] +type=FUDesc +children=opList0 opList1 +count=0 +eventq_index=0 +opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1 + +[system.cpu.fuPool.FUList4.opList0] +type=OpDesc +eventq_index=0 +opClass=MemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList4.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5] +type=FUDesc +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 + +[system.cpu.fuPool.FUList5.opList00] +type=OpDesc +eventq_index=0 +opClass=SimdAdd +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList01] +type=OpDesc +eventq_index=0 +opClass=SimdAddAcc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList02] +type=OpDesc +eventq_index=0 +opClass=SimdAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList03] +type=OpDesc +eventq_index=0 +opClass=SimdCmp +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList04] +type=OpDesc +eventq_index=0 +opClass=SimdCvt +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList05] +type=OpDesc +eventq_index=0 +opClass=SimdMisc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList06] +type=OpDesc +eventq_index=0 +opClass=SimdMult +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList07] +type=OpDesc +eventq_index=0 +opClass=SimdMultAcc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList08] +type=OpDesc +eventq_index=0 +opClass=SimdShift +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList09] +type=OpDesc +eventq_index=0 +opClass=SimdShiftAcc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList10] +type=OpDesc +eventq_index=0 +opClass=SimdSqrt +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList11] +type=OpDesc +eventq_index=0 +opClass=SimdFloatAdd +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList12] +type=OpDesc +eventq_index=0 +opClass=SimdFloatAlu +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList13] +type=OpDesc +eventq_index=0 +opClass=SimdFloatCmp +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList14] +type=OpDesc +eventq_index=0 +opClass=SimdFloatCvt +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList15] +type=OpDesc +eventq_index=0 +opClass=SimdFloatDiv +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList16] +type=OpDesc +eventq_index=0 +opClass=SimdFloatMisc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList17] +type=OpDesc +eventq_index=0 +opClass=SimdFloatMult +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList18] +type=OpDesc +eventq_index=0 +opClass=SimdFloatMultAcc +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList5.opList19] +type=OpDesc +eventq_index=0 +opClass=SimdFloatSqrt +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList6] +type=FUDesc +children=opList0 opList1 +count=0 +eventq_index=0 +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 + +[system.cpu.fuPool.FUList6.opList0] +type=OpDesc +eventq_index=0 +opClass=MemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7] +type=FUDesc +children=opList0 opList1 opList2 opList3 +count=4 +eventq_index=0 +opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3 + +[system.cpu.fuPool.FUList7.opList0] +type=OpDesc +eventq_index=0 +opClass=MemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7.opList1] +type=OpDesc +eventq_index=0 +opClass=MemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList8] +type=FUDesc +children=opList +count=1 +eventq_index=0 +opList=system.cpu.fuPool.FUList8.opList + +[system.cpu.fuPool.FUList8.opList] +type=OpDesc +eventq_index=0 +opClass=IprAccess +opLat=3 +pipelined=false + +[system.cpu.icache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +hit_latency=2 +is_read_only=true +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=131072 +system=system +tags=system.cpu.icache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=true +cpu_side=system.cpu.icache_port +mem_side=system.cpu.toL2Bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=131072 + +[system.cpu.interrupts] +type=RiscvInterrupts +eventq_index=0 + +[system.cpu.isa] +type=RiscvISA +eventq_index=0 + +[system.cpu.itb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.l2cache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=8 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +hit_latency=20 +is_read_only=false +max_miss_count=0 +mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=2097152 +system=system +tags=system.cpu.l2cache.tags +tgts_per_mshr=12 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +hit_latency=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=2097152 + +[system.cpu.toL2Bus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=0 +frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null +response_latency=1 +snoop_filter=system.cpu.toL2Bus.snoop_filter +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.cpu.toL2Bus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=0 +max_capacity=8388608 +system=system + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=hello +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/home/ar4jc/gem5/tests/testing/../test-progs/hello/bin/riscv/linux/hello +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu_clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.membus] +type=CoherentXBar +children=snoop_filter +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +forward_latency=4 +frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null +response_latency=2 +snoop_filter=system.membus.snoop_filter +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.physmem.port +slave=system.system_port system.cpu.l2cache.mem_side + +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + +[system.physmem] +type=DRAMCtrl +IDD0=0.055000 +IDD02=0.000000 +IDD2N=0.032000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.032000 +IDD2P12=0.000000 +IDD3N=0.038000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.038000 +IDD3P12=0.000000 +IDD4R=0.157000 +IDD4R2=0.000000 +IDD4W=0.125000 +IDD4W2=0.000000 +IDD5=0.235000 +IDD52=0.000000 +IDD6=0.020000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +default_p_state=UNDEFINED +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +kvm_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +page_policy=open_adaptive +power_model=Null +range=0:134217727:0:0:0:0 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCCD_L=0 +tCK=1250 +tCL=13750 +tCS=2500 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tXAW=30000 +tXP=6000 +tXPDLL=0 +tXS=270000 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/00.hello/ref/riscv/linux/o3-timing/config.json --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/00.hello/ref/riscv/linux/o3-timing/config.json Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,1145 @@ +{ + "name": null, + "sim_quantum": 0, + "system": { + "kernel": "", + "mmap_using_noreserve": false, + "kernel_addr_check": true, + "membus": { + "point_of_coherency": true, + "system": "system", + "response_latency": 2, + "cxx_class": "CoherentXBar", + "forward_latency": 4, + "clk_domain": "system.clk_domain", + "width": 16, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "master": { + "peer": [ + "system.physmem.port" + ], + "role": "MASTER" + }, + "type": "CoherentXBar", + "frontend_latency": 3, + "slave": { + "peer": [ + "system.system_port", + "system.cpu.l2cache.mem_side" + ], + "role": "SLAVE" + }, + "p_state_clk_gate_min": 1000, + "snoop_filter": { + "name": "snoop_filter", + "system": "system", + "max_capacity": 8388608, + "eventq_index": 0, + "cxx_class": "SnoopFilter", + "path": "system.membus.snoop_filter", + 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"opClass": "MemWrite", + "opLat": 1, + "name": "opList0", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList6.opList0", + "type": "OpDesc" + }, + { + "opClass": "FloatMemWrite", + "opLat": 1, + "name": "opList1", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList6.opList1", + "type": "OpDesc" + } + ], + "name": "FUList6", + "eventq_index": 0, + "cxx_class": "FUDesc", + "path": "system.cpu.fuPool.FUList6", + "type": "FUDesc" + }, + { + "count": 4, + "opList": [ + { + "opClass": "MemRead", + "opLat": 1, + "name": "opList0", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList7.opList0", + "type": "OpDesc" + }, + { + "opClass": "MemWrite", + "opLat": 1, + "name": "opList1", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList7.opList1", + "type": "OpDesc" + }, + { + "opClass": "FloatMemRead", + "opLat": 1, + "name": "opList2", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList7.opList2", + "type": "OpDesc" + }, + { + "opClass": "FloatMemWrite", + "opLat": 1, + "name": "opList3", + "pipelined": true, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList7.opList3", + "type": "OpDesc" + } + ], + "name": "FUList7", + "eventq_index": 0, + "cxx_class": "FUDesc", + "path": "system.cpu.fuPool.FUList7", + "type": "FUDesc" + }, + { + "count": 1, + "opList": [ + { + "opClass": "IprAccess", + "opLat": 3, + "name": "opList", + "pipelined": false, + "eventq_index": 0, + "cxx_class": "OpDesc", + "path": "system.cpu.fuPool.FUList8.opList", + "type": "OpDesc" + } + ], + "name": "FUList8", + "eventq_index": 0, + "cxx_class": "FUDesc", + "path": "system.cpu.fuPool.FUList8", + "type": "FUDesc" + } + ], + "eventq_index": 0, + "cxx_class": "FUPool", + "path": "system.cpu.fuPool", + "type": "FUPool" + }, + "socket_id": 0, + "renameToFetchDelay": 1, + "icache": { + "cpu_side": { + "peer": "system.cpu.icache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 131072, + "tags": { + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.icache.tags", + "hit_latency": 2, + "block_size": 64, + "type": "LRU", + "size": 131072 + }, + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[0]", + "role": "MASTER" + }, + "type": "Cache", + "writeback_clean": true, + "p_state_clk_gate_min": 1000, + "hit_latency": 2, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": true, + "prefetch_on_access": false, + "path": "system.cpu.icache", + "mshrs": 4, + "name": "icache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "path": "system.cpu", + "numRobs": 1, + "switched_out": false, + "smtLSQPolicy": "Partitioned", + "fetchBufferSize": 64, + "simpoint_start_insts": [], + "max_insts_any_thread": 0, + "smtROBThreshold": 100, + "numIQEntries": 64, + "branchPred": { + "numThreads": 1, + "BTBEntries": 4096, + "cxx_class": "TournamentBP", + "indirectPathLength": 3, + "globalCtrBits": 2, + "choicePredictorSize": 8192, + "indirectHashGHR": true, + "eventq_index": 0, + "localHistoryTableSize": 2048, + "type": "TournamentBP", + "indirectSets": 256, + "indirectWays": 2, + "choiceCtrBits": 2, + "useIndirect": true, + "localCtrBits": 2, + "path": "system.cpu.branchPred", + "localPredictorSize": 2048, + "RASSize": 16, + "globalPredictorSize": 8192, + "name": "branchPred", + "indirectHashTargets": true, + "instShiftAmt": 2, + "indirectTagSize": 16, + "BTBTagSize": 16 + }, + "LFSTSize": 1024, + "isa": [ + { + "eventq_index": 0, + "path": "system.cpu.isa", + "type": "RiscvISA", + "name": "isa", + "cxx_class": "RiscvISA::ISA" + } + ], + "smtROBPolicy": "Partitioned", + "iewToFetchDelay": 1, + "do_statistics_insts": true, + "dispatchWidth": 8, + "dcache": { + "cpu_side": { + "peer": "system.cpu.dcache_port", + "role": "SLAVE" + }, + "clusivity": "mostly_incl", + "prefetcher": null, + "system": "system", + "write_buffers": 8, + "response_latency": 2, + "cxx_class": "Cache", + "size": 262144, + "tags": { + "name": "tags", + "p_state_clk_gate_min": 1000, + "eventq_index": 0, + "p_state_clk_gate_bins": 20, + "default_p_state": "UNDEFINED", + "clk_domain": "system.cpu_clk_domain", + "power_model": null, + "sequential_access": false, + "assoc": 2, + "cxx_class": "LRU", + "p_state_clk_gate_max": 1000000000000, + "path": "system.cpu.dcache.tags", + "hit_latency": 2, + "block_size": 64, + "type": "LRU", + "size": 262144 + }, + "clk_domain": "system.cpu_clk_domain", + "max_miss_count": 0, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "p_state_clk_gate_max": 1000000000000, + "mem_side": { + "peer": "system.cpu.toL2Bus.slave[1]", + "role": "MASTER" + }, + "type": "Cache", + "writeback_clean": false, + "p_state_clk_gate_min": 1000, + "hit_latency": 2, + "tgts_per_mshr": 20, + "demand_mshr_reserve": 1, + "power_model": null, + "addr_ranges": [ + "0:18446744073709551615:0:0:0:0" + ], + "is_read_only": false, + "prefetch_on_access": false, + "path": "system.cpu.dcache", + "mshrs": 4, + "name": "dcache", + "p_state_clk_gate_bins": 20, + "sequential_access": false, + "assoc": 2 + }, + "commitToDecodeDelay": 1, + "smtIQPolicy": "Partitioned", + "issueWidth": 8, + "LSQCheckLoads": true, + "commitToRenameDelay": 1, + "cachePorts": 200, + "system": "system", + "checker": null, + "numPhysFloatRegs": 256, + "eventq_index": 0, + "default_p_state": "UNDEFINED", + "type": "DerivO3CPU", + "wbWidth": 8, + "interrupts": [ + { + "eventq_index": 0, + "path": "system.cpu.interrupts", + "type": "RiscvInterrupts", + "name": "interrupts", + "cxx_class": "RiscvISA::Interrupts" + } + ], + "smtCommitPolicy": "RoundRobin", + "issueToExecuteDelay": 1, + "dtb": { + "name": "dtb", + "eventq_index": 0, + "cxx_class": "RiscvISA::TLB", + "path": "system.cpu.dtb", + "type": "RiscvTLB", + "size": 64 + }, + "numROBEntries": 192, + "fetchQueueSize": 32, + "iewToCommitDelay": 1, + "smtNumFetchingThreads": 1, + "forwardComSize": 5, + "do_checkpoint_insts": true, + "cxx_class": "DerivO3CPU", + "commitToIEWDelay": 1, + "commitWidth": 8, + "clk_domain": "system.cpu_clk_domain", + "function_trace_start": 0, + "smtFetchPolicy": "SingleThread", + "profile": 0, + "icache_port": { + "peer": "system.cpu.icache.cpu_side", + "role": "MASTER" + }, + "dcache_port": { + "peer": "system.cpu.dcache.cpu_side", + "role": "MASTER" + }, + "LSQDepCheckShift": 4, + "trapLatency": 13, + "iewToDecodeDelay": 1, + "numPhysCCRegs": 0, + "renameToIEWDelay": 2, + "p_state_clk_gate_bins": 20, + "progress_interval": 0, + "LQEntries": 32 + } + ], + "multi_thread": false, + "exit_on_work_items": false, + "work_item_id": -1, + "num_work_ids": 16 + }, + "time_sync_period": 100000000000, + "eventq_index": 0, + "time_sync_spin_threshold": 100000000, + "cxx_class": "Root", + "path": "root", + "time_sync_enable": false, + "type": "Root", + "full_system": false +} \ No newline at end of file diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/00.hello/ref/riscv/linux/minor-timing/simerr --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/simerr Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,4 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) +warn: Unknown operating system; assuming Linux. +warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick diff -r 8aec19bd88f8 -r ea40d2a41efb tests/quick/se/00.hello/ref/riscv/linux/minor-timing/config.ini --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/tests/quick/se/00.hello/ref/riscv/linux/minor-timing/config.ini Mon Nov 28 15:24:45 2016 +0000 @@ -0,0 +1,896 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +default_p_state=UNDEFINED +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges= +memories=system.physmem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +readfile= +symbolfile= +thermal_components= +thermal_model=Null +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu] +type=MinorCPU +children=branchPred dcache dtb executeFuncUnits icache interrupts isa itb l2cache toL2Bus tracer workload +branchPred=system.cpu.branchPred +checker=Null +clk_domain=system.cpu_clk_domain +cpu_id=0 +decodeCycleInput=true +decodeInputBufferSize=3 +decodeInputWidth=2 +decodeToExecuteForwardDelay=1 +default_p_state=UNDEFINED +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +enableIdling=true +eventq_index=0 +executeAllowEarlyMemoryIssue=true +executeBranchDelay=1 +executeCommitLimit=2 +executeCycleInput=true +executeFuncUnits=system.cpu.executeFuncUnits +executeInputBufferSize=7 +executeInputWidth=2 +executeIssueLimit=2 +executeLSQMaxStoreBufferStoresPerCycle=2 +executeLSQRequestsQueueSize=1 +executeLSQStoreBufferSize=5 +executeLSQTransfersQueueSize=2 +executeMaxAccessesInMemory=2 +executeMemoryCommitLimit=1 +executeMemoryIssueLimit=1 +executeMemoryWidth=0 +executeSetTraceTimeOnCommit=true +executeSetTraceTimeOnIssue=false +fetch1FetchLimit=1 +fetch1LineSnapWidth=0 +fetch1LineWidth=0 +fetch1ToFetch2BackwardDelay=1 +fetch1ToFetch2ForwardDelay=1 +fetch2CycleInput=true +fetch2InputBufferSize=2 +fetch2ToDecodeForwardDelay=1 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +threadPolicy=RoundRobin +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.branchPred] +type=TournamentBP +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +eventq_index=0 +globalCtrBits=2 +globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 +instShiftAmt=2 +localCtrBits=2 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=1 +useIndirect=true + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615:0:0:0:0 +assoc=2 +clk_domain=system.cpu_clk_domain +clusivity=mostly_incl +default_p_state=UNDEFINED +demand_mshr_reserve=1 +eventq_index=0 +hit_latency=2 +is_read_only=false +max_miss_count=0 +mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=262144 +system=system +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +writeback_clean=false +cpu_side=system.cpu.dcache_port +mem_side=system.cpu.toL2Bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED +eventq_index=0 +hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null +sequential_access=false +size=262144 + +[system.cpu.dtb] +type=RiscvTLB +eventq_index=0 +size=64 + +[system.cpu.executeFuncUnits] +type=MinorFUPool +children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 +eventq_index=0 +funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 + +[system.cpu.executeFuncUnits.funcUnits0] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits0.timings + +[system.cpu.executeFuncUnits.funcUnits0.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits0.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits0.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits0.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits0.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits1] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits1.timings + +[system.cpu.executeFuncUnits.funcUnits1.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits1.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntAlu + +[system.cpu.executeFuncUnits.funcUnits1.timings] +type=MinorFUTiming +children=opClasses +description=Int +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits1.timings.opClasses +srcRegsRelativeLats=2 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits1.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits2] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses +opLat=3 +timings=system.cpu.executeFuncUnits.funcUnits2.timings + +[system.cpu.executeFuncUnits.funcUnits2.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits2.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntMult + +[system.cpu.executeFuncUnits.funcUnits2.timings] +type=MinorFUTiming +children=opClasses +description=Mul +eventq_index=0 +extraAssumedLat=0 +extraCommitLat=0 +extraCommitLatExpr=Null +mask=0 +match=0 +opClasses=system.cpu.executeFuncUnits.funcUnits2.timings.opClasses +srcRegsRelativeLats=0 +suppress=false + +[system.cpu.executeFuncUnits.funcUnits2.timings.opClasses] +type=MinorOpClassSet +eventq_index=0 +opClasses= + +[system.cpu.executeFuncUnits.funcUnits3] +type=MinorFU +children=opClasses +cantForwardFromFUIndices= +eventq_index=0 +issueLat=9 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses +opLat=9 +timings= + +[system.cpu.executeFuncUnits.funcUnits3.opClasses] +type=MinorOpClassSet +children=opClasses +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses + +[system.cpu.executeFuncUnits.funcUnits3.opClasses.opClasses] +type=MinorOpClass +eventq_index=0 +opClass=IntDiv + +[system.cpu.executeFuncUnits.funcUnits4] +type=MinorFU +children=opClasses timings +cantForwardFromFUIndices= +eventq_index=0 +issueLat=1 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses +opLat=6 +timings=system.cpu.executeFuncUnits.funcUnits4.timings + +[system.cpu.executeFuncUnits.funcUnits4.opClasses] +type=MinorOpClassSet +children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 opClasses26 opClasses27 +eventq_index=0 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 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