diff -r fcea8c1b00f7 -r aaf914ea5a83 tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/stats.txt --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/stats.txt Wed Jan 18 16:27:49 2017 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/stats.txt Wed Jan 18 16:41:56 2017 +0000 @@ -1,63 +1,63 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000257 # Number of seconds simulated -sim_ticks 257396500 # Number of ticks simulated -final_tick 257396500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000263 # Number of seconds simulated +sim_ticks 263193500 # Number of ticks simulated +final_tick 263193500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 23064 # Simulator instruction rate (inst/s) -host_op_rate 23064 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 29446323 # Simulator tick rate (ticks/s) -host_mem_usage 244684 # Number of bytes of host memory used -host_seconds 8.74 # Real time elapsed on the host -sim_insts 201609 # Number of instructions simulated -sim_ops 201609 # Number of ops (including micro ops) simulated +host_inst_rate 28458 # Simulator instruction rate (inst/s) +host_op_rate 28458 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 34549155 # Simulator tick rate (ticks/s) +host_mem_usage 266040 # Number of bytes of host memory used +host_seconds 7.62 # Real time elapsed on the host +sim_insts 216793 # Number of instructions simulated +sim_ops 216793 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 257396500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 70720 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18880 # Number of bytes read from this memory -system.physmem.bytes_read::total 89600 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 70720 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 70720 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 1105 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 295 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1400 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 274751211 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 73349871 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 348101081 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 274751211 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 274751211 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 274751211 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 73349871 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 348101081 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1400 # Number of read requests accepted +system.physmem.pwrStateResidencyTicks::UNDEFINED 263193500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 68800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18112 # Number of bytes read from this memory +system.physmem.bytes_read::total 86912 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 68800 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 68800 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 1075 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 283 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1358 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 261404632 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 68816289 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 330220921 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 261404632 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 261404632 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 261404632 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 68816289 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 330220921 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1358 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 1400 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 1358 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 89600 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 86912 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 89600 # Total read bytes from the system interface side +system.physmem.bytesReadSys 86912 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 195 # Per bank write bursts -system.physmem.perBankRdBursts::1 221 # Per bank write bursts -system.physmem.perBankRdBursts::2 35 # Per bank write bursts -system.physmem.perBankRdBursts::3 87 # Per bank write bursts -system.physmem.perBankRdBursts::4 141 # Per bank write bursts -system.physmem.perBankRdBursts::5 86 # Per bank write bursts -system.physmem.perBankRdBursts::6 5 # Per bank write bursts -system.physmem.perBankRdBursts::7 106 # Per bank write bursts -system.physmem.perBankRdBursts::8 78 # Per bank write bursts -system.physmem.perBankRdBursts::9 96 # Per bank write bursts -system.physmem.perBankRdBursts::10 80 # Per bank write bursts -system.physmem.perBankRdBursts::11 128 # Per bank write bursts -system.physmem.perBankRdBursts::12 40 # Per bank write bursts -system.physmem.perBankRdBursts::13 27 # Per bank write bursts -system.physmem.perBankRdBursts::14 51 # Per bank write bursts -system.physmem.perBankRdBursts::15 24 # Per bank write bursts +system.physmem.perBankRdBursts::0 168 # Per bank write bursts +system.physmem.perBankRdBursts::1 27 # Per bank write bursts +system.physmem.perBankRdBursts::2 147 # Per bank write bursts +system.physmem.perBankRdBursts::3 88 # Per bank write bursts +system.physmem.perBankRdBursts::4 12 # Per bank write bursts +system.physmem.perBankRdBursts::5 122 # Per bank write bursts +system.physmem.perBankRdBursts::6 68 # Per bank write bursts +system.physmem.perBankRdBursts::7 30 # Per bank write bursts +system.physmem.perBankRdBursts::8 115 # Per bank write bursts +system.physmem.perBankRdBursts::9 89 # Per bank write bursts +system.physmem.perBankRdBursts::10 73 # Per bank write bursts +system.physmem.perBankRdBursts::11 106 # Per bank write bursts +system.physmem.perBankRdBursts::12 27 # Per bank write bursts +system.physmem.perBankRdBursts::13 62 # Per bank write bursts +system.physmem.perBankRdBursts::14 80 # Per bank write bursts +system.physmem.perBankRdBursts::15 144 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -76,14 +76,14 @@ system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 257156500 # Total gap between requests +system.physmem.totGap 262830500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1400 # Read request sizes (log2) +system.physmem.readPktSize::6 1358 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -91,9 +91,9 @@ system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1337 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 60 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1301 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 52 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -187,94 +187,94 @@ system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 274 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 323.270073 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 216.910663 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 283.246990 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 71 25.91% 25.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 59 21.53% 47.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 52 18.98% 66.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 26 9.49% 75.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 14 5.11% 81.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 23 8.39% 89.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8 2.92% 92.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3 1.09% 93.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 18 6.57% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 274 # Bytes accessed per row activation -system.physmem.totQLat 19864500 # Total ticks spent queuing -system.physmem.totMemAccLat 46114500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 7000000 # Total ticks spent in databus transfers -system.physmem.avgQLat 14188.93 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 249 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 339.277108 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 229.795656 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 286.689769 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 62 24.90% 24.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 50 20.08% 44.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 41 16.47% 61.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 32 12.85% 74.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 20 8.03% 82.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 14 5.62% 87.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 9 3.61% 91.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3 1.20% 92.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 18 7.23% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 249 # Bytes accessed per row activation +system.physmem.totQLat 18609500 # Total ticks spent queuing +system.physmem.totMemAccLat 44072000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 6790000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13703.61 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32938.93 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 348.10 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 32453.61 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 330.22 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 348.10 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 330.22 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.72 # Data bus utilization in percentage -system.physmem.busUtilRead 2.72 # Data bus utilization in percentage for reads +system.physmem.busUtil 2.58 # Data bus utilization in percentage +system.physmem.busUtilRead 2.58 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 1124 # Number of row buffer hits during reads +system.physmem.readRowHits 1099 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.29 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.93 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 183683.21 # Average gap between requests -system.physmem.pageHitRate 80.29 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1299480 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 690690 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 6254640 # Energy for read commands per rank (pJ) +system.physmem.avgGap 193542.34 # Average gap between requests +system.physmem.pageHitRate 80.93 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1013880 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 519915 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4726680 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 20283120.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 14953950 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 477120 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 94483770 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 6205440 # Energy for precharge power-down per rank (pJ) +system.physmem_0.actBackEnergy 12241890 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 473280 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 97257960 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 8382720 # Energy for precharge power-down per rank (pJ) system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 144648210 # Total energy per rank (pJ) -system.physmem_0.averagePower 561.964316 # Core power per rank (mW) -system.physmem_0.totalIdleTime 223185500 # Total Idle time Per DRAM Rank +system.physmem_0.totalEnergy 144899445 # Total energy per rank (pJ) +system.physmem_0.averagePower 550.542880 # Core power per rank (mW) +system.physmem_0.totalIdleTime 234516000 # Total Idle time Per DRAM Rank system.physmem_0.memoryStateTime::IDLE 210000 # Time in different power states system.physmem_0.memoryStateTime::REF 8580000 # Time in different power states system.physmem_0.memoryStateTime::SREF 0 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 16154500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 25250500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 207201500 # Time in different power states -system.physmem_1.actEnergy 671160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 349140 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3741360 # Energy for read commands per rank (pJ) +system.physmem_0.memoryStateTime::PRE_PDN 21825500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 19279750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 213298250 # Time in different power states +system.physmem_1.actEnergy 835380 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 425040 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4969440 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 14751360.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 9433500 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 3408960 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 53834790 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 13144800 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 18682440 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 118017510 # Total energy per rank (pJ) -system.physmem_1.averagePower 458.502938 # Core power per rank (mW) -system.physmem_1.totalIdleTime 227632750 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 8194250 # Time in different power states -system.physmem_1.memoryStateTime::REF 6246000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 75541750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 34227000 # Time in different power states -system.physmem_1.memoryStateTime::ACT 15120250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 118067250 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 257396500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 58095 # Number of BP lookups -system.cpu.branchPred.condPredicted 37339 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 4808 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 47628 # Number of BTB lookups -system.cpu.branchPred.BTBHits 25748 # Number of BTB hits +system.physmem_1.refreshEnergy 18439200.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 12155250 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 808800 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 57816810 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 20483040 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 15240660 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 131173620 # Total energy per rank (pJ) +system.physmem_1.averagePower 498.391850 # Core power per rank (mW) +system.physmem_1.totalIdleTime 234118000 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 1293500 # Time in different power states +system.physmem_1.memoryStateTime::REF 7824000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 54299500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 53341250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 19631750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 126803500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 263193500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 61022 # Number of BP lookups +system.cpu.branchPred.condPredicted 38603 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 4965 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 50209 # Number of BTB lookups +system.cpu.branchPred.BTBHits 26446 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 54.060637 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 52.671832 # BTB Hit Percentage system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 9498 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 5462 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 4036 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 2282 # Number of mispredicted indirect branches. +system.cpu.branchPred.indirectLookups 10264 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 6060 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 4204 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 2249 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses @@ -294,468 +294,472 @@ system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 130 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 257396500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 514793 # number of cpu cycles simulated +system.cpu.workload.num_syscalls 124 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 263193500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 526387 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 201609 # Number of instructions committed -system.cpu.committedOps 201609 # Number of ops (including micro ops) committed -system.cpu.discardedOps 12686 # Number of ops (including micro ops) which were discarded before commit +system.cpu.committedInsts 216793 # Number of instructions committed +system.cpu.committedOps 216793 # Number of ops (including micro ops) committed +system.cpu.discardedOps 12030 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 2.553423 # CPI: cycles per instruction -system.cpu.ipc 0.391631 # IPC: instructions per cycle -system.cpu.op_class_0::No_OpClass 132 0.07% 0.07% # Class of committed instruction -system.cpu.op_class_0::IntAlu 120936 59.99% 60.05% # Class of committed instruction -system.cpu.op_class_0::IntMult 297 0.15% 60.20% # Class of committed instruction -system.cpu.op_class_0::IntDiv 166 0.08% 60.28% # Class of committed instruction -system.cpu.op_class_0::FloatAdd 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::FloatCmp 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::FloatCvt 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::FloatMult 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::FloatMultAcc 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::FloatDiv 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::FloatMisc 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::FloatSqrt 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::SimdAdd 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::SimdAddAcc 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::SimdAlu 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::SimdCmp 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::SimdCvt 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::SimdMisc 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::SimdMult 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::SimdMultAcc 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::SimdShift 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::SimdShiftAcc 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::SimdSqrt 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAdd 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAlu 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCmp 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCvt 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::SimdFloatDiv 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMisc 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMult 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 60.28% # Class of committed instruction -system.cpu.op_class_0::MemRead 46389 23.01% 83.29% # Class of committed instruction -system.cpu.op_class_0::MemWrite 33689 16.71% 100.00% # Class of committed instruction +system.cpu.cpi 2.428063 # CPI: cycles per instruction +system.cpu.ipc 0.411851 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 129 0.06% 0.06% # Class of committed instruction +system.cpu.op_class_0::IntAlu 130215 60.06% 60.12% # Class of committed instruction +system.cpu.op_class_0::IntMult 341 0.16% 60.28% # Class of committed instruction +system.cpu.op_class_0::IntDiv 44 0.02% 60.30% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 0 0.00% 60.30% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 0 0.00% 60.30% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 0 0.00% 60.30% # Class of committed instruction +system.cpu.op_class_0::FloatMult 0 0.00% 60.30% # Class of committed instruction +system.cpu.op_class_0::FloatMultAcc 0 0.00% 60.30% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 0 0.00% 60.30% # Class of committed instruction +system.cpu.op_class_0::FloatMisc 0 0.00% 60.30% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 60.30% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 60.30% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 60.30% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 60.30% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 60.30% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 60.30% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 60.30% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 60.30% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 60.30% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 60.30% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 60.30% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 60.30% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 60.30% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 60.30% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 60.30% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 0 0.00% 60.30% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 60.30% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 0 0.00% 60.30% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 60.30% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 60.30% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 60.30% # Class of committed instruction +system.cpu.op_class_0::MemRead 49259 22.72% 83.02% # Class of committed instruction +system.cpu.op_class_0::MemWrite 36805 16.98% 100.00% # Class of committed instruction system.cpu.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 201609 # Class of committed instruction -system.cpu.tickCycles 299839 # Number of cycles that the object actually ticked -system.cpu.idleCycles 214954 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 257396500 # Cumulative time (in ticks) in various power states +system.cpu.op_class_0::total 216793 # Class of committed instruction +system.cpu.tickCycles 315380 # Number of cycles that the object actually ticked +system.cpu.idleCycles 211007 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 263193500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 237.251323 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 81600 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 296 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 275.675676 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 234.975357 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 87921 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 284 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 309.580986 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 237.251323 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.057923 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.057923 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 296 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 264 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.072266 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 164496 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 164496 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 257396500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 48321 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 48321 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 33279 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 33279 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 81600 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 81600 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 81600 # number of overall hits -system.cpu.dcache.overall_hits::total 81600 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 91 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 91 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 500 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 500 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 500 # number of overall misses -system.cpu.dcache.overall_misses::total 500 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8843000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8843000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 32769500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 32769500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 41612500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 41612500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 41612500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 41612500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 48412 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 48412 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 33688 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 33688 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 82100 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 82100 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 82100 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 82100 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001880 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.001880 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012141 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.012141 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.006090 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.006090 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.006090 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.006090 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 97175.824176 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 97175.824176 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80121.026895 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 80121.026895 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 83225 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 83225 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 83225 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 83225 # average overall miss latency +system.cpu.dcache.tags.occ_blocks::cpu.data 234.975357 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.057367 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.057367 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 284 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 261 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.069336 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 177074 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 177074 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 263193500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 51503 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 51503 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 36418 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 36418 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 87921 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 87921 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 87921 # number of overall hits +system.cpu.dcache.overall_hits::total 87921 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 88 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 88 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 386 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 386 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 474 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses +system.cpu.dcache.overall_misses::total 474 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8764000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8764000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 30933000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 30933000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 39697000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 39697000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 39697000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 39697000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 51591 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 51591 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 36804 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 36804 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 88395 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 88395 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 88395 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 88395 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001706 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.001706 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010488 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.010488 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.005362 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.005362 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.005362 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.005362 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 99590.909091 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 99590.909091 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80137.305699 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 80137.305699 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 83748.945148 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 83748.945148 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 83748.945148 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 83748.945148 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 198 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 198 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 204 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 204 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 204 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 204 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 85 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 85 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 211 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 211 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 296 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 296 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 296 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8161000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 8161000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 16932000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 16932000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25093000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 25093000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25093000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 25093000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001756 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001756 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006263 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006263 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003605 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003605 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003605 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003605 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 96011.764706 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 96011.764706 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80246.445498 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80246.445498 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84773.648649 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 84773.648649 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84773.648649 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 84773.648649 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 257396500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 44 # number of replacements -system.cpu.icache.tags.tagsinuse 581.971054 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 86953 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1105 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 78.690498 # Average number of references to valid blocks. +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 188 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 188 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 190 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 190 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 190 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 190 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 86 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 86 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 198 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 198 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 284 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 284 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 284 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 284 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8646000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 8646000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 15811000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 15811000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24457000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 24457000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24457000 # 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average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79853.535354 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79853.535354 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 86116.197183 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 86116.197183 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 86116.197183 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 86116.197183 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 263193500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 110 # number of replacements +system.cpu.icache.tags.tagsinuse 571.960381 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 92699 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1107 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 83.738934 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 581.971054 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.284166 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.284166 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1061 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 746 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.518066 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 177221 # Number of tag accesses -system.cpu.icache.tags.data_accesses 177221 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 257396500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 86953 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 86953 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 86953 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 86953 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 86953 # number of overall hits -system.cpu.icache.overall_hits::total 86953 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1105 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1105 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1105 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1105 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1105 # number of overall misses -system.cpu.icache.overall_misses::total 1105 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 95598500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 95598500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 95598500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 95598500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 95598500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 95598500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 88058 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 88058 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 88058 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 88058 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 88058 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 88058 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.012549 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.012549 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.012549 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.012549 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.012549 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.012549 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 86514.479638 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 86514.479638 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 86514.479638 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 86514.479638 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 86514.479638 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 86514.479638 # average overall miss latency +system.cpu.icache.tags.occ_blocks::cpu.inst 571.960381 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.279278 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.279278 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 997 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 221 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 730 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.486816 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 188719 # Number of tag accesses +system.cpu.icache.tags.data_accesses 188719 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 263193500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 92699 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 92699 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 92699 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 92699 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 92699 # number of overall hits +system.cpu.icache.overall_hits::total 92699 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1107 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1107 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1107 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1107 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1107 # number of overall misses +system.cpu.icache.overall_misses::total 1107 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 92360500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 92360500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 92360500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 92360500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 92360500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 92360500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 93806 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 93806 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 93806 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 93806 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 93806 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 93806 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011801 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.011801 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.011801 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.011801 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.011801 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.011801 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 83433.152665 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 83433.152665 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 83433.152665 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 83433.152665 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 83433.152665 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 83433.152665 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 44 # number of writebacks -system.cpu.icache.writebacks::total 44 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1105 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1105 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1105 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1105 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1105 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1105 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 94493500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 94493500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 94493500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 94493500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 94493500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 94493500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.012549 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.012549 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.012549 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.012549 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.012549 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.012549 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 85514.479638 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 85514.479638 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 85514.479638 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 85514.479638 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 85514.479638 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 85514.479638 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 257396500 # Cumulative time (in ticks) in various power states +system.cpu.icache.writebacks::writebacks 110 # number of writebacks +system.cpu.icache.writebacks::total 110 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1107 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1107 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1107 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1107 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1107 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1107 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 91253500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 91253500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 91253500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 91253500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 91253500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 91253500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.011801 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.011801 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.011801 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.011801 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.011801 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.011801 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 82433.152665 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 82433.152665 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 82433.152665 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 82433.152665 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 82433.152665 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 82433.152665 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 263193500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 828.582477 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 45 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1400 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.032143 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 831.949575 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 143 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1358 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.105302 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 591.965303 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 236.617175 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.018065 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.007221 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.025286 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 1400 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 282 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1053 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.042725 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 12960 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 12960 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 257396500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackClean_hits::writebacks 44 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 44 # number of WritebackClean hits +system.cpu.l2cache.tags.occ_blocks::cpu.inst 597.603246 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 234.346329 # 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mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.988372 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.971093 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.996479 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.976276 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.971093 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.996479 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.976276 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68353.535354 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68353.535354 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73029.767442 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73029.767442 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 90041.176471 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 90041.176471 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73029.767442 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74867.491166 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73412.739323 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73029.767442 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74867.491166 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73412.739323 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1501 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 111 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 257396500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 1190 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 44 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 211 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 211 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1105 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 85 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2254 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 592 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2846 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 73536 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18944 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 92480 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 263193500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 1193 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 110 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 198 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 198 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1107 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 86 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2324 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 568 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2892 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77888 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18176 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 96064 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1401 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000714 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.026717 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 1391 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000719 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.026812 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1400 99.93% 99.93% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1390 99.93% 99.93% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 1 0.07% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1401 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 766500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1391 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 860500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1657500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1660500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 444000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 426000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 1400 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_requests 1358 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 257396500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1189 # Transaction distribution -system.membus.trans_dist::ReadExReq 211 # Transaction distribution -system.membus.trans_dist::ReadExResp 211 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1189 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2800 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 2800 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 89600 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 89600 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 263193500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1160 # Transaction distribution +system.membus.trans_dist::ReadExReq 198 # Transaction distribution +system.membus.trans_dist::ReadExResp 198 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1160 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2716 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2716 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 86912 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 86912 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 1400 # Request fanout histogram +system.membus.snoop_fanout::samples 1358 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1400 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1358 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 1400 # Request fanout histogram -system.membus.reqLayer0.occupancy 1611500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 1358 # Request fanout histogram +system.membus.reqLayer0.occupancy 1554000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 7433000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 2.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 7203500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 2.7 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff -r fcea8c1b00f7 -r aaf914ea5a83 tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/config.ini --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/config.ini Wed Jan 18 16:27:49 2017 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/config.ini Wed Jan 18 16:41:56 2017 +0000 @@ -127,7 +127,7 @@ errout=cerr euid=100 eventq_index=0 -executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64i/insttest +executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64i/insttest gid=100 input=cin kvmInSE=false diff -r fcea8c1b00f7 -r aaf914ea5a83 tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/config.json --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/config.json Wed Jan 18 16:27:49 2017 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/config.json Wed Jan 18 16:41:56 2017 +0000 @@ -217,7 +217,7 @@ "pid": 100, "kvmInSE": false, "cxx_class": "LiveProcess", - "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64i/insttest", + "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64i/insttest", "drivers": [], "system": "system", "gid": 100, diff -r fcea8c1b00f7 -r aaf914ea5a83 tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/simout --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/simout Wed Jan 18 16:27:49 2017 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/simout Wed Jan 18 16:41:56 2017 +0000 @@ -3,17 +3,17 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 30 2016 14:33:35 -gem5 started Nov 30 2016 16:18:43 -gem5 executing on zizzer, pid 34088 -command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-atomic -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64i/simple-atomic +gem5 compiled Jan 12 2017 21:09:16 +gem5 started Jan 12 2017 21:09:32 +gem5 executing on ubuntu1604, pid 14232 +command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-atomic -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64i/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. lui: PASS lui, negative: PASS -auipc: 0x157E0 +auipc: 0x14FB0 auipc: PASS jal: PASS jalr: PASS @@ -86,53 +86,11 @@ or (A): PASS and (0): PASS and (-1): PASS -Bytes written: 15 -open, write: PASS -access F_OK: PASS -access R_OK: PASS -access W_OK: PASS -access X_OK: PASS -stat: - st_dev = 2054 - st_ino = 55451710 - st_mode = 33188 - st_nlink = 1 - st_uid = 1004 - st_gid = 1007 - st_rdev = 0 - st_size = 0 - st_blksize = 0 - st_blocks = 1480540729 -fstat: - st_dev = 2054 - st_ino = 55451710 - st_mode = 33188 - st_nlink = 1 - st_uid = 1004 - st_gid = 1007 - st_rdev = 0 - st_size = 0 - st_blksize = 0 - st_blocks = 1480540730 -open, stat: PASS -Bytes read: 15 -String read: this is a test -open, read, unlink: PASS -times: - tms_utime = 0 - tms_stime = 0 - tms_cutime = 0 - tms_cstime = 0 -times: PASS -timeval: - tv_sec = 1000000000 - tv_usec = 102 -gettimeofday: PASS -Cycles: 210287 +Cycles: 160717 rdcycle: PASS -Time: 1480540732 +Time: 1484255377 rdtime: PASS -Instructions Retired: 215205 +Instructions Retired: 165715 rdinstret: PASS lwu: PASS ld: PASS @@ -168,4 +126,4 @@ sraw, erase: PASS sraw, negative: PASS sraw, truncate: PASS -Exiting @ tick 133105500 because target called exit() +Exiting @ tick 108396000 because target called exit() diff -r fcea8c1b00f7 -r aaf914ea5a83 tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/stats.txt --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/stats.txt Wed Jan 18 16:27:49 2017 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-atomic/stats.txt Wed Jan 18 16:41:56 2017 +0000 @@ -1,42 +1,42 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000133 # Number of seconds simulated -sim_ticks 133105500 # Number of ticks simulated -final_tick 133105500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000108 # Number of seconds simulated +sim_ticks 108396000 # Number of ticks simulated +final_tick 108396000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 24056 # Simulator instruction rate (inst/s) -host_op_rate 24056 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 12036090 # Simulator tick rate (ticks/s) -host_mem_usage 234212 # Number of bytes of host memory used -host_seconds 11.06 # Real time elapsed on the host -sim_insts 266028 # Number of instructions simulated -sim_ops 266028 # Number of ops (including micro ops) simulated +host_inst_rate 29056 # Simulator instruction rate (inst/s) +host_op_rate 29056 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 14536475 # Simulator tick rate (ticks/s) +host_mem_usage 254512 # Number of bytes of host memory used +host_seconds 7.46 # Real time elapsed on the host +sim_insts 216668 # Number of instructions simulated +sim_ops 216668 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 133105500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 1064848 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 412103 # Number of bytes read from this memory -system.physmem.bytes_read::total 1476951 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1064848 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1064848 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 270848 # Number of bytes written to this memory -system.physmem.bytes_written::total 270848 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 266212 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 62869 # Number of read requests responded to by this memory -system.physmem.num_reads::total 329081 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 43712 # Number of write requests responded to by this memory -system.physmem.num_writes::total 43712 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 8000030051 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3096062897 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 11096092949 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8000030051 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8000030051 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 2034837028 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2034837028 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8000030051 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5130899925 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 13130929977 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 133105500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 108396000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 867172 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 320975 # Number of bytes read from this memory +system.physmem.bytes_read::total 1188147 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 867172 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 867172 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 225529 # Number of bytes written to this memory +system.physmem.bytes_written::total 225529 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 216793 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 49259 # Number of read requests responded to by this memory +system.physmem.num_reads::total 266052 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 36804 # Number of write requests responded to by this memory +system.physmem.num_writes::total 36804 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 8000036902 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2961133252 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10961170154 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8000036902 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8000036902 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 2080602605 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2080602605 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8000036902 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5041735857 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 13041772759 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 108396000 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses @@ -56,98 +56,98 @@ system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 183 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 133105500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 266212 # number of cpu cycles simulated +system.cpu.workload.num_syscalls 124 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 108396000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 216793 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 266028 # Number of instructions committed -system.cpu.committedOps 266028 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 266027 # Number of integer alu accesses +system.cpu.committedInsts 216668 # Number of instructions committed +system.cpu.committedOps 216668 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 216667 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 19074 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 39822 # number of instructions that are conditional controls -system.cpu.num_int_insts 266027 # number of integer instructions +system.cpu.num_func_calls 15750 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 32857 # number of instructions that are conditional controls +system.cpu.num_int_insts 216667 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 351579 # number of times the integer registers were read -system.cpu.num_int_register_writes 182492 # number of times the integer registers were written +system.cpu.num_int_register_reads 287238 # number of times the integer registers were read +system.cpu.num_int_register_writes 147005 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 106582 # number of memory refs -system.cpu.num_load_insts 62869 # Number of load instructions -system.cpu.num_store_insts 43713 # Number of store instructions +system.cpu.num_mem_refs 86064 # number of memory refs +system.cpu.num_load_insts 49259 # Number of load instructions +system.cpu.num_store_insts 36805 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 266212 # Number of busy cycles +system.cpu.num_busy_cycles 216793 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 58896 # Number of branches fetched -system.cpu.op_class::No_OpClass 188 0.07% 0.07% # Class of executed instruction -system.cpu.op_class::IntAlu 158769 59.64% 59.71% # Class of executed instruction -system.cpu.op_class::IntMult 431 0.16% 59.87% # Class of executed instruction -system.cpu.op_class::IntDiv 242 0.09% 59.96% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 59.96% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 59.96% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 59.96% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 59.96% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 59.96% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 59.96% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 59.96% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 59.96% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 59.96% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 59.96% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 59.96% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 59.96% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 59.96% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 59.96% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 59.96% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 59.96% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 59.96% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 59.96% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 59.96% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 59.96% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 59.96% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 59.96% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 59.96% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 59.96% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 59.96% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 59.96% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 59.96% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 59.96% # Class of executed instruction -system.cpu.op_class::MemRead 62869 23.62% 83.58% # Class of executed instruction -system.cpu.op_class::MemWrite 43713 16.42% 100.00% # Class of executed instruction +system.cpu.Branches 48607 # Number of branches fetched +system.cpu.op_class::No_OpClass 129 0.06% 0.06% # Class of executed instruction +system.cpu.op_class::IntAlu 130215 60.06% 60.12% # Class of executed instruction +system.cpu.op_class::IntMult 341 0.16% 60.28% # Class of executed instruction +system.cpu.op_class::IntDiv 44 0.02% 60.30% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::MemRead 49259 22.72% 83.02% # Class of executed instruction +system.cpu.op_class::MemWrite 36805 16.98% 100.00% # Class of executed instruction system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 266212 # Class of executed instruction +system.cpu.op_class::total 216793 # Class of executed instruction system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 133105500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 329081 # Transaction distribution -system.membus.trans_dist::ReadResp 329081 # Transaction distribution -system.membus.trans_dist::WriteReq 43712 # Transaction distribution -system.membus.trans_dist::WriteResp 43712 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 532424 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 213162 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 745586 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1064848 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 682951 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1747799 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 108396000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 266052 # Transaction distribution +system.membus.trans_dist::ReadResp 266052 # Transaction distribution +system.membus.trans_dist::WriteReq 36804 # Transaction distribution +system.membus.trans_dist::WriteResp 36804 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 433586 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 172126 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 605712 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 867172 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 546504 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1413676 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 372793 # Request fanout histogram +system.membus.snoop_fanout::samples 302856 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 372793 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 302856 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 372793 # Request fanout histogram +system.membus.snoop_fanout::total 302856 # Request fanout histogram ---------- End Simulation Statistics ---------- diff -r fcea8c1b00f7 -r aaf914ea5a83 tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/config.ini --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/config.ini Wed Jan 18 16:27:49 2017 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/config.ini Wed Jan 18 16:41:56 2017 +0000 @@ -131,7 +131,7 @@ errout=cerr euid=100 eventq_index=0 -executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64i/insttest +executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64i/insttest gid=100 input=cin kvmInSE=false diff -r fcea8c1b00f7 -r aaf914ea5a83 tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/config.json --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/config.json Wed Jan 18 16:27:49 2017 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/config.json Wed Jan 18 16:41:56 2017 +0000 @@ -1573,7 +1573,7 @@ "pid": 100, "kvmInSE": false, "cxx_class": "LiveProcess", - "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64i/insttest", + "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64i/insttest", "drivers": [], "system": "system", "gid": 100, diff -r fcea8c1b00f7 -r aaf914ea5a83 tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/simout --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/simout Wed Jan 18 16:27:49 2017 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/simout Wed Jan 18 16:41:56 2017 +0000 @@ -3,17 +3,17 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 30 2016 14:33:35 -gem5 started Nov 30 2016 16:18:44 -gem5 executing on zizzer, pid 34093 -command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-timing-ruby -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64i/simple-timing-ruby +gem5 compiled Jan 12 2017 21:09:16 +gem5 started Jan 12 2017 21:09:32 +gem5 executing on ubuntu1604, pid 14229 +command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-timing-ruby -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64i/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. lui: PASS lui, negative: PASS -auipc: 0x157E0 +auipc: 0x14FB0 auipc: PASS jal: PASS jalr: PASS @@ -86,53 +86,11 @@ or (A): PASS and (0): PASS and (-1): PASS -Bytes written: 15 -open, write: PASS -access F_OK: PASS -access R_OK: PASS -access W_OK: PASS -access X_OK: PASS -stat: - st_dev = 2054 - st_ino = 55451710 - st_mode = 33188 - st_nlink = 1 - st_uid = 1004 - st_gid = 1007 - st_rdev = 0 - st_size = 0 - st_blksize = 0 - st_blocks = 1480540733 -fstat: - st_dev = 2054 - st_ino = 55451710 - st_mode = 33188 - st_nlink = 1 - st_uid = 1004 - st_gid = 1007 - st_rdev = 0 - st_size = 0 - st_blksize = 0 - st_blocks = 1480540733 -open, stat: PASS -Bytes read: 15 -String read: this is a test -open, read, unlink: PASS -times: - tms_utime = 0 - tms_stime = 0 - tms_cutime = 0 - tms_cstime = 0 -times: PASS -timeval: - tv_sec = 1000000000 - tv_usec = 3935 -gettimeofday: PASS -Cycles: 4032706 +Cycles: 2856846 rdcycle: PASS -Time: 1480540736 +Time: 1484255380 rdtime: PASS -Instructions Retired: 215243 +Instructions Retired: 165734 rdinstret: PASS lwu: PASS ld: PASS @@ -168,4 +126,4 @@ sraw, erase: PASS sraw, negative: PASS sraw, truncate: PASS -Exiting @ tick 5246466 because target called exit() +Exiting @ tick 4031253 because target called exit() diff -r fcea8c1b00f7 -r aaf914ea5a83 tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/stats.txt --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/stats.txt Wed Jan 18 16:27:49 2017 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing-ruby/stats.txt Wed Jan 18 16:41:56 2017 +0000 @@ -1,95 +1,95 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.005246 # Number of seconds simulated -sim_ticks 5246466 # Number of ticks simulated -final_tick 5246466 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.004031 # Number of seconds simulated +sim_ticks 4031253 # Number of ticks simulated +final_tick 4031253 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 18477 # Simulator instruction rate (inst/s) -host_op_rate 18477 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 364337 # Simulator tick rate (ticks/s) -host_mem_usage 412052 # Number of bytes of host memory used -host_seconds 14.40 # Real time elapsed on the host -sim_insts 266066 # Number of instructions simulated -sim_ops 266066 # Number of ops (including micro ops) simulated +host_inst_rate 21681 # Simulator instruction rate (inst/s) +host_op_rate 21681 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 403348 # Simulator tick rate (ticks/s) +host_mem_usage 432180 # Number of bytes of host memory used +host_seconds 9.99 # Real time elapsed on the host +sim_insts 216687 # Number of instructions simulated +sim_ops 216687 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 5246466 # Cumulative time (in ticks) in various power states -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 5073344 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 5073344 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 5073088 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 5073088 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 79271 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 79271 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 79267 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 79267 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 967002169 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 967002169 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 966953374 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 966953374 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 1933955543 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 1933955543 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 79271 # Number of read requests accepted -system.mem_ctrls.writeReqs 79267 # Number of write requests accepted -system.mem_ctrls.readBursts 79271 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 79267 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 2666176 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 2407168 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 2784128 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 5073344 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 5073088 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 37612 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 35741 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 4031253 # Cumulative time (in ticks) in various power states +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 3957952 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 3957952 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 3957696 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 3957696 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 61843 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 61843 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 61839 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 61839 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 981816820 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 981816820 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 981753316 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 981753316 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 1963570136 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1963570136 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 61843 # Number of read requests accepted +system.mem_ctrls.writeReqs 61839 # Number of write requests accepted +system.mem_ctrls.readBursts 61843 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 61839 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 2072960 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 1884992 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 2148416 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 3957952 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 3957696 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 29453 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 28241 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 4161 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 6493 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 322 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 11183 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 1470 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 254 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 44 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 830 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 271 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::9 850 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 2251 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 11315 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 562 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 405 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 342 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 906 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 4421 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 6791 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 332 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 11984 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 1476 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 255 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 44 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 877 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::8 282 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 852 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 2350 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 11612 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 563 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 405 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 350 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::15 908 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::0 2628 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 4312 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 1039 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 156 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 9 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 531 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 1395 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 56 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 7742 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 2997 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 1569 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 4675 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 58 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 927 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 2454 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 1842 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 2735 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 4744 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 1046 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 156 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 9 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 548 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 1452 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 54 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 7871 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 3024 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 1594 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 4811 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 59 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 938 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 2645 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 1883 # Per bank write bursts system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 5246394 # Total gap between requests +system.mem_ctrls.totGap 4031167 # Total gap between requests system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 79271 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 61843 # Read request sizes (log2) system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 79267 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 41659 # What read queue length does an incoming req see +system.mem_ctrls.writePktSize::6 61839 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 32390 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -136,24 +136,24 @@ system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 330 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 402 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 2224 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 2668 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 2708 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 2791 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 2963 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 2810 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 2680 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 2663 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 2661 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 2661 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 2658 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 2660 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 2658 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 2658 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 2658 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 2658 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 249 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 274 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 1803 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 2096 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 2089 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 2173 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 2236 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 2088 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 2062 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 2058 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 2058 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 2058 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 2058 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 2057 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 2056 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 2056 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 2056 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 2056 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -185,102 +185,102 @@ system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 15795 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 344.923330 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 229.090130 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 305.803840 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 3621 22.92% 22.92% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 4154 26.30% 49.22% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 2325 14.72% 63.94% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 1784 11.29% 75.24% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 865 5.48% 80.72% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 706 4.47% 85.19% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 510 3.23% 88.41% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 328 2.08% 90.49% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 1502 9.51% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 15795 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 2658 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 15.670429 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 15.605623 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 1.463558 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::12-13 110 4.14% 4.14% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::14-15 1181 44.43% 48.57% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-17 1114 41.91% 90.48% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::18-19 223 8.39% 98.87% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::20-21 29 1.09% 99.96% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::36-37 1 0.04% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 2658 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 2658 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.366441 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.340186 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 0.970216 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 2300 86.53% 86.53% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 19 0.71% 87.25% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 111 4.18% 91.42% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 179 6.73% 98.16% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::20 49 1.84% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 2658 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 835288 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 1626809 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 208295 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 20.05 # Average queueing delay per DRAM burst +system.mem_ctrls.bytesPerActivate::samples 8692 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 485.492867 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 347.631780 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 343.996268 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 985 11.33% 11.33% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 1706 19.63% 30.96% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 1202 13.83% 44.79% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 1200 13.81% 58.59% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 645 7.42% 66.01% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 527 6.06% 72.08% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 446 5.13% 77.21% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 296 3.41% 80.61% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 1685 19.39% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 8692 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 2056 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 15.748541 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 15.684185 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 1.461425 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::12-13 92 4.47% 4.47% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::14-15 832 40.47% 44.94% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-17 936 45.53% 90.47% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::18-19 174 8.46% 98.93% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::20-21 21 1.02% 99.95% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::36-37 1 0.05% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 2056 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 2056 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.327335 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.305821 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 0.873704 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 1786 86.87% 86.87% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 13 0.63% 87.50% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 120 5.84% 93.34% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 128 6.23% 99.56% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::20 9 0.44% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 2056 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 569066 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 1184476 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 161950 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 17.57 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 39.05 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 508.19 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 530.67 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 967.00 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 966.95 # Average system write bandwidth in MiByte/s +system.mem_ctrls.avgMemAccLat 36.57 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 514.22 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 532.94 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 981.82 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 981.75 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 8.12 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 3.97 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 4.15 # Data bus utilization in percentage for writes +system.mem_ctrls.busUtil 8.18 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 4.02 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 4.16 # Data bus utilization in percentage for writes system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 26.01 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 29472 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 39888 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 70.75 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 91.64 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 33.09 # Average gap between requests -system.mem_ctrls.pageHitRate 81.42 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 79710960 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 43126104 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 282823968 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 218655360 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 414882000.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 659598072 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 10126848 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.actPowerDownEnergy 1616957760 # Energy for active power-down per rank (pJ) -system.mem_ctrls_0.prePowerDownEnergy 62452224 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_0.selfRefreshEnergy 21677280 # Energy for self refresh per rank (pJ) -system.mem_ctrls_0.totalEnergy 3410010576 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 649.963342 # Core power per rank (mW) -system.mem_ctrls_0.totalIdleTime 3773570 # Total Idle time Per DRAM Rank -system.mem_ctrls_0.memoryStateTime::IDLE 6170 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 175566 # Time in different power states -system.mem_ctrls_0.memoryStateTime::SREF 65011 # Time in different power states -system.mem_ctrls_0.memoryStateTime::PRE_PDN 162636 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 1291123 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 3545960 # Time in different power states -system.mem_ctrls_1.actEnergy 33108180 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 17905776 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 193088448 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 144673344 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 397057440.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 650520024 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 12185088 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.actPowerDownEnergy 1517506896 # Energy for active power-down per rank (pJ) -system.mem_ctrls_1.prePowerDownEnergy 81936768 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_1.selfRefreshEnergy 62020080 # Energy for self refresh per rank (pJ) -system.mem_ctrls_1.totalEnergy 3110002044 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 592.780368 # Core power per rank (mW) -system.mem_ctrls_1.totalIdleTime 3787958 # Total Idle time Per DRAM Rank -system.mem_ctrls_1.memoryStateTime::IDLE 12732 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 167990 # Time in different power states -system.mem_ctrls_1.memoryStateTime::SREF 246912 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 213377 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 1277589 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT_PDN 3327866 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 5246466 # Cumulative time (in ticks) in various power states +system.mem_ctrls.avgWrQLen 25.93 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 26068 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 31192 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 80.48 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 92.84 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 32.59 # Average gap between requests +system.mem_ctrls.pageHitRate 86.77 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 26218080 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 14180880 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 115679424 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 89733888 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 301173600.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 361565592 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 7264512 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.actPowerDownEnergy 1278711096 # Energy for active power-down per rank (pJ) +system.mem_ctrls_0.prePowerDownEnergy 58404864 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_0.selfRefreshEnergy 67019520 # Energy for self refresh per rank (pJ) +system.mem_ctrls_0.totalEnergy 2319951456 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 575.491406 # Core power per rank (mW) +system.mem_ctrls_0.totalIdleTime 3219391 # Total Idle time Per DRAM Rank +system.mem_ctrls_0.memoryStateTime::IDLE 5184 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 127442 # Time in different power states +system.mem_ctrls_0.memoryStateTime::SREF 263141 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 152096 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 679199 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 2804191 # Time in different power states +system.mem_ctrls_1.actEnergy 35892780 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 19405008 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 254343936 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 190634400 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 317768880.000000 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 500561232 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 7422720 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.actPowerDownEnergy 1234599936 # Energy for active power-down per rank (pJ) +system.mem_ctrls_1.prePowerDownEnergy 54910848 # Energy for precharge power-down per rank (pJ) +system.mem_ctrls_1.selfRefreshEnergy 20269680 # Energy for self refresh per rank (pJ) +system.mem_ctrls_1.totalEnergy 2635809420 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 653.843711 # Core power per rank (mW) +system.mem_ctrls_1.totalIdleTime 2913908 # Total Idle time Per DRAM Rank +system.mem_ctrls_1.memoryStateTime::IDLE 4850 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 134480 # Time in different power states +system.mem_ctrls_1.memoryStateTime::SREF 63748 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 142997 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 977722 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 2707456 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 4031253 # Cumulative time (in ticks) in various power states system.cpu.clk_domain.clock 1 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses @@ -300,272 +300,272 @@ system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 183 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 5246466 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 5246466 # number of cpu cycles simulated +system.cpu.workload.num_syscalls 124 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 4031253 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 4031253 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 266066 # Number of instructions committed -system.cpu.committedOps 266066 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 266065 # Number of integer alu accesses +system.cpu.committedInsts 216687 # Number of instructions committed +system.cpu.committedOps 216687 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 216686 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 19074 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 39832 # number of instructions that are conditional controls -system.cpu.num_int_insts 266065 # number of integer instructions +system.cpu.num_func_calls 15750 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 32862 # number of instructions that are conditional controls +system.cpu.num_int_insts 216686 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 351637 # number of times the integer registers were read -system.cpu.num_int_register_writes 182516 # number of times the integer registers were written +system.cpu.num_int_register_reads 287267 # number of times the integer registers were read +system.cpu.num_int_register_writes 147017 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 106592 # number of memory refs -system.cpu.num_load_insts 62875 # Number of load instructions -system.cpu.num_store_insts 43717 # Number of store instructions +system.cpu.num_mem_refs 86069 # number of memory refs +system.cpu.num_load_insts 49262 # Number of load instructions +system.cpu.num_store_insts 36807 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 5246466 # Number of busy cycles +system.cpu.num_busy_cycles 4031253 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 58906 # Number of branches fetched -system.cpu.op_class::No_OpClass 188 0.07% 0.07% # Class of executed instruction -system.cpu.op_class::IntAlu 158793 59.64% 59.71% # Class of executed instruction -system.cpu.op_class::IntMult 431 0.16% 59.87% # Class of executed instruction -system.cpu.op_class::IntDiv 246 0.09% 59.97% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 59.97% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 59.97% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 59.97% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 59.97% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 59.97% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 59.97% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 59.97% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 59.97% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 59.97% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 59.97% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 59.97% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 59.97% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 59.97% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 59.97% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 59.97% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 59.97% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 59.97% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 59.97% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 59.97% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 59.97% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 59.97% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 59.97% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 59.97% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 59.97% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 59.97% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 59.97% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 59.97% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 59.97% # Class of executed instruction -system.cpu.op_class::MemRead 62875 23.62% 83.58% # Class of executed instruction -system.cpu.op_class::MemWrite 43717 16.42% 100.00% # Class of executed instruction +system.cpu.Branches 48612 # Number of branches fetched +system.cpu.op_class::No_OpClass 129 0.06% 0.06% # Class of executed instruction +system.cpu.op_class::IntAlu 130227 60.06% 60.12% # Class of executed instruction +system.cpu.op_class::IntMult 341 0.16% 60.28% # Class of executed instruction +system.cpu.op_class::IntDiv 46 0.02% 60.30% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::MemRead 49262 22.72% 83.02% # Class of executed instruction +system.cpu.op_class::MemWrite 36807 16.98% 100.00% # Class of executed instruction system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 266250 # Class of executed instruction +system.cpu.op_class::total 216812 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.pwrStateResidencyTicks::UNDEFINED 5246466 # Cumulative time (in ticks) in various power states +system.ruby.pwrStateResidencyTicks::UNDEFINED 4031253 # Cumulative time (in ticks) in various power states system.ruby.delayHist::bucket_size 1 # delay histogram for all message system.ruby.delayHist::max_bucket 9 # delay histogram for all message -system.ruby.delayHist::samples 158538 # delay histogram for all message -system.ruby.delayHist | 158538 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 158538 # delay histogram for all message +system.ruby.delayHist::samples 123682 # delay histogram for all message +system.ruby.delayHist | 123682 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 123682 # delay histogram for all message system.ruby.outstanding_req_hist_seqr::bucket_size 1 system.ruby.outstanding_req_hist_seqr::max_bucket 9 -system.ruby.outstanding_req_hist_seqr::samples 372842 +system.ruby.outstanding_req_hist_seqr::samples 302881 system.ruby.outstanding_req_hist_seqr::mean 1 system.ruby.outstanding_req_hist_seqr::gmean 1 -system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 372842 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist_seqr::total 372842 +system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 302881 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 302881 system.ruby.latency_hist_seqr::bucket_size 64 system.ruby.latency_hist_seqr::max_bucket 639 -system.ruby.latency_hist_seqr::samples 372841 -system.ruby.latency_hist_seqr::mean 13.071591 -system.ruby.latency_hist_seqr::gmean 2.303358 -system.ruby.latency_hist_seqr::stdev 28.899910 -system.ruby.latency_hist_seqr | 332521 89.19% 89.19% | 37494 10.06% 99.24% | 1855 0.50% 99.74% | 376 0.10% 99.84% | 322 0.09% 99.93% | 238 0.06% 99.99% | 17 0.00% 100.00% | 3 0.00% 100.00% | 2 0.00% 100.00% | 13 0.00% 100.00% -system.ruby.latency_hist_seqr::total 372841 +system.ruby.latency_hist_seqr::samples 302880 +system.ruby.latency_hist_seqr::mean 12.309737 +system.ruby.latency_hist_seqr::gmean 2.220633 +system.ruby.latency_hist_seqr::stdev 27.681569 +system.ruby.latency_hist_seqr | 271639 89.69% 89.69% | 29065 9.60% 99.28% | 1531 0.51% 99.79% | 180 0.06% 99.85% | 244 0.08% 99.93% | 198 0.07% 99.99% | 7 0.00% 99.99% | 2 0.00% 100.00% | 1 0.00% 100.00% | 13 0.00% 100.00% +system.ruby.latency_hist_seqr::total 302880 system.ruby.hit_latency_hist_seqr::bucket_size 1 system.ruby.hit_latency_hist_seqr::max_bucket 9 -system.ruby.hit_latency_hist_seqr::samples 293570 +system.ruby.hit_latency_hist_seqr::samples 241037 system.ruby.hit_latency_hist_seqr::mean 1 system.ruby.hit_latency_hist_seqr::gmean 1 -system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 293570 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist_seqr::total 293570 +system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 241037 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist_seqr::total 241037 system.ruby.miss_latency_hist_seqr::bucket_size 64 system.ruby.miss_latency_hist_seqr::max_bucket 639 -system.ruby.miss_latency_hist_seqr::samples 79271 -system.ruby.miss_latency_hist_seqr::mean 57.777182 -system.ruby.miss_latency_hist_seqr::gmean 50.619805 -system.ruby.miss_latency_hist_seqr::stdev 37.283085 -system.ruby.miss_latency_hist_seqr | 38951 49.14% 49.14% | 37494 47.30% 96.44% | 1855 2.34% 98.78% | 376 0.47% 99.25% | 322 0.41% 99.66% | 238 0.30% 99.96% | 17 0.02% 99.98% | 3 0.00% 99.98% | 2 0.00% 99.98% | 13 0.02% 100.00% -system.ruby.miss_latency_hist_seqr::total 79271 -system.ruby.Directory.incomplete_times_seqr 79270 -system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 5246466 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.cacheMemory.demand_hits 293570 # Number of cache demand hits -system.ruby.l1_cntrl0.cacheMemory.demand_misses 79271 # Number of cache demand misses -system.ruby.l1_cntrl0.cacheMemory.demand_accesses 372841 # Number of cache demand accesses -system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 5246466 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 5246466 # Cumulative time (in ticks) in various power states +system.ruby.miss_latency_hist_seqr::samples 61843 +system.ruby.miss_latency_hist_seqr::mean 56.390149 +system.ruby.miss_latency_hist_seqr::gmean 49.761350 +system.ruby.miss_latency_hist_seqr::stdev 36.211053 +system.ruby.miss_latency_hist_seqr | 30602 49.48% 49.48% | 29065 47.00% 96.48% | 1531 2.48% 98.96% | 180 0.29% 99.25% | 244 0.39% 99.64% | 198 0.32% 99.96% | 7 0.01% 99.97% | 2 0.00% 99.98% | 1 0.00% 99.98% | 13 0.02% 100.00% +system.ruby.miss_latency_hist_seqr::total 61843 +system.ruby.Directory.incomplete_times_seqr 61842 +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 4031253 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.cacheMemory.demand_hits 241037 # Number of cache demand hits +system.ruby.l1_cntrl0.cacheMemory.demand_misses 61843 # Number of cache demand misses +system.ruby.l1_cntrl0.cacheMemory.demand_accesses 302880 # Number of cache demand accesses +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 4031253 # Cumulative time (in ticks) in various power states +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 4031253 # Cumulative time (in ticks) in various power states system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 5246466 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.percent_links_utilized 7.554514 -system.ruby.network.routers0.msg_count.Control::2 79271 -system.ruby.network.routers0.msg_count.Data::2 79267 -system.ruby.network.routers0.msg_count.Response_Data::4 79271 -system.ruby.network.routers0.msg_count.Writeback_Control::3 79267 -system.ruby.network.routers0.msg_bytes.Control::2 634168 -system.ruby.network.routers0.msg_bytes.Data::2 5707224 -system.ruby.network.routers0.msg_bytes.Response_Data::4 5707512 -system.ruby.network.routers0.msg_bytes.Writeback_Control::3 634136 -system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 5246466 # Cumulative time (in ticks) in various power states -system.ruby.network.routers1.percent_links_utilized 7.554514 -system.ruby.network.routers1.msg_count.Control::2 79271 -system.ruby.network.routers1.msg_count.Data::2 79267 -system.ruby.network.routers1.msg_count.Response_Data::4 79271 -system.ruby.network.routers1.msg_count.Writeback_Control::3 79267 -system.ruby.network.routers1.msg_bytes.Control::2 634168 -system.ruby.network.routers1.msg_bytes.Data::2 5707224 -system.ruby.network.routers1.msg_bytes.Response_Data::4 5707512 -system.ruby.network.routers1.msg_bytes.Writeback_Control::3 634136 -system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 5246466 # Cumulative time (in ticks) in various power states -system.ruby.network.routers2.percent_links_utilized 7.554514 -system.ruby.network.routers2.msg_count.Control::2 79271 -system.ruby.network.routers2.msg_count.Data::2 79267 -system.ruby.network.routers2.msg_count.Response_Data::4 79271 -system.ruby.network.routers2.msg_count.Writeback_Control::3 79267 -system.ruby.network.routers2.msg_bytes.Control::2 634168 -system.ruby.network.routers2.msg_bytes.Data::2 5707224 -system.ruby.network.routers2.msg_bytes.Response_Data::4 5707512 -system.ruby.network.routers2.msg_bytes.Writeback_Control::3 634136 -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 5246466 # Cumulative time (in ticks) in various power states -system.ruby.network.msg_count.Control 237813 -system.ruby.network.msg_count.Data 237801 -system.ruby.network.msg_count.Response_Data 237813 -system.ruby.network.msg_count.Writeback_Control 237801 -system.ruby.network.msg_byte.Control 1902504 -system.ruby.network.msg_byte.Data 17121672 -system.ruby.network.msg_byte.Response_Data 17122536 -system.ruby.network.msg_byte.Writeback_Control 1902408 -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 5246466 # Cumulative time (in ticks) in various power states -system.ruby.network.routers0.throttle0.link_utilization 7.554666 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 79271 -system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 79267 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 5707512 -system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 634136 -system.ruby.network.routers0.throttle1.link_utilization 7.554361 -system.ruby.network.routers0.throttle1.msg_count.Control::2 79271 -system.ruby.network.routers0.throttle1.msg_count.Data::2 79267 -system.ruby.network.routers0.throttle1.msg_bytes.Control::2 634168 -system.ruby.network.routers0.throttle1.msg_bytes.Data::2 5707224 -system.ruby.network.routers1.throttle0.link_utilization 7.554361 -system.ruby.network.routers1.throttle0.msg_count.Control::2 79271 -system.ruby.network.routers1.throttle0.msg_count.Data::2 79267 -system.ruby.network.routers1.throttle0.msg_bytes.Control::2 634168 -system.ruby.network.routers1.throttle0.msg_bytes.Data::2 5707224 -system.ruby.network.routers1.throttle1.link_utilization 7.554666 -system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 79271 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 79267 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 5707512 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 634136 -system.ruby.network.routers2.throttle0.link_utilization 7.554666 -system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 79271 -system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 79267 -system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 5707512 -system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 634136 -system.ruby.network.routers2.throttle1.link_utilization 7.554361 -system.ruby.network.routers2.throttle1.msg_count.Control::2 79271 -system.ruby.network.routers2.throttle1.msg_count.Data::2 79267 -system.ruby.network.routers2.throttle1.msg_bytes.Control::2 634168 -system.ruby.network.routers2.throttle1.msg_bytes.Data::2 5707224 +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 4031253 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.percent_links_utilized 7.670196 +system.ruby.network.routers0.msg_count.Control::2 61843 +system.ruby.network.routers0.msg_count.Data::2 61839 +system.ruby.network.routers0.msg_count.Response_Data::4 61843 +system.ruby.network.routers0.msg_count.Writeback_Control::3 61839 +system.ruby.network.routers0.msg_bytes.Control::2 494744 +system.ruby.network.routers0.msg_bytes.Data::2 4452408 +system.ruby.network.routers0.msg_bytes.Response_Data::4 4452696 +system.ruby.network.routers0.msg_bytes.Writeback_Control::3 494712 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 4031253 # Cumulative time (in ticks) in various power states +system.ruby.network.routers1.percent_links_utilized 7.670196 +system.ruby.network.routers1.msg_count.Control::2 61843 +system.ruby.network.routers1.msg_count.Data::2 61839 +system.ruby.network.routers1.msg_count.Response_Data::4 61843 +system.ruby.network.routers1.msg_count.Writeback_Control::3 61839 +system.ruby.network.routers1.msg_bytes.Control::2 494744 +system.ruby.network.routers1.msg_bytes.Data::2 4452408 +system.ruby.network.routers1.msg_bytes.Response_Data::4 4452696 +system.ruby.network.routers1.msg_bytes.Writeback_Control::3 494712 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 4031253 # Cumulative time (in ticks) in various power states +system.ruby.network.routers2.percent_links_utilized 7.670196 +system.ruby.network.routers2.msg_count.Control::2 61843 +system.ruby.network.routers2.msg_count.Data::2 61839 +system.ruby.network.routers2.msg_count.Response_Data::4 61843 +system.ruby.network.routers2.msg_count.Writeback_Control::3 61839 +system.ruby.network.routers2.msg_bytes.Control::2 494744 +system.ruby.network.routers2.msg_bytes.Data::2 4452408 +system.ruby.network.routers2.msg_bytes.Response_Data::4 4452696 +system.ruby.network.routers2.msg_bytes.Writeback_Control::3 494712 +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 4031253 # Cumulative time (in ticks) in various power states +system.ruby.network.msg_count.Control 185529 +system.ruby.network.msg_count.Data 185517 +system.ruby.network.msg_count.Response_Data 185529 +system.ruby.network.msg_count.Writeback_Control 185517 +system.ruby.network.msg_byte.Control 1484232 +system.ruby.network.msg_byte.Data 13357224 +system.ruby.network.msg_byte.Response_Data 13358088 +system.ruby.network.msg_byte.Writeback_Control 1484136 +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 4031253 # Cumulative time (in ticks) in various power states +system.ruby.network.routers0.throttle0.link_utilization 7.670394 +system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 61843 +system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 61839 +system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 4452696 +system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 494712 +system.ruby.network.routers0.throttle1.link_utilization 7.669997 +system.ruby.network.routers0.throttle1.msg_count.Control::2 61843 +system.ruby.network.routers0.throttle1.msg_count.Data::2 61839 +system.ruby.network.routers0.throttle1.msg_bytes.Control::2 494744 +system.ruby.network.routers0.throttle1.msg_bytes.Data::2 4452408 +system.ruby.network.routers1.throttle0.link_utilization 7.669997 +system.ruby.network.routers1.throttle0.msg_count.Control::2 61843 +system.ruby.network.routers1.throttle0.msg_count.Data::2 61839 +system.ruby.network.routers1.throttle0.msg_bytes.Control::2 494744 +system.ruby.network.routers1.throttle0.msg_bytes.Data::2 4452408 +system.ruby.network.routers1.throttle1.link_utilization 7.670394 +system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 61843 +system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 61839 +system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 4452696 +system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 494712 +system.ruby.network.routers2.throttle0.link_utilization 7.670394 +system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 61843 +system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 61839 +system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 4452696 +system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 494712 +system.ruby.network.routers2.throttle1.link_utilization 7.669997 +system.ruby.network.routers2.throttle1.msg_count.Control::2 61843 +system.ruby.network.routers2.throttle1.msg_count.Data::2 61839 +system.ruby.network.routers2.throttle1.msg_bytes.Control::2 494744 +system.ruby.network.routers2.throttle1.msg_bytes.Data::2 4452408 system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::samples 79271 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1 | 79271 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::total 79271 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::samples 61843 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1 | 61843 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::total 61843 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::samples 79267 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2 | 79267 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::total 79267 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::samples 61839 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2 | 61839 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::total 61839 # delay histogram for vnet_2 system.ruby.LD.latency_hist_seqr::bucket_size 64 system.ruby.LD.latency_hist_seqr::max_bucket 639 -system.ruby.LD.latency_hist_seqr::samples 62875 -system.ruby.LD.latency_hist_seqr::mean 27.680191 -system.ruby.LD.latency_hist_seqr::gmean 7.180276 -system.ruby.LD.latency_hist_seqr::stdev 35.811045 -system.ruby.LD.latency_hist_seqr | 50013 79.54% 79.54% | 11930 18.97% 98.52% | 656 1.04% 99.56% | 86 0.14% 99.70% | 110 0.17% 99.87% | 69 0.11% 99.98% | 11 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.latency_hist_seqr::total 62875 +system.ruby.LD.latency_hist_seqr::samples 49262 +system.ruby.LD.latency_hist_seqr::mean 24.300049 +system.ruby.LD.latency_hist_seqr::gmean 6.005369 +system.ruby.LD.latency_hist_seqr::stdev 33.377326 +system.ruby.LD.latency_hist_seqr | 40635 82.49% 82.49% | 7988 16.22% 98.70% | 461 0.94% 99.64% | 46 0.09% 99.73% | 67 0.14% 99.87% | 62 0.13% 99.99% | 1 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% +system.ruby.LD.latency_hist_seqr::total 49262 system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 -system.ruby.LD.hit_latency_hist_seqr::samples 30585 +system.ruby.LD.hit_latency_hist_seqr::samples 26006 system.ruby.LD.hit_latency_hist_seqr::mean 1 system.ruby.LD.hit_latency_hist_seqr::gmean 1 -system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 30585 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist_seqr::total 30585 +system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 26006 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist_seqr::total 26006 system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 -system.ruby.LD.miss_latency_hist_seqr::samples 32290 -system.ruby.LD.miss_latency_hist_seqr::mean 52.951595 -system.ruby.LD.miss_latency_hist_seqr::gmean 46.459624 -system.ruby.LD.miss_latency_hist_seqr::stdev 34.412980 -system.ruby.LD.miss_latency_hist_seqr | 19428 60.17% 60.17% | 11930 36.95% 97.11% | 656 2.03% 99.15% | 86 0.27% 99.41% | 110 0.34% 99.75% | 69 0.21% 99.97% | 11 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.miss_latency_hist_seqr::total 32290 +system.ruby.LD.miss_latency_hist_seqr::samples 23256 +system.ruby.LD.miss_latency_hist_seqr::mean 50.355306 +system.ruby.LD.miss_latency_hist_seqr::gmean 44.580095 +system.ruby.LD.miss_latency_hist_seqr::stdev 32.769798 +system.ruby.LD.miss_latency_hist_seqr | 14629 62.90% 62.90% | 7988 34.35% 97.25% | 461 1.98% 99.23% | 46 0.20% 99.43% | 67 0.29% 99.72% | 62 0.27% 99.99% | 1 0.00% 99.99% | 1 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% +system.ruby.LD.miss_latency_hist_seqr::total 23256 system.ruby.ST.latency_hist_seqr::bucket_size 64 system.ruby.ST.latency_hist_seqr::max_bucket 639 -system.ruby.ST.latency_hist_seqr::samples 43716 -system.ruby.ST.latency_hist_seqr::mean 11.968158 -system.ruby.ST.latency_hist_seqr::gmean 2.425644 -system.ruby.ST.latency_hist_seqr::stdev 26.441690 -system.ruby.ST.latency_hist_seqr | 40932 93.63% 93.63% | 2520 5.76% 99.40% | 167 0.38% 99.78% | 45 0.10% 99.88% | 22 0.05% 99.93% | 18 0.04% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 2 0.00% 99.98% | 10 0.02% 100.00% -system.ruby.ST.latency_hist_seqr::total 43716 +system.ruby.ST.latency_hist_seqr::samples 36806 +system.ruby.ST.latency_hist_seqr::mean 12.876080 +system.ruby.ST.latency_hist_seqr::gmean 2.576967 +system.ruby.ST.latency_hist_seqr::stdev 27.622954 +system.ruby.ST.latency_hist_seqr | 33978 92.32% 92.32% | 2589 7.03% 99.35% | 138 0.37% 99.73% | 38 0.10% 99.83% | 28 0.08% 99.90% | 24 0.07% 99.97% | 1 0.00% 99.97% | 0 0.00% 99.97% | 1 0.00% 99.98% | 9 0.02% 100.00% +system.ruby.ST.latency_hist_seqr::total 36806 system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 -system.ruby.ST.hit_latency_hist_seqr::samples 33299 +system.ruby.ST.hit_latency_hist_seqr::samples 27494 system.ruby.ST.hit_latency_hist_seqr::mean 1 system.ruby.ST.hit_latency_hist_seqr::gmean 1 -system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 33299 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist_seqr::total 33299 +system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 27494 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist_seqr::total 27494 system.ruby.ST.miss_latency_hist_seqr::bucket_size 64 system.ruby.ST.miss_latency_hist_seqr::max_bucket 639 -system.ruby.ST.miss_latency_hist_seqr::samples 10417 -system.ruby.ST.miss_latency_hist_seqr::mean 47.028991 -system.ruby.ST.miss_latency_hist_seqr::gmean 41.206543 -system.ruby.ST.miss_latency_hist_seqr::stdev 36.336668 -system.ruby.ST.miss_latency_hist_seqr | 7633 73.27% 73.27% | 2520 24.19% 97.47% | 167 1.60% 99.07% | 45 0.43% 99.50% | 22 0.21% 99.71% | 18 0.17% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 2 0.02% 99.90% | 10 0.10% 100.00% -system.ruby.ST.miss_latency_hist_seqr::total 10417 +system.ruby.ST.miss_latency_hist_seqr::samples 9312 +system.ruby.ST.miss_latency_hist_seqr::mean 47.940614 +system.ruby.ST.miss_latency_hist_seqr::gmean 42.162056 +system.ruby.ST.miss_latency_hist_seqr::stdev 37.013607 +system.ruby.ST.miss_latency_hist_seqr | 6484 69.63% 69.63% | 2589 27.80% 97.43% | 138 1.48% 98.92% | 38 0.41% 99.32% | 28 0.30% 99.62% | 24 0.26% 99.88% | 1 0.01% 99.89% | 0 0.00% 99.89% | 1 0.01% 99.90% | 9 0.10% 100.00% +system.ruby.ST.miss_latency_hist_seqr::total 9312 system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.latency_hist_seqr::samples 266250 -system.ruby.IFETCH.latency_hist_seqr::mean 9.802941 -system.ruby.IFETCH.latency_hist_seqr::gmean 1.746090 -system.ruby.IFETCH.latency_hist_seqr::stdev 26.280316 -system.ruby.IFETCH.latency_hist_seqr | 241576 90.73% 90.73% | 23044 8.66% 99.39% | 1032 0.39% 99.78% | 245 0.09% 99.87% | 190 0.07% 99.94% | 151 0.06% 100.00% | 6 0.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% | 3 0.00% 100.00% -system.ruby.IFETCH.latency_hist_seqr::total 266250 +system.ruby.IFETCH.latency_hist_seqr::samples 216812 +system.ruby.IFETCH.latency_hist_seqr::mean 9.489267 +system.ruby.IFETCH.latency_hist_seqr::gmean 1.727172 +system.ruby.IFETCH.latency_hist_seqr::stdev 25.438831 +system.ruby.IFETCH.latency_hist_seqr | 197026 90.87% 90.87% | 18488 8.53% 99.40% | 932 0.43% 99.83% | 96 0.04% 99.88% | 149 0.07% 99.94% | 112 0.05% 100.00% | 5 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 3 0.00% 100.00% +system.ruby.IFETCH.latency_hist_seqr::total 216812 system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 -system.ruby.IFETCH.hit_latency_hist_seqr::samples 229686 +system.ruby.IFETCH.hit_latency_hist_seqr::samples 187537 system.ruby.IFETCH.hit_latency_hist_seqr::mean 1 system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 -system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 229686 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist_seqr::total 229686 +system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 187537 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist_seqr::total 187537 system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.miss_latency_hist_seqr::samples 36564 -system.ruby.IFETCH.miss_latency_hist_seqr::mean 65.100837 -system.ruby.IFETCH.miss_latency_hist_seqr::gmean 57.898658 -system.ruby.IFETCH.miss_latency_hist_seqr::stdev 38.529976 -system.ruby.IFETCH.miss_latency_hist_seqr | 11890 32.52% 32.52% | 23044 63.02% 95.54% | 1032 2.82% 98.36% | 245 0.67% 99.03% | 190 0.52% 99.55% | 151 0.41% 99.97% | 6 0.02% 99.98% | 3 0.01% 99.99% | 0 0.00% 99.99% | 3 0.01% 100.00% -system.ruby.IFETCH.miss_latency_hist_seqr::total 36564 +system.ruby.IFETCH.miss_latency_hist_seqr::samples 29275 +system.ruby.IFETCH.miss_latency_hist_seqr::mean 63.871904 +system.ruby.IFETCH.miss_latency_hist_seqr::gmean 57.242479 +system.ruby.IFETCH.miss_latency_hist_seqr::stdev 37.061973 +system.ruby.IFETCH.miss_latency_hist_seqr | 9489 32.41% 32.41% | 18488 63.15% 95.57% | 932 3.18% 98.75% | 96 0.33% 99.08% | 149 0.51% 99.59% | 112 0.38% 99.97% | 5 0.02% 99.99% | 1 0.00% 99.99% | 0 0.00% 99.99% | 3 0.01% 100.00% +system.ruby.IFETCH.miss_latency_hist_seqr::total 29275 system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 -system.ruby.Directory.miss_mach_latency_hist_seqr::samples 79271 -system.ruby.Directory.miss_mach_latency_hist_seqr::mean 57.777182 -system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 50.619805 -system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 37.283085 -system.ruby.Directory.miss_mach_latency_hist_seqr | 38951 49.14% 49.14% | 37494 47.30% 96.44% | 1855 2.34% 98.78% | 376 0.47% 99.25% | 322 0.41% 99.66% | 238 0.30% 99.96% | 17 0.02% 99.98% | 3 0.00% 99.98% | 2 0.00% 99.98% | 13 0.02% 100.00% -system.ruby.Directory.miss_mach_latency_hist_seqr::total 79271 +system.ruby.Directory.miss_mach_latency_hist_seqr::samples 61843 +system.ruby.Directory.miss_mach_latency_hist_seqr::mean 56.390149 +system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 49.761350 +system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 36.211053 +system.ruby.Directory.miss_mach_latency_hist_seqr | 30602 49.48% 49.48% | 29065 47.00% 96.48% | 1531 2.48% 98.96% | 180 0.29% 99.25% | 244 0.39% 99.64% | 198 0.32% 99.96% | 7 0.01% 99.97% | 2 0.00% 99.98% | 1 0.00% 99.98% | 13 0.02% 100.00% +system.ruby.Directory.miss_mach_latency_hist_seqr::total 61843 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1 @@ -594,51 +594,51 @@ system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 32290 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 52.951595 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 46.459624 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 34.412980 -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 19428 60.17% 60.17% | 11930 36.95% 97.11% | 656 2.03% 99.15% | 86 0.27% 99.41% | 110 0.34% 99.75% | 69 0.21% 99.97% | 11 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 32290 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 23256 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 50.355306 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 44.580095 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 32.769798 +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 14629 62.90% 62.90% | 7988 34.35% 97.25% | 461 1.98% 99.23% | 46 0.20% 99.43% | 67 0.29% 99.72% | 62 0.27% 99.99% | 1 0.00% 99.99% | 1 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 23256 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 10417 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 47.028991 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 41.206543 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 36.336668 -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 7633 73.27% 73.27% | 2520 24.19% 97.47% | 167 1.60% 99.07% | 45 0.43% 99.50% | 22 0.21% 99.71% | 18 0.17% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 2 0.02% 99.90% | 10 0.10% 100.00% -system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 10417 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 9312 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 47.940614 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 42.162056 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 37.013607 +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 6484 69.63% 69.63% | 2589 27.80% 97.43% | 138 1.48% 98.92% | 38 0.41% 99.32% | 28 0.30% 99.62% | 24 0.26% 99.88% | 1 0.01% 99.89% | 0 0.00% 99.89% | 1 0.01% 99.90% | 9 0.10% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 9312 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 36564 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 65.100837 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 57.898658 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 38.529976 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 11890 32.52% 32.52% | 23044 63.02% 95.54% | 1032 2.82% 98.36% | 245 0.67% 99.03% | 190 0.52% 99.55% | 151 0.41% 99.97% | 6 0.02% 99.98% | 3 0.01% 99.99% | 0 0.00% 99.99% | 3 0.01% 100.00% -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 36564 -system.ruby.Directory_Controller.GETX 79271 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 79267 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 79271 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 79267 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 79271 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 79267 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 79271 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 79267 0.00% 0.00% -system.ruby.L1Cache_Controller.Load 62875 0.00% 0.00% -system.ruby.L1Cache_Controller.Ifetch 266250 0.00% 0.00% -system.ruby.L1Cache_Controller.Store 43716 0.00% 0.00% -system.ruby.L1Cache_Controller.Data 79271 0.00% 0.00% -system.ruby.L1Cache_Controller.Replacement 79267 0.00% 0.00% -system.ruby.L1Cache_Controller.Writeback_Ack 79267 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Load 32290 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Ifetch 36564 0.00% 0.00% -system.ruby.L1Cache_Controller.I.Store 10417 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Load 30585 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Ifetch 229686 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Store 33299 0.00% 0.00% -system.ruby.L1Cache_Controller.M.Replacement 79267 0.00% 0.00% -system.ruby.L1Cache_Controller.MI.Writeback_Ack 79267 0.00% 0.00% -system.ruby.L1Cache_Controller.IS.Data 68854 0.00% 0.00% -system.ruby.L1Cache_Controller.IM.Data 10417 0.00% 0.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 29275 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 63.871904 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 57.242479 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 37.061973 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 9489 32.41% 32.41% | 18488 63.15% 95.57% | 932 3.18% 98.75% | 96 0.33% 99.08% | 149 0.51% 99.59% | 112 0.38% 99.97% | 5 0.02% 99.99% | 1 0.00% 99.99% | 0 0.00% 99.99% | 3 0.01% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 29275 +system.ruby.Directory_Controller.GETX 61843 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 61839 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 61843 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 61839 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 61843 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 61839 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 61843 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 61839 0.00% 0.00% +system.ruby.L1Cache_Controller.Load 49262 0.00% 0.00% +system.ruby.L1Cache_Controller.Ifetch 216812 0.00% 0.00% +system.ruby.L1Cache_Controller.Store 36806 0.00% 0.00% +system.ruby.L1Cache_Controller.Data 61843 0.00% 0.00% +system.ruby.L1Cache_Controller.Replacement 61839 0.00% 0.00% +system.ruby.L1Cache_Controller.Writeback_Ack 61839 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Load 23256 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Ifetch 29275 0.00% 0.00% +system.ruby.L1Cache_Controller.I.Store 9312 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Load 26006 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Ifetch 187537 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Store 27494 0.00% 0.00% +system.ruby.L1Cache_Controller.M.Replacement 61839 0.00% 0.00% +system.ruby.L1Cache_Controller.MI.Writeback_Ack 61839 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Data 52531 0.00% 0.00% +system.ruby.L1Cache_Controller.IM.Data 9312 0.00% 0.00% ---------- End Simulation Statistics ---------- diff -r fcea8c1b00f7 -r aaf914ea5a83 tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/config.ini --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/config.ini Wed Jan 18 16:27:49 2017 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/config.ini Wed Jan 18 16:41:56 2017 +0000 @@ -296,7 +296,7 @@ errout=cerr euid=100 eventq_index=0 -executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64i/insttest +executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64i/insttest gid=100 input=cin kvmInSE=false diff -r fcea8c1b00f7 -r aaf914ea5a83 tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/config.json --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/config.json Wed Jan 18 16:27:49 2017 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/config.json Wed Jan 18 16:41:56 2017 +0000 @@ -377,7 +377,7 @@ "pid": 100, "kvmInSE": false, "cxx_class": "LiveProcess", - "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64i/insttest", + "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64i/insttest", "drivers": [], "system": "system", "gid": 100, diff -r fcea8c1b00f7 -r aaf914ea5a83 tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/simout --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/simout Wed Jan 18 16:27:49 2017 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/simout Wed Jan 18 16:41:56 2017 +0000 @@ -3,17 +3,17 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 30 2016 14:33:35 -gem5 started Nov 30 2016 16:18:43 -gem5 executing on zizzer, pid 34089 -command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64i/simple-timing +gem5 compiled Jan 12 2017 21:09:16 +gem5 started Jan 12 2017 21:09:32 +gem5 executing on ubuntu1604, pid 14230 +command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-timing -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64i/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. lui: PASS lui, negative: PASS -auipc: 0x157E0 +auipc: 0x14FB0 auipc: PASS jal: PASS jalr: PASS @@ -86,36 +86,44 @@ or (A): PASS and (0): PASS and (-1): PASS -Bytes written: 15 -open, write: PASS -access F_OK: PASS -access R_OK: PASS -access W_OK: PASS -access X_OK: PASS -stat: - st_dev = 2054 - st_ino = 55451710 - st_mode = 33188 - st_nlink = 1 - st_uid = 1004 - st_gid = 1007 - st_rdev = 0 - st_size = 0 - st_blksize = 0 - st_blocks = 1480540730 -fstat: - st_dev = 2054 - st_ino = 58196126 - st_mode = 33277 - st_nlink = 1 - st_uid = 1004 - st_gid = 1007 - st_rdev = 0 - st_size = 0 - st_blksize = 0 - st_blocks = 1480540723 -open, stat: PASS -Bytes read: 9 -String read: Ð -open, read, unlink: FAIL (expected 1; found 0) -Exiting @ tick 352925500 because target called exit() +Cycles: 565249 +rdcycle: PASS +Time: 1484255377 +rdtime: PASS +Instructions Retired: 165715 +rdinstret: PASS +lwu: PASS +ld: PASS +sd: PASS +addiw: PASS +addiw, overflow: PASS +addiw, truncate: PASS +slliw, general: PASS +slliw, erase: PASS +slliw, truncate: PASS +srliw, general: PASS +srliw, erase: PASS +srliw, negative: PASS +srliw, truncate: PASS +sraiw, general: PASS +sraiw, erase: PASS +sraiw, negative: PASS +sraiw, truncate: PASS +addw: PASS +addw, overflow: PASS +addw, truncate: PASS +subw: PASS +subw, "overflow": PASS +subw, truncate: PASS +sllw, general: PASS +sllw, erase: PASS +sllw, truncate: PASS +srlw, general: PASS +srlw, erase: PASS +srlw, negative: PASS +srlw, truncate: PASS +sraw, general: PASS +sraw, erase: PASS +sraw, negative: PASS +sraw, truncate: PASS +Exiting @ tick 372369500 because target called exit() diff -r fcea8c1b00f7 -r aaf914ea5a83 tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/stats.txt --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/stats.txt Wed Jan 18 16:27:49 2017 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/simple-timing/stats.txt Wed Jan 18 16:41:56 2017 +0000 @@ -1,36 +1,36 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000353 # Number of seconds simulated -sim_ticks 352925500 # Number of ticks simulated -final_tick 352925500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000372 # Number of seconds simulated +sim_ticks 372369500 # Number of ticks simulated +final_tick 372369500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 23308 # Simulator instruction rate (inst/s) -host_op_rate 23308 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 40827277 # Simulator tick rate (ticks/s) -host_mem_usage 243536 # Number of bytes of host memory used -host_seconds 8.64 # Real time elapsed on the host -sim_insts 201478 # Number of instructions simulated -sim_ops 201478 # Number of ops (including micro ops) simulated +host_inst_rate 28971 # Simulator instruction rate (inst/s) +host_op_rate 28971 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 49790571 # Simulator tick rate (ticks/s) +host_mem_usage 264768 # Number of bytes of host memory used +host_seconds 7.48 # Real time elapsed on the host +sim_insts 216668 # Number of instructions simulated +sim_ops 216668 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 55168 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18368 # Number of bytes read from this memory -system.physmem.bytes_read::total 73536 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 55168 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 55168 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 862 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 287 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1149 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 156316276 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 52044978 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 208361255 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 156316276 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 156316276 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 156316276 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 52044978 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 208361255 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 372369500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 53760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 17920 # Number of bytes read from this memory +system.physmem.bytes_read::total 71680 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 53760 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 53760 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 840 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 280 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1120 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 144372727 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 48124242 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 192496969 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 144372727 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 144372727 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 144372727 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 48124242 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 192496969 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 372369500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses @@ -50,128 +50,128 @@ system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 130 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 352925500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 705851 # number of cpu cycles simulated +system.cpu.workload.num_syscalls 124 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 372369500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 744739 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 201478 # Number of instructions committed -system.cpu.committedOps 201478 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 201477 # Number of integer alu accesses +system.cpu.committedInsts 216668 # Number of instructions committed +system.cpu.committedOps 216668 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 216667 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 14627 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 30164 # number of instructions that are conditional controls -system.cpu.num_int_insts 201477 # number of integer instructions +system.cpu.num_func_calls 15750 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 32857 # number of instructions that are conditional controls +system.cpu.num_int_insts 216667 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 266871 # number of times the integer registers were read -system.cpu.num_int_register_writes 137624 # number of times the integer registers were written +system.cpu.num_int_register_reads 287238 # number of times the integer registers were read +system.cpu.num_int_register_writes 147005 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 80078 # number of memory refs -system.cpu.num_load_insts 46389 # Number of load instructions -system.cpu.num_store_insts 33689 # Number of store instructions +system.cpu.num_mem_refs 86064 # number of memory refs +system.cpu.num_load_insts 49259 # Number of load instructions +system.cpu.num_store_insts 36805 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 705851 # Number of busy cycles +system.cpu.num_busy_cycles 744739 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.Branches 44791 # Number of branches fetched -system.cpu.op_class::No_OpClass 132 0.07% 0.07% # Class of executed instruction -system.cpu.op_class::IntAlu 120936 59.99% 60.05% # Class of executed instruction -system.cpu.op_class::IntMult 297 0.15% 60.20% # Class of executed instruction -system.cpu.op_class::IntDiv 166 0.08% 60.28% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 60.28% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 60.28% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 60.28% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 60.28% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 60.28% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 60.28% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 60.28% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 60.28% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 60.28% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 60.28% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 60.28% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 60.28% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 60.28% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 60.28% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 60.28% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 60.28% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 60.28% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 60.28% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 60.28% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 60.28% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 60.28% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 60.28% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 60.28% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 60.28% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 60.28% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 60.28% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.28% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.28% # Class of executed instruction -system.cpu.op_class::MemRead 46389 23.01% 83.29% # Class of executed instruction -system.cpu.op_class::MemWrite 33689 16.71% 100.00% # Class of executed instruction +system.cpu.Branches 48607 # Number of branches fetched +system.cpu.op_class::No_OpClass 129 0.06% 0.06% # Class of executed instruction +system.cpu.op_class::IntAlu 130215 60.06% 60.12% # Class of executed instruction +system.cpu.op_class::IntMult 341 0.16% 60.28% # Class of executed instruction +system.cpu.op_class::IntDiv 44 0.02% 60.30% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::FloatMultAcc 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::FloatMisc 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.30% # Class of executed instruction +system.cpu.op_class::MemRead 49259 22.72% 83.02% # Class of executed instruction +system.cpu.op_class::MemWrite 36805 16.98% 100.00% # Class of executed instruction system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 201609 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states +system.cpu.op_class::total 216793 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 372369500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 237.806291 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 79790 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 287 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 278.013937 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 238.899633 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 85783 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 280 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 306.367857 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 237.806291 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.058058 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.058058 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 287 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 264 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.070068 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 160441 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 160441 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 46314 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 46314 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 33476 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 33476 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 79790 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 79790 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 79790 # number of overall hits -system.cpu.dcache.overall_hits::total 79790 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 75 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 75 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 212 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 212 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 287 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 287 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 287 # number of overall misses -system.cpu.dcache.overall_misses::total 287 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4725000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4725000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 13356000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 13356000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 18081000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 18081000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 18081000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 18081000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 46389 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 46389 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 33688 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 33688 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 80077 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 80077 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 80077 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 80077 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001617 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.001617 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006293 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006293 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.003584 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.003584 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.003584 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.003584 # miss rate for overall accesses +system.cpu.dcache.tags.occ_blocks::cpu.data 238.899633 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.058325 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.058325 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 280 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 266 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.068359 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 172406 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 172406 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 372369500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 49179 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 49179 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 36604 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 36604 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 85783 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 85783 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 85783 # number of overall hits +system.cpu.dcache.overall_hits::total 85783 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 80 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 80 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 200 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 200 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 280 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 280 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 280 # number of overall misses +system.cpu.dcache.overall_misses::total 280 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5040000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5040000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 12600000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 12600000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 17640000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17640000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 17640000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17640000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 49259 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 49259 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 36804 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 36804 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 86063 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 86063 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 86063 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 86063 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001624 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.001624 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005434 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.005434 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.003253 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.003253 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.003253 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.003253 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency @@ -186,30 +186,30 @@ system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 75 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 75 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 212 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 212 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 287 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 287 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 287 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 287 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4650000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4650000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13144000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 13144000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17794000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 17794000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17794000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 17794000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001617 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001617 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006293 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006293 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003584 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.003584 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003584 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.003584 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 80 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 80 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 200 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 200 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 280 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 280 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 280 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 280 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4960000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4960000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12400000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12400000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17360000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 17360000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17360000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 17360000 # 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average WriteReq mshr miss latency @@ -218,298 +218,304 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 16 # number of replacements -system.cpu.icache.tags.tagsinuse 467.242122 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 200748 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 862 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 232.886311 # Average number of references to valid blocks. +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 372369500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 37 # 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average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 63001.740139 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 63001.740139 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 63001.740139 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 63001.740139 # average overall miss latency +system.cpu.icache.tags.occ_blocks::cpu.inst 473.693596 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.231296 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.231296 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 809 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 638 # 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average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 62647.163121 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 62647.163121 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 62647.163121 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 62647.163121 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 16 # number of writebacks -system.cpu.icache.writebacks::total 16 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 862 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 862 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 862 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 862 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 862 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 862 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 53445500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 53445500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 53445500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 53445500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 53445500 # 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mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.003902 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.003902 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61647.163121 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61647.163121 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61647.163121 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 61647.163121 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61647.163121 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 61647.163121 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 372369500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 708.129693 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 16 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1149 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.013925 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 722.544979 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 43 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1120 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.038393 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 470.314864 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 237.814829 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.014353 # 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average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50501.160093 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50501.190476 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.870322 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50501.160093 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.892857 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50501.190476 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.870322 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1165 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 16 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.892857 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1163 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 37 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 937 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 16 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 212 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 212 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 862 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 75 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1740 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 574 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2314 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56192 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18368 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 74560 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 372369500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 926 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 37 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 200 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 200 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 846 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 80 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1729 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 560 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2289 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56512 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17920 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 74432 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1149 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 1126 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1149 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1126 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1149 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 598500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1126 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 618500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1293000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 430500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1269000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 420000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 1149 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_requests 1120 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 937 # Transaction distribution -system.membus.trans_dist::ReadExReq 212 # Transaction distribution -system.membus.trans_dist::ReadExResp 212 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 937 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2298 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 2298 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 73536 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 73536 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 372369500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 920 # Transaction distribution +system.membus.trans_dist::ReadExReq 200 # Transaction distribution +system.membus.trans_dist::ReadExResp 200 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 920 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2240 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2240 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 71680 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 71680 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 1149 # Request fanout histogram +system.membus.snoop_fanout::samples 1120 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1149 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1120 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 1149 # Request fanout histogram -system.membus.reqLayer0.occupancy 1150000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 1120 # Request fanout histogram +system.membus.reqLayer0.occupancy 1121000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 5745000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 5600000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff -r fcea8c1b00f7 -r aaf914ea5a83 tests/test-progs/insttest/src/riscv/rv64i.cpp --- a/tests/test-progs/insttest/src/riscv/rv64i.cpp Wed Jan 18 16:27:49 2017 +0000 +++ b/tests/test-progs/insttest/src/riscv/rv64i.cpp Wed Jan 18 16:41:56 2017 +0000 @@ -236,6 +236,9 @@ asm volatile("fence.i" : : ); // ECALL + // These tests are commented out until file-system-dependent behavior can + // be accounted for +/* char fname[] = "test.txt"; char teststr[] = "this is a test"; expect(true, [=]{ @@ -322,6 +325,7 @@ cout << "\ttv_usec =\t" << time.tv_usec << endl; return res; }, "gettimeofday"); +*/ // EBREAK not tested because it only makes sense in FS mode or when // using gdb diff -r fcea8c1b00f7 -r aaf914ea5a83 tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/config.ini --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/config.ini Wed Jan 18 16:27:49 2017 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/config.ini Wed Jan 18 16:41:56 2017 +0000 @@ -754,7 +754,7 @@ errout=cerr euid=100 eventq_index=0 -executable=/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64i/insttest +executable=/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64i/insttest gid=100 input=cin kvmInSE=false diff -r fcea8c1b00f7 -r aaf914ea5a83 tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/config.json --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/config.json Wed Jan 18 16:27:49 2017 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/config.json Wed Jan 18 16:41:56 2017 +0000 @@ -1059,7 +1059,7 @@ "pid": 100, "kvmInSE": false, "cxx_class": "LiveProcess", - "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64i/insttest", + "executable": "/home/ar4jc/gem5/tests/testing/../test-progs/insttest/bin/riscv/linux-rv64i/insttest", "drivers": [], "system": "system", "gid": 100, diff -r fcea8c1b00f7 -r aaf914ea5a83 tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/simout --- a/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/simout Wed Jan 18 16:27:49 2017 +0000 +++ b/tests/quick/se/02.insttest/ref/riscv/linux-rv64i/minor-timing/simout Wed Jan 18 16:41:56 2017 +0000 @@ -3,17 +3,17 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 30 2016 14:33:35 -gem5 started Nov 30 2016 16:18:43 -gem5 executing on zizzer, pid 34087 -command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/minor-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64i/minor-timing +gem5 compiled Jan 12 2017 21:09:16 +gem5 started Jan 12 2017 21:09:32 +gem5 executing on ubuntu1604, pid 14231 +command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/minor-timing -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64i/minor-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. lui: PASS lui, negative: PASS -auipc: 0x157E0 +auipc: 0x14FB0 auipc: PASS jal: PASS jalr: PASS @@ -86,36 +86,44 @@ or (A): PASS and (0): PASS and (-1): PASS -Bytes written: 15 -open, write: PASS -access F_OK: PASS -access R_OK: PASS -access W_OK: PASS -access X_OK: PASS -stat: - st_dev = 2054 - st_ino = 55451710 - st_mode = 33188 - st_nlink = 1 - st_uid = 1004 - st_gid = 1007 - st_rdev = 0 - st_size = 0 - st_blksize = 0 - st_blocks = 1480540730 -fstat: - st_dev = 2054 - st_ino = 55451710 - st_mode = 33188 - st_nlink = 1 - st_uid = 1004 - st_gid = 1007 - st_rdev = 0 - st_size = 0 - st_blksize = 0 - st_blocks = 1480540730 -open, stat: PASS -Bytes read: 1 -String read:  -open, read, unlink: FAIL (expected 1; found 0) -Exiting @ tick 257396500 because target called exit() +Cycles: 416899 +rdcycle: PASS +Time: 1484255378 +rdtime: PASS +Instructions Retired: 165800 +rdinstret: PASS +lwu: PASS +ld: PASS +sd: PASS +addiw: PASS +addiw, overflow: PASS +addiw, truncate: PASS +slliw, general: PASS +slliw, erase: PASS +slliw, truncate: PASS +srliw, general: PASS +srliw, erase: PASS +srliw, negative: PASS +srliw, truncate: PASS +sraiw, general: PASS +sraiw, erase: PASS +sraiw, negative: PASS +sraiw, truncate: PASS +addw: PASS +addw, overflow: PASS +addw, truncate: PASS +subw: PASS +subw, "overflow": PASS +subw, truncate: PASS +sllw, general: PASS +sllw, erase: PASS +sllw, truncate: PASS +srlw, general: PASS +srlw, erase: PASS +srlw, negative: PASS +srlw, truncate: PASS +sraw, general: PASS +sraw, erase: PASS +sraw, negative: PASS +sraw, truncate: PASS +Exiting @ tick 263193500 because target called exit()