diff -r c5b7a3ae6596 -r cac528b2adc2 configs/common/CacheConfig.py
--- a/configs/common/CacheConfig.py	Sat Jan 29 15:58:05 2011 -0800
+++ b/configs/common/CacheConfig.py	Sat Jan 29 15:59:08 2011 -0800
@@ -43,8 +43,14 @@
 
     for i in xrange(options.num_cpus):
         if options.caches:
-            system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
-                                                  L1Cache(size = '64kB'))
+            if buildEnv['TARGET_ISA'] == 'x86':
+                system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
+                                                      L1Cache(size = '64kB'),
+                                                      PageTableWalkerCache(),
+                                                      PageTableWalkerCache())
+            else:
+                system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
+                                                      L1Cache(size = '64kB'))
         if options.l2cache:
             system.cpu[i].connectMemPorts(system.tol2bus)
         else:
diff -r c5b7a3ae6596 -r cac528b2adc2 configs/common/Caches.py
--- a/configs/common/Caches.py	Sat Jan 29 15:58:05 2011 -0800
+++ b/configs/common/Caches.py	Sat Jan 29 15:59:08 2011 -0800
@@ -42,6 +42,14 @@
     mshrs = 20
     tgts_per_mshr = 12
 
+class PageTableWalkerCache(BaseCache):
+    assoc = 2
+    block_size = 64
+    latency = '1ns'
+    mshrs = 10
+    size = '1kB'
+    tgts_per_mshr = 12
+
 class IOCache(BaseCache):
     assoc = 8
     block_size = 64
diff -r c5b7a3ae6596 -r cac528b2adc2 src/cpu/BaseCPU.py
--- a/src/cpu/BaseCPU.py	Sat Jan 29 15:58:05 2011 -0800
+++ b/src/cpu/BaseCPU.py	Sat Jan 29 15:59:08 2011 -0800
@@ -166,7 +166,7 @@
             if p != 'physmem_port':
                 exec('self.%s = bus.port' % p)
 
-    def addPrivateSplitL1Caches(self, ic, dc):
+    def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
         assert(len(self._mem_ports) < 8)
         self.icache = ic
         self.dcache = dc
@@ -174,13 +174,19 @@
         self.dcache_port = dc.cpu_side
         self._mem_ports = ['icache.mem_side', 'dcache.mem_side']
         if buildEnv['FULL_SYSTEM']:
-            if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
+            if buildEnv['TARGET_ISA'] == 'x86':
+                self.itb_walker_cache = iwc
+                self.dtb_walker_cache = dwc
+                self.itb.walker.port = iwc.cpu_side
+                self.dtb.walker.port = dwc.cpu_side
+                self._mem_ports += ["itb_walker_cache.mem_side", \
+                                    "dtb_walker_cache.mem_side"]
+                self._mem_ports += ["interrupts.pio", "interrupts.int_port"]
+            elif buildEnv['TARGET_ISA'] == 'arm':
                 self._mem_ports += ["itb.walker.port", "dtb.walker.port"]
-            if buildEnv['TARGET_ISA'] == 'x86':
-                self._mem_ports += ["interrupts.pio", "interrupts.int_port"]
 
-    def addTwoLevelCacheHierarchy(self, ic, dc, l2c):
-        self.addPrivateSplitL1Caches(ic, dc)
+    def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
+        self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
         self.toL2Bus = Bus()
         self.connectMemPorts(self.toL2Bus)
         self.l2cache = l2c
diff -r c5b7a3ae6596 -r cac528b2adc2 src/cpu/o3/O3CPU.py
--- a/src/cpu/o3/O3CPU.py	Sat Jan 29 15:58:05 2011 -0800
+++ b/src/cpu/o3/O3CPU.py	Sat Jan 29 15:59:08 2011 -0800
@@ -141,7 +141,7 @@
     smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter")
     smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy")
 
-    def addPrivateSplitL1Caches(self, ic, dc):
-        BaseCPU.addPrivateSplitL1Caches(self, ic, dc)
+    def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
+        BaseCPU.addPrivateSplitL1Caches(self, ic, dc, iwc, dwc)
         self.icache.tgts_per_mshr = 20
         self.dcache.tgts_per_mshr = 20