diff -r 90bf109393c3 -r c18eae4d04e4 src/cpu/o3/lsq_unit.hh
--- a/src/cpu/o3/lsq_unit.hh	Fri Feb 25 01:21:47 2011 -0800
+++ b/src/cpu/o3/lsq_unit.hh	Sat Feb 26 16:29:36 2011 -0800
@@ -39,6 +39,7 @@
 
 #include "arch/faults.hh"
 #include "arch/locked_mem.hh"
+#include "arch/mmaped_ipr.hh"
 #include "config/full_system.hh"
 #include "config/the_isa.hh"
 #include "base/fast_alloc.hh"
@@ -562,6 +563,41 @@
         load_inst->recordResult = true;
     }
 
+    if (req->isMmapedIpr()) {
+        assert(!load_inst->memData);
+        load_inst->memData = new uint8_t[64];
+
+        ThreadContext *thread = cpu->tcBase(lsqID);
+        Tick delay;
+        PacketPtr data_pkt =
+            new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
+
+        if (!TheISA::HasUnalignedMemAcc || !sreqLow) {
+            data_pkt->dataStatic(load_inst->memData);
+            delay = TheISA::handleIprRead(thread, data_pkt);
+        } else {
+            assert(sreqLow->isMmapedIpr() && sreqHigh->isMmapedIpr());
+            PacketPtr fst_data_pkt =
+                new Packet(sreqLow, MemCmd::ReadReq, Packet::Broadcast);
+            PacketPtr snd_data_pkt =
+                new Packet(sreqHigh, MemCmd::ReadReq, Packet::Broadcast);
+
+            fst_data_pkt->dataStatic(load_inst->memData);
+            snd_data_pkt->dataStatic(load_inst->memData + sreqLow->getSize());
+
+            delay = TheISA::handleIprRead(thread, fst_data_pkt);
+            unsigned delay2 = TheISA::handleIprRead(thread, snd_data_pkt);
+            if (delay2 > delay)
+                delay = delay2;
+
+            delete fst_data_pkt;
+            delete snd_data_pkt;
+        }
+        WritebackEvent *wb = new WritebackEvent(load_inst, data_pkt, this);
+        cpu->schedule(wb, curTick() + delay);
+        return NoFault;
+    }
+
     while (store_idx != -1) {
         // End once we've reached the top of the LSQ
         if (store_idx == storeWBIdx) {
diff -r 90bf109393c3 -r c18eae4d04e4 src/cpu/o3/lsq_unit_impl.hh
--- a/src/cpu/o3/lsq_unit_impl.hh	Fri Feb 25 01:21:47 2011 -0800
+++ b/src/cpu/o3/lsq_unit_impl.hh	Sat Feb 26 16:29:36 2011 -0800
@@ -806,20 +806,34 @@
             state->noWB = true;
         }
 
-        if (!sendStore(data_pkt)) {
+        bool split =
+            TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit;
+
+        ThreadContext *thread = cpu->tcBase(lsqID);
+
+        if (req->isMmapedIpr()) {
+            assert(!inst->isStoreConditional());
+            TheISA::handleIprWrite(thread, data_pkt);
+            if (split) {
+                assert(snd_data_pkt->req->isMmapedIpr());
+                TheISA::handleIprWrite(thread, snd_data_pkt);
+            }
+            completeStore(storeWBIdx);
+            incrStIdx(storeWBIdx);
+        } else if (!sendStore(data_pkt)) {
             DPRINTF(IEW, "D-Cache became blocked when writing [sn:%lli], will"
                     "retry later\n",
                     inst->seqNum);
 
             // Need to store the second packet, if split.
-            if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) {
+            if (split) {
                 state->pktToSend = true;
                 state->pendingPacket = snd_data_pkt;
             }
         } else {
 
             // If split, try to send the second packet too
-            if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) {
+            if (split) {
                 assert(snd_data_pkt);
 
                 // Ensure there are enough ports to use.