diff -r 1d371a84a085 -r ed52ebb95491 configs/common/Caches.py
--- a/configs/common/Caches.py	Fri Feb 25 22:57:40 2011 -0600
+++ b/configs/common/Caches.py	Fri Feb 25 22:57:52 2011 -0600
@@ -34,6 +34,7 @@
     latency = '1ns'
     mshrs = 10
     tgts_per_mshr = 5
+    is_top_level = True
 
 class L2Cache(BaseCache):
     assoc = 8
@@ -49,6 +50,7 @@
     mshrs = 10
     size = '1kB'
     tgts_per_mshr = 12
+    is_top_level = True
 
 class IOCache(BaseCache):
     assoc = 8
@@ -58,3 +60,4 @@
     size = '1kB'
     tgts_per_mshr = 12
     forward_snoops = False
+    is_top_level = True
diff -r 1d371a84a085 -r ed52ebb95491 src/cpu/o3/fetch_impl.hh
--- a/src/cpu/o3/fetch_impl.hh	Fri Feb 25 22:57:40 2011 -0600
+++ b/src/cpu/o3/fetch_impl.hh	Fri Feb 25 22:57:52 2011 -0600
@@ -112,6 +112,9 @@
 {
     DPRINTF(Fetch, "Received timing\n");
     if (pkt->isResponse()) {
+        // We shouldn't ever get a block in ownership state
+        assert(pkt->sharedAsserted() || !pkt->memInhibitAsserted());
+
         fetch->processCacheCompletion(pkt);
     }
     //else Snooped a coherence request, just return
diff -r 1d371a84a085 -r ed52ebb95491 src/dev/io_device.cc
--- a/src/dev/io_device.cc	Fri Feb 25 22:57:40 2011 -0600
+++ b/src/dev/io_device.cc	Fri Feb 25 22:57:52 2011 -0600
@@ -139,6 +139,9 @@
         assert(pendingCount >= 0);
         assert(state);
 
+        // We shouldn't ever get a block in ownership state
+        assert(pkt->sharedAsserted() || !pkt->memInhibitAsserted());
+
         state->numBytes += pkt->req->getSize();
         assert(state->totBytes >= state->numBytes);
         if (state->totBytes == state->numBytes) {
diff -r 1d371a84a085 -r ed52ebb95491 src/mem/cache/BaseCache.py
--- a/src/mem/cache/BaseCache.py	Fri Feb 25 22:57:40 2011 -0600
+++ b/src/mem/cache/BaseCache.py	Fri Feb 25 22:57:52 2011 -0600
@@ -48,6 +48,7 @@
     size = Param.MemorySize("capacity in bytes")
     forward_snoops = Param.Bool(True,
         "forward snoops from mem side to cpu side")
+    is_top_level = Param.Bool(False, "Is this cache at the top level (e.g. L1)")
     subblock_size = Param.Int(0,
         "Size of subblock in IIC used for compression")
     tgts_per_mshr = Param.Int("max number of accesses per MSHR")
diff -r 1d371a84a085 -r ed52ebb95491 src/mem/cache/base.hh
--- a/src/mem/cache/base.hh	Fri Feb 25 22:57:40 2011 -0600
+++ b/src/mem/cache/base.hh	Fri Feb 25 22:57:52 2011 -0600
@@ -194,6 +194,11 @@
     /** Do we forward snoops from mem side port through to cpu side port? */
     bool forwardSnoops;
 
+    /** Is this cache a toplevel cache (e.g. L1, I/O cache). If so we should
+     * never try to forward ownership and similar optimizations to the cpu
+     * side */
+    bool isTopLevel;
+
     /**
      * Bit vector of the blocking reasons for the access path.
      * @sa #BlockedCause
diff -r 1d371a84a085 -r ed52ebb95491 src/mem/cache/base.cc
--- a/src/mem/cache/base.cc	Fri Feb 25 22:57:40 2011 -0600
+++ b/src/mem/cache/base.cc	Fri Feb 25 22:57:52 2011 -0600
@@ -58,6 +58,7 @@
       hitLatency(p->latency),
       numTarget(p->tgts_per_mshr),
       forwardSnoops(p->forward_snoops),
+      isTopLevel(p->is_top_level),
       blocked(0),
       noTargetMSHR(NULL),
       missCount(p->max_miss_count),
diff -r 1d371a84a085 -r ed52ebb95491 src/mem/cache/cache_impl.hh
--- a/src/mem/cache/cache_impl.hh	Fri Feb 25 22:57:40 2011 -0600
+++ b/src/mem/cache/cache_impl.hh	Fri Feb 25 22:57:52 2011 -0600
@@ -216,7 +216,7 @@
                 
                 if (blk->isDirty()) {
                     // special considerations if we're owner:
-                    if (!deferred_response) {
+                    if (!deferred_response && !isTopLevel) {
                         // if we are responding immediately and can
                         // signal that we're transferring ownership
                         // along with exclusivity, do so
diff -r 1d371a84a085 -r ed52ebb95491 tests/configs/inorder-timing.py
--- a/tests/configs/inorder-timing.py	Fri Feb 25 22:57:40 2011 -0600
+++ b/tests/configs/inorder-timing.py	Fri Feb 25 22:57:52 2011 -0600
@@ -37,8 +37,12 @@
     mshrs = 10
     tgts_per_mshr = 5
 
+class MyL1Cache(MyCache):
+    is_top_level = True
+
 cpu = InOrderCPU(cpu_id=0)
-cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
+cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
+                              MyL1Cache(size = '256kB'),
                               MyCache(size = '2MB', latency='10ns'))
 
 cpu.clock = '2GHz'
diff -r 1d371a84a085 -r ed52ebb95491 tests/configs/memtest.py
--- a/tests/configs/memtest.py	Fri Feb 25 22:57:40 2011 -0600
+++ b/tests/configs/memtest.py	Fri Feb 25 22:57:52 2011 -0600
@@ -38,6 +38,7 @@
     block_size = 64
     mshrs = 12
     tgts_per_mshr = 8
+    is_top_level = True
 
 # ----------------------
 # Base L2 Cache
diff -r 1d371a84a085 -r ed52ebb95491 tests/configs/o3-timing-mp.py
--- a/tests/configs/o3-timing-mp.py	Fri Feb 25 22:57:40 2011 -0600
+++ b/tests/configs/o3-timing-mp.py	Fri Feb 25 22:57:52 2011 -0600
@@ -39,6 +39,7 @@
     block_size = 64
     mshrs = 4
     tgts_per_mshr = 8
+    is_top_level = True
 
 # ----------------------
 # Base L2 Cache
diff -r 1d371a84a085 -r ed52ebb95491 tests/configs/o3-timing.py
--- a/tests/configs/o3-timing.py	Fri Feb 25 22:57:40 2011 -0600
+++ b/tests/configs/o3-timing.py	Fri Feb 25 22:57:52 2011 -0600
@@ -37,8 +37,12 @@
     mshrs = 10
     tgts_per_mshr = 5
 
+class MyL1Cache(MyCache):
+    is_top_level = True
+
 cpu = DerivO3CPU(cpu_id=0)
-cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
+cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
+                              MyL1Cache(size = '256kB'),
                               MyCache(size = '2MB'))
 cpu.clock = '2GHz'
 
diff -r 1d371a84a085 -r ed52ebb95491 tests/configs/pc-simple-atomic.py
--- a/tests/configs/pc-simple-atomic.py	Fri Feb 25 22:57:40 2011 -0600
+++ b/tests/configs/pc-simple-atomic.py	Fri Feb 25 22:57:52 2011 -0600
@@ -43,6 +43,7 @@
     block_size = 64
     mshrs = 4
     tgts_per_mshr = 8
+    is_top_level = True
 
 # ----------------------
 # Base L2 Cache
@@ -65,6 +66,7 @@
     mshrs = 10
     size = '1kB'
     tgts_per_mshr = 12
+    is_top_level = True
 
 # ---------------------
 # I/O Cache
@@ -78,6 +80,7 @@
     tgts_per_mshr = 12
     addr_range = AddrRange(0, size=mem_size)
     forward_snoops = False
+    is_top_level = True
 
 #cpu
 cpu = AtomicSimpleCPU(cpu_id=0)
diff -r 1d371a84a085 -r ed52ebb95491 tests/configs/pc-simple-timing.py
--- a/tests/configs/pc-simple-timing.py	Fri Feb 25 22:57:40 2011 -0600
+++ b/tests/configs/pc-simple-timing.py	Fri Feb 25 22:57:52 2011 -0600
@@ -44,6 +44,7 @@
     block_size = 64
     mshrs = 4
     tgts_per_mshr = 8
+    is_top_level = True
 
 # ----------------------
 # Base L2 Cache
diff -r 1d371a84a085 -r ed52ebb95491 tests/configs/realview-simple-atomic.py
--- a/tests/configs/realview-simple-atomic.py	Fri Feb 25 22:57:40 2011 -0600
+++ b/tests/configs/realview-simple-atomic.py	Fri Feb 25 22:57:52 2011 -0600
@@ -40,6 +40,7 @@
     block_size = 64
     mshrs = 4
     tgts_per_mshr = 8
+    is_top_level = True
 
 # ----------------------
 # Base L2 Cache
diff -r 1d371a84a085 -r ed52ebb95491 tests/configs/realview-simple-timing.py
--- a/tests/configs/realview-simple-timing.py	Fri Feb 25 22:57:40 2011 -0600
+++ b/tests/configs/realview-simple-timing.py	Fri Feb 25 22:57:52 2011 -0600
@@ -41,6 +41,7 @@
     block_size = 64
     mshrs = 4
     tgts_per_mshr = 8
+    is_top_level = True
 
 # ----------------------
 # Base L2 Cache
diff -r 1d371a84a085 -r ed52ebb95491 tests/configs/simple-atomic-mp.py
--- a/tests/configs/simple-atomic-mp.py	Fri Feb 25 22:57:40 2011 -0600
+++ b/tests/configs/simple-atomic-mp.py	Fri Feb 25 22:57:52 2011 -0600
@@ -38,6 +38,7 @@
     block_size = 64
     mshrs = 4
     tgts_per_mshr = 8
+    is_top_level = True
 
 # ----------------------
 # Base L2 Cache
diff -r 1d371a84a085 -r ed52ebb95491 tests/configs/simple-timing-mp.py
--- a/tests/configs/simple-timing-mp.py	Fri Feb 25 22:57:40 2011 -0600
+++ b/tests/configs/simple-timing-mp.py	Fri Feb 25 22:57:52 2011 -0600
@@ -38,6 +38,7 @@
     block_size = 64
     mshrs = 4
     tgts_per_mshr = 8
+    is_top_level = True
 
 # ----------------------
 # Base L2 Cache
diff -r 1d371a84a085 -r ed52ebb95491 tests/configs/simple-timing.py
--- a/tests/configs/simple-timing.py	Fri Feb 25 22:57:40 2011 -0600
+++ b/tests/configs/simple-timing.py	Fri Feb 25 22:57:52 2011 -0600
@@ -36,8 +36,12 @@
     mshrs = 10
     tgts_per_mshr = 5
 
+class MyL1Cache(MyCache):
+    is_top_level = True
+
 cpu = TimingSimpleCPU(cpu_id=0)
-cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
+cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
+                              MyL1Cache(size = '256kB'),
                               MyCache(size = '2MB', latency='10ns'))
 system = System(cpu = cpu,
                 physmem = PhysicalMemory(),
diff -r 1d371a84a085 -r ed52ebb95491 tests/configs/tsunami-o3-dual.py
--- a/tests/configs/tsunami-o3-dual.py	Fri Feb 25 22:57:40 2011 -0600
+++ b/tests/configs/tsunami-o3-dual.py	Fri Feb 25 22:57:52 2011 -0600
@@ -41,6 +41,7 @@
     block_size = 64
     mshrs = 4
     tgts_per_mshr = 8
+    is_top_level = True
 
 # ----------------------
 # Base L2 Cache
@@ -65,6 +66,7 @@
     tgts_per_mshr = 12
     addr_range=AddrRange(0, size='8GB')
     forward_snoops = False
+    is_top_level = True
 
 #cpu
 cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(2) ]
diff -r 1d371a84a085 -r ed52ebb95491 tests/configs/tsunami-o3.py
--- a/tests/configs/tsunami-o3.py	Fri Feb 25 22:57:40 2011 -0600
+++ b/tests/configs/tsunami-o3.py	Fri Feb 25 22:57:52 2011 -0600
@@ -41,6 +41,7 @@
     block_size = 64
     mshrs = 4
     tgts_per_mshr = 8
+    is_top_level = True
 
 # ----------------------
 # Base L2 Cache
@@ -65,6 +66,7 @@
     tgts_per_mshr = 12
     addr_range=AddrRange(0, size='8GB')
     forward_snoops = False
+    is_top_level = True
 
 #cpu
 cpu = DerivO3CPU(cpu_id=0)
diff -r 1d371a84a085 -r ed52ebb95491 tests/configs/tsunami-simple-atomic-dual.py
--- a/tests/configs/tsunami-simple-atomic-dual.py	Fri Feb 25 22:57:40 2011 -0600
+++ b/tests/configs/tsunami-simple-atomic-dual.py	Fri Feb 25 22:57:52 2011 -0600
@@ -40,6 +40,7 @@
     block_size = 64
     mshrs = 4
     tgts_per_mshr = 8
+    is_top_level = True
 
 # ----------------------
 # Base L2 Cache
@@ -64,6 +65,7 @@
     tgts_per_mshr = 12
     addr_range=AddrRange(0, size='8GB')
     forward_snoops = False
+    is_top_level = True
 
 #cpu
 cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(2) ]
diff -r 1d371a84a085 -r ed52ebb95491 tests/configs/tsunami-simple-atomic.py
--- a/tests/configs/tsunami-simple-atomic.py	Fri Feb 25 22:57:40 2011 -0600
+++ b/tests/configs/tsunami-simple-atomic.py	Fri Feb 25 22:57:52 2011 -0600
@@ -40,6 +40,7 @@
     block_size = 64
     mshrs = 4
     tgts_per_mshr = 8
+    is_top_level = True
 
 # ----------------------
 # Base L2 Cache
@@ -64,6 +65,7 @@
     tgts_per_mshr = 12
     addr_range=AddrRange(0, size='8GB')
     forward_snoops = False
+    is_top_level = True
 
 #cpu
 cpu = AtomicSimpleCPU(cpu_id=0)
diff -r 1d371a84a085 -r ed52ebb95491 tests/configs/tsunami-simple-timing-dual.py
--- a/tests/configs/tsunami-simple-timing-dual.py	Fri Feb 25 22:57:40 2011 -0600
+++ b/tests/configs/tsunami-simple-timing-dual.py	Fri Feb 25 22:57:52 2011 -0600
@@ -40,6 +40,7 @@
     block_size = 64
     mshrs = 4
     tgts_per_mshr = 8
+    is_top_level = True
 
 # ----------------------
 # Base L2 Cache
@@ -64,6 +65,7 @@
     tgts_per_mshr = 12
     addr_range=AddrRange(0, size='8GB')
     forward_snoops = False
+    is_top_level = True
 
 #cpu
 cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(2) ]
diff -r 1d371a84a085 -r ed52ebb95491 tests/configs/tsunami-simple-timing.py
--- a/tests/configs/tsunami-simple-timing.py	Fri Feb 25 22:57:40 2011 -0600
+++ b/tests/configs/tsunami-simple-timing.py	Fri Feb 25 22:57:52 2011 -0600
@@ -41,6 +41,7 @@
     block_size = 64
     mshrs = 4
     tgts_per_mshr = 8
+    is_top_level = True
 
 # ----------------------
 # Base L2 Cache
@@ -65,6 +66,7 @@
     tgts_per_mshr = 12
     addr_range=AddrRange(0, size='8GB')
     forward_snoops = False
+    is_top_level = True
 
 #cpu
 cpu = TimingSimpleCPU(cpu_id=0)