diff -r f72fd452f04b -r d3158aeb6ca0 src/arch/alpha/predecoder.hh
--- a/src/arch/alpha/predecoder.hh	Fri Feb 25 22:58:03 2011 -0600
+++ b/src/arch/alpha/predecoder.hh	Fri Feb 25 22:58:18 2011 -0600
@@ -76,6 +76,12 @@
         emiIsReady = false;
     }
 
+    void
+    reset(const ExtMachInst &old_emi)
+    {
+        reset();
+    }
+
     // Use this to give data to the predecoder. This should be used
     // when there is control flow.
     void
diff -r f72fd452f04b -r d3158aeb6ca0 src/arch/arm/predecoder.hh
--- a/src/arch/arm/predecoder.hh	Fri Feb 25 22:58:03 2011 -0600
+++ b/src/arch/arm/predecoder.hh	Fri Feb 25 22:58:18 2011 -0600
@@ -83,6 +83,14 @@
             predAddrValid = false;
         }
 
+        void reset(const ExtMachInst &old_emi)
+        {
+            reset();
+            itstate = old_emi.newItstate;
+        }
+
+
+
         Predecoder(ThreadContext * _tc) :
             tc(_tc), data(0)
         {
diff -r f72fd452f04b -r d3158aeb6ca0 src/arch/mips/predecoder.hh
--- a/src/arch/mips/predecoder.hh	Fri Feb 25 22:58:03 2011 -0600
+++ b/src/arch/mips/predecoder.hh	Fri Feb 25 22:58:18 2011 -0600
@@ -75,6 +75,12 @@
         emiIsReady = false;
     }
 
+    void
+    reset(const ExtMachInst &old_emi)
+    {
+        reset();
+    }
+
     //Use this to give data to the predecoder. This should be used
     //when there is control flow.
     void
diff -r f72fd452f04b -r d3158aeb6ca0 src/arch/power/predecoder.hh
--- a/src/arch/power/predecoder.hh	Fri Feb 25 22:58:03 2011 -0600
+++ b/src/arch/power/predecoder.hh	Fri Feb 25 22:58:18 2011 -0600
@@ -82,6 +82,12 @@
         emiIsReady = false;
     }
 
+    void
+    reset(const ExtMachInst &old_emi)
+    {
+        reset();
+    }
+
     // Use this to give data to the predecoder. This should be used
     // when there is control flow.
     void
diff -r f72fd452f04b -r d3158aeb6ca0 src/arch/sparc/predecoder.hh
--- a/src/arch/sparc/predecoder.hh	Fri Feb 25 22:58:03 2011 -0600
+++ b/src/arch/sparc/predecoder.hh	Fri Feb 25 22:58:18 2011 -0600
@@ -68,12 +68,19 @@
     }
 
     void process() {}
+
     void
     reset()
     {
         emiIsReady = false;
     }
 
+    void
+    reset(const ExtMachInst &old_emi)
+    {
+        reset();
+    }
+
     // Use this to give data to the predecoder. This should be used
     // when there is control flow.
     void
diff -r f72fd452f04b -r d3158aeb6ca0 src/arch/x86/predecoder.hh
--- a/src/arch/x86/predecoder.hh	Fri Feb 25 22:58:03 2011 -0600
+++ b/src/arch/x86/predecoder.hh	Fri Feb 25 22:58:18 2011 -0600
@@ -174,6 +174,12 @@
             state = ResetState;
         }
 
+        void
+        reset(const ExtMachInst &old_emi)
+        {
+            reset();
+        }
+
         ThreadContext * getTC()
         {
             return tc;
diff -r f72fd452f04b -r d3158aeb6ca0 src/cpu/o3/cpu.cc
--- a/src/cpu/o3/cpu.cc	Fri Feb 25 22:58:03 2011 -0600
+++ b/src/cpu/o3/cpu.cc	Fri Feb 25 22:58:18 2011 -0600
@@ -808,8 +808,9 @@
     }
 
     // Squash Throughout Pipeline
-    InstSeqNum squash_seq_num = commit.rob->readHeadInst(tid)->seqNum;
-    fetch.squash(0, squash_seq_num, tid);
+    DynInstPtr inst = commit.rob->readHeadInst(tid);
+    InstSeqNum squash_seq_num = inst->seqNum;
+    fetch.squash(0, squash_seq_num, inst, tid);
     decode.squash(tid);
     rename.squash(squash_seq_num, tid);
     iew.squash(tid);
diff -r f72fd452f04b -r d3158aeb6ca0 src/cpu/o3/fetch.hh
--- a/src/cpu/o3/fetch.hh	Fri Feb 25 22:58:03 2011 -0600
+++ b/src/cpu/o3/fetch.hh	Fri Feb 25 22:58:18 2011 -0600
@@ -312,8 +312,8 @@
      * remove any instructions that are not in the ROB. The source of this
      * squash should be the commit stage.
      */
-    void squash(const TheISA::PCState &newPC,
-                const InstSeqNum &seq_num, ThreadID tid);
+    void squash(const TheISA::PCState &newPC, const InstSeqNum &seq_num,
+                DynInstPtr &squashInst, ThreadID tid);
 
     /** Ticks the fetch stage, processing all inputs signals and fetching
      * as many instructions as possible.
diff -r f72fd452f04b -r d3158aeb6ca0 src/cpu/o3/fetch_impl.hh
--- a/src/cpu/o3/fetch_impl.hh	Fri Feb 25 22:58:03 2011 -0600
+++ b/src/cpu/o3/fetch_impl.hh	Fri Feb 25 22:58:18 2011 -0600
@@ -815,11 +815,14 @@
 template <class Impl>
 void
 DefaultFetch<Impl>::squash(const TheISA::PCState &newPC,
-                           const InstSeqNum &seq_num, ThreadID tid)
+                           const InstSeqNum &seq_num, DynInstPtr &squashInst,
+                           ThreadID tid)
 {
     DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n", tid);
 
     doSquash(newPC, tid);
+    if (squashInst)
+        predecoder.reset(squashInst->staticInst->machInst);
 
     // Tell the CPU to remove any instructions that are not in the ROB.
     cpu->removeInstsNotInROB(tid);