diff -r 41441f97c587 -r 801a71272969 src/mem/cache/BaseCache.py
--- a/src/mem/cache/BaseCache.py	Sat Jul 10 02:15:42 2010 +0100
+++ b/src/mem/cache/BaseCache.py	Sat Jul 10 02:15:58 2010 +0100
@@ -76,3 +76,6 @@
     cpu_side = Port("Port on side closer to CPU")
     mem_side = Port("Port on side closer to MEM")
     addr_range = Param.AddrRange(AllMemory, "The address range for the CPU-side port")
+
+    def markAllReady(self):
+        self._ccObject.markAllReady()
diff -r 41441f97c587 -r 801a71272969 src/mem/cache/base.hh
--- a/src/mem/cache/base.hh	Sat Jul 10 02:15:42 2010 +0100
+++ b/src/mem/cache/base.hh	Sat Jul 10 02:15:58 2010 +0100
@@ -538,6 +538,7 @@
         }
     }
 
+    virtual void markAllReady() {};
 };
 
 #endif //__BASE_CACHE_HH__
diff -r 41441f97c587 -r 801a71272969 src/mem/cache/cache.hh
--- a/src/mem/cache/cache.hh	Sat Jul 10 02:15:42 2010 +0100
+++ b/src/mem/cache/cache.hh	Sat Jul 10 02:15:58 2010 +0100
@@ -324,6 +324,9 @@
      * Find next request ready time from among possible sources.
      */
     Tick nextMSHRReadyTime();
+
+    /* Mark all blocks as ready */
+    void markAllReady();
 };
 
 #endif // __CACHE_HH__
diff -r 41441f97c587 -r 801a71272969 src/mem/cache/cache_impl.hh
--- a/src/mem/cache/cache_impl.hh	Sat Jul 10 02:15:42 2010 +0100
+++ b/src/mem/cache/cache_impl.hh	Sat Jul 10 02:15:58 2010 +0100
@@ -1393,6 +1393,14 @@
 }
 
 
+template<class TagStore>
+void
+Cache<TagStore>::markAllReady()
+{
+  tags->markAllReady();
+}
+
+
 ///////////////
 //
 // CpuSidePort
diff -r 41441f97c587 -r 801a71272969 src/mem/cache/tags/base.hh
--- a/src/mem/cache/tags/base.hh	Sat Jul 10 02:15:42 2010 +0100
+++ b/src/mem/cache/tags/base.hh	Sat Jul 10 02:15:58 2010 +0100
@@ -140,6 +140,9 @@
      * exits.
      */
     virtual void cleanupRefs() {}
+
+    /* Mark all blocks as ready */
+    virtual void markAllReady() { assert(false); }
 };
 
 class BaseTagsCallback : public Callback
diff -r 41441f97c587 -r 801a71272969 src/mem/cache/tags/lru.hh
--- a/src/mem/cache/tags/lru.hh	Sat Jul 10 02:15:42 2010 +0100
+++ b/src/mem/cache/tags/lru.hh	Sat Jul 10 02:15:58 2010 +0100
@@ -229,6 +229,9 @@
      * Called at end of simulation to complete average block reference stats.
      */
     virtual void cleanupRefs();
+
+    /* Mark all blocks as ready */
+    void markAllReady();
 };
 
 #endif // __MEM_CACHE_TAGS_LRU_HH__
diff -r 41441f97c587 -r 801a71272969 src/mem/cache/tags/lru.cc
--- a/src/mem/cache/tags/lru.cc	Sat Jul 10 02:15:42 2010 +0100
+++ b/src/mem/cache/tags/lru.cc	Sat Jul 10 02:15:58 2010 +0100
@@ -226,3 +226,11 @@
         }
     }
 }
+
+void
+LRU::markAllReady()
+{
+    for (unsigned i = 0; i < numSets*assoc; ++i) {
+        blks[i].whenReady = curTick;
+    }
+}
diff -r 41441f97c587 -r 801a71272969 src/python/swig/sim_object.i
--- a/src/python/swig/sim_object.i	Sat Jul 10 02:15:42 2010 +0100
+++ b/src/python/swig/sim_object.i	Sat Jul 10 02:15:58 2010 +0100
@@ -54,6 +54,7 @@
     void resume();
     void switchOut();
     void takeOverFrom(BaseCPU *cpu, bool connectMem);
+    void markAllReady();
     void setMaxInsts(uint64_t insts);
     Counter getInstsExecuted(int thread_num);
     SimObject(const SimObjectParams *p);
diff -r 41441f97c587 -r 801a71272969 src/sim/sim_object.hh
--- a/src/sim/sim_object.hh	Sat Jul 10 02:15:42 2010 +0100
+++ b/src/sim/sim_object.hh	Sat Jul 10 02:15:58 2010 +0100
@@ -126,6 +126,7 @@
     virtual void setMemoryMode(State new_mode);
     virtual void switchOut();
     virtual void takeOverFrom(BaseCPU *cpu, bool connectMem);
+    virtual void markAllReady();
     virtual void setMaxInsts(uint64_t insts);
     virtual Counter getInstsExecuted(int thread_num);
 
diff -r 41441f97c587 -r 801a71272969 src/sim/sim_object.cc
--- a/src/sim/sim_object.cc	Sat Jul 10 02:15:42 2010 +0100
+++ b/src/sim/sim_object.cc	Sat Jul 10 02:15:58 2010 +0100
@@ -270,6 +270,12 @@
 }
 
 void
+SimObject::markAllReady()
+{
+    panic("Unimplemented!");
+}
+
+void
 SimObject::setMaxInsts(uint64_t insts)
 {
     panic("Unimplemented!");