diff -r baf4b5f6782e -r 080c7d791d86 src/cpu/testers/rubytest/Check.hh --- a/src/cpu/testers/rubytest/Check.hh Sat Feb 26 21:43:11 2011 -0800 +++ b/src/cpu/testers/rubytest/Check.hh Tue Mar 22 21:29:56 2011 -0500 @@ -58,6 +58,7 @@ void print(std::ostream& out) const; private: + void initiateFlush(); void initiatePrefetch(); void initiateAction(); void initiateCheck(); diff -r baf4b5f6782e -r 080c7d791d86 src/cpu/testers/rubytest/Check.cc --- a/src/cpu/testers/rubytest/Check.cc Sat Feb 26 21:43:11 2011 -0800 +++ b/src/cpu/testers/rubytest/Check.cc Tue Mar 22 21:29:56 2011 -0500 @@ -59,6 +59,11 @@ initiatePrefetch(); // Prefetch from random processor } + // currently MOESI_hammer protocol support flushes + if (true && (random() & 0xff) == 0) { + initiateFlush(); // issue a Flush request from random processor + } + if (m_status == TesterStatus_Idle) { initiateAction(); } else if (m_status == TesterStatus_Ready) { @@ -124,6 +129,37 @@ } void +Check::initiateFlush() +{ + + DPRINTF(RubyTest, "initiating Flush\n"); + + int index = random() % m_num_cpu_sequencers; + RubyTester::CpuPort* port = + safe_cast(m_tester_ptr->getCpuPort(index)); + + Request::Flags flags; + + Request *req = new Request(m_address.getAddress(), CHECK_SIZE, flags, curTick(), + m_pc.getAddress()); + + Packet::Command cmd; + + cmd = MemCmd::FlushReq; + + PacketPtr pkt = new Packet(req, cmd, port->idx); + + // push the subblock onto the sender state. The sequencer will + // update the subblock on the return + pkt->senderState = + new SenderState(m_address, req->getSize(), pkt->senderState); + + if (port->sendTiming(pkt)) { + DPRINTF(RubyTest, "initiating Flush - successful\n"); + } +} + +void Check::initiateAction() { DPRINTF(RubyTest, "initiating Action\n"); diff -r baf4b5f6782e -r 080c7d791d86 src/mem/packet.hh --- a/src/mem/packet.hh Sat Feb 26 21:43:11 2011 -0800 +++ b/src/mem/packet.hh Tue Mar 22 21:29:56 2011 -0500 @@ -105,6 +105,7 @@ BadAddressError, // memory address invalid // Fake simulator-only commands PrintReq, // Print state matching address + FlushReq, //request for a cache flush NUM_MEM_CMDS }; @@ -129,6 +130,7 @@ HasData, //!< There is an associated payload IsError, //!< Error response IsPrint, //!< Print state matching address (for debugging) + IsFlush, //!< Flush the address from caches NUM_COMMAND_ATTRIBUTES }; @@ -175,6 +177,7 @@ bool isLLSC() const { return testCmdAttrib(IsLlsc); } bool isError() const { return testCmdAttrib(IsError); } bool isPrint() const { return testCmdAttrib(IsPrint); } + bool isFlush() const { return testCmdAttrib(IsFlush); } const Command responseCommand() const @@ -411,6 +414,8 @@ bool isLLSC() const { return cmd.isLLSC(); } bool isError() const { return cmd.isError(); } bool isPrint() const { return cmd.isPrint(); } + bool isFlush() const { return cmd.isFlush(); } + // Snoop flags void assertMemInhibit() { flags.set(MEM_INHIBIT); } diff -r baf4b5f6782e -r 080c7d791d86 src/mem/packet.cc --- a/src/mem/packet.cc Sat Feb 26 21:43:11 2011 -0800 +++ b/src/mem/packet.cc Tue Mar 22 21:29:56 2011 -0500 @@ -148,7 +148,10 @@ /* BadAddressError -- memory address invalid */ { SET2(IsResponse, IsError), InvalidCmd, "BadAddressError" }, /* PrintReq */ - { SET2(IsRequest, IsPrint), InvalidCmd, "PrintReq" } + { SET2(IsRequest, IsPrint), InvalidCmd, "PrintReq" }, + /* Flush Request */ + { SET3(IsRequest, IsFlush, NeedsExclusive), + InvalidCmd, "FlushReq" } }; bool diff -r baf4b5f6782e -r 080c7d791d86 src/mem/protocol/MOESI_hammer-cache.sm --- a/src/mem/protocol/MOESI_hammer-cache.sm Sat Feb 26 21:43:11 2011 -0800 +++ b/src/mem/protocol/MOESI_hammer-cache.sm Tue Mar 22 21:29:56 2011 -0500 @@ -79,6 +79,15 @@ OT, AccessPermission:Busy, "OT", desc="O block transferring to L1"; MT, AccessPermission:Busy, "MT", desc="M block transferring to L1"; MMT, AccessPermission:Busy, "MMT", desc="MM block transferring to L1"; + + //Transition States Related to Flushing + MI_F, AccessPermission:Busy, "MI_F", desc="Issued PutX due to a Flush, waiting for ack"; + MM_F, AccessPermission:Busy, "MM_F", desc="Issued GETF due to a Flush, waiting for ack"; + IM_F, AccessPermission:Busy, "IM_F", desc="Issued GetX due to a Flush"; + ISM_F, AccessPermission:Read_Only, "ISM_F", desc="Issued GetX, received data, waiting for all acks"; + SM_F, AccessPermission:Read_Only, "SM_F", desc="Issued GetX, we still have an old copy of the line"; + OM_F, AccessPermission:Read_Only, "OM_F", desc="Issued GetX, received data"; + MM_WF, AccessPermission:Busy, "MM_WF", desc="Issued GetX, received exclusive data"; } // EVENTS @@ -113,6 +122,10 @@ // Triggers All_acks, desc="Received all required data and message acks"; All_acks_no_sharers, desc="Received all acks and no other processor has a shared copy"; + + // For Flush + Flush_line, desc="flush the cache line from all caches"; + Block_Ack, desc="the directory is blocked and ready for the flush"; } // TYPES @@ -219,6 +232,8 @@ return Event:Ifetch; } else if ((type == CacheRequestType:ST) || (type == CacheRequestType:ATOMIC)) { return Event:Store; + } else if ((type == CacheRequestType:FLUSH)) { + return Event:Flush_line; } else { error("Invalid CacheRequestType"); } @@ -316,7 +331,7 @@ Entry cache_entry := getCacheEntry(in_msg.Address); TBE tbe := TBEs[in_msg.Address]; - if (in_msg.Type == CoherenceRequestType:GETX) { + if ((in_msg.Type == CoherenceRequestType:GETX) || (in_msg.Type == CoherenceRequestType:GETF)) { trigger(Event:Other_GETX, in_msg.Address, cache_entry, tbe); } else if (in_msg.Type == CoherenceRequestType:MERGED_GETS) { trigger(Event:Merged_GETS, in_msg.Address, cache_entry, tbe); @@ -340,6 +355,8 @@ trigger(Event:Writeback_Ack, in_msg.Address, cache_entry, tbe); } else if (in_msg.Type == CoherenceRequestType:WB_NACK) { trigger(Event:Writeback_Nack, in_msg.Address, cache_entry, tbe); + } else if (in_msg.Type == CoherenceRequestType:BLOCK_ACK) { + trigger(Event:Block_Ack, in_msg.Address, cache_entry, tbe); } else { error("Unexpected message"); } @@ -502,6 +519,21 @@ } } + + action(bf_issueGETF, "bf", desc="Issue GETF") { + enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) { + assert(is_valid(tbe)); + out_msg.Address := address; + out_msg.Type := CoherenceRequestType:GETF; + out_msg.Requestor := machineID; + out_msg.Destination.add(map_Address_to_Directory(address)); + out_msg.MessageSize := MessageSizeType:Request_Control; + out_msg.InitialRequestTime := get_time(); + tbe.NumPendingMsgs := machineCount(MachineType:L1Cache); // One from each other cache (n-1) plus the memory (+1) + } + } + + action(c_sendExclusiveData, "c", desc="Send exclusive data from cache to requestor") { peek(forwardToCache_in, RequestMsg) { enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) { @@ -525,6 +557,31 @@ } } + action(ct_sendExclusiveDataFromTBE, "ct", desc="Send exclusive data from tbe to requestor") { + peek(forwardToCache_in, RequestMsg) { + enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) { + assert(is_valid(tbe)); + out_msg.Address := address; + out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE; + out_msg.Sender := machineID; + out_msg.Destination.add(in_msg.Requestor); + out_msg.DataBlk := tbe.DataBlk; + out_msg.Dirty := tbe.Dirty; + if (in_msg.DirectedProbe) { + out_msg.Acks := machineCount(MachineType:L1Cache); + } else { + out_msg.Acks := 2; + } + out_msg.SilentAcks := in_msg.SilentAcks; + out_msg.MessageSize := MessageSizeType:Response_Data; + out_msg.InitialRequestTime := in_msg.InitialRequestTime; + out_msg.ForwardRequestTime := in_msg.ForwardRequestTime; + } + } + } + + + action(d_issuePUT, "d", desc="Issue PUT") { enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) { out_msg.Address := address; @@ -535,6 +592,16 @@ } } + action(df_issuePUTF, "df", desc="Issue PUTF") { + enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) { + out_msg.Address := address; + out_msg.Type := CoherenceRequestType:PUTF; + out_msg.Requestor := machineID; + out_msg.Destination.add(map_Address_to_Directory(address)); + out_msg.MessageSize := MessageSizeType:Writeback_Control; + } + } + action(e_sendData, "e", desc="Send data from cache to requestor") { peek(forwardToCache_in, RequestMsg) { enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) { @@ -581,7 +648,33 @@ } } } - + + action(et_sendDataSharedFromTBE, "\et", desc="Send data from TBE to requestor, keep a shared copy") { + peek(forwardToCache_in, RequestMsg) { + enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) { + assert(is_valid(tbe)); + out_msg.Address := address; + out_msg.Type := CoherenceResponseType:DATA_SHARED; + out_msg.Sender := machineID; + out_msg.Destination.add(in_msg.Requestor); + out_msg.DataBlk := tbe.DataBlk; + out_msg.Dirty := tbe.Dirty; + DPRINTF(RubySlicc, "%s\n", out_msg.DataBlk); + if (in_msg.DirectedProbe) { + out_msg.Acks := machineCount(MachineType:L1Cache); + } else { + out_msg.Acks := 2; + } + out_msg.SilentAcks := in_msg.SilentAcks; + out_msg.MessageSize := MessageSizeType:Response_Data; + out_msg.InitialRequestTime := in_msg.InitialRequestTime; + out_msg.ForwardRequestTime := in_msg.ForwardRequestTime; + } + } + } + + + action(em_sendDataSharedMultiple, "em", desc="Send data from cache to all requestors") { peek(forwardToCache_in, RequestMsg) { enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) { @@ -601,7 +694,28 @@ } } } - + + action(emt_sendDataSharedMultipleFromTBE, "emt", desc="Send data from tbe to all requestors") { + peek(forwardToCache_in, RequestMsg) { + enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) { + assert(is_valid(tbe)); + out_msg.Address := address; + out_msg.Type := CoherenceResponseType:DATA_SHARED; + out_msg.Sender := machineID; + out_msg.Destination := in_msg.MergedRequestors; + out_msg.DataBlk := tbe.DataBlk; + out_msg.Dirty := tbe.Dirty; + DPRINTF(RubySlicc, "%s\n", out_msg.DataBlk); + out_msg.Acks := machineCount(MachineType:L1Cache); + out_msg.SilentAcks := in_msg.SilentAcks; + out_msg.MessageSize := MessageSizeType:Response_Data; + out_msg.InitialRequestTime := in_msg.InitialRequestTime; + out_msg.ForwardRequestTime := in_msg.ForwardRequestTime; + } + } + } + + action(f_sendAck, "f", desc="Send ack from cache to requestor") { peek(forwardToCache_in, RequestMsg) { enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) { @@ -745,6 +859,16 @@ tbe.Sharers := false; } + + action(it_allocateTBE, "it", desc="Allocate TBE") { + check_allocate(TBEs); + TBEs.allocate(address); + set_tbe(TBEs[address]); + tbe.Dirty := false; + tbe.Sharers := false; + } + + action(j_popTriggerQueue, "j", desc="Pop trigger queue.") { triggerQueue_in.dequeue(); } @@ -953,6 +1077,15 @@ } } + action(uf_writeDataToCacheTBE, "uf", desc="Write data to TBE") { + peek(responseToCache_in, ResponseMsg) { + assert(is_valid(tbe)); + tbe.DataBlk := in_msg.DataBlk; + tbe.Dirty := in_msg.Dirty; + } + } + + action(v_writeDataToCacheVerify, "v", desc="Write data to cache, assert it was same as before") { peek(responseToCache_in, ResponseMsg) { assert(is_valid(cache_entry)); @@ -963,6 +1096,17 @@ cache_entry.Dirty := in_msg.Dirty || cache_entry.Dirty; } } + + action(vt_writeDataToTBEVerify, "vt", desc="Write data to TBE, assert it was same as before") { + peek(responseToCache_in, ResponseMsg) { + assert(is_valid(tbe)); + DPRINTF(RubySlicc, "Cached Data Block: %s, Msg Data Block: %s\n", + tbe.DataBlk, in_msg.DataBlk); + assert(tbe.DataBlk == in_msg.DataBlk); + tbe.DataBlk := in_msg.DataBlk; + tbe.Dirty := in_msg.Dirty || tbe.Dirty; + } + } action(gg_deallocateL1CacheBlock, "\g", desc="Deallocate cache block. Sets the cache to invalid, allowing a replacement in parallel with a fetch.") { if (L1DcacheMemory.isTagPresent(address)) { @@ -1024,23 +1168,36 @@ //***************************************************** // Transitions for Load/Store/L2_Replacement from transient states - transition({IM, SM, ISM, OM, IS, SS, OI, MI, II, IT, ST, OT, MT, MMT}, {Store, L2_Replacement}) { + transition({IM, IM_F, MM_WF, SM, SM_F, ISM, ISM_F, OM, OM_F, IS, SS, OI, MI, II, IT, ST, OT, MT, MMT}, {Store, L2_Replacement}) { zz_stallAndWaitMandatoryQueue; } - transition({M_W, MM_W}, {L2_Replacement}) { + transition({IM, IM_F, MM_WF, SM, SM_F, ISM, ISM_F, OM, OM_F, IS, SS, OI, MI, II}, {Flush_line}) { zz_stallAndWaitMandatoryQueue; } - transition({IM, IS, OI, MI, II, IT, ST, OT, MT, MMT}, {Load, Ifetch}) { + transition({M_W, MM_W}, {L2_Replacement, Flush_line}) { zz_stallAndWaitMandatoryQueue; } - transition({IM, SM, ISM, OM, IS, SS, MM_W, M_W, OI, MI, II, IT, ST, OT, MT, MMT}, L1_to_L2) { + transition({IM, IS, OI, MI, II, IT, ST, OT, MT, MMT, MI_F, MM_F, OM_F, IM_F, ISM_F, SM_F, MM_WF}, {Load, Ifetch}) { zz_stallAndWaitMandatoryQueue; } - transition({IT, ST, OT, MT, MMT}, {Other_GETX, NC_DMA_GETS, Other_GETS, Merged_GETS, Other_GETS_No_Mig, Invalidate}) { + transition({IM, IM_F, SM, SM_F, ISM, ISM_F, OM, OM_F, IS, SS, MM_W, MM_WF, M_W, OI, MI, II, IT, ST, OT, MT, MMT, MI_F, MM_F}, L1_to_L2) { + zz_stallAndWaitMandatoryQueue; + } + + transition({MI_F, MM_F}, {Store}) { + zz_stallAndWaitMandatoryQueue; + } + + transition({MM_F, MI_F}, {Flush_line}) { + zz_stallAndWaitMandatoryQueue; + } + + + transition({IT, ST, OT, MT, MMT}, {Other_GETX, NC_DMA_GETS, Other_GETS, Merged_GETS, Other_GETS_No_Mig, Invalidate, Flush_line}) { // stall } @@ -1213,6 +1370,13 @@ uu_profileMiss; k_popMandatoryQueue; } + + transition(I, Flush_line, IM_F) { + it_allocateTBE; + bf_issueGETF; + uu_profileMiss; + k_popMandatoryQueue; + } transition(I, L2_Replacement) { rr_deallocateL2CacheBlock; @@ -1237,6 +1401,14 @@ k_popMandatoryQueue; } + transition(S, Flush_line, SM_F) { + i_allocateTBE; + bf_issueGETF; + uu_profileMiss; + gg_deallocateL1CacheBlock; + k_popMandatoryQueue; + } + transition(S, L2_Replacement, I) { rr_deallocateL2CacheBlock; ka_wakeUpAllDependents; @@ -1266,6 +1438,15 @@ k_popMandatoryQueue; } + transition(O, Flush_line, OM_F) { + i_allocateTBE; + bf_issueGETF; + p_decrementNumberOfMessagesByOne; + uu_profileMiss; + gg_deallocateL1CacheBlock; + k_popMandatoryQueue; + } + transition(O, L2_Replacement, OI) { i_allocateTBE; d_issuePUT; @@ -1299,6 +1480,21 @@ k_popMandatoryQueue; } + + transition({MM, M}, Flush_line, MM_F) { + i_allocateTBE; + bf_issueGETF; + p_decrementNumberOfMessagesByOne; + gg_deallocateL1CacheBlock; + k_popMandatoryQueue; + } + + transition(MM_F, Block_Ack, MI_F) { + df_issuePUTF; + l_popForwardQueue; + kd_wakeUpDependents; + } + transition(MM, L2_Replacement, MI) { i_allocateTBE; d_issuePUT; @@ -1331,6 +1527,7 @@ l_popForwardQueue; } + // Transitions from Dirty Exclusive transition(M, {Load, Ifetch}) { h_load_hit; @@ -1371,12 +1568,12 @@ // Transitions from IM - transition(IM, {Other_GETX, NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig, Invalidate}) { + transition({IM, IM_F}, {Other_GETX, NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig, Invalidate}) { f_sendAck; l_popForwardQueue; } - transition(IM, Ack) { + transition({IM, IM_F, MM_F}, Ack) { m_decrementNumberOfMessages; o_checkForCompletion; n_popResponseQueue; @@ -1389,6 +1586,14 @@ n_popResponseQueue; } + transition(IM_F, Data, ISM_F) { + uf_writeDataToCacheTBE; + m_decrementNumberOfMessages; + o_checkForCompletion; + n_popResponseQueue; + } + + transition(IM, Exclusive_Data, MM_W) { u_writeDataToCache; m_decrementNumberOfMessages; @@ -1398,8 +1603,16 @@ kd_wakeUpDependents; } + transition(IM_F, Exclusive_Data, MM_WF) { + uf_writeDataToCacheTBE; + m_decrementNumberOfMessages; + o_checkForCompletion; + n_popResponseQueue; + } + + // Transitions from SM - transition(SM, {NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig}) { + transition({SM, SM_F}, {NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig}) { ff_sendAckShared; l_popForwardQueue; } @@ -1409,7 +1622,12 @@ l_popForwardQueue; } - transition(SM, Ack) { + transition(SM_F, {Other_GETX, Invalidate}, IM_F) { + f_sendAck; + l_popForwardQueue; + } + + transition({SM, SM_F}, Ack) { m_decrementNumberOfMessages; o_checkForCompletion; n_popResponseQueue; @@ -1422,8 +1640,15 @@ n_popResponseQueue; } + transition(SM_F, {Data, Exclusive_Data}, ISM_F) { + vt_writeDataToTBEVerify; + m_decrementNumberOfMessages; + o_checkForCompletion; + n_popResponseQueue; + } + // Transitions from ISM - transition(ISM, Ack) { + transition({ISM, ISM_F}, Ack) { m_decrementNumberOfMessages; o_checkForCompletion; n_popResponseQueue; @@ -1437,6 +1662,14 @@ kd_wakeUpDependents; } + + + transition(ISM_F, All_acks_no_sharers, MI_F) { + df_issuePUTF; + j_popTriggerQueue; + kd_wakeUpDependents; + } + // Transitions from OM transition(OM, {Other_GETX, Invalidate}, IM) { @@ -1445,6 +1678,13 @@ l_popForwardQueue; } + transition(OM_F, {Other_GETX, Invalidate}, IM_F) { + q_sendDataFromTBEToCache; + pp_incrementNumberOfMessagesByOne; + l_popForwardQueue; + } + + transition(OM, {NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig}) { ee_sendDataShared; l_popForwardQueue; @@ -1455,7 +1695,18 @@ l_popForwardQueue; } - transition(OM, Ack) { + transition(OM_F, {NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig}) { + et_sendDataSharedFromTBE; + l_popForwardQueue; + } + + transition(OM_F, Merged_GETS) { + emt_sendDataSharedMultipleFromTBE; + l_popForwardQueue; + } + + + transition({OM, OM_F}, Ack) { m_decrementNumberOfMessages; o_checkForCompletion; n_popResponseQueue; @@ -1469,6 +1720,11 @@ kd_wakeUpDependents; } + transition({MM_F, OM_F}, {All_acks, All_acks_no_sharers}, MI_F) { + df_issuePUTF; + j_popTriggerQueue; + kd_wakeUpDependents; + } // Transitions from IS transition(IS, {Other_GETX, NC_DMA_GETS, Other_GETS, Other_GETS_No_Mig, Invalidate}) { @@ -1556,7 +1812,7 @@ k_popMandatoryQueue; } - transition(MM_W, Ack) { + transition({MM_W,MM_WF}, Ack) { m_decrementNumberOfMessages; o_checkForCompletion; n_popResponseQueue; @@ -1569,6 +1825,13 @@ kd_wakeUpDependents; } + transition(MM_WF, All_acks_no_sharers, MI_F) { + df_issuePUTF; + j_popTriggerQueue; + kd_wakeUpDependents; + } + + // Transitions from M_W transition(M_W, Store, MM_W) { @@ -1613,6 +1876,13 @@ kd_wakeUpDependents; } + transition(MI_F, Writeback_Ack, I) { + t_sendExclusiveDataFromTBEToMemory; + s_deallocateTBE; + l_popForwardQueue; + kd_wakeUpDependents; + } + transition(OI, Writeback_Ack, I) { qq_sendDataFromTBEToMemory; s_deallocateTBE; @@ -1638,4 +1908,34 @@ l_popForwardQueue; kd_wakeUpDependents; } + + + transition(MM_F, {Other_GETX, Invalidate}, IM_F) { + ct_sendExclusiveDataFromTBE; + pp_incrementNumberOfMessagesByOne; + l_popForwardQueue; + } + + transition(MM_F, Other_GETS, IM_F) { + ct_sendExclusiveDataFromTBE; + pp_incrementNumberOfMessagesByOne; + l_popForwardQueue; + } + + transition(MM_F, NC_DMA_GETS) { + ct_sendExclusiveDataFromTBE; + l_popForwardQueue; + } + + transition(MM_F, Other_GETS_No_Mig, OM_F) { + et_sendDataSharedFromTBE; + l_popForwardQueue; + } + + transition(MM_F, Merged_GETS, OM_F) { + emt_sendDataSharedMultipleFromTBE; + l_popForwardQueue; + } + + } diff -r baf4b5f6782e -r 080c7d791d86 src/mem/protocol/MOESI_hammer-dir.sm --- a/src/mem/protocol/MOESI_hammer-dir.sm Sat Feb 26 21:43:11 2011 -0800 +++ b/src/mem/protocol/MOESI_hammer-dir.sm Tue Mar 22 21:29:56 2011 -0500 @@ -88,6 +88,9 @@ WB, AccessPermission:Invalid, desc="Blocked on a writeback"; WB_O_W, AccessPermission:Invalid, desc="Blocked on memory write, will go to O"; WB_E_W, AccessPermission:Invalid, desc="Blocked on memory write, will go to E"; + + NO_F, AccessPermission:Invalid, desc="Blocked on a flush"; + NO_F_W, AccessPermission:Invalid, desc="Not Owner, Blocked, waiting for Dram"; } // Events @@ -126,6 +129,8 @@ All_acks_and_owner_data, desc="Received shared data and message acks"; All_acks_and_data_no_sharers, desc="Received all acks and no other processor has a shared copy"; All_Unblocks, desc="Received all unblocks for a merged gets request"; + GETF, desc="A GETF arrives"; + PUTF, desc="A PUTF arrives"; } // TYPES @@ -231,6 +236,8 @@ return Event:GETS; } else if (type == CoherenceRequestType:GETX) { return Event:GETX; + } else if (type == CoherenceRequestType:GETF) { + return Event:GETF; } else { error("Invalid CoherenceRequestType"); } @@ -353,6 +360,8 @@ TBE tbe := TBEs[in_msg.Address]; if (in_msg.Type == CoherenceRequestType:PUT) { trigger(Event:PUT, in_msg.Address, pf_entry, tbe); + } else if (in_msg.Type == CoherenceRequestType:PUTF) { + trigger(Event:PUTF, in_msg.Address, pf_entry, tbe); } else { if (probe_filter_enabled || full_bit_dir_enabled) { if (is_valid(pf_entry)) { @@ -451,6 +460,21 @@ } } + + action(oc_sendBlockAck, "oc", desc="Send block ack to the owner") { + peek(requestQueue_in, RequestMsg) { + if ((probe_filter_enabled || full_bit_dir_enabled) && (in_msg.Requestor == cache_entry.Owner)) { + enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) { + out_msg.Address := address; + out_msg.Type := CoherenceRequestType:BLOCK_ACK; + out_msg.Requestor := in_msg.Requestor; + out_msg.Destination.add(in_msg.Requestor); + out_msg.MessageSize := MessageSizeType:Writeback_Control; + } + } + } + } + action(b_sendWriteBackNack, "b", desc="Send writeback nack to requestor") { peek(requestQueue_in, RequestMsg) { enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) { @@ -963,6 +987,45 @@ } } + + action(nofc_forwardRequestConditionalOwner, "nofc", desc="Forward request to one or more nodes if the requestor is not the owner") { + assert(machineCount(MachineType:L1Cache) > 1); + + if (probe_filter_enabled || full_bit_dir_enabled) { + peek(requestQueue_in, RequestMsg) { + if (in_msg.Requestor != cache_entry.Owner) { + enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) { + assert(is_valid(cache_entry)); + out_msg.Address := address; + out_msg.Type := in_msg.Type; + out_msg.Requestor := in_msg.Requestor; + out_msg.Destination.add(cache_entry.Owner); + out_msg.MessageSize := MessageSizeType:Request_Control; + out_msg.DirectedProbe := true; + out_msg.InitialRequestTime := in_msg.InitialRequestTime; + out_msg.ForwardRequestTime := get_time(); + } + } + } + } else { + peek(requestQueue_in, RequestMsg) { + enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) { + out_msg.Address := address; + out_msg.Type := in_msg.Type; + out_msg.Requestor := in_msg.Requestor; + out_msg.Destination.broadcast(MachineType:L1Cache); // Send to all L1 caches + out_msg.Destination.remove(in_msg.Requestor); // Don't include the original requestor + out_msg.MessageSize := MessageSizeType:Broadcast_Control; + out_msg.InitialRequestTime := in_msg.InitialRequestTime; + out_msg.ForwardRequestTime := get_time(); + } + } + } + + } + + + action(f_forwardWriteFromDma, "fw", desc="Forward requests") { assert(is_valid(tbe)); if (tbe.NumPendingMsgs > 0) { @@ -1182,6 +1245,17 @@ i_popIncomingRequestQueue; } + transition(E, GETF, NO_F_W) { + pfa_probeFilterAllocate; + v_allocateTBE; + rx_recordExclusiveInTBE; + saa_setAcksToAllIfPF; + qf_queueMemoryFetchRequest; + fn_forwardRequestIfNecessary; + i_popIncomingRequestQueue; + } + + transition(E, GETS, NO_B_W) { pfa_probeFilterAllocate; v_allocateTBE; @@ -1220,6 +1294,18 @@ i_popIncomingRequestQueue; } + transition(O, GETF, NO_F_W) { + r_setMRU; + v_allocateTBE; + r_recordDataInTBE; + sa_setAcksToOne; + qf_queueMemoryFetchRequest; + fb_forwardRequestBcast; + cs_clearSharers; + i_popIncomingRequestQueue; + } + + // This transition is dumb, if a shared copy exists on-chip, then that should // provide data, not slow off-chip dram. The problem is that the current // caches don't provide data in S state @@ -1283,6 +1369,14 @@ i_popIncomingRequestQueue; } + transition(NX, GETF, NO_F) { + r_setMRU; + fb_forwardRequestBcast; + cs_clearSharers; + i_popIncomingRequestQueue; + } + + // Transitions out of NO state transition(NO, GETX, NO_B) { r_setMRU; @@ -1292,6 +1386,16 @@ i_popIncomingRequestQueue; } + transition(NO, GETF, NO_F) { + r_setMRU; + //ano_assertNotOwner; + nofc_forwardRequestConditionalOwner; //forward request if the requester is not the owner + cs_clearSharers; + oc_sendBlockAck; // send ack if the owner + i_popIncomingRequestQueue; + } + + transition(S, GETX, NO_B) { r_setMRU; fb_forwardRequestBcast; @@ -1299,6 +1403,14 @@ i_popIncomingRequestQueue; } + transition(S, GETF, NO_F) { + r_setMRU; + fb_forwardRequestBcast; + cs_clearSharers; + i_popIncomingRequestQueue; + } + + transition(S, GETS, NO_B) { r_setMRU; ano_assertNotOwner; @@ -1345,12 +1457,16 @@ // Blocked transient states transition({NO_B_X, O_B, NO_DR_B_W, NO_DW_B_W, NO_B_W, NO_DR_B_D, NO_DR_B, O_DR_B, O_B_W, O_DR_B_W, NO_DW_W, NO_B_S_W, - NO_W, O_W, WB, WB_E_W, WB_O_W, O_R, S_R, NO_R}, - {GETS, GETX, PUT, Pf_Replacement}) { + NO_W, O_W, WB, WB_E_W, WB_O_W, O_R, S_R, NO_R, NO_F_W}, + {GETS, GETX, GETF, PUT, Pf_Replacement}) { + z_stallAndWaitRequest; + } + + transition(NO_F, {GETS, GETX, GETF, PUT, Pf_Replacement}){ z_stallAndWaitRequest; } - transition(NO_B, GETX, NO_B_X) { + transition(NO_B, {GETX, GETF}, NO_B_X) { z_stallAndWaitRequest; } @@ -1358,13 +1474,13 @@ z_stallAndWaitRequest; } - transition(NO_B_S, {GETX, PUT, Pf_Replacement}) { + transition(NO_B_S, {GETX, GETF, PUT, Pf_Replacement}) { z_stallAndWaitRequest; } transition({NO_B_X, NO_B, NO_B_S, O_B, NO_DR_B_W, NO_DW_B_W, NO_B_W, NO_DR_B_D, NO_DR_B, O_DR_B, O_B_W, O_DR_B_W, NO_DW_W, NO_B_S_W, - NO_W, O_W, WB, WB_E_W, WB_O_W, O_R, S_R, NO_R}, + NO_W, O_W, WB, WB_E_W, WB_O_W, O_R, S_R, NO_R, NO_F_W}, {DMA_READ, DMA_WRITE}) { zd_stallAndWaitDMARequest; } @@ -1441,6 +1557,13 @@ l_popMemQueue; } + transition(NO_F_W, Memory_Data, NO_F) { + d_sendData; + w_deallocateTBE; + l_popMemQueue; + } + + transition(NO_DR_B_W, Memory_Data, NO_DR_B) { r_recordMemoryData; o_checkForCompletion; @@ -1735,4 +1858,18 @@ k_wakeUpDependents; j_popIncomingUnblockQueue; } + + transition(NO_F, PUTF, WB) { + a_sendWriteBackAck; + i_popIncomingRequestQueue; + } + + + //possible race between GETF and UnblockM -- not sure needed any more? + transition(NO_F, UnblockM) { + us_updateSharerIfFBD; + uo_updateOwnerIfPf; + j_popIncomingUnblockQueue; + } + } diff -r baf4b5f6782e -r 080c7d791d86 src/mem/protocol/MOESI_hammer-msg.sm --- a/src/mem/protocol/MOESI_hammer-msg.sm Sat Feb 26 21:43:11 2011 -0800 +++ b/src/mem/protocol/MOESI_hammer-msg.sm Tue Mar 22 21:29:56 2011 -0500 @@ -37,6 +37,9 @@ PUT, desc="Put Ownership"; WB_ACK, desc="Writeback ack"; WB_NACK, desc="Writeback neg. ack"; + PUTF, desc="PUT on a Flush"; + GETF, desc="Issue exclusive for Flushing"; + BLOCK_ACK, desc="Dir Block ack"; INV, desc="Invalidate"; } diff -r baf4b5f6782e -r 080c7d791d86 src/mem/protocol/RubySlicc_Exports.sm --- a/src/mem/protocol/RubySlicc_Exports.sm Sat Feb 26 21:43:11 2011 -0800 +++ b/src/mem/protocol/RubySlicc_Exports.sm Tue Mar 22 21:29:56 2011 -0500 @@ -113,6 +113,7 @@ REPLACEMENT, desc="Replacement"; COMMIT, desc="Commit version"; NULL, desc="Invalid request type"; + FLUSH, desc="Flush request type"; } enumeration(SequencerRequestType, desc="...", default="SequencerRequestType_NULL") { diff -r baf4b5f6782e -r 080c7d791d86 src/mem/protocol/RubySlicc_Types.sm --- a/src/mem/protocol/RubySlicc_Types.sm Sat Feb 26 21:43:11 2011 -0800 +++ b/src/mem/protocol/RubySlicc_Types.sm Tue Mar 22 21:29:56 2011 -0500 @@ -105,6 +105,9 @@ void writeCallback(Address, DataBlock); void writeCallback(Address, GenericMachineType, DataBlock); void writeCallback(Address, GenericMachineType, DataBlock, Time, Time, Time); + void flushCallback(Address, DataBlock); + void flushCallback(Address, GenericMachineType, DataBlock); + void flushCallback(Address, GenericMachineType, DataBlock, Time, Time, Time); void checkCoherence(Address); void profileNack(Address, int, int, uint64); } diff -r baf4b5f6782e -r 080c7d791d86 src/mem/ruby/slicc_interface/RubyRequest.hh --- a/src/mem/ruby/slicc_interface/RubyRequest.hh Sat Feb 26 21:43:11 2011 -0800 +++ b/src/mem/ruby/slicc_interface/RubyRequest.hh Tue Mar 22 21:29:56 2011 -0500 @@ -50,6 +50,7 @@ RubyRequestType_RMW_Write, RubyRequestType_Locked_RMW_Read, RubyRequestType_Locked_RMW_Write, + RubyRequestType_FLUSH, RubyRequestType_NUM }; diff -r baf4b5f6782e -r 080c7d791d86 src/mem/ruby/slicc_interface/RubyRequest.cc --- a/src/mem/ruby/slicc_interface/RubyRequest.cc Sat Feb 26 21:43:11 2011 -0800 +++ b/src/mem/ruby/slicc_interface/RubyRequest.cc Tue Mar 22 21:29:56 2011 -0500 @@ -26,6 +26,8 @@ return "Locked_RMW_Read"; case RubyRequestType_Locked_RMW_Write: return "Locked_RMW_Write"; + case RubyRequestType_FLUSH: + return "FLUSH"; case RubyRequestType_NULL: default: assert(0); @@ -42,6 +44,8 @@ return RubyRequestType_LD; else if (str == "ST") return RubyRequestType_ST; + else if (str == "FLUSH") + return RubyRequestType_FLUSH; else if (str == "Locked_Read") return RubyRequestType_Load_Linked; else if (str == "Locked_Write") diff -r baf4b5f6782e -r 080c7d791d86 src/mem/ruby/system/DMASequencer.cc --- a/src/mem/ruby/system/DMASequencer.cc Sat Feb 26 21:43:11 2011 -0800 +++ b/src/mem/ruby/system/DMASequencer.cc Tue Mar 22 21:29:56 2011 -0500 @@ -72,6 +72,7 @@ case RubyRequestType_RMW_Write: case RubyRequestType_Locked_RMW_Read: case RubyRequestType_Locked_RMW_Write: + case RubyRequestType_FLUSH: case RubyRequestType_NUM: panic("DMASequencer::makeRequest does not support RubyRequestType"); return RequestStatus_NULL; diff -r baf4b5f6782e -r 080c7d791d86 src/mem/ruby/system/RubyPort.cc --- a/src/mem/ruby/system/RubyPort.cc Sat Feb 26 21:43:11 2011 -0800 +++ b/src/mem/ruby/system/RubyPort.cc Tue Mar 22 21:29:56 2011 -0500 @@ -244,6 +244,8 @@ // Note: M5 packets do not differentiate ST from RMW_Write // type = RubyRequestType_ST; + } else if (pkt->isFlush()) { + type = RubyRequestType_FLUSH; } else { panic("Unsupported ruby packet type\n"); } @@ -351,6 +353,11 @@ pkt->convertLlToRead(); } } + + if (pkt->isFlush()) { + accessPhysMem = false; + } + DPRINTF(MemoryAccess, "Hit callback needs response %d\n", needsResponse); if (accessPhysMem) { diff -r baf4b5f6782e -r 080c7d791d86 src/mem/ruby/system/Sequencer.cc --- a/src/mem/ruby/system/Sequencer.cc Sat Feb 26 21:43:11 2011 -0800 +++ b/src/mem/ruby/system/Sequencer.cc Tue Mar 22 21:29:56 2011 -0500 @@ -265,7 +265,9 @@ g_system_ptr->getProfiler()->sequencerRequests(m_outstanding_count); - total_outstanding = m_writeRequestTable.size() + m_readRequestTable.size(); + total_outstanding = m_writeRequestTable.size() + + m_readRequestTable.size(); + assert(m_outstanding_count == total_outstanding); return false; @@ -506,7 +508,8 @@ (type == RubyRequestType_IFETCH) || (type == RubyRequestType_RMW_Read) || (type == RubyRequestType_Locked_RMW_Read) || - (type == RubyRequestType_Load_Linked)) { + (type == RubyRequestType_Load_Linked) + ) { memcpy(ruby_request.data, data.getData(request_address.getOffset(), ruby_request.len), ruby_request.len); @@ -545,6 +548,7 @@ !!m_writeRequestTable.count(line_address(Address(request.paddr))); bool is_outstanding_load = !!m_readRequestTable.count(line_address(Address(request.paddr))); + if (is_outstanding_store) { if ((request.type == RubyRequestType_LD) || (request.type == RubyRequestType_IFETCH) || @@ -615,6 +619,9 @@ case RubyRequestType_LD: ctype = CacheRequestType_LD; break; + case RubyRequestType_FLUSH: + ctype = CacheRequestType_FLUSH; + break; case RubyRequestType_ST: case RubyRequestType_RMW_Read: case RubyRequestType_RMW_Write: