diff -r ef18d64a1fb4 -r 76831ae2c840 src/arch/x86/isa/decoder/x87.isa
--- a/src/arch/x86/isa/decoder/x87.isa	Thu Mar 17 16:00:40 2011 -0700
+++ b/src/arch/x86/isa/decoder/x87.isa	Thu Mar 17 16:01:01 2011 -0700
@@ -247,7 +247,7 @@
             }
             0x7: decode MODRM_MOD {
                 0x3: Inst::UD2();
-                default: fnstsw();
+                default: Inst::FNSTSW(Mw);
             }
         }
         //0x6: esc6();
@@ -310,7 +310,7 @@
             }
             0x4: decode MODRM_MOD {
                 0x3: decode MODRM_RM {
-                    0x0: fnstsw();
+                    0x0: Inst::FNSTSW(rAw);
                     default: Inst::UD2();
                 }
                 default: fbld();
diff -r ef18d64a1fb4 -r 76831ae2c840 src/arch/x86/isa/insts/x87/control/save_x87_status_word.py
--- a/src/arch/x86/isa/insts/x87/control/save_x87_status_word.py	Thu Mar 17 16:00:40 2011 -0700
+++ b/src/arch/x86/isa/insts/x87/control/save_x87_status_word.py	Thu Mar 17 16:01:01 2011 -0700
@@ -36,6 +36,44 @@
 # Authors: Gabe Black
 
 microcode = '''
-# FSTSW
-# FNSTSW
+
+# FSTSW (pseudo-op, FWAIT followed by FNSTSW)
+
+# x87 status word is 16-bits
+#   15 = busy
+#   14,10,9,8 = condition codes set by results of various instructions
+#   13,12,11  = top of stack pointer
+#   7 = exception flag
+#   6 = stack fault
+#   5 = precision
+#   4 = underflow
+#   3 = overflow
+#   2 = divide by zero
+#   1 = denormalized
+#   0 = invalid
+
+def macroop FNSTSW_R {
+    rdval t1, "InstRegIndex(MISCREG_X87_STATUS)"
+    rdval t2, "InstRegIndex(MISCREG_X87_TOP)"
+    slli t2, t2, 11
+    or t1,t1,t2
+    mov rax, rax, t1, dataSize=2
+};
+
+def macroop FNSTSW_M {
+    rdval t1, "InstRegIndex(MISCREG_X87_STATUS)"
+    rdval t2, "InstRegIndex(MISCREG_X87_TOP)"
+    slli t2, t2, 11
+    or t1,t1,t2
+    st t1, seg, sib, disp, dataSize=2
+};
+
+def macroop FNSTSW_P {
+    rdip t7
+    rdval t1, "InstRegIndex(MISCREG_X87_STATUS)"
+    rdval t2, "InstRegIndex(MISCREG_X87_TOP)"
+    slli t2, t2, 11
+    or t1,t1,t2
+    st t1, seg, riprel, disp, dataSize=2
+};
 '''
diff -r ef18d64a1fb4 -r 76831ae2c840 src/arch/x86/isa/operands.isa
--- a/src/arch/x86/isa/operands.isa	Thu Mar 17 16:00:40 2011 -0700
+++ b/src/arch/x86/isa/operands.isa	Thu Mar 17 16:01:01 2011 -0700
@@ -110,6 +110,7 @@
         # instructions don't map their indexes with an old value.
         'nccFlagBits':   controlReg('MISCREG_RFLAGS', 61),
         'TOP':           controlReg('MISCREG_X87_TOP', 62, ctype='ub'),
+        'FPSTATUS':      controlReg('MISCREG_X87_STATUS', 63, ctype='uw'),
         # The segment base as used by memory instructions.
         'SegBase':       controlReg('MISCREG_SEG_EFF_BASE(segment)', 70),
 
diff -r ef18d64a1fb4 -r 76831ae2c840 src/arch/x86/regs/misc.hh
--- a/src/arch/x86/regs/misc.hh	Thu Mar 17 16:00:40 2011 -0700
+++ b/src/arch/x86/regs/misc.hh	Thu Mar 17 16:01:01 2011 -0700
@@ -355,6 +355,7 @@
         // Floating point control registers
         MISCREG_X87_TOP =
             MISCREG_SEG_ATTR_BASE + NUM_SEGMENTREGS,
+        MISCREG_X87_STATUS,
 
         MISCREG_MXCSR,
         MISCREG_FCW,