diff -r e185667727d7 -r 36b132d15391 src/arch/power/miscregs.hh
--- a/src/arch/power/miscregs.hh	Wed Jul 21 15:19:34 2010 +0100
+++ b/src/arch/power/miscregs.hh	Wed Jul 21 21:14:27 2010 +0100
@@ -44,7 +44,12 @@
 };
 
 BitUnion32(Cr)
-    Bitfield<31,28> cr0;
+    SubBitUnion(cr0, 31, 28)
+        Bitfield<31> lt;
+        Bitfield<30> gt;
+        Bitfield<29> eq;
+        Bitfield<28> so;
+    EndSubBitUnion(cr0)
     Bitfield<27,24> cr1;
 EndBitUnion(Cr)
 
diff -r e185667727d7 -r 36b132d15391 src/arch/power/process.cc
--- a/src/arch/power/process.cc	Wed Jul 21 15:19:34 2010 +0100
+++ b/src/arch/power/process.cc	Wed Jul 21 21:14:27 2010 +0100
@@ -284,5 +284,12 @@
 PowerLiveProcess::setSyscallReturn(ThreadContext *tc,
         SyscallReturn return_value)
 {
+    Cr cr = tc->readIntReg(INTREG_CR);
+    if (return_value.successful()) {
+        cr.cr0.so = 0;
+    } else {
+        cr.cr0.so = 1;
+    }
+    tc->setIntReg(INTREG_CR, cr);
     tc->setIntReg(ReturnValueReg, return_value.value());
 }