diff -r 657342ac5aba -r f85850e14f7c src/mem/slicc/symbols/StateMachine.py
--- a/src/mem/slicc/symbols/StateMachine.py	Thu Mar 31 12:15:52 2011 -0700
+++ b/src/mem/slicc/symbols/StateMachine.py	Thu Mar 31 12:17:02 2011 -0700
@@ -30,6 +30,7 @@
 from slicc.symbols.Symbol import Symbol
 from slicc.symbols.Var import Var
 import slicc.generate.html as html
+import re
 
 python_class_map = {"int": "Int",
                     "std::string": "String",
@@ -474,9 +475,12 @@
         # contecting the sequencer back to the L1 cache controller.
         #
         contains_sequencer = False
+        sequencers = []
         for param in self.config_parameters:
-            if param.name == "sequencer" or param.name == "dma_sequencer":
-                contains_sequencer = True
+            if param.name == "dma_sequencer":
+                contains_dma_sequencer = True
+            elif re.compile("sequencer").search(param.name):
+                sequencers.append(param.name)
             if param.pointer:
                 code('m_${{param.name}}_ptr = p->${{param.name}};')
             else:
@@ -487,19 +491,20 @@
         # includes passing the sequencer a pointer to the controller.
         #
         if self.ident == "L1Cache":
-            if not contains_sequencer:
+            if not sequencers:
                 self.error("The L1Cache controller must include the sequencer " \
                            "configuration parameter")
 
-            code('''
-m_sequencer_ptr->setController(this);
-''')
+            for seq in sequencers:
+                code('''
+m_${{seq}}_ptr->setController(this);
+    ''')
         #
         # For the DMA controller, pass the sequencer a pointer to the
         # controller.
         #
         if self.ident == "DMA":
-            if not contains_sequencer:
+            if not contains_dma_sequencer:
                 self.error("The DMA controller must include the sequencer " \
                            "configuration parameter")