diff -r f57aa75cfa9d -r dbbb31b398b9 src/mem/cache/base.cc --- a/src/mem/cache/base.cc Tue Apr 19 18:53:01 2011 -0700 +++ b/src/mem/cache/base.cc Tue Apr 19 18:56:34 2011 -0700 @@ -145,17 +145,20 @@ { using namespace Stats; + int num_contexts = _numCpus; +#if FULL_SYSTEM + // extra for devices + num_contexts += 1; +#endif + + // Hit statistics for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { MemCmd cmd(access_idx); const string &cstr = cmd.toString(); hits[access_idx] -#if FULL_SYSTEM - .init(_numCpus + 1) -#else - .init(_numCpus) -#endif + .init(num_contexts) .name(name() + "." + cstr + "_hits") .desc("number of " + cstr + " hits") .flags(total | nozero | nonan) @@ -192,11 +195,7 @@ const string &cstr = cmd.toString(); misses[access_idx] -#if FULL_SYSTEM - .init(_numCpus + 1) -#else - .init(_numCpus) -#endif + .init(num_contexts) .name(name() + "." + cstr + "_misses") .desc("number of " + cstr + " misses") .flags(total | nozero | nonan) @@ -223,7 +222,7 @@ const string &cstr = cmd.toString(); missLatency[access_idx] - .init(maxThreadsPerCPU) + .init(num_contexts) .name(name() + "." + cstr + "_miss_latency") .desc("number of " + cstr + " miss cycles") .flags(total | nozero | nonan) @@ -366,7 +365,7 @@ ; writebacks - .init(maxThreadsPerCPU) + .init(num_contexts) .name(name() + ".writebacks") .desc("number of writebacks") .flags(total) @@ -379,7 +378,7 @@ const string &cstr = cmd.toString(); mshr_hits[access_idx] - .init(maxThreadsPerCPU) + .init(num_contexts) .name(name() + "." + cstr + "_mshr_hits") .desc("number of " + cstr + " MSHR hits") .flags(total | nozero | nonan) @@ -406,7 +405,7 @@ const string &cstr = cmd.toString(); mshr_misses[access_idx] - .init(maxThreadsPerCPU) + .init(num_contexts) .name(name() + "." + cstr + "_mshr_misses") .desc("number of " + cstr + " MSHR misses") .flags(total | nozero | nonan) @@ -433,7 +432,7 @@ const string &cstr = cmd.toString(); mshr_miss_latency[access_idx] - .init(maxThreadsPerCPU) + .init(num_contexts) .name(name() + "." + cstr + "_mshr_miss_latency") .desc("number of " + cstr + " MSHR miss cycles") .flags(total | nozero | nonan) @@ -461,7 +460,7 @@ const string &cstr = cmd.toString(); mshr_uncacheable[access_idx] - .init(maxThreadsPerCPU) + .init(num_contexts) .name(name() + "." + cstr + "_mshr_uncacheable") .desc("number of " + cstr + " MSHR uncacheable") .flags(total | nozero | nonan) @@ -482,7 +481,7 @@ const string &cstr = cmd.toString(); mshr_uncacheable_lat[access_idx] - .init(maxThreadsPerCPU) + .init(num_contexts) .name(name() + "." + cstr + "_mshr_uncacheable_latency") .desc("number of " + cstr + " MSHR uncacheable cycles") .flags(total | nozero | nonan) @@ -611,7 +610,7 @@ overallAvgMshrUncacheableLatency = overallMshrUncacheableLatency / overallMshrUncacheable; mshr_cap_events - .init(maxThreadsPerCPU) + .init(num_contexts) .name(name() + ".mshr_cap_events") .desc("number of times MSHR cap was activated") .flags(total) @@ -619,7 +618,7 @@ //software prefetching stats soft_prefetch_mshr_full - .init(maxThreadsPerCPU) + .init(num_contexts) .name(name() + ".soft_prefetch_mshr_full") .desc("number of mshr full events for SW prefetching instrutions") .flags(total)