diff -r 03cfd2ecf6bb -r d7ea4c3e70f6 src/arch/alpha/isa/mem.isa --- a/src/arch/alpha/isa/mem.isa Sun May 29 21:48:58 2011 -0700 +++ b/src/arch/alpha/isa/mem.isa Sun May 29 23:59:24 2011 -0700 @@ -197,7 +197,7 @@ %(ea_code)s; if (fault == NoFault) { - fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags); + fault = xc->read(EA, (%(mem_acc_type)s&)Mem, memAccessFlags); %(memacc_code)s; } @@ -223,7 +223,7 @@ %(ea_code)s; if (fault == NoFault) { - fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags); + fault = xc->read(EA, (%(mem_acc_type)s&)Mem, memAccessFlags); } return fault; @@ -273,7 +273,7 @@ } if (fault == NoFault) { - fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, + fault = xc->write((%(mem_acc_type)s&)Mem, EA, memAccessFlags, NULL); } @@ -307,7 +307,7 @@ } if (fault == NoFault) { - fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, + fault = xc->write((%(mem_acc_type)s&)Mem, EA, memAccessFlags, &write_result); } @@ -340,7 +340,7 @@ } if (fault == NoFault) { - fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, + fault = xc->write((%(mem_acc_type)s&)Mem, EA, memAccessFlags, NULL); } diff -r 03cfd2ecf6bb -r d7ea4c3e70f6 src/arch/arm/isa/insts/ldr.isa --- a/src/arch/arm/isa/insts/ldr.isa Sun May 29 21:48:58 2011 -0700 +++ b/src/arch/arm/isa/insts/ldr.isa Sun May 29 23:59:24 2011 -0700 @@ -194,12 +194,16 @@ # Code that actually handles the access if self.flavor == "dprefetch" or self.flavor == "iprefetch": - accCode = 'uint64_t temp = Mem%s; temp = temp;' + accCode = 'uint64_t temp = %(cast)sMem%(suffix)s; temp = temp;' elif self.flavor == "fp": - accCode = "FpDest.uw = cSwap(Mem%s, ((CPSR)Cpsr).e);\n" + accCode = "FpDest.uw = cSwap(%(cast)sMem%(suffix)s, " + \ + "((CPSR)Cpsr).e);\n" else: - accCode = "IWDest = cSwap(Mem%s, ((CPSR)Cpsr).e);" - accCode = accCode % buildMemSuffix(self.sign, self.size) + accCode = "IWDest = cSwap(%(cast)sMem%(suffix)s, " + \ + "((CPSR)Cpsr).e);" + accCode = accCode % \ + { "suffix" : buildMemSuffix(self.size), + "cast" : buildMemCast(self.sign, self.size) } self.codeBlobs["memacc_code"] = accCode diff -r 03cfd2ecf6bb -r d7ea4c3e70f6 src/arch/arm/isa/insts/mem.isa --- a/src/arch/arm/isa/insts/mem.isa Sun May 29 21:48:58 2011 -0700 +++ b/src/arch/arm/isa/insts/mem.isa Sun May 29 23:59:24 2011 -0700 @@ -175,19 +175,31 @@ return Name - def buildMemSuffix(sign, size): + def buildMemSuffix(size): if size == 4: memSuffix = '' elif size == 2: + memSuffix = '.uh' + elif size == 1: + memSuffix = '.ub' + else: + raise Exception, "Unrecognized size for access %d" % size + + return memSuffix + + def buildMemCast(sign, size): + if size == 4: + return '(uint32_t)' + elif size == 2: if sign: - memSuffix = '.sh' + return '(int16_t)' else: - memSuffix = '.uh' + return '(uint16_t)' elif size == 1: if sign: - memSuffix = '.sb' + return '(int8_t)' else: - memSuffix = '.ub' + return '(uint8_t)' else: raise Exception, "Unrecognized size for access %d" % size diff -r 03cfd2ecf6bb -r d7ea4c3e70f6 src/arch/arm/isa/insts/str.isa --- a/src/arch/arm/isa/insts/str.isa Sun May 29 21:48:58 2011 -0700 +++ b/src/arch/arm/isa/insts/str.isa Sun May 29 23:59:24 2011 -0700 @@ -201,9 +201,10 @@ accCode = 'Mem%(suffix)s = cSwap(FpDest.uw, ((CPSR)Cpsr).e);' else: accCode = \ - 'Mem%(suffix)s = cSwap(Dest%(suffix)s, ((CPSR)Cpsr).e);' + 'Mem%(suffix)s = cSwap(%(cast)sDest, ((CPSR)Cpsr).e);' accCode = accCode % \ - { "suffix" : buildMemSuffix(self.sign, self.size) } + { "suffix" : buildMemSuffix(self.size), + "cast" : buildMemCast(self.sign, self.size) } self.codeBlobs["memacc_code"] = accCode diff -r 03cfd2ecf6bb -r d7ea4c3e70f6 src/arch/arm/isa/templates/mem.isa --- a/src/arch/arm/isa/templates/mem.isa Sun May 29 21:48:58 2011 -0700 +++ b/src/arch/arm/isa/templates/mem.isa Sun May 29 23:59:24 2011 -0700 @@ -87,7 +87,7 @@ %(preacc_code)s; if (fault == NoFault) { - fault = xc->write((uint%(mem_acc_size)d_t&)Mem, + fault = xc->write((%(mem_acc_type)s&)Mem, EA, memAccessFlags, &memData); } @@ -123,7 +123,7 @@ %(preacc_code)s; if (fault == NoFault) { - fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, + fault = xc->write((%(mem_acc_type)s&)Mem, EA, memAccessFlags, &memData); } } else { @@ -174,7 +174,7 @@ if (%(predicate_test)s) { if (fault == NoFault) { - fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags); + fault = xc->read(EA, (%(mem_acc_type)s&)Mem, memAccessFlags); %(memacc_code)s; } @@ -241,7 +241,7 @@ } if (fault == NoFault) { - fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, + fault = xc->write((%(mem_acc_type)s&)Mem, EA, memAccessFlags, NULL); } @@ -314,7 +314,7 @@ uint64_t writeResult; if (fault == NoFault) { - fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, + fault = xc->write((%(mem_acc_type)s&)Mem, EA, memAccessFlags, &writeResult); } @@ -351,7 +351,7 @@ } if (fault == NoFault) { - fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, + fault = xc->write((%(mem_acc_type)s&)Mem, EA, memAccessFlags, NULL); } } else { @@ -380,7 +380,7 @@ } if (fault == NoFault) { - fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, + fault = xc->write((%(mem_acc_type)s&)Mem, EA, memAccessFlags, NULL); } } else { @@ -437,7 +437,7 @@ if (%(predicate_test)s) { if (fault == NoFault) { - fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags); + fault = xc->read(EA, (%(mem_acc_type)s&)Mem, memAccessFlags); } } else { xc->setPredicate(false); diff -r 03cfd2ecf6bb -r d7ea4c3e70f6 src/arch/isa_parser.py --- a/src/arch/isa_parser.py Sun May 29 21:48:58 2011 -0700 +++ b/src/arch/isa_parser.py Sun May 29 23:59:24 2011 -0700 @@ -210,7 +210,6 @@ myDict['op_wb'] = op_wb_str if d.operands.memOperand: - myDict['mem_acc_size'] = d.operands.memOperand.mem_acc_size myDict['mem_acc_type'] = d.operands.memOperand.mem_acc_type elif isinstance(d, dict): @@ -417,29 +416,18 @@ subst_dict = {"name": self.base_name, "func": func, "reg_idx": self.reg_spec, - "size": self.size, "ctype": self.ctype} if hasattr(self, 'src_reg_idx'): subst_dict['op_idx'] = self.src_reg_idx code = self.read_code % subst_dict - if self.size != self.dflt_size: - return '%s = bits(%s, %d, 0);\n' % \ - (self.base_name, code, self.size-1) - else: - return '%s = %s;\n' % \ - (self.base_name, code) + return '%s = %s;\n' % (self.base_name, code) def buildWriteCode(self, func = None): - if (self.size != self.dflt_size and self.is_signed): - final_val = 'sext<%d>(%s)' % (self.size, self.base_name) - else: - final_val = self.base_name subst_dict = {"name": self.base_name, "func": func, "reg_idx": self.reg_spec, - "size": self.size, "ctype": self.ctype, - "final_val": final_val} + "final_val": self.base_name} if hasattr(self, 'dest_reg_idx'): subst_dict['op_idx'] = self.dest_reg_idx code = self.write_code % subst_dict @@ -448,7 +436,7 @@ %s final_val = %s; %s; if (traceData) { traceData->setData(final_val); } - }''' % (self.dflt_ctype, final_val, code) + }''' % (self.dflt_ctype, self.base_name, code) def __init__(self, parser, full_name, ext, is_src, is_dest): self.full_name = full_name @@ -463,17 +451,12 @@ self.eff_ext = self.dflt_ext if hasattr(self, 'eff_ext'): - self.size, self.ctype, self.is_signed = \ - parser.operandTypeMap[self.eff_ext] + self.ctype = parser.operandTypeMap[self.eff_ext] - # note that mem_acc_size is undefined for non-mem operands... + # note that mem_acc_type is undefined for non-mem operands... # template must be careful not to use it if it doesn't apply. if self.isMem(): - self.mem_acc_size = self.makeAccSize() - if self.ctype in ['Twin32_t', 'Twin64_t']: - self.mem_acc_type = 'Twin' - else: - self.mem_acc_type = 'uint' + self.mem_acc_type = self.ctype # Finalize additional fields (primarily code fields). This step # is done separately since some of these fields may depend on the @@ -556,34 +539,20 @@ error('Attempt to read integer register as FP') if self.read_code != None: return self.buildReadCode('readIntRegOperand') - if (self.size == self.dflt_size): - return '%s = xc->readIntRegOperand(this, %d);\n' % \ - (self.base_name, self.src_reg_idx) - elif (self.size > self.dflt_size): - int_reg_val = 'xc->readIntRegOperand(this, %d)' % \ - (self.src_reg_idx) - if (self.is_signed): - int_reg_val = 'sext<%d>(%s)' % (self.dflt_size, int_reg_val) - return '%s = %s;\n' % (self.base_name, int_reg_val) - else: - return '%s = bits(xc->readIntRegOperand(this, %d), %d, 0);\n' % \ - (self.base_name, self.src_reg_idx, self.size-1) + int_reg_val = 'xc->readIntRegOperand(this, %d)' % self.src_reg_idx + return '%s = %s;\n' % (self.base_name, int_reg_val) def makeWrite(self): if (self.ctype == 'float' or self.ctype == 'double'): error('Attempt to write integer register as FP') if self.write_code != None: return self.buildWriteCode('setIntRegOperand') - if (self.size != self.dflt_size and self.is_signed): - final_val = 'sext<%d>(%s)' % (self.size, self.base_name) - else: - final_val = self.base_name wb = ''' { %s final_val = %s; xc->setIntRegOperand(this, %d, final_val);\n if (traceData) { traceData->setData(final_val); } - }''' % (self.dflt_ctype, final_val, self.dest_reg_idx) + }''' % (self.ctype, self.base_name, self.dest_reg_idx) return wb class FloatRegOperand(Operand): @@ -609,29 +578,16 @@ func = 'readFloatRegOperand' else: func = 'readFloatRegOperandBits' - if (self.size != self.dflt_size): - bit_select = 1 - base = 'xc->%s(this, %d)' % (func, self.src_reg_idx) if self.read_code != None: return self.buildReadCode(func) - if bit_select: - return '%s = bits(%s, %d, 0);\n' % \ - (self.base_name, base, self.size-1) - else: - return '%s = %s;\n' % (self.base_name, base) + return '%s = xc->%s(this, %d);\n' % \ + (self.base_name, func, self.src_reg_idx) def makeWrite(self): - final_val = self.base_name - final_ctype = self.ctype if (self.ctype == 'float' or self.ctype == 'double'): func = 'setFloatRegOperand' - elif (self.ctype == 'uint32_t' or self.ctype == 'uint64_t'): - func = 'setFloatRegOperandBits' else: func = 'setFloatRegOperandBits' - final_ctype = 'uint%d_t' % self.dflt_size - if (self.size != self.dflt_size and self.is_signed): - final_val = 'sext<%d>(%s)' % (self.size, self.base_name) if self.write_code != None: return self.buildWriteCode(func) wb = ''' @@ -639,7 +595,7 @@ %s final_val = %s; xc->%s(this, %d, final_val);\n if (traceData) { traceData->setData(final_val); } - }''' % (final_ctype, final_val, func, self.dest_reg_idx) + }''' % (self.ctype, self.base_name, func, self.dest_reg_idx) return wb class ControlRegOperand(Operand): @@ -665,12 +621,8 @@ error('Attempt to read control register as FP') if self.read_code != None: return self.buildReadCode('readMiscRegOperand') - base = 'xc->readMiscRegOperand(this, %s)' % self.src_reg_idx - if self.size == self.dflt_size: - return '%s = %s;\n' % (self.base_name, base) - else: - return '%s = bits(%s, %d, 0);\n' % \ - (self.base_name, base, self.size-1) + return '%s = xc->readMiscRegOperand(this, %s);\n' % \ + (self.base_name, self.src_reg_idx) def makeWrite(self): if (self.ctype == 'float' or self.ctype == 'double'): @@ -694,9 +646,6 @@ # Note that initializations in the declarations are solely # to avoid 'uninitialized variable' errors from the compiler. # Declare memory data variable. - if self.ctype in ['Twin32_t','Twin64_t']: - return "%s %s; %s.a = 0; %s.b = 0;\n" % \ - (self.ctype, self.base_name, self.base_name, self.base_name) return '%s %s = 0;\n' % (self.ctype, self.base_name) def makeRead(self): @@ -709,11 +658,6 @@ return self.buildWriteCode() return '' - # Return the memory access size *in bits*, suitable for - # forming a type via "uint%d_t". Divide by 8 if you want bytes. - def makeAccSize(self): - return self.size - class PCStateOperand(Operand): def makeConstructor(self): return '' @@ -1851,26 +1795,21 @@ for (ext, (desc, size)) in user_dict.iteritems(): if desc == 'signed int': ctype = 'int%d_t' % size - is_signed = 1 elif desc == 'unsigned int': ctype = 'uint%d_t' % size - is_signed = 0 elif desc == 'float': - is_signed = 1 # shouldn't really matter if size == 32: ctype = 'float' elif size == 64: ctype = 'double' elif desc == 'twin64 int': - is_signed = 0 ctype = 'Twin64_t' elif desc == 'twin32 int': - is_signed = 0 ctype = 'Twin32_t' if ctype == '': error(parser, lineno, 'Unrecognized type description "%s" in user_dict') - operand_type[ext] = (size, ctype, is_signed) + operand_type[ext] = ctype self.operandTypeMap = operand_type @@ -1916,10 +1855,8 @@ attrList = ['reg_spec', 'flags', 'sort_pri', 'read_code', 'write_code'] if dflt_ext: - (dflt_size, dflt_ctype, dflt_is_signed) = \ - self.operandTypeMap[dflt_ext] - attrList.extend(['dflt_size', 'dflt_ctype', - 'dflt_is_signed', 'dflt_ext']) + dflt_ctype = self.operandTypeMap[dflt_ext] + attrList.extend(['dflt_ctype', 'dflt_ext']) for attr in attrList: tmp_dict[attr] = eval(attr) tmp_dict['base_name'] = op_name diff -r 03cfd2ecf6bb -r d7ea4c3e70f6 src/arch/mips/isa/decoder.isa --- a/src/arch/mips/isa/decoder.isa Sun May 29 21:48:58 2011 -0700 +++ b/src/arch/mips/isa/decoder.isa Sun May 29 23:59:24 2011 -0700 @@ -1662,8 +1662,8 @@ 0x2: decode OP_HI { 0x0: decode OP_LO { format LoadIndexedMemory { - 0x0: lwx({{ Rd.sw = Mem.sw; }}); - 0x4: lhx({{ Rd.sw = Mem.sh; }}); + 0x0: lwx({{ Rd.sw = (int32_t)Mem.uw; }}); + 0x4: lhx({{ Rd.sw = (int16_t)Mem.uh; }}); 0x6: lbux({{ Rd.uw = Mem.ub; }}); } } @@ -2483,9 +2483,9 @@ 0x4: decode OPCODE_LO { format LoadMemory { - 0x0: lb({{ Rt.sw = Mem.sb; }}); - 0x1: lh({{ Rt.sw = Mem.sh; }}); - 0x3: lw({{ Rt.sw = Mem.sw; }}); + 0x0: lb({{ Rt.sw = (int8_t)Mem.ub; }}); + 0x1: lh({{ Rt.sw = (int16_t)Mem.uh; }}); + 0x3: lw({{ Rt.sw = (int32_t)Mem.uw; }}); 0x4: lbu({{ Rt.uw = Mem.ub;}}); 0x5: lhu({{ Rt.uw = Mem.uh; }}); } diff -r 03cfd2ecf6bb -r d7ea4c3e70f6 src/arch/mips/isa/formats/mem.isa --- a/src/arch/mips/isa/formats/mem.isa Sun May 29 21:48:58 2011 -0700 +++ b/src/arch/mips/isa/formats/mem.isa Sun May 29 23:59:24 2011 -0700 @@ -216,7 +216,7 @@ %(ea_code)s; if (fault == NoFault) { - fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags); + fault = xc->read(EA, (%(mem_acc_type)s&)Mem, memAccessFlags); %(memacc_code)s; } @@ -248,7 +248,7 @@ %(ea_code)s; if (fault == NoFault) { - fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags); + fault = xc->read(EA, (%(mem_acc_type)s&)Mem, memAccessFlags); } return fault; @@ -303,7 +303,7 @@ } if (fault == NoFault) { - fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, + fault = xc->write((%(mem_acc_type)s&)Mem, EA, memAccessFlags, NULL); } @@ -339,7 +339,7 @@ } if (fault == NoFault) { - fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, + fault = xc->write((%(mem_acc_type)s&)Mem, EA, memAccessFlags, NULL); } @@ -373,7 +373,7 @@ } if (fault == NoFault) { - fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, + fault = xc->write((%(mem_acc_type)s&)Mem, EA, memAccessFlags, &write_result); } @@ -406,7 +406,7 @@ } if (fault == NoFault) { - fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, + fault = xc->write((%(mem_acc_type)s&)Mem, EA, memAccessFlags, NULL); } diff -r 03cfd2ecf6bb -r d7ea4c3e70f6 src/arch/power/isa/decoder.isa --- a/src/arch/power/isa/decoder.isa Sun May 29 21:48:58 2011 -0700 +++ b/src/arch/power/isa/decoder.isa Sun May 29 23:59:24 2011 -0700 @@ -284,10 +284,11 @@ format LoadIndexOp { 87: lbzx({{ Rt = Mem.ub; }}); 279: lhzx({{ Rt = Mem.uh; }}); - 343: lhax({{ Rt = Mem.sh; }}); + 343: lhax({{ Rt = (int16_t)Mem.uh; }}); 23: lwzx({{ Rt = Mem; }}); - 341: lwax({{ Rt = Mem.sw; }}); - 20: lwarx({{ Rt = Mem.sw; Rsv = 1; RsvLen = 4; RsvAddr = EA; }}); + 341: lwax({{ Rt = (int32_t)Mem.uw; }}); + 20: lwarx({{ Rt = (int32_t)Mem.uw; + Rsv = 1; RsvLen = 4; RsvAddr = EA; }}); 535: lfsx({{ Ft.sf = Mem.sf; }}); 599: lfdx({{ Ft = Mem.df; }}); 855: lfiwax({{ Ft.uw = Mem; }}); @@ -296,9 +297,9 @@ format LoadIndexUpdateOp { 119: lbzux({{ Rt = Mem.ub; }}); 311: lhzux({{ Rt = Mem.uh; }}); - 375: lhaux({{ Rt = Mem.sh; }}); + 375: lhaux({{ Rt = (int16_t)Mem.uh; }}); 55: lwzux({{ Rt = Mem; }}); - 373: lwaux({{ Rt = Mem.sw; }}); + 373: lwaux({{ Rt = (int32_t)Mem.uw; }}); 567: lfsux({{ Ft.sf = Mem.sf; }}); 631: lfdux({{ Ft = Mem.df; }}); } @@ -478,9 +479,9 @@ format LoadDispOp { 34: lbz({{ Rt = Mem.ub; }}); 40: lhz({{ Rt = Mem.uh; }}); - 42: lha({{ Rt = Mem.sh; }}); + 42: lha({{ Rt = (int16_t)Mem.uh; }}); 32: lwz({{ Rt = Mem; }}); - 58: lwa({{ Rt = Mem.sw; }}, + 58: lwa({{ Rt = (int32_t)Mem.uw; }}, {{ EA = Ra + (disp & 0xfffffffc); }}, {{ EA = disp & 0xfffffffc; }}); 48: lfs({{ Ft.sf = Mem.sf; }}); @@ -490,7 +491,7 @@ format LoadDispUpdateOp { 35: lbzu({{ Rt = Mem.ub; }}); 41: lhzu({{ Rt = Mem.uh; }}); - 43: lhau({{ Rt = Mem.sh; }}); + 43: lhau({{ Rt = (int16_t)Mem.uh; }}); 33: lwzu({{ Rt = Mem; }}); 49: lfsu({{ Ft.sf = Mem.sf; }}); 51: lfdu({{ Ft = Mem.df; }}); diff -r 03cfd2ecf6bb -r d7ea4c3e70f6 src/arch/power/isa/formats/mem.isa --- a/src/arch/power/isa/formats/mem.isa Sun May 29 21:48:58 2011 -0700 +++ b/src/arch/power/isa/formats/mem.isa Sun May 29 23:59:24 2011 -0700 @@ -84,7 +84,7 @@ %(ea_code)s; if (fault == NoFault) { - fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags); + fault = xc->read(EA, (%(mem_acc_type)s&)Mem, memAccessFlags); %(memacc_code)s; } @@ -109,7 +109,7 @@ %(ea_code)s; if (fault == NoFault) { - fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags); + fault = xc->read(EA, (%(mem_acc_type)s&)Mem, memAccessFlags); xc->setEA(EA); } @@ -125,15 +125,15 @@ { Addr EA; Fault fault = NoFault; - uint%(mem_acc_size)d_t val; + %(mem_acc_type)s val; %(op_decl)s; %(op_rd)s; EA = xc->getEA(); - val = pkt->get(); - *((uint%(mem_acc_size)d_t*)&Mem) = val; + val = pkt->get<%(mem_acc_type)s>(); + *((%(mem_acc_type)s*)&Mem) = val; if (fault == NoFault) { %(memacc_code)s; @@ -164,7 +164,7 @@ } if (fault == NoFault) { - fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, + fault = xc->write((%(mem_acc_type)s&)Mem, EA, memAccessFlags, NULL); } @@ -193,7 +193,7 @@ } if (fault == NoFault) { - fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, + fault = xc->write((%(mem_acc_type)s&)Mem, EA, memAccessFlags, NULL); } diff -r 03cfd2ecf6bb -r d7ea4c3e70f6 src/arch/sparc/isa/decoder.isa --- a/src/arch/sparc/isa/decoder.isa Sun May 29 21:48:58 2011 -0700 +++ b/src/arch/sparc/isa/decoder.isa Sun May 29 23:59:24 2011 -0700 @@ -1125,10 +1125,10 @@ }}); } format Load { - 0x08: ldsw({{Rd = (int32_t)Mem.sw;}}); - 0x09: ldsb({{Rd = (int8_t)Mem.sb;}}); - 0x0A: ldsh({{Rd = (int16_t)Mem.shw;}}); - 0x0B: ldx({{Rd = (int64_t)Mem.sdw;}}); + 0x08: ldsw({{Rd = (int32_t)Mem.uw;}}); + 0x09: ldsb({{Rd = (int8_t)Mem.ub;}}); + 0x0A: ldsh({{Rd = (int16_t)Mem.uhw;}}); + 0x0B: ldx({{Rd = (int64_t)Mem.udw;}}); } 0x0D: Swap::ldstub({{Mem.ub = 0xFF;}}, {{ @@ -1223,10 +1223,10 @@ }}); } format LoadAlt { - 0x18: ldswa({{Rd = (int32_t)Mem.sw;}}); - 0x19: ldsba({{Rd = (int8_t)Mem.sb;}}); - 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}}); - 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}}); + 0x18: ldswa({{Rd = (int32_t)Mem.uw;}}); + 0x19: ldsba({{Rd = (int8_t)Mem.ub;}}); + 0x1A: ldsha({{Rd = (int16_t)Mem.uhw;}}); + 0x1B: ldxa({{Rd = (int64_t)Mem.udw;}}); } 0x1D: SwapAlt::ldstuba({{Mem.ub = 0xFF;}}, {{ diff -r 03cfd2ecf6bb -r d7ea4c3e70f6 src/arch/sparc/isa/formats/mem/swap.isa --- a/src/arch/sparc/isa/formats/mem/swap.isa Sun May 29 21:48:58 2011 -0700 +++ b/src/arch/sparc/isa/formats/mem/swap.isa Sun May 29 23:59:24 2011 -0700 @@ -50,7 +50,7 @@ } if (storeCond && fault == NoFault) { %(EA_trunc)s - fault = xc->write((uint%(mem_acc_size)s_t)Mem, + fault = xc->write((%(mem_acc_type)s)Mem, EA, %(asi_val)s, &mem_data); } if (fault == NoFault) { @@ -87,7 +87,7 @@ } if (fault == NoFault) { %(EA_trunc)s - fault = xc->write((uint%(mem_acc_size)s_t)Mem, + fault = xc->write((%(mem_acc_type)s)Mem, EA, %(asi_val)s, &mem_data); } return fault; @@ -103,7 +103,7 @@ Fault fault = NoFault; %(op_decl)s; - uint64_t mem_data = pkt->get(); + uint64_t mem_data = pkt->get<%(mem_acc_type)s>(); if (fault == NoFault) { // Handle the swapping diff -r 03cfd2ecf6bb -r d7ea4c3e70f6 src/arch/sparc/isa/formats/mem/util.isa --- a/src/arch/sparc/isa/formats/mem/util.isa Sun May 29 21:48:58 2011 -0700 +++ b/src/arch/sparc/isa/formats/mem/util.isa Sun May 29 23:59:24 2011 -0700 @@ -143,7 +143,7 @@ %(fault_check)s; if (fault == NoFault) { %(EA_trunc)s - fault = xc->read(EA, (%(mem_acc_type)s%(mem_acc_size)s_t&)Mem, %(asi_val)s); + fault = xc->read(EA, (%(mem_acc_type)s&)Mem, %(asi_val)s); } if (fault == NoFault) { %(code)s; @@ -171,7 +171,7 @@ %(fault_check)s; if (fault == NoFault) { %(EA_trunc)s - fault = xc->read(EA, (%(mem_acc_type)s%(mem_acc_size)s_t&)Mem, %(asi_val)s); + fault = xc->read(EA, (%(mem_acc_type)s&)Mem, %(asi_val)s); } return fault; } @@ -214,7 +214,7 @@ } if (storeCond && fault == NoFault) { %(EA_trunc)s - fault = xc->write((%(mem_acc_type)s%(mem_acc_size)s_t)Mem, + fault = xc->write((%(mem_acc_type)s)Mem, EA, %(asi_val)s, 0); } if (fault == NoFault) { @@ -245,7 +245,7 @@ } if (storeCond && fault == NoFault) { %(EA_trunc)s - fault = xc->write((%(mem_acc_type)s%(mem_acc_size)s_t)Mem, + fault = xc->write((%(mem_acc_type)s)Mem, EA, %(asi_val)s, 0); } return fault;